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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 21:53:27 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 22:10:43 -0700 |
| commit | 54f3237720709f7c59f4e440ebfdbc61a63c926a (patch) | |
| tree | a50b697cb68722fa35b6703c234f7c9874e2e10f | |
| parent | 8e56cfb6bbaa4e61b201c123b04a4eb4ca3403cf (diff) | |
| download | yosys-54f3237720709f7c59f4e440ebfdbc61a63c926a.tar.gz yosys-54f3237720709f7c59f4e440ebfdbc61a63c926a.tar.bz2 yosys-54f3237720709f7c59f4e440ebfdbc61a63c926a.zip | |
Fix gcc warning of potentially uninitialised
| -rw-r--r-- | passes/techmap/abc9.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index d48877779..e9f35be91 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -523,7 +523,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri for (auto c : mapped_mod->cells()) { if (c->type == "$_NOT_") { - RTLIL::Cell *cell; + RTLIL::Cell *cell = nullptr; RTLIL::SigBit a_bit = c->getPort("\\A").as_bit(); RTLIL::SigBit y_bit = c->getPort("\\Y").as_bit(); if (!a_bit.wire) { @@ -577,7 +577,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri cell->setPort("\\Y", RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset)); cell_stats[RTLIL::unescape_id(c->type)]++; } - if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; + if (cell && markgroups) cell->attributes["\\abcgroup"] = map_autoidx; continue; } cell_stats[RTLIL::unescape_id(c->type)]++; |