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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 16:45:09 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 17:38:16 -0700 |
| commit | f11c9a419b99563b462356add5446d9fc2dbe2eb (patch) | |
| tree | ffbeeefa25dd2cef30f406082df8b26ad0c372d4 | |
| parent | 4e5836a5fb009751a6f3bd7ec3eba20e223861f1 (diff) | |
| download | yosys-f11c9a419b99563b462356add5446d9fc2dbe2eb.tar.gz yosys-f11c9a419b99563b462356add5446d9fc2dbe2eb.tar.bz2 yosys-f11c9a419b99563b462356add5446d9fc2dbe2eb.zip | |
Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 45bc47f24..86b49b13c 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -281,6 +281,7 @@ struct SynthXilinxPass : public ScriptPass } if (check_label("map_luts")) { + run("opt_expr -mux_undef"); if (abc == "abc9") run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + XC7_WIRE_DELAY + string(retime ? " -dff" : "")); else if (help_mode) |