| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix running sva tests | Miodrag Milanovic | 2022-05-09 | 1 | -4/+3 |
| * | Bump version | github-actions[bot] | 2022-05-08 | 1 | -1/+1 |
| * | opt_mem: Remove constant-value bit lanes. | Marcelina Kościelnicka | 2022-05-07 | 3 | -28/+145 |
| * | Bump version | github-actions[bot] | 2022-05-07 | 1 | -1/+1 |
| * | include latest abc changes | Miodrag Milanovic | 2022-05-06 | 1 | -1/+1 |
| * | include latest abc changes | Miodrag Milanovic | 2022-05-06 | 1 | -1/+1 |
| * | Merge pull request #3300 from imhcyx/master | Miodrag Milanović | 2022-05-06 | 1 | -1/+1 |
| |\ | |||||
| | * | memory_share: fix wrong argidx in extra_args | imhcyx | 2022-05-05 | 1 | -1/+1 |
| * | | Include abc change to fix FreeBSD build | Miodrag Milanovic | 2022-05-06 | 1 | -1/+1 |
| |/ | |||||
| * | Bump version | github-actions[bot] | 2022-05-05 | 1 | -1/+1 |
| * | abc: Use dict/pool instead of std::map/std::set | Marcelina Kościelnicka | 2022-05-04 | 1 | -14/+14 |
| * | Bump version | github-actions[bot] | 2022-05-03 | 1 | -1/+1 |
| * | AIM file could have gaps in or between inputs and inits | Miodrag Milanovic | 2022-05-02 | 1 | -3/+6 |
| * | Bump version | github-actions[bot] | 2022-04-30 | 1 | -1/+1 |
| * | Merge pull request #3294 from YosysHQ/micko/verific_merge_past_ff | Miodrag Milanović | 2022-04-29 | 1 | -0/+1 |
| |\ | |||||
| | * | Ignore merging past ffs that we are not properly merging | Miodrag Milanovic | 2022-04-29 | 1 | -0/+1 |
| |/ | |||||
| * | Bump version | github-actions[bot] | 2022-04-26 | 1 | -1/+1 |
| * | Add missing parameters for ecp5 | Rick Luiken | 2022-04-25 | 2 | -1/+2 |
| * | Merge pull request #3287 from jix/smt2-conditional-store | Jannis Harder | 2022-04-25 | 1 | -2/+4 |
| |\ | |||||
| | * | smt2: Make write port array stores conditional on nonzero write mask | Jannis Harder | 2022-04-20 | 1 | -2/+4 |
| * | | Merge pull request #3257 from jix/tribuf-formal | Jannis Harder | 2022-04-25 | 1 | -3/+46 |
| |\ \ | |||||
| | * | | tribuf: `-formal` option: convert all to logic and detect conflicts | Jannis Harder | 2022-04-12 | 1 | -3/+46 |
| * | | | Merge pull request #3290 from mpasternacki/bugfix/freebsd-build | Miodrag Milanović | 2022-04-25 | 1 | -0/+3 |
| |\ \ \ | |||||
| | * | | | Fix build on FreeBSD, which has no alloca.h | Maciej Pasternacki | 2022-04-24 | 1 | -0/+3 |
| | | |/ | |/| | |||||
| * | | | Merge pull request #3289 from YosysHQ/micko/sim_improve | Miodrag Milanović | 2022-04-25 | 2 | -29/+74 |
| |\ \ \ | |/ / |/| | | |||||
| | * | | Match $anyseq input if connected to public wire | Miodrag Milanovic | 2022-04-22 | 1 | -6/+12 |
| | * | | Treat $anyseq as input from FST | Miodrag Milanovic | 2022-04-22 | 1 | -0/+21 |
| | * | | Ignore change on last edge | Miodrag Milanovic | 2022-04-22 | 1 | -4/+5 |
| | * | | Last sample from input does not represent change | Miodrag Milanovic | 2022-04-22 | 1 | -1/+2 |
| | * | | latches are always set to zero | Miodrag Milanovic | 2022-04-22 | 1 | -6/+1 |
| | * | | If not multiclock, output only on clock edges | Miodrag Milanovic | 2022-04-22 | 1 | -0/+18 |
| | * | | Set init state for all wires from FST and set past | Miodrag Milanovic | 2022-04-22 | 1 | -13/+12 |
| | * | | Fix multiclock for btor2 witness | Miodrag Milanovic | 2022-04-22 | 1 | -5/+9 |
| |/ / | |||||
| * | | Bump version | github-actions[bot] | 2022-04-19 | 1 | -1/+1 |
| * | | Merge pull request #3280 from YosysHQ/micko/fix_readaiw | Miodrag Milanović | 2022-04-18 | 2 | -3/+3 |
| |\ \ | |||||
| | * | | Update abc | Miodrag Milanovic | 2022-04-18 | 1 | -1/+1 |
| | * | | Fix reading aiw from other solvers | Miodrag Milanovic | 2022-04-15 | 1 | -2/+2 |
| | |/ | |||||
| * | | verific: allow memories to be inferred in loops (vhdl) | Miodrag Milanovic | 2022-04-18 | 1 | -0/+1 |
| * | | Merge pull request #3282 from nakengelhardt/verific_loop_rams | Miodrag Milanović | 2022-04-18 | 1 | -0/+1 |
| |\ \ | |||||
| | * | | verific: allow memories to be inferred in loops | N. Engelhardt | 2022-04-15 | 1 | -0/+1 |
| | |/ | |||||
| * | | Bump version | github-actions[bot] | 2022-04-16 | 1 | -1/+1 |
| * | | memory_share: Fix up mismatched address widths. | Marcelina Kościelnicka | 2022-04-15 | 1 | -0/+14 |
| * | | opt_dff: Fix behavior on $ff with D == Q. | Marcelina Kościelnicka | 2022-04-15 | 1 | -1/+1 |
| |/ | |||||
| * | Bump version | github-actions[bot] | 2022-04-09 | 1 | -1/+1 |
| * | Merge pull request #3275 from YosysHQ/micko/clk2fflogic_fix | Miodrag Milanović | 2022-04-08 | 1 | -9/+11 |
| |\ | |||||
| | * | Use wrap_async_control_gate if ff is fine | Miodrag Milanovic | 2022-04-08 | 1 | -9/+11 |
| |/ | |||||
| * | Merge pull request #3273 from modwizcode/fix-build | Miodrag Milanović | 2022-04-08 | 2 | -1/+12 |
| |\ | |||||
| | * | Makefile: properly conditionalize features requiring compression. | Iris Johnson | 2022-04-07 | 2 | -1/+12 |
| * | | pass jny: flipped the defaults for the inclusion of various bits of metadata | Aki Van Ness | 2022-04-08 | 1 | -30/+30 |
| * | | pass jny: ensured the cell collection is cleared between modules | Aki Van Ness | 2022-04-08 | 1 | -0/+1 |
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |