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* Resolve @cliffordwolf comment on sigmapEddie Hung2019-06-071-2/+2
* Another muxpack testEddie Hung2019-06-072-0/+32
* Fix and test for balanced caseEddie Hung2019-06-063-10/+55
* Fix warningsEddie Hung2019-06-062-3/+3
* Support cascading $pmux.A with $mux.A and $mux.BEddie Hung2019-06-063-17/+65
* More cleanupEddie Hung2019-06-061-15/+20
* Fix spacingEddie Hung2019-06-061-6/+5
* Non chain user check using next_sigEddie Hung2019-06-061-7/+5
* Add non exclusive testEddie Hung2019-06-062-0/+56
* Move muxpack from passes/techmap to passes/optEddie Hung2019-06-063-1/+1
* Update docEddie Hung2019-06-061-4/+5
* Add to CHANGELOGEddie Hung2019-06-061-0/+1
* One more and tidy upEddie Hung2019-06-062-6/+28
* Add a few more special case testsEddie Hung2019-06-062-0/+51
* Add tests, fix for !=Eddie Hung2019-06-063-9/+110
* Missing fileEddie Hung2019-06-061-0/+232
* Initial adaptation of muxpack from shregmapEddie Hung2019-06-061-0/+1
* Merge pull request #1060 from antmicro/parsing_attr_on_port_connClifford Wolf2019-06-0614-10/+279
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| * Fixed memory leak.Maciej Kurc2019-06-051-0/+4
| * Moved tests that fail with Icarus Verilog to /tests/various. Those tests are ...Maciej Kurc2019-06-044-0/+46
| * Added tests for attributesMaciej Kurc2019-06-039-0/+219
| * Added support for parsing attributes on port connections.Maciej Kurc2019-05-311-10/+10
* | Merge pull request #1073 from whitequark/ecp5-diamond-iobDavid Shah2019-06-061-0/+15
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| * | ECP5: implement all Diamond I/O buffer primitives.whitequark2019-06-061-0/+15
* | | Merge pull request #1071 from YosysHQ/eddie/fix_1070Clifford Wolf2019-06-061-2/+2
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| * | | Fix typo in opt_rmdffEddie Hung2019-06-051-2/+2
* | | | Merge pull request #1072 from YosysHQ/eddie/fix_1069Clifford Wolf2019-06-061-0/+5
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| * | | | Error out if no top module given before 'sim'Eddie Hung2019-06-051-0/+5
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* / / / Missing doc for -tech xilinx in shregmapEddie Hung2019-06-051-0/+3
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* | | Merge pull request #1067 from YosysHQ/clifford/fix1065Eddie Hung2019-06-051-1/+1
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| * | | Suppress driver-driver conflict warning for unknown cell types, fixes #1065Clifford Wolf2019-06-051-1/+1
* | | | Merge pull request #1066 from YosysHQ/clifford/fix1056Clifford Wolf2019-06-051-1/+0
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| * | | | Remove yosys_banner() from python wrapper init, fixes #1056Clifford Wolf2019-06-051-1/+0
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* | | | Major rewrite of wire selection in setundef -initClifford Wolf2019-06-051-30/+89
* | | | Indent fixClifford Wolf2019-06-051-23/+25
* | | | Merge pull request #999 from jakobwenzel/setundefInitFixClifford Wolf2019-06-051-16/+23
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| * | | | initialize more registers in setundef -initJakob Wenzel2019-05-091-16/+23
* | | | | Fix typo in fmcombine log message, fixes #1063Clifford Wolf2019-06-051-2/+2
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* | | | Merge pull request #1062 from tux3/patch-1Clifford Wolf2019-06-041-1/+1
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| * | | | README.md: Missing formatting for <tag>Tux32019-06-041-1/+1
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* | | | Merge pull request #1061 from YosysHQ/eddie/techmap_and_arith_mapEddie Hung2019-06-031-6/+5
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| * | | | Remove extra newlineEddie Hung2019-06-031-1/+0
| * | | | Execute techmap and arith_map simultaneouslyEddie Hung2019-06-031-6/+6
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* | | / Only support Symbiotic EDA flavored VerificClifford Wolf2019-06-021-0/+8
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* | | Fix "tee" handling of log_streamsClifford Wolf2019-05-311-0/+5
* | | Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, ...Clifford Wolf2019-05-301-0/+3
* | | Merge pull request #1057 from mmicko/fix_478Clifford Wolf2019-05-301-0/+4
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| * | | Aded one more load of .conf to support change of prefixMiodrag Milanovic2019-05-291-0/+4
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* | | Merge pull request #1049 from YosysHQ/clifford/fix1047Clifford Wolf2019-05-282-4/+15
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| * | | Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047Clifford Wolf2019-05-282-4/+15
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