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* xilinx: Add simulation model for IBUFG.Marcin Kościelnicki2019-10-105-33/+14
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* Revert "Add test that is expecting to fail"Eddie Hung2019-10-081-20/+0
| | | | This reverts commit c28d4b804720c2cf0086e921748219150e9631b5.
* Revert "Be mindful that sigmap(wire) could have dupes when checking \init"Eddie Hung2019-10-081-4/+1
| | | | This reverts commit f46ac1df9f8847dac9d9851f2f948d93a1064ff1.
* Merge pull request #1432 from YosysHQ/eddie/fix1427Eddie Hung2019-10-084-50/+145
|\ | | | | Refactor peepopt_dffmux and be sensitive to \init when trimming
| * Use `sat -tempinduct` and comments for why equiv_opt not sufficientEddie Hung2019-10-031-1/+8
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| * Fix broken CI, check reset even for constants, trim rstmuxEddie Hung2019-10-022-25/+28
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| * Fix testEddie Hung2019-10-021-2/+12
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| * Merge branch 'eddie/fix_sat_init' into eddie/fix1427Eddie Hung2019-10-022-1/+24
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| | * Be mindful that sigmap(wire) could have dupes when checking \initEddie Hung2019-10-021-1/+4
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| | * Add test that is expecting to failEddie Hung2019-10-021-0/+20
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| * | Update testEddie Hung2019-10-021-13/+3
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| * | Refactor peepopt_dffmux and be sensitive to \init when trimmingEddie Hung2019-10-021-32/+63
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| * | Add testEddie Hung2019-10-021-0/+31
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* | | Merge pull request #1433 from YosysHQ/eddie/equiv_opt_async2syncEddie Hung2019-10-083-13/+19
|\ \ \ | | | | | | | | async2sync to be called by equiv_opt only when -async2sync given
| * | | Add -async2sync to help text as per @daveshah1Eddie Hung2019-10-041-1/+4
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| * | | Restore part of docEddie Hung2019-10-031-1/+2
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| * | | Disable equiv check for ice40 latchesEddie Hung2019-10-031-6/+3
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| * | | Add new -async2sync optionEddie Hung2019-10-031-1/+11
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| * | | Use equiv_opt -async2sync for xilinxEddie Hung2019-10-031-3/+1
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| * | | Revert "equiv_opt to call async2sync when not -multiclock like SymbiYosys"Eddie Hung2019-10-031-2/+0
| | | | | | | | | | | | | | | | This reverts commit a39505e329cc05dbd4ad624a1cf0f6caf664fd9a.
| * | | Revert "Update doc for equiv_opt"Eddie Hung2019-10-031-3/+2
| |/ / | | | | | | | | | This reverts commit a274b7cc86d4f64541d3d2903b4eeed4616ab1d8.
* | | Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9Eddie Hung2019-10-0834-309/+316
|\ \ \ | | | | | | | | Rename abc_* names/attributes to more precisely be abc9_*
| * \ \ Merge branch 'master' into eddie/abc_to_abc9Eddie Hung2019-10-048-185/+33
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| * | | | Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-0434-305/+313
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* | | | | Merge pull request #1438 from YosysHQ/eddie/xilinx_dsp_commentsEddie Hung2019-10-085-72/+364
|\ \ \ \ \ | | | | | | | | | | | | Add notes and comments for xilinx_dsp
| * | | | | Missed thisEddie Hung2019-10-051-3/+4
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| * | | | | Add comment on why we have to match for clock-enable/reset muxesEddie Hung2019-10-053-3/+11
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| * | | | | Add note on pattern detectorEddie Hung2019-10-051-3/+7
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| * | | | | Add comment on why partial multipliers are 18x18Eddie Hung2019-10-041-4/+8
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| * | | | | Add comments for xilinx_dsp_cascadeEddie Hung2019-10-041-12/+100
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| * | | | | Improve comments for xilinx_dsp_CREGEddie Hung2019-10-041-6/+7
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| * | | | | Fix commentEddie Hung2019-10-041-1/+1
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| * | | | | Restore optimisation for sigM.empty()Eddie Hung2019-10-041-1/+4
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| * | | | | Retry on fixing TODOsEddie Hung2019-10-042-13/+1
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| * | | | | Revert "Fix TODOs"Eddie Hung2019-10-042-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 8674a6c68d563908014d16671567459499c6dc99.
| * | | | | More comments, cleanupEddie Hung2019-10-042-41/+108
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| * | | | | Fix TODOsEddie Hung2019-10-042-20/+0
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| * | | | | ConsistencyEddie Hung2019-10-041-3/+3
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| * | | | | Add comments for xilinx_dspEddie Hung2019-10-043-6/+134
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* | | | | | Merge pull request #1439 from YosysHQ/eddie/fix_ice40_wrapcarryClifford Wolf2019-10-062-0/+26
|\ \ \ \ \ \ | | | | | | | | | | | | | | Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf
| * | | | | | Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolfEddie Hung2019-10-052-0/+26
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* | | | | | Update README.mdClifford Wolf2019-10-051-1/+1
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* | | | | | Merge pull request #1436 from YosysHQ/mmicko/msvc_fixMiodrag Milanović2019-10-052-2/+7
|\ \ \ \ \ \ | |/ / / / / |/| | | | | Fixes for MSVC build
| * | | | | Fixes for MSVC buildMiodrag Milanovic2019-10-042-2/+7
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* | | | | | Fix typo in check_label()Eddie Hung2019-10-041-1/+1
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* | | | | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`Eddie Hung2019-10-042-5/+19
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* | | | | Remove DSP48E1 from *_cells_xtra.vEddie Hung2019-10-043-178/+2
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* | | | | Fix xilinx_dsp for unsigned extensionsEddie Hung2019-10-041-1/+3
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* | | | | Fix for SigSpec() == SigSpec(State::Sx, 0) to be true againEddie Hung2019-10-041-0/+6
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* | | | | Add Const::{begin,end,empty}()Eddie Hung2019-10-041-0/+3
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