iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Merge branch 'eddie/fix_retime' into xc7srl	Eddie Hung	2019-04-05	2	-1/+7
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\| *	Add retime test	Eddie Hung	2019-04-05	1	-0/+6
\| *	Fix S0 -> S1	Eddie Hung	2019-04-05	1	-1/+1
* \|	Move dffinit til after abc	Eddie Hung	2019-04-05	3	-2/+2
* \|	Merge branch 'eddie/fix_retime' into xc7srl	Eddie Hung	2019-04-05	11	-14/+85
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\| *	Move techamp t:$_DFF_?N? to before abc call	Eddie Hung	2019-04-05	1	-2/+2
\| *	Retry	Eddie Hung	2019-04-05	1	-1/+1
\| *	"&nf -D 0" fails => use "-D 1" instead	Eddie Hung	2019-04-05	1	-1/+1
\| *	Resolve @daveshah1 comment, update synth_xilinx help	Eddie Hung	2019-04-05	2	-7/+9
\| *	synth_xilinx to techmap FFs after abc call, otherwise -retime fails	Eddie Hung	2019-04-05	1	-3/+3
\| *	abc -dff now implies "-D 0" otherwise retiming doesn't happen	Eddie Hung	2019-04-05	1	-0/+2
\| *	Add "read_ilang -lib"	Clifford Wolf	2019-04-05	5	-3/+39
\| *	Added missing argument checking to "mutate" command	Clifford Wolf	2019-04-04	1	-0/+32
* \|	techmap inside map_cells stage	Eddie Hung	2019-04-05	2	-2/+1
* \|	Merge branch 'map_cells_before_map_luts' into xc7srl	Eddie Hung	2019-04-04	1	-0/+1
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\| * \|	Missing techmap entry in help	Eddie Hung	2019-04-04	1	-0/+1
* \| \|	Use soft-logic, not LUT3 instantiation	Eddie Hung	2019-04-04	1	-4/+2
* \| \|	Merge branch 'map_cells_before_map_luts' into xc7srl	Eddie Hung	2019-04-04	2	-13/+13
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\| * \|	synth_xilinx to map_cells before map_luts	Eddie Hung	2019-04-04	1	-12/+12
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\| *	Merge pull request #913 from smunaut/fix_proc_mux	Eddie Hung	2019-04-03	1	-1/+1
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\| \| *	proc_mux: Fix crash when trying to optimize non-existant mux to shiftx	Sylvain Munaut	2019-04-03	1	-1/+1
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* \|	Cleanup comments	Eddie Hung	2019-04-04	1	-5/+4
* \|	t:$dff* -> t:$dff t:$dffe	Eddie Hung	2019-04-04	1	-2/+2
* \|	Remove handling for $pmux, since #895	Eddie Hung	2019-04-03	1	-40/+0
* \|	-nosrl meant when -nobram	Eddie Hung	2019-04-03	1	-1/+1
* \|	Remove duplicate STARTUPE2	Eddie Hung	2019-04-03	1	-1/+0
* \|	Disable shregmap in synth_xilinx if -retime	Eddie Hung	2019-04-03	1	-3/+3
* \|	Add changelog entry	Eddie Hung	2019-04-03	1	-0/+1
* \|	Merge remote-tracking branch 'origin/master' into xc7srl	Eddie Hung	2019-04-03	14	-73/+526
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\| *	Merge pull request #912 from YosysHQ/bram_addr_en	Clifford Wolf	2019-04-03	1	-0/+2
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\| \| *	memory_bram: Consider read enable for address expansion register	David Shah	2019-04-02	1	-0/+2
\| * \|	Merge pull request #910 from ucb-bar/memupdates	Clifford Wolf	2019-04-03	1	-30/+173
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\| \| *	Refine memory support to deal with general Verilog memory definitions.	Jim Lawson	2019-04-01	1	-30/+173
\| * \|	Merge pull request #895 from YosysHQ/pmux2shiftx	Eddie Hung	2019-04-02	1	-0/+28
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\| \| *	Create one $shiftx per bit in width	Eddie Hung	2019-03-25	1	-10/+17
\| \| *	Add a pmux-to-shiftx optimisation to proc_mux	Eddie Hung	2019-03-23	1	-0/+21
\| * \|	Merge pull request #907 from YosysHQ/clifford/fix906	Clifford Wolf	2019-03-30	1	-0/+2
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\| \| * \|	Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906	Clifford Wolf	2019-03-29	1	-0/+2
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\| * \|	Merge pull request #901 from trcwm/libertyfixes	Clifford Wolf	2019-03-28	4	-9/+151
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\| \| * \|	Liberty file parser now accepts superfluous ;	Niels Moseley	2019-03-27	1	-1/+1
\| \| * \|	Liberty file parser now accepts superfluous ;	Niels Moseley	2019-03-27	1	-1/+1
\| \| * \|	Liberty file parser now accepts superfluous ;	Niels Moseley	2019-03-27	4	-9/+151
\| * \| \|	Merge pull request #903 from YosysHQ/bram_reset_transp	Clifford Wolf	2019-03-28	1	-0/+1
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\| \| * \|	memory_bram: Reset make_transp when growing read ports	David Shah	2019-03-27	1	-0/+1
\| * \| \|	Add "read -verific" and "read -noverific"	Clifford Wolf	2019-03-27	1	-6/+28
\| * \| \|	Add "rename -output"	Clifford Wolf	2019-03-27	1	-3/+23
\| * \| \|	Improve "rename" help message	Clifford Wolf	2019-03-27	1	-0/+6
\| * \| \|	Add "cutpoint -undef"	Clifford Wolf	2019-03-26	1	-10/+14
\| * \| \|	Add "hdlname" attribute	Clifford Wolf	2019-03-26	2	-0/+5
\| * \| \|	Fix "verific -extnets" for more complex situations	Clifford Wolf	2019-03-26	2	-15/+93