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verilog: error out when non-ANSI task/func arguments
Eddie Hung
2020-05-11
1
-1
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+5
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tests: add #2042 testcase
Eddie Hung
2020-05-11
1
-0
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+12
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Setup tests/verilog properly
Eddie Hung
2020-05-11
3
-0
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+24
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Merge pull request #2038 from nakengelhardt/no-libdir-flag
Claire Wolf
2020-05-08
1
-2
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+1
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Remove yosys libdir from LDFLAGS (and fix a typo)
N. Engelhardt
2020-05-07
1
-2
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+1
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Fix clang compiler warning
Claire Wolf
2020-05-08
1
-2
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+2
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Merge pull request #2022 from Xiretza/fallthroughs
whitequark
2020-05-08
5
-9
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+26
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Reorder cases to avoid fall-through warning
Xiretza
2020-05-07
1
-3
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+3
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Add YS_FALLTHROUGH macro to mark case fall-through
Xiretza
2020-05-07
5
-6
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+23
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intel_alm: direct LUTRAM cell instantiation
Dan Ravensloft
2020-05-07
9
-52
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+163
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Merge pull request #2005 from YosysHQ/claire/fix1990
Claire Wolf
2020-05-07
9
-19
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+142
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Fix the other "opt_expr -fine" bug introduced in 213a89558
Claire Wolf
2020-05-02
1
-7
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+19
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Add plusargs for output files in test_autotb output
Claire Wolf
2020-05-02
1
-3
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+10
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Bugfix in partsel.v signed indices test cases
Claire Wolf
2020-05-02
1
-2
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+2
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Fix handling of signed indices in bit slices
Claire Wolf
2020-05-02
1
-3
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+8
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Add tests based on the test case from #1990
Claire Wolf
2020-05-02
1
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+46
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Add AST_SELFSZ and improve handling of bit slices
Claire Wolf
2020-05-02
5
-7
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+22
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Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offs...
Claire Wolf
2020-05-02
6
-7
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+57
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Merge pull request #2034 from YosysHQ/eddie/abc_remote
Eddie Hung
2020-05-07
1
-1
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+1
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Makefile: git fetch all commits from $(ABCURL) repo
Eddie Hung
2020-05-06
1
-1
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+1
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Merge pull request #2028 from zachjs/master
Eddie Hung
2020-05-06
3
-1
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+23
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verilog: allow null gen-if then block
Zachary Snow
2020-05-06
3
-1
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+23
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Merge pull request #2025 from YosysHQ/eddie/frontend_cleanup
Eddie Hung
2020-05-05
7
-31
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+34
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frontend: cleanup to use more ID::*, more dict<> instead of map<>
Eddie Hung
2020-05-04
7
-31
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+34
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Merge pull request #2012 from whitequark/fix-wasi-abc-build
whitequark
2020-05-05
1
-3
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+3
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Update ABC to include WASI support fixes.
whitequark
2020-05-02
1
-1
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+1
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Fix WASI builds with abc enabled.
whitequark
2020-05-01
1
-2
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+2
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Merge pull request #2026 from YosysHQ/eddie/scratchpad_abc9_W
Eddie Hung
2020-05-05
3
-11
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+34
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synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad
Eddie Hung
2020-05-04
3
-11
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+34
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Merge pull request #2024 from YosysHQ/eddie/primitive_src
Eddie Hung
2020-05-05
3
-2
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+22
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verilog: set src attribute for primitives
Eddie Hung
2020-05-04
2
-2
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+6
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tests: add tests for primitives' src
Eddie Hung
2020-05-04
1
-0
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+16
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Merge pull request #2023 from YosysHQ/eddie/specify_src
Eddie Hung
2020-05-05
2
-18
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+26
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verilog: fix specify src attribute
Eddie Hung
2020-05-04
2
-18
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+26
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Merge pull request #1996 from boqwxp/rtlil_source_locations
Eddie Hung
2020-05-04
1
-13
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+13
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frontend: Include complete source location instead of just `location.first_li...
Alberto Gonzalez
2020-05-01
1
-13
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+13
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Merge pull request #2000 from whitequark/log_error-trap
whitequark
2020-05-03
2
-3
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+44
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kernel: Trap in `log_error()` when a debugger is attached.
whitequark
2020-05-03
2
-3
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+44
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Merge pull request #2014 from YosysHQ/claire/fixoptalu
Claire Wolf
2020-05-03
2
-7
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+31
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test: add test for #2014
Eddie Hung
2020-05-02
1
-0
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+12
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Fix the other "opt_expr -fine" bug introduced in 213a89558
Claire Wolf
2020-05-02
1
-7
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+19
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Merge pull request #2013 from YosysHQ/eddie/aiger_fixes
Eddie Hung
2020-05-02
6
-42
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+101
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abc9_ops: -reintegrate to be sensitive to start_offset too
Eddie Hung
2020-05-02
1
-3
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+5
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tests: aiger test for wire->start_offset != 0
Eddie Hung
2020-05-02
2
-0
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+41
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aiger: fixes for ports that have start_offset != 0
Eddie Hung
2020-05-02
3
-39
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+55
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Merge pull request #2010 from YosysHQ/claire/fixopt
Claire Wolf
2020-05-02
2
-7
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+29
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Add testcase for #2010
Eddie Hung
2020-05-01
1
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+10
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Fix "opt_expr -fine" bug introduced in 213a89558
Claire Wolf
2020-05-01
1
-7
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+19
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Merge pull request #2001 from whitequark/wasi
whitequark
2020-05-01
17
-29
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+166
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Add WASI platform support.
whitequark
2020-04-30
17
-30
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+167
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