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* Merge branch 'master' into eddie/submod_poEddie Hung2020-02-01219-5980/+12044
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| * Merge pull request #1668 from gsomlo/gls-abc9-externalEddie Hung2020-01-311-0/+1
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| | * abc9: restore ability to use ABCEXTERNALGabriel Somlo2020-01-301-0/+1
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| * Merge pull request #1667 from YosysHQ/clifford/verificnandClaire Wolf2020-01-301-0/+8
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| | * Add Verific support for OPER_REDUCE_NANDClaire Wolf2020-01-301-0/+8
| * | Merge pull request #1503 from YosysHQ/eddie/verific_helpClaire Wolf2020-01-301-8/+8
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| | * \ Merge remote-tracking branch 'origin/master' into eddie/verific_helpEddie Hung2020-01-27208-4938/+10113
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| | * | | verific: no help() when no YOSYS_ENABLE_VERIFICEddie Hung2020-01-271-4/+1
| | * | | OopsEddie Hung2019-11-191-1/+1
| | * | | Print help message for verific passEddie Hung2019-11-191-9/+12
| * | | | Merge pull request #1654 from YosysHQ/eddie/sby_fix69Claire Wolf2020-01-301-0/+6
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| | * | | verific: also unflatten for 'hierarchy' flow as per @cliffordwolfEddie Hung2020-01-271-0/+3
| | * | | verific: unflatten struct portsEddie Hung2020-01-241-0/+3
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| * | | Merge branch 'vector_fix' of https://github.com/Kmanfi/yosysClaire Wolf2020-01-291-1/+3
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| | * | | Fix input vector for reduce cells. Infinite loop fixed.Kaj Tuomi2017-10-171-0/+2
| | * | | Merge branch 'master' of https://github.com/cliffordwolf/yosys into vector_fixKaj Tuomi2017-10-173-1/+54
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| | * | | | Add Verific fairness/liveness supportClifford Wolf2017-10-121-11/+32
| * | | | | Merge pull request #1662 from YosysHQ/dave/opt-reduce-move-checkClaire Wolf2020-01-291-1/+2
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| | * | | | | opt_reduce: Call check() per run rather than per optimised cellDavid Shah2020-01-281-1/+2
| * | | | | | Merge pull request #1665 from YosysHQ/clifford/edifkeepClaire Wolf2020-01-291-9/+34
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| | * | | | | | Preserve wires with keep attribute in EDIF back-endClaire Wolf2020-01-291-9/+34
| * | | | | | | Merge pull request #1659 from YosysHQ/clifford/experimentalClaire Wolf2020-01-296-4/+56
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| | * | | | | | | Improve logging use of experimental featuresClaire Wolf2020-01-283-4/+8
| | * | | | | | | Add log_experimental() and experimental() API and "yosys -x"Claire Wolf2020-01-276-4/+52
| * | | | | | | | Merge pull request #1510 from pumbor/masterN. Engelhardt2020-01-291-0/+13
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| | * | | | | | | | handle anonymous unions to fix #1080Patrick Eibl2019-11-211-0/+13
| * | | | | | | | | Merge pull request #1559 from YosysHQ/efinix_test_fixMiodrag Milanović2020-01-291-1/+1
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| | * | | | | | | | | Updated test to use assert-maxMiodrag Milanovic2020-01-281-1/+1
| | * | | | | | | | | Fix for non-deterministic testMiodrag Milanovic2019-12-071-1/+1
| * | | | | | | | | | Add "help -all" and "help -celltypes" sanity testEddie Hung2020-01-281-0/+2
| * | | | | | | | | | synth_xilinx: cleanup helpEddie Hung2020-01-281-6/+4
| * | | | | | | | | | synth_xilinx: fix help when no active_design; fixes #1664Eddie Hung2020-01-281-2/+3
| * | | | | | | | | | xilinx: Add simulation model for DSP48 (Virtex 4).Marcin Kościelnicki2020-01-296-45/+534
| * | | | | | | | | | Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_lutsEddie Hung2020-01-289-149/+207
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| | * | | | | | | | | | Add and use SigSpec::reverse()Eddie Hung2020-01-282-3/+5
| | * | | | | | | | | | Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwardsEddie Hung2020-01-272-2/+2
| | * | | | | | | | | | Import tests from #1628Eddie Hung2020-01-273-2/+104
| | * | | | | | | | | | xilinx/ice40/ecp5: undo permuting LUT masks in lut_mapEddie Hung2020-01-274-148/+102
| * | | | | | | | | | | Fix unresolved conflict from #1573Eddie Hung2020-01-281-1/+1
| * | | | | | | | | | | Merge pull request #1567 from YosysHQ/eddie/sat_init_warningClaire Wolf2020-01-282-1/+13
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| | * | | | | | | | | | Even more obvious testcaseEddie Hung2019-12-111-6/+5
| | * | | | | | | | | | Make testcase clearer with \o having its own initEddie Hung2019-12-111-0/+2
| | * | | | | | | | | | Suppress warning message for init[i] = 1'bxEddie Hung2019-12-111-1/+2
| | * | | | | | | | | | Add test: 'Warning: ignoring initial value on non-register: \o'Eddie Hung2019-12-111-0/+10
| * | | | | | | | | | | Merge pull request #1573 from YosysHQ/eddie/xilinx_tristateN. Engelhardt2020-01-283-1/+13
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| | * | | | | | | | | | Duplicate tribuf call, credit to @mwkmwkmwkEddie Hung2019-12-131-1/+0
| | * | | | | | | | | | Add testEddie Hung2019-12-121-0/+5
| | * | | | | | | | | | synth_xilinx: error out if tristate without '-iopad'Eddie Hung2019-12-121-0/+4
| | * | | | | | | | | | tribuf: set scratchpad boolean 'tribuf.added_something'Eddie Hung2019-12-121-1/+5
| * | | | | | | | | | | redirect fuser stderr to /dev/nullPepijn de Vos2020-01-281-1/+1
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