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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-19 13:25:38 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-19 13:25:38 -0800 |
| commit | e2819ce31c20b60b7b5b3a58509006322ceb76ab (patch) | |
| tree | a5b93f0471198b2b7bf7ed5cbf7af82166c94d3f | |
| parent | 84711f0e8c842b7309c7f1eff375cb757b41755b (diff) | |
| download | yosys-e2819ce31c20b60b7b5b3a58509006322ceb76ab.tar.gz yosys-e2819ce31c20b60b7b5b3a58509006322ceb76ab.tar.bz2 yosys-e2819ce31c20b60b7b5b3a58509006322ceb76ab.zip | |
Oops
| -rw-r--r-- | frontends/verific/verific.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index e88702087..79730c98a 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2397,7 +2397,7 @@ struct VerificPass : public Pass { else { if (argidx == GetSize(args)) - cmd_error(arg, argidx, "No top module specified.\n"); + cmd_error(args, argidx, "No top module specified.\n"); Array veri_modules, vhdl_units; for (; argidx < GetSize(args); argidx++) |