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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-11 23:52:05 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-11 23:52:05 -0800 |
| commit | 4a805108776f563bcd7550d1331a73a50512fbe2 (patch) | |
| tree | 0f458363389e75544899a1b1c17086bb708b4d7e | |
| parent | 61a1f3f49b7bd0478b92c0933c487af5803c53f9 (diff) | |
| download | yosys-4a805108776f563bcd7550d1331a73a50512fbe2.tar.gz yosys-4a805108776f563bcd7550d1331a73a50512fbe2.tar.bz2 yosys-4a805108776f563bcd7550d1331a73a50512fbe2.zip | |
Even more obvious testcase
| -rw-r--r-- | tests/sat/initval.ys | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 6cb68a8d3..1436724b0 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -5,12 +5,11 @@ sat -seq 10 -prove-asserts design -reset read_verilog -icells <<EOT -module top(input clk, i, output o, p); -(* init = 1'b0 *) -wire o; -(* init = 1'bx *) -wire p = o; -$_DFF_P_ dff (.C(clk), .D(i), .Q(o)); +module top(input clk, i, output [1:0] o); +(* init = 2'bx0 *) +wire [1:0] o; +assign o[1] = o[0]; +$_DFF_P_ dff (.C(clk), .D(i), .Q(o[0])); endmodule EOT sat -seq 1 |