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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-11 23:48:09 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-11 23:48:09 -0800 |
| commit | 61a1f3f49b7bd0478b92c0933c487af5803c53f9 (patch) | |
| tree | 64c01c1094c1854fe2ebbf161fe13682fe66458f | |
| parent | 9a892199f72bb08f78c868fe8ab5b8a63cf25f37 (diff) | |
| download | yosys-61a1f3f49b7bd0478b92c0933c487af5803c53f9.tar.gz yosys-61a1f3f49b7bd0478b92c0933c487af5803c53f9.tar.bz2 yosys-61a1f3f49b7bd0478b92c0933c487af5803c53f9.zip | |
Make testcase clearer with \o having its own init
| -rw-r--r-- | tests/sat/initval.ys | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 337aa9343..6cb68a8d3 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -6,6 +6,8 @@ sat -seq 10 -prove-asserts design -reset read_verilog -icells <<EOT module top(input clk, i, output o, p); +(* init = 1'b0 *) +wire o; (* init = 1'bx *) wire p = o; $_DFF_P_ dff (.C(clk), .D(i), .Q(o)); |