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* synth: add asserts in synth-valuesTristan Gingold2019-08-051-0/+5
* synth: handle subtype conversions.Tristan Gingold2019-08-055-73/+154
* synth: handle signed conversions in disp_vhdl.Tristan Gingold2019-08-051-2/+6
* synth: preliminary support of integer literals.Tristan Gingold2019-08-022-18/+67
* synth: add a debug procedure.Tristan Gingold2019-08-022-0/+22
* synth: improve error message for multiple assignments.Tristan Gingold2019-08-021-4/+20
* synth: handle signed integer comparisons (#878)Pepijn de Vos2019-08-013-0/+43
* synth: handle partial assignments in a process (WIP).Tristan Gingold2019-08-011-18/+75
* synth: refactoring in inference/environment.Tristan Gingold2019-08-013-7/+13
* synth: refactor inference, add comment, strengthen check.Tristan Gingold2019-08-014-31/+62
* synth: refactoring in synth-inference.Tristan Gingold2019-07-311-129/+137
* synth: add location on monadic operators.Tristan Gingold2019-07-311-7/+10
* synth: regenerate ghdlsynth_gates.hTristan Gingold2019-07-311-3/+4
* synth: fix a crash in instantiation.Tristan Gingold2019-07-312-8/+9
* synth: slightly improve output for indexes.Tristan Gingold2019-07-301-3/+7
* synth: adjust output for dyn_insert, add dpram2 test.Tristan Gingold2019-07-301-2/+2
* synth: fixes for indexed names.Tristan Gingold2019-07-303-3/+13
* synth: rework indexed names.Tristan Gingold2019-07-304-101/+106
* synth: handle more conversions in disp_vhdlTristan Gingold2019-07-291-1/+44
* synth: add support for memories.Tristan Gingold2019-07-2915-152/+445
* synth: remove extract_bound (trivial).Tristan Gingold2019-07-285-15/+6
* synth: unconstrained arrays.Tristan Gingold2019-07-285-17/+71
* synth: preliminary support of dynamic indexing.Tristan Gingold2019-07-2813-740/+956
* vhdl: linearize analyze and evaluation of concat operators.Tristan Gingold2019-07-265-360/+647
* synth: rework range.Tristan Gingold2019-07-265-48/+52
* synth: preliminary support of integer subtypes.Tristan Gingold2019-07-268-42/+68
* synth: handle array aggregate.Tristan Gingold2019-07-262-27/+32
* synth: handle bit.Tristan Gingold2019-07-253-4/+11
* synth: array inequality, integer in choices.Tristan Gingold2019-07-252-0/+11
* vhdl+synth: recognize /= to std_logic_unsigned.Tristan Gingold2019-07-253-1/+16
* vhdl: handle (discard) more pragmas.Tristan Gingold2019-07-253-1/+19
* synth: save and display locations for instances.Tristan Gingold2019-07-258-66/+247
* synth: fix incorrect slice in disp_vhdl for Insert.Tristan Gingold2019-07-251-6/+1
* vhdl annotations: fix annotation of type in interface list.Tristan Gingold2019-07-241-0/+1
* synth: fix bad ordering in case statement.Tristan Gingold2019-07-241-2/+3
* synth: do not consider (unrecognized) ieee functions as user functions.Tristan Gingold2019-07-241-0/+19
* synth: enable handling of pragma translate_on/off.Tristan Gingold2019-07-241-0/+3
* vhdl scanner: handle pragma translate_on/translate_off.Tristan Gingold2019-07-245-5/+109
* synth: handle resize.Tristan Gingold2019-07-241-0/+15
* synth: handle record type declarations.Tristan Gingold2019-07-241-1/+11
* vhdl: recognize resize function.Tristan Gingold2019-07-244-3/+43
* synth: fix slice/indexed assignment that partially override previous assign.Tristan Gingold2019-07-231-5/+8
* synth: add more operators.Tristan Gingold2019-07-231-1/+34
* synth: fix to_unsigned.Tristan Gingold2019-07-231-2/+2
* synth: use original entity to display netlist.Tristan Gingold2019-07-237-22/+314
* vhdl-prints: improve output for ports/generics.Tristan Gingold2019-07-221-5/+27
* synth: remove bounds (unused) for ports.Tristan Gingold2019-07-224-13/+4
* ghdlsynth: preliminary work for wrapped generation.Tristan Gingold2019-07-221-1/+8
* synth: minor refactoring in netlists.disp_vhdlTristan Gingold2019-07-222-47/+54
* synth: minor rework.Tristan Gingold2019-07-223-10/+37
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