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| author | Tristan Gingold <tgingold@free.fr> | 2019-07-31 05:53:58 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-07-31 05:53:58 +0200 |
| commit | 64025f9a660e39b627e91c08d988138032e11b0e (patch) | |
| tree | 7a9b15376932aa5d64b17cb743de485faa0c9832 /src | |
| parent | e2a988ff5777dc81708842676564e3fa32a2b910 (diff) | |
| download | ghdl-64025f9a660e39b627e91c08d988138032e11b0e.tar.gz ghdl-64025f9a660e39b627e91c08d988138032e11b0e.tar.bz2 ghdl-64025f9a660e39b627e91c08d988138032e11b0e.zip | |
synth: fix a crash in instantiation.
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-expr.adb | 2 | ||||
| -rw-r--r-- | src/synth/synth-insts.adb | 15 |
2 files changed, 9 insertions, 8 deletions
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index b1e88ea3c..943608aaf 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -130,7 +130,7 @@ package body Synth.Expr is begin if Etype = Logic_Type then From_Std_Logic (Enum, Val, Zx); - elsif Etype = Boolean_Type then + elsif Etype = Boolean_Type or Etype = Bit_Type then From_Bit (Enum, Val); Zx := 0; else diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb index c9cbd1ea7..721671e1e 100644 --- a/src/synth/synth-insts.adb +++ b/src/synth/synth-insts.adb @@ -258,9 +258,11 @@ package body Synth.Insts is Build => Build, Equal => Equal); + -- Subprogram used for instantiation (direct or by component). + -- PORTS_ASSOC belong to SYN_INST. procedure Synth_Instantiate_Module (Syn_Inst : Synth_Instance_Acc; Inst : Instance; - Ports : Node; + Inst_Obj : Inst_Object; Ports_Assoc : Node) is -- Instantiate the module @@ -277,7 +279,7 @@ package body Synth.Insts is Nbr_Outputs : Port_Nbr; begin Assoc := Ports_Assoc; - Assoc_Inter := Ports; + Assoc_Inter := Get_Port_Chain (Inst_Obj.Decl); Nbr_Inputs := 0; Nbr_Outputs := 0; while Is_Valid (Assoc) loop @@ -303,7 +305,8 @@ package body Synth.Insts is | Port_Inout => Port := Get_Output (Inst, Nbr_Outputs); Port := Builders.Build_Port (Build_Context, Port); - O := Create_Value_Net (Port, null); + O := Create_Value_Net + (Port, Get_Value_Type (Inst_Obj.Syn_Inst, Get_Type (Inter))); Synth_Assignment (Syn_Inst, Actual, O); Nbr_Outputs := Nbr_Outputs + 1; end case; @@ -366,8 +369,7 @@ package body Synth.Insts is New_Sname_User (Get_Identifier (Stmt))); Synth_Instantiate_Module - (Syn_Inst, Inst, - Get_Port_Chain (Ent), Get_Port_Map_Aspect_Chain (Stmt)); + (Syn_Inst, Inst, Inst_Obj, Get_Port_Map_Aspect_Chain (Stmt)); end Synth_Direct_Instantiation_Statement; procedure Synth_Design_Instantiation_Statement @@ -538,8 +540,7 @@ package body Synth.Insts is New_Sname_User (Get_Identifier (Stmt))); Synth_Instantiate_Module - (Comp_Inst, Inst, - Get_Port_Chain (Ent), Get_Port_Map_Aspect_Chain (Bind)); + (Comp_Inst, Inst, Inst_Obj, Get_Port_Map_Aspect_Chain (Bind)); -- Connect out from component to instance. -- Instantiate the module |