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| author | Tristan Gingold <tgingold@free.fr> | 2019-08-01 04:31:37 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-08-01 04:31:37 +0200 |
| commit | 45d2b4e9327e4798b8dd657c5e9abec9d8e6c617 (patch) | |
| tree | 070c0545dfcff9caefcf22d6e1df36832259e2e0 /src | |
| parent | d8daefafb575227a1644b2f24bd604dcbfc76c75 (diff) | |
| download | ghdl-45d2b4e9327e4798b8dd657c5e9abec9d8e6c617.tar.gz ghdl-45d2b4e9327e4798b8dd657c5e9abec9d8e6c617.tar.bz2 ghdl-45d2b4e9327e4798b8dd657c5e9abec9d8e6c617.zip | |
synth: refactoring in inference/environment.
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-environment.adb | 9 | ||||
| -rw-r--r-- | src/synth/synth-environment.ads | 2 | ||||
| -rw-r--r-- | src/synth/synth-inference.adb | 9 |
3 files changed, 13 insertions, 7 deletions
diff --git a/src/synth/synth-environment.adb b/src/synth/synth-environment.adb index 0051f48fa..0368edcc3 100644 --- a/src/synth/synth-environment.adb +++ b/src/synth/synth-environment.adb @@ -144,7 +144,8 @@ package body Synth.Environment is Wire_Rec.Nbr_Final_Assign := Wire_Rec.Nbr_Final_Assign + 1; end Add_Conc_Assign_Partial; - procedure Add_Conc_Assign (Wid : Wire_Id; Val : Net; Stmt : Source.Syn_Src) + procedure Add_Conc_Assign_Comb + (Wid : Wire_Id; Val : Net; Stmt : Source.Syn_Src) is Wire_Rec : Wire_Id_Record renames Wire_Id_Table.Table (Wid); Inst : constant Instance := Get_Parent (Val); @@ -169,6 +170,12 @@ package body Synth.Environment is Off := 0; end if; Add_Conc_Assign_Partial (Wid, V, Off, Stmt); + end Add_Conc_Assign_Comb; + + procedure Add_Conc_Assign + (Wid : Wire_Id; Val : Net; Stmt : Source.Syn_Src) is + begin + Add_Conc_Assign_Partial (Wid, Val, 0, Stmt); end Add_Conc_Assign; -- This procedure is called after each concurrent statement to assign diff --git a/src/synth/synth-environment.ads b/src/synth/synth-environment.ads index c16a3cc0b..09730b43d 100644 --- a/src/synth/synth-environment.ads +++ b/src/synth/synth-environment.ads @@ -110,6 +110,8 @@ package Synth.Environment is pragma Inline (Current_Phi); procedure Add_Conc_Assign (Wid : Wire_Id; Val : Net; Stmt : Source.Syn_Src); + procedure Add_Conc_Assign_Comb + (Wid : Wire_Id; Val : Net; Stmt : Source.Syn_Src); procedure Finalize_Assignments (Ctxt : Builders.Context_Acc); private diff --git a/src/synth/synth-inference.adb b/src/synth/synth-inference.adb index ebe478fa7..a6b4cd094 100644 --- a/src/synth/synth-inference.adb +++ b/src/synth/synth-inference.adb @@ -334,12 +334,9 @@ package body Synth.Inference is Enable : Net; begin Find_Longest_Loop (Val, Prev_Val, Last_Mux, Len); - if Len < 0 then - -- No logical loop - Add_Conc_Assign (Wid, Val, Stmt); - elsif Len = 0 then - -- Self assignment. - Add_Conc_Assign (Wid, Val, Stmt); + if Len <= 0 then + -- No logical loop or self assignment. + Add_Conc_Assign_Comb (Wid, Val, Stmt); else -- So there is a logical loop. Sel := Get_Mux2_Sel (Last_Mux); |