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| author | Tristan Gingold <tgingold@free.fr> | 2019-07-23 05:29:59 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-07-23 05:29:59 +0200 |
| commit | 5ab518311214dec42f0ae4ce8287008f964624e1 (patch) | |
| tree | 942cdc82f1d5244869ff09d25eb62eefbd62eec4 /src | |
| parent | 3d683addbbf4bd7a96e202a9949b4820590d6134 (diff) | |
| download | ghdl-5ab518311214dec42f0ae4ce8287008f964624e1.tar.gz ghdl-5ab518311214dec42f0ae4ce8287008f964624e1.tar.bz2 ghdl-5ab518311214dec42f0ae4ce8287008f964624e1.zip | |
synth: fix to_unsigned.
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-expr.adb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index 25efc8a56..d8614f543 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -22,7 +22,7 @@ with Ada.Unchecked_Conversion; with Types_Utils; use Types_Utils; with Std_Names; with Str_Table; -with Vhdl.Ieee.Std_Logic_1164; +with Vhdl.Ieee.Std_Logic_1164; use Vhdl.Ieee.Std_Logic_1164; with Vhdl.Std_Package; with Vhdl.Errors; use Vhdl.Errors; with Vhdl.Utils; use Vhdl.Utils; @@ -1450,7 +1450,7 @@ package body Synth.Expr is Arr := Create_Value_Array (Len); for I in 1 .. Len loop Arr.V (Len - I + 1) := Create_Value_Discrete - ((Arg / 2 ** Natural (I - 1)) mod 2); + (Std_Logic_0_Pos + (Arg / 2 ** Natural (I - 1)) mod 2); end loop; Bnds := Create_Value_Bound_Array (1); Bnds.D (1) := Create_Value_Bound |