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| author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-08-01 19:07:53 +0200 |
|---|---|---|
| committer | tgingold <tgingold@users.noreply.github.com> | 2019-08-01 19:07:53 +0200 |
| commit | 9b64728925b49051e6ae489ae005c0f22df0110e (patch) | |
| tree | 41bcb027ac5757e8c501fb8ce8892972d24bf463 /src | |
| parent | ae6d2b79e508684f189b6d8cc093dbb6f586f767 (diff) | |
| download | ghdl-9b64728925b49051e6ae489ae005c0f22df0110e.tar.gz ghdl-9b64728925b49051e6ae489ae005c0f22df0110e.tar.bz2 ghdl-9b64728925b49051e6ae489ae005c0f22df0110e.zip | |
synth: handle signed integer comparisons (#878)
* comparisons with integer literals
* display signed comparison nicely
* revert literal size changes
* properly display signed values
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/netlists-builders.adb | 10 | ||||
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 12 | ||||
| -rw-r--r-- | src/synth/synth-expr.adb | 21 |
3 files changed, 43 insertions, 0 deletions
diff --git a/src/synth/netlists-builders.adb b/src/synth/netlists-builders.adb index d1c0b3785..a35159e77 100644 --- a/src/synth/netlists-builders.adb +++ b/src/synth/netlists-builders.adb @@ -434,6 +434,16 @@ package body Netlists.Builders is Create_Compare_Module (Design, Res.M_Compare (Id_Uge), Get_Identifier ("uge"), Id_Uge); + Create_Compare_Module (Design, Res.M_Compare (Id_Slt), + Get_Identifier ("slt"), Id_Slt); + Create_Compare_Module (Design, Res.M_Compare (Id_Sle), + Get_Identifier ("sle"), Id_Sle); + + Create_Compare_Module (Design, Res.M_Compare (Id_Sgt), + Get_Identifier ("sgt"), Id_Sgt); + Create_Compare_Module (Design, Res.M_Compare (Id_Sge), + Get_Identifier ("sge"), Id_Sge); + Create_Concat_Modules (Res); Create_Const_Modules (Res); diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 800fc585c..55026054d 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -635,6 +635,18 @@ package body Netlists.Disp_Vhdl is when Id_Uge => Disp_Template (" \o0 <= '1' when \ui0 >= \ui1 else '0';" & NL, Inst); + when Id_Slt => + Disp_Template (" \o0 <= '1' when \si0 < \si1 else '0';" & NL, + Inst); + when Id_Sle => + Disp_Template (" \o0 <= '1' when \si0 <= \si1 else '0';" & NL, + Inst); + when Id_Sgt => + Disp_Template (" \o0 <= '1' when \si0 > \si1 else '0';" & NL, + Inst); + when Id_Sge => + Disp_Template (" \o0 <= '1' when \si0 >= \si1 else '0';" & NL, + Inst); when Id_Eq => Disp_Template (" \o0 <= '1' when \i0 = \i1 else '0';" & NL, Inst); when Id_Ne => diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index 67121652f..f7cbe074b 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -1048,6 +1048,27 @@ package body Synth.Expr is else return Synth_Compare (Id_Sle); end if; + when Iir_Predefined_Integer_Less => + if Is_Const (Left) and then Is_Const (Right) then + return Create_Value_Discrete + (Boolean'Pos (Left.Scal < Right.Scal), Boolean_Type); + else + return Synth_Compare (Id_Slt); + end if; + when Iir_Predefined_Integer_Greater_Equal => + if Is_Const (Left) and then Is_Const (Right) then + return Create_Value_Discrete + (Boolean'Pos (Left.Scal >= Right.Scal), Boolean_Type); + else + return Synth_Compare (Id_Sge); + end if; + when Iir_Predefined_Integer_Greater => + if Is_Const (Left) and then Is_Const (Right) then + return Create_Value_Discrete + (Boolean'Pos (Left.Scal > Right.Scal), Boolean_Type); + else + return Synth_Compare (Id_Sgt); + end if; when Iir_Predefined_Integer_Equality => if Is_Const (Left) and then Is_Const (Right) then return Create_Value_Discrete |