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authorTristan Gingold <tgingold@free.fr>2019-07-23 18:36:50 +0200
committerTristan Gingold <tgingold@free.fr>2019-07-24 05:23:31 +0200
commit8653cfdef98b6ccd591b2cdf903c4a8149a18e93 (patch)
tree980761da8bab228485a55bd3d2d0d3a96703f928 /src
parente0281345a5437282f287568b6fafa8519512b9dd (diff)
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vhdl: recognize resize function.
Diffstat (limited to 'src')
-rw-r--r--src/std_names.adb1
-rw-r--r--src/std_names.ads7
-rw-r--r--src/vhdl/vhdl-ieee-numeric.adb33
-rw-r--r--src/vhdl/vhdl-nodes.ads5
4 files changed, 43 insertions, 3 deletions
diff --git a/src/std_names.adb b/src/std_names.adb
index 3a5cb9c9f..499eb29c4 100644
--- a/src/std_names.adb
+++ b/src/std_names.adb
@@ -625,6 +625,7 @@ package body Std_Names is
Def ("to_integer", Name_To_Integer);
Def ("to_unsigned", Name_To_Unsigned);
Def ("to_signed", Name_To_Signed);
+ Def ("resize", Name_Resize);
Def ("math_real", Name_Math_Real);
Def ("ceil", Name_Ceil);
Def ("log2", Name_Log2);
diff --git a/src/std_names.ads b/src/std_names.ads
index 44a6b8495..5b7cc7964 100644
--- a/src/std_names.ads
+++ b/src/std_names.ads
@@ -708,9 +708,10 @@ package Std_Names is
Name_To_Integer : constant Name_Id := Name_First_Ieee + 019;
Name_To_Unsigned : constant Name_Id := Name_First_Ieee + 020;
Name_To_Signed : constant Name_Id := Name_First_Ieee + 021;
- Name_Math_Real : constant Name_Id := Name_First_Ieee + 022;
- Name_Ceil : constant Name_Id := Name_First_Ieee + 023;
- Name_Log2 : constant Name_Id := Name_First_Ieee + 024;
+ Name_Resize : constant Name_Id := Name_First_Ieee + 022;
+ Name_Math_Real : constant Name_Id := Name_First_Ieee + 023;
+ Name_Ceil : constant Name_Id := Name_First_Ieee + 024;
+ Name_Log2 : constant Name_Id := Name_First_Ieee + 025;
Name_Last_Ieee : constant Name_Id := Name_Log2;
-- Verilog Directives.
diff --git a/src/vhdl/vhdl-ieee-numeric.adb b/src/vhdl/vhdl-ieee-numeric.adb
index 9f57e7787..ad13f9274 100644
--- a/src/vhdl/vhdl-ieee-numeric.adb
+++ b/src/vhdl/vhdl-ieee-numeric.adb
@@ -319,6 +319,37 @@ package body Vhdl.Ieee.Numeric is
raise Error;
end if;
end Handle_To_Integer;
+
+ procedure Handle_Resize is
+ begin
+ if Arg2_Kind = Arg_Scal and Arg2_Sign = Type_Unsigned then
+ if Arg1_Kind = Arg_Vect and Arg1_Sign = Type_Unsigned then
+ Set_Implicit_Definition
+ (Decl, Iir_Predefined_Ieee_Numeric_Std_Resize_Uns_Nat);
+ elsif Arg1_Kind = Arg_Vect and Arg1_Sign = Type_Signed then
+ Set_Implicit_Definition
+ (Decl, Iir_Predefined_Ieee_Numeric_Std_Resize_Sgn_Nat);
+ else
+ raise Error;
+ end if;
+ elsif Arg2_Kind = Arg_Vect then
+ if Arg1_Kind = Arg_Vect and Arg1_Sign = Type_Unsigned
+ and Arg2_Sign = Type_Unsigned
+ then
+ Set_Implicit_Definition
+ (Decl, Iir_Predefined_Ieee_Numeric_Std_Resize_Uns_Uns);
+ elsif Arg1_Kind = Arg_Vect and Arg1_Sign = Type_Signed
+ and Arg2_Sign = Type_Signed
+ then
+ Set_Implicit_Definition
+ (Decl, Iir_Predefined_Ieee_Numeric_Std_Resize_Sgn_Sgn);
+ else
+ raise Error;
+ end if;
+ else
+ raise Error;
+ end if;
+ end Handle_Resize;
begin
Decl := Get_Declaration_Chain (Pkg_Decl);
@@ -413,6 +444,8 @@ package body Vhdl.Ieee.Numeric is
Handle_To_Unsigned;
when Name_To_Signed =>
Handle_To_Signed;
+ when Name_Resize =>
+ Handle_Resize;
when others =>
null;
end case;
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads
index c6f4a9c2a..6930d79bc 100644
--- a/src/vhdl/vhdl-nodes.ads
+++ b/src/vhdl/vhdl-nodes.ads
@@ -4886,6 +4886,11 @@ package Vhdl.Nodes is
Iir_Predefined_Ieee_Numeric_Std_Tosgn_Int_Nat_Sgn,
Iir_Predefined_Ieee_Numeric_Std_Tosgn_Int_Sgn_Sgn,
+ Iir_Predefined_Ieee_Numeric_Std_Resize_Uns_Nat,
+ Iir_Predefined_Ieee_Numeric_Std_Resize_Sgn_Nat,
+ Iir_Predefined_Ieee_Numeric_Std_Resize_Uns_Uns,
+ Iir_Predefined_Ieee_Numeric_Std_Resize_Sgn_Sgn,
+
Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Uns,
Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Nat,
Iir_Predefined_Ieee_Numeric_Std_Add_Nat_Uns,