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path: root/src/synth/netlists-disp_vhdl.adb
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* netlists-disp_vhdl: adjust output for #2140Tristan Gingold2022-07-271-2/+8
* netlist-disp_vhdl: add a separator between instances and signals.Tristan Gingold2022-07-261-1/+1
* synth: Display dlatchTristan Gingold2022-07-141-1/+4
* synth memories: also accept constant signal as memory initial valueTristan Gingold2021-11-281-3/+8
* synth: put direction into port descTristan Gingold2021-11-171-9/+5
* synth: use a global table for instances attributesTristan Gingold2021-11-171-48/+38
* synth: renaming to instance_attributes.Tristan Gingold2021-11-171-5/+6
* synth: reuse signal name while creating memories. Fix #1838Tristan Gingold2021-08-251-5/+5
* netlists-disp_vhdl: do not display edge net when not needed. Fix #1703Tristan Gingold2021-03-291-6/+48
* synth: expand ports for record. Fix #1675Tristan Gingold2021-03-271-5/+3
* netlists-dump: also dump attributesTristan Gingold2021-03-171-64/+1
* update license headersumarcor2021-02-051-5/+3
* synth: add option to treat asserts as assumes and vice-versatmeissner2021-01-021-1/+2
* netlists-disp_vhdl: handle null vectors for reducation operators.Tristan Gingold2020-09-281-3/+12
* synth: disp_vhdl: const_x may not have a location.Tristan Gingold2020-07-211-0/+1
* netlists-disp_vhdl: display inout ports as inout.Tristan Gingold2020-07-021-2/+8
* netlists: handle UL32 in memory initial value.Tristan Gingold2020-05-291-1/+11
* synth: handle reduction operators. Fix #1342Tristan Gingold2020-05-271-0/+16
* netlists: disp attributes in vhdl output (as comments). For #1318Tristan Gingold2020-05-231-20/+95
* netlists-memories: set location on utrunc. Fix #1332Tristan Gingold2020-05-211-10/+11
* netlists-disp_vhdl: fix id_sextend for 1 bit.Tristan Gingold2020-05-211-1/+1
* synth: handle inout ports with default values. For #1312Tristan Gingold2020-05-161-1/+2
* netlists-builders: add Build_Pmux.Tristan Gingold2020-05-091-0/+29
* synth: add Id_Enable gate (for sequential assertions).Tristan Gingold2020-05-061-0/+2
* synth: preliminary support of sequential assertions. For #1273Tristan Gingold2020-05-041-1/+1
* netlists: ignore missing location on more const.Tristan Gingold2020-04-271-7/+10
* netlists-disp_vhdl: check presence location on significant instances.Tristan Gingold2020-04-261-0/+15
* netlists: add resolver gate.Tristan Gingold2020-04-221-0/+5
* synth: add tri gate.Tristan Gingold2020-04-221-0/+4
* synth: improve handling of nested memories. Fix #1250Tristan Gingold2020-04-201-1/+5
* synth: rework edge handling to properly support falling edge. Fix #1227Tristan Gingold2020-04-151-20/+53
* netlists-disp_vhdl: factorize code, improve handling of 'Z'.Tristan Gingold2020-04-061-16/+8
* netlists-disp_vhdl: display generics.Tristan Gingold2020-03-311-0/+25
* synth: preliminary work to export module parameters.Tristan Gingold2020-03-311-12/+41
* netlists-disp_vhdl: fix typos.Tristan Gingold2020-03-311-2/+2
* synth: improve output of memory initial value.Tristan Gingold2020-03-291-4/+36
* synth: add id_inout gate to handle inout behaviour. Fir #1166Tristan Gingold2020-03-231-0/+13
* synth-disp_vhdl: do not wrap inout ports. For #1166Tristan Gingold2020-03-221-0/+2
* netlists: add id_nop gate.Tristan Gingold2020-03-221-0/+2
* synth: handle numeric_std minimum/maximum. Fix #1168Tristan Gingold2020-03-211-0/+12
* synth: handle div/rem/mod operations. Fix #1157Tristan Gingold2020-03-131-0/+3
* netlists: handle more case of 0 sized nets.Tristan Gingold2020-03-131-1/+0
* netlists-expands: fix dyn_insert_en (en was missing). Fix #1155Tristan Gingold2020-03-071-0/+2
* netlists-disp_vhdl: handle xnor. Fix #1153Tristan Gingold2020-03-071-0/+2
* netlists: rework memories to fix port orders, add a loop.Tristan Gingold2020-02-231-7/+10
* synth: handle component with ports in different order.Tristan Gingold2020-02-131-18/+12
* synth: handle null vector for vec-vec concat. Fix #1133Tristan Gingold2020-02-111-1/+3
* netlists-disp_vhdl: handle 1-bit const_x. For #1107Tristan Gingold2020-02-051-3/+9
* netlists-disp_vhdl: minor rework.Tristan Gingold2020-01-261-2/+2
* synth: improve support of 0-width nets and gates. Fix #1113Tristan Gingold2020-01-251-14/+22
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