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authorTristan Gingold <tgingold@free.fr>2020-03-21 17:16:08 +0100
committerTristan Gingold <tgingold@free.fr>2020-03-21 17:16:08 +0100
commit134c6ed91339538eeb0c62b25de4c2ea79e89e37 (patch)
tree9b3da160a0b299533ee8a5c0c7553ff29be0469b /src/synth/netlists-disp_vhdl.adb
parente63bc8249ddfca1176b72f038ba8b9fa12b0f38c (diff)
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synth: handle numeric_std minimum/maximum. Fix #1168
Diffstat (limited to 'src/synth/netlists-disp_vhdl.adb')
-rw-r--r--src/synth/netlists-disp_vhdl.adb12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb
index 22dc86e84..423a9ed96 100644
--- a/src/synth/netlists-disp_vhdl.adb
+++ b/src/synth/netlists-disp_vhdl.adb
@@ -943,6 +943,18 @@ package body Netlists.Disp_Vhdl is
Disp_Template (" \o0 <= std_logic_vector (\ui0 - \ui1);" & NL,
Inst);
end if;
+ when Id_Umin =>
+ Disp_Template (" \o0 <= \i0 when \ui0 < \ui1 else \i1;" & NL,
+ Inst);
+ when Id_Smin =>
+ Disp_Template (" \o0 <= \i0 when \si0 < \si1 else \i1;" & NL,
+ Inst);
+ when Id_Umax =>
+ Disp_Template (" \o0 <= \i0 when \ui0 > \ui1 else \i1;" & NL,
+ Inst);
+ when Id_Smax =>
+ Disp_Template (" \o0 <= \i0 when \si0 > \si1 else \i1;" & NL,
+ Inst);
when Id_Umul =>
Disp_Template
(" \o0 <= std_logic_vector (resize (\ui0 * \ui1, \n0));" & NL,