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| author | Tristan Gingold <tgingold@free.fr> | 2020-03-13 06:20:41 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-03-13 06:30:36 +0100 |
| commit | 1fe0246646e2876c0d78d2a0ee16979658d79ac7 (patch) | |
| tree | 043451ad88bce4a387f0639816f8ae55eced1c13 /src/synth/netlists-disp_vhdl.adb | |
| parent | ee840b7acee12202cbbedcd9794be67e32e312ef (diff) | |
| download | ghdl-1fe0246646e2876c0d78d2a0ee16979658d79ac7.tar.gz ghdl-1fe0246646e2876c0d78d2a0ee16979658d79ac7.tar.bz2 ghdl-1fe0246646e2876c0d78d2a0ee16979658d79ac7.zip | |
synth: handle div/rem/mod operations. Fix #1157
Diffstat (limited to 'src/synth/netlists-disp_vhdl.adb')
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 387665705..22dc86e84 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -957,6 +957,9 @@ package body Netlists.Disp_Vhdl is when Id_Srem => Disp_Template (" \o0 <= std_logic_vector (\si0 rem \si1);" & NL, Inst); + when Id_Umod => + Disp_Template + (" \o0 <= std_logic_vector (\ui0 mod \ui1);" & NL, Inst); when Id_Sdiv => Disp_Template (" \o0 <= std_logic_vector (\si0 / \si1);" & NL, Inst); |