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| author | Tristan Gingold <tgingold@free.fr> | 2021-08-25 18:37:58 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-08-25 18:38:22 +0200 |
| commit | 2ef64244d0317a750a8a225b22a59c5b667ec8ee (patch) | |
| tree | 19efa805b1e2e2562607a4cb046a03f8d1bd3017 /src/synth/netlists-disp_vhdl.adb | |
| parent | 14862c4f2cb088c8274f9fb42217784db28856c3 (diff) | |
| download | ghdl-2ef64244d0317a750a8a225b22a59c5b667ec8ee.tar.gz ghdl-2ef64244d0317a750a8a225b22a59c5b667ec8ee.tar.bz2 ghdl-2ef64244d0317a750a8a225b22a59c5b667ec8ee.zip | |
synth: reuse signal name while creating memories. Fix #1838
Diffstat (limited to 'src/synth/netlists-disp_vhdl.adb')
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index ce25ca15b..79e86bc36 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -750,7 +750,7 @@ package body Netlists.Disp_Vhdl is Depth := Get_Width (Ports) / Data_W; -- Declare the memory. - Disp_Template (" type \o0_type is array (0 to \n0)" & NL, + Disp_Template (" type \l0_type is array (0 to \n0)" & NL, Mem, (0 => Depth - 1)); if Data_W = 1 then Disp_Template (" of std_logic;" & NL, Mem); @@ -758,7 +758,7 @@ package body Netlists.Disp_Vhdl is Disp_Template (" of std_logic_vector (\n0 downto 0);" & NL, Mem, (0 => Data_W - 1)); end if; - Disp_Template (" variable \o0 : \o0_type", Mem); + Disp_Template (" variable \l0 : \l0_type", Mem); if Get_Id (Mem) = Id_Memory_Init then declare Val : Net; @@ -785,19 +785,19 @@ package body Netlists.Disp_Vhdl is Disp_Template (" if \ei2 and (\fi3 = '1') then" & NL, Port_Inst); - Disp_Template (" \o0 (", Mem); + Disp_Template (" \l0 (", Mem); Disp_Template ("to_integer (\ui1)) := \i4;" & NL, Port_Inst); Put_Line (" end if;"); when Id_Mem_Rd => Disp_Template (" \o1 <= ", Port_Inst); - Disp_Template ("\o0", Mem); + Disp_Template ("\l0", Mem); Disp_Template ("(to_integer (\ui1));" & NL, Port_Inst); when Id_Mem_Rd_Sync => Disp_Template (" if \ei2 and (\fi3 = '1') then" & NL, Port_Inst); Disp_Template (" \o1 <= ", Port_Inst); - Disp_Template ("\o0", Mem); + Disp_Template ("\l0", Mem); Disp_Template ("(to_integer (\ui1));" & NL, Port_Inst); Put_Line (" end if;"); when Id_Memory |