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authorTristan Gingold <tgingold@free.fr>2020-03-23 06:48:46 +0100
committerTristan Gingold <tgingold@free.fr>2020-03-23 06:48:46 +0100
commite1e293701bb457af7bffc2e18a890cf552599144 (patch)
tree7a0776b854dcac395b522da787441a95fe554534 /src/synth/netlists-disp_vhdl.adb
parent0cd37c83c170b5292b5ec9800013da6b4f63c1c1 (diff)
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synth: add id_inout gate to handle inout behaviour. Fir #1166
Diffstat (limited to 'src/synth/netlists-disp_vhdl.adb')
-rw-r--r--src/synth/netlists-disp_vhdl.adb13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb
index 99a87d2f4..a9086785c 100644
--- a/src/synth/netlists-disp_vhdl.adb
+++ b/src/synth/netlists-disp_vhdl.adb
@@ -757,6 +757,19 @@ package body Netlists.Disp_Vhdl is
null;
when Id_Output =>
Disp_Template (" \o0 <= \i0; -- (output)" & NL, Inst);
+ when Id_Inout =>
+ -- Gates inout are special: output 1 must be connected to an
+ -- output (with the is_inout flag set) of the module.
+ Disp_Template (" \o1 <= \i0; -- (inout - port)" & NL, Inst);
+ Disp_Template (" \o0 <= ", Inst);
+ declare
+ Inp : constant Input := Get_First_Sink (Get_Output (Inst, 1));
+ Iinst : constant Instance := Get_Input_Parent (Inp);
+ begin
+ Put_Name (Get_Output_Name (Get_Module (Iinst),
+ Get_Port_Idx (Inp)));
+ end;
+ Put ("; -- (inout - read)" & NL);
when Id_Signal =>
Disp_Template (" \o0 <= \i0; -- (signal)" & NL, Inst);
when Id_Isignal =>