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authorTristan Gingold <tgingold@free.fr>2020-03-30 08:34:43 +0200
committerTristan Gingold <tgingold@free.fr>2020-03-31 18:29:04 +0200
commit570a6b767eaedb0398072005c36313c062235488 (patch)
tree4100901cadc3c95634fdbedf8b9d57f3c04fe45f /src/synth/netlists-disp_vhdl.adb
parent182487b3c39814564a2b687d30170d42b28915f1 (diff)
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netlists-disp_vhdl: fix typos.
Diffstat (limited to 'src/synth/netlists-disp_vhdl.adb')
-rw-r--r--src/synth/netlists-disp_vhdl.adb4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb
index 8f53ae9d1..3cb08bd28 100644
--- a/src/synth/netlists-disp_vhdl.adb
+++ b/src/synth/netlists-disp_vhdl.adb
@@ -1165,7 +1165,7 @@ package body Netlists.Disp_Vhdl is
& NL, Inst, (0 => Iw - 1));
else
Disp_Template
- (" \o0 <= \i1; -- reduce or" & NL, Inst);
+ (" \o0 <= \i0; -- reduce or" & NL, Inst);
end if;
end;
when Id_Red_And =>
@@ -1178,7 +1178,7 @@ package body Netlists.Disp_Vhdl is
& NL, Inst, (0 => Iw - 1));
else
Disp_Template
- (" \o0 <= \i1; -- reduce and" & NL, Inst);
+ (" \o0 <= \i0; -- reduce and" & NL, Inst);
end if;
end;
when Id_Edge =>