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* Fix build of upf packages for openieee.Tristan Gingold2019-08-141-5/+5
* synth: also extract edge in PSL expressions.Tristan Gingold2019-08-135-19/+64
* synth: extract edge for PSL clocks.Tristan Gingold2019-08-135-29/+120
* vhdl-nodes_walk: handle iir_kind_psl_default_clock.Tristan Gingold2019-08-131-1/+2
* libghdlsynth: make it almost empty, as libghdl will be used instead.Tristan Gingold2019-08-131-8/+0
* Support for PSL assert and assume in synthesis (#892)Pepijn de Vos2019-08-132-5/+55
* libghdl: also add synthesis part. For #884Tristan Gingold2019-08-137-55/+61
* synth: build_header was replaced by a Makefile target.Tristan Gingold2019-08-131-8/+0
* libghdl: preliminary work to also support synth.Tristan Gingold2019-08-133-4/+10
* openieee: add dummy UPF package (#889)1138-4EB2019-08-113-1/+47
* vhdl: improve reprint of inertial association.Tristan Gingold2019-08-116-181/+206
* Add testcase for #885Tristan Gingold2019-08-112-0/+44
* vhdl-sem: fix minor thinko for sem_insert_anonymous_signal.Tristan Gingold2019-08-111-1/+24
* Add testcase for #886Tristan Gingold2019-08-105-0/+141
* vhdl: avoid crash on incorrect unit name.Tristan Gingold2019-08-102-6/+36
* vhdl: handle subtype indication (with range) in discrete_range.Tristan Gingold2019-08-107-63/+105
* synth: add comments.Tristan Gingold2019-08-091-1/+9
* vhdl: remove unused Get/Set_Choice_Order.Tristan Gingold2019-08-097-580/+515
* synth: add testcase from #872Tristan Gingold2019-08-082-0/+51
* synth: add testcase for aggregate target.Tristan Gingold2019-08-083-0/+56
* synth: fix crash when assignment target is an aggregate.Tristan Gingold2019-08-081-5/+7
* vhdl: remove -Whides warnings for processes without a label.Tristan Gingold2019-08-081-0/+9
* Add reproducer for tgingold/ghdlsynth-beta#26Tristan Gingold2019-08-082-0/+29
* synth: handle 1 bit integer in disp_vhdl, fix range in synth-expr.Tristan Gingold2019-08-082-4/+13
* vhdl: remove severity from cover, report and severity from assume.Tristan Gingold2019-08-0811-142/+160
* pnodes.py: be strict about comments, refactoring.Tristan Gingold2019-08-071-42/+62
* vhdl-nodes: gather PSL nodes, regenerate nodes_meta.Tristan Gingold2019-08-072-125/+91
* Add support for PSL assumptions, used in formal verification (#880)Pepijn de Vos2019-08-0736-251/+555
* Add testcase for #877Tristan Gingold2019-08-065-0/+43
* vhdl: allow discrete subtype indication for discrete_range.Tristan Gingold2019-08-065-45/+53
* Add more tests in issue613Tristan Gingold2019-08-062-0/+5
* Add a testcase for #881Tristan Gingold2019-08-063-0/+57
* vhdl: for time resolution, do not consider unit name from textio body.Tristan Gingold2019-08-063-14/+42
* Add testcase for #882Tristan Gingold2019-08-052-0/+23
* synth: improve support of vhdl08. Fix #882Tristan Gingold2019-08-052-5/+22
* synth: add asserts in synth-valuesTristan Gingold2019-08-051-0/+5
* synth: add test for previous commit.Tristan Gingold2019-08-053-2/+77
* synth: handle subtype conversions.Tristan Gingold2019-08-055-73/+154
* synth: handle signed conversions in disp_vhdl.Tristan Gingold2019-08-051-2/+6
* synth: add tests for uns/uns comparisons.Tristan Gingold2019-08-023-0/+102
* synth: preliminary support of integer literals.Tristan Gingold2019-08-022-18/+67
* synth: add a debug procedure.Tristan Gingold2019-08-022-0/+22
* synth: improve error message for multiple assignments.Tristan Gingold2019-08-021-4/+20
* synth: handle signed integer comparisons (#878)Pepijn de Vos2019-08-013-0/+43
* synth: add tests for partial assignment.Tristan Gingold2019-08-015-0/+106
* synth: handle partial assignments in a process (WIP).Tristan Gingold2019-08-011-18/+75
* synth: refactoring in inference/environment.Tristan Gingold2019-08-013-7/+13
* synth: refactor inference, add comment, strengthen check.Tristan Gingold2019-08-014-31/+62
* synth: add a dff test.Tristan Gingold2019-07-313-1/+65
* synth: refactoring in synth-inference.Tristan Gingold2019-07-311-129/+137
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