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| author | Tristan Gingold <tgingold@free.fr> | 2019-08-07 06:22:59 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-08-08 04:33:32 +0200 |
| commit | afafa2c3f856df075db309d553988ff5407c56ff (patch) | |
| tree | af74fe1f2cc750d742f3e3b61f0288726454fc96 | |
| parent | 97d3a89195c8aeb981a7f4171b939c48ec4bdfaa (diff) | |
| download | ghdl-afafa2c3f856df075db309d553988ff5407c56ff.tar.gz ghdl-afafa2c3f856df075db309d553988ff5407c56ff.tar.bz2 ghdl-afafa2c3f856df075db309d553988ff5407c56ff.zip | |
synth: handle 1 bit integer in disp_vhdl, fix range in synth-expr.
| -rw-r--r-- | src/synth/synth-disp_vhdl.adb | 15 | ||||
| -rw-r--r-- | src/synth/synth-expr.adb | 2 |
2 files changed, 13 insertions, 4 deletions
diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb index 07e9fc94e..e7d61b11c 100644 --- a/src/synth/synth-disp_vhdl.adb +++ b/src/synth/synth-disp_vhdl.adb @@ -77,9 +77,18 @@ package body Synth.Disp_Vhdl is end if; when Iir_Kind_Integer_Type_Definition => -- FIXME: signed or unsigned ? - Put (" wrap_" & Pfx & " <= std_logic_vector(to_unsigned("); - Put (Pfx & "," & Width'Image (Desc.W) & "));"); - New_Line; + Put (" wrap_" & Pfx & " <= "); + if Desc.W > 1 then + Put ("std_logic_vector("); + end if; + Put ("to_unsigned("); + Put (Pfx & "," & Width'Image (Desc.W) & ")"); + if Desc.W > 1 then + Put (")"); + elsif Desc.W = 1 then + Put ("(0)"); + end if; + Put_Line (";"); Idx := Idx + 1; when Iir_Kind_Array_Type_Definition => if Btype = Vhdl.Ieee.Std_Logic_1164.Std_Logic_Vector_Type then diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index c3f1f2589..dab693362 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -460,7 +460,7 @@ package body Synth.Expr is elsif Lo >= 0 then -- Positive. V.Is_Signed := False; - V.W := Width (Clog2 (Uns64 (Hi))); + V.W := Width (Clog2 (Uns64 (Hi) + 1)); elsif Lo = Int64'First then -- Handle possible overflow. V.Is_Signed := True; |