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authorTristan Gingold <tgingold@free.fr>2019-08-05 08:09:47 +0200
committerTristan Gingold <tgingold@free.fr>2019-08-05 08:09:47 +0200
commit7687582d7faebfb3e3c691ccd57df15106f09046 (patch)
tree284505642fbcd7ee91f42ee37e29b6e7d9a533af
parent8c7b05c79661cd140305c214de9b00747042723c (diff)
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Add testcase for #882
-rw-r--r--testsuite/synth/issue882/cpu.vhdl13
-rwxr-xr-xtestsuite/synth/issue882/testsuite.sh10
2 files changed, 23 insertions, 0 deletions
diff --git a/testsuite/synth/issue882/cpu.vhdl b/testsuite/synth/issue882/cpu.vhdl
new file mode 100644
index 000000000..28229eeb4
--- /dev/null
+++ b/testsuite/synth/issue882/cpu.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cpu is
+ port (
+ test : out std_logic_vector(7 downto 0)
+ );
+end cpu;
+
+architecture rtl of cpu is
+begin
+ test <= "00000000";
+end rtl;
diff --git a/testsuite/synth/issue882/testsuite.sh b/testsuite/synth/issue882/testsuite.sh
new file mode 100755
index 000000000..c980ae914
--- /dev/null
+++ b/testsuite/synth/issue882/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+synth cpu.vhdl -e $t > syn_cpu.vhdl
+analyze syn_cpu.vhdl
+clean
+
+echo "Test successful"