synth: add tests for partial assignment.

5 files changed, 106 insertions, 0 deletions

diff --git a/testsuite/synth/output01/output01.vhdl b/testsuite/synth/output01/output01.vhdl
new file mode 100644
index 000000000..1700bb53d
--- /dev/null
+++ b/testsuite/synth/output01/output01.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity output01 is
+  port (i : std_logic;
+        o : out std_logic_vector (1 downto 0));
+end output01;
+
+architecture behav of output01 is
+begin
+  o (0) <= i;
+  o (1) <= not i;
+end behav;
diff --git a/testsuite/synth/output01/output06.vhdl b/testsuite/synth/output01/output06.vhdl
new file mode 100644
index 000000000..0ececa86f
--- /dev/null
+++ b/testsuite/synth/output01/output06.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity output06 is
+  port (i : std_logic;
+        o : out std_logic_vector (3 downto 0));
+end output06;
+
+architecture behav of output06 is
+  signal s : std_logic_vector(3 downto 0);
+begin
+  process (i)
+  begin
+    s(0) <= i;
+    s (1) <= not i;
+    s (3) <= i;
+  end process;
+
+  s (2) <= '0';
+
+  o <= s;
+end behav;
+
diff --git a/testsuite/synth/output01/tb_output01.vhdl b/testsuite/synth/output01/tb_output01.vhdl
new file mode 100644
index 000000000..1eacded14
--- /dev/null
+++ b/testsuite/synth/output01/tb_output01.vhdl
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity tb_output01 is
+end tb_output01;
+
+architecture behav of tb_output01 is
+  signal i : std_logic;
+  signal o : std_logic_vector (1 downto 0);
+begin
+  inst: entity work.output01
+    port map (i => i, o => o);
+
+  process
+  begin
+    i <= '0';
+    wait for 1 ns;
+    assert o = "10" severity failure;
+
+    i <= '1';
+    wait for 1 ns;
+    assert o = "01" severity failure;
+
+    wait;
+  end process;
+end behav;
+
diff --git a/testsuite/synth/output01/tb_output06.vhdl b/testsuite/synth/output01/tb_output06.vhdl
new file mode 100644
index 000000000..0be4414d8
--- /dev/null
+++ b/testsuite/synth/output01/tb_output06.vhdl
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity tb_output06 is
+end tb_output06;
+
+architecture behav of tb_output06 is
+  signal i : std_logic;
+  signal o : std_logic_vector (3 downto 0);
+begin
+  inst: entity work.output06
+    port map (i => i, o => o);
+
+  process
+  begin
+    i <= '0';
+    wait for 1 ns;
+    assert o = "0010" severity failure;
+
+    i <= '1';
+    wait for 1 ns;
+    assert o = "1001" severity failure;
+
+    wait;
+  end process;
+end behav;
+
diff --git a/testsuite/synth/output01/testsuite.sh b/testsuite/synth/output01/testsuite.sh
new file mode 100755
index 000000000..063bb7111
--- /dev/null
+++ b/testsuite/synth/output01/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in output01 output06; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+done
+
+echo "Test successful"