synth: add a dff test.

3 files changed, 65 insertions, 1 deletions

diff --git a/testsuite/synth/dff01/dff13.vhdl b/testsuite/synth/dff01/dff13.vhdl
new file mode 100644
index 000000000..41039efa1
--- /dev/null
+++ b/testsuite/synth/dff01/dff13.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff13 is
+  port (q : out std_logic;
+        d : std_logic;
+        clk : std_logic);
+end dff13;
+
+architecture behav of dff13 is
+  signal m : std_logic;
+begin
+  q <= m;
+
+  --  This is a little bit weird, but it works.
+  process (clk) is
+  begin
+    if rising_edge (clk) then
+      m <= d;
+    else
+      m <= m;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff01/tb_dff13.vhdl b/testsuite/synth/dff01/tb_dff13.vhdl
new file mode 100644
index 000000000..22adb53d1
--- /dev/null
+++ b/testsuite/synth/dff01/tb_dff13.vhdl
@@ -0,0 +1,40 @@
+entity tb_dff13 is
+end tb_dff13;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff13 is
+  signal clk : std_logic;
+  signal din : std_logic;
+  signal dout : std_logic;
+begin
+  dut: entity work.dff13
+    port map (
+      q => dout,
+      d => din,
+      clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    din <= '0';
+    pulse;
+    assert dout = '0' severity failure;
+    din <= '1';
+    pulse;
+    assert dout = '1' severity failure;
+    pulse;
+    assert dout = '1' severity failure;
+    din <= '0';
+    pulse;
+    assert dout = '0' severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff01/testsuite.sh b/testsuite/synth/dff01/testsuite.sh
index 3c3bc22f2..d77be3b3d 100755
--- a/testsuite/synth/dff01/testsuite.sh
+++ b/testsuite/synth/dff01/testsuite.sh
@@ -3,7 +3,7 @@
 . ../../testenv.sh
 
 for t in dff01 dff02 dff03 dff04 dff05 dff06 dff07 dff08 dff09 \
-         dff10 dff11 dff12; do
+         dff10 dff11 dff12 dff13; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean