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* testsuite: add testsuite.sh in 001unitsTristan Gingold2019-08-141-0/+7
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* Fix build of upf packages for openieee.Tristan Gingold2019-08-141-5/+5
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* synth: also extract edge in PSL expressions.Tristan Gingold2019-08-135-19/+64
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* synth: extract edge for PSL clocks.Tristan Gingold2019-08-135-29/+120
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* vhdl-nodes_walk: handle iir_kind_psl_default_clock.Tristan Gingold2019-08-131-1/+2
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* libghdlsynth: make it almost empty, as libghdl will be used instead.Tristan Gingold2019-08-131-8/+0
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* Support for PSL assert and assume in synthesis (#892)Pepijn de Vos2019-08-132-5/+55
| | | | | | | | * initial support for PSL assert and assume * add support for true, false, and, or in psl synth * update testsuite with new psl things
* libghdl: also add synthesis part. For #884Tristan Gingold2019-08-137-55/+61
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* synth: build_header was replaced by a Makefile target.Tristan Gingold2019-08-131-8/+0
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* libghdl: preliminary work to also support synth.Tristan Gingold2019-08-133-4/+10
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* openieee: add dummy UPF package (#889)1138-4EB2019-08-113-1/+47
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* vhdl: improve reprint of inertial association.Tristan Gingold2019-08-116-181/+206
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* Add testcase for #885Tristan Gingold2019-08-112-0/+44
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* vhdl-sem: fix minor thinko for sem_insert_anonymous_signal.Tristan Gingold2019-08-111-1/+24
| | | | Fix #885
* Add testcase for #886Tristan Gingold2019-08-105-0/+141
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* vhdl: avoid crash on incorrect unit name.Tristan Gingold2019-08-102-6/+36
| | | | Fix #886
* vhdl: handle subtype indication (with range) in discrete_range.Tristan Gingold2019-08-107-63/+105
| | | | For #877
* synth: add comments.Tristan Gingold2019-08-091-1/+9
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* vhdl: remove unused Get/Set_Choice_Order.Tristan Gingold2019-08-097-580/+515
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* synth: add testcase from #872Tristan Gingold2019-08-082-0/+51
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* synth: add testcase for aggregate target.Tristan Gingold2019-08-083-0/+56
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* synth: fix crash when assignment target is an aggregate.Tristan Gingold2019-08-081-5/+7
| | | | For tgingold/ghdlsynth-beta#26
* vhdl: remove -Whides warnings for processes without a label.Tristan Gingold2019-08-081-0/+9
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* Add reproducer for tgingold/ghdlsynth-beta#26Tristan Gingold2019-08-082-0/+29
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* synth: handle 1 bit integer in disp_vhdl, fix range in synth-expr.Tristan Gingold2019-08-082-4/+13
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* vhdl: remove severity from cover, report and severity from assume.Tristan Gingold2019-08-0811-142/+160
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* pnodes.py: be strict about comments, refactoring.Tristan Gingold2019-08-071-42/+62
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* vhdl-nodes: gather PSL nodes, regenerate nodes_meta.Tristan Gingold2019-08-072-125/+91
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* Add support for PSL assumptions, used in formal verification (#880)Pepijn de Vos2019-08-0736-251/+555
| | | | | | | | | | | | | | | | | | | | | | | | | | * vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code
* Add testcase for #877Tristan Gingold2019-08-065-0/+43
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* vhdl: allow discrete subtype indication for discrete_range.Tristan Gingold2019-08-065-45/+53
| | | | For #877
* Add more tests in issue613Tristan Gingold2019-08-062-0/+5
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* Add a testcase for #881Tristan Gingold2019-08-063-0/+57
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* vhdl: for time resolution, do not consider unit name from textio body.Tristan Gingold2019-08-063-14/+42
| | | | For #881
* Add testcase for #882Tristan Gingold2019-08-052-0/+23
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* synth: improve support of vhdl08. Fix #882Tristan Gingold2019-08-052-5/+22
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* synth: add asserts in synth-valuesTristan Gingold2019-08-051-0/+5
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* synth: add test for previous commit.Tristan Gingold2019-08-053-2/+77
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* synth: handle subtype conversions.Tristan Gingold2019-08-055-73/+154
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* synth: handle signed conversions in disp_vhdl.Tristan Gingold2019-08-051-2/+6
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* synth: add tests for uns/uns comparisons.Tristan Gingold2019-08-023-0/+102
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* synth: preliminary support of integer literals.Tristan Gingold2019-08-022-18/+67
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* synth: add a debug procedure.Tristan Gingold2019-08-022-0/+22
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* synth: improve error message for multiple assignments.Tristan Gingold2019-08-021-4/+20
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* synth: handle signed integer comparisons (#878)Pepijn de Vos2019-08-013-0/+43
| | | | | | | | | | * comparisons with integer literals * display signed comparison nicely * revert literal size changes * properly display signed values
* synth: add tests for partial assignment.Tristan Gingold2019-08-015-0/+106
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* synth: handle partial assignments in a process (WIP).Tristan Gingold2019-08-011-18/+75
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* synth: refactoring in inference/environment.Tristan Gingold2019-08-013-7/+13
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* synth: refactor inference, add comment, strengthen check.Tristan Gingold2019-08-014-31/+62
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* synth: add a dff test.Tristan Gingold2019-07-313-1/+65
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