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authorTristan Gingold <tgingold@free.fr>2019-10-08 18:43:52 +0200
committerTristan Gingold <tgingold@free.fr>2019-10-08 18:43:52 +0200
commit0a3ca95575c7c5d3c153ec2de271613c228124a8 (patch)
tree43234189433a515b75591e9ce814236cd633a09e /testsuite/synth
parent32272b4c7e384e0f54a8216ee14db5b8554f9793 (diff)
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testsuite/synth: add a test for previous commit.
Diffstat (limited to 'testsuite/synth')
-rw-r--r--testsuite/synth/dispout01/pkg_rec09.vhdl8
-rw-r--r--testsuite/synth/dispout01/pkg_rec10.vhdl8
-rw-r--r--testsuite/synth/dispout01/rec09.vhdl13
-rw-r--r--testsuite/synth/dispout01/rec10.vhdl13
-rw-r--r--testsuite/synth/dispout01/tb_rec09.vhdl27
-rw-r--r--testsuite/synth/dispout01/tb_rec10.vhdl27
-rwxr-xr-xtestsuite/synth/dispout01/testsuite.sh2
7 files changed, 97 insertions, 1 deletions
diff --git a/testsuite/synth/dispout01/pkg_rec09.vhdl b/testsuite/synth/dispout01/pkg_rec09.vhdl
new file mode 100644
index 000000000..948adcb9b
--- /dev/null
+++ b/testsuite/synth/dispout01/pkg_rec09.vhdl
@@ -0,0 +1,8 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package rec09_pkg is
+ type myrec is record
+ b : std_logic;
+ end record;
+end rec09_pkg;
diff --git a/testsuite/synth/dispout01/pkg_rec10.vhdl b/testsuite/synth/dispout01/pkg_rec10.vhdl
new file mode 100644
index 000000000..53fefc73b
--- /dev/null
+++ b/testsuite/synth/dispout01/pkg_rec10.vhdl
@@ -0,0 +1,8 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package rec10_pkg is
+ type myrec is record
+ b : std_logic_vector (1 to 1);
+ end record;
+end rec10_pkg;
diff --git a/testsuite/synth/dispout01/rec09.vhdl b/testsuite/synth/dispout01/rec09.vhdl
new file mode 100644
index 000000000..f009a7026
--- /dev/null
+++ b/testsuite/synth/dispout01/rec09.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use work.rec09_pkg.all;
+
+entity rec09 is
+ port (inp : std_logic;
+ o : out myrec);
+end rec09;
+
+architecture behav of rec09 is
+begin
+ o.b <= not inp;
+end behav;
diff --git a/testsuite/synth/dispout01/rec10.vhdl b/testsuite/synth/dispout01/rec10.vhdl
new file mode 100644
index 000000000..2e53bac22
--- /dev/null
+++ b/testsuite/synth/dispout01/rec10.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use work.rec10_pkg.all;
+
+entity rec10 is
+ port (inp : std_logic;
+ o : out myrec);
+end rec10;
+
+architecture behav of rec10 is
+begin
+ o.b (1) <= not inp;
+end behav;
diff --git a/testsuite/synth/dispout01/tb_rec09.vhdl b/testsuite/synth/dispout01/tb_rec09.vhdl
new file mode 100644
index 000000000..beb53143e
--- /dev/null
+++ b/testsuite/synth/dispout01/tb_rec09.vhdl
@@ -0,0 +1,27 @@
+entity tb_rec09 is
+end tb_rec09;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.rec09_pkg.all;
+
+architecture behav of tb_rec09 is
+ signal inp : std_logic;
+ signal r : myrec;
+begin
+ dut: entity work.rec09
+ port map (inp => inp, o => r);
+
+ process
+ begin
+ inp <= '1';
+ wait for 1 ns;
+ assert r.b = '0' severity failure;
+
+ inp <= '0';
+ wait for 1 ns;
+ assert r.b = '1' severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/dispout01/tb_rec10.vhdl b/testsuite/synth/dispout01/tb_rec10.vhdl
new file mode 100644
index 000000000..690dd055c
--- /dev/null
+++ b/testsuite/synth/dispout01/tb_rec10.vhdl
@@ -0,0 +1,27 @@
+entity tb_rec10 is
+end tb_rec10;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.rec10_pkg.all;
+
+architecture behav of tb_rec10 is
+ signal inp : std_logic;
+ signal r : myrec;
+begin
+ dut: entity work.rec10
+ port map (inp => inp, o => r);
+
+ process
+ begin
+ inp <= '1';
+ wait for 1 ns;
+ assert r.b (1) = '0' severity failure;
+
+ inp <= '0';
+ wait for 1 ns;
+ assert r.b (1) = '1' severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/dispout01/testsuite.sh b/testsuite/synth/dispout01/testsuite.sh
index 94d07f0e2..3e0e54fe5 100755
--- a/testsuite/synth/dispout01/testsuite.sh
+++ b/testsuite/synth/dispout01/testsuite.sh
@@ -2,7 +2,7 @@
. ../../testenv.sh
-for t in rec01 rec02 rec03 rec04 rec05 rec06 rec07 rec08; do
+for t in rec01 rec02 rec03 rec04 rec05 rec06 rec07 rec08 rec09 rec10; do
analyze pkg_$t.vhdl $t.vhdl tb_$t.vhdl
elab_simulate tb_$t
clean