Merge branch 'master' into mike

271 files changed, 82091 insertions, 18115 deletions

diff --git a/os/common/ext/CMSIS/KINETIS/k20xx.h b/os/common/ext/CMSIS/KINETIS/k20xx.h
index 38855aa..8218b3c 100644
--- a/os/common/ext/CMSIS/KINETIS/k20xx.h
+++ b/os/common/ext/CMSIS/KINETIS/k20xx.h
@@ -2242,7 +2242,7 @@ typedef struct
 /******** Bits definition for USBx_CTL register *****************/
 #define USBx_CTL_JSTATE              ((uint8_t)0x80) /*!< Live USB differential receiver JSTATE signal */
 #define USBx_CTL_SE0                 ((uint8_t)0x40) /*!< Live USB single ended zero signal */
-#define USBx_CTL_TXSUSPENDTOKENBUS   ((uint8_t)0x20) /*!<  */
+#define USBx_CTL_TXSUSPENDTOKENBUSY  ((uint8_t)0x20) /*!<  */
 #define USBx_CTL_RESET               ((uint8_t)0x10) /*!< Generates an USB reset signal (host mode) */
 #define USBx_CTL_HOSTMODEEN          ((uint8_t)0x08) /*!< Operate in Host mode */
 #define USBx_CTL_RESUME              ((uint8_t)0x04) /*!< Executes resume signaling */
diff --git a/os/common/ext/MSP430/inc/in430.h b/os/common/ext/MSP430/inc/in430.h
new file mode 100644
index 0000000..f907209
--- /dev/null
+++ b/os/common/ext/MSP430/inc/in430.h
@@ -0,0 +1,343 @@
+/*******************************************************************************
+ *  in430.h -
+ *
+ *  Copyright (C) 2003-2016 Texas Instruments Incorporated - http://www.ti.com/ 
+ * 
+ *  Redistribution and use in source and binary forms, with or without 
+ *  modification, are permitted provided that the following conditions 
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the   
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************/
+
+#ifndef __IN430_H__
+#define __IN430_H__
+
+/* Definitions for projects using the GNU C/C++ compiler */
+#if !defined(__ASSEMBLER__)
+
+/* Definitions of things which are intrinsics with IAR and CCS, but which don't 
+   appear to be intrinsics with the RedHat GCC compiler */
+
+/* The data type used to hold interrupt state */
+typedef unsigned int __istate_t;
+
+#define _no_operation()                     __asm__ __volatile__ ("nop")
+
+#define _get_interrupt_state() \
+({ \
+	unsigned int __x; \
+	__asm__ __volatile__( \
+	"mov SR, %0" \
+	: "=r" ((unsigned int) __x) \
+	:); \
+	__x; \
+})
+
+#if defined(__MSP430_HAS_MSP430XV2_CPU__)  || defined(__MSP430_HAS_MSP430X_CPU__)
+#define _set_interrupt_state(x) \
+({ \
+    __asm__ __volatile__ ("mov %0, SR { nop" \
+        : : "ri"((unsigned int) x) \
+    );\
+})
+
+#define _enable_interrupts()                __asm__ __volatile__ ("nop { eint { nop")
+
+#define _bis_SR_register(x) \
+    __asm__ __volatile__ ("bis.w %0, SR { nop" \
+        : : "ri"((unsigned int) x) \
+    )
+#else
+
+#define _set_interrupt_state(x) \
+({ \
+    __asm__ __volatile__ ("mov %0, SR" \
+        : : "ri"((unsigned int) x) \
+    );\
+})
+
+#define _enable_interrupts()                __asm__ __volatile__ ("eint { nop")
+
+#define _bis_SR_register(x) \
+    __asm__ __volatile__ ("bis.w %0, SR" \
+        : : "ri"((unsigned int) x) \
+    )
+
+#endif
+
+#define _disable_interrupts()               __asm__ __volatile__ ("dint { nop")
+
+#define _bic_SR_register(x) \
+    __asm__ __volatile__ ("bic.w %0, SR { nop" \
+        : : "ri"((unsigned int) x) \
+   )
+
+#define _get_SR_register() \
+({ \
+	unsigned int __x; \
+	__asm__ __volatile__( \
+	"mov SR, %0" \
+	: "=r" ((unsigned int) __x) \
+	:); \
+	__x; \
+})
+
+#define _swap_bytes(x) \
+({ \
+        unsigned int __dst = x; \
+	__asm__ __volatile__( \
+	"swpb %0" \
+	: "+r" ((unsigned int) __dst) \
+	:); \
+	__dst; \
+})
+
+/* Alternative names for GCC built-ins */
+#define _bic_SR_register_on_exit(x)        __bic_SR_register_on_exit(x)
+#define _bis_SR_register_on_exit(x)        __bis_SR_register_on_exit(x)
+
+/* Additional intrinsics provided for IAR/CCS compatibility */
+#define _bcd_add_short(x,y) \
+({ \
+        unsigned short __z = ((unsigned short) y); \
+	__asm__ __volatile__( \
+	"clrc \n\t" \
+	"dadd.w %1, %0" \
+	: "+r" ((unsigned short) __z) \
+	: "ri" ((unsigned short) x) \
+	); \
+	__z; \
+})
+
+#define __bcd_add_short(x,y) _bcd_add_short(x,y)
+
+#define _bcd_add_long(x,y) \
+({ \
+        unsigned long __z = ((unsigned long) y);	\
+	__asm__ __volatile__( \
+	"clrc \n\t" \
+	"dadd.w %L1, %L0 \n\t" \
+	"dadd.w %H1, %H0" \
+	: "+r" ((unsigned long) __z) \
+	: "ri" ((unsigned long) x) \
+	); \
+	__z; \
+ })
+
+#define __bcd_add_long(x,y) _bcd_add_long(x,y)
+
+#define _get_SP_register() \
+({ \
+	unsigned int __x; \
+	__asm__ __volatile__( \
+	"mov SP, %0" \
+	: "=r" ((unsigned int) __x) \
+	:); \
+	__x; \
+})
+
+#define __get_SP_register() _get_SP_register()
+
+#define _set_SP_register(x) \
+({ \
+        __asm__ __volatile__ ("mov %0, SP" \
+        : : "ri"((unsigned int) x) \
+        );\
+})
+
+#define __set_SP_register(x) _set_SP_register(x)
+
+#define _data16_write_addr(addr,src) \
+({ \
+        unsigned long __src = src; \
+        __asm__ __volatile__ ( \
+	"movx.a %1, 0(%0)" \
+	: : "r"((unsigned int) addr), "m"((unsigned long) __src) \
+	); \
+})
+
+#define __data16_write_addr(addr,src) _data16_write_addr(addr,src)
+
+#define _data16_read_addr(addr) \
+({ \
+         unsigned long __dst; \
+         __asm__ __volatile__ ( \
+	 "movx.a @%1, %0" \
+	 : "=m"((unsigned long) __dst) \
+	 : "r"((unsigned int) addr) \
+	 ); \
+         __dst; \
+})
+
+#define __data16_read_addr(addr) _data16_read_addr(addr)
+
+#define _data20_write_char(addr,src) \
+({ \
+        unsigned int __tmp; \
+	unsigned long __addr = addr; \
+        __asm__ __volatile__ ( \
+	"movx.a %1, %0 \n\t" \
+	"mov.b  %2, 0(%0)" \
+	: "=&r"((unsigned int) __tmp) \
+        : "m"((unsigned long) __addr), "ri"((char) src)	 \
+	); \
+})
+
+#define __data20_write_char(addr,src) _data20_write_char(addr,src)
+
+#define _data20_read_char(addr) \
+({ \
+        char __dst; \
+        unsigned int __tmp; \
+	unsigned long __addr = addr; \
+	__asm__ __volatile__ ( \
+	"movx.a %2, %1 \n\t" \
+	"mov.b 0(%1), %0" \
+	: "=r"((char) __dst), "=&r"((unsigned int) __tmp) \
+	: "m"((unsigned long) __addr) \
+	); \
+	__dst ; \
+})
+
+#define __data20_read_char(addr) _data20_read_char(addr)
+
+#define _data20_write_short(addr,src) \
+({ \
+        unsigned int __tmp; \
+	unsigned long __addr = addr; \
+        __asm__ __volatile__ ( \
+	"movx.a %1, %0 \n\t" \
+	"mov.w  %2, 0(%0)" \
+	: "=&r"((unsigned int) __tmp) \
+        : "m"((unsigned long) __addr), "ri"((short) src) \
+	); \
+})
+
+#define __data20_write_short(addr,src) _data20_write_short(addr,src)
+
+#define _data20_read_short(addr) \
+({ \
+        short __dst; \
+        unsigned int __tmp; \
+	unsigned long __addr = addr; \
+	__asm__ __volatile__ ( \
+	"movx.a %2, %1 \n\t" \
+	"mov.w 0(%1), %0" \
+	: "=r"((short) __dst), "=&r"((unsigned int) __tmp) \
+	: "m"((unsigned long) __addr) \
+	); \
+	__dst ; \
+})
+
+#define __data20_read_short(addr) _data20_read_short(addr)
+
+#define _data20_write_long(addr,src) \
+({ \
+        unsigned int __tmp; \
+	unsigned long __addr = addr; \
+        __asm__ __volatile__ ( \
+	"movx.a %1, %0 \n\t" \
+	"mov.w  %L2, 0(%0) \n\t" \
+	"mov.w  %H2, 2(%0)" \
+	: "=&r"((unsigned int) __tmp) \
+        : "m"((unsigned long) __addr), "ri"((long) src) \
+	); \
+})
+
+#define __data20_write_long(addr,src) _data20_write_long(addr,src)
+
+#define _data20_read_long(addr) \
+({ \
+        long __dst; \
+        unsigned int __tmp; \
+	unsigned long __addr = addr; \
+	__asm__ __volatile__ ( \
+	"movx.a %2, %1 \n\t" \
+	"mov.w  0(%1), %L0 \n\t" \
+	"mov.w  2(%1), %H0" \
+	: "=r"((long) __dst), "=&r"((unsigned int) __tmp) \
+	: "m"((unsigned long) __addr) \
+	); \
+	__dst ; \
+})
+
+#define __data20_read_long(addr) _data20_read_long(addr)
+
+#define _low_power_mode_0() _bis_SR_register(0x18)
+#define _low_power_mode_1() _bis_SR_register(0x58)
+#define _low_power_mode_2() _bis_SR_register(0x98)
+#define _low_power_mode_3() _bis_SR_register(0xD8)
+#define _low_power_mode_4() _bis_SR_register(0xF8)
+#define _low_power_mode_off_on_exit() _bic_SR_register_on_exit(0xF0)
+
+#define __low_power_mode_0() _low_power_mode_0()
+#define __low_power_mode_1() _low_power_mode_1()
+#define __low_power_mode_2() _low_power_mode_2()
+#define __low_power_mode_3() _low_power_mode_3()
+#define __low_power_mode_4() _low_power_mode_4()
+#define __low_power_mode_off_on_exit() _low_power_mode_off_on_exit()
+
+#define _even_in_range(x,y) (x)
+#define __even_in_range(x,y) _even_in_range(x,y)
+
+/* Define some alternative names for the intrinsics, which have been used 
+   in the various versions of IAR and GCC */
+#define __no_operation()                    _no_operation()
+
+#define __get_interrupt_state()             _get_interrupt_state()
+#define __set_interrupt_state(x)            _set_interrupt_state(x)
+#define __enable_interrupt()                _enable_interrupts()
+#define __disable_interrupt()               _disable_interrupts()
+
+#define __bic_SR_register(x)                _bic_SR_register(x)
+#define __bis_SR_register(x)                _bis_SR_register(x)
+#define __get_SR_register()                 _get_SR_register()
+
+#define __swap_bytes(x)                     _swap_bytes(x)
+
+#define __nop()                             _no_operation()
+
+#define __eint()                            _enable_interrupts()
+#define __dint()                            _disable_interrupts()
+
+#define _NOP()                              _no_operation()
+#define _EINT()                             _enable_interrupts()
+#define _DINT()                             _disable_interrupts()
+
+#define _BIC_SR(x)                          _bic_SR_register(x)
+#define _BIC_SR_IRQ(x)                      _bic_SR_register_on_exit(x)
+#define _BIS_SR(x)                          _bis_SR_register(x)
+#define _BIS_SR_IRQ(x)                      _bis_SR_register_on_exit(x)
+#define _BIS_NMI_IE1(x)                     _bis_nmi_ie1(x)
+
+#define _SWAP_BYTES(x)                      _swap_bytes(x)
+
+#define __no_init    __attribute__ ((section (".noinit")))
+
+#endif /* !defined _GNU_ASSEMBLER_ */
+
+#endif /* __IN430_H__ */
diff --git a/os/common/ext/MSP430/inc/iomacros.h b/os/common/ext/MSP430/inc/iomacros.h
new file mode 100644
index 0000000..fc0e76d
--- /dev/null
+++ b/os/common/ext/MSP430/inc/iomacros.h
@@ -0,0 +1,85 @@
+/*******************************************************************************
+ *  iomacros.h -
+ *
+ *  Copyright (C) 2003-2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************/
+
+#if !defined(_IOMACROS_H_)
+#define _IOMACROS_H_
+
+
+#if defined(__ASSEMBLER__)
+
+/* Definitions for assembly compilation using the GNU assembler */
+#define sfrb(x,x_) x=x_
+#define sfrw(x,x_) x=x_
+#define sfra(x,x_) x=x_
+#define sfrl(x,x_) x=x_
+
+#define const_sfrb(x,x_) x=x_
+#define const_sfrw(x,x_) x=x_
+#define const_sfra(x,x_) x=x_
+#define const_sfrl(x,x_) x=x_
+
+#define sfr_b(x)
+#define sfr_w(x)
+#define sfr_a(x)
+#define sfr_l(x)
+
+#else
+
+#define sfr_b(x) extern volatile unsigned char x
+#define sfr_w(x) extern volatile unsigned int x
+#define sfr_a(x) extern volatile unsigned long int x
+#define sfr_l(x) extern volatile unsigned long int x
+
+#define sfrb_(x,x_) extern volatile unsigned char x __asm__(#x_)
+#define sfrw_(x,x_) extern volatile unsigned int x __asm__(#x_)
+#define sfra_(x,x_) extern volatile unsigned long int x __asm__(#x_)
+#define sfrl_(x,x_) extern volatile unsigned long int x __asm__(#x_)
+
+#define sfrb(x,x_) sfrb_(x,x_)
+#define sfrw(x,x_) sfrw_(x,x_)
+#define sfra(x,x_) sfra_(x,x_)
+#define sfrl(x,x_) sfrl_(x,x_)
+
+#define const_sfrb(x,x_) const sfrb_(x,x_)
+#define const_sfrw(x,x_) const sfrw_(x,x_)
+#define const_sfra(x,x_) const sfra_(x,x_)
+#define const_sfrl(x,x_) const sfrl_(x,x_)
+
+#define __interrupt __attribute__((__interrupt__))
+#define __interrupt_vec(vec) __attribute__((interrupt(vec)))
+
+#endif /* defined(__ASSEMBLER__) */
+
+#endif /* _IOMACROS_H_ */
diff --git a/os/common/ext/MSP430/inc/msp430.h b/os/common/ext/MSP430/inc/msp430.h
new file mode 100755
index 0000000..40f8759
--- /dev/null
+++ b/os/common/ext/MSP430/inc/msp430.h
@@ -0,0 +1,1847 @@
+/*******************************************************************
+*                                                                  *
+* This file is a generic include file controlled by                *
+* compiler/assembler IDE generated defines                         *
+*                                                                  *
+*******************************************************************/
+
+#ifndef __msp430
+#define __msp430
+
+
+#if defined (__MSP430C111__)
+#include "msp430c111.h"
+
+#elif defined (__MSP430C1111__)
+#include "msp430c1111.h"
+
+#elif defined (__MSP430C112__)
+#include "msp430c112.h"
+
+#elif defined (__MSP430C1121__)
+#include "msp430c1121.h"
+
+#elif defined (__MSP430C1331__)
+#include "msp430c1331.h"
+
+#elif defined (__MSP430C1351__)
+#include "msp430c1351.h"
+
+#elif defined (__MSP430C311S__)
+#include "msp430c311s.h"
+
+#elif defined (__MSP430C312__)
+#include "msp430c312.h"
+
+#elif defined (__MSP430C313__)
+#include "msp430c313.h"
+
+#elif defined (__MSP430C314__)
+#include "msp430c314.h"
+
+#elif defined (__MSP430C315__)
+#include "msp430c315.h"
+
+#elif defined (__MSP430C323__)
+#include "msp430c323.h"
+
+#elif defined (__MSP430C325__)
+#include "msp430c325.h"
+
+#elif defined (__MSP430C336__)
+#include "msp430c336.h"
+
+#elif defined (__MSP430C337__)
+#include "msp430c337.h"
+
+#elif defined (__MSP430C412__)
+#include "msp430c412.h"
+
+#elif defined (__MSP430C413__)
+#include "msp430c413.h"
+
+#elif defined (__MSP430CG4616__)
+#include "msp430cg4616.h"
+
+#elif defined (__MSP430CG4617__)
+#include "msp430cg4617.h"
+
+#elif defined (__MSP430CG4618__)
+#include "msp430cg4618.h"
+
+#elif defined (__MSP430CG4619__)
+#include "msp430cg4619.h"
+
+#elif defined (__MSP430E112__)
+#include "msp430e112.h"
+
+#elif defined (__MSP430E313__)
+#include "msp430e313.h"
+
+#elif defined (__MSP430E315__)
+#include "msp430e315.h"
+
+#elif defined (__MSP430E325__)
+#include "msp430e325.h"
+
+#elif defined (__MSP430E337__)
+#include "msp430e337.h"
+
+#elif defined (__MSP430F110__)
+#include "msp430f110.h"
+
+#elif defined (__MSP430F1101__)
+#include "msp430f1101.h"
+
+#elif defined (__MSP430F1101A__)
+#include "msp430f1101a.h"
+
+#elif defined (__MSP430F1111__)
+#include "msp430f1111.h"
+
+#elif defined (__MSP430F1111A__)
+#include "msp430f1111a.h"
+
+#elif defined (__MSP430F112__)
+#include "msp430f112.h"
+
+#elif defined (__MSP430F1121__)
+#include "msp430f1121.h"
+
+#elif defined (__MSP430F1121A__)
+#include "msp430f1121a.h"
+
+#elif defined (__MSP430F1122__)
+#include "msp430f1122.h"
+
+#elif defined (__MSP430F1132__)
+#include "msp430f1132.h"
+
+#elif defined (__MSP430F122__)
+#include "msp430f122.h"
+
+#elif defined (__MSP430F1222__)
+#include "msp430f1222.h"
+
+#elif defined (__MSP430F123__)
+#include "msp430f123.h"
+
+#elif defined (__MSP430F1232__)
+#include "msp430f1232.h"
+
+#elif defined (__MSP430F133__)
+#include "msp430f133.h"
+
+#elif defined (__MSP430F135__)
+#include "msp430f135.h"
+
+#elif defined (__MSP430F147__)
+#include "msp430f147.h"
+
+#elif defined (__MSP430F148__)
+#include "msp430f148.h"
+
+#elif defined (__MSP430F149__)
+#include "msp430f149.h"
+
+#elif defined (__MSP430F1471__)
+#include "msp430f1471.h"
+
+#elif defined (__MSP430F1481__)
+#include "msp430f1481.h"
+
+#elif defined (__MSP430F1491__)
+#include "msp430f1491.h"
+
+#elif defined (__MSP430F155__)
+#include "msp430f155.h"
+
+#elif defined (__MSP430F156__)
+#include "msp430f156.h"
+
+#elif defined (__MSP430F157__)
+#include "msp430f157.h"
+
+#elif defined (__MSP430F167__)
+#include "msp430f167.h"
+
+#elif defined (__MSP430F168__)
+#include "msp430f168.h"
+
+#elif defined (__MSP430F169__)
+#include "msp430f169.h"
+
+#elif defined (__MSP430F1610__)
+#include "msp430f1610.h"
+
+#elif defined (__MSP430F1611__)
+#include "msp430f1611.h"
+
+#elif defined (__MSP430F1612__)
+#include "msp430f1612.h"
+
+#elif defined (__MSP430F2001__)
+#include "msp430f2001.h"
+
+#elif defined (__MSP430F2011__)
+#include "msp430f2011.h"
+
+#elif defined (__MSP430F2002__)
+#include "msp430f2002.h"
+
+#elif defined (__MSP430F2012__)
+#include "msp430f2012.h"
+
+#elif defined (__MSP430F2003__)
+#include "msp430f2003.h"
+
+#elif defined (__MSP430F2013__)
+#include "msp430f2013.h"
+
+#elif defined (__MSP430F2101__)
+#include "msp430f2101.h"
+
+#elif defined (__MSP430F2111__)
+#include "msp430f2111.h"
+
+#elif defined (__MSP430F2121__)
+#include "msp430f2121.h"
+
+#elif defined (__MSP430F2131__)
+#include "msp430f2131.h"
+
+#elif defined (__MSP430F2112__)
+#include "msp430f2112.h"
+
+#elif defined (__MSP430F2122__)
+#include "msp430f2122.h"
+
+#elif defined (__MSP430F2132__)
+#include "msp430f2132.h"
+
+#elif defined (__MSP430F2232__)
+#include "msp430f2232.h"
+
+#elif defined (__MSP430F2252__)
+#include "msp430f2252.h"
+
+#elif defined (__MSP430F2272__)
+#include "msp430f2272.h"
+
+#elif defined (__MSP430F2234__)
+#include "msp430f2234.h"
+
+#elif defined (__MSP430F2254__)
+#include "msp430f2254.h"
+
+#elif defined (__MSP430F2274__)
+#include "msp430f2274.h"
+
+#elif defined (__MSP430F2330__)
+#include "msp430f2330.h"
+
+#elif defined (__MSP430F2350__)
+#include "msp430f2350.h"
+
+#elif defined (__MSP430F2370__)
+#include "msp430f2370.h"
+
+#elif defined (__MSP430F233__)
+#include "msp430f233.h"
+
+#elif defined (__MSP430F235__)
+#include "msp430f235.h"
+
+#elif defined (__MSP430F247__)
+#include "msp430f247.h"
+
+#elif defined (__MSP430F248__)
+#include "msp430f248.h"
+
+#elif defined (__MSP430F249__)
+#include "msp430f249.h"
+
+#elif defined (__MSP430F2410__)
+#include "msp430f2410.h"
+
+#elif defined (__MSP430F2471__)
+#include "msp430f2471.h"
+
+#elif defined (__MSP430F2481__)
+#include "msp430f2481.h"
+
+#elif defined (__MSP430F2491__)
+#include "msp430f2491.h"
+
+#elif defined (__MSP430F2416__)
+#include "msp430f2416.h"
+
+#elif defined (__MSP430F2417__)
+#include "msp430f2417.h"
+
+#elif defined (__MSP430F2418__)
+#include "msp430f2418.h"
+
+#elif defined (__MSP430F2419__)
+#include "msp430f2419.h"
+
+#elif defined (__MSP430F2616__)
+#include "msp430f2616.h"
+
+#elif defined (__MSP430F2617__)
+#include "msp430f2617.h"
+
+#elif defined (__MSP430F2618__)
+#include "msp430f2618.h"
+
+#elif defined (__MSP430F2619__)
+#include "msp430f2619.h"
+
+#elif defined (__MSP430F412__)
+#include "msp430f412.h"
+
+#elif defined (__MSP430F413__)
+#include "msp430f413.h"
+
+#elif defined (__MSP430F415__)
+#include "msp430f415.h"
+
+#elif defined (__MSP430F417__)
+#include "msp430f417.h"
+
+#elif defined (__MSP430F4132__)
+#include "msp430f4132.h"
+
+#elif defined (__MSP430F4152__)
+#include "msp430f4152.h"
+
+#elif defined (__MSP430F423__)
+#include "msp430f423.h"
+
+#elif defined (__MSP430F425__)
+#include "msp430f425.h"
+
+#elif defined (__MSP430F427__)
+#include "msp430f427.h"
+
+#elif defined (__MSP430F423A__)
+#include "msp430f423a.h"
+
+#elif defined (__MSP430F425A__)
+#include "msp430f425a.h"
+
+#elif defined (__MSP430F427A__)
+#include "msp430f427a.h"
+
+#elif defined (__MSP430F435__)
+#include "msp430f435.h"
+
+#elif defined (__MSP430F436__)
+#include "msp430f436.h"
+
+#elif defined (__MSP430F437__)
+#include "msp430f437.h"
+
+#elif defined (__MSP430F4351__)
+#include "msp430f4351.h"
+
+#elif defined (__MSP430F4361__)
+#include "msp430f4361.h"
+
+#elif defined (__MSP430F4371__)
+#include "msp430f4371.h"
+
+#elif defined (__MSP430F4481__)
+#include "msp430f4481.h"
+
+#elif defined (__MSP430F4491__)
+#include "msp430f4491.h"
+
+#elif defined (__MSP430F447__)
+#include "msp430f447.h"
+
+#elif defined (__MSP430F448__)
+#include "msp430f448.h"
+
+#elif defined (__MSP430F449__)
+#include "msp430f449.h"
+
+#elif defined (__MSP430FE423__)
+#include "msp430fe423.h"
+
+#elif defined (__MSP430FE425__)
+#include "msp430fe425.h"
+
+#elif defined (__MSP430FE427__)
+#include "msp430fe427.h"
+
+#elif defined (__MSP430FE423A__)
+#include "msp430fe423a.h"
+
+#elif defined (__MSP430FE425A__)
+#include "msp430fe425a.h"
+
+#elif defined (__MSP430FE427A__)
+#include "msp430fe427a.h"
+
+#elif defined (__MSP430FE4232__)
+#include "msp430fe4232.h"
+
+#elif defined (__MSP430FE4242__)
+#include "msp430fe4242.h"
+
+#elif defined (__MSP430FE4252__)
+#include "msp430fe4252.h"
+
+#elif defined (__MSP430FE4272__)
+#include "msp430fe4272.h"
+
+#elif defined (__MSP430F4783__)
+#include "msp430f4783.h"
+
+#elif defined (__MSP430F4793__)
+#include "msp430f4793.h"
+
+#elif defined (__MSP430F4784__)
+#include "msp430f4784.h"
+
+#elif defined (__MSP430F4794__)
+#include "msp430f4794.h"
+
+#elif defined (__MSP430F47126__)
+#include "msp430f47126.h"
+
+#elif defined (__MSP430F47127__)
+#include "msp430f47127.h"
+
+#elif defined (__MSP430F47163__)
+#include "msp430f47163.h"
+
+#elif defined (__MSP430F47173__)
+#include "msp430f47173.h"
+
+#elif defined (__MSP430F47183__)
+#include "msp430f47183.h"
+
+#elif defined (__MSP430F47193__)
+#include "msp430f47193.h"
+
+#elif defined (__MSP430F47166__)
+#include "msp430f47166.h"
+
+#elif defined (__MSP430F47176__)
+#include "msp430f47176.h"
+
+#elif defined (__MSP430F47186__)
+#include "msp430f47186.h"
+
+#elif defined (__MSP430F47196__)
+#include "msp430f47196.h"
+
+#elif defined (__MSP430F47167__)
+#include "msp430f47167.h"
+
+#elif defined (__MSP430F47177__)
+#include "msp430f47177.h"
+
+#elif defined (__MSP430F47187__)
+#include "msp430f47187.h"
+
+#elif defined (__MSP430F47197__)
+#include "msp430f47197.h"
+
+#elif defined (__MSP430F4250__)
+#include "msp430f4250.h"
+
+#elif defined (__MSP430F4260__)
+#include "msp430f4260.h"
+
+#elif defined (__MSP430F4270__)
+#include "msp430f4270.h"
+
+#elif defined (__MSP430FG4250__)
+#include "msp430fg4250.h"
+
+#elif defined (__MSP430FG4260__)
+#include "msp430fg4260.h"
+
+#elif defined (__MSP430FG4270__)
+#include "msp430fg4270.h"
+
+#elif defined (__MSP430FW423__)
+#include "msp430fw423.h"
+
+#elif defined (__MSP430FW425__)
+#include "msp430fw425.h"
+
+#elif defined (__MSP430FW427__)
+#include "msp430fw427.h"
+
+#elif defined (__MSP430FW428__)
+#include "msp430fw428.h"
+
+#elif defined (__MSP430FW429__)
+#include "msp430fw429.h"
+
+#elif defined (__MSP430FG437__)
+#include "msp430fg437.h"
+
+#elif defined (__MSP430FG438__)
+#include "msp430fg438.h"
+
+#elif defined (__MSP430FG439__)
+#include "msp430fg439.h"
+
+#elif defined (__MSP430F438__)
+#include "msp430f438.h"
+
+#elif defined (__MSP430F439__)
+#include "msp430f439.h"
+
+#elif defined (__MSP430F477__)
+#include "msp430f477.h"
+
+#elif defined (__MSP430F478__)
+#include "msp430f478.h"
+
+#elif defined (__MSP430F479__)
+#include "msp430f479.h"
+
+#elif defined (__MSP430FG477__)
+#include "msp430fg477.h"
+
+#elif defined (__MSP430FG478__)
+#include "msp430fg478.h"
+
+#elif defined (__MSP430FG479__)
+#include "msp430fg479.h"
+
+#elif defined (__MSP430F46161__)
+#include "msp430f46161.h"
+
+#elif defined (__MSP430F46171__)
+#include "msp430f46171.h"
+
+#elif defined (__MSP430F46181__)
+#include "msp430f46181.h"
+
+#elif defined (__MSP430F46191__)
+#include "msp430f46191.h"
+
+#elif defined (__MSP430F4616__)
+#include "msp430f4616.h"
+
+#elif defined (__MSP430F4617__)
+#include "msp430f4617.h"
+
+#elif defined (__MSP430F4618__)
+#include "msp430f4618.h"
+
+#elif defined (__MSP430F4619__)
+#include "msp430f4619.h"
+
+#elif defined (__MSP430FG4616__)
+#include "msp430fg4616.h"
+
+#elif defined (__MSP430FG4617__)
+#include "msp430fg4617.h"
+
+#elif defined (__MSP430FG4618__)
+#include "msp430fg4618.h"
+
+#elif defined (__MSP430FG4619__)
+#include "msp430fg4619.h"
+
+#elif defined (__MSP430F5418__)
+#include "msp430f5418.h"
+
+#elif defined (__MSP430F5419__)
+#include "msp430f5419.h"
+
+#elif defined (__MSP430F5435__)
+#include "msp430f5435.h"
+
+#elif defined (__MSP430F5436__)
+#include "msp430f5436.h"
+
+#elif defined (__MSP430F5437__)
+#include "msp430f5437.h"
+
+#elif defined (__MSP430F5438__)
+#include "msp430f5438.h"
+
+#elif defined (__MSP430F5418A__)
+#include "msp430f5418a.h"
+
+#elif defined (__MSP430F5419A__)
+#include "msp430f5419a.h"
+
+#elif defined (__MSP430F5435A__)
+#include "msp430f5435a.h"
+
+#elif defined (__MSP430F5436A__)
+#include "msp430f5436a.h"
+
+#elif defined (__MSP430F5437A__)
+#include "msp430f5437a.h"
+
+#elif defined (__MSP430F5438A__)
+#include "msp430f5438a.h"
+
+#elif defined (__MSP430F5212__)
+#include "msp430f5212.h"
+
+#elif defined (__MSP430F5213__)
+#include "msp430f5213.h"
+
+#elif defined (__MSP430F5214__)
+#include "msp430f5214.h"
+
+#elif defined (__MSP430F5217__)
+#include "msp430f5217.h"
+
+#elif defined (__MSP430F5218__)
+#include "msp430f5218.h"
+
+#elif defined (__MSP430F5219__)
+#include "msp430f5219.h"
+
+#elif defined (__MSP430F5222__)
+#include "msp430f5222.h"
+
+#elif defined (__MSP430F5223__)
+#include "msp430f5223.h"
+
+#elif defined (__MSP430F5224__)
+#include "msp430f5224.h"
+
+#elif defined (__MSP430F5227__)
+#include "msp430f5227.h"
+
+#elif defined (__MSP430F5228__)
+#include "msp430f5228.h"
+
+#elif defined (__MSP430F5229__)
+#include "msp430f5229.h"
+
+#elif defined (__MSP430F5232__)
+#include "msp430f5232.h"
+
+#elif defined (__MSP430F5234__)
+#include "msp430f5234.h"
+
+#elif defined (__MSP430F5237__)
+#include "msp430f5237.h"
+
+#elif defined (__MSP430F5239__)
+#include "msp430f5239.h"
+
+#elif defined (__MSP430F5242__)
+#include "msp430f5242.h"
+
+#elif defined (__MSP430F5244__)
+#include "msp430f5244.h"
+
+#elif defined (__MSP430F5247__)
+#include "msp430f5247.h"
+
+#elif defined (__MSP430F5249__)
+#include "msp430f5249.h"
+
+#elif defined (__MSP430F5304__)
+#include "msp430f5304.h"
+
+#elif defined (__MSP430F5308__)
+#include "msp430f5308.h"
+
+#elif defined (__MSP430F5309__)
+#include "msp430f5309.h"
+
+#elif defined (__MSP430F5310__)
+#include "msp430f5310.h"
+
+#elif defined (__MSP430F5340__)
+#include "msp430f5340.h"
+
+#elif defined (__MSP430F5341__)
+#include "msp430f5341.h"
+
+#elif defined (__MSP430F5342__)
+#include "msp430f5342.h"
+
+#elif defined (__MSP430F5324__)
+#include "msp430f5324.h"
+
+#elif defined (__MSP430F5325__)
+#include "msp430f5325.h"
+
+#elif defined (__MSP430F5326__)
+#include "msp430f5326.h"
+
+#elif defined (__MSP430F5327__)
+#include "msp430f5327.h"
+
+#elif defined (__MSP430F5328__)
+#include "msp430f5328.h"
+
+#elif defined (__MSP430F5329__)
+#include "msp430f5329.h"
+
+#elif defined (__MSP430F5500__)
+#include "msp430f5500.h"
+
+#elif defined (__MSP430F5501__)
+#include "msp430f5501.h"
+
+#elif defined (__MSP430F5502__)
+#include "msp430f5502.h"
+
+#elif defined (__MSP430F5503__)
+#include "msp430f5503.h"
+
+#elif defined (__MSP430F5504__)
+#include "msp430f5504.h"
+
+#elif defined (__MSP430F5505__)
+#include "msp430f5505.h"
+
+#elif defined (__MSP430F5506__)
+#include "msp430f5506.h"
+
+#elif defined (__MSP430F5507__)
+#include "msp430f5507.h"
+
+#elif defined (__MSP430F5508__)
+#include "msp430f5508.h"
+
+#elif defined (__MSP430F5509__)
+#include "msp430f5509.h"
+
+#elif defined (__MSP430F5510__)
+#include "msp430f5510.h"
+
+#elif defined (__MSP430F5513__)
+#include "msp430f5513.h"
+
+#elif defined (__MSP430F5514__)
+#include "msp430f5514.h"
+
+#elif defined (__MSP430F5515__)
+#include "msp430f5515.h"
+
+#elif defined (__MSP430F5517__)
+#include "msp430f5517.h"
+
+#elif defined (__MSP430F5519__)
+#include "msp430f5519.h"
+
+#elif defined (__MSP430F5521__)
+#include "msp430f5521.h"
+
+#elif defined (__MSP430F5522__)
+#include "msp430f5522.h"
+
+#elif defined (__MSP430F5524__)
+#include "msp430f5524.h"
+
+#elif defined (__MSP430F5525__)
+#include "msp430f5525.h"
+
+#elif defined (__MSP430F5526__)
+#include "msp430f5526.h"
+
+#elif defined (__MSP430F5527__)
+#include "msp430f5527.h"
+
+#elif defined (__MSP430F5528__)
+#include "msp430f5528.h"
+
+#elif defined (__MSP430F5529__)
+#include "msp430f5529.h"
+
+#elif defined (__MSP430P112__)
+#include "msp430p112.h"
+
+#elif defined (__MSP430P313__)
+#include "msp430p313.h"
+
+#elif defined (__MSP430P315__)
+#include "msp430p315.h"
+
+#elif defined (__MSP430P315S__)
+#include "msp430p315s.h"
+
+#elif defined (__MSP430P325__)
+#include "msp430p325.h"
+
+#elif defined (__MSP430P337__)
+#include "msp430p337.h"
+
+#elif defined (__CC430F5133__)
+#include "cc430f5133.h"
+
+#elif defined (__CC430F5135__)
+#include "cc430f5135.h"
+
+#elif defined (__CC430F5137__)
+#include "cc430f5137.h"
+
+#elif defined (__CC430F6125__)
+#include "cc430f6125.h"
+
+#elif defined (__CC430F6126__)
+#include "cc430f6126.h"
+
+#elif defined (__CC430F6127__)
+#include "cc430f6127.h"
+
+#elif defined (__CC430F6135__)
+#include "cc430f6135.h"
+
+#elif defined (__CC430F6137__)
+#include "cc430f6137.h"
+
+#elif defined (__CC430F5123__)
+#include "cc430f5123.h"
+
+#elif defined (__CC430F5125__)
+#include "cc430f5125.h"
+
+#elif defined (__CC430F5143__)
+#include "cc430f5143.h"
+
+#elif defined (__CC430F5145__)
+#include "cc430f5145.h"
+
+#elif defined (__CC430F5147__)
+#include "cc430f5147.h"
+
+#elif defined (__CC430F6143__)
+#include "cc430f6143.h"
+
+#elif defined (__CC430F6145__)
+#include "cc430f6145.h"
+
+#elif defined (__CC430F6147__)
+#include "cc430f6147.h"
+
+#elif defined (__MSP430F5333__)
+#include "msp430f5333.h"
+
+#elif defined (__MSP430F5335__)
+#include "msp430f5335.h"
+
+#elif defined (__MSP430F5336__)
+#include "msp430f5336.h"
+
+#elif defined (__MSP430F5338__)
+#include "msp430f5338.h"
+
+#elif defined (__MSP430F5630__)
+#include "msp430f5630.h"
+
+#elif defined (__MSP430F5631__)
+#include "msp430f5631.h"
+
+#elif defined (__MSP430F5632__)
+#include "msp430f5632.h"
+
+#elif defined (__MSP430F5633__)
+#include "msp430f5633.h"
+
+#elif defined (__MSP430F5634__)
+#include "msp430f5634.h"
+
+#elif defined (__MSP430F5635__)
+#include "msp430f5635.h"
+
+#elif defined (__MSP430F5636__)
+#include "msp430f5636.h"
+
+#elif defined (__MSP430F5637__)
+#include "msp430f5637.h"
+
+#elif defined (__MSP430F5638__)
+#include "msp430f5638.h"
+
+#elif defined (__MSP430F6433__)
+#include "msp430f6433.h"
+
+#elif defined (__MSP430F6435__)
+#include "msp430f6435.h"
+
+#elif defined (__MSP430F6436__)
+#include "msp430f6436.h"
+
+#elif defined (__MSP430F6438__)
+#include "msp430f6438.h"
+
+#elif defined (__MSP430F6630__)
+#include "msp430f6630.h"
+
+#elif defined (__MSP430F6631__)
+#include "msp430f6631.h"
+
+#elif defined (__MSP430F6632__)
+#include "msp430f6632.h"
+
+#elif defined (__MSP430F6633__)
+#include "msp430f6633.h"
+
+#elif defined (__MSP430F6634__)
+#include "msp430f6634.h"
+
+#elif defined (__MSP430F6635__)
+#include "msp430f6635.h"
+
+#elif defined (__MSP430F6636__)
+#include "msp430f6636.h"
+
+#elif defined (__MSP430F6637__)
+#include "msp430f6637.h"
+
+#elif defined (__MSP430F6638__)
+#include "msp430f6638.h"
+
+#elif defined (__MSP430F5358__)
+#include "msp430f5358.h"
+
+#elif defined (__MSP430F5359__)
+#include "msp430f5359.h"
+
+#elif defined (__MSP430F5658__)
+#include "msp430f5658.h"
+
+#elif defined (__MSP430F5659__)
+#include "msp430f5659.h"
+
+#elif defined (__MSP430F6458__)
+#include "msp430f6458.h"
+
+#elif defined (__MSP430F6459__)
+#include "msp430f6459.h"
+
+#elif defined (__MSP430F6658__)
+#include "msp430f6658.h"
+
+#elif defined (__MSP430F6659__)
+#include "msp430f6659.h"
+
+#elif defined (__MSP430FG6425__)
+#include "msp430fg6425.h"
+
+#elif defined (__MSP430FG6426__)
+#include "msp430fg6426.h"
+
+#elif defined (__MSP430FG6625__)
+#include "msp430fg6625.h"
+
+#elif defined (__MSP430FG6626__)
+#include "msp430fg6626.h"
+
+#elif defined (__MSP430L092__)
+#include "msp430l092.h"
+
+#elif defined (__MSP430C091__)
+#include "msp430c091.h"
+
+#elif defined (__MSP430C092__)
+#include "msp430c092.h"
+
+#elif defined (__MSP430F5131__)
+#include "msp430f5131.h"
+
+#elif defined (__MSP430F5151__)
+#include "msp430f5151.h"
+
+#elif defined (__MSP430F5171__)
+#include "msp430f5171.h"
+
+#elif defined (__MSP430F5132__)
+#include "msp430f5132.h"
+
+#elif defined (__MSP430F5152__)
+#include "msp430f5152.h"
+
+#elif defined (__MSP430F5172__)
+#include "msp430f5172.h"
+
+#elif defined (__MSP430F6720__)
+#include "msp430f6720.h"
+
+#elif defined (__MSP430F6721__)
+#include "msp430f6721.h"
+
+#elif defined (__MSP430F6723__)
+#include "msp430f6723.h"
+
+#elif defined (__MSP430F6724__)
+#include "msp430f6724.h"
+
+#elif defined (__MSP430F6725__)
+#include "msp430f6725.h"
+
+#elif defined (__MSP430F6726__)
+#include "msp430f6726.h"
+
+#elif defined (__MSP430F6730__)
+#include "msp430f6730.h"
+
+#elif defined (__MSP430F6731__)
+#include "msp430f6731.h"
+
+#elif defined (__MSP430F6733__)
+#include "msp430f6733.h"
+
+#elif defined (__MSP430F6734__)
+#include "msp430f6734.h"
+
+#elif defined (__MSP430F6735__)
+#include "msp430f6735.h"
+
+#elif defined (__MSP430F6736__)
+#include "msp430f6736.h"
+
+#elif defined (__MSP430F67621__)
+#include "msp430f67621.h"
+
+#elif defined (__MSP430F67641__)
+#include "msp430f67641.h"
+
+#elif defined (__MSP430F6720A__)
+#include "msp430f6720a.h"
+
+#elif defined (__MSP430F6721A__)
+#include "msp430f6721a.h"
+
+#elif defined (__MSP430F6723A__)
+#include "msp430f6723a.h"
+
+#elif defined (__MSP430F6724A__)
+#include "msp430f6724a.h"
+
+#elif defined (__MSP430F6725A__)
+#include "msp430f6725a.h"
+
+#elif defined (__MSP430F6726A__)
+#include "msp430f6726a.h"
+
+#elif defined (__MSP430F6730A__)
+#include "msp430f6730a.h"
+
+#elif defined (__MSP430F6731A__)
+#include "msp430f6731a.h"
+
+#elif defined (__MSP430F6733A__)
+#include "msp430f6733a.h"
+
+#elif defined (__MSP430F6734A__)
+#include "msp430f6734a.h"
+
+#elif defined (__MSP430F6735A__)
+#include "msp430f6735a.h"
+
+#elif defined (__MSP430F6736A__)
+#include "msp430f6736a.h"
+
+#elif defined (__MSP430F67621A__)
+#include "msp430f67621a.h"
+
+#elif defined (__MSP430F67641A__)
+#include "msp430f67641a.h"
+
+#elif defined (__MSP430F67451__)
+#include "msp430f67451.h"
+
+#elif defined (__MSP430F67651__)
+#include "msp430f67651.h"
+
+#elif defined (__MSP430F67751__)
+#include "msp430f67751.h"
+
+#elif defined (__MSP430F67461__)
+#include "msp430f67461.h"
+
+#elif defined (__MSP430F67661__)
+#include "msp430f67661.h"
+
+#elif defined (__MSP430F67761__)
+#include "msp430f67761.h"
+
+#elif defined (__MSP430F67471__)
+#include "msp430f67471.h"
+
+#elif defined (__MSP430F67671__)
+#include "msp430f67671.h"
+
+#elif defined (__MSP430F67771__)
+#include "msp430f67771.h"
+
+#elif defined (__MSP430F67481__)
+#include "msp430f67481.h"
+
+#elif defined (__MSP430F67681__)
+#include "msp430f67681.h"
+
+#elif defined (__MSP430F67781__)
+#include "msp430f67781.h"
+
+#elif defined (__MSP430F67491__)
+#include "msp430f67491.h"
+
+#elif defined (__MSP430F67691__)
+#include "msp430f67691.h"
+
+#elif defined (__MSP430F67791__)
+#include "msp430f67791.h"
+
+#elif defined (__MSP430F6745__)
+#include "msp430f6745.h"
+
+#elif defined (__MSP430F6765__)
+#include "msp430f6765.h"
+
+#elif defined (__MSP430F6775__)
+#include "msp430f6775.h"
+
+#elif defined (__MSP430F6746__)
+#include "msp430f6746.h"
+
+#elif defined (__MSP430F6766__)
+#include "msp430f6766.h"
+
+#elif defined (__MSP430F6776__)
+#include "msp430f6776.h"
+
+#elif defined (__MSP430F6747__)
+#include "msp430f6747.h"
+
+#elif defined (__MSP430F6767__)
+#include "msp430f6767.h"
+
+#elif defined (__MSP430F6777__)
+#include "msp430f6777.h"
+
+#elif defined (__MSP430F6748__)
+#include "msp430f6748.h"
+
+#elif defined (__MSP430F6768__)
+#include "msp430f6768.h"
+
+#elif defined (__MSP430F6778__)
+#include "msp430f6778.h"
+
+#elif defined (__MSP430F6749__)
+#include "msp430f6749.h"
+
+#elif defined (__MSP430F6769__)
+#include "msp430f6769.h"
+
+#elif defined (__MSP430F6779__)
+#include "msp430f6779.h"
+
+#elif defined (__MSP430F67451A__)
+#include "msp430f67451a.h"
+
+#elif defined (__MSP430F67651A__)
+#include "msp430f67651a.h"
+
+#elif defined (__MSP430F67751A__)
+#include "msp430f67751a.h"
+
+#elif defined (__MSP430F67461A__)
+#include "msp430f67461a.h"
+
+#elif defined (__MSP430F67661A__)
+#include "msp430f67661a.h"
+
+#elif defined (__MSP430F67761A__)
+#include "msp430f67761a.h"
+
+#elif defined (__MSP430F67471A__)
+#include "msp430f67471a.h"
+
+#elif defined (__MSP430F67671A__)
+#include "msp430f67671a.h"
+
+#elif defined (__MSP430F67771A__)
+#include "msp430f67771a.h"
+
+#elif defined (__MSP430F67481A__)
+#include "msp430f67481a.h"
+
+#elif defined (__MSP430F67681A__)
+#include "msp430f67681a.h"
+
+#elif defined (__MSP430F67781A__)
+#include "msp430f67781a.h"
+
+#elif defined (__MSP430F67491A__)
+#include "msp430f67491a.h"
+
+#elif defined (__MSP430F67691A__)
+#include "msp430f67691a.h"
+
+#elif defined (__MSP430F67791A__)
+#include "msp430f67791a.h"
+
+#elif defined (__MSP430F6745A__)
+#include "msp430f6745a.h"
+
+#elif defined (__MSP430F6765A__)
+#include "msp430f6765a.h"
+
+#elif defined (__MSP430F6775A__)
+#include "msp430f6775a.h"
+
+#elif defined (__MSP430F6746A__)
+#include "msp430f6746a.h"
+
+#elif defined (__MSP430F6766A__)
+#include "msp430f6766a.h"
+
+#elif defined (__MSP430F6776A__)
+#include "msp430f6776a.h"
+
+#elif defined (__MSP430F6747A__)
+#include "msp430f6747a.h"
+
+#elif defined (__MSP430F6767A__)
+#include "msp430f6767a.h"
+
+#elif defined (__MSP430F6777A__)
+#include "msp430f6777a.h"
+
+#elif defined (__MSP430F6748A__)
+#include "msp430f6748a.h"
+
+#elif defined (__MSP430F6768A__)
+#include "msp430f6768a.h"
+
+#elif defined (__MSP430F6778A__)
+#include "msp430f6778a.h"
+
+#elif defined (__MSP430F6749A__)
+#include "msp430f6749a.h"
+
+#elif defined (__MSP430F6769A__)
+#include "msp430f6769a.h"
+
+#elif defined (__MSP430F6779A__)
+#include "msp430f6779a.h"
+
+#elif defined (__MSP430FR5720__)
+#include "msp430fr5720.h"
+
+#elif defined (__MSP430FR5721__)
+#include "msp430fr5721.h"
+
+#elif defined (__MSP430FR5722__)
+#include "msp430fr5722.h"
+
+#elif defined (__MSP430FR5723__)
+#include "msp430fr5723.h"
+
+#elif defined (__MSP430FR5724__)
+#include "msp430fr5724.h"
+
+#elif defined (__MSP430FR5725__)
+#include "msp430fr5725.h"
+
+#elif defined (__MSP430FR5726__)
+#include "msp430fr5726.h"
+
+#elif defined (__MSP430FR5727__)
+#include "msp430fr5727.h"
+
+#elif defined (__MSP430FR5728__)
+#include "msp430fr5728.h"
+
+#elif defined (__MSP430FR5729__)
+#include "msp430fr5729.h"
+
+#elif defined (__MSP430FR5730__)
+#include "msp430fr5730.h"
+
+#elif defined (__MSP430FR5731__)
+#include "msp430fr5731.h"
+
+#elif defined (__MSP430FR5732__)
+#include "msp430fr5732.h"
+
+#elif defined (__MSP430FR5733__)
+#include "msp430fr5733.h"
+
+#elif defined (__MSP430FR5734__)
+#include "msp430fr5734.h"
+
+#elif defined (__MSP430FR5735__)
+#include "msp430fr5735.h"
+
+#elif defined (__MSP430FR5736__)
+#include "msp430fr5736.h"
+
+#elif defined (__MSP430FR5737__)
+#include "msp430fr5737.h"
+
+#elif defined (__MSP430FR5738__)
+#include "msp430fr5738.h"
+
+#elif defined (__MSP430FR5739__)
+#include "msp430fr5739.h"
+
+#elif defined (__MSP430G2211__)
+#include "msp430g2211.h"
+
+#elif defined (__MSP430G2201__)
+#include "msp430g2201.h"
+
+#elif defined (__MSP430G2111__)
+#include "msp430g2111.h"
+
+#elif defined (__MSP430G2101__)
+#include "msp430g2101.h"
+
+#elif defined (__MSP430G2001__)
+#include "msp430g2001.h"
+
+#elif defined (__MSP430G2231__)
+#include "msp430g2231.h"
+
+#elif defined (__MSP430G2221__)
+#include "msp430g2221.h"
+
+#elif defined (__MSP430G2131__)
+#include "msp430g2131.h"
+
+#elif defined (__MSP430G2121__)
+#include "msp430g2121.h"
+
+#elif defined (__MSP430AFE221__)
+#include "msp430afe221.h"
+
+#elif defined (__MSP430AFE231__)
+#include "msp430afe231.h"
+
+#elif defined (__MSP430AFE251__)
+#include "msp430afe251.h"
+
+#elif defined (__MSP430AFE222__)
+#include "msp430afe222.h"
+
+#elif defined (__MSP430AFE232__)
+#include "msp430afe232.h"
+
+#elif defined (__MSP430AFE252__)
+#include "msp430afe252.h"
+
+#elif defined (__MSP430AFE223__)
+#include "msp430afe223.h"
+
+#elif defined (__MSP430AFE233__)
+#include "msp430afe233.h"
+
+#elif defined (__MSP430AFE253__)
+#include "msp430afe253.h"
+
+#elif defined (__MSP430G2102__)
+#include "msp430g2102.h"
+
+#elif defined (__MSP430G2202__)
+#include "msp430g2202.h"
+
+#elif defined (__MSP430G2302__)
+#include "msp430g2302.h"
+
+#elif defined (__MSP430G2402__)
+#include "msp430g2402.h"
+
+#elif defined (__MSP430G2132__)
+#include "msp430g2132.h"
+
+#elif defined (__MSP430G2232__)
+#include "msp430g2232.h"
+
+#elif defined (__MSP430G2332__)
+#include "msp430g2332.h"
+
+#elif defined (__MSP430G2432__)
+#include "msp430g2432.h"
+
+#elif defined (__MSP430G2112__)
+#include "msp430g2112.h"
+
+#elif defined (__MSP430G2212__)
+#include "msp430g2212.h"
+
+#elif defined (__MSP430G2312__)
+#include "msp430g2312.h"
+
+#elif defined (__MSP430G2412__)
+#include "msp430g2412.h"
+
+#elif defined (__MSP430G2152__)
+#include "msp430g2152.h"
+
+#elif defined (__MSP430G2252__)
+#include "msp430g2252.h"
+
+#elif defined (__MSP430G2352__)
+#include "msp430g2352.h"
+
+#elif defined (__MSP430G2452__)
+#include "msp430g2452.h"
+
+#elif defined (__MSP430G2113__)
+#include "msp430g2113.h"
+
+#elif defined (__MSP430G2213__)
+#include "msp430g2213.h"
+
+#elif defined (__MSP430G2313__)
+#include "msp430g2313.h"
+
+#elif defined (__MSP430G2413__)
+#include "msp430g2413.h"
+
+#elif defined (__MSP430G2513__)
+#include "msp430g2513.h"
+
+#elif defined (__MSP430G2153__)
+#include "msp430g2153.h"
+
+#elif defined (__MSP430G2253__)
+#include "msp430g2253.h"
+
+#elif defined (__MSP430G2353__)
+#include "msp430g2353.h"
+
+#elif defined (__MSP430G2453__)
+#include "msp430g2453.h"
+
+#elif defined (__MSP430G2553__)
+#include "msp430g2553.h"
+
+#elif defined (__MSP430G2203__)
+#include "msp430g2203.h"
+
+#elif defined (__MSP430G2303__)
+#include "msp430g2303.h"
+
+#elif defined (__MSP430G2403__)
+#include "msp430g2403.h"
+
+#elif defined (__MSP430G2233__)
+#include "msp430g2233.h"
+
+#elif defined (__MSP430G2333__)
+#include "msp430g2333.h"
+
+#elif defined (__MSP430G2433__)
+#include "msp430g2433.h"
+
+#elif defined (__MSP430G2533__)
+#include "msp430g2533.h"
+
+#elif defined (__MSP430TCH5E__)
+#include "msp430tch5e.h"
+
+#elif defined (__MSP430G2444__)
+#include "msp430g2444.h"
+
+#elif defined (__MSP430G2544__)
+#include "msp430g2544.h"
+
+#elif defined (__MSP430G2744__)
+#include "msp430g2744.h"
+
+#elif defined (__MSP430G2755__)
+#include "msp430g2755.h"
+
+#elif defined (__MSP430G2855__)
+#include "msp430g2855.h"
+
+#elif defined (__MSP430G2955__)
+#include "msp430g2955.h"
+
+#elif defined (__MSP430G2230__)
+#include "msp430g2230.h"
+
+#elif defined (__MSP430G2210__)
+#include "msp430g2210.h"
+
+#elif defined (__MSP430BT5190__)
+#include "msp430bt5190.h"
+
+#elif defined (__MSP430FR5857__)
+#include "msp430fr5857.h"
+
+#elif defined (__MSP430FR5858__)
+#include "msp430fr5858.h"
+
+#elif defined (__MSP430FR5859__)
+#include "msp430fr5859.h"
+
+#elif defined (__MSP430FR5847__)
+#include "msp430fr5847.h"
+
+#elif defined (__MSP430FR58471__)
+#include "msp430fr58471.h"
+
+#elif defined (__MSP430FR5848__)
+#include "msp430fr5848.h"
+
+#elif defined (__MSP430FR5849__)
+#include "msp430fr5849.h"
+
+#elif defined (__MSP430FR5867__)
+#include "msp430fr5867.h"
+
+#elif defined (__MSP430FR58671__)
+#include "msp430fr58671.h"
+
+#elif defined (__MSP430FR5868__)
+#include "msp430fr5868.h"
+
+#elif defined (__MSP430FR5869__)
+#include "msp430fr5869.h"
+
+#elif defined (__MSP430FR5957__)
+#include "msp430fr5957.h"
+
+#elif defined (__MSP430FR5958__)
+#include "msp430fr5958.h"
+
+#elif defined (__MSP430FR5959__)
+#include "msp430fr5959.h"
+
+#elif defined (__MSP430FR5947__)
+#include "msp430fr5947.h"
+
+#elif defined (__MSP430FR59471__)
+#include "msp430fr59471.h"
+
+#elif defined (__MSP430FR5948__)
+#include "msp430fr5948.h"
+
+#elif defined (__MSP430FR5949__)
+#include "msp430fr5949.h"
+
+#elif defined (__MSP430FR5967__)
+#include "msp430fr5967.h"
+
+#elif defined (__MSP430FR5968__)
+#include "msp430fr5968.h"
+
+#elif defined (__MSP430FR5969__)
+#include "msp430fr5969.h"
+
+#elif defined (__MSP430FR59691__)
+#include "msp430fr59691.h"
+
+#elif defined (__MSP430FR5962__)
+#include "msp430fr5962.h"
+
+#elif defined (__MSP430FR5964__)
+#include "msp430fr5964.h"
+
+#elif defined (__MSP430FR5992__)
+#include "msp430fr5992.h"
+
+#elif defined (__MSP430FR5994__)
+#include "msp430fr5994.h"
+
+#elif defined (__MSP430FR59941__)
+#include "msp430fr59941.h"
+
+#elif defined (__MSP430i2020__)
+#include "msp430i2020.h"
+
+#elif defined (__MSP430i2021__)
+#include "msp430i2021.h"
+
+#elif defined (__MSP430i2030__)
+#include "msp430i2030.h"
+
+#elif defined (__MSP430i2031__)
+#include "msp430i2031.h"
+
+#elif defined (__MSP430i2040__)
+#include "msp430i2040.h"
+
+#elif defined (__MSP430i2041__)
+#include "msp430i2041.h"
+
+#elif defined (__RF430FRL152H__)
+#include "rf430frl152h.h"
+
+#elif defined (__RF430FRL153H__)
+#include "rf430frl153h.h"
+
+#elif defined (__RF430FRL154H__)
+#include "rf430frl154h.h"
+
+#elif defined (__RF430FRL152H_ROM__)
+#include "rf430frl152h_rom.h"
+
+#elif defined (__RF430FRL153H_ROM__)
+#include "rf430frl153h_rom.h"
+
+#elif defined (__RF430FRL154H_ROM__)
+#include "rf430frl154h_rom.h"
+
+#elif defined (__RF430F5175__)
+#include "rf430f5175.h"
+
+#elif defined (__RF430F5155__)
+#include "rf430f5155.h"
+
+#elif defined (__RF430F5144__)
+#include "rf430f5144.h"
+
+#elif defined (__MSP430FR69271__)
+#include "msp430fr69271.h"
+
+#elif defined (__MSP430FR68791__)
+#include "msp430fr68791.h"
+
+#elif defined (__MSP430FR69791__)
+#include "msp430fr69791.h"
+
+#elif defined (__MSP430FR6927__)
+#include "msp430fr6927.h"
+
+#elif defined (__MSP430FR6928__)
+#include "msp430fr6928.h"
+
+#elif defined (__MSP430FR6877__)
+#include "msp430fr6877.h"
+
+#elif defined (__MSP430FR6977__)
+#include "msp430fr6977.h"
+
+#elif defined (__MSP430FR6879__)
+#include "msp430fr6879.h"
+
+#elif defined (__MSP430FR6979__)
+#include "msp430fr6979.h"
+
+#elif defined (__MSP430FR58891__)
+#include "msp430fr58891.h"
+
+#elif defined (__MSP430FR68891__)
+#include "msp430fr68891.h"
+
+#elif defined (__MSP430FR59891__)
+#include "msp430fr59891.h"
+
+#elif defined (__MSP430FR69891__)
+#include "msp430fr69891.h"
+
+#elif defined (__MSP430FR5887__)
+#include "msp430fr5887.h"
+
+#elif defined (__MSP430FR5888__)
+#include "msp430fr5888.h"
+
+#elif defined (__MSP430FR5889__)
+#include "msp430fr5889.h"
+
+#elif defined (__MSP430FR6887__)
+#include "msp430fr6887.h"
+
+#elif defined (__MSP430FR6888__)
+#include "msp430fr6888.h"
+
+#elif defined (__MSP430FR6889__)
+#include "msp430fr6889.h"
+
+#elif defined (__MSP430FR5986__)
+#include "msp430fr5986.h"
+
+#elif defined (__MSP430FR5987__)
+#include "msp430fr5987.h"
+
+#elif defined (__MSP430FR5988__)
+#include "msp430fr5988.h"
+
+#elif defined (__MSP430FR5989__)
+#include "msp430fr5989.h"
+
+#elif defined (__MSP430FR6987__)
+#include "msp430fr6987.h"
+
+#elif defined (__MSP430FR6988__)
+#include "msp430fr6988.h"
+
+#elif defined (__MSP430FR6989__)
+#include "msp430fr6989.h"
+
+#elif defined (__MSP430FR5922__)
+#include "msp430fr5922.h"
+
+#elif defined (__MSP430FR5870__)
+#include "msp430fr5870.h"
+
+#elif defined (__MSP430FR5970__)
+#include "msp430fr5970.h"
+
+#elif defined (__MSP430FR5872__)
+#include "msp430fr5872.h"
+
+#elif defined (__MSP430FR5972__)
+#include "msp430fr5972.h"
+
+#elif defined (__MSP430FR6820__)
+#include "msp430fr6820.h"
+
+#elif defined (__MSP430FR6920__)
+#include "msp430fr6920.h"
+
+#elif defined (__MSP430FR6822__)
+#include "msp430fr6822.h"
+
+#elif defined (__MSP430FR6922__)
+#include "msp430fr6922.h"
+
+#elif defined (__MSP430FR6870__)
+#include "msp430fr6870.h"
+
+#elif defined (__MSP430FR6970__)
+#include "msp430fr6970.h"
+
+#elif defined (__MSP430FR6872__)
+#include "msp430fr6872.h"
+
+#elif defined (__MSP430FR6972__)
+#include "msp430fr6972.h"
+
+#elif defined (__MSP430FR59221__)
+#include "msp430fr59221.h"
+
+#elif defined (__MSP430FR58721__)
+#include "msp430fr58721.h"
+
+#elif defined (__MSP430FR59721__)
+#include "msp430fr59721.h"
+
+#elif defined (__MSP430FR68221__)
+#include "msp430fr68221.h"
+
+#elif defined (__MSP430FR69221__)
+#include "msp430fr69221.h"
+
+#elif defined (__MSP430FR68721__)
+#include "msp430fr68721.h"
+
+#elif defined (__MSP430FR69721__)
+#include "msp430fr69721.h"
+
+#elif defined (__MSP430SL5438A__)
+#include "msp430sl5438a.h"
+
+#elif defined (__MSP430FR4131__)
+#include "msp430fr4131.h"
+
+#elif defined (__MSP430FR4132__)
+#include "msp430fr4132.h"
+
+#elif defined (__MSP430FR4133__)
+#include "msp430fr4133.h"
+
+#elif defined (__MSP430FR2032__)
+#include "msp430fr2032.h"
+
+#elif defined (__MSP430FR2033__)
+#include "msp430fr2033.h"
+
+#elif defined (__MSP430FR2110__)
+#include "msp430fr2110.h"
+
+#elif defined (__MSP430FR2111__)
+#include "msp430fr2111.h"
+
+#elif defined (__MSP430FR2310__)
+#include "msp430fr2310.h"
+
+#elif defined (__MSP430FR2311__)
+#include "msp430fr2311.h"
+
+#elif defined (__MSP430FR2433__)
+#include "msp430fr2433.h"
+
+#elif defined (__MSP430FR2532__)
+#include "msp430fr2532.h"
+
+#elif defined (__MSP430FR2533__)
+#include "msp430fr2533.h"
+
+#elif defined (__MSP430FR2632__)
+#include "msp430fr2632.h"
+
+#elif defined (__MSP430FR2633__)
+#include "msp430fr2633.h"
+
+#elif defined (__MSP430F5252__)
+#include "msp430f5252.h"
+
+#elif defined (__MSP430F5253__)
+#include "msp430f5253.h"
+
+#elif defined (__MSP430F5254__)
+#include "msp430f5254.h"
+
+#elif defined (__MSP430F5255__)
+#include "msp430f5255.h"
+
+#elif defined (__MSP430F5256__)
+#include "msp430f5256.h"
+
+#elif defined (__MSP430F5257__)
+#include "msp430f5257.h"
+
+#elif defined (__MSP430F5258__)
+#include "msp430f5258.h"
+
+#elif defined (__MSP430F5259__)
+#include "msp430f5259.h"
+
+
+#elif defined (__MSP430XGENERIC__)
+#include "msp430xgeneric.h"
+
+#elif defined (__MSP430F5XX_6XXGENERIC__)
+#include "msp430f5xx_6xxgeneric.h"
+
+#elif defined (__MSP430FR5XX_6XXGENERIC__)
+#include "msp430fr5xx_6xxgeneric.h"
+
+#elif defined (__MSP430FR2XX_4XXGENERIC__)
+#include "msp430fr2xx_4xxgeneric.h"
+
+#elif defined (__MSP430FR57XXGENERIC__)
+#include "msp430fr57xxgeneric.h"
+
+#elif defined (__MSP430I2XXGENERIC__)
+#include "msp430i2xxgeneric.h"
+
+/********************************************************************
+ *  msp430 generic
+ ********************************************************************/
+#elif defined (__MSP430GENERIC__)
+#error "msp430 generic device does not have a default include file"
+
+#elif defined (__MSP430XGENERIC__)
+#error "msp430X generic device does not have a default include file"
+
+
+/********************************************************************
+ *
+ ********************************************************************/
+#else
+#error "Failed to match a default include file"
+#endif
+
+#endif /* #ifndef __msp430 */
+
+
diff --git a/os/common/ext/MSP430/inc/msp430fr5969.h b/os/common/ext/MSP430/inc/msp430fr5969.h
new file mode 100755
index 0000000..54b14f1
--- /dev/null
+++ b/os/common/ext/MSP430/inc/msp430fr5969.h
@@ -0,0 +1,4509 @@
+/* ============================================================================ */
+/* Copyright (c) 2016, Texas Instruments Incorporated                           */
+/*  All rights reserved.                                                        */
+/*                                                                              */
+/*  Redistribution and use in source and binary forms, with or without          */
+/*  modification, are permitted provided that the following conditions          */
+/*  are met:                                                                    */
+/*                                                                              */
+/*  *  Redistributions of source code must retain the above copyright           */
+/*     notice, this list of conditions and the following disclaimer.            */
+/*                                                                              */
+/*  *  Redistributions in binary form must reproduce the above copyright        */
+/*     notice, this list of conditions and the following disclaimer in the      */
+/*     documentation and/or other materials provided with the distribution.     */
+/*                                                                              */
+/*  *  Neither the name of Texas Instruments Incorporated nor the names of      */
+/*     its contributors may be used to endorse or promote products derived      */
+/*     from this software without specific prior written permission.            */
+/*                                                                              */
+/*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */
+/*  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,       */
+/*  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR      */
+/*  PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR            */
+/*  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,       */
+/*  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,         */
+/*  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */
+/*  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,    */
+/*  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR     */
+/*  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,              */
+/*  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                          */
+/* ============================================================================ */
+
+/********************************************************************
+*
+* Standard register and bit definitions for the Texas Instruments
+* MSP430 microcontroller.
+*
+* This file supports assembler and C development for
+* MSP430FR5969 devices.
+*
+* Texas Instruments, Version 1.4
+*
+* Rev. 1.0, Setup
+* Rev. 1.1  updated PxSELC register address to offset 0x16 (instead of 0x10)
+*           replaced Comperator B with Comperator E
+* Rev. 1.2  fixed typo in SYSRSTIV_MPUSEG defintions
+*           replaced COMP_B with COMP_E
+* Rev. 1.3  removed not available PxDS Register definitions
+* Rev. 1.4  replaced NACCESSx with NWAITSx
+*
+********************************************************************/
+
+#ifndef __MSP430FR5969
+#define __MSP430FR5969
+
+#define __MSP430_HAS_MSP430XV2_CPU__                /* Definition to show that it has MSP430XV2 CPU */
+#define __MSP430FR5XX_6XX_FAMILY__
+
+#define __MSP430_HEADER_VERSION__ 1198
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*----------------------------------------------------------------------------*/
+/* PERIPHERAL FILE MAP                                                        */
+/*----------------------------------------------------------------------------*/
+
+#define __MSP430_TI_HEADERS__
+
+#include <iomacros.h>
+
+
+/************************************************************
+* STANDARD BITS
+************************************************************/
+
+#define BIT0                   (0x0001)
+#define BIT1                   (0x0002)
+#define BIT2                   (0x0004)
+#define BIT3                   (0x0008)
+#define BIT4                   (0x0010)
+#define BIT5                   (0x0020)
+#define BIT6                   (0x0040)
+#define BIT7                   (0x0080)
+#define BIT8                   (0x0100)
+#define BIT9                   (0x0200)
+#define BITA                   (0x0400)
+#define BITB                   (0x0800)
+#define BITC                   (0x1000)
+#define BITD                   (0x2000)
+#define BITE                   (0x4000)
+#define BITF                   (0x8000)
+
+/************************************************************
+* STATUS REGISTER BITS
+************************************************************/
+
+#define C                      (0x0001)
+#define Z                      (0x0002)
+#define N                      (0x0004)
+#define V                      (0x0100)
+#define GIE                    (0x0008)
+#define CPUOFF                 (0x0010)
+#define OSCOFF                 (0x0020)
+#define SCG0                   (0x0040)
+#define SCG1                   (0x0080)
+
+/* Low Power Modes coded with Bits 4-7 in SR */
+
+#ifndef __STDC__ /* Begin #defines for assembler */
+#define LPM0                   (CPUOFF)
+#define LPM1                   (SCG0+CPUOFF)
+#define LPM2                   (SCG1+CPUOFF)
+#define LPM3                   (SCG1+SCG0+CPUOFF)
+#define LPM4                   (SCG1+SCG0+OSCOFF+CPUOFF)
+/* End #defines for assembler */
+
+#else /* Begin #defines for C */
+#define LPM0_bits              (CPUOFF)
+#define LPM1_bits              (SCG0+CPUOFF)
+#define LPM2_bits              (SCG1+CPUOFF)
+#define LPM3_bits              (SCG1+SCG0+CPUOFF)
+#define LPM4_bits              (SCG1+SCG0+OSCOFF+CPUOFF)
+
+#include "in430.h"
+
+#define LPM0      __bis_SR_register(LPM0_bits)         /* Enter Low Power Mode 0 */
+#define LPM0_EXIT __bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */
+#define LPM1      __bis_SR_register(LPM1_bits)         /* Enter Low Power Mode 1 */
+#define LPM1_EXIT __bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */
+#define LPM2      __bis_SR_register(LPM2_bits)         /* Enter Low Power Mode 2 */
+#define LPM2_EXIT __bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */
+#define LPM3      __bis_SR_register(LPM3_bits)         /* Enter Low Power Mode 3 */
+#define LPM3_EXIT __bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */
+#define LPM4      __bis_SR_register(LPM4_bits)         /* Enter Low Power Mode 4 */
+#define LPM4_EXIT __bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */
+#endif /* End #defines for C */
+
+/************************************************************
+* PERIPHERAL FILE MAP
+************************************************************/
+
+/************************************************************
+* ADC12_B
+************************************************************/
+#define __MSP430_HAS_ADC12_B__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_ADC12_B__ 0x0800
+#define ADC12_B_BASE           __MSP430_BASEADDRESS_ADC12_B__
+
+sfr_w(ADC12CTL0);                             /* ADC12 B Control 0 */
+sfr_b(ADC12CTL0_L);                           /* ADC12 B Control 0 */
+sfr_b(ADC12CTL0_H);                           /* ADC12 B Control 0 */
+sfr_w(ADC12CTL1);                             /* ADC12 B Control 1 */
+sfr_b(ADC12CTL1_L);                           /* ADC12 B Control 1 */
+sfr_b(ADC12CTL1_H);                           /* ADC12 B Control 1 */
+sfr_w(ADC12CTL2);                             /* ADC12 B Control 2 */
+sfr_b(ADC12CTL2_L);                           /* ADC12 B Control 2 */
+sfr_b(ADC12CTL2_H);                           /* ADC12 B Control 2 */
+sfr_w(ADC12CTL3);                             /* ADC12 B Control 3 */
+sfr_b(ADC12CTL3_L);                           /* ADC12 B Control 3 */
+sfr_b(ADC12CTL3_H);                           /* ADC12 B Control 3 */
+sfr_w(ADC12LO);                               /* ADC12 B Window Comparator High Threshold */
+sfr_b(ADC12LO_L);                             /* ADC12 B Window Comparator High Threshold */
+sfr_b(ADC12LO_H);                             /* ADC12 B Window Comparator High Threshold */
+sfr_w(ADC12HI);                               /* ADC12 B Window Comparator High Threshold */
+sfr_b(ADC12HI_L);                             /* ADC12 B Window Comparator High Threshold */
+sfr_b(ADC12HI_H);                             /* ADC12 B Window Comparator High Threshold */
+sfr_w(ADC12IFGR0);                            /* ADC12 B Interrupt Flag 0 */
+sfr_b(ADC12IFGR0_L);                          /* ADC12 B Interrupt Flag 0 */
+sfr_b(ADC12IFGR0_H);                          /* ADC12 B Interrupt Flag 0 */
+sfr_w(ADC12IFGR1);                            /* ADC12 B Interrupt Flag 1 */
+sfr_b(ADC12IFGR1_L);                          /* ADC12 B Interrupt Flag 1 */
+sfr_b(ADC12IFGR1_H);                          /* ADC12 B Interrupt Flag 1 */
+sfr_w(ADC12IFGR2);                            /* ADC12 B Interrupt Flag 2 */
+sfr_b(ADC12IFGR2_L);                          /* ADC12 B Interrupt Flag 2 */
+sfr_b(ADC12IFGR2_H);                          /* ADC12 B Interrupt Flag 2 */
+sfr_w(ADC12IER0);                             /* ADC12 B Interrupt Enable 0 */
+sfr_b(ADC12IER0_L);                           /* ADC12 B Interrupt Enable 0 */
+sfr_b(ADC12IER0_H);                           /* ADC12 B Interrupt Enable 0 */
+sfr_w(ADC12IER1);                             /* ADC12 B Interrupt Enable 1 */
+sfr_b(ADC12IER1_L);                           /* ADC12 B Interrupt Enable 1 */
+sfr_b(ADC12IER1_H);                           /* ADC12 B Interrupt Enable 1 */
+sfr_w(ADC12IER2);                             /* ADC12 B Interrupt Enable 2 */
+sfr_b(ADC12IER2_L);                           /* ADC12 B Interrupt Enable 2 */
+sfr_b(ADC12IER2_H);                           /* ADC12 B Interrupt Enable 2 */
+sfr_w(ADC12IV);                               /* ADC12 B Interrupt Vector Word */
+sfr_b(ADC12IV_L);                             /* ADC12 B Interrupt Vector Word */
+sfr_b(ADC12IV_H);                             /* ADC12 B Interrupt Vector Word */
+
+sfr_w(ADC12MCTL0);                            /* ADC12 Memory Control 0 */
+sfr_b(ADC12MCTL0_L);                          /* ADC12 Memory Control 0 */
+sfr_b(ADC12MCTL0_H);                          /* ADC12 Memory Control 0 */
+sfr_w(ADC12MCTL1);                            /* ADC12 Memory Control 1 */
+sfr_b(ADC12MCTL1_L);                          /* ADC12 Memory Control 1 */
+sfr_b(ADC12MCTL1_H);                          /* ADC12 Memory Control 1 */
+sfr_w(ADC12MCTL2);                            /* ADC12 Memory Control 2 */
+sfr_b(ADC12MCTL2_L);                          /* ADC12 Memory Control 2 */
+sfr_b(ADC12MCTL2_H);                          /* ADC12 Memory Control 2 */
+sfr_w(ADC12MCTL3);                            /* ADC12 Memory Control 3 */
+sfr_b(ADC12MCTL3_L);                          /* ADC12 Memory Control 3 */
+sfr_b(ADC12MCTL3_H);                          /* ADC12 Memory Control 3 */
+sfr_w(ADC12MCTL4);                            /* ADC12 Memory Control 4 */
+sfr_b(ADC12MCTL4_L);                          /* ADC12 Memory Control 4 */
+sfr_b(ADC12MCTL4_H);                          /* ADC12 Memory Control 4 */
+sfr_w(ADC12MCTL5);                            /* ADC12 Memory Control 5 */
+sfr_b(ADC12MCTL5_L);                          /* ADC12 Memory Control 5 */
+sfr_b(ADC12MCTL5_H);                          /* ADC12 Memory Control 5 */
+sfr_w(ADC12MCTL6);                            /* ADC12 Memory Control 6 */
+sfr_b(ADC12MCTL6_L);                          /* ADC12 Memory Control 6 */
+sfr_b(ADC12MCTL6_H);                          /* ADC12 Memory Control 6 */
+sfr_w(ADC12MCTL7);                            /* ADC12 Memory Control 7 */
+sfr_b(ADC12MCTL7_L);                          /* ADC12 Memory Control 7 */
+sfr_b(ADC12MCTL7_H);                          /* ADC12 Memory Control 7 */
+sfr_w(ADC12MCTL8);                            /* ADC12 Memory Control 8 */
+sfr_b(ADC12MCTL8_L);                          /* ADC12 Memory Control 8 */
+sfr_b(ADC12MCTL8_H);                          /* ADC12 Memory Control 8 */
+sfr_w(ADC12MCTL9);                            /* ADC12 Memory Control 9 */
+sfr_b(ADC12MCTL9_L);                          /* ADC12 Memory Control 9 */
+sfr_b(ADC12MCTL9_H);                          /* ADC12 Memory Control 9 */
+sfr_w(ADC12MCTL10);                           /* ADC12 Memory Control 10 */
+sfr_b(ADC12MCTL10_L);                         /* ADC12 Memory Control 10 */
+sfr_b(ADC12MCTL10_H);                         /* ADC12 Memory Control 10 */
+sfr_w(ADC12MCTL11);                           /* ADC12 Memory Control 11 */
+sfr_b(ADC12MCTL11_L);                         /* ADC12 Memory Control 11 */
+sfr_b(ADC12MCTL11_H);                         /* ADC12 Memory Control 11 */
+sfr_w(ADC12MCTL12);                           /* ADC12 Memory Control 12 */
+sfr_b(ADC12MCTL12_L);                         /* ADC12 Memory Control 12 */
+sfr_b(ADC12MCTL12_H);                         /* ADC12 Memory Control 12 */
+sfr_w(ADC12MCTL13);                           /* ADC12 Memory Control 13 */
+sfr_b(ADC12MCTL13_L);                         /* ADC12 Memory Control 13 */
+sfr_b(ADC12MCTL13_H);                         /* ADC12 Memory Control 13 */
+sfr_w(ADC12MCTL14);                           /* ADC12 Memory Control 14 */
+sfr_b(ADC12MCTL14_L);                         /* ADC12 Memory Control 14 */
+sfr_b(ADC12MCTL14_H);                         /* ADC12 Memory Control 14 */
+sfr_w(ADC12MCTL15);                           /* ADC12 Memory Control 15 */
+sfr_b(ADC12MCTL15_L);                         /* ADC12 Memory Control 15 */
+sfr_b(ADC12MCTL15_H);                         /* ADC12 Memory Control 15 */
+sfr_w(ADC12MCTL16);                           /* ADC12 Memory Control 16 */
+sfr_b(ADC12MCTL16_L);                         /* ADC12 Memory Control 16 */
+sfr_b(ADC12MCTL16_H);                         /* ADC12 Memory Control 16 */
+sfr_w(ADC12MCTL17);                           /* ADC12 Memory Control 17 */
+sfr_b(ADC12MCTL17_L);                         /* ADC12 Memory Control 17 */
+sfr_b(ADC12MCTL17_H);                         /* ADC12 Memory Control 17 */
+sfr_w(ADC12MCTL18);                           /* ADC12 Memory Control 18 */
+sfr_b(ADC12MCTL18_L);                         /* ADC12 Memory Control 18 */
+sfr_b(ADC12MCTL18_H);                         /* ADC12 Memory Control 18 */
+sfr_w(ADC12MCTL19);                           /* ADC12 Memory Control 19 */
+sfr_b(ADC12MCTL19_L);                         /* ADC12 Memory Control 19 */
+sfr_b(ADC12MCTL19_H);                         /* ADC12 Memory Control 19 */
+sfr_w(ADC12MCTL20);                           /* ADC12 Memory Control 20 */
+sfr_b(ADC12MCTL20_L);                         /* ADC12 Memory Control 20 */
+sfr_b(ADC12MCTL20_H);                         /* ADC12 Memory Control 20 */
+sfr_w(ADC12MCTL21);                           /* ADC12 Memory Control 21 */
+sfr_b(ADC12MCTL21_L);                         /* ADC12 Memory Control 21 */
+sfr_b(ADC12MCTL21_H);                         /* ADC12 Memory Control 21 */
+sfr_w(ADC12MCTL22);                           /* ADC12 Memory Control 22 */
+sfr_b(ADC12MCTL22_L);                         /* ADC12 Memory Control 22 */
+sfr_b(ADC12MCTL22_H);                         /* ADC12 Memory Control 22 */
+sfr_w(ADC12MCTL23);                           /* ADC12 Memory Control 23 */
+sfr_b(ADC12MCTL23_L);                         /* ADC12 Memory Control 23 */
+sfr_b(ADC12MCTL23_H);                         /* ADC12 Memory Control 23 */
+sfr_w(ADC12MCTL24);                           /* ADC12 Memory Control 24 */
+sfr_b(ADC12MCTL24_L);                         /* ADC12 Memory Control 24 */
+sfr_b(ADC12MCTL24_H);                         /* ADC12 Memory Control 24 */
+sfr_w(ADC12MCTL25);                           /* ADC12 Memory Control 25 */
+sfr_b(ADC12MCTL25_L);                         /* ADC12 Memory Control 25 */
+sfr_b(ADC12MCTL25_H);                         /* ADC12 Memory Control 25 */
+sfr_w(ADC12MCTL26);                           /* ADC12 Memory Control 26 */
+sfr_b(ADC12MCTL26_L);                         /* ADC12 Memory Control 26 */
+sfr_b(ADC12MCTL26_H);                         /* ADC12 Memory Control 26 */
+sfr_w(ADC12MCTL27);                           /* ADC12 Memory Control 27 */
+sfr_b(ADC12MCTL27_L);                         /* ADC12 Memory Control 27 */
+sfr_b(ADC12MCTL27_H);                         /* ADC12 Memory Control 27 */
+sfr_w(ADC12MCTL28);                           /* ADC12 Memory Control 28 */
+sfr_b(ADC12MCTL28_L);                         /* ADC12 Memory Control 28 */
+sfr_b(ADC12MCTL28_H);                         /* ADC12 Memory Control 28 */
+sfr_w(ADC12MCTL29);                           /* ADC12 Memory Control 29 */
+sfr_b(ADC12MCTL29_L);                         /* ADC12 Memory Control 29 */
+sfr_b(ADC12MCTL29_H);                         /* ADC12 Memory Control 29 */
+sfr_w(ADC12MCTL30);                           /* ADC12 Memory Control 30 */
+sfr_b(ADC12MCTL30_L);                         /* ADC12 Memory Control 30 */
+sfr_b(ADC12MCTL30_H);                         /* ADC12 Memory Control 30 */
+sfr_w(ADC12MCTL31);                           /* ADC12 Memory Control 31 */
+sfr_b(ADC12MCTL31_L);                         /* ADC12 Memory Control 31 */
+sfr_b(ADC12MCTL31_H);                         /* ADC12 Memory Control 31 */
+#define ADC12MCTL_             ADC12MCTL      /* ADC12 Memory Control */
+#ifndef __STDC__
+#define ADC12MCTL              ADC12MCTL0     /* ADC12 Memory Control (for assembler) */
+#else
+#define ADC12MCTL              ((volatile char*)       &ADC12MCTL0) /* ADC12 Memory Control (for C) */
+#endif
+
+sfr_w(ADC12MEM0);                             /* ADC12 Conversion Memory 0 */
+sfr_b(ADC12MEM0_L);                           /* ADC12 Conversion Memory 0 */
+sfr_b(ADC12MEM0_H);                           /* ADC12 Conversion Memory 0 */
+sfr_w(ADC12MEM1);                             /* ADC12 Conversion Memory 1 */
+sfr_b(ADC12MEM1_L);                           /* ADC12 Conversion Memory 1 */
+sfr_b(ADC12MEM1_H);                           /* ADC12 Conversion Memory 1 */
+sfr_w(ADC12MEM2);                             /* ADC12 Conversion Memory 2 */
+sfr_b(ADC12MEM2_L);                           /* ADC12 Conversion Memory 2 */
+sfr_b(ADC12MEM2_H);                           /* ADC12 Conversion Memory 2 */
+sfr_w(ADC12MEM3);                             /* ADC12 Conversion Memory 3 */
+sfr_b(ADC12MEM3_L);                           /* ADC12 Conversion Memory 3 */
+sfr_b(ADC12MEM3_H);                           /* ADC12 Conversion Memory 3 */
+sfr_w(ADC12MEM4);                             /* ADC12 Conversion Memory 4 */
+sfr_b(ADC12MEM4_L);                           /* ADC12 Conversion Memory 4 */
+sfr_b(ADC12MEM4_H);                           /* ADC12 Conversion Memory 4 */
+sfr_w(ADC12MEM5);                             /* ADC12 Conversion Memory 5 */
+sfr_b(ADC12MEM5_L);                           /* ADC12 Conversion Memory 5 */
+sfr_b(ADC12MEM5_H);                           /* ADC12 Conversion Memory 5 */
+sfr_w(ADC12MEM6);                             /* ADC12 Conversion Memory 6 */
+sfr_b(ADC12MEM6_L);                           /* ADC12 Conversion Memory 6 */
+sfr_b(ADC12MEM6_H);                           /* ADC12 Conversion Memory 6 */
+sfr_w(ADC12MEM7);                             /* ADC12 Conversion Memory 7 */
+sfr_b(ADC12MEM7_L);                           /* ADC12 Conversion Memory 7 */
+sfr_b(ADC12MEM7_H);                           /* ADC12 Conversion Memory 7 */
+sfr_w(ADC12MEM8);                             /* ADC12 Conversion Memory 8 */
+sfr_b(ADC12MEM8_L);                           /* ADC12 Conversion Memory 8 */
+sfr_b(ADC12MEM8_H);                           /* ADC12 Conversion Memory 8 */
+sfr_w(ADC12MEM9);                             /* ADC12 Conversion Memory 9 */
+sfr_b(ADC12MEM9_L);                           /* ADC12 Conversion Memory 9 */
+sfr_b(ADC12MEM9_H);                           /* ADC12 Conversion Memory 9 */
+sfr_w(ADC12MEM10);                            /* ADC12 Conversion Memory 10 */
+sfr_b(ADC12MEM10_L);                          /* ADC12 Conversion Memory 10 */
+sfr_b(ADC12MEM10_H);                          /* ADC12 Conversion Memory 10 */
+sfr_w(ADC12MEM11);                            /* ADC12 Conversion Memory 11 */
+sfr_b(ADC12MEM11_L);                          /* ADC12 Conversion Memory 11 */
+sfr_b(ADC12MEM11_H);                          /* ADC12 Conversion Memory 11 */
+sfr_w(ADC12MEM12);                            /* ADC12 Conversion Memory 12 */
+sfr_b(ADC12MEM12_L);                          /* ADC12 Conversion Memory 12 */
+sfr_b(ADC12MEM12_H);                          /* ADC12 Conversion Memory 12 */
+sfr_w(ADC12MEM13);                            /* ADC12 Conversion Memory 13 */
+sfr_b(ADC12MEM13_L);                          /* ADC12 Conversion Memory 13 */
+sfr_b(ADC12MEM13_H);                          /* ADC12 Conversion Memory 13 */
+sfr_w(ADC12MEM14);                            /* ADC12 Conversion Memory 14 */
+sfr_b(ADC12MEM14_L);                          /* ADC12 Conversion Memory 14 */
+sfr_b(ADC12MEM14_H);                          /* ADC12 Conversion Memory 14 */
+sfr_w(ADC12MEM15);                            /* ADC12 Conversion Memory 15 */
+sfr_b(ADC12MEM15_L);                          /* ADC12 Conversion Memory 15 */
+sfr_b(ADC12MEM15_H);                          /* ADC12 Conversion Memory 15 */
+sfr_w(ADC12MEM16);                            /* ADC12 Conversion Memory 16 */
+sfr_b(ADC12MEM16_L);                          /* ADC12 Conversion Memory 16 */
+sfr_b(ADC12MEM16_H);                          /* ADC12 Conversion Memory 16 */
+sfr_w(ADC12MEM17);                            /* ADC12 Conversion Memory 17 */
+sfr_b(ADC12MEM17_L);                          /* ADC12 Conversion Memory 17 */
+sfr_b(ADC12MEM17_H);                          /* ADC12 Conversion Memory 17 */
+sfr_w(ADC12MEM18);                            /* ADC12 Conversion Memory 18 */
+sfr_b(ADC12MEM18_L);                          /* ADC12 Conversion Memory 18 */
+sfr_b(ADC12MEM18_H);                          /* ADC12 Conversion Memory 18 */
+sfr_w(ADC12MEM19);                            /* ADC12 Conversion Memory 19 */
+sfr_b(ADC12MEM19_L);                          /* ADC12 Conversion Memory 19 */
+sfr_b(ADC12MEM19_H);                          /* ADC12 Conversion Memory 19 */
+sfr_w(ADC12MEM20);                            /* ADC12 Conversion Memory 20 */
+sfr_b(ADC12MEM20_L);                          /* ADC12 Conversion Memory 20 */
+sfr_b(ADC12MEM20_H);                          /* ADC12 Conversion Memory 20 */
+sfr_w(ADC12MEM21);                            /* ADC12 Conversion Memory 21 */
+sfr_b(ADC12MEM21_L);                          /* ADC12 Conversion Memory 21 */
+sfr_b(ADC12MEM21_H);                          /* ADC12 Conversion Memory 21 */
+sfr_w(ADC12MEM22);                            /* ADC12 Conversion Memory 22 */
+sfr_b(ADC12MEM22_L);                          /* ADC12 Conversion Memory 22 */
+sfr_b(ADC12MEM22_H);                          /* ADC12 Conversion Memory 22 */
+sfr_w(ADC12MEM23);                            /* ADC12 Conversion Memory 23 */
+sfr_b(ADC12MEM23_L);                          /* ADC12 Conversion Memory 23 */
+sfr_b(ADC12MEM23_H);                          /* ADC12 Conversion Memory 23 */
+sfr_w(ADC12MEM24);                            /* ADC12 Conversion Memory 24 */
+sfr_b(ADC12MEM24_L);                          /* ADC12 Conversion Memory 24 */
+sfr_b(ADC12MEM24_H);                          /* ADC12 Conversion Memory 24 */
+sfr_w(ADC12MEM25);                            /* ADC12 Conversion Memory 25 */
+sfr_b(ADC12MEM25_L);                          /* ADC12 Conversion Memory 25 */
+sfr_b(ADC12MEM25_H);                          /* ADC12 Conversion Memory 25 */
+sfr_w(ADC12MEM26);                            /* ADC12 Conversion Memory 26 */
+sfr_b(ADC12MEM26_L);                          /* ADC12 Conversion Memory 26 */
+sfr_b(ADC12MEM26_H);                          /* ADC12 Conversion Memory 26 */
+sfr_w(ADC12MEM27);                            /* ADC12 Conversion Memory 27 */
+sfr_b(ADC12MEM27_L);                          /* ADC12 Conversion Memory 27 */
+sfr_b(ADC12MEM27_H);                          /* ADC12 Conversion Memory 27 */
+sfr_w(ADC12MEM28);                            /* ADC12 Conversion Memory 28 */
+sfr_b(ADC12MEM28_L);                          /* ADC12 Conversion Memory 28 */
+sfr_b(ADC12MEM28_H);                          /* ADC12 Conversion Memory 28 */
+sfr_w(ADC12MEM29);                            /* ADC12 Conversion Memory 29 */
+sfr_b(ADC12MEM29_L);                          /* ADC12 Conversion Memory 29 */
+sfr_b(ADC12MEM29_H);                          /* ADC12 Conversion Memory 29 */
+sfr_w(ADC12MEM30);                            /* ADC12 Conversion Memory 30 */
+sfr_b(ADC12MEM30_L);                          /* ADC12 Conversion Memory 30 */
+sfr_b(ADC12MEM30_H);                          /* ADC12 Conversion Memory 30 */
+sfr_w(ADC12MEM31);                            /* ADC12 Conversion Memory 31 */
+sfr_b(ADC12MEM31_L);                          /* ADC12 Conversion Memory 31 */
+sfr_b(ADC12MEM31_H);                          /* ADC12 Conversion Memory 31 */
+#define ADC12MEM_              ADC12MEM       /* ADC12 Conversion Memory */
+#ifndef __STDC__
+#define ADC12MEM               ADC12MEM0      /* ADC12 Conversion Memory (for assembler) */
+#else
+#define ADC12MEM               ((volatile int*)        &ADC12MEM0) /* ADC12 Conversion Memory (for C) */
+#endif
+
+/* ADC12CTL0 Control Bits */
+#define ADC12SC                (0x0001)       /* ADC12 Start Conversion */
+#define ADC12ENC               (0x0002)       /* ADC12 Enable Conversion */
+#define ADC12ON                (0x0010)       /* ADC12 On/enable */
+#define ADC12MSC               (0x0080)       /* ADC12 Multiple SampleConversion */
+#define ADC12SHT00             (0x0100)       /* ADC12 Sample Hold 0 Select Bit: 0 */
+#define ADC12SHT01             (0x0200)       /* ADC12 Sample Hold 0 Select Bit: 1 */
+#define ADC12SHT02             (0x0400)       /* ADC12 Sample Hold 0 Select Bit: 2 */
+#define ADC12SHT03             (0x0800)       /* ADC12 Sample Hold 0 Select Bit: 3 */
+#define ADC12SHT10             (0x1000)       /* ADC12 Sample Hold 1 Select Bit: 0 */
+#define ADC12SHT11             (0x2000)       /* ADC12 Sample Hold 1 Select Bit: 1 */
+#define ADC12SHT12             (0x4000)       /* ADC12 Sample Hold 1 Select Bit: 2 */
+#define ADC12SHT13             (0x8000)       /* ADC12 Sample Hold 1 Select Bit: 3 */
+
+/* ADC12CTL0 Control Bits */
+#define ADC12SC_L              (0x0001)       /* ADC12 Start Conversion */
+#define ADC12ENC_L             (0x0002)       /* ADC12 Enable Conversion */
+#define ADC12ON_L              (0x0010)       /* ADC12 On/enable */
+#define ADC12MSC_L             (0x0080)       /* ADC12 Multiple SampleConversion */
+
+/* ADC12CTL0 Control Bits */
+#define ADC12SHT00_H           (0x0001)       /* ADC12 Sample Hold 0 Select Bit: 0 */
+#define ADC12SHT01_H           (0x0002)       /* ADC12 Sample Hold 0 Select Bit: 1 */
+#define ADC12SHT02_H           (0x0004)       /* ADC12 Sample Hold 0 Select Bit: 2 */
+#define ADC12SHT03_H           (0x0008)       /* ADC12 Sample Hold 0 Select Bit: 3 */
+#define ADC12SHT10_H           (0x0010)       /* ADC12 Sample Hold 1 Select Bit: 0 */
+#define ADC12SHT11_H           (0x0020)       /* ADC12 Sample Hold 1 Select Bit: 1 */
+#define ADC12SHT12_H           (0x0040)       /* ADC12 Sample Hold 1 Select Bit: 2 */
+#define ADC12SHT13_H           (0x0080)       /* ADC12 Sample Hold 1 Select Bit: 3 */
+
+#define ADC12SHT0_0            (0x0000)       /* ADC12 Sample Hold 0 Select Bit: 0 */
+#define ADC12SHT0_1            (0x0100)       /* ADC12 Sample Hold 0 Select Bit: 1 */
+#define ADC12SHT0_2            (0x0200)       /* ADC12 Sample Hold 0 Select Bit: 2 */
+#define ADC12SHT0_3            (0x0300)       /* ADC12 Sample Hold 0 Select Bit: 3 */
+#define ADC12SHT0_4            (0x0400)       /* ADC12 Sample Hold 0 Select Bit: 4 */
+#define ADC12SHT0_5            (0x0500)       /* ADC12 Sample Hold 0 Select Bit: 5 */
+#define ADC12SHT0_6            (0x0600)       /* ADC12 Sample Hold 0 Select Bit: 6 */
+#define ADC12SHT0_7            (0x0700)       /* ADC12 Sample Hold 0 Select Bit: 7 */
+#define ADC12SHT0_8            (0x0800)       /* ADC12 Sample Hold 0 Select Bit: 8 */
+#define ADC12SHT0_9            (0x0900)       /* ADC12 Sample Hold 0 Select Bit: 9 */
+#define ADC12SHT0_10           (0x0A00)       /* ADC12 Sample Hold 0 Select Bit: 10 */
+#define ADC12SHT0_11           (0x0B00)       /* ADC12 Sample Hold 0 Select Bit: 11 */
+#define ADC12SHT0_12           (0x0C00)       /* ADC12 Sample Hold 0 Select Bit: 12 */
+#define ADC12SHT0_13           (0x0D00)       /* ADC12 Sample Hold 0 Select Bit: 13 */
+#define ADC12SHT0_14           (0x0E00)       /* ADC12 Sample Hold 0 Select Bit: 14 */
+#define ADC12SHT0_15           (0x0F00)       /* ADC12 Sample Hold 0 Select Bit: 15 */
+
+#define ADC12SHT1_0            (0x0000)       /* ADC12 Sample Hold 1 Select Bit: 0 */
+#define ADC12SHT1_1            (0x1000)       /* ADC12 Sample Hold 1 Select Bit: 1 */
+#define ADC12SHT1_2            (0x2000)       /* ADC12 Sample Hold 1 Select Bit: 2 */
+#define ADC12SHT1_3            (0x3000)       /* ADC12 Sample Hold 1 Select Bit: 3 */
+#define ADC12SHT1_4            (0x4000)       /* ADC12 Sample Hold 1 Select Bit: 4 */
+#define ADC12SHT1_5            (0x5000)       /* ADC12 Sample Hold 1 Select Bit: 5 */
+#define ADC12SHT1_6            (0x6000)       /* ADC12 Sample Hold 1 Select Bit: 6 */
+#define ADC12SHT1_7            (0x7000)       /* ADC12 Sample Hold 1 Select Bit: 7 */
+#define ADC12SHT1_8            (0x8000)       /* ADC12 Sample Hold 1 Select Bit: 8 */
+#define ADC12SHT1_9            (0x9000)       /* ADC12 Sample Hold 1 Select Bit: 9 */
+#define ADC12SHT1_10           (0xA000)       /* ADC12 Sample Hold 1 Select Bit: 10 */
+#define ADC12SHT1_11           (0xB000)       /* ADC12 Sample Hold 1 Select Bit: 11 */
+#define ADC12SHT1_12           (0xC000)       /* ADC12 Sample Hold 1 Select Bit: 12 */
+#define ADC12SHT1_13           (0xD000)       /* ADC12 Sample Hold 1 Select Bit: 13 */
+#define ADC12SHT1_14           (0xE000)       /* ADC12 Sample Hold 1 Select Bit: 14 */
+#define ADC12SHT1_15           (0xF000)       /* ADC12 Sample Hold 1 Select Bit: 15 */
+
+/* ADC12CTL1 Control Bits */
+#define ADC12BUSY              (0x0001)       /* ADC12 Busy */
+#define ADC12CONSEQ0           (0x0002)       /* ADC12 Conversion Sequence Select Bit: 0 */
+#define ADC12CONSEQ1           (0x0004)       /* ADC12 Conversion Sequence Select Bit: 1 */
+#define ADC12SSEL0             (0x0008)       /* ADC12 Clock Source Select Bit: 0 */
+#define ADC12SSEL1             (0x0010)       /* ADC12 Clock Source Select Bit: 1 */
+#define ADC12DIV0              (0x0020)       /* ADC12 Clock Divider Select Bit: 0 */
+#define ADC12DIV1              (0x0040)       /* ADC12 Clock Divider Select Bit: 1 */
+#define ADC12DIV2              (0x0080)       /* ADC12 Clock Divider Select Bit: 2 */
+#define ADC12ISSH              (0x0100)       /* ADC12 Invert Sample Hold Signal */
+#define ADC12SHP               (0x0200)       /* ADC12 Sample/Hold Pulse Mode */
+#define ADC12SHS0              (0x0400)       /* ADC12 Sample/Hold Source Bit: 0 */
+#define ADC12SHS1              (0x0800)       /* ADC12 Sample/Hold Source Bit: 1 */
+#define ADC12SHS2              (0x1000)       /* ADC12 Sample/Hold Source Bit: 2 */
+#define ADC12PDIV0             (0x2000)       /* ADC12 Predivider Bit: 0 */
+#define ADC12PDIV1             (0x4000)       /* ADC12 Predivider Bit: 1 */
+
+/* ADC12CTL1 Control Bits */
+#define ADC12BUSY_L            (0x0001)       /* ADC12 Busy */
+#define ADC12CONSEQ0_L         (0x0002)       /* ADC12 Conversion Sequence Select Bit: 0 */
+#define ADC12CONSEQ1_L         (0x0004)       /* ADC12 Conversion Sequence Select Bit: 1 */
+#define ADC12SSEL0_L           (0x0008)       /* ADC12 Clock Source Select Bit: 0 */
+#define ADC12SSEL1_L           (0x0010)       /* ADC12 Clock Source Select Bit: 1 */
+#define ADC12DIV0_L            (0x0020)       /* ADC12 Clock Divider Select Bit: 0 */
+#define ADC12DIV1_L            (0x0040)       /* ADC12 Clock Divider Select Bit: 1 */
+#define ADC12DIV2_L            (0x0080)       /* ADC12 Clock Divider Select Bit: 2 */
+
+/* ADC12CTL1 Control Bits */
+#define ADC12ISSH_H            (0x0001)       /* ADC12 Invert Sample Hold Signal */
+#define ADC12SHP_H             (0x0002)       /* ADC12 Sample/Hold Pulse Mode */
+#define ADC12SHS0_H            (0x0004)       /* ADC12 Sample/Hold Source Bit: 0 */
+#define ADC12SHS1_H            (0x0008)       /* ADC12 Sample/Hold Source Bit: 1 */
+#define ADC12SHS2_H            (0x0010)       /* ADC12 Sample/Hold Source Bit: 2 */
+#define ADC12PDIV0_H           (0x0020)       /* ADC12 Predivider Bit: 0 */
+#define ADC12PDIV1_H           (0x0040)       /* ADC12 Predivider Bit: 1 */
+
+#define ADC12CONSEQ_0          (0x0000)       /* ADC12 Conversion Sequence Select: 0 */
+#define ADC12CONSEQ_1          (0x0002)       /* ADC12 Conversion Sequence Select: 1 */
+#define ADC12CONSEQ_2          (0x0004)       /* ADC12 Conversion Sequence Select: 2 */
+#define ADC12CONSEQ_3          (0x0006)       /* ADC12 Conversion Sequence Select: 3 */
+
+#define ADC12SSEL_0            (0x0000)       /* ADC12 Clock Source Select: 0 */
+#define ADC12SSEL_1            (0x0008)       /* ADC12 Clock Source Select: 1 */
+#define ADC12SSEL_2            (0x0010)       /* ADC12 Clock Source Select: 2 */
+#define ADC12SSEL_3            (0x0018)       /* ADC12 Clock Source Select: 3 */
+
+#define ADC12DIV_0             (0x0000)       /* ADC12 Clock Divider Select: 0 */
+#define ADC12DIV_1             (0x0020)       /* ADC12 Clock Divider Select: 1 */
+#define ADC12DIV_2             (0x0040)       /* ADC12 Clock Divider Select: 2 */
+#define ADC12DIV_3             (0x0060)       /* ADC12 Clock Divider Select: 3 */
+#define ADC12DIV_4             (0x0080)       /* ADC12 Clock Divider Select: 4 */
+#define ADC12DIV_5             (0x00A0)       /* ADC12 Clock Divider Select: 5 */
+#define ADC12DIV_6             (0x00C0)       /* ADC12 Clock Divider Select: 6 */
+#define ADC12DIV_7             (0x00E0)       /* ADC12 Clock Divider Select: 7 */
+
+#define ADC12SHS_0             (0x0000)       /* ADC12 Sample/Hold Source: 0 */
+#define ADC12SHS_1             (0x0400)       /* ADC12 Sample/Hold Source: 1 */
+#define ADC12SHS_2             (0x0800)       /* ADC12 Sample/Hold Source: 2 */
+#define ADC12SHS_3             (0x0C00)       /* ADC12 Sample/Hold Source: 3 */
+#define ADC12SHS_4             (0x1000)       /* ADC12 Sample/Hold Source: 4 */
+#define ADC12SHS_5             (0x1400)       /* ADC12 Sample/Hold Source: 5 */
+#define ADC12SHS_6             (0x1800)       /* ADC12 Sample/Hold Source: 6 */
+#define ADC12SHS_7             (0x1C00)       /* ADC12 Sample/Hold Source: 7 */
+
+#define ADC12PDIV_0            (0x0000)       /* ADC12 Clock predivider Select 0 */
+#define ADC12PDIV_1            (0x2000)       /* ADC12 Clock predivider Select 1 */
+#define ADC12PDIV_2            (0x4000)       /* ADC12 Clock predivider Select 2 */
+#define ADC12PDIV_3            (0x6000)       /* ADC12 Clock predivider Select 3 */
+#define ADC12PDIV__1           (0x0000)       /* ADC12 Clock predivider Select: /1 */
+#define ADC12PDIV__4           (0x2000)       /* ADC12 Clock predivider Select: /4 */
+#define ADC12PDIV__32          (0x4000)       /* ADC12 Clock predivider Select: /32 */
+#define ADC12PDIV__64          (0x6000)       /* ADC12 Clock predivider Select: /64 */
+
+/* ADC12CTL2 Control Bits */
+#define ADC12PWRMD             (0x0001)       /* ADC12 Power Mode */
+#define ADC12DF                (0x0008)       /* ADC12 Data Format */
+#define ADC12RES0              (0x0010)       /* ADC12 Resolution Bit: 0 */
+#define ADC12RES1              (0x0020)       /* ADC12 Resolution Bit: 1 */
+
+/* ADC12CTL2 Control Bits */
+#define ADC12PWRMD_L           (0x0001)       /* ADC12 Power Mode */
+#define ADC12DF_L              (0x0008)       /* ADC12 Data Format */
+#define ADC12RES0_L            (0x0010)       /* ADC12 Resolution Bit: 0 */
+#define ADC12RES1_L            (0x0020)       /* ADC12 Resolution Bit: 1 */
+
+#define ADC12RES_0             (0x0000)       /* ADC12+ Resolution : 8 Bit */
+#define ADC12RES_1             (0x0010)       /* ADC12+ Resolution : 10 Bit */
+#define ADC12RES_2             (0x0020)       /* ADC12+ Resolution : 12 Bit */
+#define ADC12RES_3             (0x0030)       /* ADC12+ Resolution : reserved */
+
+#define ADC12RES__8BIT         (0x0000)       /* ADC12+ Resolution : 8 Bit */
+#define ADC12RES__10BIT        (0x0010)       /* ADC12+ Resolution : 10 Bit */
+#define ADC12RES__12BIT        (0x0020)       /* ADC12+ Resolution : 12 Bit */
+
+/* ADC12CTL3 Control Bits */
+#define ADC12CSTARTADD0        (0x0001)       /* ADC12 Conversion Start Address Bit: 0 */
+#define ADC12CSTARTADD1        (0x0002)       /* ADC12 Conversion Start Address Bit: 1 */
+#define ADC12CSTARTADD2        (0x0004)       /* ADC12 Conversion Start Address Bit: 2 */
+#define ADC12CSTARTADD3        (0x0008)       /* ADC12 Conversion Start Address Bit: 3 */
+#define ADC12CSTARTADD4        (0x0010)       /* ADC12 Conversion Start Address Bit: 4 */
+#define ADC12BATMAP            (0x0040)       /* ADC12 Internal AVCC/2 select */
+#define ADC12TCMAP             (0x0080)       /* ADC12 Internal TempSensor select */
+#define ADC12ICH0MAP           (0x0100)       /* ADC12 Internal Channel 0 select */
+#define ADC12ICH1MAP           (0x0200)       /* ADC12 Internal Channel 1 select */
+#define ADC12ICH2MAP           (0x0400)       /* ADC12 Internal Channel 2 select */
+#define ADC12ICH3MAP           (0x0800)       /* ADC12 Internal Channel 3 select */
+
+/* ADC12CTL3 Control Bits */
+#define ADC12CSTARTADD0_L      (0x0001)       /* ADC12 Conversion Start Address Bit: 0 */
+#define ADC12CSTARTADD1_L      (0x0002)       /* ADC12 Conversion Start Address Bit: 1 */
+#define ADC12CSTARTADD2_L      (0x0004)       /* ADC12 Conversion Start Address Bit: 2 */
+#define ADC12CSTARTADD3_L      (0x0008)       /* ADC12 Conversion Start Address Bit: 3 */
+#define ADC12CSTARTADD4_L      (0x0010)       /* ADC12 Conversion Start Address Bit: 4 */
+#define ADC12BATMAP_L          (0x0040)       /* ADC12 Internal AVCC/2 select */
+#define ADC12TCMAP_L           (0x0080)       /* ADC12 Internal TempSensor select */
+
+/* ADC12CTL3 Control Bits */
+#define ADC12ICH0MAP_H         (0x0001)       /* ADC12 Internal Channel 0 select */
+#define ADC12ICH1MAP_H         (0x0002)       /* ADC12 Internal Channel 1 select */
+#define ADC12ICH2MAP_H         (0x0004)       /* ADC12 Internal Channel 2 select */
+#define ADC12ICH3MAP_H         (0x0008)       /* ADC12 Internal Channel 3 select */
+
+#define ADC12CSTARTADD_0       (0x0000)       /* ADC12 Conversion Start Address: 0 */
+#define ADC12CSTARTADD_1       (0x0001)       /* ADC12 Conversion Start Address: 1 */
+#define ADC12CSTARTADD_2       (0x0002)       /* ADC12 Conversion Start Address: 2 */
+#define ADC12CSTARTADD_3       (0x0003)       /* ADC12 Conversion Start Address: 3 */
+#define ADC12CSTARTADD_4       (0x0004)       /* ADC12 Conversion Start Address: 4 */
+#define ADC12CSTARTADD_5       (0x0005)       /* ADC12 Conversion Start Address: 5 */
+#define ADC12CSTARTADD_6       (0x0006)       /* ADC12 Conversion Start Address: 6 */
+#define ADC12CSTARTADD_7       (0x0007)       /* ADC12 Conversion Start Address: 7 */
+#define ADC12CSTARTADD_8       (0x0008)       /* ADC12 Conversion Start Address: 8 */
+#define ADC12CSTARTADD_9       (0x0009)       /* ADC12 Conversion Start Address: 9 */
+#define ADC12CSTARTADD_10      (0x000A)       /* ADC12 Conversion Start Address: 10 */
+#define ADC12CSTARTADD_11      (0x000B)       /* ADC12 Conversion Start Address: 11 */
+#define ADC12CSTARTADD_12      (0x000C)       /* ADC12 Conversion Start Address: 12 */
+#define ADC12CSTARTADD_13      (0x000D)       /* ADC12 Conversion Start Address: 13 */
+#define ADC12CSTARTADD_14      (0x000E)       /* ADC12 Conversion Start Address: 14 */
+#define ADC12CSTARTADD_15      (0x000F)       /* ADC12 Conversion Start Address: 15 */
+#define ADC12CSTARTADD_16      (0x0010)       /* ADC12 Conversion Start Address: 16 */
+#define ADC12CSTARTADD_17      (0x0011)       /* ADC12 Conversion Start Address: 17 */
+#define ADC12CSTARTADD_18      (0x0012)       /* ADC12 Conversion Start Address: 18 */
+#define ADC12CSTARTADD_19      (0x0013)       /* ADC12 Conversion Start Address: 19 */
+#define ADC12CSTARTADD_20      (0x0014)       /* ADC12 Conversion Start Address: 20 */
+#define ADC12CSTARTADD_21      (0x0015)       /* ADC12 Conversion Start Address: 21 */
+#define ADC12CSTARTADD_22      (0x0016)       /* ADC12 Conversion Start Address: 22 */
+#define ADC12CSTARTADD_23      (0x0017)       /* ADC12 Conversion Start Address: 23 */
+#define ADC12CSTARTADD_24      (0x0018)       /* ADC12 Conversion Start Address: 24 */
+#define ADC12CSTARTADD_25      (0x0019)       /* ADC12 Conversion Start Address: 25 */
+#define ADC12CSTARTADD_26      (0x001A)       /* ADC12 Conversion Start Address: 26 */
+#define ADC12CSTARTADD_27      (0x001B)       /* ADC12 Conversion Start Address: 27 */
+#define ADC12CSTARTADD_28      (0x001C)       /* ADC12 Conversion Start Address: 28 */
+#define ADC12CSTARTADD_29      (0x001D)       /* ADC12 Conversion Start Address: 29 */
+#define ADC12CSTARTADD_30      (0x001E)       /* ADC12 Conversion Start Address: 30 */
+#define ADC12CSTARTADD_31      (0x001F)       /* ADC12 Conversion Start Address: 31 */
+
+/* ADC12MCTLx Control Bits */
+#define ADC12INCH0             (0x0001)       /* ADC12 Input Channel Select Bit 0 */
+#define ADC12INCH1             (0x0002)       /* ADC12 Input Channel Select Bit 1 */
+#define ADC12INCH2             (0x0004)       /* ADC12 Input Channel Select Bit 2 */
+#define ADC12INCH3             (0x0008)       /* ADC12 Input Channel Select Bit 3 */
+#define ADC12INCH4             (0x0010)       /* ADC12 Input Channel Select Bit 4 */
+#define ADC12EOS               (0x0080)       /* ADC12 End of Sequence */
+#define ADC12VRSEL0            (0x0100)       /* ADC12 VR Select Bit 0 */
+#define ADC12VRSEL1            (0x0200)       /* ADC12 VR Select Bit 1 */
+#define ADC12VRSEL2            (0x0400)       /* ADC12 VR Select Bit 2 */
+#define ADC12VRSEL3            (0x0800)       /* ADC12 VR Select Bit 3 */
+#define ADC12DIF               (0x2000)       /* ADC12 Differential mode (only for even Registers) */
+#define ADC12WINC              (0x4000)       /* ADC12 Comparator window enable */
+
+/* ADC12MCTLx Control Bits */
+#define ADC12INCH0_L           (0x0001)       /* ADC12 Input Channel Select Bit 0 */
+#define ADC12INCH1_L           (0x0002)       /* ADC12 Input Channel Select Bit 1 */
+#define ADC12INCH2_L           (0x0004)       /* ADC12 Input Channel Select Bit 2 */
+#define ADC12INCH3_L           (0x0008)       /* ADC12 Input Channel Select Bit 3 */
+#define ADC12INCH4_L           (0x0010)       /* ADC12 Input Channel Select Bit 4 */
+#define ADC12EOS_L             (0x0080)       /* ADC12 End of Sequence */
+
+/* ADC12MCTLx Control Bits */
+#define ADC12VRSEL0_H          (0x0001)       /* ADC12 VR Select Bit 0 */
+#define ADC12VRSEL1_H          (0x0002)       /* ADC12 VR Select Bit 1 */
+#define ADC12VRSEL2_H          (0x0004)       /* ADC12 VR Select Bit 2 */
+#define ADC12VRSEL3_H          (0x0008)       /* ADC12 VR Select Bit 3 */
+#define ADC12DIF_H             (0x0020)       /* ADC12 Differential mode (only for even Registers) */
+#define ADC12WINC_H            (0x0040)       /* ADC12 Comparator window enable */
+
+#define ADC12INCH_0            (0x0000)       /* ADC12 Input Channel 0 */
+#define ADC12INCH_1            (0x0001)       /* ADC12 Input Channel 1 */
+#define ADC12INCH_2            (0x0002)       /* ADC12 Input Channel 2 */
+#define ADC12INCH_3            (0x0003)       /* ADC12 Input Channel 3 */
+#define ADC12INCH_4            (0x0004)       /* ADC12 Input Channel 4 */
+#define ADC12INCH_5            (0x0005)       /* ADC12 Input Channel 5 */
+#define ADC12INCH_6            (0x0006)       /* ADC12 Input Channel 6 */
+#define ADC12INCH_7            (0x0007)       /* ADC12 Input Channel 7 */
+#define ADC12INCH_8            (0x0008)       /* ADC12 Input Channel 8 */
+#define ADC12INCH_9            (0x0009)       /* ADC12 Input Channel 9 */
+#define ADC12INCH_10           (0x000A)       /* ADC12 Input Channel 10 */
+#define ADC12INCH_11           (0x000B)       /* ADC12 Input Channel 11 */
+#define ADC12INCH_12           (0x000C)       /* ADC12 Input Channel 12 */
+#define ADC12INCH_13           (0x000D)       /* ADC12 Input Channel 13 */
+#define ADC12INCH_14           (0x000E)       /* ADC12 Input Channel 14 */
+#define ADC12INCH_15           (0x000F)       /* ADC12 Input Channel 15 */
+#define ADC12INCH_16           (0x0010)       /* ADC12 Input Channel 16 */
+#define ADC12INCH_17           (0x0011)       /* ADC12 Input Channel 17 */
+#define ADC12INCH_18           (0x0012)       /* ADC12 Input Channel 18 */
+#define ADC12INCH_19           (0x0013)       /* ADC12 Input Channel 19 */
+#define ADC12INCH_20           (0x0014)       /* ADC12 Input Channel 20 */
+#define ADC12INCH_21           (0x0015)       /* ADC12 Input Channel 21 */
+#define ADC12INCH_22           (0x0016)       /* ADC12 Input Channel 22 */
+#define ADC12INCH_23           (0x0017)       /* ADC12 Input Channel 23 */
+#define ADC12INCH_24           (0x0018)       /* ADC12 Input Channel 24 */
+#define ADC12INCH_25           (0x0019)       /* ADC12 Input Channel 25 */
+#define ADC12INCH_26           (0x001A)       /* ADC12 Input Channel 26 */
+#define ADC12INCH_27           (0x001B)       /* ADC12 Input Channel 27 */
+#define ADC12INCH_28           (0x001C)       /* ADC12 Input Channel 28 */
+#define ADC12INCH_29           (0x001D)       /* ADC12 Input Channel 29 */
+#define ADC12INCH_30           (0x001E)       /* ADC12 Input Channel 30 */
+#define ADC12INCH_31           (0x001F)       /* ADC12 Input Channel 31 */
+
+#define ADC12VRSEL_0           (0x0000)       /* ADC12 Select Reference 0 */
+#define ADC12VRSEL_1           (0x0100)       /* ADC12 Select Reference 1 */
+#define ADC12VRSEL_2           (0x0200)       /* ADC12 Select Reference 2 */
+#define ADC12VRSEL_3           (0x0300)       /* ADC12 Select Reference 3 */
+#define ADC12VRSEL_4           (0x0400)       /* ADC12 Select Reference 4 */
+#define ADC12VRSEL_5           (0x0500)       /* ADC12 Select Reference 5 */
+#define ADC12VRSEL_6           (0x0600)       /* ADC12 Select Reference 6 */
+#define ADC12VRSEL_7           (0x0700)       /* ADC12 Select Reference 7 */
+#define ADC12VRSEL_8           (0x0800)       /* ADC12 Select Reference 8  */
+#define ADC12VRSEL_9           (0x0900)       /* ADC12 Select Reference 9  */
+#define ADC12VRSEL_10          (0x0A00)       /* ADC12 Select Reference 10 */
+#define ADC12VRSEL_11          (0x0B00)       /* ADC12 Select Reference 11 */
+#define ADC12VRSEL_12          (0x0C00)       /* ADC12 Select Reference 12 */
+#define ADC12VRSEL_13          (0x0D00)       /* ADC12 Select Reference 13 */
+#define ADC12VRSEL_14          (0x0E00)       /* ADC12 Select Reference 14 */
+#define ADC12VRSEL_15          (0x0F00)       /* ADC12 Select Reference 15 */
+
+/* ADC12HI Control Bits */
+
+/* ADC12LO Control Bits */
+
+/* ADC12IER0 Control Bits */
+#define ADC12IE0               (0x0001)       /* ADC12 Memory 0 Interrupt Enable */
+#define ADC12IE1               (0x0002)       /* ADC12 Memory 1 Interrupt Enable */
+#define ADC12IE2               (0x0004)       /* ADC12 Memory 2 Interrupt Enable */
+#define ADC12IE3               (0x0008)       /* ADC12 Memory 3 Interrupt Enable */
+#define ADC12IE4               (0x0010)       /* ADC12 Memory 4 Interrupt Enable */
+#define ADC12IE5               (0x0020)       /* ADC12 Memory 5 Interrupt Enable */
+#define ADC12IE6               (0x0040)       /* ADC12 Memory 6 Interrupt Enable */
+#define ADC12IE7               (0x0080)       /* ADC12 Memory 7 Interrupt Enable */
+#define ADC12IE8               (0x0100)       /* ADC12 Memory 8 Interrupt Enable */
+#define ADC12IE9               (0x0200)       /* ADC12 Memory 9 Interrupt Enable */
+#define ADC12IE10              (0x0400)       /* ADC12 Memory 10 Interrupt Enable */
+#define ADC12IE11              (0x0800)       /* ADC12 Memory 11 Interrupt Enable */
+#define ADC12IE12              (0x1000)       /* ADC12 Memory 12 Interrupt Enable */
+#define ADC12IE13              (0x2000)       /* ADC12 Memory 13 Interrupt Enable */
+#define ADC12IE14              (0x4000)       /* ADC12 Memory 14 Interrupt Enable */
+#define ADC12IE15              (0x8000)       /* ADC12 Memory 15 Interrupt Enable */
+
+/* ADC12IER0 Control Bits */
+#define ADC12IE0_L             (0x0001)       /* ADC12 Memory 0 Interrupt Enable */
+#define ADC12IE1_L             (0x0002)       /* ADC12 Memory 1 Interrupt Enable */
+#define ADC12IE2_L             (0x0004)       /* ADC12 Memory 2 Interrupt Enable */
+#define ADC12IE3_L             (0x0008)       /* ADC12 Memory 3 Interrupt Enable */
+#define ADC12IE4_L             (0x0010)       /* ADC12 Memory 4 Interrupt Enable */
+#define ADC12IE5_L             (0x0020)       /* ADC12 Memory 5 Interrupt Enable */
+#define ADC12IE6_L             (0x0040)       /* ADC12 Memory 6 Interrupt Enable */
+#define ADC12IE7_L             (0x0080)       /* ADC12 Memory 7 Interrupt Enable */
+
+/* ADC12IER0 Control Bits */
+#define ADC12IE8_H             (0x0001)       /* ADC12 Memory 8 Interrupt Enable */
+#define ADC12IE9_H             (0x0002)       /* ADC12 Memory 9 Interrupt Enable */
+#define ADC12IE10_H            (0x0004)       /* ADC12 Memory 10 Interrupt Enable */
+#define ADC12IE11_H            (0x0008)       /* ADC12 Memory 11 Interrupt Enable */
+#define ADC12IE12_H            (0x0010)       /* ADC12 Memory 12 Interrupt Enable */
+#define ADC12IE13_H            (0x0020)       /* ADC12 Memory 13 Interrupt Enable */
+#define ADC12IE14_H            (0x0040)       /* ADC12 Memory 14 Interrupt Enable */
+#define ADC12IE15_H            (0x0080)       /* ADC12 Memory 15 Interrupt Enable */
+
+/* ADC12IER1 Control Bits */
+#define ADC12IE16              (0x0001)       /* ADC12 Memory 16 Interrupt Enable */
+#define ADC12IE17              (0x0002)       /* ADC12 Memory 17 Interrupt Enable */
+#define ADC12IE18              (0x0004)       /* ADC12 Memory 18 Interrupt Enable */
+#define ADC12IE19              (0x0008)       /* ADC12 Memory 19 Interrupt Enable */
+#define ADC12IE20              (0x0010)       /* ADC12 Memory 20 Interrupt Enable */
+#define ADC12IE21              (0x0020)       /* ADC12 Memory 21 Interrupt Enable */
+#define ADC12IE22              (0x0040)       /* ADC12 Memory 22 Interrupt Enable */
+#define ADC12IE23              (0x0080)       /* ADC12 Memory 23 Interrupt Enable */
+#define ADC12IE24              (0x0100)       /* ADC12 Memory 24 Interrupt Enable */
+#define ADC12IE25              (0x0200)       /* ADC12 Memory 25 Interrupt Enable */
+#define ADC12IE26              (0x0400)       /* ADC12 Memory 26 Interrupt Enable */
+#define ADC12IE27              (0x0800)       /* ADC12 Memory 27 Interrupt Enable */
+#define ADC12IE28              (0x1000)       /* ADC12 Memory 28 Interrupt Enable */
+#define ADC12IE29              (0x2000)       /* ADC12 Memory 29 Interrupt Enable */
+#define ADC12IE30              (0x4000)       /* ADC12 Memory 30 Interrupt Enable */
+#define ADC12IE31              (0x8000)       /* ADC12 Memory 31 Interrupt Enable */
+
+/* ADC12IER1 Control Bits */
+#define ADC12IE16_L            (0x0001)       /* ADC12 Memory 16 Interrupt Enable */
+#define ADC12IE17_L            (0x0002)       /* ADC12 Memory 17 Interrupt Enable */
+#define ADC12IE18_L            (0x0004)       /* ADC12 Memory 18 Interrupt Enable */
+#define ADC12IE19_L            (0x0008)       /* ADC12 Memory 19 Interrupt Enable */
+#define ADC12IE20_L            (0x0010)       /* ADC12 Memory 20 Interrupt Enable */
+#define ADC12IE21_L            (0x0020)       /* ADC12 Memory 21 Interrupt Enable */
+#define ADC12IE22_L            (0x0040)       /* ADC12 Memory 22 Interrupt Enable */
+#define ADC12IE23_L            (0x0080)       /* ADC12 Memory 23 Interrupt Enable */
+
+/* ADC12IER1 Control Bits */
+#define ADC12IE24_H            (0x0001)       /* ADC12 Memory 24 Interrupt Enable */
+#define ADC12IE25_H            (0x0002)       /* ADC12 Memory 25 Interrupt Enable */
+#define ADC12IE26_H            (0x0004)       /* ADC12 Memory 26 Interrupt Enable */
+#define ADC12IE27_H            (0x0008)       /* ADC12 Memory 27 Interrupt Enable */
+#define ADC12IE28_H            (0x0010)       /* ADC12 Memory 28 Interrupt Enable */
+#define ADC12IE29_H            (0x0020)       /* ADC12 Memory 29 Interrupt Enable */
+#define ADC12IE30_H            (0x0040)       /* ADC12 Memory 30 Interrupt Enable */
+#define ADC12IE31_H            (0x0080)       /* ADC12 Memory 31 Interrupt Enable */
+
+/* ADC12IER2 Control Bits */
+#define ADC12INIE              (0x0002)       /* ADC12 Interrupt enable for the inside of window of the Window comparator */
+#define ADC12LOIE              (0x0004)       /* ADC12 Interrupt enable for lower threshold of the Window comparator */
+#define ADC12HIIE              (0x0008)       /* ADC12 Interrupt enable for upper threshold of the Window comparator */
+#define ADC12OVIE              (0x0010)       /* ADC12 ADC12MEMx Overflow interrupt enable */
+#define ADC12TOVIE             (0x0020)       /* ADC12 Timer Overflow interrupt enable */
+#define ADC12RDYIE             (0x0040)       /* ADC12 local buffered reference ready interrupt enable */
+
+/* ADC12IER2 Control Bits */
+#define ADC12INIE_L            (0x0002)       /* ADC12 Interrupt enable for the inside of window of the Window comparator */
+#define ADC12LOIE_L            (0x0004)       /* ADC12 Interrupt enable for lower threshold of the Window comparator */
+#define ADC12HIIE_L            (0x0008)       /* ADC12 Interrupt enable for upper threshold of the Window comparator */
+#define ADC12OVIE_L            (0x0010)       /* ADC12 ADC12MEMx Overflow interrupt enable */
+#define ADC12TOVIE_L           (0x0020)       /* ADC12 Timer Overflow interrupt enable */
+#define ADC12RDYIE_L           (0x0040)       /* ADC12 local buffered reference ready interrupt enable */
+
+/* ADC12IFGR0 Control Bits */
+#define ADC12IFG0              (0x0001)       /* ADC12 Memory 0 Interrupt Flag */
+#define ADC12IFG1              (0x0002)       /* ADC12 Memory 1 Interrupt Flag */
+#define ADC12IFG2              (0x0004)       /* ADC12 Memory 2 Interrupt Flag */
+#define ADC12IFG3              (0x0008)       /* ADC12 Memory 3 Interrupt Flag */
+#define ADC12IFG4              (0x0010)       /* ADC12 Memory 4 Interrupt Flag */
+#define ADC12IFG5              (0x0020)       /* ADC12 Memory 5 Interrupt Flag */
+#define ADC12IFG6              (0x0040)       /* ADC12 Memory 6 Interrupt Flag */
+#define ADC12IFG7              (0x0080)       /* ADC12 Memory 7 Interrupt Flag */
+#define ADC12IFG8              (0x0100)       /* ADC12 Memory 8 Interrupt Flag */
+#define ADC12IFG9              (0x0200)       /* ADC12 Memory 9 Interrupt Flag */
+#define ADC12IFG10             (0x0400)       /* ADC12 Memory 10 Interrupt Flag */
+#define ADC12IFG11             (0x0800)       /* ADC12 Memory 11 Interrupt Flag */
+#define ADC12IFG12             (0x1000)       /* ADC12 Memory 12 Interrupt Flag */
+#define ADC12IFG13             (0x2000)       /* ADC12 Memory 13 Interrupt Flag */
+#define ADC12IFG14             (0x4000)       /* ADC12 Memory 14 Interrupt Flag */
+#define ADC12IFG15             (0x8000)       /* ADC12 Memory 15 Interrupt Flag */
+
+/* ADC12IFGR0 Control Bits */
+#define ADC12IFG0_L            (0x0001)       /* ADC12 Memory 0 Interrupt Flag */
+#define ADC12IFG1_L            (0x0002)       /* ADC12 Memory 1 Interrupt Flag */
+#define ADC12IFG2_L            (0x0004)       /* ADC12 Memory 2 Interrupt Flag */
+#define ADC12IFG3_L            (0x0008)       /* ADC12 Memory 3 Interrupt Flag */
+#define ADC12IFG4_L            (0x0010)       /* ADC12 Memory 4 Interrupt Flag */
+#define ADC12IFG5_L            (0x0020)       /* ADC12 Memory 5 Interrupt Flag */
+#define ADC12IFG6_L            (0x0040)       /* ADC12 Memory 6 Interrupt Flag */
+#define ADC12IFG7_L            (0x0080)       /* ADC12 Memory 7 Interrupt Flag */
+
+/* ADC12IFGR0 Control Bits */
+#define ADC12IFG8_H            (0x0001)       /* ADC12 Memory 8 Interrupt Flag */
+#define ADC12IFG9_H            (0x0002)       /* ADC12 Memory 9 Interrupt Flag */
+#define ADC12IFG10_H           (0x0004)       /* ADC12 Memory 10 Interrupt Flag */
+#define ADC12IFG11_H           (0x0008)       /* ADC12 Memory 11 Interrupt Flag */
+#define ADC12IFG12_H           (0x0010)       /* ADC12 Memory 12 Interrupt Flag */
+#define ADC12IFG13_H           (0x0020)       /* ADC12 Memory 13 Interrupt Flag */
+#define ADC12IFG14_H           (0x0040)       /* ADC12 Memory 14 Interrupt Flag */
+#define ADC12IFG15_H           (0x0080)       /* ADC12 Memory 15 Interrupt Flag */
+
+/* ADC12IFGR1 Control Bits */
+#define ADC12IFG16             (0x0001)       /* ADC12 Memory 16 Interrupt Flag */
+#define ADC12IFG17             (0x0002)       /* ADC12 Memory 17 Interrupt Flag */
+#define ADC12IFG18             (0x0004)       /* ADC12 Memory 18 Interrupt Flag */
+#define ADC12IFG19             (0x0008)       /* ADC12 Memory 19 Interrupt Flag */
+#define ADC12IFG20             (0x0010)       /* ADC12 Memory 20 Interrupt Flag */
+#define ADC12IFG21             (0x0020)       /* ADC12 Memory 21 Interrupt Flag */
+#define ADC12IFG22             (0x0040)       /* ADC12 Memory 22 Interrupt Flag */
+#define ADC12IFG23             (0x0080)       /* ADC12 Memory 23 Interrupt Flag */
+#define ADC12IFG24             (0x0100)       /* ADC12 Memory 24 Interrupt Flag */
+#define ADC12IFG25             (0x0200)       /* ADC12 Memory 25 Interrupt Flag */
+#define ADC12IFG26             (0x0400)       /* ADC12 Memory 26 Interrupt Flag */
+#define ADC12IFG27             (0x0800)       /* ADC12 Memory 27 Interrupt Flag */
+#define ADC12IFG28             (0x1000)       /* ADC12 Memory 28 Interrupt Flag */
+#define ADC12IFG29             (0x2000)       /* ADC12 Memory 29 Interrupt Flag */
+#define ADC12IFG30             (0x4000)       /* ADC12 Memory 30 Interrupt Flag */
+#define ADC12IFG31             (0x8000)       /* ADC12 Memory 31 Interrupt Flag */
+
+/* ADC12IFGR1 Control Bits */
+#define ADC12IFG16_L           (0x0001)       /* ADC12 Memory 16 Interrupt Flag */
+#define ADC12IFG17_L           (0x0002)       /* ADC12 Memory 17 Interrupt Flag */
+#define ADC12IFG18_L           (0x0004)       /* ADC12 Memory 18 Interrupt Flag */
+#define ADC12IFG19_L           (0x0008)       /* ADC12 Memory 19 Interrupt Flag */
+#define ADC12IFG20_L           (0x0010)       /* ADC12 Memory 20 Interrupt Flag */
+#define ADC12IFG21_L           (0x0020)       /* ADC12 Memory 21 Interrupt Flag */
+#define ADC12IFG22_L           (0x0040)       /* ADC12 Memory 22 Interrupt Flag */
+#define ADC12IFG23_L           (0x0080)       /* ADC12 Memory 23 Interrupt Flag */
+
+/* ADC12IFGR1 Control Bits */
+#define ADC12IFG24_H           (0x0001)       /* ADC12 Memory 24 Interrupt Flag */
+#define ADC12IFG25_H           (0x0002)       /* ADC12 Memory 25 Interrupt Flag */
+#define ADC12IFG26_H           (0x0004)       /* ADC12 Memory 26 Interrupt Flag */
+#define ADC12IFG27_H           (0x0008)       /* ADC12 Memory 27 Interrupt Flag */
+#define ADC12IFG28_H           (0x0010)       /* ADC12 Memory 28 Interrupt Flag */
+#define ADC12IFG29_H           (0x0020)       /* ADC12 Memory 29 Interrupt Flag */
+#define ADC12IFG30_H           (0x0040)       /* ADC12 Memory 30 Interrupt Flag */
+#define ADC12IFG31_H           (0x0080)       /* ADC12 Memory 31 Interrupt Flag */
+
+/* ADC12IFGR2 Control Bits */
+#define ADC12INIFG             (0x0002)       /* ADC12 Interrupt Flag for the inside of window of the Window comparator */
+#define ADC12LOIFG             (0x0004)       /* ADC12 Interrupt Flag for lower threshold of the Window comparator */
+#define ADC12HIIFG             (0x0008)       /* ADC12 Interrupt Flag for upper threshold of the Window comparator */
+#define ADC12OVIFG             (0x0010)       /* ADC12 ADC12MEMx Overflow interrupt Flag */
+#define ADC12TOVIFG            (0x0020)       /* ADC12 Timer Overflow interrupt Flag */
+#define ADC12RDYIFG            (0x0040)       /* ADC12 local buffered reference ready interrupt Flag */
+
+/* ADC12IFGR2 Control Bits */
+#define ADC12INIFG_L           (0x0002)       /* ADC12 Interrupt Flag for the inside of window of the Window comparator */
+#define ADC12LOIFG_L           (0x0004)       /* ADC12 Interrupt Flag for lower threshold of the Window comparator */
+#define ADC12HIIFG_L           (0x0008)       /* ADC12 Interrupt Flag for upper threshold of the Window comparator */
+#define ADC12OVIFG_L           (0x0010)       /* ADC12 ADC12MEMx Overflow interrupt Flag */
+#define ADC12TOVIFG_L          (0x0020)       /* ADC12 Timer Overflow interrupt Flag */
+#define ADC12RDYIFG_L          (0x0040)       /* ADC12 local buffered reference ready interrupt Flag */
+
+/* ADC12IV Definitions */
+#define ADC12IV_NONE           (0x0000)       /* No Interrupt pending */
+#define ADC12IV_ADC12OVIFG     (0x0002)       /* ADC12OVIFG */
+#define ADC12IV_ADC12TOVIFG    (0x0004)       /* ADC12TOVIFG */
+#define ADC12IV_ADC12HIIFG     (0x0006)       /* ADC12HIIFG */
+#define ADC12IV_ADC12LOIFG     (0x0008)       /* ADC12LOIFG */
+#define ADC12IV_ADC12INIFG     (0x000A)       /* ADC12INIFG */
+#define ADC12IV_ADC12IFG0      (0x000C)       /* ADC12IFG0 */
+#define ADC12IV_ADC12IFG1      (0x000E)       /* ADC12IFG1 */
+#define ADC12IV_ADC12IFG2      (0x0010)       /* ADC12IFG2 */
+#define ADC12IV_ADC12IFG3      (0x0012)       /* ADC12IFG3 */
+#define ADC12IV_ADC12IFG4      (0x0014)       /* ADC12IFG4 */
+#define ADC12IV_ADC12IFG5      (0x0016)       /* ADC12IFG5 */
+#define ADC12IV_ADC12IFG6      (0x0018)       /* ADC12IFG6 */
+#define ADC12IV_ADC12IFG7      (0x001A)       /* ADC12IFG7 */
+#define ADC12IV_ADC12IFG8      (0x001C)       /* ADC12IFG8 */
+#define ADC12IV_ADC12IFG9      (0x001E)       /* ADC12IFG9 */
+#define ADC12IV_ADC12IFG10     (0x0020)       /* ADC12IFG10 */
+#define ADC12IV_ADC12IFG11     (0x0022)       /* ADC12IFG11 */
+#define ADC12IV_ADC12IFG12     (0x0024)       /* ADC12IFG12 */
+#define ADC12IV_ADC12IFG13     (0x0026)       /* ADC12IFG13 */
+#define ADC12IV_ADC12IFG14     (0x0028)       /* ADC12IFG14 */
+#define ADC12IV_ADC12IFG15     (0x002A)       /* ADC12IFG15 */
+#define ADC12IV_ADC12IFG16     (0x002C)       /* ADC12IFG16 */
+#define ADC12IV_ADC12IFG17     (0x002E)       /* ADC12IFG17 */
+#define ADC12IV_ADC12IFG18     (0x0030)       /* ADC12IFG18 */
+#define ADC12IV_ADC12IFG19     (0x0032)       /* ADC12IFG19 */
+#define ADC12IV_ADC12IFG20     (0x0034)       /* ADC12IFG20 */
+#define ADC12IV_ADC12IFG21     (0x0036)       /* ADC12IFG21 */
+#define ADC12IV_ADC12IFG22     (0x0038)       /* ADC12IFG22 */
+#define ADC12IV_ADC12IFG23     (0x003A)       /* ADC12IFG23 */
+#define ADC12IV_ADC12IFG24     (0x003C)       /* ADC12IFG24 */
+#define ADC12IV_ADC12IFG25     (0x003E)       /* ADC12IFG25 */
+#define ADC12IV_ADC12IFG26     (0x0040)       /* ADC12IFG26 */
+#define ADC12IV_ADC12IFG27     (0x0042)       /* ADC12IFG27 */
+#define ADC12IV_ADC12IFG28     (0x0044)       /* ADC12IFG28 */
+#define ADC12IV_ADC12IFG29     (0x0046)       /* ADC12IFG29 */
+#define ADC12IV_ADC12IFG30     (0x0048)       /* ADC12IFG30 */
+#define ADC12IV_ADC12IFG31     (0x004A)       /* ADC12IFG31 */
+#define ADC12IV_ADC12RDYIFG    (0x004C)       /* ADC12RDYIFG */
+
+
+/************************************************************
+* AES256 Accelerator
+************************************************************/
+#define __MSP430_HAS_AES256__                 /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_AES256__ 0x09C0
+#define AES256_BASE            __MSP430_BASEADDRESS_AES256__
+
+sfr_w(AESACTL0);                              /* AES accelerator control register 0 */
+sfr_b(AESACTL0_L);                            /* AES accelerator control register 0 */
+sfr_b(AESACTL0_H);                            /* AES accelerator control register 0 */
+sfr_w(AESACTL1);                              /* AES accelerator control register 1 */
+sfr_b(AESACTL1_L);                            /* AES accelerator control register 1 */
+sfr_b(AESACTL1_H);                            /* AES accelerator control register 1 */
+sfr_w(AESASTAT);                              /* AES accelerator status register */
+sfr_b(AESASTAT_L);                            /* AES accelerator status register */
+sfr_b(AESASTAT_H);                            /* AES accelerator status register */
+sfr_w(AESAKEY);                               /* AES accelerator key register */
+sfr_b(AESAKEY_L);                             /* AES accelerator key register */
+sfr_b(AESAKEY_H);                             /* AES accelerator key register */
+sfr_w(AESADIN);                               /* AES accelerator data in register */
+sfr_b(AESADIN_L);                             /* AES accelerator data in register */
+sfr_b(AESADIN_H);                             /* AES accelerator data in register */
+sfr_w(AESADOUT);                              /* AES accelerator data out register  */
+sfr_b(AESADOUT_L);                            /* AES accelerator data out register  */
+sfr_b(AESADOUT_H);                            /* AES accelerator data out register  */
+sfr_w(AESAXDIN);                              /* AES accelerator XORed data in register */
+sfr_b(AESAXDIN_L);                            /* AES accelerator XORed data in register */
+sfr_b(AESAXDIN_H);                            /* AES accelerator XORed data in register */
+sfr_w(AESAXIN);                               /* AES accelerator XORed data in register (no trigger)  */
+sfr_b(AESAXIN_L);                             /* AES accelerator XORed data in register (no trigger)  */
+sfr_b(AESAXIN_H);                             /* AES accelerator XORed data in register (no trigger)  */
+
+/* AESACTL0 Control Bits */
+#define AESOP0                 (0x0001)       /* AES Operation Bit: 0 */
+#define AESOP1                 (0x0002)       /* AES Operation Bit: 1 */
+#define AESKL0                 (0x0004)       /* AES Key length Bit: 0 */
+#define AESKL1                 (0x0008)       /* AES Key length Bit: 1 */
+#define AESTRIG                (0x0010)       /* AES Trigger Select */
+#define AESCM0                 (0x0020)       /* AES Cipher mode select Bit: 0 */
+#define AESCM1                 (0x0040)       /* AES Cipher mode select Bit: 1 */
+#define AESSWRST               (0x0080)       /* AES Software Reset */
+#define AESRDYIFG              (0x0100)       /* AES ready interrupt flag */
+#define AESERRFG               (0x0800)       /* AES Error Flag */
+#define AESRDYIE               (0x1000)       /* AES ready interrupt enable*/
+#define AESCMEN                (0x8000)       /* AES DMA cipher mode enable*/
+
+/* AESACTL0 Control Bits */
+#define AESOP0_L               (0x0001)       /* AES Operation Bit: 0 */
+#define AESOP1_L               (0x0002)       /* AES Operation Bit: 1 */
+#define AESKL0_L               (0x0004)       /* AES Key length Bit: 0 */
+#define AESKL1_L               (0x0008)       /* AES Key length Bit: 1 */
+#define AESTRIG_L              (0x0010)       /* AES Trigger Select */
+#define AESCM0_L               (0x0020)       /* AES Cipher mode select Bit: 0 */
+#define AESCM1_L               (0x0040)       /* AES Cipher mode select Bit: 1 */
+#define AESSWRST_L             (0x0080)       /* AES Software Reset */
+
+/* AESACTL0 Control Bits */
+#define AESRDYIFG_H            (0x0001)       /* AES ready interrupt flag */
+#define AESERRFG_H             (0x0008)       /* AES Error Flag */
+#define AESRDYIE_H             (0x0010)       /* AES ready interrupt enable*/
+#define AESCMEN_H              (0x0080)       /* AES DMA cipher mode enable*/
+
+#define AESOP_0                (0x0000)       /* AES Operation: Encrypt */
+#define AESOP_1                (0x0001)       /* AES Operation: Decrypt (same Key) */
+#define AESOP_2                (0x0002)       /* AES Operation: Generate first round Key */
+#define AESOP_3                (0x0003)       /* AES Operation: Decrypt (first round Key) */
+
+#define AESKL_0                (0x0000)       /* AES Key length: AES128 */
+#define AESKL_1                (0x0004)       /* AES Key length: AES192 */
+#define AESKL_2                (0x0008)       /* AES Key length: AES256 */
+#define AESKL__128             (0x0000)       /* AES Key length: AES128 */
+#define AESKL__192             (0x0004)       /* AES Key length: AES192 */
+#define AESKL__256             (0x0008)       /* AES Key length: AES256 */
+
+#define AESCM_0                (0x0000)       /* AES Cipher mode select: ECB */
+#define AESCM_1                (0x0020)       /* AES Cipher mode select: CBC */
+#define AESCM_2                (0x0040)       /* AES Cipher mode select: OFB */
+#define AESCM_3                (0x0060)       /* AES Cipher mode select: CFB */
+#define AESCM__ECB             (0x0000)       /* AES Cipher mode select: ECB */
+#define AESCM__CBC             (0x0020)       /* AES Cipher mode select: CBC */
+#define AESCM__OFB             (0x0040)       /* AES Cipher mode select: OFB */
+#define AESCM__CFB             (0x0060)       /* AES Cipher mode select: CFB */
+
+/* AESACTL1 Control Bits */
+#define AESBLKCNT0             (0x0001)       /* AES Cipher Block Counter Bit: 0 */
+#define AESBLKCNT1             (0x0002)       /* AES Cipher Block Counter Bit: 1 */
+#define AESBLKCNT2             (0x0004)       /* AES Cipher Block Counter Bit: 2 */
+#define AESBLKCNT3             (0x0008)       /* AES Cipher Block Counter Bit: 3 */
+#define AESBLKCNT4             (0x0010)       /* AES Cipher Block Counter Bit: 4 */
+#define AESBLKCNT5             (0x0020)       /* AES Cipher Block Counter Bit: 5 */
+#define AESBLKCNT6             (0x0040)       /* AES Cipher Block Counter Bit: 6 */
+#define AESBLKCNT7             (0x0080)       /* AES Cipher Block Counter Bit: 7 */
+
+/* AESACTL1 Control Bits */
+#define AESBLKCNT0_L           (0x0001)       /* AES Cipher Block Counter Bit: 0 */
+#define AESBLKCNT1_L           (0x0002)       /* AES Cipher Block Counter Bit: 1 */
+#define AESBLKCNT2_L           (0x0004)       /* AES Cipher Block Counter Bit: 2 */
+#define AESBLKCNT3_L           (0x0008)       /* AES Cipher Block Counter Bit: 3 */
+#define AESBLKCNT4_L           (0x0010)       /* AES Cipher Block Counter Bit: 4 */
+#define AESBLKCNT5_L           (0x0020)       /* AES Cipher Block Counter Bit: 5 */
+#define AESBLKCNT6_L           (0x0040)       /* AES Cipher Block Counter Bit: 6 */
+#define AESBLKCNT7_L           (0x0080)       /* AES Cipher Block Counter Bit: 7 */
+
+/* AESASTAT Control Bits */
+#define AESBUSY                (0x0001)       /* AES Busy */
+#define AESKEYWR               (0x0002)       /* AES All 16 bytes written to AESAKEY */
+#define AESDINWR               (0x0004)       /* AES All 16 bytes written to AESADIN */
+#define AESDOUTRD              (0x0008)       /* AES All 16 bytes read from AESADOUT */
+#define AESKEYCNT0             (0x0010)       /* AES Bytes written via AESAKEY Bit: 0 */
+#define AESKEYCNT1             (0x0020)       /* AES Bytes written via AESAKEY Bit: 1 */
+#define AESKEYCNT2             (0x0040)       /* AES Bytes written via AESAKEY Bit: 2 */
+#define AESKEYCNT3             (0x0080)       /* AES Bytes written via AESAKEY Bit: 3 */
+#define AESDINCNT0             (0x0100)       /* AES Bytes written via AESADIN Bit: 0 */
+#define AESDINCNT1             (0x0200)       /* AES Bytes written via AESADIN Bit: 1 */
+#define AESDINCNT2             (0x0400)       /* AES Bytes written via AESADIN Bit: 2 */
+#define AESDINCNT3             (0x0800)       /* AES Bytes written via AESADIN Bit: 3 */
+#define AESDOUTCNT0            (0x1000)       /* AES Bytes read via AESADOUT Bit: 0 */
+#define AESDOUTCNT1            (0x2000)       /* AES Bytes read via AESADOUT Bit: 1 */
+#define AESDOUTCNT2            (0x4000)       /* AES Bytes read via AESADOUT Bit: 2 */
+#define AESDOUTCNT3            (0x8000)       /* AES Bytes read via AESADOUT Bit: 3 */
+
+/* AESASTAT Control Bits */
+#define AESBUSY_L              (0x0001)       /* AES Busy */
+#define AESKEYWR_L             (0x0002)       /* AES All 16 bytes written to AESAKEY */
+#define AESDINWR_L             (0x0004)       /* AES All 16 bytes written to AESADIN */
+#define AESDOUTRD_L            (0x0008)       /* AES All 16 bytes read from AESADOUT */
+#define AESKEYCNT0_L           (0x0010)       /* AES Bytes written via AESAKEY Bit: 0 */
+#define AESKEYCNT1_L           (0x0020)       /* AES Bytes written via AESAKEY Bit: 1 */
+#define AESKEYCNT2_L           (0x0040)       /* AES Bytes written via AESAKEY Bit: 2 */
+#define AESKEYCNT3_L           (0x0080)       /* AES Bytes written via AESAKEY Bit: 3 */
+
+/* AESASTAT Control Bits */
+#define AESDINCNT0_H           (0x0001)       /* AES Bytes written via AESADIN Bit: 0 */
+#define AESDINCNT1_H           (0x0002)       /* AES Bytes written via AESADIN Bit: 1 */
+#define AESDINCNT2_H           (0x0004)       /* AES Bytes written via AESADIN Bit: 2 */
+#define AESDINCNT3_H           (0x0008)       /* AES Bytes written via AESADIN Bit: 3 */
+#define AESDOUTCNT0_H          (0x0010)       /* AES Bytes read via AESADOUT Bit: 0 */
+#define AESDOUTCNT1_H          (0x0020)       /* AES Bytes read via AESADOUT Bit: 1 */
+#define AESDOUTCNT2_H          (0x0040)       /* AES Bytes read via AESADOUT Bit: 2 */
+#define AESDOUTCNT3_H          (0x0080)       /* AES Bytes read via AESADOUT Bit: 3 */
+
+/************************************************************
+* Capacitive_Touch_IO 0
+************************************************************/
+#define __MSP430_HAS_CAP_TOUCH_IO_0__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_CAP_TOUCH_IO_0__ 0x0430
+#define CAP_TOUCH_0_BASE       __MSP430_BASEADDRESS_CAP_TOUCH_IO_0__
+
+sfr_w(CAPTIO0CTL);                            /* Capacitive_Touch_IO 0 control register */
+sfr_b(CAPTIO0CTL_L);                          /* Capacitive_Touch_IO 0 control register */
+sfr_b(CAPTIO0CTL_H);                          /* Capacitive_Touch_IO 0 control register */
+
+#define  CAPSIO0CTL            CAPTIO0CTL     /* legacy define */
+
+/************************************************************
+* Capacitive_Touch_IO 1
+************************************************************/
+#define __MSP430_HAS_CAP_TOUCH_IO_1__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_CAP_TOUCH_IO_1__ 0x0470
+#define CAP_TOUCH_1_BASE       __MSP430_BASEADDRESS_CAP_TOUCH_IO_1__
+
+sfr_w(CAPTIO1CTL);                            /* Capacitive_Touch_IO 1 control register */
+sfr_b(CAPTIO1CTL_L);                          /* Capacitive_Touch_IO 1 control register */
+sfr_b(CAPTIO1CTL_H);                          /* Capacitive_Touch_IO 1 control register */
+
+#define  CAPSIO1CTL            CAPTIO1CTL     /* legacy define */
+
+/* CAPTIOxCTL Control Bits */
+#define CAPTIOPISEL0           (0x0002)       /* CapTouchIO Pin Select Bit: 0 */
+#define CAPTIOPISEL1           (0x0004)       /* CapTouchIO Pin Select Bit: 1 */
+#define CAPTIOPISEL2           (0x0008)       /* CapTouchIO Pin Select Bit: 2 */
+#define CAPTIOPOSEL0           (0x0010)       /* CapTouchIO Port Select Bit: 0 */
+#define CAPTIOPOSEL1           (0x0020)       /* CapTouchIO Port Select Bit: 1 */
+#define CAPTIOPOSEL2           (0x0040)       /* CapTouchIO Port Select Bit: 2 */
+#define CAPTIOPOSEL3           (0x0080)       /* CapTouchIO Port Select Bit: 3 */
+#define CAPTIOEN               (0x0100)       /* CapTouchIO Enable */
+#define CAPTIO                 (0x0200)       /* CapTouchIO state */
+
+/* CAPTIOxCTL Control Bits */
+#define CAPTIOPISEL0_L         (0x0002)       /* CapTouchIO Pin Select Bit: 0 */
+#define CAPTIOPISEL1_L         (0x0004)       /* CapTouchIO Pin Select Bit: 1 */
+#define CAPTIOPISEL2_L         (0x0008)       /* CapTouchIO Pin Select Bit: 2 */
+#define CAPTIOPOSEL0_L         (0x0010)       /* CapTouchIO Port Select Bit: 0 */
+#define CAPTIOPOSEL1_L         (0x0020)       /* CapTouchIO Port Select Bit: 1 */
+#define CAPTIOPOSEL2_L         (0x0040)       /* CapTouchIO Port Select Bit: 2 */
+#define CAPTIOPOSEL3_L         (0x0080)       /* CapTouchIO Port Select Bit: 3 */
+
+/* CAPTIOxCTL Control Bits */
+#define CAPTIOEN_H             (0x0001)       /* CapTouchIO Enable */
+#define CAPTIO_H               (0x0002)       /* CapTouchIO state */
+
+/* Legacy defines */
+#define CAPSIOPISEL0           (0x0002)       /* CapTouchIO Pin Select Bit: 0 */
+#define CAPSIOPISEL1           (0x0004)       /* CapTouchIO Pin Select Bit: 1 */
+#define CAPSIOPISEL2           (0x0008)       /* CapTouchIO Pin Select Bit: 2 */
+#define CAPSIOPOSEL0           (0x0010)       /* CapTouchIO Port Select Bit: 0 */
+#define CAPSIOPOSEL1           (0x0020)       /* CapTouchIO Port Select Bit: 1 */
+#define CAPSIOPOSEL2           (0x0040)       /* CapTouchIO Port Select Bit: 2 */
+#define CAPSIOPOSEL3           (0x0080)       /* CapTouchIO Port Select Bit: 3 */
+#define CAPSIOEN               (0x0100)       /* CapTouchIO Enable */
+#define CAPSIO                 (0x0200)       /* CapTouchIO state */
+
+/************************************************************
+* Comparator E
+************************************************************/
+#define __MSP430_HAS_COMP_E__                 /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_COMP_E__ 0x08C0
+#define COMP_E_BASE            __MSP430_BASEADDRESS_COMP_E__
+
+sfr_w(CECTL0);                                /* Comparator E Control Register 0 */
+sfr_b(CECTL0_L);                              /* Comparator E Control Register 0 */
+sfr_b(CECTL0_H);                              /* Comparator E Control Register 0 */
+sfr_w(CECTL1);                                /* Comparator E Control Register 1 */
+sfr_b(CECTL1_L);                              /* Comparator E Control Register 1 */
+sfr_b(CECTL1_H);                              /* Comparator E Control Register 1 */
+sfr_w(CECTL2);                                /* Comparator E Control Register 2 */
+sfr_b(CECTL2_L);                              /* Comparator E Control Register 2 */
+sfr_b(CECTL2_H);                              /* Comparator E Control Register 2 */
+sfr_w(CECTL3);                                /* Comparator E Control Register 3 */
+sfr_b(CECTL3_L);                              /* Comparator E Control Register 3 */
+sfr_b(CECTL3_H);                              /* Comparator E Control Register 3 */
+sfr_w(CEINT);                                 /* Comparator E Interrupt Register */
+sfr_b(CEINT_L);                               /* Comparator E Interrupt Register */
+sfr_b(CEINT_H);                               /* Comparator E Interrupt Register */
+sfr_w(CEIV);                                  /* Comparator E Interrupt Vector Word */
+sfr_b(CEIV_L);                                /* Comparator E Interrupt Vector Word */
+sfr_b(CEIV_H);                                /* Comparator E Interrupt Vector Word */
+
+/* CECTL0 Control Bits */
+#define CEIPSEL0               (0x0001)       /* Comp. E Pos. Channel Input Select 0 */
+#define CEIPSEL1               (0x0002)       /* Comp. E Pos. Channel Input Select 1 */
+#define CEIPSEL2               (0x0004)       /* Comp. E Pos. Channel Input Select 2 */
+#define CEIPSEL3               (0x0008)       /* Comp. E Pos. Channel Input Select 3 */
+//#define RESERVED            (0x0010)  /* Comp. E */
+//#define RESERVED            (0x0020)  /* Comp. E */
+//#define RESERVED            (0x0040)  /* Comp. E */
+#define CEIPEN                 (0x0080)       /* Comp. E Pos. Channel Input Enable */
+#define CEIMSEL0               (0x0100)       /* Comp. E Neg. Channel Input Select 0 */
+#define CEIMSEL1               (0x0200)       /* Comp. E Neg. Channel Input Select 1 */
+#define CEIMSEL2               (0x0400)       /* Comp. E Neg. Channel Input Select 2 */
+#define CEIMSEL3               (0x0800)       /* Comp. E Neg. Channel Input Select 3 */
+//#define RESERVED            (0x1000)  /* Comp. E */
+//#define RESERVED            (0x2000)  /* Comp. E */
+//#define RESERVED            (0x4000)  /* Comp. E */
+#define CEIMEN                 (0x8000)       /* Comp. E Neg. Channel Input Enable */
+
+/* CECTL0 Control Bits */
+#define CEIPSEL0_L             (0x0001)       /* Comp. E Pos. Channel Input Select 0 */
+#define CEIPSEL1_L             (0x0002)       /* Comp. E Pos. Channel Input Select 1 */
+#define CEIPSEL2_L             (0x0004)       /* Comp. E Pos. Channel Input Select 2 */
+#define CEIPSEL3_L             (0x0008)       /* Comp. E Pos. Channel Input Select 3 */
+//#define RESERVED            (0x0010)  /* Comp. E */
+//#define RESERVED            (0x0020)  /* Comp. E */
+//#define RESERVED            (0x0040)  /* Comp. E */
+#define CEIPEN_L               (0x0080)       /* Comp. E Pos. Channel Input Enable */
+//#define RESERVED            (0x1000)  /* Comp. E */
+//#define RESERVED            (0x2000)  /* Comp. E */
+//#define RESERVED            (0x4000)  /* Comp. E */
+
+/* CECTL0 Control Bits */
+//#define RESERVED            (0x0010)  /* Comp. E */
+//#define RESERVED            (0x0020)  /* Comp. E */
+//#define RESERVED            (0x0040)  /* Comp. E */
+#define CEIMSEL0_H             (0x0001)       /* Comp. E Neg. Channel Input Select 0 */
+#define CEIMSEL1_H             (0x0002)       /* Comp. E Neg. Channel Input Select 1 */
+#define CEIMSEL2_H             (0x0004)       /* Comp. E Neg. Channel Input Select 2 */
+#define CEIMSEL3_H             (0x0008)       /* Comp. E Neg. Channel Input Select 3 */
+//#define RESERVED            (0x1000)  /* Comp. E */
+//#define RESERVED            (0x2000)  /* Comp. E */
+//#define RESERVED            (0x4000)  /* Comp. E */
+#define CEIMEN_H               (0x0080)       /* Comp. E Neg. Channel Input Enable */
+
+#define CEIPSEL_0              (0x0000)       /* Comp. E V+ terminal Input Select: Channel 0 */
+#define CEIPSEL_1              (0x0001)       /* Comp. E V+ terminal Input Select: Channel 1 */
+#define CEIPSEL_2              (0x0002)       /* Comp. E V+ terminal Input Select: Channel 2 */
+#define CEIPSEL_3              (0x0003)       /* Comp. E V+ terminal Input Select: Channel 3 */
+#define CEIPSEL_4              (0x0004)       /* Comp. E V+ terminal Input Select: Channel 4 */
+#define CEIPSEL_5              (0x0005)       /* Comp. E V+ terminal Input Select: Channel 5 */
+#define CEIPSEL_6              (0x0006)       /* Comp. E V+ terminal Input Select: Channel 6 */
+#define CEIPSEL_7              (0x0007)       /* Comp. E V+ terminal Input Select: Channel 7 */
+#define CEIPSEL_8              (0x0008)       /* Comp. E V+ terminal Input Select: Channel 8 */
+#define CEIPSEL_9              (0x0009)       /* Comp. E V+ terminal Input Select: Channel 9 */
+#define CEIPSEL_10             (0x000A)       /* Comp. E V+ terminal Input Select: Channel 10 */
+#define CEIPSEL_11             (0x000B)       /* Comp. E V+ terminal Input Select: Channel 11 */
+#define CEIPSEL_12             (0x000C)       /* Comp. E V+ terminal Input Select: Channel 12 */
+#define CEIPSEL_13             (0x000D)       /* Comp. E V+ terminal Input Select: Channel 13 */
+#define CEIPSEL_14             (0x000E)       /* Comp. E V+ terminal Input Select: Channel 14 */
+#define CEIPSEL_15             (0x000F)       /* Comp. E V+ terminal Input Select: Channel 15 */
+
+#define CEIMSEL_0              (0x0000)       /* Comp. E V- Terminal Input Select: Channel 0 */
+#define CEIMSEL_1              (0x0100)       /* Comp. E V- Terminal Input Select: Channel 1 */
+#define CEIMSEL_2              (0x0200)       /* Comp. E V- Terminal Input Select: Channel 2 */
+#define CEIMSEL_3              (0x0300)       /* Comp. E V- Terminal Input Select: Channel 3 */
+#define CEIMSEL_4              (0x0400)       /* Comp. E V- Terminal Input Select: Channel 4 */
+#define CEIMSEL_5              (0x0500)       /* Comp. E V- Terminal Input Select: Channel 5 */
+#define CEIMSEL_6              (0x0600)       /* Comp. E V- Terminal Input Select: Channel 6 */
+#define CEIMSEL_7              (0x0700)       /* Comp. E V- Terminal Input Select: Channel 7 */
+#define CEIMSEL_8              (0x0800)       /* Comp. E V- terminal Input Select: Channel 8 */
+#define CEIMSEL_9              (0x0900)       /* Comp. E V- terminal Input Select: Channel 9 */
+#define CEIMSEL_10             (0x0A00)       /* Comp. E V- terminal Input Select: Channel 10 */
+#define CEIMSEL_11             (0x0B00)       /* Comp. E V- terminal Input Select: Channel 11 */
+#define CEIMSEL_12             (0x0C00)       /* Comp. E V- terminal Input Select: Channel 12 */
+#define CEIMSEL_13             (0x0D00)       /* Comp. E V- terminal Input Select: Channel 13 */
+#define CEIMSEL_14             (0x0E00)       /* Comp. E V- terminal Input Select: Channel 14 */
+#define CEIMSEL_15             (0x0F00)       /* Comp. E V- terminal Input Select: Channel 15 */
+
+/* CECTL1 Control Bits */
+#define CEOUT                  (0x0001)       /* Comp. E Output */
+#define CEOUTPOL               (0x0002)       /* Comp. E Output Polarity */
+#define CEF                    (0x0004)       /* Comp. E Enable Output Filter */
+#define CEIES                  (0x0008)       /* Comp. E Interrupt Edge Select */
+#define CESHORT                (0x0010)       /* Comp. E Input Short */
+#define CEEX                   (0x0020)       /* Comp. E Exchange Inputs */
+#define CEFDLY0                (0x0040)       /* Comp. E Filter delay Bit 0 */
+#define CEFDLY1                (0x0080)       /* Comp. E Filter delay Bit 1 */
+#define CEPWRMD0               (0x0100)       /* Comp. E Power mode Bit 0 */
+#define CEPWRMD1               (0x0200)       /* Comp. E Power mode Bit 1 */
+#define CEON                   (0x0400)       /* Comp. E enable */
+#define CEMRVL                 (0x0800)       /* Comp. E CEMRV Level */
+#define CEMRVS                 (0x1000)       /* Comp. E Output selects between VREF0 or VREF1*/
+//#define RESERVED            (0x2000)  /* Comp. E */
+//#define RESERVED            (0x4000)  /* Comp. E */
+//#define RESERVED            (0x8000)  /* Comp. E */
+
+/* CECTL1 Control Bits */
+#define CEOUT_L                (0x0001)       /* Comp. E Output */
+#define CEOUTPOL_L             (0x0002)       /* Comp. E Output Polarity */
+#define CEF_L                  (0x0004)       /* Comp. E Enable Output Filter */
+#define CEIES_L                (0x0008)       /* Comp. E Interrupt Edge Select */
+#define CESHORT_L              (0x0010)       /* Comp. E Input Short */
+#define CEEX_L                 (0x0020)       /* Comp. E Exchange Inputs */
+#define CEFDLY0_L              (0x0040)       /* Comp. E Filter delay Bit 0 */
+#define CEFDLY1_L              (0x0080)       /* Comp. E Filter delay Bit 1 */
+//#define RESERVED            (0x2000)  /* Comp. E */
+//#define RESERVED            (0x4000)  /* Comp. E */
+//#define RESERVED            (0x8000)  /* Comp. E */
+
+/* CECTL1 Control Bits */
+#define CEPWRMD0_H             (0x0001)       /* Comp. E Power mode Bit 0 */
+#define CEPWRMD1_H             (0x0002)       /* Comp. E Power mode Bit 1 */
+#define CEON_H                 (0x0004)       /* Comp. E enable */
+#define CEMRVL_H               (0x0008)       /* Comp. E CEMRV Level */
+#define CEMRVS_H               (0x0010)       /* Comp. E Output selects between VREF0 or VREF1*/
+//#define RESERVED            (0x2000)  /* Comp. E */
+//#define RESERVED            (0x4000)  /* Comp. E */
+//#define RESERVED            (0x8000)  /* Comp. E */
+
+#define CEPWRMD_0              (0x0000)       /* Comp. E Power mode 0 */
+#define CEPWRMD_1              (0x0100)       /* Comp. E Power mode 1 */
+#define CEPWRMD_2              (0x0200)       /* Comp. E Power mode 2 */
+#define CEPWRMD_3              (0x0300)       /* Comp. E Power mode 3*/
+
+#define CEFDLY_0               (0x0000)       /* Comp. E Filter delay 0 : 450ns */
+#define CEFDLY_1               (0x0040)       /* Comp. E Filter delay 1 : 900ns */
+#define CEFDLY_2               (0x0080)       /* Comp. E Filter delay 2 : 1800ns */
+#define CEFDLY_3               (0x00C0)       /* Comp. E Filter delay 3 : 3600ns */
+
+/* CECTL2 Control Bits */
+#define CEREF00                (0x0001)       /* Comp. E Reference 0 Resistor Select Bit : 0 */
+#define CEREF01                (0x0002)       /* Comp. E Reference 0 Resistor Select Bit : 1 */
+#define CEREF02                (0x0004)       /* Comp. E Reference 0 Resistor Select Bit : 2 */
+#define CEREF03                (0x0008)       /* Comp. E Reference 0 Resistor Select Bit : 3 */
+#define CEREF04                (0x0010)       /* Comp. E Reference 0 Resistor Select Bit : 4 */
+#define CERSEL                 (0x0020)       /* Comp. E Reference select */
+#define CERS0                  (0x0040)       /* Comp. E Reference Source Bit : 0 */
+#define CERS1                  (0x0080)       /* Comp. E Reference Source Bit : 1 */
+#define CEREF10                (0x0100)       /* Comp. E Reference 1 Resistor Select Bit : 0 */
+#define CEREF11                (0x0200)       /* Comp. E Reference 1 Resistor Select Bit : 1 */
+#define CEREF12                (0x0400)       /* Comp. E Reference 1 Resistor Select Bit : 2 */
+#define CEREF13                (0x0800)       /* Comp. E Reference 1 Resistor Select Bit : 3 */
+#define CEREF14                (0x1000)       /* Comp. E Reference 1 Resistor Select Bit : 4 */
+#define CEREFL0                (0x2000)       /* Comp. E Reference voltage level Bit : 0 */
+#define CEREFL1                (0x4000)       /* Comp. E Reference voltage level Bit : 1 */
+#define CEREFACC               (0x8000)       /* Comp. E Reference Accuracy */
+
+/* CECTL2 Control Bits */
+#define CEREF00_L              (0x0001)       /* Comp. E Reference 0 Resistor Select Bit : 0 */
+#define CEREF01_L              (0x0002)       /* Comp. E Reference 0 Resistor Select Bit : 1 */
+#define CEREF02_L              (0x0004)       /* Comp. E Reference 0 Resistor Select Bit : 2 */
+#define CEREF03_L              (0x0008)       /* Comp. E Reference 0 Resistor Select Bit : 3 */
+#define CEREF04_L              (0x0010)       /* Comp. E Reference 0 Resistor Select Bit : 4 */
+#define CERSEL_L               (0x0020)       /* Comp. E Reference select */
+#define CERS0_L                (0x0040)       /* Comp. E Reference Source Bit : 0 */
+#define CERS1_L                (0x0080)       /* Comp. E Reference Source Bit : 1 */
+
+/* CECTL2 Control Bits */
+#define CEREF10_H              (0x0001)       /* Comp. E Reference 1 Resistor Select Bit : 0 */
+#define CEREF11_H              (0x0002)       /* Comp. E Reference 1 Resistor Select Bit : 1 */
+#define CEREF12_H              (0x0004)       /* Comp. E Reference 1 Resistor Select Bit : 2 */
+#define CEREF13_H              (0x0008)       /* Comp. E Reference 1 Resistor Select Bit : 3 */
+#define CEREF14_H              (0x0010)       /* Comp. E Reference 1 Resistor Select Bit : 4 */
+#define CEREFL0_H              (0x0020)       /* Comp. E Reference voltage level Bit : 0 */
+#define CEREFL1_H              (0x0040)       /* Comp. E Reference voltage level Bit : 1 */
+#define CEREFACC_H             (0x0080)       /* Comp. E Reference Accuracy */
+
+#define CEREF0_0               (0x0000)       /* Comp. E Int. Ref.0 Select 0 : 1/32 */
+#define CEREF0_1               (0x0001)       /* Comp. E Int. Ref.0 Select 1 : 2/32 */
+#define CEREF0_2               (0x0002)       /* Comp. E Int. Ref.0 Select 2 : 3/32 */
+#define CEREF0_3               (0x0003)       /* Comp. E Int. Ref.0 Select 3 : 4/32 */
+#define CEREF0_4               (0x0004)       /* Comp. E Int. Ref.0 Select 4 : 5/32 */
+#define CEREF0_5               (0x0005)       /* Comp. E Int. Ref.0 Select 5 : 6/32 */
+#define CEREF0_6               (0x0006)       /* Comp. E Int. Ref.0 Select 6 : 7/32 */
+#define CEREF0_7               (0x0007)       /* Comp. E Int. Ref.0 Select 7 : 8/32 */
+#define CEREF0_8               (0x0008)       /* Comp. E Int. Ref.0 Select 0 : 9/32 */
+#define CEREF0_9               (0x0009)       /* Comp. E Int. Ref.0 Select 1 : 10/32 */
+#define CEREF0_10              (0x000A)       /* Comp. E Int. Ref.0 Select 2 : 11/32 */
+#define CEREF0_11              (0x000B)       /* Comp. E Int. Ref.0 Select 3 : 12/32 */
+#define CEREF0_12              (0x000C)       /* Comp. E Int. Ref.0 Select 4 : 13/32 */
+#define CEREF0_13              (0x000D)       /* Comp. E Int. Ref.0 Select 5 : 14/32 */
+#define CEREF0_14              (0x000E)       /* Comp. E Int. Ref.0 Select 6 : 15/32 */
+#define CEREF0_15              (0x000F)       /* Comp. E Int. Ref.0 Select 7 : 16/32 */
+#define CEREF0_16              (0x0010)       /* Comp. E Int. Ref.0 Select 0 : 17/32 */
+#define CEREF0_17              (0x0011)       /* Comp. E Int. Ref.0 Select 1 : 18/32 */
+#define CEREF0_18              (0x0012)       /* Comp. E Int. Ref.0 Select 2 : 19/32 */
+#define CEREF0_19              (0x0013)       /* Comp. E Int. Ref.0 Select 3 : 20/32 */
+#define CEREF0_20              (0x0014)       /* Comp. E Int. Ref.0 Select 4 : 21/32 */
+#define CEREF0_21              (0x0015)       /* Comp. E Int. Ref.0 Select 5 : 22/32 */
+#define CEREF0_22              (0x0016)       /* Comp. E Int. Ref.0 Select 6 : 23/32 */
+#define CEREF0_23              (0x0017)       /* Comp. E Int. Ref.0 Select 7 : 24/32 */
+#define CEREF0_24              (0x0018)       /* Comp. E Int. Ref.0 Select 0 : 25/32 */
+#define CEREF0_25              (0x0019)       /* Comp. E Int. Ref.0 Select 1 : 26/32 */
+#define CEREF0_26              (0x001A)       /* Comp. E Int. Ref.0 Select 2 : 27/32 */
+#define CEREF0_27              (0x001B)       /* Comp. E Int. Ref.0 Select 3 : 28/32 */
+#define CEREF0_28              (0x001C)       /* Comp. E Int. Ref.0 Select 4 : 29/32 */
+#define CEREF0_29              (0x001D)       /* Comp. E Int. Ref.0 Select 5 : 30/32 */
+#define CEREF0_30              (0x001E)       /* Comp. E Int. Ref.0 Select 6 : 31/32 */
+#define CEREF0_31              (0x001F)       /* Comp. E Int. Ref.0 Select 7 : 32/32 */
+
+#define CERS_0                 (0x0000)       /* Comp. E Reference Source 0 : Off */
+#define CERS_1                 (0x0040)       /* Comp. E Reference Source 1 : Vcc */
+#define CERS_2                 (0x0080)       /* Comp. E Reference Source 2 : Shared Ref. */
+#define CERS_3                 (0x00C0)       /* Comp. E Reference Source 3 : Shared Ref. / Off */
+
+#define CEREF1_0               (0x0000)       /* Comp. E Int. Ref.1 Select 0 : 1/32 */
+#define CEREF1_1               (0x0100)       /* Comp. E Int. Ref.1 Select 1 : 2/32 */
+#define CEREF1_2               (0x0200)       /* Comp. E Int. Ref.1 Select 2 : 3/32 */
+#define CEREF1_3               (0x0300)       /* Comp. E Int. Ref.1 Select 3 : 4/32 */
+#define CEREF1_4               (0x0400)       /* Comp. E Int. Ref.1 Select 4 : 5/32 */
+#define CEREF1_5               (0x0500)       /* Comp. E Int. Ref.1 Select 5 : 6/32 */
+#define CEREF1_6               (0x0600)       /* Comp. E Int. Ref.1 Select 6 : 7/32 */
+#define CEREF1_7               (0x0700)       /* Comp. E Int. Ref.1 Select 7 : 8/32 */
+#define CEREF1_8               (0x0800)       /* Comp. E Int. Ref.1 Select 0 : 9/32 */
+#define CEREF1_9               (0x0900)       /* Comp. E Int. Ref.1 Select 1 : 10/32 */
+#define CEREF1_10              (0x0A00)       /* Comp. E Int. Ref.1 Select 2 : 11/32 */
+#define CEREF1_11              (0x0B00)       /* Comp. E Int. Ref.1 Select 3 : 12/32 */
+#define CEREF1_12              (0x0C00)       /* Comp. E Int. Ref.1 Select 4 : 13/32 */
+#define CEREF1_13              (0x0D00)       /* Comp. E Int. Ref.1 Select 5 : 14/32 */
+#define CEREF1_14              (0x0E00)       /* Comp. E Int. Ref.1 Select 6 : 15/32 */
+#define CEREF1_15              (0x0F00)       /* Comp. E Int. Ref.1 Select 7 : 16/32 */
+#define CEREF1_16              (0x1000)       /* Comp. E Int. Ref.1 Select 0 : 17/32 */
+#define CEREF1_17              (0x1100)       /* Comp. E Int. Ref.1 Select 1 : 18/32 */
+#define CEREF1_18              (0x1200)       /* Comp. E Int. Ref.1 Select 2 : 19/32 */
+#define CEREF1_19              (0x1300)       /* Comp. E Int. Ref.1 Select 3 : 20/32 */
+#define CEREF1_20              (0x1400)       /* Comp. E Int. Ref.1 Select 4 : 21/32 */
+#define CEREF1_21              (0x1500)       /* Comp. E Int. Ref.1 Select 5 : 22/32 */
+#define CEREF1_22              (0x1600)       /* Comp. E Int. Ref.1 Select 6 : 23/32 */
+#define CEREF1_23              (0x1700)       /* Comp. E Int. Ref.1 Select 7 : 24/32 */
+#define CEREF1_24              (0x1800)       /* Comp. E Int. Ref.1 Select 0 : 25/32 */
+#define CEREF1_25              (0x1900)       /* Comp. E Int. Ref.1 Select 1 : 26/32 */
+#define CEREF1_26              (0x1A00)       /* Comp. E Int. Ref.1 Select 2 : 27/32 */
+#define CEREF1_27              (0x1B00)       /* Comp. E Int. Ref.1 Select 3 : 28/32 */
+#define CEREF1_28              (0x1C00)       /* Comp. E Int. Ref.1 Select 4 : 29/32 */
+#define CEREF1_29              (0x1D00)       /* Comp. E Int. Ref.1 Select 5 : 30/32 */
+#define CEREF1_30              (0x1E00)       /* Comp. E Int. Ref.1 Select 6 : 31/32 */
+#define CEREF1_31              (0x1F00)       /* Comp. E Int. Ref.1 Select 7 : 32/32 */
+
+#define CEREFL_0               (0x0000)       /* Comp. E Reference voltage level 0 : None */
+#define CEREFL_1               (0x2000)       /* Comp. E Reference voltage level 1 : 1.2V */
+#define CEREFL_2               (0x4000)       /* Comp. E Reference voltage level 2 : 2.0V  */
+#define CEREFL_3               (0x6000)       /* Comp. E Reference voltage level 3 : 2.5V  */
+
+#define CEPD0                  (0x0001)       /* Comp. E Disable Input Buffer of Port Register .0 */
+#define CEPD1                  (0x0002)       /* Comp. E Disable Input Buffer of Port Register .1 */
+#define CEPD2                  (0x0004)       /* Comp. E Disable Input Buffer of Port Register .2 */
+#define CEPD3                  (0x0008)       /* Comp. E Disable Input Buffer of Port Register .3 */
+#define CEPD4                  (0x0010)       /* Comp. E Disable Input Buffer of Port Register .4 */
+#define CEPD5                  (0x0020)       /* Comp. E Disable Input Buffer of Port Register .5 */
+#define CEPD6                  (0x0040)       /* Comp. E Disable Input Buffer of Port Register .6 */
+#define CEPD7                  (0x0080)       /* Comp. E Disable Input Buffer of Port Register .7 */
+#define CEPD8                  (0x0100)       /* Comp. E Disable Input Buffer of Port Register .8 */
+#define CEPD9                  (0x0200)       /* Comp. E Disable Input Buffer of Port Register .9 */
+#define CEPD10                 (0x0400)       /* Comp. E Disable Input Buffer of Port Register .10 */
+#define CEPD11                 (0x0800)       /* Comp. E Disable Input Buffer of Port Register .11 */
+#define CEPD12                 (0x1000)       /* Comp. E Disable Input Buffer of Port Register .12 */
+#define CEPD13                 (0x2000)       /* Comp. E Disable Input Buffer of Port Register .13 */
+#define CEPD14                 (0x4000)       /* Comp. E Disable Input Buffer of Port Register .14 */
+#define CEPD15                 (0x8000)       /* Comp. E Disable Input Buffer of Port Register .15 */
+
+#define CEPD0_L                (0x0001)       /* Comp. E Disable Input Buffer of Port Register .0 */
+#define CEPD1_L                (0x0002)       /* Comp. E Disable Input Buffer of Port Register .1 */
+#define CEPD2_L                (0x0004)       /* Comp. E Disable Input Buffer of Port Register .2 */
+#define CEPD3_L                (0x0008)       /* Comp. E Disable Input Buffer of Port Register .3 */
+#define CEPD4_L                (0x0010)       /* Comp. E Disable Input Buffer of Port Register .4 */
+#define CEPD5_L                (0x0020)       /* Comp. E Disable Input Buffer of Port Register .5 */
+#define CEPD6_L                (0x0040)       /* Comp. E Disable Input Buffer of Port Register .6 */
+#define CEPD7_L                (0x0080)       /* Comp. E Disable Input Buffer of Port Register .7 */
+
+#define CEPD8_H                (0x0001)       /* Comp. E Disable Input Buffer of Port Register .8 */
+#define CEPD9_H                (0x0002)       /* Comp. E Disable Input Buffer of Port Register .9 */
+#define CEPD10_H               (0x0004)       /* Comp. E Disable Input Buffer of Port Register .10 */
+#define CEPD11_H               (0x0008)       /* Comp. E Disable Input Buffer of Port Register .11 */
+#define CEPD12_H               (0x0010)       /* Comp. E Disable Input Buffer of Port Register .12 */
+#define CEPD13_H               (0x0020)       /* Comp. E Disable Input Buffer of Port Register .13 */
+#define CEPD14_H               (0x0040)       /* Comp. E Disable Input Buffer of Port Register .14 */
+#define CEPD15_H               (0x0080)       /* Comp. E Disable Input Buffer of Port Register .15 */
+
+/* CEINT Control Bits */
+#define CEIFG                  (0x0001)       /* Comp. E Interrupt Flag */
+#define CEIIFG                 (0x0002)       /* Comp. E Interrupt Flag Inverted Polarity */
+//#define RESERVED             (0x0004)  /* Comp. E */
+//#define RESERVED             (0x0008)  /* Comp. E */
+#define CERDYIFG               (0x0010)       /* Comp. E Comparator_E ready interrupt flag */
+//#define RESERVED             (0x0020)  /* Comp. E */
+//#define RESERVED             (0x0040)  /* Comp. E */
+//#define RESERVED             (0x0080)  /* Comp. E */
+#define CEIE                   (0x0100)       /* Comp. E Interrupt Enable */
+#define CEIIE                  (0x0200)       /* Comp. E Interrupt Enable Inverted Polarity */
+//#define RESERVED             (0x0400)  /* Comp. E */
+//#define RESERVED             (0x0800)  /* Comp. E */
+#define CERDYIE                (0x1000)       /* Comp. E Comparator_E ready interrupt enable */
+//#define RESERVED             (0x2000)  /* Comp. E */
+//#define RESERVED             (0x4000)  /* Comp. E */
+//#define RESERVED             (0x8000)  /* Comp. E */
+
+/* CEINT Control Bits */
+#define CEIFG_L                (0x0001)       /* Comp. E Interrupt Flag */
+#define CEIIFG_L               (0x0002)       /* Comp. E Interrupt Flag Inverted Polarity */
+//#define RESERVED             (0x0004)  /* Comp. E */
+//#define RESERVED             (0x0008)  /* Comp. E */
+#define CERDYIFG_L             (0x0010)       /* Comp. E Comparator_E ready interrupt flag */
+//#define RESERVED             (0x0020)  /* Comp. E */
+//#define RESERVED             (0x0040)  /* Comp. E */
+//#define RESERVED             (0x0080)  /* Comp. E */
+//#define RESERVED             (0x0400)  /* Comp. E */
+//#define RESERVED             (0x0800)  /* Comp. E */
+//#define RESERVED             (0x2000)  /* Comp. E */
+//#define RESERVED             (0x4000)  /* Comp. E */
+//#define RESERVED             (0x8000)  /* Comp. E */
+
+/* CEINT Control Bits */
+//#define RESERVED             (0x0004)  /* Comp. E */
+//#define RESERVED             (0x0008)  /* Comp. E */
+//#define RESERVED             (0x0020)  /* Comp. E */
+//#define RESERVED             (0x0040)  /* Comp. E */
+//#define RESERVED             (0x0080)  /* Comp. E */
+#define CEIE_H                 (0x0001)       /* Comp. E Interrupt Enable */
+#define CEIIE_H                (0x0002)       /* Comp. E Interrupt Enable Inverted Polarity */
+//#define RESERVED             (0x0400)  /* Comp. E */
+//#define RESERVED             (0x0800)  /* Comp. E */
+#define CERDYIE_H              (0x0010)       /* Comp. E Comparator_E ready interrupt enable */
+//#define RESERVED             (0x2000)  /* Comp. E */
+//#define RESERVED             (0x4000)  /* Comp. E */
+//#define RESERVED             (0x8000)  /* Comp. E */
+
+/* CEIV Definitions */
+#define CEIV_NONE              (0x0000)       /* No Interrupt pending */
+#define CEIV_CEIFG             (0x0002)       /* CEIFG */
+#define CEIV_CEIIFG            (0x0004)       /* CEIIFG */
+#define CEIV_CERDYIFG          (0x000A)       /* CERDYIFG */
+
+/*************************************************************
+* CRC Module
+*************************************************************/
+#define __MSP430_HAS_CRC__                    /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_CRC__ 0x0150
+#define CRC_BASE               __MSP430_BASEADDRESS_CRC__
+
+sfr_w(CRCDI);                                 /* CRC Data In Register */
+sfr_b(CRCDI_L);                               /* CRC Data In Register */
+sfr_b(CRCDI_H);                               /* CRC Data In Register */
+sfr_w(CRCDIRB);                               /* CRC data in reverse byte Register */
+sfr_b(CRCDIRB_L);                             /* CRC data in reverse byte Register */
+sfr_b(CRCDIRB_H);                             /* CRC data in reverse byte Register */
+sfr_w(CRCINIRES);                             /* CRC Initialisation Register and Result Register */
+sfr_b(CRCINIRES_L);                           /* CRC Initialisation Register and Result Register */
+sfr_b(CRCINIRES_H);                           /* CRC Initialisation Register and Result Register */
+sfr_w(CRCRESR);                               /* CRC reverse result Register */
+sfr_b(CRCRESR_L);                             /* CRC reverse result Register */
+sfr_b(CRCRESR_H);                             /* CRC reverse result Register */
+
+/************************************************************
+* CLOCK SYSTEM
+************************************************************/
+#define __MSP430_HAS_CS__                     /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_CS__ 0x0160
+#define CS_BASE                __MSP430_BASEADDRESS_CS__
+
+sfr_w(CSCTL0);                                /* CS Control Register 0 */
+sfr_b(CSCTL0_L);                              /* CS Control Register 0 */
+sfr_b(CSCTL0_H);                              /* CS Control Register 0 */
+sfr_w(CSCTL1);                                /* CS Control Register 1 */
+sfr_b(CSCTL1_L);                              /* CS Control Register 1 */
+sfr_b(CSCTL1_H);                              /* CS Control Register 1 */
+sfr_w(CSCTL2);                                /* CS Control Register 2 */
+sfr_b(CSCTL2_L);                              /* CS Control Register 2 */
+sfr_b(CSCTL2_H);                              /* CS Control Register 2 */
+sfr_w(CSCTL3);                                /* CS Control Register 3 */
+sfr_b(CSCTL3_L);                              /* CS Control Register 3 */
+sfr_b(CSCTL3_H);                              /* CS Control Register 3 */
+sfr_w(CSCTL4);                                /* CS Control Register 4 */
+sfr_b(CSCTL4_L);                              /* CS Control Register 4 */
+sfr_b(CSCTL4_H);                              /* CS Control Register 4 */
+sfr_w(CSCTL5);                                /* CS Control Register 5 */
+sfr_b(CSCTL5_L);                              /* CS Control Register 5 */
+sfr_b(CSCTL5_H);                              /* CS Control Register 5 */
+sfr_w(CSCTL6);                                /* CS Control Register 6 */
+sfr_b(CSCTL6_L);                              /* CS Control Register 6 */
+sfr_b(CSCTL6_H);                              /* CS Control Register 6 */
+
+/* CSCTL0 Control Bits */
+
+#define CSKEY                  (0xA500)       /* CS Password */
+#define CSKEY_H                (0xA5)         /* CS Password for high byte access */
+
+/* CSCTL1 Control Bits */
+#define DCOFSEL0               (0x0002)       /* DCO frequency select Bit: 0 */
+#define DCOFSEL1               (0x0004)       /* DCO frequency select Bit: 1 */
+#define DCOFSEL2               (0x0008)       /* DCO frequency select Bit: 2 */
+#define DCORSEL                (0x0040)       /* DCO range select. */
+
+/* CSCTL1 Control Bits */
+#define DCOFSEL0_L             (0x0002)       /* DCO frequency select Bit: 0 */
+#define DCOFSEL1_L             (0x0004)       /* DCO frequency select Bit: 1 */
+#define DCOFSEL2_L             (0x0008)       /* DCO frequency select Bit: 2 */
+#define DCORSEL_L              (0x0040)       /* DCO range select. */
+
+#define DCOFSEL_0              (0x0000)       /* DCO frequency select: 0 */
+#define DCOFSEL_1              (0x0002)       /* DCO frequency select: 1 */
+#define DCOFSEL_2              (0x0004)       /* DCO frequency select: 2 */
+#define DCOFSEL_3              (0x0006)       /* DCO frequency select: 3 */
+#define DCOFSEL_4              (0x0008)       /* DCO frequency select: 4 */
+#define DCOFSEL_5              (0x000A)       /* DCO frequency select: 5 */
+#define DCOFSEL_6              (0x000C)       /* DCO frequency select: 6 */
+#define DCOFSEL_7              (0x000E)       /* DCO frequency select: 7 */
+
+/* CSCTL2 Control Bits */
+#define SELM0                  (0x0001)       /* MCLK Source Select Bit: 0 */
+#define SELM1                  (0x0002)       /* MCLK Source Select Bit: 1 */
+#define SELM2                  (0x0004)       /* MCLK Source Select Bit: 2 */
+//#define RESERVED            (0x0004)    /* RESERVED */
+//#define RESERVED            (0x0008)    /* RESERVED */
+#define SELS0                  (0x0010)       /* SMCLK Source Select Bit: 0 */
+#define SELS1                  (0x0020)       /* SMCLK Source Select Bit: 1 */
+#define SELS2                  (0x0040)       /* SMCLK Source Select Bit: 2 */
+//#define RESERVED            (0x0040)    /* RESERVED */
+//#define RESERVED            (0x0080)    /* RESERVED */
+#define SELA0                  (0x0100)       /* ACLK Source Select Bit: 0 */
+#define SELA1                  (0x0200)       /* ACLK Source Select Bit: 1 */
+#define SELA2                  (0x0400)       /* ACLK Source Select Bit: 2 */
+//#define RESERVED            (0x0400)    /* RESERVED */
+//#define RESERVED            (0x0800)    /* RESERVED */
+//#define RESERVED            (0x1000)    /* RESERVED */
+//#define RESERVED            (0x2000)    /* RESERVED */
+//#define RESERVED            (0x4000)    /* RESERVED */
+//#define RESERVED            (0x8000)    /* RESERVED */
+
+/* CSCTL2 Control Bits */
+#define SELM0_L                (0x0001)       /* MCLK Source Select Bit: 0 */
+#define SELM1_L                (0x0002)       /* MCLK Source Select Bit: 1 */
+#define SELM2_L                (0x0004)       /* MCLK Source Select Bit: 2 */
+//#define RESERVED            (0x0004)    /* RESERVED */
+//#define RESERVED            (0x0008)    /* RESERVED */
+#define SELS0_L                (0x0010)       /* SMCLK Source Select Bit: 0 */
+#define SELS1_L                (0x0020)       /* SMCLK Source Select Bit: 1 */
+#define SELS2_L                (0x0040)       /* SMCLK Source Select Bit: 2 */
+//#define RESERVED            (0x0040)    /* RESERVED */
+//#define RESERVED            (0x0080)    /* RESERVED */
+//#define RESERVED            (0x0400)    /* RESERVED */
+//#define RESERVED            (0x0800)    /* RESERVED */
+//#define RESERVED            (0x1000)    /* RESERVED */
+//#define RESERVED            (0x2000)    /* RESERVED */
+//#define RESERVED            (0x4000)    /* RESERVED */
+//#define RESERVED            (0x8000)    /* RESERVED */
+
+/* CSCTL2 Control Bits */
+//#define RESERVED            (0x0004)    /* RESERVED */
+//#define RESERVED            (0x0008)    /* RESERVED */
+//#define RESERVED            (0x0040)    /* RESERVED */
+//#define RESERVED            (0x0080)    /* RESERVED */
+#define SELA0_H                (0x0001)       /* ACLK Source Select Bit: 0 */
+#define SELA1_H                (0x0002)       /* ACLK Source Select Bit: 1 */
+#define SELA2_H                (0x0004)       /* ACLK Source Select Bit: 2 */
+//#define RESERVED            (0x0400)    /* RESERVED */
+//#define RESERVED            (0x0800)    /* RESERVED */
+//#define RESERVED            (0x1000)    /* RESERVED */
+//#define RESERVED            (0x2000)    /* RESERVED */
+//#define RESERVED            (0x4000)    /* RESERVED */
+//#define RESERVED            (0x8000)    /* RESERVED */
+
+#define SELM_0                 (0x0000)       /* MCLK Source Select 0 */
+#define SELM_1                 (0x0001)       /* MCLK Source Select 1 */
+#define SELM_2                 (0x0002)       /* MCLK Source Select 2 */
+#define SELM_3                 (0x0003)       /* MCLK Source Select 3 */
+#define SELM_4                 (0x0004)       /* MCLK Source Select 4 */
+#define SELM_5                 (0x0005)       /* MCLK Source Select 5 */
+#define SELM_6                 (0x0006)       /* MCLK Source Select 6 */
+#define SELM_7                 (0x0007)       /* MCLK Source Select 7 */
+#define SELM__LFXTCLK          (0x0000)       /* MCLK Source Select LFXTCLK */
+#define SELM__VLOCLK           (0x0001)       /* MCLK Source Select VLOCLK */
+#define SELM__LFMODCLK         (0x0002)       /* MCLK Source Select LFMODOSC */
+#define SELM__LFMODOSC         (0x0002)       /* MCLK Source Select LFMODOSC (legacy) */
+#define SELM__DCOCLK           (0x0003)       /* MCLK Source Select DCOCLK */
+#define SELM__MODCLK           (0x0004)       /* MCLK Source Select MODOSC */
+#define SELM__MODOSC           (0x0004)       /* MCLK Source Select MODOSC (legacy) */
+#define SELM__HFXTCLK          (0x0005)       /* MCLK Source Select HFXTCLK */
+
+#define SELS_0                 (0x0000)       /* SMCLK Source Select 0 */
+#define SELS_1                 (0x0010)       /* SMCLK Source Select 1 */
+#define SELS_2                 (0x0020)       /* SMCLK Source Select 2 */
+#define SELS_3                 (0x0030)       /* SMCLK Source Select 3 */
+#define SELS_4                 (0x0040)       /* SMCLK Source Select 4 */
+#define SELS_5                 (0x0050)       /* SMCLK Source Select 5 */
+#define SELS_6                 (0x0060)       /* SMCLK Source Select 6 */
+#define SELS_7                 (0x0070)       /* SMCLK Source Select 7 */
+#define SELS__LFXTCLK          (0x0000)       /* SMCLK Source Select LFXTCLK */
+#define SELS__VLOCLK           (0x0010)       /* SMCLK Source Select VLOCLK */
+#define SELS__LFMODCLK         (0x0020)       /* SMCLK Source Select LFMODOSC */
+#define SELS__LFMODOSC         (0x0020)       /* SMCLK Source Select LFMODOSC (legacy) */
+#define SELS__DCOCLK           (0x0030)       /* SMCLK Source Select DCOCLK */
+#define SELS__MODCLK           (0x0040)       /* SMCLK Source Select MODOSC */
+#define SELS__MODOSC           (0x0040)       /* SMCLK Source Select MODOSC (legacy) */
+#define SELS__HFXTCLK          (0x0050)       /* SMCLK Source Select HFXTCLK */
+
+#define SELA_0                 (0x0000)       /* ACLK Source Select 0 */
+#define SELA_1                 (0x0100)       /* ACLK Source Select 1 */
+#define SELA_2                 (0x0200)       /* ACLK Source Select 2 */
+#define SELA_3                 (0x0300)       /* ACLK Source Select 3 */
+#define SELA_4                 (0x0400)       /* ACLK Source Select 4 */
+#define SELA_5                 (0x0500)       /* ACLK Source Select 5 */
+#define SELA_6                 (0x0600)       /* ACLK Source Select 6 */
+#define SELA_7                 (0x0700)       /* ACLK Source Select 7 */
+#define SELA__LFXTCLK          (0x0000)       /* ACLK Source Select LFXTCLK */
+#define SELA__VLOCLK           (0x0100)       /* ACLK Source Select VLOCLK */
+#define SELA__LFMODCLK         (0x0200)       /* ACLK Source Select LFMODOSC */
+#define SELA__LFMODOSC         (0x0200)       /* ACLK Source Select LFMODOSC (legacy) */
+
+/* CSCTL3 Control Bits */
+#define DIVM0                  (0x0001)       /* MCLK Divider Bit: 0 */
+#define DIVM1                  (0x0002)       /* MCLK Divider Bit: 1 */
+#define DIVM2                  (0x0004)       /* MCLK Divider Bit: 2 */
+//#define RESERVED            (0x0004)    /* RESERVED */
+//#define RESERVED            (0x0008)    /* RESERVED */
+#define DIVS0                  (0x0010)       /* SMCLK Divider Bit: 0 */
+#define DIVS1                  (0x0020)       /* SMCLK Divider Bit: 1 */
+#define DIVS2                  (0x0040)       /* SMCLK Divider Bit: 2 */
+//#define RESERVED            (0x0040)    /* RESERVED */
+//#define RESERVED            (0x0080)    /* RESERVED */
+#define DIVA0                  (0x0100)       /* ACLK Divider Bit: 0 */
+#define DIVA1                  (0x0200)       /* ACLK Divider Bit: 1 */
+#define DIVA2                  (0x0400)       /* ACLK Divider Bit: 2 */
+//#define RESERVED            (0x0400)    /* RESERVED */
+//#define RESERVED            (0x0800)    /* RESERVED */
+//#define RESERVED            (0x1000)    /* RESERVED */
+//#define RESERVED            (0x2000)    /* RESERVED */
+//#define RESERVED            (0x4000)    /* RESERVED */
+//#define RESERVED            (0x8000)    /* RESERVED */
+
+/* CSCTL3 Control Bits */
+#define DIVM0_L                (0x0001)       /* MCLK Divider Bit: 0 */
+#define DIVM1_L                (0x0002)       /* MCLK Divider Bit: 1 */
+#define DIVM2_L                (0x0004)       /* MCLK Divider Bit: 2 */
+//#define RESERVED            (0x0004)    /* RESERVED */
+//#define RESERVED            (0x0008)    /* RESERVED */
+#define DIVS0_L                (0x0010)       /* SMCLK Divider Bit: 0 */
+#define DIVS1_L                (0x0020)       /* SMCLK Divider Bit: 1 */
+#define DIVS2_L                (0x0040)       /* SMCLK Divider Bit: 2 */
+//#define RESERVED            (0x0040)    /* RESERVED */
+//#define RESERVED            (0x0080)    /* RESERVED */
+//#define RESERVED            (0x0400)    /* RESERVED */
+//#define RESERVED            (0x0800)    /* RESERVED */
+//#define RESERVED            (0x1000)    /* RESERVED */
+//#define RESERVED            (0x2000)    /* RESERVED */
+//#define RESERVED            (0x4000)    /* RESERVED */
+//#define RESERVED            (0x8000)    /* RESERVED */
+
+/* CSCTL3 Control Bits */
+//#define RESERVED            (0x0004)    /* RESERVED */
+//#define RESERVED            (0x0008)    /* RESERVED */
+//#define RESERVED            (0x0040)    /* RESERVED */
+//#define RESERVED            (0x0080)    /* RESERVED */
+#define DIVA0_H                (0x0001)       /* ACLK Divider Bit: 0 */
+#define DIVA1_H                (0x0002)       /* ACLK Divider Bit: 1 */
+#define DIVA2_H                (0x0004)       /* ACLK Divider Bit: 2 */
+//#define RESERVED            (0x0400)    /* RESERVED */
+//#define RESERVED            (0x0800)    /* RESERVED */
+//#define RESERVED            (0x1000)    /* RESERVED */
+//#define RESERVED            (0x2000)    /* RESERVED */
+//#define RESERVED            (0x4000)    /* RESERVED */
+//#define RESERVED            (0x8000)    /* RESERVED */
+
+#define DIVM_0                 (0x0000)       /* MCLK Source Divider 0 */
+#define DIVM_1                 (0x0001)       /* MCLK Source Divider 1 */
+#define DIVM_2                 (0x0002)       /* MCLK Source Divider 2 */
+#define DIVM_3                 (0x0003)       /* MCLK Source Divider 3 */
+#define DIVM_4                 (0x0004)       /* MCLK Source Divider 4 */
+#define DIVM_5                 (0x0005)       /* MCLK Source Divider 5 */
+#define DIVM__1                (0x0000)       /* MCLK Source Divider f(MCLK)/1 */
+#define DIVM__2                (0x0001)       /* MCLK Source Divider f(MCLK)/2 */
+#define DIVM__4                (0x0002)       /* MCLK Source Divider f(MCLK)/4 */
+#define DIVM__8                (0x0003)       /* MCLK Source Divider f(MCLK)/8 */
+#define DIVM__16               (0x0004)       /* MCLK Source Divider f(MCLK)/16 */
+#define DIVM__32               (0x0005)       /* MCLK Source Divider f(MCLK)/32 */
+
+#define DIVS_0                 (0x0000)       /* SMCLK Source Divider 0 */
+#define DIVS_1                 (0x0010)       /* SMCLK Source Divider 1 */
+#define DIVS_2                 (0x0020)       /* SMCLK Source Divider 2 */
+#define DIVS_3                 (0x0030)       /* SMCLK Source Divider 3 */
+#define DIVS_4                 (0x0040)       /* SMCLK Source Divider 4 */
+#define DIVS_5                 (0x0050)       /* SMCLK Source Divider 5 */
+#define DIVS__1                (0x0000)       /* SMCLK Source Divider f(SMCLK)/1 */
+#define DIVS__2                (0x0010)       /* SMCLK Source Divider f(SMCLK)/2 */
+#define DIVS__4                (0x0020)       /* SMCLK Source Divider f(SMCLK)/4 */
+#define DIVS__8                (0x0030)       /* SMCLK Source Divider f(SMCLK)/8 */
+#define DIVS__16               (0x0040)       /* SMCLK Source Divider f(SMCLK)/16 */
+#define DIVS__32               (0x0050)       /* SMCLK Source Divider f(SMCLK)/32 */
+
+#define DIVA_0                 (0x0000)       /* ACLK Source Divider 0 */
+#define DIVA_1                 (0x0100)       /* ACLK Source Divider 1 */
+#define DIVA_2                 (0x0200)       /* ACLK Source Divider 2 */
+#define DIVA_3                 (0x0300)       /* ACLK Source Divider 3 */
+#define DIVA_4                 (0x0400)       /* ACLK Source Divider 4 */
+#define DIVA_5                 (0x0500)       /* ACLK Source Divider 5 */
+#define DIVA__1                (0x0000)       /* ACLK Source Divider f(ACLK)/1 */
+#define DIVA__2                (0x0100)       /* ACLK Source Divider f(ACLK)/2 */
+#define DIVA__4                (0x0200)       /* ACLK Source Divider f(ACLK)/4 */
+#define DIVA__8                (0x0300)       /* ACLK Source Divider f(ACLK)/8 */
+#define DIVA__16               (0x0400)       /* ACLK Source Divider f(ACLK)/16 */
+#define DIVA__32               (0x0500)       /* ACLK Source Divider f(ACLK)/32 */
+
+/* CSCTL4 Control Bits */
+#define LFXTOFF                (0x0001)       /* Low Frequency Oscillator (LFXT) disable */
+#define SMCLKOFF               (0x0002)       /* SMCLK Off */
+#define VLOOFF                 (0x0008)       /* VLO Off */
+#define LFXTBYPASS             (0x0010)       /* LFXT bypass mode : 0: internal 1:sourced from external pin */
+#define LFXTDRIVE0             (0x0040)       /* LFXT Drive Level mode Bit 0 */
+#define LFXTDRIVE1             (0x0080)       /* LFXT Drive Level mode Bit 1 */
+#define HFXTOFF                (0x0100)       /* High Frequency Oscillator disable */
+#define HFFREQ0                (0x0400)       /* HFXT frequency selection Bit 1 */
+#define HFFREQ1                (0x0800)       /* HFXT frequency selection Bit 0 */
+#define HFXTBYPASS             (0x1000)       /* HFXT bypass mode : 0: internal 1:sourced from external pin */
+#define HFXTDRIVE0             (0x4000)       /* HFXT Drive Level mode Bit 0 */
+#define HFXTDRIVE1             (0x8000)       /* HFXT Drive Level mode Bit 1 */
+
+/* CSCTL4 Control Bits */
+#define LFXTOFF_L              (0x0001)       /* Low Frequency Oscillator (LFXT) disable */
+#define SMCLKOFF_L             (0x0002)       /* SMCLK Off */
+#define VLOOFF_L               (0x0008)       /* VLO Off */
+#define LFXTBYPASS_L           (0x0010)       /* LFXT bypass mode : 0: internal 1:sourced from external pin */
+#define LFXTDRIVE0_L           (0x0040)       /* LFXT Drive Level mode Bit 0 */
+#define LFXTDRIVE1_L           (0x0080)       /* LFXT Drive Level mode Bit 1 */
+
+/* CSCTL4 Control Bits */
+#define HFXTOFF_H              (0x0001)       /* High Frequency Oscillator disable */
+#define HFFREQ0_H              (0x0004)       /* HFXT frequency selection Bit 1 */
+#define HFFREQ1_H              (0x0008)       /* HFXT frequency selection Bit 0 */
+#define HFXTBYPASS_H           (0x0010)       /* HFXT bypass mode : 0: internal 1:sourced from external pin */
+#define HFXTDRIVE0_H           (0x0040)       /* HFXT Drive Level mode Bit 0 */
+#define HFXTDRIVE1_H           (0x0080)       /* HFXT Drive Level mode Bit 1 */
+
+#define LFXTDRIVE_0            (0x0000)       /* LFXT Drive Level mode: 0 */
+#define LFXTDRIVE_1            (0x0040)       /* LFXT Drive Level mode: 1 */
+#define LFXTDRIVE_2            (0x0080)       /* LFXT Drive Level mode: 2 */
+#define LFXTDRIVE_3            (0x00C0)       /* LFXT Drive Level mode: 3 */
+
+#define HFFREQ_0               (0x0000)       /* HFXT frequency selection: 0 */
+#define HFFREQ_1               (0x0400)       /* HFXT frequency selection: 1 */
+#define HFFREQ_2               (0x0800)       /* HFXT frequency selection: 2 */
+#define HFFREQ_3               (0x0C00)       /* HFXT frequency selection: 3 */
+
+#define HFXTDRIVE_0            (0x0000)       /* HFXT Drive Level mode: 0 */
+#define HFXTDRIVE_1            (0x4000)       /* HFXT Drive Level mode: 1 */
+#define HFXTDRIVE_2            (0x8000)       /* HFXT Drive Level mode: 2 */
+#define HFXTDRIVE_3            (0xC000)       /* HFXT Drive Level mode: 3 */
+
+/* CSCTL5 Control Bits */
+#define LFXTOFFG               (0x0001)       /* LFXT Low Frequency Oscillator Fault Flag */
+#define HFXTOFFG               (0x0002)       /* HFXT High Frequency Oscillator Fault Flag */
+#define ENSTFCNT1              (0x0040)       /* Enable start counter for XT1 */
+#define ENSTFCNT2              (0x0080)       /* Enable start counter for XT2 */
+
+/* CSCTL5 Control Bits */
+#define LFXTOFFG_L             (0x0001)       /* LFXT Low Frequency Oscillator Fault Flag */
+#define HFXTOFFG_L             (0x0002)       /* HFXT High Frequency Oscillator Fault Flag */
+#define ENSTFCNT1_L            (0x0040)       /* Enable start counter for XT1 */
+#define ENSTFCNT2_L            (0x0080)       /* Enable start counter for XT2 */
+
+/* CSCTL6 Control Bits */
+#define ACLKREQEN              (0x0001)       /* ACLK Clock Request Enable */
+#define MCLKREQEN              (0x0002)       /* MCLK Clock Request Enable */
+#define SMCLKREQEN             (0x0004)       /* SMCLK Clock Request Enable */
+#define MODCLKREQEN            (0x0008)       /* MODOSC Clock Request Enable */
+
+/* CSCTL6 Control Bits */
+#define ACLKREQEN_L            (0x0001)       /* ACLK Clock Request Enable */
+#define MCLKREQEN_L            (0x0002)       /* MCLK Clock Request Enable */
+#define SMCLKREQEN_L           (0x0004)       /* SMCLK Clock Request Enable */
+#define MODCLKREQEN_L          (0x0008)       /* MODOSC Clock Request Enable */
+
+/************************************************************
+* DMA_X
+************************************************************/
+#define __MSP430_HAS_DMAX_3__                 /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_DMAX_3__ 0x0500
+#define DMA_BASE               __MSP430_BASEADDRESS_DMAX_3__
+
+sfr_w(DMACTL0);                               /* DMA Module Control 0 */
+sfr_b(DMACTL0_L);                             /* DMA Module Control 0 */
+sfr_b(DMACTL0_H);                             /* DMA Module Control 0 */
+sfr_w(DMACTL1);                               /* DMA Module Control 1 */
+sfr_b(DMACTL1_L);                             /* DMA Module Control 1 */
+sfr_b(DMACTL1_H);                             /* DMA Module Control 1 */
+sfr_w(DMACTL2);                               /* DMA Module Control 2 */
+sfr_b(DMACTL2_L);                             /* DMA Module Control 2 */
+sfr_b(DMACTL2_H);                             /* DMA Module Control 2 */
+sfr_w(DMACTL3);                               /* DMA Module Control 3 */
+sfr_b(DMACTL3_L);                             /* DMA Module Control 3 */
+sfr_b(DMACTL3_H);                             /* DMA Module Control 3 */
+sfr_w(DMACTL4);                               /* DMA Module Control 4 */
+sfr_b(DMACTL4_L);                             /* DMA Module Control 4 */
+sfr_b(DMACTL4_H);                             /* DMA Module Control 4 */
+sfr_w(DMAIV);                                 /* DMA Interrupt Vector Word */
+sfr_b(DMAIV_L);                               /* DMA Interrupt Vector Word */
+sfr_b(DMAIV_H);                               /* DMA Interrupt Vector Word */
+
+sfr_w(DMA0CTL);                               /* DMA Channel 0 Control */
+sfr_b(DMA0CTL_L);                             /* DMA Channel 0 Control */
+sfr_b(DMA0CTL_H);                             /* DMA Channel 0 Control */
+sfr_l(DMA0SA);                                /* DMA Channel 0 Source Address */
+sfr_w(DMA0SAL);                               /* DMA Channel 0 Source Address */
+sfr_w(DMA0SAH);                               /* DMA Channel 0 Source Address */
+sfr_l(DMA0DA);                                /* DMA Channel 0 Destination Address */
+sfr_w(DMA0DAL);                               /* DMA Channel 0 Destination Address */
+sfr_w(DMA0DAH);                               /* DMA Channel 0 Destination Address */
+sfr_w(DMA0SZ);                                /* DMA Channel 0 Transfer Size */
+
+sfr_w(DMA1CTL);                               /* DMA Channel 1 Control */
+sfr_b(DMA1CTL_L);                             /* DMA Channel 1 Control */
+sfr_b(DMA1CTL_H);                             /* DMA Channel 1 Control */
+sfr_l(DMA1SA);                                /* DMA Channel 1 Source Address */
+sfr_w(DMA1SAL);                               /* DMA Channel 1 Source Address */
+sfr_w(DMA1SAH);                               /* DMA Channel 1 Source Address */
+sfr_l(DMA1DA);                                /* DMA Channel 1 Destination Address */
+sfr_w(DMA1DAL);                               /* DMA Channel 1 Destination Address */
+sfr_w(DMA1DAH);                               /* DMA Channel 1 Destination Address */
+sfr_w(DMA1SZ);                                /* DMA Channel 1 Transfer Size */
+
+sfr_w(DMA2CTL);                               /* DMA Channel 2 Control */
+sfr_b(DMA2CTL_L);                             /* DMA Channel 2 Control */
+sfr_b(DMA2CTL_H);                             /* DMA Channel 2 Control */
+sfr_l(DMA2SA);                                /* DMA Channel 2 Source Address */
+sfr_w(DMA2SAL);                               /* DMA Channel 2 Source Address */
+sfr_w(DMA2SAH);                               /* DMA Channel 2 Source Address */
+sfr_l(DMA2DA);                                /* DMA Channel 2 Destination Address */
+sfr_w(DMA2DAL);                               /* DMA Channel 2 Destination Address */
+sfr_w(DMA2DAH);                               /* DMA Channel 2 Destination Address */
+sfr_w(DMA2SZ);                                /* DMA Channel 2 Transfer Size */
+
+/* DMACTL0 Control Bits */
+#define DMA0TSEL0              (0x0001)       /* DMA channel 0 transfer select bit 0 */
+#define DMA0TSEL1              (0x0002)       /* DMA channel 0 transfer select bit 1 */
+#define DMA0TSEL2              (0x0004)       /* DMA channel 0 transfer select bit 2 */
+#define DMA0TSEL3              (0x0008)       /* DMA channel 0 transfer select bit 3 */
+#define DMA0TSEL4              (0x0010)       /* DMA channel 0 transfer select bit 4 */
+#define DMA1TSEL0              (0x0100)       /* DMA channel 1 transfer select bit 0 */
+#define DMA1TSEL1              (0x0200)       /* DMA channel 1 transfer select bit 1 */
+#define DMA1TSEL2              (0x0400)       /* DMA channel 1 transfer select bit 2 */
+#define DMA1TSEL3              (0x0800)       /* DMA channel 1 transfer select bit 3 */
+#define DMA1TSEL4              (0x1000)       /* DMA channel 1 transfer select bit 4 */
+
+/* DMACTL0 Control Bits */
+#define DMA0TSEL0_L            (0x0001)       /* DMA channel 0 transfer select bit 0 */
+#define DMA0TSEL1_L            (0x0002)       /* DMA channel 0 transfer select bit 1 */
+#define DMA0TSEL2_L            (0x0004)       /* DMA channel 0 transfer select bit 2 */
+#define DMA0TSEL3_L            (0x0008)       /* DMA channel 0 transfer select bit 3 */
+#define DMA0TSEL4_L            (0x0010)       /* DMA channel 0 transfer select bit 4 */
+
+/* DMACTL0 Control Bits */
+#define DMA1TSEL0_H            (0x0001)       /* DMA channel 1 transfer select bit 0 */
+#define DMA1TSEL1_H            (0x0002)       /* DMA channel 1 transfer select bit 1 */
+#define DMA1TSEL2_H            (0x0004)       /* DMA channel 1 transfer select bit 2 */
+#define DMA1TSEL3_H            (0x0008)       /* DMA channel 1 transfer select bit 3 */
+#define DMA1TSEL4_H            (0x0010)       /* DMA channel 1 transfer select bit 4 */
+
+/* DMACTL01 Control Bits */
+#define DMA2TSEL0              (0x0001)       /* DMA channel 2 transfer select bit 0 */
+#define DMA2TSEL1              (0x0002)       /* DMA channel 2 transfer select bit 1 */
+#define DMA2TSEL2              (0x0004)       /* DMA channel 2 transfer select bit 2 */
+#define DMA2TSEL3              (0x0008)       /* DMA channel 2 transfer select bit 3 */
+#define DMA2TSEL4              (0x0010)       /* DMA channel 2 transfer select bit 4 */
+
+/* DMACTL01 Control Bits */
+#define DMA2TSEL0_L            (0x0001)       /* DMA channel 2 transfer select bit 0 */
+#define DMA2TSEL1_L            (0x0002)       /* DMA channel 2 transfer select bit 1 */
+#define DMA2TSEL2_L            (0x0004)       /* DMA channel 2 transfer select bit 2 */
+#define DMA2TSEL3_L            (0x0008)       /* DMA channel 2 transfer select bit 3 */
+#define DMA2TSEL4_L            (0x0010)       /* DMA channel 2 transfer select bit 4 */
+
+/* DMACTL4 Control Bits */
+#define ENNMI                  (0x0001)       /* Enable NMI interruption of DMA */
+#define ROUNDROBIN             (0x0002)       /* Round-Robin DMA channel priorities */
+#define DMARMWDIS              (0x0004)       /* Inhibited DMA transfers during read-modify-write CPU operations */
+
+/* DMACTL4 Control Bits */
+#define ENNMI_L                (0x0001)       /* Enable NMI interruption of DMA */
+#define ROUNDROBIN_L           (0x0002)       /* Round-Robin DMA channel priorities */
+#define DMARMWDIS_L            (0x0004)       /* Inhibited DMA transfers during read-modify-write CPU operations */
+
+/* DMAxCTL Control Bits */
+#define DMAREQ                 (0x0001)       /* Initiate DMA transfer with DMATSEL */
+#define DMAABORT               (0x0002)       /* DMA transfer aborted by NMI */
+#define DMAIE                  (0x0004)       /* DMA interrupt enable */
+#define DMAIFG                 (0x0008)       /* DMA interrupt flag */
+#define DMAEN                  (0x0010)       /* DMA enable */
+#define DMALEVEL               (0x0020)       /* DMA level sensitive trigger select */
+#define DMASRCBYTE             (0x0040)       /* DMA source byte */
+#define DMADSTBYTE             (0x0080)       /* DMA destination byte */
+#define DMASRCINCR0            (0x0100)       /* DMA source increment bit 0 */
+#define DMASRCINCR1            (0x0200)       /* DMA source increment bit 1 */
+#define DMADSTINCR0            (0x0400)       /* DMA destination increment bit 0 */
+#define DMADSTINCR1            (0x0800)       /* DMA destination increment bit 1 */
+#define DMADT0                 (0x1000)       /* DMA transfer mode bit 0 */
+#define DMADT1                 (0x2000)       /* DMA transfer mode bit 1 */
+#define DMADT2                 (0x4000)       /* DMA transfer mode bit 2 */
+
+/* DMAxCTL Control Bits */
+#define DMAREQ_L               (0x0001)       /* Initiate DMA transfer with DMATSEL */
+#define DMAABORT_L             (0x0002)       /* DMA transfer aborted by NMI */
+#define DMAIE_L                (0x0004)       /* DMA interrupt enable */
+#define DMAIFG_L               (0x0008)       /* DMA interrupt flag */
+#define DMAEN_L                (0x0010)       /* DMA enable */
+#define DMALEVEL_L             (0x0020)       /* DMA level sensitive trigger select */
+#define DMASRCBYTE_L           (0x0040)       /* DMA source byte */
+#define DMADSTBYTE_L           (0x0080)       /* DMA destination byte */
+
+/* DMAxCTL Control Bits */
+#define DMASRCINCR0_H          (0x0001)       /* DMA source increment bit 0 */
+#define DMASRCINCR1_H          (0x0002)       /* DMA source increment bit 1 */
+#define DMADSTINCR0_H          (0x0004)       /* DMA destination increment bit 0 */
+#define DMADSTINCR1_H          (0x0008)       /* DMA destination increment bit 1 */
+#define DMADT0_H               (0x0010)       /* DMA transfer mode bit 0 */
+#define DMADT1_H               (0x0020)       /* DMA transfer mode bit 1 */
+#define DMADT2_H               (0x0040)       /* DMA transfer mode bit 2 */
+
+#define DMASWDW                (0x0000)       /* DMA transfer: source word to destination word */
+#define DMASBDW                (0x0040)       /* DMA transfer: source byte to destination word */
+#define DMASWDB                (0x0080)       /* DMA transfer: source word to destination byte */
+#define DMASBDB                (0x00C0)       /* DMA transfer: source byte to destination byte */
+
+#define DMASRCINCR_0           (0x0000)       /* DMA source increment 0: source address unchanged */
+#define DMASRCINCR_1           (0x0100)       /* DMA source increment 1: source address unchanged */
+#define DMASRCINCR_2           (0x0200)       /* DMA source increment 2: source address decremented */
+#define DMASRCINCR_3           (0x0300)       /* DMA source increment 3: source address incremented */
+
+#define DMADSTINCR_0           (0x0000)       /* DMA destination increment 0: destination address unchanged */
+#define DMADSTINCR_1           (0x0400)       /* DMA destination increment 1: destination address unchanged */
+#define DMADSTINCR_2           (0x0800)       /* DMA destination increment 2: destination address decremented */
+#define DMADSTINCR_3           (0x0C00)       /* DMA destination increment 3: destination address incremented */
+
+#define DMADT_0                (0x0000)       /* DMA transfer mode 0: Single transfer */
+#define DMADT_1                (0x1000)       /* DMA transfer mode 1: Block transfer */
+#define DMADT_2                (0x2000)       /* DMA transfer mode 2: Burst-Block transfer */
+#define DMADT_3                (0x3000)       /* DMA transfer mode 3: Burst-Block transfer */
+#define DMADT_4                (0x4000)       /* DMA transfer mode 4: Repeated Single transfer */
+#define DMADT_5                (0x5000)       /* DMA transfer mode 5: Repeated Block transfer */
+#define DMADT_6                (0x6000)       /* DMA transfer mode 6: Repeated Burst-Block transfer */
+#define DMADT_7                (0x7000)       /* DMA transfer mode 7: Repeated Burst-Block transfer */
+
+/* DMAIV Definitions */
+#define DMAIV_NONE             (0x0000)       /* No Interrupt pending */
+#define DMAIV_DMA0IFG          (0x0002)       /* DMA0IFG*/
+#define DMAIV_DMA1IFG          (0x0004)       /* DMA1IFG*/
+#define DMAIV_DMA2IFG          (0x0006)       /* DMA2IFG*/
+
+#define DMA0TSEL_0             (0x0000)       /* DMA channel 0 transfer select 0:  DMA_REQ (sw) */
+#define DMA0TSEL_1             (0x0001)       /* DMA channel 0 transfer select 1:  */
+#define DMA0TSEL_2             (0x0002)       /* DMA channel 0 transfer select 2:  */
+#define DMA0TSEL_3             (0x0003)       /* DMA channel 0 transfer select 3:  */
+#define DMA0TSEL_4             (0x0004)       /* DMA channel 0 transfer select 4:  */
+#define DMA0TSEL_5             (0x0005)       /* DMA channel 0 transfer select 5:  */
+#define DMA0TSEL_6             (0x0006)       /* DMA channel 0 transfer select 6:  */
+#define DMA0TSEL_7             (0x0007)       /* DMA channel 0 transfer select 7:  */
+#define DMA0TSEL_8             (0x0008)       /* DMA channel 0 transfer select 8:  */
+#define DMA0TSEL_9             (0x0009)       /* DMA channel 0 transfer select 9:  */
+#define DMA0TSEL_10            (0x000A)       /* DMA channel 0 transfer select 10: */
+#define DMA0TSEL_11            (0x000B)       /* DMA channel 0 transfer select 11: */
+#define DMA0TSEL_12            (0x000C)       /* DMA channel 0 transfer select 12: */
+#define DMA0TSEL_13            (0x000D)       /* DMA channel 0 transfer select 13: */
+#define DMA0TSEL_14            (0x000E)       /* DMA channel 0 transfer select 14: */
+#define DMA0TSEL_15            (0x000F)       /* DMA channel 0 transfer select 15: */
+#define DMA0TSEL_16            (0x0010)       /* DMA channel 0 transfer select 16: */
+#define DMA0TSEL_17            (0x0011)       /* DMA channel 0 transfer select 17: */
+#define DMA0TSEL_18            (0x0012)       /* DMA channel 0 transfer select 18: */
+#define DMA0TSEL_19            (0x0013)       /* DMA channel 0 transfer select 19: */
+#define DMA0TSEL_20            (0x0014)       /* DMA channel 0 transfer select 20: */
+#define DMA0TSEL_21            (0x0015)       /* DMA channel 0 transfer select 21: */
+#define DMA0TSEL_22            (0x0016)       /* DMA channel 0 transfer select 22: */
+#define DMA0TSEL_23            (0x0017)       /* DMA channel 0 transfer select 23: */
+#define DMA0TSEL_24            (0x0018)       /* DMA channel 0 transfer select 24: */
+#define DMA0TSEL_25            (0x0019)       /* DMA channel 0 transfer select 25: */
+#define DMA0TSEL_26            (0x001A)       /* DMA channel 0 transfer select 26: */
+#define DMA0TSEL_27            (0x001B)       /* DMA channel 0 transfer select 27: */
+#define DMA0TSEL_28            (0x001C)       /* DMA channel 0 transfer select 28: */
+#define DMA0TSEL_29            (0x001D)       /* DMA channel 0 transfer select 29: */
+#define DMA0TSEL_30            (0x001E)       /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */
+#define DMA0TSEL_31            (0x001F)       /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */
+
+#define DMA1TSEL_0             (0x0000)       /* DMA channel 1 transfer select 0:  DMA_REQ (sw) */
+#define DMA1TSEL_1             (0x0100)       /* DMA channel 1 transfer select 1:  */
+#define DMA1TSEL_2             (0x0200)       /* DMA channel 1 transfer select 2:  */
+#define DMA1TSEL_3             (0x0300)       /* DMA channel 1 transfer select 3:  */
+#define DMA1TSEL_4             (0x0400)       /* DMA channel 1 transfer select 4:  */
+#define DMA1TSEL_5             (0x0500)       /* DMA channel 1 transfer select 5:  */
+#define DMA1TSEL_6             (0x0600)       /* DMA channel 1 transfer select 6:  */
+#define DMA1TSEL_7             (0x0700)       /* DMA channel 1 transfer select 7:  */
+#define DMA1TSEL_8             (0x0800)       /* DMA channel 1 transfer select 8:  */
+#define DMA1TSEL_9             (0x0900)       /* DMA channel 1 transfer select 9:  */
+#define DMA1TSEL_10            (0x0A00)       /* DMA channel 1 transfer select 10: */
+#define DMA1TSEL_11            (0x0B00)       /* DMA channel 1 transfer select 11: */
+#define DMA1TSEL_12            (0x0C00)       /* DMA channel 1 transfer select 12: */
+#define DMA1TSEL_13            (0x0D00)       /* DMA channel 1 transfer select 13: */
+#define DMA1TSEL_14            (0x0E00)       /* DMA channel 1 transfer select 14: */
+#define DMA1TSEL_15            (0x0F00)       /* DMA channel 1 transfer select 15: */
+#define DMA1TSEL_16            (0x1000)       /* DMA channel 1 transfer select 16: */
+#define DMA1TSEL_17            (0x1100)       /* DMA channel 1 transfer select 17: */
+#define DMA1TSEL_18            (0x1200)       /* DMA channel 1 transfer select 18: */
+#define DMA1TSEL_19            (0x1300)       /* DMA channel 1 transfer select 19: */
+#define DMA1TSEL_20            (0x1400)       /* DMA channel 1 transfer select 20: */
+#define DMA1TSEL_21            (0x1500)       /* DMA channel 1 transfer select 21: */
+#define DMA1TSEL_22            (0x1600)       /* DMA channel 1 transfer select 22: */
+#define DMA1TSEL_23            (0x1700)       /* DMA channel 1 transfer select 23: */
+#define DMA1TSEL_24            (0x1800)       /* DMA channel 1 transfer select 24: */
+#define DMA1TSEL_25            (0x1900)       /* DMA channel 1 transfer select 25: */
+#define DMA1TSEL_26            (0x1A00)       /* DMA channel 1 transfer select 26: */
+#define DMA1TSEL_27            (0x1B00)       /* DMA channel 1 transfer select 27: */
+#define DMA1TSEL_28            (0x1C00)       /* DMA channel 1 transfer select 28: */
+#define DMA1TSEL_29            (0x1D00)       /* DMA channel 1 transfer select 29: */
+#define DMA1TSEL_30            (0x1E00)       /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */
+#define DMA1TSEL_31            (0x1F00)       /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */
+
+#define DMA2TSEL_0             (0x0000)       /* DMA channel 2 transfer select 0:  DMA_REQ (sw) */
+#define DMA2TSEL_1             (0x0001)       /* DMA channel 2 transfer select 1:  */
+#define DMA2TSEL_2             (0x0002)       /* DMA channel 2 transfer select 2:  */
+#define DMA2TSEL_3             (0x0003)       /* DMA channel 2 transfer select 3:  */
+#define DMA2TSEL_4             (0x0004)       /* DMA channel 2 transfer select 4:  */
+#define DMA2TSEL_5             (0x0005)       /* DMA channel 2 transfer select 5:  */
+#define DMA2TSEL_6             (0x0006)       /* DMA channel 2 transfer select 6:  */
+#define DMA2TSEL_7             (0x0007)       /* DMA channel 2 transfer select 7:  */
+#define DMA2TSEL_8             (0x0008)       /* DMA channel 2 transfer select 8:  */
+#define DMA2TSEL_9             (0x0009)       /* DMA channel 2 transfer select 9:  */
+#define DMA2TSEL_10            (0x000A)       /* DMA channel 2 transfer select 10: */
+#define DMA2TSEL_11            (0x000B)       /* DMA channel 2 transfer select 11: */
+#define DMA2TSEL_12            (0x000C)       /* DMA channel 2 transfer select 12: */
+#define DMA2TSEL_13            (0x000D)       /* DMA channel 2 transfer select 13: */
+#define DMA2TSEL_14            (0x000E)       /* DMA channel 2 transfer select 14: */
+#define DMA2TSEL_15            (0x000F)       /* DMA channel 2 transfer select 15: */
+#define DMA2TSEL_16            (0x0010)       /* DMA channel 2 transfer select 16: */
+#define DMA2TSEL_17            (0x0011)       /* DMA channel 2 transfer select 17: */
+#define DMA2TSEL_18            (0x0012)       /* DMA channel 2 transfer select 18: */
+#define DMA2TSEL_19            (0x0013)       /* DMA channel 2 transfer select 19: */
+#define DMA2TSEL_20            (0x0014)       /* DMA channel 2 transfer select 20: */
+#define DMA2TSEL_21            (0x0015)       /* DMA channel 2 transfer select 21: */
+#define DMA2TSEL_22            (0x0016)       /* DMA channel 2 transfer select 22: */
+#define DMA2TSEL_23            (0x0017)       /* DMA channel 2 transfer select 23: */
+#define DMA2TSEL_24            (0x0018)       /* DMA channel 2 transfer select 24: */
+#define DMA2TSEL_25            (0x0019)       /* DMA channel 2 transfer select 25: */
+#define DMA2TSEL_26            (0x001A)       /* DMA channel 2 transfer select 26: */
+#define DMA2TSEL_27            (0x001B)       /* DMA channel 2 transfer select 27: */
+#define DMA2TSEL_28            (0x001C)       /* DMA channel 2 transfer select 28: */
+#define DMA2TSEL_29            (0x001D)       /* DMA channel 2 transfer select 29: */
+#define DMA2TSEL_30            (0x001E)       /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */
+#define DMA2TSEL_31            (0x001F)       /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */
+
+#define DMA0TSEL__DMAREQ       (0x0000)       /* DMA channel 0 transfer select 0:  DMA_REQ (sw) */
+#define DMA0TSEL__TA0CCR0      (0x0001)       /* DMA channel 0 transfer select 1:  TA0CCR0 */
+#define DMA0TSEL__TA0CCR2      (0x0002)       /* DMA channel 0 transfer select 2:  TA0CCR2 */
+#define DMA0TSEL__TA1CCR0      (0x0003)       /* DMA channel 0 transfer select 3:  TA1CCR0 */
+#define DMA0TSEL__TA1CCR2      (0x0004)       /* DMA channel 0 transfer select 4:  TA1CCR2 */
+#define DMA0TSEL__TA2CCR0      (0x0005)       /* DMA channel 0 transfer select 3:  TA2CCR0 */
+#define DMA0TSEL__TA3CCR0      (0x0006)       /* DMA channel 0 transfer select 4:  TA3CCR0 */
+#define DMA0TSEL__TB0CCR0      (0x0007)       /* DMA channel 0 transfer select 7:  TB0CCR0 */
+#define DMA0TSEL__TB0CCR2      (0x0008)       /* DMA channel 0 transfer select 8:  TB0CCR2 */
+#define DMA0TSEL__RES9         (0x0009)       /* DMA channel 0 transfer select 9:  RES9 */
+#define DMA0TSEL__RES10        (0x000A)       /* DMA channel 0 transfer select 10: RES10 */
+#define DMA0TSEL__RES11        (0x000B)       /* DMA channel 0 transfer select 11: RES11 */
+#define DMA0TSEL__RES12        (0x000C)       /* DMA channel 0 transfer select 12: RES12 */
+#define DMA0TSEL__RES13        (0x000D)       /* DMA channel 0 transfer select 13: RES13 */
+#define DMA0TSEL__UCA0RXIFG    (0x000E)       /* DMA channel 0 transfer select 14: UCA0RXIFG */
+#define DMA0TSEL__UCA0TXIFG    (0x000F)       /* DMA channel 0 transfer select 15: UCA0TXIFG */
+#define DMA0TSEL__UCA1RXIFG    (0x0010)       /* DMA channel 0 transfer select 16: UCA1RXIFG */
+#define DMA0TSEL__UCA1TXIFG    (0x0011)       /* DMA channel 0 transfer select 17: UCA1TXIFG */
+#define DMA0TSEL__UCB0RXIFG0   (0x0012)       /* DMA channel 0 transfer select 18: UCB0RXIFG0 */
+#define DMA0TSEL__UCB0TXIFG0   (0x0013)       /* DMA channel 0 transfer select 19: UCB0TXIFG0 */
+#define DMA0TSEL__UCB0RXIFG1   (0x0014)       /* DMA channel 0 transfer select 20: UCB0RXIFG1 */
+#define DMA0TSEL__UCB0TXIFG1   (0x0015)       /* DMA channel 0 transfer select 21: UCB0TXIFG1 */
+#define DMA0TSEL__UCB0RXIFG2   (0x0016)       /* DMA channel 0 transfer select 22: UCB0RXIFG2 */
+#define DMA0TSEL__UCB0TXIFG2   (0x0017)       /* DMA channel 0 transfer select 23: UCB0TXIFG2 */
+#define DMA0TSEL__UCB0RXIFG3   (0x0018)       /* DMA channel 0 transfer select 24: UCB0RXIFG3 */
+#define DMA0TSEL__UCB0TXIFG3   (0x0019)       /* DMA channel 0 transfer select 25: UCB0TXIFG3 */
+#define DMA0TSEL__ADC12IFG     (0x001A)       /* DMA channel 0 transfer select 26: ADC12IFG */
+#define DMA0TSEL__RES27        (0x001B)       /* DMA channel 0 transfer select 27: RES27 */
+#define DMA0TSEL__RES28        (0x001C)       /* DMA channel 0 transfer select 28: RES28 */
+#define DMA0TSEL__MPY          (0x001D)       /* DMA channel 0 transfer select 29: MPY */
+#define DMA0TSEL__DMA2IFG      (0x001E)       /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */
+#define DMA0TSEL__DMAE0        (0x001F)       /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */
+
+#define DMA1TSEL__DMAREQ       (0x0000)       /* DMA channel 1 transfer select 0:  DMA_REQ (sw) */
+#define DMA1TSEL__TA0CCR0      (0x0100)       /* DMA channel 1 transfer select 1:  TA0CCR0 */
+#define DMA1TSEL__TA0CCR2      (0x0200)       /* DMA channel 1 transfer select 2:  TA0CCR2 */
+#define DMA1TSEL__TA1CCR0      (0x0300)       /* DMA channel 1 transfer select 3:  TA1CCR0 */
+#define DMA1TSEL__TA1CCR2      (0x0400)       /* DMA channel 1 transfer select 4:  TA1CCR2 */
+#define DMA1TSEL__TA2CCR0      (0x0500)       /* DMA channel 1 transfer select 5:  TA2CCR0 */
+#define DMA1TSEL__TA3CCR0      (0x0600)       /* DMA channel 1 transfer select 6:  TA3CCR0 */
+#define DMA1TSEL__TB0CCR0      (0x0700)       /* DMA channel 1 transfer select 7:  TB0CCR0 */
+#define DMA1TSEL__TB0CCR2      (0x0800)       /* DMA channel 1 transfer select 8:  TB0CCR2 */
+#define DMA1TSEL__RES9         (0x0900)       /* DMA channel 1 transfer select 9:  RES9 */
+#define DMA1TSEL__RES10        (0x0A00)       /* DMA channel 1 transfer select 10: RES10 */
+#define DMA1TSEL__RES11        (0x0B00)       /* DMA channel 1 transfer select 11: RES11 */
+#define DMA1TSEL__RES12        (0x0C00)       /* DMA channel 1 transfer select 12: RES12 */
+#define DMA1TSEL__RES13        (0x0D00)       /* DMA channel 1 transfer select 13: RES13 */
+#define DMA1TSEL__UCA0RXIFG    (0x0E00)       /* DMA channel 1 transfer select 14: UCA0RXIFG */
+#define DMA1TSEL__UCA0TXIFG    (0x0F00)       /* DMA channel 1 transfer select 15: UCA0TXIFG */
+#define DMA1TSEL__UCA1RXIFG    (0x1000)       /* DMA channel 1 transfer select 16: UCA1RXIFG */
+#define DMA1TSEL__UCA1TXIFG    (0x1100)       /* DMA channel 1 transfer select 17: UCA1TXIFG */
+#define DMA1TSEL__UCB0RXIFG0   (0x1200)       /* DMA channel 1 transfer select 18: UCB0RXIFG0 */
+#define DMA1TSEL__UCB0TXIFG0   (0x1300)       /* DMA channel 1 transfer select 19: UCB0TXIFG0 */
+#define DMA1TSEL__UCB0RXIFG1   (0x1400)       /* DMA channel 1 transfer select 20: UCB0RXIFG1 */
+#define DMA1TSEL__UCB0TXIFG1   (0x1500)       /* DMA channel 1 transfer select 21: UCB0TXIFG1 */
+#define DMA1TSEL__UCB0RXIFG2   (0x1600)       /* DMA channel 1 transfer select 22: UCB0RXIFG2 */
+#define DMA1TSEL__UCB0TXIFG2   (0x1700)       /* DMA channel 1 transfer select 23: UCB0TXIFG2 */
+#define DMA1TSEL__UCB0RXIFG3   (0x1800)       /* DMA channel 1 transfer select 24: UCB0RXIFG3 */
+#define DMA1TSEL__UCB0TXIFG3   (0x1900)       /* DMA channel 1 transfer select 25: UCB0TXIFG3 */
+#define DMA1TSEL__ADC12IFG     (0x1A00)       /* DMA channel 1 transfer select 26: ADC12IFG */
+#define DMA1TSEL__RES27        (0x1B00)       /* DMA channel 1 transfer select 27: RES27 */
+#define DMA1TSEL__RES28        (0x1C00)       /* DMA channel 1 transfer select 28: RES28 */
+#define DMA1TSEL__MPY          (0x1D00)       /* DMA channel 1 transfer select 29: MPY */
+#define DMA1TSEL__DMA2IFG      (0x1E00)       /* DMA channel 1 transfer select 30: previous DMA channel DMA2IFG */
+#define DMA1TSEL__DMAE0        (0x1F00)       /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */
+
+#define DMA2TSEL__DMAREQ       (0x0000)       /* DMA channel 2 transfer select 0:  DMA_REQ (sw) */
+#define DMA2TSEL__TA0CCR0      (0x0001)       /* DMA channel 2 transfer select 1:  TA0CCR0 */
+#define DMA2TSEL__TA0CCR2      (0x0002)       /* DMA channel 2 transfer select 2:  TA0CCR2 */
+#define DMA2TSEL__TA1CCR0      (0x0003)       /* DMA channel 2 transfer select 3:  TA1CCR0 */
+#define DMA2TSEL__TA1CCR2      (0x0004)       /* DMA channel 2 transfer select 4:  TA1CCR2 */
+#define DMA2TSEL__TA2CCR0      (0x0005)       /* DMA channel 2 transfer select 5:  TA2CCR0 */
+#define DMA2TSEL__TA3CCR0      (0x0006)       /* DMA channel 2 transfer select 6:  TA3CCR0 */
+#define DMA2TSEL__TB0CCR0      (0x0007)       /* DMA channel 2 transfer select 7:  TB0CCR0 */
+#define DMA2TSEL__TB0CCR2      (0x0008)       /* DMA channel 2 transfer select 8:  TB0CCR2 */
+#define DMA2TSEL__RES9         (0x0009)       /* DMA channel 2 transfer select 9:  RES9 */
+#define DMA2TSEL__RES10        (0x000A)       /* DMA channel 2 transfer select 10: RES10 */
+#define DMA2TSEL__RES11        (0x000B)       /* DMA channel 2 transfer select 11: RES11 */
+#define DMA2TSEL__RES12        (0x000C)       /* DMA channel 2 transfer select 12: RES12 */
+#define DMA2TSEL__RES13        (0x000D)       /* DMA channel 2 transfer select 13: RES13 */
+#define DMA2TSEL__UCA0RXIFG    (0x000E)       /* DMA channel 2 transfer select 14: UCA0RXIFG */
+#define DMA2TSEL__UCA0TXIFG    (0x000F)       /* DMA channel 2 transfer select 15: UCA0TXIFG */
+#define DMA2TSEL__UCA1RXIFG    (0x0010)       /* DMA channel 2 transfer select 16: UCA1RXIFG */
+#define DMA2TSEL__UCA1TXIFG    (0x0011)       /* DMA channel 2 transfer select 17: UCA1TXIFG */
+#define DMA2TSEL__UCB0RXIFG0   (0x0012)       /* DMA channel 2 transfer select 18: UCB0RXIFG0 */
+#define DMA2TSEL__UCB0TXIFG0   (0x0013)       /* DMA channel 2 transfer select 19: UCB0TXIFG0 */
+#define DMA2TSEL__UCB0RXIFG1   (0x0014)       /* DMA channel 2 transfer select 20: UCB0RXIFG1 */
+#define DMA2TSEL__UCB0TXIFG1   (0x0015)       /* DMA channel 2 transfer select 21: UCB0TXIFG1 */
+#define DMA2TSEL__UCB0RXIFG2   (0x0016)       /* DMA channel 2 transfer select 22: UCB0RXIFG2 */
+#define DMA2TSEL__UCB0TXIFG2   (0x0017)       /* DMA channel 2 transfer select 23: UCB0TXIFG2 */
+#define DMA2TSEL__UCB0RXIFG3   (0x0018)       /* DMA channel 2 transfer select 24: UCB0RXIFG3 */
+#define DMA2TSEL__UCB0TXIFG3   (0x0019)       /* DMA channel 2 transfer select 25: UCB0TXIFG3 */
+#define DMA2TSEL__ADC12IFG     (0x001A)       /* DMA channel 2 transfer select 26: ADC12IFG */
+#define DMA2TSEL__RES27        (0x001B)       /* DMA channel 2 transfer select 27: RES27 */
+#define DMA2TSEL__RES28        (0x001C)       /* DMA channel 2 transfer select 28: RES28 */
+#define DMA2TSEL__MPY          (0x001D)       /* DMA channel 2 transfer select 29: MPY */
+#define DMA2TSEL__DMA2IFG      (0x001E)       /* DMA channel 2 transfer select 30: previous DMA channel DMA2IFG */
+#define DMA2TSEL__DMAE0        (0x001F)       /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */
+
+/*************************************************************
+* FRAM Memory
+*************************************************************/
+#define __MSP430_HAS_FRAM__                   /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_FRAM__ 0x0140
+#define FRAM_BASE              __MSP430_BASEADDRESS_FRAM__
+#define __MSP430_HAS_GC__                     /* Definition to show that Module is available */
+
+sfr_w(FRCTL0);                                /* FRAM Controller Control 0 */
+sfr_b(FRCTL0_L);                              /* FRAM Controller Control 0 */
+sfr_b(FRCTL0_H);                              /* FRAM Controller Control 0 */
+sfr_w(GCCTL0);                                /* General Control 0 */
+sfr_b(GCCTL0_L);                              /* General Control 0 */
+sfr_b(GCCTL0_H);                              /* General Control 0 */
+sfr_w(GCCTL1);                                /* General Control 1 */
+sfr_b(GCCTL1_L);                              /* General Control 1 */
+sfr_b(GCCTL1_H);                              /* General Control 1 */
+
+#define FRCTLPW                (0xA500)       /* FRAM password for write */
+#define FRPW                   (0x9600)       /* FRAM password returned by read */
+#define FWPW                   (0xA500)       /* FRAM password for write */
+#define FXPW                   (0x3300)       /* for use with XOR instruction */
+
+/* FRCTL0 Control Bits */
+//#define RESERVED            (0x0001)  /* RESERVED */
+//#define RESERVED            (0x0002)  /* RESERVED */
+//#define RESERVED            (0x0004)  /* RESERVED */
+#define NWAITS0                (0x0010)       /* FRAM Wait state control Bit: 0 */
+#define NWAITS1                (0x0020)       /* FRAM Wait state control Bit: 1 */
+#define NWAITS2                (0x0040)       /* FRAM Wait state control Bit: 2 */
+//#define RESERVED            (0x0080)  /* RESERVED */
+
+/* FRCTL0 Control Bits */
+//#define RESERVED            (0x0001)  /* RESERVED */
+//#define RESERVED            (0x0002)  /* RESERVED */
+//#define RESERVED            (0x0004)  /* RESERVED */
+#define NWAITS0_L              (0x0010)       /* FRAM Wait state control Bit: 0 */
+#define NWAITS1_L              (0x0020)       /* FRAM Wait state control Bit: 1 */
+#define NWAITS2_L              (0x0040)       /* FRAM Wait state control Bit: 2 */
+//#define RESERVED            (0x0080)  /* RESERVED */
+
+#define NWAITS_0               (0x0000)       /* FRAM Wait state control: 0 */
+#define NWAITS_1               (0x0010)       /* FRAM Wait state control: 1 */
+#define NWAITS_2               (0x0020)       /* FRAM Wait state control: 2 */
+#define NWAITS_3               (0x0030)       /* FRAM Wait state control: 3 */
+#define NWAITS_4               (0x0040)       /* FRAM Wait state control: 4 */
+#define NWAITS_5               (0x0050)       /* FRAM Wait state control: 5 */
+#define NWAITS_6               (0x0060)       /* FRAM Wait state control: 6 */
+#define NWAITS_7               (0x0070)       /* FRAM Wait state control: 7 */
+
+/* Legacy Defines */
+#define NACCESS0               (0x0010)       /* FRAM Wait state Generator Access Time control Bit: 0 */
+#define NACCESS1               (0x0020)       /* FRAM Wait state Generator Access Time control Bit: 1 */
+#define NACCESS2               (0x0040)       /* FRAM Wait state Generator Access Time control Bit: 2 */
+#define NACCESS_0              (0x0000)       /* FRAM Wait state Generator Access Time control: 0 */
+#define NACCESS_1              (0x0010)       /* FRAM Wait state Generator Access Time control: 1 */
+#define NACCESS_2              (0x0020)       /* FRAM Wait state Generator Access Time control: 2 */
+#define NACCESS_3              (0x0030)       /* FRAM Wait state Generator Access Time control: 3 */
+#define NACCESS_4              (0x0040)       /* FRAM Wait state Generator Access Time control: 4 */
+#define NACCESS_5              (0x0050)       /* FRAM Wait state Generator Access Time control: 5 */
+#define NACCESS_6              (0x0060)       /* FRAM Wait state Generator Access Time control: 6 */
+#define NACCESS_7              (0x0070)       /* FRAM Wait state Generator Access Time control: 7 */
+
+/* GCCTL0 Control Bits */
+//#define RESERVED            (0x0001)  /* RESERVED */
+#define FRLPMPWR               (0x0002)       /* FRAM Enable FRAM auto power up after LPM */
+#define FRPWR                  (0x0004)       /* FRAM Power Control */
+#define ACCTEIE                (0x0008)       /* RESERVED */
+//#define RESERVED            (0x0010)  /* RESERVED */
+#define CBDIE                  (0x0020)       /* Enable NMI event if correctable bit error detected */
+#define UBDIE                  (0x0040)       /* Enable NMI event if uncorrectable bit error detected */
+#define UBDRSTEN               (0x0080)       /* Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected */
+
+/* GCCTL0 Control Bits */
+//#define RESERVED            (0x0001)  /* RESERVED */
+#define FRLPMPWR_L             (0x0002)       /* FRAM Enable FRAM auto power up after LPM */
+#define FRPWR_L                (0x0004)       /* FRAM Power Control */
+#define ACCTEIE_L              (0x0008)       /* RESERVED */
+//#define RESERVED            (0x0010)  /* RESERVED */
+#define CBDIE_L                (0x0020)       /* Enable NMI event if correctable bit error detected */
+#define UBDIE_L                (0x0040)       /* Enable NMI event if uncorrectable bit error detected */
+#define UBDRSTEN_L             (0x0080)       /* Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected */
+
+/* GCCTL1 Control Bits */
+//#define RESERVED            (0x0001)  /* RESERVED */
+#define CBDIFG                 (0x0002)       /* FRAM correctable bit error flag */
+#define UBDIFG                 (0x0004)       /* FRAM uncorrectable bit error flag */
+#define ACCTEIFG               (0x0008)       /* Access time error flag */
+
+/* GCCTL1 Control Bits */
+//#define RESERVED            (0x0001)  /* RESERVED */
+#define CBDIFG_L               (0x0002)       /* FRAM correctable bit error flag */
+#define UBDIFG_L               (0x0004)       /* FRAM uncorrectable bit error flag */
+#define ACCTEIFG_L             (0x0008)       /* Access time error flag */
+
+/************************************************************
+* Memory Protection Unit
+************************************************************/
+#define __MSP430_HAS_MPU__                    /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_MPU__ 0x05A0
+#define MPU_BASE               __MSP430_BASEADDRESS_MPU__
+
+sfr_w(MPUCTL0);                               /* MPU Control Register 0 */
+sfr_b(MPUCTL0_L);                             /* MPU Control Register 0 */
+sfr_b(MPUCTL0_H);                             /* MPU Control Register 0 */
+sfr_w(MPUCTL1);                               /* MPU Control Register 1 */
+sfr_b(MPUCTL1_L);                             /* MPU Control Register 1 */
+sfr_b(MPUCTL1_H);                             /* MPU Control Register 1 */
+sfr_w(MPUSEGB2);                              /* MPU Segmentation Border 2 Register */
+sfr_b(MPUSEGB2_L);                            /* MPU Segmentation Border 2 Register */
+sfr_b(MPUSEGB2_H);                            /* MPU Segmentation Border 2 Register */
+sfr_w(MPUSEGB1);                              /* MPU Segmentation Border 1 Register */
+sfr_b(MPUSEGB1_L);                            /* MPU Segmentation Border 1 Register */
+sfr_b(MPUSEGB1_H);                            /* MPU Segmentation Border 1 Register */
+sfr_w(MPUSAM);                                /* MPU Access Management Register */
+sfr_b(MPUSAM_L);                              /* MPU Access Management Register */
+sfr_b(MPUSAM_H);                              /* MPU Access Management Register */
+sfr_w(MPUIPC0);                               /* MPU IP Control 0 Register */
+sfr_b(MPUIPC0_L);                             /* MPU IP Control 0 Register */
+sfr_b(MPUIPC0_H);                             /* MPU IP Control 0 Register */
+sfr_w(MPUIPSEGB2);                            /* MPU IP Segment Border 2 Register */
+sfr_b(MPUIPSEGB2_L);                          /* MPU IP Segment Border 2 Register */
+sfr_b(MPUIPSEGB2_H);                          /* MPU IP Segment Border 2 Register */
+sfr_w(MPUIPSEGB1);                            /* MPU IP Segment Border 1 Register */
+sfr_b(MPUIPSEGB1_L);                          /* MPU IP Segment Border 1 Register */
+sfr_b(MPUIPSEGB1_H);                          /* MPU IP Segment Border 1 Register */
+
+/* MPUCTL0 Control Bits */
+#define MPUENA                 (0x0001)       /* MPU Enable */
+#define MPULOCK                (0x0002)       /* MPU Lock */
+#define MPUSEGIE               (0x0010)       /* MPU Enable NMI on Segment violation */
+
+/* MPUCTL0 Control Bits */
+#define MPUENA_L               (0x0001)       /* MPU Enable */
+#define MPULOCK_L              (0x0002)       /* MPU Lock */
+#define MPUSEGIE_L             (0x0010)       /* MPU Enable NMI on Segment violation */
+
+#define MPUPW                  (0xA500)       /* MPU Access Password */
+#define MPUPW_H                (0xA5)         /* MPU Access Password */
+
+/* MPUCTL1 Control Bits */
+#define MPUSEG1IFG             (0x0001)       /* MPU Main Memory Segment 1 violation interupt flag */
+#define MPUSEG2IFG             (0x0002)       /* MPU Main Memory Segment 2 violation interupt flag */
+#define MPUSEG3IFG             (0x0004)       /* MPU Main Memory Segment 3 violation interupt flag */
+#define MPUSEGIIFG             (0x0008)       /* MPU Info Memory Segment violation interupt flag */
+#define MPUSEGIPIFG            (0x0010)       /* MPU IP Memory Segment violation interupt flag */
+
+/* MPUCTL1 Control Bits */
+#define MPUSEG1IFG_L           (0x0001)       /* MPU Main Memory Segment 1 violation interupt flag */
+#define MPUSEG2IFG_L           (0x0002)       /* MPU Main Memory Segment 2 violation interupt flag */
+#define MPUSEG3IFG_L           (0x0004)       /* MPU Main Memory Segment 3 violation interupt flag */
+#define MPUSEGIIFG_L           (0x0008)       /* MPU Info Memory Segment violation interupt flag */
+#define MPUSEGIPIFG_L          (0x0010)       /* MPU IP Memory Segment violation interupt flag */
+
+/* MPUSEGB2 Control Bits */
+
+/* MPUSEGB2 Control Bits */
+
+/* MPUSEGB2 Control Bits */
+
+/* MPUSEGB1 Control Bits */
+
+/* MPUSEGB1 Control Bits */
+
+/* MPUSEGB1 Control Bits */
+
+/* MPUSAM Control Bits */
+#define MPUSEG1RE              (0x0001)       /* MPU Main memory Segment 1 Read enable */
+#define MPUSEG1WE              (0x0002)       /* MPU Main memory Segment 1 Write enable */
+#define MPUSEG1XE              (0x0004)       /* MPU Main memory Segment 1 Execute enable */
+#define MPUSEG1VS              (0x0008)       /* MPU Main memory Segment 1 Violation select */
+#define MPUSEG2RE              (0x0010)       /* MPU Main memory Segment 2 Read enable */
+#define MPUSEG2WE              (0x0020)       /* MPU Main memory Segment 2 Write enable */
+#define MPUSEG2XE              (0x0040)       /* MPU Main memory Segment 2 Execute enable */
+#define MPUSEG2VS              (0x0080)       /* MPU Main memory Segment 2 Violation select */
+#define MPUSEG3RE              (0x0100)       /* MPU Main memory Segment 3 Read enable */
+#define MPUSEG3WE              (0x0200)       /* MPU Main memory Segment 3 Write enable */
+#define MPUSEG3XE              (0x0400)       /* MPU Main memory Segment 3 Execute enable */
+#define MPUSEG3VS              (0x0800)       /* MPU Main memory Segment 3 Violation select */
+#define MPUSEGIRE              (0x1000)       /* MPU Info memory Segment Read enable */
+#define MPUSEGIWE              (0x2000)       /* MPU Info memory Segment Write enable */
+#define MPUSEGIXE              (0x4000)       /* MPU Info memory Segment Execute enable */
+#define MPUSEGIVS              (0x8000)       /* MPU Info memory Segment Violation select */
+
+/* MPUSAM Control Bits */
+#define MPUSEG1RE_L            (0x0001)       /* MPU Main memory Segment 1 Read enable */
+#define MPUSEG1WE_L            (0x0002)       /* MPU Main memory Segment 1 Write enable */
+#define MPUSEG1XE_L            (0x0004)       /* MPU Main memory Segment 1 Execute enable */
+#define MPUSEG1VS_L            (0x0008)       /* MPU Main memory Segment 1 Violation select */
+#define MPUSEG2RE_L            (0x0010)       /* MPU Main memory Segment 2 Read enable */
+#define MPUSEG2WE_L            (0x0020)       /* MPU Main memory Segment 2 Write enable */
+#define MPUSEG2XE_L            (0x0040)       /* MPU Main memory Segment 2 Execute enable */
+#define MPUSEG2VS_L            (0x0080)       /* MPU Main memory Segment 2 Violation select */
+
+/* MPUSAM Control Bits */
+#define MPUSEG3RE_H            (0x0001)       /* MPU Main memory Segment 3 Read enable */
+#define MPUSEG3WE_H            (0x0002)       /* MPU Main memory Segment 3 Write enable */
+#define MPUSEG3XE_H            (0x0004)       /* MPU Main memory Segment 3 Execute enable */
+#define MPUSEG3VS_H            (0x0008)       /* MPU Main memory Segment 3 Violation select */
+#define MPUSEGIRE_H            (0x0010)       /* MPU Info memory Segment Read enable */
+#define MPUSEGIWE_H            (0x0020)       /* MPU Info memory Segment Write enable */
+#define MPUSEGIXE_H            (0x0040)       /* MPU Info memory Segment Execute enable */
+#define MPUSEGIVS_H            (0x0080)       /* MPU Info memory Segment Violation select */
+
+/* MPUIPC0 Control Bits */
+#define MPUIPVS                (0x0020)       /* MPU MPU IP protection segment Violation Select */
+#define MPUIPENA               (0x0040)       /* MPU MPU IP Protection Enable */
+#define MPUIPLOCK              (0x0080)       /* MPU IP Protection Lock */
+
+/* MPUIPC0 Control Bits */
+#define MPUIPVS_L              (0x0020)       /* MPU MPU IP protection segment Violation Select */
+#define MPUIPENA_L             (0x0040)       /* MPU MPU IP Protection Enable */
+#define MPUIPLOCK_L            (0x0080)       /* MPU IP Protection Lock */
+
+/* MPUIPSEGB2 Control Bits */
+
+/* MPUIPSEGB2 Control Bits */
+
+/* MPUIPSEGB2 Control Bits */
+
+/* MPUIPSEGB1 Control Bits */
+
+/* MPUIPSEGB1 Control Bits */
+
+/* MPUIPSEGB1 Control Bits */
+
+/************************************************************
+* HARDWARE MULTIPLIER 32Bit
+************************************************************/
+#define __MSP430_HAS_MPY32__                  /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_MPY32__ 0x04C0
+#define MPY32_BASE             __MSP430_BASEADDRESS_MPY32__
+
+sfr_w(MPY);                                   /* Multiply Unsigned/Operand 1 */
+sfr_b(MPY_L);                                 /* Multiply Unsigned/Operand 1 */
+sfr_b(MPY_H);                                 /* Multiply Unsigned/Operand 1 */
+sfr_w(MPYS);                                  /* Multiply Signed/Operand 1 */
+sfr_b(MPYS_L);                                /* Multiply Signed/Operand 1 */
+sfr_b(MPYS_H);                                /* Multiply Signed/Operand 1 */
+sfr_w(MAC);                                   /* Multiply Unsigned and Accumulate/Operand 1 */
+sfr_b(MAC_L);                                 /* Multiply Unsigned and Accumulate/Operand 1 */
+sfr_b(MAC_H);                                 /* Multiply Unsigned and Accumulate/Operand 1 */
+sfr_w(MACS);                                  /* Multiply Signed and Accumulate/Operand 1 */
+sfr_b(MACS_L);                                /* Multiply Signed and Accumulate/Operand 1 */
+sfr_b(MACS_H);                                /* Multiply Signed and Accumulate/Operand 1 */
+sfr_w(OP2);                                   /* Operand 2 */
+sfr_b(OP2_L);                                 /* Operand 2 */
+sfr_b(OP2_H);                                 /* Operand 2 */
+sfr_w(RESLO);                                 /* Result Low Word */
+sfr_b(RESLO_L);                               /* Result Low Word */
+sfr_b(RESLO_H);                               /* Result Low Word */
+sfr_w(RESHI);                                 /* Result High Word */
+sfr_b(RESHI_L);                               /* Result High Word */
+sfr_b(RESHI_H);                               /* Result High Word */
+sfr_w(SUMEXT);                                /* Sum Extend */
+sfr_b(SUMEXT_L);                              /* Sum Extend */
+sfr_b(SUMEXT_H);                              /* Sum Extend */
+
+sfr_w(MPY32L);                                /* 32-bit operand 1 - multiply - low word */
+sfr_b(MPY32L_L);                              /* 32-bit operand 1 - multiply - low word */
+sfr_b(MPY32L_H);                              /* 32-bit operand 1 - multiply - low word */
+sfr_w(MPY32H);                                /* 32-bit operand 1 - multiply - high word */
+sfr_b(MPY32H_L);                              /* 32-bit operand 1 - multiply - high word */
+sfr_b(MPY32H_H);                              /* 32-bit operand 1 - multiply - high word */
+sfr_w(MPYS32L);                               /* 32-bit operand 1 - signed multiply - low word */
+sfr_b(MPYS32L_L);                             /* 32-bit operand 1 - signed multiply - low word */
+sfr_b(MPYS32L_H);                             /* 32-bit operand 1 - signed multiply - low word */
+sfr_w(MPYS32H);                               /* 32-bit operand 1 - signed multiply - high word */
+sfr_b(MPYS32H_L);                             /* 32-bit operand 1 - signed multiply - high word */
+sfr_b(MPYS32H_H);                             /* 32-bit operand 1 - signed multiply - high word */
+sfr_w(MAC32L);                                /* 32-bit operand 1 - multiply accumulate - low word */
+sfr_b(MAC32L_L);                              /* 32-bit operand 1 - multiply accumulate - low word */
+sfr_b(MAC32L_H);                              /* 32-bit operand 1 - multiply accumulate - low word */
+sfr_w(MAC32H);                                /* 32-bit operand 1 - multiply accumulate - high word */
+sfr_b(MAC32H_L);                              /* 32-bit operand 1 - multiply accumulate - high word */
+sfr_b(MAC32H_H);                              /* 32-bit operand 1 - multiply accumulate - high word */
+sfr_w(MACS32L);                               /* 32-bit operand 1 - signed multiply accumulate - low word */
+sfr_b(MACS32L_L);                             /* 32-bit operand 1 - signed multiply accumulate - low word */
+sfr_b(MACS32L_H);                             /* 32-bit operand 1 - signed multiply accumulate - low word */
+sfr_w(MACS32H);                               /* 32-bit operand 1 - signed multiply accumulate - high word */
+sfr_b(MACS32H_L);                             /* 32-bit operand 1 - signed multiply accumulate - high word */
+sfr_b(MACS32H_H);                             /* 32-bit operand 1 - signed multiply accumulate - high word */
+sfr_w(OP2L);                                  /* 32-bit operand 2 - low word */
+sfr_b(OP2L_L);                                /* 32-bit operand 2 - low word */
+sfr_b(OP2L_H);                                /* 32-bit operand 2 - low word */
+sfr_w(OP2H);                                  /* 32-bit operand 2 - high word */
+sfr_b(OP2H_L);                                /* 32-bit operand 2 - high word */
+sfr_b(OP2H_H);                                /* 32-bit operand 2 - high word */
+sfr_w(RES0);                                  /* 32x32-bit result 0 - least significant word */
+sfr_b(RES0_L);                                /* 32x32-bit result 0 - least significant word */
+sfr_b(RES0_H);                                /* 32x32-bit result 0 - least significant word */
+sfr_w(RES1);                                  /* 32x32-bit result 1 */
+sfr_b(RES1_L);                                /* 32x32-bit result 1 */
+sfr_b(RES1_H);                                /* 32x32-bit result 1 */
+sfr_w(RES2);                                  /* 32x32-bit result 2 */
+sfr_b(RES2_L);                                /* 32x32-bit result 2 */
+sfr_b(RES2_H);                                /* 32x32-bit result 2 */
+sfr_w(RES3);                                  /* 32x32-bit result 3 - most significant word */
+sfr_b(RES3_L);                                /* 32x32-bit result 3 - most significant word */
+sfr_b(RES3_H);                                /* 32x32-bit result 3 - most significant word */
+sfr_w(MPY32CTL0);                             /* MPY32 Control Register 0 */
+sfr_b(MPY32CTL0_L);                           /* MPY32 Control Register 0 */
+sfr_b(MPY32CTL0_H);                           /* MPY32 Control Register 0 */
+
+#define MPY_B                  MPY_L          /* Multiply Unsigned/Operand 1 (Byte Access) */
+#define MPYS_B                 MPYS_L         /* Multiply Signed/Operand 1 (Byte Access) */
+#define MAC_B                  MAC_L          /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */
+#define MACS_B                 MACS_L         /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */
+#define OP2_B                  OP2_L          /* Operand 2 (Byte Access) */
+#define MPY32L_B               MPY32L_L       /* 32-bit operand 1 - multiply - low word (Byte Access) */
+#define MPY32H_B               MPY32H_L       /* 32-bit operand 1 - multiply - high word (Byte Access) */
+#define MPYS32L_B              MPYS32L_L      /* 32-bit operand 1 - signed multiply - low word (Byte Access) */
+#define MPYS32H_B              MPYS32H_L      /* 32-bit operand 1 - signed multiply - high word (Byte Access) */
+#define MAC32L_B               MAC32L_L       /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */
+#define MAC32H_B               MAC32H_L       /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */
+#define MACS32L_B              MACS32L_L      /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */
+#define MACS32H_B              MACS32H_L      /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */
+#define OP2L_B                 OP2L_L         /* 32-bit operand 2 - low word (Byte Access) */
+#define OP2H_B                 OP2H_L         /* 32-bit operand 2 - high word (Byte Access) */
+
+/* MPY32CTL0 Control Bits */
+#define MPYC                   (0x0001)       /* Carry of the multiplier */
+//#define RESERVED            (0x0002)  /* Reserved */
+#define MPYFRAC                (0x0004)       /* Fractional mode */
+#define MPYSAT                 (0x0008)       /* Saturation mode */
+#define MPYM0                  (0x0010)       /* Multiplier mode Bit:0 */
+#define MPYM1                  (0x0020)       /* Multiplier mode Bit:1 */
+#define OP1_32                 (0x0040)       /* Bit-width of operand 1 0:16Bit / 1:32Bit */
+#define OP2_32                 (0x0080)       /* Bit-width of operand 2 0:16Bit / 1:32Bit */
+#define MPYDLYWRTEN            (0x0100)       /* Delayed write enable */
+#define MPYDLY32               (0x0200)       /* Delayed write mode */
+
+/* MPY32CTL0 Control Bits */
+#define MPYC_L                 (0x0001)       /* Carry of the multiplier */
+//#define RESERVED            (0x0002)  /* Reserved */
+#define MPYFRAC_L              (0x0004)       /* Fractional mode */
+#define MPYSAT_L               (0x0008)       /* Saturation mode */
+#define MPYM0_L                (0x0010)       /* Multiplier mode Bit:0 */
+#define MPYM1_L                (0x0020)       /* Multiplier mode Bit:1 */
+#define OP1_32_L               (0x0040)       /* Bit-width of operand 1 0:16Bit / 1:32Bit */
+#define OP2_32_L               (0x0080)       /* Bit-width of operand 2 0:16Bit / 1:32Bit */
+
+/* MPY32CTL0 Control Bits */
+//#define RESERVED            (0x0002)  /* Reserved */
+#define MPYDLYWRTEN_H          (0x0001)       /* Delayed write enable */
+#define MPYDLY32_H             (0x0002)       /* Delayed write mode */
+
+#define MPYM_0                 (0x0000)       /* Multiplier mode: MPY */
+#define MPYM_1                 (0x0010)       /* Multiplier mode: MPYS */
+#define MPYM_2                 (0x0020)       /* Multiplier mode: MAC */
+#define MPYM_3                 (0x0030)       /* Multiplier mode: MACS */
+#define MPYM__MPY              (0x0000)       /* Multiplier mode: MPY */
+#define MPYM__MPYS             (0x0010)       /* Multiplier mode: MPYS */
+#define MPYM__MAC              (0x0020)       /* Multiplier mode: MAC */
+#define MPYM__MACS             (0x0030)       /* Multiplier mode: MACS */
+
+/************************************************************
+* PMM - Power Management System for FRAM
+************************************************************/
+#define __MSP430_HAS_PMM_FRAM__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PMM_FRAM__ 0x0120
+#define PMM_BASE               __MSP430_BASEADDRESS_PMM_FRAM__
+
+sfr_w(PMMCTL0);                               /* PMM Control 0 */
+sfr_b(PMMCTL0_L);                             /* PMM Control 0 */
+sfr_b(PMMCTL0_H);                             /* PMM Control 0 */
+sfr_w(PMMIFG);                                /* PMM Interrupt Flag */
+sfr_b(PMMIFG_L);                              /* PMM Interrupt Flag */
+sfr_b(PMMIFG_H);                              /* PMM Interrupt Flag */
+sfr_w(PM5CTL0);                               /* PMM Power Mode 5 Control Register 0 */
+sfr_b(PM5CTL0_L);                             /* PMM Power Mode 5 Control Register 0 */
+sfr_b(PM5CTL0_H);                             /* PMM Power Mode 5 Control Register 0 */
+
+#define PMMPW                  (0xA500)       /* PMM Register Write Password */
+#define PMMPW_H                (0xA5)         /* PMM Register Write Password for high word access */
+
+/* PMMCTL0 Control Bits */
+#define PMMSWBOR               (0x0004)       /* PMM Software BOR */
+#define PMMSWPOR               (0x0008)       /* PMM Software POR */
+#define PMMREGOFF              (0x0010)       /* PMM Turn Regulator off */
+#define SVSHE                  (0x0040)       /* SVS high side enable */
+#define PMMLPRST               (0x0080)       /* PMM Low-Power Reset Enable */
+
+/* PMMCTL0 Control Bits */
+#define PMMSWBOR_L             (0x0004)       /* PMM Software BOR */
+#define PMMSWPOR_L             (0x0008)       /* PMM Software POR */
+#define PMMREGOFF_L            (0x0010)       /* PMM Turn Regulator off */
+#define SVSHE_L                (0x0040)       /* SVS high side enable */
+#define PMMLPRST_L             (0x0080)       /* PMM Low-Power Reset Enable */
+
+/* PMMIFG Control Bits */
+#define PMMBORIFG              (0x0100)       /* PMM Software BOR interrupt flag */
+#define PMMRSTIFG              (0x0200)       /* PMM RESET pin interrupt flag */
+#define PMMPORIFG              (0x0400)       /* PMM Software POR interrupt flag */
+#define SVSHIFG                (0x2000)       /* SVS low side interrupt flag */
+#define PMMLPM5IFG             (0x8000)       /* LPM5 indication Flag */
+
+/* PMMIFG Control Bits */
+#define PMMBORIFG_H            (0x0001)       /* PMM Software BOR interrupt flag */
+#define PMMRSTIFG_H            (0x0002)       /* PMM RESET pin interrupt flag */
+#define PMMPORIFG_H            (0x0004)       /* PMM Software POR interrupt flag */
+#define SVSHIFG_H              (0x0020)       /* SVS low side interrupt flag */
+#define PMMLPM5IFG_H           (0x0080)       /* LPM5 indication Flag */
+
+/* PM5CTL0 Power Mode 5 Control Bits */
+#define LOCKLPM5               (0x0001)       /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
+
+/* PM5CTL0 Power Mode 5 Control Bits */
+#define LOCKLPM5_L             (0x0001)       /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
+
+
+/************************************************************
+* DIGITAL I/O Port1/2 Pull up / Pull down Resistors
+************************************************************/
+#define __MSP430_HAS_PORT1_R__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORT1_R__ 0x0200
+#define P1_BASE                __MSP430_BASEADDRESS_PORT1_R__
+#define __MSP430_HAS_PORT2_R__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORT2_R__ 0x0200
+#define P2_BASE                __MSP430_BASEADDRESS_PORT2_R__
+#define __MSP430_HAS_PORTA_R__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORTA_R__ 0x0200
+#define PA_BASE                __MSP430_BASEADDRESS_PORTA_R__
+#define __MSP430_HAS_P1SEL0__                 /* Define for DriverLib */
+#define __MSP430_HAS_P2SEL0__                 /* Define for DriverLib */
+#define __MSP430_HAS_PASEL0__                 /* Define for DriverLib */
+#define __MSP430_HAS_P1SEL1__                 /* Define for DriverLib */
+#define __MSP430_HAS_P2SEL1__                 /* Define for DriverLib */
+#define __MSP430_HAS_PASEL1__                 /* Define for DriverLib */
+
+sfr_w(PAIN);                                  /* Port A Input */
+sfr_b(PAIN_L);                                /* Port A Input */
+sfr_b(PAIN_H);                                /* Port A Input */
+sfr_w(PAOUT);                                 /* Port A Output */
+sfr_b(PAOUT_L);                               /* Port A Output */
+sfr_b(PAOUT_H);                               /* Port A Output */
+sfr_w(PADIR);                                 /* Port A Direction */
+sfr_b(PADIR_L);                               /* Port A Direction */
+sfr_b(PADIR_H);                               /* Port A Direction */
+sfr_w(PAREN);                                 /* Port A Resistor Enable */
+sfr_b(PAREN_L);                               /* Port A Resistor Enable */
+sfr_b(PAREN_H);                               /* Port A Resistor Enable */
+sfr_w(PASEL0);                                /* Port A Selection 0 */
+sfr_b(PASEL0_L);                              /* Port A Selection 0 */
+sfr_b(PASEL0_H);                              /* Port A Selection 0 */
+sfr_w(PASEL1);                                /* Port A Selection 1 */
+sfr_b(PASEL1_L);                              /* Port A Selection 1 */
+sfr_b(PASEL1_H);                              /* Port A Selection 1 */
+sfr_w(PASELC);                                /* Port A Complement Selection */
+sfr_b(PASELC_L);                              /* Port A Complement Selection */
+sfr_b(PASELC_H);                              /* Port A Complement Selection */
+sfr_w(PAIES);                                 /* Port A Interrupt Edge Select */
+sfr_b(PAIES_L);                               /* Port A Interrupt Edge Select */
+sfr_b(PAIES_H);                               /* Port A Interrupt Edge Select */
+sfr_w(PAIE);                                  /* Port A Interrupt Enable */
+sfr_b(PAIE_L);                                /* Port A Interrupt Enable */
+sfr_b(PAIE_H);                                /* Port A Interrupt Enable */
+sfr_w(PAIFG);                                 /* Port A Interrupt Flag */
+sfr_b(PAIFG_L);                               /* Port A Interrupt Flag */
+sfr_b(PAIFG_H);                               /* Port A Interrupt Flag */
+
+
+sfr_w(P1IV);                                  /* Port 1 Interrupt Vector Word */
+sfr_w(P2IV);                                  /* Port 2 Interrupt Vector Word */
+#define P1IN                   (PAIN_L)       /* Port 1 Input */
+#define P1OUT                  (PAOUT_L)      /* Port 1 Output */
+#define P1DIR                  (PADIR_L)      /* Port 1 Direction */
+#define P1REN                  (PAREN_L)      /* Port 1 Resistor Enable */
+#define P1SEL0                 (PASEL0_L)     /* Port 1 Selection 0 */
+#define P1SEL1                 (PASEL1_L)     /* Port 1 Selection 1 */
+#define P1SELC                 (PASELC_L)     /* Port 1 Complement Selection */
+#define P1IES                  (PAIES_L)      /* Port 1 Interrupt Edge Select */
+#define P1IE                   (PAIE_L)       /* Port 1 Interrupt Enable */
+#define P1IFG                  (PAIFG_L)      /* Port 1 Interrupt Flag */
+
+//Definitions for P1IV
+#define P1IV_NONE              (0x0000)       /* No Interrupt pending */
+#define P1IV_P1IFG0            (0x0002)       /* P1IV P1IFG.0 */
+#define P1IV_P1IFG1            (0x0004)       /* P1IV P1IFG.1 */
+#define P1IV_P1IFG2            (0x0006)       /* P1IV P1IFG.2 */
+#define P1IV_P1IFG3            (0x0008)       /* P1IV P1IFG.3 */
+#define P1IV_P1IFG4            (0x000A)       /* P1IV P1IFG.4 */
+#define P1IV_P1IFG5            (0x000C)       /* P1IV P1IFG.5 */
+#define P1IV_P1IFG6            (0x000E)       /* P1IV P1IFG.6 */
+#define P1IV_P1IFG7            (0x0010)       /* P1IV P1IFG.7 */
+
+#define P2IN                   (PAIN_H)       /* Port 2 Input */
+#define P2OUT                  (PAOUT_H)      /* Port 2 Output */
+#define P2DIR                  (PADIR_H)      /* Port 2 Direction */
+#define P2REN                  (PAREN_H)      /* Port 2 Resistor Enable */
+#define P2SEL0                 (PASEL0_H)     /* Port 2 Selection 0 */
+#define P2SEL1                 (PASEL1_H)     /* Port 2 Selection 1 */
+#define P2SELC                 (PASELC_H)     /* Port 2 Complement Selection */
+#define P2IES                  (PAIES_H)      /* Port 2 Interrupt Edge Select */
+#define P2IE                   (PAIE_H)       /* Port 2 Interrupt Enable */
+#define P2IFG                  (PAIFG_H)      /* Port 2 Interrupt Flag */
+
+//Definitions for P2IV
+#define P2IV_NONE              (0x0000)       /* No Interrupt pending */
+#define P2IV_P2IFG0            (0x0002)       /* P2IV P2IFG.0 */
+#define P2IV_P2IFG1            (0x0004)       /* P2IV P2IFG.1 */
+#define P2IV_P2IFG2            (0x0006)       /* P2IV P2IFG.2 */
+#define P2IV_P2IFG3            (0x0008)       /* P2IV P2IFG.3 */
+#define P2IV_P2IFG4            (0x000A)       /* P2IV P2IFG.4 */
+#define P2IV_P2IFG5            (0x000C)       /* P2IV P2IFG.5 */
+#define P2IV_P2IFG6            (0x000E)       /* P2IV P2IFG.6 */
+#define P2IV_P2IFG7            (0x0010)       /* P2IV P2IFG.7 */
+
+
+/************************************************************
+* DIGITAL I/O Port3/4 Pull up / Pull down Resistors
+************************************************************/
+#define __MSP430_HAS_PORT3_R__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORT3_R__ 0x0220
+#define P3_BASE                __MSP430_BASEADDRESS_PORT3_R__
+#define __MSP430_HAS_PORT4_R__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORT4_R__ 0x0220
+#define P4_BASE                __MSP430_BASEADDRESS_PORT4_R__
+#define __MSP430_HAS_PORTB_R__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORTB_R__ 0x0220
+#define PB_BASE                __MSP430_BASEADDRESS_PORTB_R__
+#define __MSP430_HAS_P3SEL0__                 /* Define for DriverLib */
+#define __MSP430_HAS_P4SEL0__                 /* Define for DriverLib */
+#define __MSP430_HAS_PBSEL0__                 /* Define for DriverLib */
+#define __MSP430_HAS_P3SEL1__                 /* Define for DriverLib */
+#define __MSP430_HAS_P4SEL1__                 /* Define for DriverLib */
+#define __MSP430_HAS_PBSEL1__                 /* Define for DriverLib */
+
+sfr_w(PBIN);                                  /* Port B Input */
+sfr_b(PBIN_L);                                /* Port B Input */
+sfr_b(PBIN_H);                                /* Port B Input */
+sfr_w(PBOUT);                                 /* Port B Output */
+sfr_b(PBOUT_L);                               /* Port B Output */
+sfr_b(PBOUT_H);                               /* Port B Output */
+sfr_w(PBDIR);                                 /* Port B Direction */
+sfr_b(PBDIR_L);                               /* Port B Direction */
+sfr_b(PBDIR_H);                               /* Port B Direction */
+sfr_w(PBREN);                                 /* Port B Resistor Enable */
+sfr_b(PBREN_L);                               /* Port B Resistor Enable */
+sfr_b(PBREN_H);                               /* Port B Resistor Enable */
+sfr_w(PBSEL0);                                /* Port B Selection 0 */
+sfr_b(PBSEL0_L);                              /* Port B Selection 0 */
+sfr_b(PBSEL0_H);                              /* Port B Selection 0 */
+sfr_w(PBSEL1);                                /* Port B Selection 1 */
+sfr_b(PBSEL1_L);                              /* Port B Selection 1 */
+sfr_b(PBSEL1_H);                              /* Port B Selection 1 */
+sfr_w(PBSELC);                                /* Port B Complement Selection */
+sfr_b(PBSELC_L);                              /* Port B Complement Selection */
+sfr_b(PBSELC_H);                              /* Port B Complement Selection */
+sfr_w(PBIES);                                 /* Port B Interrupt Edge Select */
+sfr_b(PBIES_L);                               /* Port B Interrupt Edge Select */
+sfr_b(PBIES_H);                               /* Port B Interrupt Edge Select */
+sfr_w(PBIE);                                  /* Port B Interrupt Enable */
+sfr_b(PBIE_L);                                /* Port B Interrupt Enable */
+sfr_b(PBIE_H);                                /* Port B Interrupt Enable */
+sfr_w(PBIFG);                                 /* Port B Interrupt Flag */
+sfr_b(PBIFG_L);                               /* Port B Interrupt Flag */
+sfr_b(PBIFG_H);                               /* Port B Interrupt Flag */
+
+
+sfr_w(P3IV);                                  /* Port 3 Interrupt Vector Word */
+sfr_w(P4IV);                                  /* Port 4 Interrupt Vector Word */
+#define P3IN                   (PBIN_L)       /* Port 3 Input */
+#define P3OUT                  (PBOUT_L)      /* Port 3 Output */
+#define P3DIR                  (PBDIR_L)      /* Port 3 Direction */
+#define P3REN                  (PBREN_L)      /* Port 3 Resistor Enable */
+#define P3SEL0                 (PBSEL0_L)     /* Port 3 Selection 0 */
+#define P3SEL1                 (PBSEL1_L)     /* Port 3 Selection 1 */
+#define P3SELC                 (PBSELC_L)     /* Port 3 Complement Selection */
+#define P3IES                  (PBIES_L)      /* Port 3 Interrupt Edge Select */
+#define P3IE                   (PBIE_L)       /* Port 3 Interrupt Enable */
+#define P3IFG                  (PBIFG_L)      /* Port 3 Interrupt Flag */
+
+//Definitions for P3IV
+#define P3IV_NONE              (0x0000)       /* No Interrupt pending */
+#define P3IV_P3IFG0            (0x0002)       /* P3IV P3IFG.0 */
+#define P3IV_P3IFG1            (0x0004)       /* P3IV P3IFG.1 */
+#define P3IV_P3IFG2            (0x0006)       /* P3IV P3IFG.2 */
+#define P3IV_P3IFG3            (0x0008)       /* P3IV P3IFG.3 */
+#define P3IV_P3IFG4            (0x000A)       /* P3IV P3IFG.4 */
+#define P3IV_P3IFG5            (0x000C)       /* P3IV P3IFG.5 */
+#define P3IV_P3IFG6            (0x000E)       /* P3IV P3IFG.6 */
+#define P3IV_P3IFG7            (0x0010)       /* P3IV P3IFG.7 */
+
+#define P4IN                   (PBIN_H)       /* Port 4 Input */
+#define P4OUT                  (PBOUT_H)      /* Port 4 Output */
+#define P4DIR                  (PBDIR_H)      /* Port 4 Direction */
+#define P4REN                  (PBREN_H)      /* Port 4 Resistor Enable */
+#define P4SEL0                 (PBSEL0_H)     /* Port 4 Selection 0 */
+#define P4SEL1                 (PBSEL1_H)     /* Port 4 Selection 1 */
+#define P4SELC                 (PBSELC_H)     /* Port 4 Complement Selection */
+#define P4IES                  (PBIES_H)      /* Port 4 Interrupt Edge Select */
+#define P4IE                   (PBIE_H)       /* Port 4 Interrupt Enable */
+#define P4IFG                  (PBIFG_H)      /* Port 4 Interrupt Flag */
+
+//Definitions for P4IV
+#define P4IV_NONE              (0x0000)       /* No Interrupt pending */
+#define P4IV_P4IFG0            (0x0002)       /* P4IV P4IFG.0 */
+#define P4IV_P4IFG1            (0x0004)       /* P4IV P4IFG.1 */
+#define P4IV_P4IFG2            (0x0006)       /* P4IV P4IFG.2 */
+#define P4IV_P4IFG3            (0x0008)       /* P4IV P4IFG.3 */
+#define P4IV_P4IFG4            (0x000A)       /* P4IV P4IFG.4 */
+#define P4IV_P4IFG5            (0x000C)       /* P4IV P4IFG.5 */
+#define P4IV_P4IFG6            (0x000E)       /* P4IV P4IFG.6 */
+#define P4IV_P4IFG7            (0x0010)       /* P4IV P4IFG.7 */
+
+
+/************************************************************
+* DIGITAL I/O PortJ Pull up / Pull down Resistors
+************************************************************/
+#define __MSP430_HAS_PORTJ_R__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORTJ_R__ 0x0320
+#define PJ_BASE                __MSP430_BASEADDRESS_PORTJ_R__
+#define __MSP430_HAS_PJSEL0__                 /* Define for DriverLib */
+#define __MSP430_HAS_PJSEL1__                 /* Define for DriverLib */
+
+sfr_w(PJIN);                                  /* Port J Input */
+sfr_b(PJIN_L);                                /* Port J Input */
+sfr_b(PJIN_H);                                /* Port J Input */
+sfr_w(PJOUT);                                 /* Port J Output */
+sfr_b(PJOUT_L);                               /* Port J Output */
+sfr_b(PJOUT_H);                               /* Port J Output */
+sfr_w(PJDIR);                                 /* Port J Direction */
+sfr_b(PJDIR_L);                               /* Port J Direction */
+sfr_b(PJDIR_H);                               /* Port J Direction */
+sfr_w(PJREN);                                 /* Port J Resistor Enable */
+sfr_b(PJREN_L);                               /* Port J Resistor Enable */
+sfr_b(PJREN_H);                               /* Port J Resistor Enable */
+sfr_w(PJSEL0);                                /* Port J Selection 0 */
+sfr_b(PJSEL0_L);                              /* Port J Selection 0 */
+sfr_b(PJSEL0_H);                              /* Port J Selection 0 */
+sfr_w(PJSEL1);                                /* Port J Selection 1 */
+sfr_b(PJSEL1_L);                              /* Port J Selection 1 */
+sfr_b(PJSEL1_H);                              /* Port J Selection 1 */
+sfr_w(PJSELC);                                /* Port J Complement Selection */
+sfr_b(PJSELC_L);                              /* Port J Complement Selection */
+sfr_b(PJSELC_H);                              /* Port J Complement Selection */
+
+/************************************************************
+* Shared Reference
+************************************************************/
+#define __MSP430_HAS_REF_A__                  /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_REF_A__ 0x01B0
+#define REF_A_BASE             __MSP430_BASEADDRESS_REF_A__
+
+sfr_w(REFCTL0);                               /* REF Shared Reference control register 0 */
+sfr_b(REFCTL0_L);                             /* REF Shared Reference control register 0 */
+sfr_b(REFCTL0_H);                             /* REF Shared Reference control register 0 */
+
+/* REFCTL0 Control Bits */
+#define REFON                  (0x0001)       /* REF Reference On */
+#define REFOUT                 (0x0002)       /* REF Reference output Buffer On */
+//#define RESERVED            (0x0004)  /* Reserved */
+#define REFTCOFF               (0x0008)       /* REF Temp.Sensor off */
+#define REFVSEL0               (0x0010)       /* REF Reference Voltage Level Select Bit:0 */
+#define REFVSEL1               (0x0020)       /* REF Reference Voltage Level Select Bit:1 */
+#define REFGENOT               (0x0040)       /* REF Reference generator one-time trigger */
+#define REFBGOT                (0x0080)       /* REF Bandgap and bandgap buffer one-time trigger */
+#define REFGENACT              (0x0100)       /* REF Reference generator active */
+#define REFBGACT               (0x0200)       /* REF Reference bandgap active */
+#define REFGENBUSY             (0x0400)       /* REF Reference generator busy */
+#define BGMODE                 (0x0800)       /* REF Bandgap mode */
+#define REFGENRDY              (0x1000)       /* REF Reference generator ready */
+#define REFBGRDY               (0x2000)       /* REF Reference bandgap ready */
+//#define RESERVED            (0x4000)  /* Reserved */
+//#define RESERVED            (0x8000)  /* Reserved */
+
+/* REFCTL0 Control Bits */
+#define REFON_L                (0x0001)       /* REF Reference On */
+#define REFOUT_L               (0x0002)       /* REF Reference output Buffer On */
+//#define RESERVED            (0x0004)  /* Reserved */
+#define REFTCOFF_L             (0x0008)       /* REF Temp.Sensor off */
+#define REFVSEL0_L             (0x0010)       /* REF Reference Voltage Level Select Bit:0 */
+#define REFVSEL1_L             (0x0020)       /* REF Reference Voltage Level Select Bit:1 */
+#define REFGENOT_L             (0x0040)       /* REF Reference generator one-time trigger */
+#define REFBGOT_L              (0x0080)       /* REF Bandgap and bandgap buffer one-time trigger */
+//#define RESERVED            (0x4000)  /* Reserved */
+//#define RESERVED            (0x8000)  /* Reserved */
+
+/* REFCTL0 Control Bits */
+//#define RESERVED            (0x0004)  /* Reserved */
+#define REFGENACT_H            (0x0001)       /* REF Reference generator active */
+#define REFBGACT_H             (0x0002)       /* REF Reference bandgap active */
+#define REFGENBUSY_H           (0x0004)       /* REF Reference generator busy */
+#define BGMODE_H               (0x0008)       /* REF Bandgap mode */
+#define REFGENRDY_H            (0x0010)       /* REF Reference generator ready */
+#define REFBGRDY_H             (0x0020)       /* REF Reference bandgap ready */
+//#define RESERVED            (0x4000)  /* Reserved */
+//#define RESERVED            (0x8000)  /* Reserved */
+
+#define REFVSEL_0              (0x0000)       /* REF Reference Voltage Level Select 1.2V */
+#define REFVSEL_1              (0x0010)       /* REF Reference Voltage Level Select 2.0V */
+#define REFVSEL_2              (0x0020)       /* REF Reference Voltage Level Select 2.5V */
+#define REFVSEL_3              (0x0030)       /* REF Reference Voltage Level Select 2.5V */
+
+/************************************************************
+* Real Time Clock
+************************************************************/
+#define __MSP430_HAS_RTC_B__                  /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_RTC_B__ 0x04A0
+#define RTC_B_BASE             __MSP430_BASEADDRESS_RTC_B__
+
+sfr_w(RTCCTL01);                              /* Real Timer Control 0/1 */
+sfr_b(RTCCTL01_L);                            /* Real Timer Control 0/1 */
+sfr_b(RTCCTL01_H);                            /* Real Timer Control 0/1 */
+sfr_w(RTCCTL23);                              /* Real Timer Control 2/3 */
+sfr_b(RTCCTL23_L);                            /* Real Timer Control 2/3 */
+sfr_b(RTCCTL23_H);                            /* Real Timer Control 2/3 */
+sfr_w(RTCPS0CTL);                             /* Real Timer Prescale Timer 0 Control */
+sfr_b(RTCPS0CTL_L);                           /* Real Timer Prescale Timer 0 Control */
+sfr_b(RTCPS0CTL_H);                           /* Real Timer Prescale Timer 0 Control */
+sfr_w(RTCPS1CTL);                             /* Real Timer Prescale Timer 1 Control */
+sfr_b(RTCPS1CTL_L);                           /* Real Timer Prescale Timer 1 Control */
+sfr_b(RTCPS1CTL_H);                           /* Real Timer Prescale Timer 1 Control */
+sfr_w(RTCPS);                                 /* Real Timer Prescale Timer Control */
+sfr_b(RTCPS_L);                               /* Real Timer Prescale Timer Control */
+sfr_b(RTCPS_H);                               /* Real Timer Prescale Timer Control */
+sfr_w(RTCIV);                                 /* Real Time Clock Interrupt Vector */
+sfr_w(RTCTIM0);                               /* Real Time Clock Time 0 */
+sfr_b(RTCTIM0_L);                             /* Real Time Clock Time 0 */
+sfr_b(RTCTIM0_H);                             /* Real Time Clock Time 0 */
+sfr_w(RTCTIM1);                               /* Real Time Clock Time 1 */
+sfr_b(RTCTIM1_L);                             /* Real Time Clock Time 1 */
+sfr_b(RTCTIM1_H);                             /* Real Time Clock Time 1 */
+sfr_w(RTCDATE);                               /* Real Time Clock Date */
+sfr_b(RTCDATE_L);                             /* Real Time Clock Date */
+sfr_b(RTCDATE_H);                             /* Real Time Clock Date */
+sfr_w(RTCYEAR);                               /* Real Time Clock Year */
+sfr_b(RTCYEAR_L);                             /* Real Time Clock Year */
+sfr_b(RTCYEAR_H);                             /* Real Time Clock Year */
+sfr_w(RTCAMINHR);                             /* Real Time Clock Alarm Min/Hour */
+sfr_b(RTCAMINHR_L);                           /* Real Time Clock Alarm Min/Hour */
+sfr_b(RTCAMINHR_H);                           /* Real Time Clock Alarm Min/Hour */
+sfr_w(RTCADOWDAY);                            /* Real Time Clock Alarm day of week/day */
+sfr_b(RTCADOWDAY_L);                          /* Real Time Clock Alarm day of week/day */
+sfr_b(RTCADOWDAY_H);                          /* Real Time Clock Alarm day of week/day */
+sfr_w(BIN2BCD);                               /* Real Time Binary-to-BCD conversion register */
+sfr_w(BCD2BIN);                               /* Real Time BCD-to-binary conversion register */
+
+#define RTCCTL0                RTCCTL01_L     /* Real Time Clock Control 0 */
+#define RTCCTL1                RTCCTL01_H     /* Real Time Clock Control 1 */
+#define RTCCTL2                RTCCTL23_L     /* Real Time Clock Control 2 */
+#define RTCCTL3                RTCCTL23_H     /* Real Time Clock Control 3 */
+#define RTCNT12                RTCTIM0
+#define RTCNT34                RTCTIM1
+#define RTCNT1                 RTCTIM0_L
+#define RTCNT2                 RTCTIM0_H
+#define RTCNT3                 RTCTIM1_L
+#define RTCNT4                 RTCTIM1_H
+#define RTCSEC                 RTCTIM0_L
+#define RTCMIN                 RTCTIM0_H
+#define RTCHOUR                RTCTIM1_L
+#define RTCDOW                 RTCTIM1_H
+#define RTCDAY                 RTCDATE_L
+#define RTCMON                 RTCDATE_H
+#define RTCYEARL               RTCYEAR_L
+#define RTCYEARH               RTCYEAR_H
+#define RT0PS                  RTCPS_L
+#define RT1PS                  RTCPS_H
+#define RTCAMIN                RTCAMINHR_L    /* Real Time Clock Alarm Min */
+#define RTCAHOUR               RTCAMINHR_H    /* Real Time Clock Alarm Hour */
+#define RTCADOW                RTCADOWDAY_L   /* Real Time Clock Alarm day of week */
+#define RTCADAY                RTCADOWDAY_H   /* Real Time Clock Alarm day */
+
+/* RTCCTL01 Control Bits */
+#define RTCBCD                 (0x8000)       /* RTC BCD  0:Binary / 1:BCD */
+#define RTCHOLD                (0x4000)       /* RTC Hold */
+//#define RESERVED            (0x2000)     /* RESERVED */
+#define RTCRDY                 (0x1000)       /* RTC Ready */
+//#define RESERVED            (0x0800)     /* RESERVED */
+//#define RESERVED            (0x0400)     /* RESERVED */
+#define RTCTEV1                (0x0200)       /* RTC Time Event 1 */
+#define RTCTEV0                (0x0100)       /* RTC Time Event 0 */
+#define RTCOFIE                (0x0080)       /* RTC 32kHz cyrstal oscillator fault interrupt enable */
+#define RTCTEVIE               (0x0040)       /* RTC Time Event Interrupt Enable Flag */
+#define RTCAIE                 (0x0020)       /* RTC Alarm Interrupt Enable Flag */
+#define RTCRDYIE               (0x0010)       /* RTC Ready Interrupt Enable Flag */
+#define RTCOFIFG               (0x0008)       /* RTC 32kHz cyrstal oscillator fault interrupt flag */
+#define RTCTEVIFG              (0x0004)       /* RTC Time Event Interrupt Flag */
+#define RTCAIFG                (0x0002)       /* RTC Alarm Interrupt Flag */
+#define RTCRDYIFG              (0x0001)       /* RTC Ready Interrupt Flag */
+
+/* RTCCTL01 Control Bits */
+//#define RESERVED            (0x2000)     /* RESERVED */
+//#define RESERVED            (0x0800)     /* RESERVED */
+//#define RESERVED            (0x0400)     /* RESERVED */
+#define RTCOFIE_L              (0x0080)       /* RTC 32kHz cyrstal oscillator fault interrupt enable */
+#define RTCTEVIE_L             (0x0040)       /* RTC Time Event Interrupt Enable Flag */
+#define RTCAIE_L               (0x0020)       /* RTC Alarm Interrupt Enable Flag */
+#define RTCRDYIE_L             (0x0010)       /* RTC Ready Interrupt Enable Flag */
+#define RTCOFIFG_L             (0x0008)       /* RTC 32kHz cyrstal oscillator fault interrupt flag */
+#define RTCTEVIFG_L            (0x0004)       /* RTC Time Event Interrupt Flag */
+#define RTCAIFG_L              (0x0002)       /* RTC Alarm Interrupt Flag */
+#define RTCRDYIFG_L            (0x0001)       /* RTC Ready Interrupt Flag */
+
+/* RTCCTL01 Control Bits */
+#define RTCBCD_H               (0x0080)       /* RTC BCD  0:Binary / 1:BCD */
+#define RTCHOLD_H              (0x0040)       /* RTC Hold */
+//#define RESERVED            (0x2000)     /* RESERVED */
+#define RTCRDY_H               (0x0010)       /* RTC Ready */
+//#define RESERVED            (0x0800)     /* RESERVED */
+//#define RESERVED            (0x0400)     /* RESERVED */
+#define RTCTEV1_H              (0x0002)       /* RTC Time Event 1 */
+#define RTCTEV0_H              (0x0001)       /* RTC Time Event 0 */
+
+#define RTCTEV_0               (0x0000)       /* RTC Time Event: 0 (Min. changed) */
+#define RTCTEV_1               (0x0100)       /* RTC Time Event: 1 (Hour changed) */
+#define RTCTEV_2               (0x0200)       /* RTC Time Event: 2 (12:00 changed) */
+#define RTCTEV_3               (0x0300)       /* RTC Time Event: 3 (00:00 changed) */
+#define RTCTEV__MIN            (0x0000)       /* RTC Time Event: 0 (Min. changed) */
+#define RTCTEV__HOUR           (0x0100)       /* RTC Time Event: 1 (Hour changed) */
+#define RTCTEV__0000           (0x0200)       /* RTC Time Event: 2 (00:00 changed) */
+#define RTCTEV__1200           (0x0300)       /* RTC Time Event: 3 (12:00 changed) */
+
+/* RTCCTL23 Control Bits */
+#define RTCCALF1               (0x0200)       /* RTC Calibration Frequency Bit 1 */
+#define RTCCALF0               (0x0100)       /* RTC Calibration Frequency Bit 0 */
+#define RTCCALS                (0x0080)       /* RTC Calibration Sign */
+//#define Reserved          (0x0040)
+#define RTCCAL5                (0x0020)       /* RTC Calibration Bit 5 */
+#define RTCCAL4                (0x0010)       /* RTC Calibration Bit 4 */
+#define RTCCAL3                (0x0008)       /* RTC Calibration Bit 3 */
+#define RTCCAL2                (0x0004)       /* RTC Calibration Bit 2 */
+#define RTCCAL1                (0x0002)       /* RTC Calibration Bit 1 */
+#define RTCCAL0                (0x0001)       /* RTC Calibration Bit 0 */
+
+/* RTCCTL23 Control Bits */
+#define RTCCALS_L              (0x0080)       /* RTC Calibration Sign */
+//#define Reserved          (0x0040)
+#define RTCCAL5_L              (0x0020)       /* RTC Calibration Bit 5 */
+#define RTCCAL4_L              (0x0010)       /* RTC Calibration Bit 4 */
+#define RTCCAL3_L              (0x0008)       /* RTC Calibration Bit 3 */
+#define RTCCAL2_L              (0x0004)       /* RTC Calibration Bit 2 */
+#define RTCCAL1_L              (0x0002)       /* RTC Calibration Bit 1 */
+#define RTCCAL0_L              (0x0001)       /* RTC Calibration Bit 0 */
+
+/* RTCCTL23 Control Bits */
+#define RTCCALF1_H             (0x0002)       /* RTC Calibration Frequency Bit 1 */
+#define RTCCALF0_H             (0x0001)       /* RTC Calibration Frequency Bit 0 */
+//#define Reserved          (0x0040)
+
+#define RTCCALF_0              (0x0000)       /* RTC Calibration Frequency: No Output */
+#define RTCCALF_1              (0x0100)       /* RTC Calibration Frequency: 512 Hz */
+#define RTCCALF_2              (0x0200)       /* RTC Calibration Frequency: 256 Hz */
+#define RTCCALF_3              (0x0300)       /* RTC Calibration Frequency: 1 Hz */
+
+#define RTCAE                  (0x80)         /* Real Time Clock Alarm enable */
+
+/* RTCPS0CTL Control Bits */
+//#define Reserved          (0x0080)
+//#define Reserved          (0x0040)
+//#define Reserved          (0x0020)
+#define RT0IP2                 (0x0010)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
+#define RT0IP1                 (0x0008)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
+#define RT0IP0                 (0x0004)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
+#define RT0PSIE                (0x0002)       /* RTC Prescale Timer 0 Interrupt Enable Flag */
+#define RT0PSIFG               (0x0001)       /* RTC Prescale Timer 0 Interrupt Flag */
+
+/* RTCPS0CTL Control Bits */
+//#define Reserved          (0x0080)
+//#define Reserved          (0x0040)
+//#define Reserved          (0x0020)
+#define RT0IP2_L               (0x0010)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
+#define RT0IP1_L               (0x0008)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
+#define RT0IP0_L               (0x0004)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
+#define RT0PSIE_L              (0x0002)       /* RTC Prescale Timer 0 Interrupt Enable Flag */
+#define RT0PSIFG_L             (0x0001)       /* RTC Prescale Timer 0 Interrupt Flag */
+
+#define RT0IP_0                (0x0000)       /* RTC Prescale Timer 0 Interrupt Interval /2 */
+#define RT0IP_1                (0x0004)       /* RTC Prescale Timer 0 Interrupt Interval /4 */
+#define RT0IP_2                (0x0008)       /* RTC Prescale Timer 0 Interrupt Interval /8 */
+#define RT0IP_3                (0x000C)       /* RTC Prescale Timer 0 Interrupt Interval /16 */
+#define RT0IP_4                (0x0010)       /* RTC Prescale Timer 0 Interrupt Interval /32 */
+#define RT0IP_5                (0x0014)       /* RTC Prescale Timer 0 Interrupt Interval /64 */
+#define RT0IP_6                (0x0018)       /* RTC Prescale Timer 0 Interrupt Interval /128 */
+#define RT0IP_7                (0x001C)       /* RTC Prescale Timer 0 Interrupt Interval /256 */
+
+#define RT0IP__2               (0x0000)       /* RTC Prescale Timer 0 Interrupt Interval /2 */
+#define RT0IP__4               (0x0004)       /* RTC Prescale Timer 0 Interrupt Interval /4 */
+#define RT0IP__8               (0x0008)       /* RTC Prescale Timer 0 Interrupt Interval /8 */
+#define RT0IP__16              (0x000C)       /* RTC Prescale Timer 0 Interrupt Interval /16 */
+#define RT0IP__32              (0x0010)       /* RTC Prescale Timer 0 Interrupt Interval /32 */
+#define RT0IP__64              (0x0014)       /* RTC Prescale Timer 0 Interrupt Interval /64 */
+#define RT0IP__128             (0x0018)       /* RTC Prescale Timer 0 Interrupt Interval /128 */
+#define RT0IP__256             (0x001C)       /* RTC Prescale Timer 0 Interrupt Interval /256 */
+
+/* RTCPS1CTL Control Bits */
+//#define Reserved          (0x0080)
+//#define Reserved          (0x0040)
+//#define Reserved          (0x0020)
+#define RT1IP2                 (0x0010)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
+#define RT1IP1                 (0x0008)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
+#define RT1IP0                 (0x0004)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
+#define RT1PSIE                (0x0002)       /* RTC Prescale Timer 1 Interrupt Enable Flag */
+#define RT1PSIFG               (0x0001)       /* RTC Prescale Timer 1 Interrupt Flag */
+
+/* RTCPS1CTL Control Bits */
+//#define Reserved          (0x0080)
+//#define Reserved          (0x0040)
+//#define Reserved          (0x0020)
+#define RT1IP2_L               (0x0010)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
+#define RT1IP1_L               (0x0008)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
+#define RT1IP0_L               (0x0004)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
+#define RT1PSIE_L              (0x0002)       /* RTC Prescale Timer 1 Interrupt Enable Flag */
+#define RT1PSIFG_L             (0x0001)       /* RTC Prescale Timer 1 Interrupt Flag */
+
+#define RT1IP_0                (0x0000)       /* RTC Prescale Timer 1 Interrupt Interval /2 */
+#define RT1IP_1                (0x0004)       /* RTC Prescale Timer 1 Interrupt Interval /4 */
+#define RT1IP_2                (0x0008)       /* RTC Prescale Timer 1 Interrupt Interval /8 */
+#define RT1IP_3                (0x000C)       /* RTC Prescale Timer 1 Interrupt Interval /16 */
+#define RT1IP_4                (0x0010)       /* RTC Prescale Timer 1 Interrupt Interval /32 */
+#define RT1IP_5                (0x0014)       /* RTC Prescale Timer 1 Interrupt Interval /64 */
+#define RT1IP_6                (0x0018)       /* RTC Prescale Timer 1 Interrupt Interval /128 */
+#define RT1IP_7                (0x001C)       /* RTC Prescale Timer 1 Interrupt Interval /256 */
+
+#define RT1IP__2               (0x0000)       /* RTC Prescale Timer 1 Interrupt Interval /2 */
+#define RT1IP__4               (0x0004)       /* RTC Prescale Timer 1 Interrupt Interval /4 */
+#define RT1IP__8               (0x0008)       /* RTC Prescale Timer 1 Interrupt Interval /8 */
+#define RT1IP__16              (0x000C)       /* RTC Prescale Timer 1 Interrupt Interval /16 */
+#define RT1IP__32              (0x0010)       /* RTC Prescale Timer 1 Interrupt Interval /32 */
+#define RT1IP__64              (0x0014)       /* RTC Prescale Timer 1 Interrupt Interval /64 */
+#define RT1IP__128             (0x0018)       /* RTC Prescale Timer 1 Interrupt Interval /128 */
+#define RT1IP__256             (0x001C)       /* RTC Prescale Timer 1 Interrupt Interval /256 */
+
+/* RTC Definitions */
+#define RTCIV_NONE             (0x0000)       /* No Interrupt pending */
+#define RTCIV_RTCRDYIFG        (0x0002)       /* RTC ready: RTCRDYIFG */
+#define RTCIV_RTCTEVIFG        (0x0004)       /* RTC interval timer: RTCTEVIFG */
+#define RTCIV_RTCAIFG          (0x0006)       /* RTC user alarm: RTCAIFG */
+#define RTCIV_RT0PSIFG         (0x0008)       /* RTC prescaler 0: RT0PSIFG */
+#define RTCIV_RT1PSIFG         (0x000A)       /* RTC prescaler 1: RT1PSIFG */
+#define RTCIV_RTCOFIFG         (0x000C)       /* RTC Oscillator fault */
+
+/* Legacy Definitions */
+#define RTC_NONE               (0x0000)       /* No Interrupt pending */
+#define RTC_RTCRDYIFG          (0x0002)       /* RTC ready: RTCRDYIFG */
+#define RTC_RTCTEVIFG          (0x0004)       /* RTC interval timer: RTCTEVIFG */
+#define RTC_RTCAIFG            (0x0006)       /* RTC user alarm: RTCAIFG */
+#define RTC_RT0PSIFG           (0x0008)       /* RTC prescaler 0: RT0PSIFG */
+#define RTC_RT1PSIFG           (0x000A)       /* RTC prescaler 1: RT1PSIFG */
+#define RTC_RTCOFIFG           (0x000C)       /* RTC Oscillator fault */
+
+/************************************************************
+* SFR - Special Function Register Module
+************************************************************/
+#define __MSP430_HAS_SFR__                    /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_SFR__ 0x0100
+#define SFR_BASE               __MSP430_BASEADDRESS_SFR__
+
+sfr_w(SFRIE1);                                /* Interrupt Enable 1 */
+sfr_b(SFRIE1_L);                              /* Interrupt Enable 1 */
+sfr_b(SFRIE1_H);                              /* Interrupt Enable 1 */
+
+/* SFRIE1 Control Bits */
+#define WDTIE                  (0x0001)       /* WDT Interrupt Enable */
+#define OFIE                   (0x0002)       /* Osc Fault Enable */
+//#define Reserved          (0x0004)
+#define VMAIE                  (0x0008)       /* Vacant Memory Interrupt Enable */
+#define NMIIE                  (0x0010)       /* NMI Interrupt Enable */
+#define JMBINIE                (0x0040)       /* JTAG Mail Box input Interrupt Enable */
+#define JMBOUTIE               (0x0080)       /* JTAG Mail Box output Interrupt Enable */
+
+#define WDTIE_L                (0x0001)       /* WDT Interrupt Enable */
+#define OFIE_L                 (0x0002)       /* Osc Fault Enable */
+//#define Reserved          (0x0004)
+#define VMAIE_L                (0x0008)       /* Vacant Memory Interrupt Enable */
+#define NMIIE_L                (0x0010)       /* NMI Interrupt Enable */
+#define JMBINIE_L              (0x0040)       /* JTAG Mail Box input Interrupt Enable */
+#define JMBOUTIE_L             (0x0080)       /* JTAG Mail Box output Interrupt Enable */
+
+sfr_w(SFRIFG1);                               /* Interrupt Flag 1 */
+sfr_b(SFRIFG1_L);                             /* Interrupt Flag 1 */
+sfr_b(SFRIFG1_H);                             /* Interrupt Flag 1 */
+/* SFRIFG1 Control Bits */
+#define WDTIFG                 (0x0001)       /* WDT Interrupt Flag */
+#define OFIFG                  (0x0002)       /* Osc Fault Flag */
+//#define Reserved          (0x0004)
+#define VMAIFG                 (0x0008)       /* Vacant Memory Interrupt Flag */
+#define NMIIFG                 (0x0010)       /* NMI Interrupt Flag */
+//#define Reserved          (0x0020)
+#define JMBINIFG               (0x0040)       /* JTAG Mail Box input Interrupt Flag */
+#define JMBOUTIFG              (0x0080)       /* JTAG Mail Box output Interrupt Flag */
+
+#define WDTIFG_L               (0x0001)       /* WDT Interrupt Flag */
+#define OFIFG_L                (0x0002)       /* Osc Fault Flag */
+//#define Reserved          (0x0004)
+#define VMAIFG_L               (0x0008)       /* Vacant Memory Interrupt Flag */
+#define NMIIFG_L               (0x0010)       /* NMI Interrupt Flag */
+//#define Reserved          (0x0020)
+#define JMBINIFG_L             (0x0040)       /* JTAG Mail Box input Interrupt Flag */
+#define JMBOUTIFG_L            (0x0080)       /* JTAG Mail Box output Interrupt Flag */
+
+sfr_w(SFRRPCR);                               /* RESET Pin Control Register */
+sfr_b(SFRRPCR_L);                             /* RESET Pin Control Register */
+sfr_b(SFRRPCR_H);                             /* RESET Pin Control Register */
+/* SFRRPCR Control Bits */
+#define SYSNMI                 (0x0001)       /* NMI select */
+#define SYSNMIIES              (0x0002)       /* NMI edge select */
+#define SYSRSTUP               (0x0004)       /* RESET Pin pull down/up select */
+#define SYSRSTRE               (0x0008)       /* RESET Pin Resistor enable */
+
+#define SYSNMI_L               (0x0001)       /* NMI select */
+#define SYSNMIIES_L            (0x0002)       /* NMI edge select */
+#define SYSRSTUP_L             (0x0004)       /* RESET Pin pull down/up select */
+#define SYSRSTRE_L             (0x0008)       /* RESET Pin Resistor enable */
+
+/************************************************************
+* SYS - System Module
+************************************************************/
+#define __MSP430_HAS_SYS__                    /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_SYS__ 0x0180
+#define SYS_BASE               __MSP430_BASEADDRESS_SYS__
+
+sfr_w(SYSCTL);                                /* System control */
+sfr_b(SYSCTL_L);                              /* System control */
+sfr_b(SYSCTL_H);                              /* System control */
+sfr_w(SYSJMBC);                               /* JTAG mailbox control */
+sfr_b(SYSJMBC_L);                             /* JTAG mailbox control */
+sfr_b(SYSJMBC_H);                             /* JTAG mailbox control */
+sfr_w(SYSJMBI0);                              /* JTAG mailbox input 0 */
+sfr_b(SYSJMBI0_L);                            /* JTAG mailbox input 0 */
+sfr_b(SYSJMBI0_H);                            /* JTAG mailbox input 0 */
+sfr_w(SYSJMBI1);                              /* JTAG mailbox input 1 */
+sfr_b(SYSJMBI1_L);                            /* JTAG mailbox input 1 */
+sfr_b(SYSJMBI1_H);                            /* JTAG mailbox input 1 */
+sfr_w(SYSJMBO0);                              /* JTAG mailbox output 0 */
+sfr_b(SYSJMBO0_L);                            /* JTAG mailbox output 0 */
+sfr_b(SYSJMBO0_H);                            /* JTAG mailbox output 0 */
+sfr_w(SYSJMBO1);                              /* JTAG mailbox output 1 */
+sfr_b(SYSJMBO1_L);                            /* JTAG mailbox output 1 */
+sfr_b(SYSJMBO1_H);                            /* JTAG mailbox output 1 */
+
+sfr_w(SYSUNIV);                               /* User NMI vector generator */
+sfr_b(SYSUNIV_L);                             /* User NMI vector generator */
+sfr_b(SYSUNIV_H);                             /* User NMI vector generator */
+sfr_w(SYSSNIV);                               /* System NMI vector generator */
+sfr_b(SYSSNIV_L);                             /* System NMI vector generator */
+sfr_b(SYSSNIV_H);                             /* System NMI vector generator */
+sfr_w(SYSRSTIV);                              /* Reset vector generator */
+sfr_b(SYSRSTIV_L);                            /* Reset vector generator */
+sfr_b(SYSRSTIV_H);                            /* Reset vector generator */
+
+/* SYSCTL Control Bits */
+#define SYSRIVECT              (0x0001)       /* SYS - RAM based interrupt vectors */
+//#define RESERVED            (0x0002)  /* SYS - Reserved */
+#define SYSPMMPE               (0x0004)       /* SYS - PMM access protect */
+//#define RESERVED            (0x0008)  /* SYS - Reserved */
+#define SYSBSLIND              (0x0010)       /* SYS - TCK/RST indication detected */
+#define SYSJTAGPIN             (0x0020)       /* SYS - Dedicated JTAG pins enabled */
+//#define RESERVED            (0x0040)  /* SYS - Reserved */
+//#define RESERVED            (0x0080)  /* SYS - Reserved */
+//#define RESERVED            (0x0100)  /* SYS - Reserved */
+//#define RESERVED            (0x0200)  /* SYS - Reserved */
+//#define RESERVED            (0x0400)  /* SYS - Reserved */
+//#define RESERVED            (0x0800)  /* SYS - Reserved */
+//#define RESERVED            (0x1000)  /* SYS - Reserved */
+//#define RESERVED            (0x2000)  /* SYS - Reserved */
+//#define RESERVED            (0x4000)  /* SYS - Reserved */
+//#define RESERVED            (0x8000)  /* SYS - Reserved */
+
+/* SYSCTL Control Bits */
+#define SYSRIVECT_L            (0x0001)       /* SYS - RAM based interrupt vectors */
+//#define RESERVED            (0x0002)  /* SYS - Reserved */
+#define SYSPMMPE_L             (0x0004)       /* SYS - PMM access protect */
+//#define RESERVED            (0x0008)  /* SYS - Reserved */
+#define SYSBSLIND_L            (0x0010)       /* SYS - TCK/RST indication detected */
+#define SYSJTAGPIN_L           (0x0020)       /* SYS - Dedicated JTAG pins enabled */
+//#define RESERVED            (0x0040)  /* SYS - Reserved */
+//#define RESERVED            (0x0080)  /* SYS - Reserved */
+//#define RESERVED            (0x0100)  /* SYS - Reserved */
+//#define RESERVED            (0x0200)  /* SYS - Reserved */
+//#define RESERVED            (0x0400)  /* SYS - Reserved */
+//#define RESERVED            (0x0800)  /* SYS - Reserved */
+//#define RESERVED            (0x1000)  /* SYS - Reserved */
+//#define RESERVED            (0x2000)  /* SYS - Reserved */
+//#define RESERVED            (0x4000)  /* SYS - Reserved */
+//#define RESERVED            (0x8000)  /* SYS - Reserved */
+
+/* SYSJMBC Control Bits */
+#define JMBIN0FG               (0x0001)       /* SYS - Incoming JTAG Mailbox 0 Flag */
+#define JMBIN1FG               (0x0002)       /* SYS - Incoming JTAG Mailbox 1 Flag */
+#define JMBOUT0FG              (0x0004)       /* SYS - Outgoing JTAG Mailbox 0 Flag */
+#define JMBOUT1FG              (0x0008)       /* SYS - Outgoing JTAG Mailbox 1 Flag */
+#define JMBMODE                (0x0010)       /* SYS - JMB 16/32 Bit Mode */
+//#define RESERVED            (0x0020)  /* SYS - Reserved */
+#define JMBCLR0OFF             (0x0040)       /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
+#define JMBCLR1OFF             (0x0080)       /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
+//#define RESERVED            (0x0100)  /* SYS - Reserved */
+//#define RESERVED            (0x0200)  /* SYS - Reserved */
+//#define RESERVED            (0x0400)  /* SYS - Reserved */
+//#define RESERVED            (0x0800)  /* SYS - Reserved */
+//#define RESERVED            (0x1000)  /* SYS - Reserved */
+//#define RESERVED            (0x2000)  /* SYS - Reserved */
+//#define RESERVED            (0x4000)  /* SYS - Reserved */
+//#define RESERVED            (0x8000)  /* SYS - Reserved */
+
+/* SYSJMBC Control Bits */
+#define JMBIN0FG_L             (0x0001)       /* SYS - Incoming JTAG Mailbox 0 Flag */
+#define JMBIN1FG_L             (0x0002)       /* SYS - Incoming JTAG Mailbox 1 Flag */
+#define JMBOUT0FG_L            (0x0004)       /* SYS - Outgoing JTAG Mailbox 0 Flag */
+#define JMBOUT1FG_L            (0x0008)       /* SYS - Outgoing JTAG Mailbox 1 Flag */
+#define JMBMODE_L              (0x0010)       /* SYS - JMB 16/32 Bit Mode */
+//#define RESERVED            (0x0020)  /* SYS - Reserved */
+#define JMBCLR0OFF_L           (0x0040)       /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
+#define JMBCLR1OFF_L           (0x0080)       /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
+//#define RESERVED            (0x0100)  /* SYS - Reserved */
+//#define RESERVED            (0x0200)  /* SYS - Reserved */
+//#define RESERVED            (0x0400)  /* SYS - Reserved */
+//#define RESERVED            (0x0800)  /* SYS - Reserved */
+//#define RESERVED            (0x1000)  /* SYS - Reserved */
+//#define RESERVED            (0x2000)  /* SYS - Reserved */
+//#define RESERVED            (0x4000)  /* SYS - Reserved */
+//#define RESERVED            (0x8000)  /* SYS - Reserved */
+
+
+/* SYSUNIV Definitions */
+#define SYSUNIV_NONE           (0x0000)       /* No Interrupt pending */
+#define SYSUNIV_NMIIFG         (0x0002)       /* SYSUNIV : NMIIFG */
+#define SYSUNIV_OFIFG          (0x0004)       /* SYSUNIV : Osc. Fail - OFIFG */
+
+/* SYSSNIV Definitions */
+#define SYSSNIV_NONE           (0x0000)       /* No Interrupt pending */
+#define SYSSNIV_RES02          (0x0002)       /* SYSSNIV : Reserved */
+#define SYSSNIV_UBDIFG         (0x0004)       /* SYSSNIV : FRAM Uncorrectable bit Error */
+#define SYSSNIV_RES06          (0x0006)       /* SYSSNIV : Reserved */
+#define SYSSNIV_MPUSEGPIFG     (0x0008)       /* SYSSNIV : MPUSEGPIFG violation */
+#define SYSSNIV_MPUSEGIIFG     (0x000A)       /* SYSSNIV : MPUSEGIIFG violation */
+#define SYSSNIV_MPUSEG1IFG     (0x000C)       /* SYSSNIV : MPUSEG1IFG violation */
+#define SYSSNIV_MPUSEG2IFG     (0x000E)       /* SYSSNIV : MPUSEG2IFG violation */
+#define SYSSNIV_MPUSEG3IFG     (0x0010)       /* SYSSNIV : MPUSEG3IFG violation */
+#define SYSSNIV_VMAIFG         (0x0012)       /* SYSSNIV : VMAIFG */
+#define SYSSNIV_JMBINIFG       (0x0014)       /* SYSSNIV : JMBINIFG */
+#define SYSSNIV_JMBOUTIFG      (0x0016)       /* SYSSNIV : JMBOUTIFG */
+#define SYSSNIV_CBDIFG         (0x0018)       /* SYSSNIV : FRAM Correctable Bit error */
+
+/* SYSRSTIV Definitions */
+#define SYSRSTIV_NONE          (0x0000)       /* No Interrupt pending */
+#define SYSRSTIV_BOR           (0x0002)       /* SYSRSTIV : BOR */
+#define SYSRSTIV_RSTNMI        (0x0004)       /* SYSRSTIV : RST/NMI */
+#define SYSRSTIV_DOBOR         (0x0006)       /* SYSRSTIV : Do BOR */
+#define SYSRSTIV_LPM5WU        (0x0008)       /* SYSRSTIV : Port LPM5 Wake Up */
+#define SYSRSTIV_SECYV         (0x000A)       /* SYSRSTIV : Security violation */
+#define SYSRSTIV_RES0C         (0x000C)       /* SYSRSTIV : Reserved */
+#define SYSRSTIV_SVSHIFG       (0x000E)       /* SYSRSTIV : SVSHIFG */
+#define SYSRSTIV_RES10         (0x0010)       /* SYSRSTIV : Reserved */
+#define SYSRSTIV_RES12         (0x0012)       /* SYSRSTIV : Reserved */
+#define SYSRSTIV_DOPOR         (0x0014)       /* SYSRSTIV : Do POR */
+#define SYSRSTIV_WDTTO         (0x0016)       /* SYSRSTIV : WDT Time out */
+#define SYSRSTIV_WDTKEY        (0x0018)       /* SYSRSTIV : WDTKEY violation */
+#define SYSRSTIV_FRCTLPW       (0x001A)       /* SYSRSTIV : FRAM Key violation */
+#define SYSRSTIV_UBDIFG        (0x001C)       /* SYSRSTIV : FRAM Uncorrectable bit Error */
+#define SYSRSTIV_PERF          (0x001E)       /* SYSRSTIV : peripheral/config area fetch */
+#define SYSRSTIV_PMMPW         (0x0020)       /* SYSRSTIV : PMM Password violation */
+#define SYSRSTIV_MPUPW         (0x0022)       /* SYSRSTIV : MPU Password violation */
+#define SYSRSTIV_CSPW          (0x0024)       /* SYSRSTIV : CS Password violation */
+#define SYSRSTIV_MPUSEGPIFG    (0x0026)       /* SYSRSTIV : MPUSEGPIFG violation */
+#define SYSRSTIV_MPUSEGIIFG    (0x0028)       /* SYSRSTIV : MPUSEGIIFG violation */
+#define SYSRSTIV_MPUSEG1IFG    (0x002A)       /* SYSRSTIV : MPUSEG1IFG violation */
+#define SYSRSTIV_MPUSEG2IFG    (0x002C)       /* SYSRSTIV : MPUSEG2IFG violation */
+#define SYSRSTIV_MPUSEG3IFG    (0x002E)       /* SYSRSTIV : MPUSEG3IFG violation */
+#define SYSRSTIV_ACCTEIFG      (0x0030)       /* SYSRSTIV : ACCTEIFG access time error */
+
+/************************************************************
+* Timer0_A3
+************************************************************/
+#define __MSP430_HAS_T0A3__                   /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_T0A3__ 0x0340
+#define TIMER_A0_BASE          __MSP430_BASEADDRESS_T0A3__
+
+sfr_w(TA0CTL);                                /* Timer0_A3 Control */
+sfr_w(TA0CCTL0);                              /* Timer0_A3 Capture/Compare Control 0 */
+sfr_w(TA0CCTL1);                              /* Timer0_A3 Capture/Compare Control 1 */
+sfr_w(TA0CCTL2);                              /* Timer0_A3 Capture/Compare Control 2 */
+sfr_w(TA0R);                                  /* Timer0_A3 */
+sfr_w(TA0CCR0);                               /* Timer0_A3 Capture/Compare 0 */
+sfr_w(TA0CCR1);                               /* Timer0_A3 Capture/Compare 1 */
+sfr_w(TA0CCR2);                               /* Timer0_A3 Capture/Compare 2 */
+sfr_w(TA0IV);                                 /* Timer0_A3 Interrupt Vector Word */
+sfr_w(TA0EX0);                                /* Timer0_A3 Expansion Register 0 */
+
+/* TAxCTL Control Bits */
+#define TASSEL1                (0x0200)       /* Timer A clock source select 1 */
+#define TASSEL0                (0x0100)       /* Timer A clock source select 0 */
+#define ID1                    (0x0080)       /* Timer A clock input divider 1 */
+#define ID0                    (0x0040)       /* Timer A clock input divider 0 */
+#define MC1                    (0x0020)       /* Timer A mode control 1 */
+#define MC0                    (0x0010)       /* Timer A mode control 0 */
+#define TACLR                  (0x0004)       /* Timer A counter clear */
+#define TAIE                   (0x0002)       /* Timer A counter interrupt enable */
+#define TAIFG                  (0x0001)       /* Timer A counter interrupt flag */
+
+#define MC_0                   (0x0000)       /* Timer A mode control: 0 - Stop */
+#define MC_1                   (0x0010)       /* Timer A mode control: 1 - Up to CCR0 */
+#define MC_2                   (0x0020)       /* Timer A mode control: 2 - Continuous up */
+#define MC_3                   (0x0030)       /* Timer A mode control: 3 - Up/Down */
+#define ID_0                   (0x0000)       /* Timer A input divider: 0 - /1 */
+#define ID_1                   (0x0040)       /* Timer A input divider: 1 - /2 */
+#define ID_2                   (0x0080)       /* Timer A input divider: 2 - /4 */
+#define ID_3                   (0x00C0)       /* Timer A input divider: 3 - /8 */
+#define TASSEL_0               (0x0000)       /* Timer A clock source select: 0 - TACLK */
+#define TASSEL_1               (0x0100)       /* Timer A clock source select: 1 - ACLK  */
+#define TASSEL_2               (0x0200)       /* Timer A clock source select: 2 - SMCLK */
+#define TASSEL_3               (0x0300)       /* Timer A clock source select: 3 - INCLK */
+#define MC__STOP               (0x0000)       /* Timer A mode control: 0 - Stop */
+#define MC__UP                 (0x0010)       /* Timer A mode control: 1 - Up to CCR0 */
+#define MC__CONTINUOUS         (0x0020)       /* Timer A mode control: 2 - Continuous up */
+#define MC__CONTINOUS          (0x0020)       /* Legacy define */
+#define MC__UPDOWN             (0x0030)       /* Timer A mode control: 3 - Up/Down */
+#define ID__1                  (0x0000)       /* Timer A input divider: 0 - /1 */
+#define ID__2                  (0x0040)       /* Timer A input divider: 1 - /2 */
+#define ID__4                  (0x0080)       /* Timer A input divider: 2 - /4 */
+#define ID__8                  (0x00C0)       /* Timer A input divider: 3 - /8 */
+#define TASSEL__TACLK          (0x0000)       /* Timer A clock source select: 0 - TACLK */
+#define TASSEL__ACLK           (0x0100)       /* Timer A clock source select: 1 - ACLK  */
+#define TASSEL__SMCLK          (0x0200)       /* Timer A clock source select: 2 - SMCLK */
+#define TASSEL__INCLK          (0x0300)       /* Timer A clock source select: 3 - INCLK */
+
+/* TAxCCTLx Control Bits */
+#define CM1                    (0x8000)       /* Capture mode 1 */
+#define CM0                    (0x4000)       /* Capture mode 0 */
+#define CCIS1                  (0x2000)       /* Capture input select 1 */
+#define CCIS0                  (0x1000)       /* Capture input select 0 */
+#define SCS                    (0x0800)       /* Capture sychronize */
+#define SCCI                   (0x0400)       /* Latched capture signal (read) */
+#define CAP                    (0x0100)       /* Capture mode: 1 /Compare mode : 0 */
+#define OUTMOD2                (0x0080)       /* Output mode 2 */
+#define OUTMOD1                (0x0040)       /* Output mode 1 */
+#define OUTMOD0                (0x0020)       /* Output mode 0 */
+#define CCIE                   (0x0010)       /* Capture/compare interrupt enable */
+#define CCI                    (0x0008)       /* Capture input signal (read) */
+#define OUT                    (0x0004)       /* PWM Output signal if output mode 0 */
+#define COV                    (0x0002)       /* Capture/compare overflow flag */
+#define CCIFG                  (0x0001)       /* Capture/compare interrupt flag */
+
+#define OUTMOD_0               (0x0000)       /* PWM output mode: 0 - output only */
+#define OUTMOD_1               (0x0020)       /* PWM output mode: 1 - set */
+#define OUTMOD_2               (0x0040)       /* PWM output mode: 2 - PWM toggle/reset */
+#define OUTMOD_3               (0x0060)       /* PWM output mode: 3 - PWM set/reset */
+#define OUTMOD_4               (0x0080)       /* PWM output mode: 4 - toggle */
+#define OUTMOD_5               (0x00A0)       /* PWM output mode: 5 - Reset */
+#define OUTMOD_6               (0x00C0)       /* PWM output mode: 6 - PWM toggle/set */
+#define OUTMOD_7               (0x00E0)       /* PWM output mode: 7 - PWM reset/set */
+#define CCIS_0                 (0x0000)       /* Capture input select: 0 - CCIxA */
+#define CCIS_1                 (0x1000)       /* Capture input select: 1 - CCIxB */
+#define CCIS_2                 (0x2000)       /* Capture input select: 2 - GND */
+#define CCIS_3                 (0x3000)       /* Capture input select: 3 - Vcc */
+#define CM_0                   (0x0000)       /* Capture mode: 0 - disabled */
+#define CM_1                   (0x4000)       /* Capture mode: 1 - pos. edge */
+#define CM_2                   (0x8000)       /* Capture mode: 1 - neg. edge */
+#define CM_3                   (0xC000)       /* Capture mode: 1 - both edges */
+
+/* TAxEX0 Control Bits */
+#define TAIDEX0                (0x0001)       /* Timer A Input divider expansion Bit: 0 */
+#define TAIDEX1                (0x0002)       /* Timer A Input divider expansion Bit: 1 */
+#define TAIDEX2                (0x0004)       /* Timer A Input divider expansion Bit: 2 */
+
+#define TAIDEX_0               (0x0000)       /* Timer A Input divider expansion : /1 */
+#define TAIDEX_1               (0x0001)       /* Timer A Input divider expansion : /2 */
+#define TAIDEX_2               (0x0002)       /* Timer A Input divider expansion : /3 */
+#define TAIDEX_3               (0x0003)       /* Timer A Input divider expansion : /4 */
+#define TAIDEX_4               (0x0004)       /* Timer A Input divider expansion : /5 */
+#define TAIDEX_5               (0x0005)       /* Timer A Input divider expansion : /6 */
+#define TAIDEX_6               (0x0006)       /* Timer A Input divider expansion : /7 */
+#define TAIDEX_7               (0x0007)       /* Timer A Input divider expansion : /8 */
+
+/* T0A3IV Definitions */
+#define TA0IV_NONE             (0x0000)       /* No Interrupt pending */
+#define TA0IV_TACCR1           (0x0002)       /* TA0CCR1_CCIFG */
+#define TA0IV_TACCR2           (0x0004)       /* TA0CCR2_CCIFG */
+#define TA0IV_3                (0x0006)       /* Reserved */
+#define TA0IV_4                (0x0008)       /* Reserved */
+#define TA0IV_5                (0x000A)       /* Reserved */
+#define TA0IV_6                (0x000C)       /* Reserved */
+#define TA0IV_TAIFG            (0x000E)       /* TA0IFG */
+
+/* Legacy Defines */
+#define TA0IV_TA0CCR1          (0x0002)       /* TA0CCR1_CCIFG */
+#define TA0IV_TA0CCR2          (0x0004)       /* TA0CCR2_CCIFG */
+#define TA0IV_TA0IFG           (0x000E)       /* TA0IFG */
+
+/************************************************************
+* Timer1_A3
+************************************************************/
+#define __MSP430_HAS_T1A3__                   /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_T1A3__ 0x0380
+#define TIMER_A1_BASE          __MSP430_BASEADDRESS_T1A3__
+
+sfr_w(TA1CTL);                                /* Timer1_A3 Control */
+sfr_w(TA1CCTL0);                              /* Timer1_A3 Capture/Compare Control 0 */
+sfr_w(TA1CCTL1);                              /* Timer1_A3 Capture/Compare Control 1 */
+sfr_w(TA1CCTL2);                              /* Timer1_A3 Capture/Compare Control 2 */
+sfr_w(TA1R);                                  /* Timer1_A3 */
+sfr_w(TA1CCR0);                               /* Timer1_A3 Capture/Compare 0 */
+sfr_w(TA1CCR1);                               /* Timer1_A3 Capture/Compare 1 */
+sfr_w(TA1CCR2);                               /* Timer1_A3 Capture/Compare 2 */
+sfr_w(TA1IV);                                 /* Timer1_A3 Interrupt Vector Word */
+sfr_w(TA1EX0);                                /* Timer1_A3 Expansion Register 0 */
+
+/* Bits are already defined within the Timer0_Ax */
+
+/* TA1IV Definitions */
+#define TA1IV_NONE             (0x0000)       /* No Interrupt pending */
+#define TA1IV_TACCR1           (0x0002)       /* TA1CCR1_CCIFG */
+#define TA1IV_TACCR2           (0x0004)       /* TA1CCR2_CCIFG */
+#define TA1IV_3                (0x0006)       /* Reserved */
+#define TA1IV_4                (0x0008)       /* Reserved */
+#define TA1IV_5                (0x000A)       /* Reserved */
+#define TA1IV_6                (0x000C)       /* Reserved */
+#define TA1IV_TAIFG            (0x000E)       /* TA1IFG */
+
+/* Legacy Defines */
+#define TA1IV_TA1CCR1          (0x0002)       /* TA1CCR1_CCIFG */
+#define TA1IV_TA1CCR2          (0x0004)       /* TA1CCR2_CCIFG */
+#define TA1IV_TA1IFG           (0x000E)       /* TA1IFG */
+
+/************************************************************
+* Timer2_A2
+************************************************************/
+#define __MSP430_HAS_T2A2__                   /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_T2A2__ 0x0400
+#define TIMER_A2_BASE          __MSP430_BASEADDRESS_T2A2__
+
+sfr_w(TA2CTL);                                /* Timer2_A2 Control */
+sfr_w(TA2CCTL0);                              /* Timer2_A2 Capture/Compare Control 0 */
+sfr_w(TA2CCTL1);                              /* Timer2_A2 Capture/Compare Control 1 */
+sfr_w(TA2R);                                  /* Timer2_A2 */
+sfr_w(TA2CCR0);                               /* Timer2_A2 Capture/Compare 0 */
+sfr_w(TA2CCR1);                               /* Timer2_A2 Capture/Compare 1 */
+sfr_w(TA2IV);                                 /* Timer2_A2 Interrupt Vector Word */
+sfr_w(TA2EX0);                                /* Timer2_A2 Expansion Register 0 */
+
+/* Bits are already defined within the Timer0_Ax */
+
+/* TA2IV Definitions */
+#define TA2IV_NONE             (0x0000)       /* No Interrupt pending */
+#define TA2IV_TACCR1           (0x0002)       /* TA2CCR1_CCIFG */
+#define TA2IV_3                (0x0006)       /* Reserved */
+#define TA2IV_4                (0x0008)       /* Reserved */
+#define TA2IV_5                (0x000A)       /* Reserved */
+#define TA2IV_6                (0x000C)       /* Reserved */
+#define TA2IV_TAIFG            (0x000E)       /* TA2IFG */
+
+/* Legacy Defines */
+#define TA2IV_TA2CCR1          (0x0002)       /* TA2CCR1_CCIFG */
+#define TA2IV_TA2IFG           (0x000E)       /* TA2IFG */
+
+/************************************************************
+* Timer3_A2
+************************************************************/
+#define __MSP430_HAS_T3A2__                   /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_T3A2__ 0x0440
+#define TIMER_A3_BASE          __MSP430_BASEADDRESS_T3A2__
+
+sfr_w(TA3CTL);                                /* Timer3_A2 Control */
+sfr_w(TA3CCTL0);                              /* Timer3_A2 Capture/Compare Control 0 */
+sfr_w(TA3CCTL1);                              /* Timer3_A2 Capture/Compare Control 1 */
+sfr_w(TA3R);                                  /* Timer3_A2 */
+sfr_w(TA3CCR0);                               /* Timer3_A2 Capture/Compare 0 */
+sfr_w(TA3CCR1);                               /* Timer3_A2 Capture/Compare 1 */
+sfr_w(TA3IV);                                 /* Timer3_A2 Interrupt Vector Word */
+sfr_w(TA3EX0);                                /* Timer3_A2 Expansion Register 0 */
+
+/* Bits are already defined within the Timer0_Ax */
+
+/* TA3IV Definitions */
+#define TA3IV_NONE             (0x0000)       /* No Interrupt pending */
+#define TA3IV_TACCR1           (0x0002)       /* TA3CCR1_CCIFG */
+#define TA3IV_3                (0x0006)       /* Reserved */
+#define TA3IV_4                (0x0008)       /* Reserved */
+#define TA3IV_5                (0x000A)       /* Reserved */
+#define TA3IV_6                (0x000C)       /* Reserved */
+#define TA3IV_TAIFG            (0x000E)       /* TA3IFG */
+
+/* Legacy Defines */
+#define TA3IV_TA3CCR1          (0x0002)       /* TA3CCR1_CCIFG */
+#define TA3IV_TA3IFG           (0x000E)       /* TA3IFG */
+
+/************************************************************
+* Timer0_B7
+************************************************************/
+#define __MSP430_HAS_T0B7__                   /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_T0B7__ 0x03C0
+#define TIMER_B0_BASE          __MSP430_BASEADDRESS_T0B7__
+
+sfr_w(TB0CTL);                                /* Timer0_B7 Control */
+sfr_w(TB0CCTL0);                              /* Timer0_B7 Capture/Compare Control 0 */
+sfr_w(TB0CCTL1);                              /* Timer0_B7 Capture/Compare Control 1 */
+sfr_w(TB0CCTL2);                              /* Timer0_B7 Capture/Compare Control 2 */
+sfr_w(TB0CCTL3);                              /* Timer0_B7 Capture/Compare Control 3 */
+sfr_w(TB0CCTL4);                              /* Timer0_B7 Capture/Compare Control 4 */
+sfr_w(TB0CCTL5);                              /* Timer0_B7 Capture/Compare Control 5 */
+sfr_w(TB0CCTL6);                              /* Timer0_B7 Capture/Compare Control 6 */
+sfr_w(TB0R);                                  /* Timer0_B7 */
+sfr_w(TB0CCR0);                               /* Timer0_B7 Capture/Compare 0 */
+sfr_w(TB0CCR1);                               /* Timer0_B7 Capture/Compare 1 */
+sfr_w(TB0CCR2);                               /* Timer0_B7 Capture/Compare 2 */
+sfr_w(TB0CCR3);                               /* Timer0_B7 Capture/Compare 3 */
+sfr_w(TB0CCR4);                               /* Timer0_B7 Capture/Compare 4 */
+sfr_w(TB0CCR5);                               /* Timer0_B7 Capture/Compare 5 */
+sfr_w(TB0CCR6);                               /* Timer0_B7 Capture/Compare 6 */
+sfr_w(TB0EX0);                                /* Timer0_B7 Expansion Register 0 */
+sfr_w(TB0IV);                                 /* Timer0_B7 Interrupt Vector Word */
+
+/* Legacy Type Definitions for TimerB */
+#define TBCTL                  TB0CTL         /* Timer0_B7 Control */
+#define TBCCTL0                TB0CCTL0       /* Timer0_B7 Capture/Compare Control 0 */
+#define TBCCTL1                TB0CCTL1       /* Timer0_B7 Capture/Compare Control 1 */
+#define TBCCTL2                TB0CCTL2       /* Timer0_B7 Capture/Compare Control 2 */
+#define TBCCTL3                TB0CCTL3       /* Timer0_B7 Capture/Compare Control 3 */
+#define TBCCTL4                TB0CCTL4       /* Timer0_B7 Capture/Compare Control 4 */
+#define TBCCTL5                TB0CCTL5       /* Timer0_B7 Capture/Compare Control 5 */
+#define TBCCTL6                TB0CCTL6       /* Timer0_B7 Capture/Compare Control 6 */
+#define TBR                    TB0R           /* Timer0_B7 */
+#define TBCCR0                 TB0CCR0        /* Timer0_B7 Capture/Compare 0 */
+#define TBCCR1                 TB0CCR1        /* Timer0_B7 Capture/Compare 1 */
+#define TBCCR2                 TB0CCR2        /* Timer0_B7 Capture/Compare 2 */
+#define TBCCR3                 TB0CCR3        /* Timer0_B7 Capture/Compare 3 */
+#define TBCCR4                 TB0CCR4        /* Timer0_B7 Capture/Compare 4 */
+#define TBCCR5                 TB0CCR5        /* Timer0_B7 Capture/Compare 5 */
+#define TBCCR6                 TB0CCR6        /* Timer0_B7 Capture/Compare 6 */
+#define TBEX0                  TB0EX0         /* Timer0_B7 Expansion Register 0 */
+#define TBIV                   TB0IV          /* Timer0_B7 Interrupt Vector Word */
+#define TIMERB1_VECTOR       TIMER0_B1_VECTOR /* Timer0_B7 CC1-6, TB */
+#define TIMERB0_VECTOR       TIMER0_B0_VECTOR /* Timer0_B7 CC0 */
+
+/* TBxCTL Control Bits */
+#define TBCLGRP1               (0x4000)       /* Timer0_B7 Compare latch load group 1 */
+#define TBCLGRP0               (0x2000)       /* Timer0_B7 Compare latch load group 0 */
+#define CNTL1                  (0x1000)       /* Counter lenght 1 */
+#define CNTL0                  (0x0800)       /* Counter lenght 0 */
+#define TBSSEL1                (0x0200)       /* Clock source 1 */
+#define TBSSEL0                (0x0100)       /* Clock source 0 */
+#define TBCLR                  (0x0004)       /* Timer0_B7 counter clear */
+#define TBIE                   (0x0002)       /* Timer0_B7 interrupt enable */
+#define TBIFG                  (0x0001)       /* Timer0_B7 interrupt flag */
+
+#define SHR1                   (0x4000)       /* Timer0_B7 Compare latch load group 1 */
+#define SHR0                   (0x2000)       /* Timer0_B7 Compare latch load group 0 */
+
+#define TBSSEL_0               (0x0000)       /* Clock Source: TBCLK */
+#define TBSSEL_1               (0x0100)       /* Clock Source: ACLK  */
+#define TBSSEL_2               (0x0200)       /* Clock Source: SMCLK */
+#define TBSSEL_3               (0x0300)       /* Clock Source: INCLK */
+#define CNTL_0                 (0x0000)       /* Counter lenght: 16 bit */
+#define CNTL_1                 (0x0800)       /* Counter lenght: 12 bit */
+#define CNTL_2                 (0x1000)       /* Counter lenght: 10 bit */
+#define CNTL_3                 (0x1800)       /* Counter lenght:  8 bit */
+#define SHR_0                  (0x0000)       /* Timer0_B7 Group: 0 - individually */
+#define SHR_1                  (0x2000)       /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
+#define SHR_2                  (0x4000)       /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/
+#define SHR_3                  (0x6000)       /* Timer0_B7 Group: 3 - 1 group (all) */
+#define TBCLGRP_0              (0x0000)       /* Timer0_B7 Group: 0 - individually */
+#define TBCLGRP_1              (0x2000)       /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
+#define TBCLGRP_2              (0x4000)       /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/
+#define TBCLGRP_3              (0x6000)       /* Timer0_B7 Group: 3 - 1 group (all) */
+#define TBSSEL__TBCLK          (0x0000)       /* Timer0_B7 clock source select: 0 - TBCLK */
+#define TBSSEL__TACLK          (0x0000)       /* Timer0_B7 clock source select: 0 - TBCLK (legacy) */
+#define TBSSEL__ACLK           (0x0100)       /* Timer0_B7 clock source select: 1 - ACLK  */
+#define TBSSEL__SMCLK          (0x0200)       /* Timer0_B7 clock source select: 2 - SMCLK */
+#define TBSSEL__INCLK          (0x0300)       /* Timer0_B7 clock source select: 3 - INCLK */
+#define CNTL__16               (0x0000)       /* Counter lenght: 16 bit */
+#define CNTL__12               (0x0800)       /* Counter lenght: 12 bit */
+#define CNTL__10               (0x1000)       /* Counter lenght: 10 bit */
+#define CNTL__8                (0x1800)       /* Counter lenght:  8 bit */
+
+/* Additional Timer B Control Register bits are defined in Timer A */
+/* TBxCCTLx Control Bits */
+#define CLLD1                  (0x0400)       /* Compare latch load source 1 */
+#define CLLD0                  (0x0200)       /* Compare latch load source 0 */
+
+#define SLSHR1                 (0x0400)       /* Compare latch load source 1 */
+#define SLSHR0                 (0x0200)       /* Compare latch load source 0 */
+
+#define SLSHR_0                (0x0000)       /* Compare latch load sourec : 0 - immediate */
+#define SLSHR_1                (0x0200)       /* Compare latch load sourec : 1 - TBR counts to 0 */
+#define SLSHR_2                (0x0400)       /* Compare latch load sourec : 2 - up/down */
+#define SLSHR_3                (0x0600)       /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
+
+#define CLLD_0                 (0x0000)       /* Compare latch load sourec : 0 - immediate */
+#define CLLD_1                 (0x0200)       /* Compare latch load sourec : 1 - TBR counts to 0 */
+#define CLLD_2                 (0x0400)       /* Compare latch load sourec : 2 - up/down */
+#define CLLD_3                 (0x0600)       /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
+
+/* TBxEX0 Control Bits */
+#define TBIDEX0                (0x0001)       /* Timer0_B7 Input divider expansion Bit: 0 */
+#define TBIDEX1                (0x0002)       /* Timer0_B7 Input divider expansion Bit: 1 */
+#define TBIDEX2                (0x0004)       /* Timer0_B7 Input divider expansion Bit: 2 */
+
+#define TBIDEX_0               (0x0000)       /* Timer0_B7 Input divider expansion : /1 */
+#define TBIDEX_1               (0x0001)       /* Timer0_B7 Input divider expansion : /2 */
+#define TBIDEX_2               (0x0002)       /* Timer0_B7 Input divider expansion : /3 */
+#define TBIDEX_3               (0x0003)       /* Timer0_B7 Input divider expansion : /4 */
+#define TBIDEX_4               (0x0004)       /* Timer0_B7 Input divider expansion : /5 */
+#define TBIDEX_5               (0x0005)       /* Timer0_B7 Input divider expansion : /6 */
+#define TBIDEX_6               (0x0006)       /* Timer0_B7 Input divider expansion : /7 */
+#define TBIDEX_7               (0x0007)       /* Timer0_B7 Input divider expansion : /8 */
+#define TBIDEX__1              (0x0000)       /* Timer0_B7 Input divider expansion : /1 */
+#define TBIDEX__2              (0x0001)       /* Timer0_B7 Input divider expansion : /2 */
+#define TBIDEX__3              (0x0002)       /* Timer0_B7 Input divider expansion : /3 */
+#define TBIDEX__4              (0x0003)       /* Timer0_B7 Input divider expansion : /4 */
+#define TBIDEX__5              (0x0004)       /* Timer0_B7 Input divider expansion : /5 */
+#define TBIDEX__6              (0x0005)       /* Timer0_B7 Input divider expansion : /6 */
+#define TBIDEX__7              (0x0006)       /* Timer0_B7 Input divider expansion : /7 */
+#define TBIDEX__8              (0x0007)       /* Timer0_B7 Input divider expansion : /8 */
+
+/* TB0IV Definitions */
+#define TB0IV_NONE             (0x0000)       /* No Interrupt pending */
+#define TB0IV_TBCCR1           (0x0002)       /* TB0CCR1_CCIFG */
+#define TB0IV_TBCCR2           (0x0004)       /* TB0CCR2_CCIFG */
+#define TB0IV_TBCCR3           (0x0006)       /* TB0CCR3_CCIFG */
+#define TB0IV_TBCCR4           (0x0008)       /* TB0CCR4_CCIFG */
+#define TB0IV_TBCCR5           (0x000A)       /* TB0CCR5_CCIFG */
+#define TB0IV_TBCCR6           (0x000C)       /* TB0CCR6_CCIFG */
+#define TB0IV_TBIFG            (0x000E)       /* TB0IFG */
+
+/* Legacy Defines */
+#define TB0IV_TB0CCR1          (0x0002)       /* TB0CCR1_CCIFG */
+#define TB0IV_TB0CCR2          (0x0004)       /* TB0CCR2_CCIFG */
+#define TB0IV_TB0CCR3          (0x0006)       /* TB0CCR3_CCIFG */
+#define TB0IV_TB0CCR4          (0x0008)       /* TB0CCR4_CCIFG */
+#define TB0IV_TB0CCR5          (0x000A)       /* TB0CCR5_CCIFG */
+#define TB0IV_TB0CCR6          (0x000C)       /* TB0CCR6_CCIFG */
+#define TB0IV_TB0IFG           (0x000E)       /* TB0IFG */
+
+
+/************************************************************
+* USCI A0
+************************************************************/
+#define __MSP430_HAS_EUSCI_A0__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_EUSCI_A0__ 0x05C0
+#define EUSCI_A0_BASE          __MSP430_BASEADDRESS_EUSCI_A0__
+
+sfr_w(UCA0CTLW0);                             /* USCI A0 Control Word Register 0 */
+sfr_b(UCA0CTLW0_L);                           /* USCI A0 Control Word Register 0 */
+sfr_b(UCA0CTLW0_H);                           /* USCI A0 Control Word Register 0 */
+#define UCA0CTL1               UCA0CTLW0_L    /* USCI A0 Control Register 1 */
+#define UCA0CTL0               UCA0CTLW0_H    /* USCI A0 Control Register 0 */
+sfr_w(UCA0CTLW1);                             /* USCI A0 Control Word Register 1 */
+sfr_b(UCA0CTLW1_L);                           /* USCI A0 Control Word Register 1 */
+sfr_b(UCA0CTLW1_H);                           /* USCI A0 Control Word Register 1 */
+sfr_w(UCA0BRW);                               /* USCI A0 Baud Word Rate 0 */
+sfr_b(UCA0BRW_L);                             /* USCI A0 Baud Word Rate 0 */
+sfr_b(UCA0BRW_H);                             /* USCI A0 Baud Word Rate 0 */
+#define UCA0BR0                UCA0BRW_L      /* USCI A0 Baud Rate 0 */
+#define UCA0BR1                UCA0BRW_H      /* USCI A0 Baud Rate 1 */
+sfr_w(UCA0MCTLW);                             /* USCI A0 Modulation Control */
+sfr_b(UCA0MCTLW_L);                           /* USCI A0 Modulation Control */
+sfr_b(UCA0MCTLW_H);                           /* USCI A0 Modulation Control */
+sfr_b(UCA0STATW);                             /* USCI A0 Status Register */
+sfr_w(UCA0RXBUF);                             /* USCI A0 Receive Buffer */
+sfr_b(UCA0RXBUF_L);                           /* USCI A0 Receive Buffer */
+sfr_b(UCA0RXBUF_H);                           /* USCI A0 Receive Buffer */
+sfr_w(UCA0TXBUF);                             /* USCI A0 Transmit Buffer */
+sfr_b(UCA0TXBUF_L);                           /* USCI A0 Transmit Buffer */
+sfr_b(UCA0TXBUF_H);                           /* USCI A0 Transmit Buffer */
+sfr_b(UCA0ABCTL);                             /* USCI A0 LIN Control */
+sfr_w(UCA0IRCTL);                             /* USCI A0 IrDA Transmit Control */
+sfr_b(UCA0IRCTL_L);                           /* USCI A0 IrDA Transmit Control */
+sfr_b(UCA0IRCTL_H);                           /* USCI A0 IrDA Transmit Control */
+#define UCA0IRTCTL             UCA0IRCTL_L    /* USCI A0 IrDA Transmit Control */
+#define UCA0IRRCTL             UCA0IRCTL_H    /* USCI A0 IrDA Receive Control */
+sfr_w(UCA0IE);                                /* USCI A0 Interrupt Enable Register */
+sfr_b(UCA0IE_L);                              /* USCI A0 Interrupt Enable Register */
+sfr_b(UCA0IE_H);                              /* USCI A0 Interrupt Enable Register */
+sfr_w(UCA0IFG);                               /* USCI A0 Interrupt Flags Register */
+sfr_b(UCA0IFG_L);                             /* USCI A0 Interrupt Flags Register */
+sfr_b(UCA0IFG_H);                             /* USCI A0 Interrupt Flags Register */
+sfr_w(UCA0IV);                                /* USCI A0 Interrupt Vector Register */
+
+
+/************************************************************
+* USCI A1
+************************************************************/
+#define __MSP430_HAS_EUSCI_A1__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_EUSCI_A1__ 0x05E0
+#define EUSCI_A1_BASE          __MSP430_BASEADDRESS_EUSCI_A1__
+
+sfr_w(UCA1CTLW0);                             /* USCI A1 Control Word Register 0 */
+sfr_b(UCA1CTLW0_L);                           /* USCI A1 Control Word Register 0 */
+sfr_b(UCA1CTLW0_H);                           /* USCI A1 Control Word Register 0 */
+#define UCA1CTL1               UCA1CTLW0_L    /* USCI A1 Control Register 1 */
+#define UCA1CTL0               UCA1CTLW0_H    /* USCI A1 Control Register 0 */
+sfr_w(UCA1CTLW1);                             /* USCI A1 Control Word Register 1 */
+sfr_b(UCA1CTLW1_L);                           /* USCI A1 Control Word Register 1 */
+sfr_b(UCA1CTLW1_H);                           /* USCI A1 Control Word Register 1 */
+sfr_w(UCA1BRW);                               /* USCI A1 Baud Word Rate 0 */
+sfr_b(UCA1BRW_L);                             /* USCI A1 Baud Word Rate 0 */
+sfr_b(UCA1BRW_H);                             /* USCI A1 Baud Word Rate 0 */
+#define UCA1BR0                UCA1BRW_L      /* USCI A1 Baud Rate 0 */
+#define UCA1BR1                UCA1BRW_H      /* USCI A1 Baud Rate 1 */
+sfr_w(UCA1MCTLW);                             /* USCI A1 Modulation Control */
+sfr_b(UCA1MCTLW_L);                           /* USCI A1 Modulation Control */
+sfr_b(UCA1MCTLW_H);                           /* USCI A1 Modulation Control */
+sfr_b(UCA1STATW);                             /* USCI A1 Status Register */
+sfr_w(UCA1RXBUF);                             /* USCI A1 Receive Buffer */
+sfr_b(UCA1RXBUF_L);                           /* USCI A1 Receive Buffer */
+sfr_b(UCA1RXBUF_H);                           /* USCI A1 Receive Buffer */
+sfr_w(UCA1TXBUF);                             /* USCI A1 Transmit Buffer */
+sfr_b(UCA1TXBUF_L);                           /* USCI A1 Transmit Buffer */
+sfr_b(UCA1TXBUF_H);                           /* USCI A1 Transmit Buffer */
+sfr_b(UCA1ABCTL);                             /* USCI A1 LIN Control */
+sfr_w(UCA1IRCTL);                             /* USCI A1 IrDA Transmit Control */
+sfr_b(UCA1IRCTL_L);                           /* USCI A1 IrDA Transmit Control */
+sfr_b(UCA1IRCTL_H);                           /* USCI A1 IrDA Transmit Control */
+#define UCA1IRTCTL             UCA1IRCTL_L    /* USCI A1 IrDA Transmit Control */
+#define UCA1IRRCTL             UCA1IRCTL_H    /* USCI A1 IrDA Receive Control */
+sfr_w(UCA1IE);                                /* USCI A1 Interrupt Enable Register */
+sfr_b(UCA1IE_L);                              /* USCI A1 Interrupt Enable Register */
+sfr_b(UCA1IE_H);                              /* USCI A1 Interrupt Enable Register */
+sfr_w(UCA1IFG);                               /* USCI A1 Interrupt Flags Register */
+sfr_b(UCA1IFG_L);                             /* USCI A1 Interrupt Flags Register */
+sfr_b(UCA1IFG_H);                             /* USCI A1 Interrupt Flags Register */
+sfr_w(UCA1IV);                                /* USCI A1 Interrupt Vector Register */
+
+
+/************************************************************
+* USCI B0
+************************************************************/
+#define __MSP430_HAS_EUSCI_B0__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_EUSCI_B0__ 0x0640
+#define EUSCI_B0_BASE          __MSP430_BASEADDRESS_EUSCI_B0__
+
+
+sfr_w(UCB0CTLW0);                             /* USCI B0 Control Word Register 0 */
+sfr_b(UCB0CTLW0_L);                           /* USCI B0 Control Word Register 0 */
+sfr_b(UCB0CTLW0_H);                           /* USCI B0 Control Word Register 0 */
+#define UCB0CTL1               UCB0CTLW0_L    /* USCI B0 Control Register 1 */
+#define UCB0CTL0               UCB0CTLW0_H    /* USCI B0 Control Register 0 */
+sfr_w(UCB0CTLW1);                             /* USCI B0 Control Word Register 1 */
+sfr_b(UCB0CTLW1_L);                           /* USCI B0 Control Word Register 1 */
+sfr_b(UCB0CTLW1_H);                           /* USCI B0 Control Word Register 1 */
+sfr_w(UCB0BRW);                               /* USCI B0 Baud Word Rate 0 */
+sfr_b(UCB0BRW_L);                             /* USCI B0 Baud Word Rate 0 */
+sfr_b(UCB0BRW_H);                             /* USCI B0 Baud Word Rate 0 */
+#define UCB0BR0                UCB0BRW_L      /* USCI B0 Baud Rate 0 */
+#define UCB0BR1                UCB0BRW_H      /* USCI B0 Baud Rate 1 */
+sfr_w(UCB0STATW);                             /* USCI B0 Status Word Register */
+sfr_b(UCB0STATW_L);                           /* USCI B0 Status Word Register */
+sfr_b(UCB0STATW_H);                           /* USCI B0 Status Word Register */
+#define UCB0STAT               UCB0STATW_L    /* USCI B0 Status Register */
+#define UCB0BCNT               UCB0STATW_H    /* USCI B0 Byte Counter Register */
+sfr_w(UCB0TBCNT);                             /* USCI B0 Byte Counter Threshold Register */
+sfr_b(UCB0TBCNT_L);                           /* USCI B0 Byte Counter Threshold Register */
+sfr_b(UCB0TBCNT_H);                           /* USCI B0 Byte Counter Threshold Register */
+sfr_w(UCB0RXBUF);                             /* USCI B0 Receive Buffer */
+sfr_b(UCB0RXBUF_L);                           /* USCI B0 Receive Buffer */
+sfr_b(UCB0RXBUF_H);                           /* USCI B0 Receive Buffer */
+sfr_w(UCB0TXBUF);                             /* USCI B0 Transmit Buffer */
+sfr_b(UCB0TXBUF_L);                           /* USCI B0 Transmit Buffer */
+sfr_b(UCB0TXBUF_H);                           /* USCI B0 Transmit Buffer */
+sfr_w(UCB0I2COA0);                            /* USCI B0 I2C Own Address 0 */
+sfr_b(UCB0I2COA0_L);                          /* USCI B0 I2C Own Address 0 */
+sfr_b(UCB0I2COA0_H);                          /* USCI B0 I2C Own Address 0 */
+sfr_w(UCB0I2COA1);                            /* USCI B0 I2C Own Address 1 */
+sfr_b(UCB0I2COA1_L);                          /* USCI B0 I2C Own Address 1 */
+sfr_b(UCB0I2COA1_H);                          /* USCI B0 I2C Own Address 1 */
+sfr_w(UCB0I2COA2);                            /* USCI B0 I2C Own Address 2 */
+sfr_b(UCB0I2COA2_L);                          /* USCI B0 I2C Own Address 2 */
+sfr_b(UCB0I2COA2_H);                          /* USCI B0 I2C Own Address 2 */
+sfr_w(UCB0I2COA3);                            /* USCI B0 I2C Own Address 3 */
+sfr_b(UCB0I2COA3_L);                          /* USCI B0 I2C Own Address 3 */
+sfr_b(UCB0I2COA3_H);                          /* USCI B0 I2C Own Address 3 */
+sfr_w(UCB0ADDRX);                             /* USCI B0 Received Address Register */
+sfr_b(UCB0ADDRX_L);                           /* USCI B0 Received Address Register */
+sfr_b(UCB0ADDRX_H);                           /* USCI B0 Received Address Register */
+sfr_w(UCB0ADDMASK);                           /* USCI B0 Address Mask Register */
+sfr_b(UCB0ADDMASK_L);                         /* USCI B0 Address Mask Register */
+sfr_b(UCB0ADDMASK_H);                         /* USCI B0 Address Mask Register */
+sfr_w(UCB0I2CSA);                             /* USCI B0 I2C Slave Address */
+sfr_b(UCB0I2CSA_L);                           /* USCI B0 I2C Slave Address */
+sfr_b(UCB0I2CSA_H);                           /* USCI B0 I2C Slave Address */
+sfr_w(UCB0IE);                                /* USCI B0 Interrupt Enable Register */
+sfr_b(UCB0IE_L);                              /* USCI B0 Interrupt Enable Register */
+sfr_b(UCB0IE_H);                              /* USCI B0 Interrupt Enable Register */
+sfr_w(UCB0IFG);                               /* USCI B0 Interrupt Flags Register */
+sfr_b(UCB0IFG_L);                             /* USCI B0 Interrupt Flags Register */
+sfr_b(UCB0IFG_H);                             /* USCI B0 Interrupt Flags Register */
+sfr_w(UCB0IV);                                /* USCI B0 Interrupt Vector Register */
+
+// UCAxCTLW0 UART-Mode Control Bits
+#define UCPEN                  (0x8000)       /* Async. Mode: Parity enable */
+#define UCPAR                  (0x4000)       /* Async. Mode: Parity     0:odd / 1:even */
+#define UCMSB                  (0x2000)       /* Async. Mode: MSB first  0:LSB / 1:MSB */
+#define UC7BIT                 (0x1000)       /* Async. Mode: Data Bits  0:8-bits / 1:7-bits */
+#define UCSPB                  (0x0800)       /* Async. Mode: Stop Bits  0:one / 1: two */
+#define UCMODE1                (0x0400)       /* Async. Mode: USCI Mode 1 */
+#define UCMODE0                (0x0200)       /* Async. Mode: USCI Mode 0 */
+#define UCSYNC                 (0x0100)       /* Sync-Mode  0:UART-Mode / 1:SPI-Mode */
+#define UCSSEL1                (0x0080)       /* USCI 0 Clock Source Select 1 */
+#define UCSSEL0                (0x0040)       /* USCI 0 Clock Source Select 0 */
+#define UCRXEIE                (0x0020)       /* RX Error interrupt enable */
+#define UCBRKIE                (0x0010)       /* Break interrupt enable */
+#define UCDORM                 (0x0008)       /* Dormant (Sleep) Mode */
+#define UCTXADDR               (0x0004)       /* Send next Data as Address */
+#define UCTXBRK                (0x0002)       /* Send next Data as Break */
+#define UCSWRST                (0x0001)       /* USCI Software Reset */
+
+// UCAxCTLW0 UART-Mode Control Bits
+#define UCSSEL1_L              (0x0080)       /* USCI 0 Clock Source Select 1 */
+#define UCSSEL0_L              (0x0040)       /* USCI 0 Clock Source Select 0 */
+#define UCRXEIE_L              (0x0020)       /* RX Error interrupt enable */
+#define UCBRKIE_L              (0x0010)       /* Break interrupt enable */
+#define UCDORM_L               (0x0008)       /* Dormant (Sleep) Mode */
+#define UCTXADDR_L             (0x0004)       /* Send next Data as Address */
+#define UCTXBRK_L              (0x0002)       /* Send next Data as Break */
+#define UCSWRST_L              (0x0001)       /* USCI Software Reset */
+
+// UCAxCTLW0 UART-Mode Control Bits
+#define UCPEN_H                (0x0080)       /* Async. Mode: Parity enable */
+#define UCPAR_H                (0x0040)       /* Async. Mode: Parity     0:odd / 1:even */
+#define UCMSB_H                (0x0020)       /* Async. Mode: MSB first  0:LSB / 1:MSB */
+#define UC7BIT_H               (0x0010)       /* Async. Mode: Data Bits  0:8-bits / 1:7-bits */
+#define UCSPB_H                (0x0008)       /* Async. Mode: Stop Bits  0:one / 1: two */
+#define UCMODE1_H              (0x0004)       /* Async. Mode: USCI Mode 1 */
+#define UCMODE0_H              (0x0002)       /* Async. Mode: USCI Mode 0 */
+#define UCSYNC_H               (0x0001)       /* Sync-Mode  0:UART-Mode / 1:SPI-Mode */
+
+// UCxxCTLW0 SPI-Mode Control Bits
+#define UCCKPH                 (0x8000)       /* Sync. Mode: Clock Phase */
+#define UCCKPL                 (0x4000)       /* Sync. Mode: Clock Polarity */
+#define UCMST                  (0x0800)       /* Sync. Mode: Master Select */
+//#define res               (0x0020)    /* reserved */
+//#define res               (0x0010)    /* reserved */
+//#define res               (0x0008)    /* reserved */
+//#define res               (0x0004)    /* reserved */
+#define UCSTEM                 (0x0002)       /* USCI STE Mode */
+
+// UCBxCTLW0 I2C-Mode Control Bits
+#define UCA10                  (0x8000)       /* 10-bit Address Mode */
+#define UCSLA10                (0x4000)       /* 10-bit Slave Address Mode */
+#define UCMM                   (0x2000)       /* Multi-Master Environment */
+//#define res               (0x1000)    /* reserved */
+//#define res               (0x0100)    /* reserved */
+#define UCTXACK                (0x0020)       /* Transmit ACK */
+#define UCTR                   (0x0010)       /* Transmit/Receive Select/Flag */
+#define UCTXNACK               (0x0008)       /* Transmit NACK */
+#define UCTXSTP                (0x0004)       /* Transmit STOP */
+#define UCTXSTT                (0x0002)       /* Transmit START */
+
+// UCBxCTLW0 I2C-Mode Control Bits
+//#define res               (0x1000)    /* reserved */
+//#define res               (0x0100)    /* reserved */
+#define UCTXACK_L              (0x0020)       /* Transmit ACK */
+#define UCTR_L                 (0x0010)       /* Transmit/Receive Select/Flag */
+#define UCTXNACK_L             (0x0008)       /* Transmit NACK */
+#define UCTXSTP_L              (0x0004)       /* Transmit STOP */
+#define UCTXSTT_L              (0x0002)       /* Transmit START */
+
+// UCBxCTLW0 I2C-Mode Control Bits
+#define UCA10_H                (0x0080)       /* 10-bit Address Mode */
+#define UCSLA10_H              (0x0040)       /* 10-bit Slave Address Mode */
+#define UCMM_H                 (0x0020)       /* Multi-Master Environment */
+//#define res               (0x1000)    /* reserved */
+//#define res               (0x0100)    /* reserved */
+
+#define UCMODE_0               (0x0000)       /* Sync. Mode: USCI Mode: 0 */
+#define UCMODE_1               (0x0200)       /* Sync. Mode: USCI Mode: 1 */
+#define UCMODE_2               (0x0400)       /* Sync. Mode: USCI Mode: 2 */
+#define UCMODE_3               (0x0600)       /* Sync. Mode: USCI Mode: 3 */
+
+#define UCSSEL_0               (0x0000)       /* USCI 0 Clock Source: 0 */
+#define UCSSEL_1               (0x0040)       /* USCI 0 Clock Source: 1 */
+#define UCSSEL_2               (0x0080)       /* USCI 0 Clock Source: 2 */
+#define UCSSEL_3               (0x00C0)       /* USCI 0 Clock Source: 3 */
+#define UCSSEL__UCLK           (0x0000)       /* USCI 0 Clock Source: UCLK */
+#define UCSSEL__ACLK           (0x0040)       /* USCI 0 Clock Source: ACLK */
+#define UCSSEL__SMCLK          (0x0080)       /* USCI 0 Clock Source: SMCLK */
+
+// UCAxCTLW1 UART-Mode Control Bits
+#define UCGLIT1                (0x0002)       /* USCI Deglitch Time Bit 1 */
+#define UCGLIT0                (0x0001)       /* USCI Deglitch Time Bit 0 */
+
+// UCAxCTLW1 UART-Mode Control Bits
+#define UCGLIT1_L              (0x0002)       /* USCI Deglitch Time Bit 1 */
+#define UCGLIT0_L              (0x0001)       /* USCI Deglitch Time Bit 0 */
+
+// UCBxCTLW1 I2C-Mode Control Bits
+#define UCETXINT               (0x0100)       /* USCI Early UCTXIFG0 */
+#define UCCLTO1                (0x0080)       /* USCI Clock low timeout Bit: 1 */
+#define UCCLTO0                (0x0040)       /* USCI Clock low timeout Bit: 0 */
+#define UCSTPNACK              (0x0020)       /* USCI Acknowledge Stop last byte */
+#define UCSWACK                (0x0010)       /* USCI Software controlled ACK */
+#define UCASTP1                (0x0008)       /* USCI Automatic Stop condition generation Bit: 1 */
+#define UCASTP0                (0x0004)       /* USCI Automatic Stop condition generation Bit: 0 */
+#define UCGLIT1                (0x0002)       /* USCI Deglitch time Bit: 1 */
+#define UCGLIT0                (0x0001)       /* USCI Deglitch time Bit: 0 */
+
+// UCBxCTLW1 I2C-Mode Control Bits
+#define UCCLTO1_L              (0x0080)       /* USCI Clock low timeout Bit: 1 */
+#define UCCLTO0_L              (0x0040)       /* USCI Clock low timeout Bit: 0 */
+#define UCSTPNACK_L            (0x0020)       /* USCI Acknowledge Stop last byte */
+#define UCSWACK_L              (0x0010)       /* USCI Software controlled ACK */
+#define UCASTP1_L              (0x0008)       /* USCI Automatic Stop condition generation Bit: 1 */
+#define UCASTP0_L              (0x0004)       /* USCI Automatic Stop condition generation Bit: 0 */
+#define UCGLIT1_L              (0x0002)       /* USCI Deglitch time Bit: 1 */
+#define UCGLIT0_L              (0x0001)       /* USCI Deglitch time Bit: 0 */
+
+// UCBxCTLW1 I2C-Mode Control Bits
+#define UCETXINT_H             (0x0001)       /* USCI Early UCTXIFG0 */
+
+#define UCGLIT_0               (0x0000)       /* USCI Deglitch time: 0 */
+#define UCGLIT_1               (0x0001)       /* USCI Deglitch time: 1 */
+#define UCGLIT_2               (0x0002)       /* USCI Deglitch time: 2 */
+#define UCGLIT_3               (0x0003)       /* USCI Deglitch time: 3 */
+
+#define UCASTP_0               (0x0000)       /* USCI Automatic Stop condition generation: 0 */
+#define UCASTP_1               (0x0004)       /* USCI Automatic Stop condition generation: 1 */
+#define UCASTP_2               (0x0008)       /* USCI Automatic Stop condition generation: 2 */
+#define UCASTP_3               (0x000C)       /* USCI Automatic Stop condition generation: 3 */
+
+#define UCCLTO_0               (0x0000)       /* USCI Clock low timeout: 0 */
+#define UCCLTO_1               (0x0040)       /* USCI Clock low timeout: 1 */
+#define UCCLTO_2               (0x0080)       /* USCI Clock low timeout: 2 */
+#define UCCLTO_3               (0x00C0)       /* USCI Clock low timeout: 3 */
+
+/* UCAxMCTLW Control Bits */
+#define UCBRS7                 (0x8000)       /* USCI Second Stage Modulation Select 7 */
+#define UCBRS6                 (0x4000)       /* USCI Second Stage Modulation Select 6 */
+#define UCBRS5                 (0x2000)       /* USCI Second Stage Modulation Select 5 */
+#define UCBRS4                 (0x1000)       /* USCI Second Stage Modulation Select 4 */
+#define UCBRS3                 (0x0800)       /* USCI Second Stage Modulation Select 3 */
+#define UCBRS2                 (0x0400)       /* USCI Second Stage Modulation Select 2 */
+#define UCBRS1                 (0x0200)       /* USCI Second Stage Modulation Select 1 */
+#define UCBRS0                 (0x0100)       /* USCI Second Stage Modulation Select 0 */
+#define UCBRF3                 (0x0080)       /* USCI First Stage Modulation Select 3 */
+#define UCBRF2                 (0x0040)       /* USCI First Stage Modulation Select 2 */
+#define UCBRF1                 (0x0020)       /* USCI First Stage Modulation Select 1 */
+#define UCBRF0                 (0x0010)       /* USCI First Stage Modulation Select 0 */
+#define UCOS16                 (0x0001)       /* USCI 16-times Oversampling enable */
+
+/* UCAxMCTLW Control Bits */
+#define UCBRF3_L               (0x0080)       /* USCI First Stage Modulation Select 3 */
+#define UCBRF2_L               (0x0040)       /* USCI First Stage Modulation Select 2 */
+#define UCBRF1_L               (0x0020)       /* USCI First Stage Modulation Select 1 */
+#define UCBRF0_L               (0x0010)       /* USCI First Stage Modulation Select 0 */
+#define UCOS16_L               (0x0001)       /* USCI 16-times Oversampling enable */
+
+/* UCAxMCTLW Control Bits */
+#define UCBRS7_H               (0x0080)       /* USCI Second Stage Modulation Select 7 */
+#define UCBRS6_H               (0x0040)       /* USCI Second Stage Modulation Select 6 */
+#define UCBRS5_H               (0x0020)       /* USCI Second Stage Modulation Select 5 */
+#define UCBRS4_H               (0x0010)       /* USCI Second Stage Modulation Select 4 */
+#define UCBRS3_H               (0x0008)       /* USCI Second Stage Modulation Select 3 */
+#define UCBRS2_H               (0x0004)       /* USCI Second Stage Modulation Select 2 */
+#define UCBRS1_H               (0x0002)       /* USCI Second Stage Modulation Select 1 */
+#define UCBRS0_H               (0x0001)       /* USCI Second Stage Modulation Select 0 */
+
+#define UCBRF_0                (0x00)         /* USCI First Stage Modulation: 0 */
+#define UCBRF_1                (0x10)         /* USCI First Stage Modulation: 1 */
+#define UCBRF_2                (0x20)         /* USCI First Stage Modulation: 2 */
+#define UCBRF_3                (0x30)         /* USCI First Stage Modulation: 3 */
+#define UCBRF_4                (0x40)         /* USCI First Stage Modulation: 4 */
+#define UCBRF_5                (0x50)         /* USCI First Stage Modulation: 5 */
+#define UCBRF_6                (0x60)         /* USCI First Stage Modulation: 6 */
+#define UCBRF_7                (0x70)         /* USCI First Stage Modulation: 7 */
+#define UCBRF_8                (0x80)         /* USCI First Stage Modulation: 8 */
+#define UCBRF_9                (0x90)         /* USCI First Stage Modulation: 9 */
+#define UCBRF_10               (0xA0)         /* USCI First Stage Modulation: A */
+#define UCBRF_11               (0xB0)         /* USCI First Stage Modulation: B */
+#define UCBRF_12               (0xC0)         /* USCI First Stage Modulation: C */
+#define UCBRF_13               (0xD0)         /* USCI First Stage Modulation: D */
+#define UCBRF_14               (0xE0)         /* USCI First Stage Modulation: E */
+#define UCBRF_15               (0xF0)         /* USCI First Stage Modulation: F */
+
+/* UCAxSTATW Control Bits */
+#define UCLISTEN               (0x0080)       /* USCI Listen mode */
+#define UCFE                   (0x0040)       /* USCI Frame Error Flag */
+#define UCOE                   (0x0020)       /* USCI Overrun Error Flag */
+#define UCPE                   (0x0010)       /* USCI Parity Error Flag */
+#define UCBRK                  (0x0008)       /* USCI Break received */
+#define UCRXERR                (0x0004)       /* USCI RX Error Flag */
+#define UCADDR                 (0x0002)       /* USCI Address received Flag */
+#define UCBUSY                 (0x0001)       /* USCI Busy Flag */
+#define UCIDLE                 (0x0002)       /* USCI Idle line detected Flag */
+
+/* UCBxSTATW I2C Control Bits */
+#define UCBCNT7                (0x8000)       /* USCI Byte Counter Bit 7 */
+#define UCBCNT6                (0x4000)       /* USCI Byte Counter Bit 6 */
+#define UCBCNT5                (0x2000)       /* USCI Byte Counter Bit 5 */
+#define UCBCNT4                (0x1000)       /* USCI Byte Counter Bit 4 */
+#define UCBCNT3                (0x0800)       /* USCI Byte Counter Bit 3 */
+#define UCBCNT2                (0x0400)       /* USCI Byte Counter Bit 2 */
+#define UCBCNT1                (0x0200)       /* USCI Byte Counter Bit 1 */
+#define UCBCNT0                (0x0100)       /* USCI Byte Counter Bit 0 */
+#define UCSCLLOW               (0x0040)       /* SCL low */
+#define UCGC                   (0x0020)       /* General Call address received Flag */
+#define UCBBUSY                (0x0010)       /* Bus Busy Flag */
+
+/* UCBxTBCNT I2C Control Bits */
+#define UCTBCNT7               (0x0080)       /* USCI Byte Counter Bit 7 */
+#define UCTBCNT6               (0x0040)       /* USCI Byte Counter Bit 6 */
+#define UCTBCNT5               (0x0020)       /* USCI Byte Counter Bit 5 */
+#define UCTBCNT4               (0x0010)       /* USCI Byte Counter Bit 4 */
+#define UCTBCNT3               (0x0008)       /* USCI Byte Counter Bit 3 */
+#define UCTBCNT2               (0x0004)       /* USCI Byte Counter Bit 2 */
+#define UCTBCNT1               (0x0002)       /* USCI Byte Counter Bit 1 */
+#define UCTBCNT0               (0x0001)       /* USCI Byte Counter Bit 0 */
+
+/* UCAxIRCTL Control Bits */
+#define UCIRRXFL5              (0x8000)       /* IRDA Receive Filter Length 5 */
+#define UCIRRXFL4              (0x4000)       /* IRDA Receive Filter Length 4 */
+#define UCIRRXFL3              (0x2000)       /* IRDA Receive Filter Length 3 */
+#define UCIRRXFL2              (0x1000)       /* IRDA Receive Filter Length 2 */
+#define UCIRRXFL1              (0x0800)       /* IRDA Receive Filter Length 1 */
+#define UCIRRXFL0              (0x0400)       /* IRDA Receive Filter Length 0 */
+#define UCIRRXPL               (0x0200)       /* IRDA Receive Input Polarity */
+#define UCIRRXFE               (0x0100)       /* IRDA Receive Filter enable */
+#define UCIRTXPL5              (0x0080)       /* IRDA Transmit Pulse Length 5 */
+#define UCIRTXPL4              (0x0040)       /* IRDA Transmit Pulse Length 4 */
+#define UCIRTXPL3              (0x0020)       /* IRDA Transmit Pulse Length 3 */
+#define UCIRTXPL2              (0x0010)       /* IRDA Transmit Pulse Length 2 */
+#define UCIRTXPL1              (0x0008)       /* IRDA Transmit Pulse Length 1 */
+#define UCIRTXPL0              (0x0004)       /* IRDA Transmit Pulse Length 0 */
+#define UCIRTXCLK              (0x0002)       /* IRDA Transmit Pulse Clock Select */
+#define UCIREN                 (0x0001)       /* IRDA Encoder/Decoder enable */
+
+/* UCAxIRCTL Control Bits */
+#define UCIRTXPL5_L            (0x0080)       /* IRDA Transmit Pulse Length 5 */
+#define UCIRTXPL4_L            (0x0040)       /* IRDA Transmit Pulse Length 4 */
+#define UCIRTXPL3_L            (0x0020)       /* IRDA Transmit Pulse Length 3 */
+#define UCIRTXPL2_L            (0x0010)       /* IRDA Transmit Pulse Length 2 */
+#define UCIRTXPL1_L            (0x0008)       /* IRDA Transmit Pulse Length 1 */
+#define UCIRTXPL0_L            (0x0004)       /* IRDA Transmit Pulse Length 0 */
+#define UCIRTXCLK_L            (0x0002)       /* IRDA Transmit Pulse Clock Select */
+#define UCIREN_L               (0x0001)       /* IRDA Encoder/Decoder enable */
+
+/* UCAxIRCTL Control Bits */
+#define UCIRRXFL5_H            (0x0080)       /* IRDA Receive Filter Length 5 */
+#define UCIRRXFL4_H            (0x0040)       /* IRDA Receive Filter Length 4 */
+#define UCIRRXFL3_H            (0x0020)       /* IRDA Receive Filter Length 3 */
+#define UCIRRXFL2_H            (0x0010)       /* IRDA Receive Filter Length 2 */
+#define UCIRRXFL1_H            (0x0008)       /* IRDA Receive Filter Length 1 */
+#define UCIRRXFL0_H            (0x0004)       /* IRDA Receive Filter Length 0 */
+#define UCIRRXPL_H             (0x0002)       /* IRDA Receive Input Polarity */
+#define UCIRRXFE_H             (0x0001)       /* IRDA Receive Filter enable */
+
+/* UCAxABCTL Control Bits */
+//#define res               (0x80)    /* reserved */
+//#define res               (0x40)    /* reserved */
+#define UCDELIM1               (0x20)         /* Break Sync Delimiter 1 */
+#define UCDELIM0               (0x10)         /* Break Sync Delimiter 0 */
+#define UCSTOE                 (0x08)         /* Sync-Field Timeout error */
+#define UCBTOE                 (0x04)         /* Break Timeout error */
+//#define res               (0x02)    /* reserved */
+#define UCABDEN                (0x01)         /* Auto Baud Rate detect enable */
+
+/* UCBxI2COA0 Control Bits */
+#define UCGCEN                 (0x8000)       /* I2C General Call enable */
+#define UCOAEN                 (0x0400)       /* I2C Own Address enable */
+#define UCOA9                  (0x0200)       /* I2C Own Address Bit 9 */
+#define UCOA8                  (0x0100)       /* I2C Own Address Bit 8 */
+#define UCOA7                  (0x0080)       /* I2C Own Address Bit 7 */
+#define UCOA6                  (0x0040)       /* I2C Own Address Bit 6 */
+#define UCOA5                  (0x0020)       /* I2C Own Address Bit 5 */
+#define UCOA4                  (0x0010)       /* I2C Own Address Bit 4 */
+#define UCOA3                  (0x0008)       /* I2C Own Address Bit 3 */
+#define UCOA2                  (0x0004)       /* I2C Own Address Bit 2 */
+#define UCOA1                  (0x0002)       /* I2C Own Address Bit 1 */
+#define UCOA0                  (0x0001)       /* I2C Own Address Bit 0 */
+
+/* UCBxI2COA0 Control Bits */
+#define UCOA7_L                (0x0080)       /* I2C Own Address Bit 7 */
+#define UCOA6_L                (0x0040)       /* I2C Own Address Bit 6 */
+#define UCOA5_L                (0x0020)       /* I2C Own Address Bit 5 */
+#define UCOA4_L                (0x0010)       /* I2C Own Address Bit 4 */
+#define UCOA3_L                (0x0008)       /* I2C Own Address Bit 3 */
+#define UCOA2_L                (0x0004)       /* I2C Own Address Bit 2 */
+#define UCOA1_L                (0x0002)       /* I2C Own Address Bit 1 */
+#define UCOA0_L                (0x0001)       /* I2C Own Address Bit 0 */
+
+/* UCBxI2COA0 Control Bits */
+#define UCGCEN_H               (0x0080)       /* I2C General Call enable */
+#define UCOAEN_H               (0x0004)       /* I2C Own Address enable */
+#define UCOA9_H                (0x0002)       /* I2C Own Address Bit 9 */
+#define UCOA8_H                (0x0001)       /* I2C Own Address Bit 8 */
+
+/* UCBxI2COAx Control Bits */
+#define UCOAEN                 (0x0400)       /* I2C Own Address enable */
+#define UCOA9                  (0x0200)       /* I2C Own Address Bit 9 */
+#define UCOA8                  (0x0100)       /* I2C Own Address Bit 8 */
+#define UCOA7                  (0x0080)       /* I2C Own Address Bit 7 */
+#define UCOA6                  (0x0040)       /* I2C Own Address Bit 6 */
+#define UCOA5                  (0x0020)       /* I2C Own Address Bit 5 */
+#define UCOA4                  (0x0010)       /* I2C Own Address Bit 4 */
+#define UCOA3                  (0x0008)       /* I2C Own Address Bit 3 */
+#define UCOA2                  (0x0004)       /* I2C Own Address Bit 2 */
+#define UCOA1                  (0x0002)       /* I2C Own Address Bit 1 */
+#define UCOA0                  (0x0001)       /* I2C Own Address Bit 0 */
+
+/* UCBxI2COAx Control Bits */
+#define UCOA7_L                (0x0080)       /* I2C Own Address Bit 7 */
+#define UCOA6_L                (0x0040)       /* I2C Own Address Bit 6 */
+#define UCOA5_L                (0x0020)       /* I2C Own Address Bit 5 */
+#define UCOA4_L                (0x0010)       /* I2C Own Address Bit 4 */
+#define UCOA3_L                (0x0008)       /* I2C Own Address Bit 3 */
+#define UCOA2_L                (0x0004)       /* I2C Own Address Bit 2 */
+#define UCOA1_L                (0x0002)       /* I2C Own Address Bit 1 */
+#define UCOA0_L                (0x0001)       /* I2C Own Address Bit 0 */
+
+/* UCBxI2COAx Control Bits */
+#define UCOAEN_H               (0x0004)       /* I2C Own Address enable */
+#define UCOA9_H                (0x0002)       /* I2C Own Address Bit 9 */
+#define UCOA8_H                (0x0001)       /* I2C Own Address Bit 8 */
+
+/* UCBxADDRX Control Bits */
+#define UCADDRX9               (0x0200)       /* I2C Receive Address Bit 9 */
+#define UCADDRX8               (0x0100)       /* I2C Receive Address Bit 8 */
+#define UCADDRX7               (0x0080)       /* I2C Receive Address Bit 7 */
+#define UCADDRX6               (0x0040)       /* I2C Receive Address Bit 6 */
+#define UCADDRX5               (0x0020)       /* I2C Receive Address Bit 5 */
+#define UCADDRX4               (0x0010)       /* I2C Receive Address Bit 4 */
+#define UCADDRX3               (0x0008)       /* I2C Receive Address Bit 3 */
+#define UCADDRX2               (0x0004)       /* I2C Receive Address Bit 2 */
+#define UCADDRX1               (0x0002)       /* I2C Receive Address Bit 1 */
+#define UCADDRX0               (0x0001)       /* I2C Receive Address Bit 0 */
+
+/* UCBxADDRX Control Bits */
+#define UCADDRX7_L             (0x0080)       /* I2C Receive Address Bit 7 */
+#define UCADDRX6_L             (0x0040)       /* I2C Receive Address Bit 6 */
+#define UCADDRX5_L             (0x0020)       /* I2C Receive Address Bit 5 */
+#define UCADDRX4_L             (0x0010)       /* I2C Receive Address Bit 4 */
+#define UCADDRX3_L             (0x0008)       /* I2C Receive Address Bit 3 */
+#define UCADDRX2_L             (0x0004)       /* I2C Receive Address Bit 2 */
+#define UCADDRX1_L             (0x0002)       /* I2C Receive Address Bit 1 */
+#define UCADDRX0_L             (0x0001)       /* I2C Receive Address Bit 0 */
+
+/* UCBxADDRX Control Bits */
+#define UCADDRX9_H             (0x0002)       /* I2C Receive Address Bit 9 */
+#define UCADDRX8_H             (0x0001)       /* I2C Receive Address Bit 8 */
+
+/* UCBxADDMASK Control Bits */
+#define UCADDMASK9             (0x0200)       /* I2C Address Mask Bit 9 */
+#define UCADDMASK8             (0x0100)       /* I2C Address Mask Bit 8 */
+#define UCADDMASK7             (0x0080)       /* I2C Address Mask Bit 7 */
+#define UCADDMASK6             (0x0040)       /* I2C Address Mask Bit 6 */
+#define UCADDMASK5             (0x0020)       /* I2C Address Mask Bit 5 */
+#define UCADDMASK4             (0x0010)       /* I2C Address Mask Bit 4 */
+#define UCADDMASK3             (0x0008)       /* I2C Address Mask Bit 3 */
+#define UCADDMASK2             (0x0004)       /* I2C Address Mask Bit 2 */
+#define UCADDMASK1             (0x0002)       /* I2C Address Mask Bit 1 */
+#define UCADDMASK0             (0x0001)       /* I2C Address Mask Bit 0 */
+
+/* UCBxADDMASK Control Bits */
+#define UCADDMASK7_L           (0x0080)       /* I2C Address Mask Bit 7 */
+#define UCADDMASK6_L           (0x0040)       /* I2C Address Mask Bit 6 */
+#define UCADDMASK5_L           (0x0020)       /* I2C Address Mask Bit 5 */
+#define UCADDMASK4_L           (0x0010)       /* I2C Address Mask Bit 4 */
+#define UCADDMASK3_L           (0x0008)       /* I2C Address Mask Bit 3 */
+#define UCADDMASK2_L           (0x0004)       /* I2C Address Mask Bit 2 */
+#define UCADDMASK1_L           (0x0002)       /* I2C Address Mask Bit 1 */
+#define UCADDMASK0_L           (0x0001)       /* I2C Address Mask Bit 0 */
+
+/* UCBxADDMASK Control Bits */
+#define UCADDMASK9_H           (0x0002)       /* I2C Address Mask Bit 9 */
+#define UCADDMASK8_H           (0x0001)       /* I2C Address Mask Bit 8 */
+
+/* UCBxI2CSA Control Bits */
+#define UCSA9                  (0x0200)       /* I2C Slave Address Bit 9 */
+#define UCSA8                  (0x0100)       /* I2C Slave Address Bit 8 */
+#define UCSA7                  (0x0080)       /* I2C Slave Address Bit 7 */
+#define UCSA6                  (0x0040)       /* I2C Slave Address Bit 6 */
+#define UCSA5                  (0x0020)       /* I2C Slave Address Bit 5 */
+#define UCSA4                  (0x0010)       /* I2C Slave Address Bit 4 */
+#define UCSA3                  (0x0008)       /* I2C Slave Address Bit 3 */
+#define UCSA2                  (0x0004)       /* I2C Slave Address Bit 2 */
+#define UCSA1                  (0x0002)       /* I2C Slave Address Bit 1 */
+#define UCSA0                  (0x0001)       /* I2C Slave Address Bit 0 */
+
+/* UCBxI2CSA Control Bits */
+#define UCSA7_L                (0x0080)       /* I2C Slave Address Bit 7 */
+#define UCSA6_L                (0x0040)       /* I2C Slave Address Bit 6 */
+#define UCSA5_L                (0x0020)       /* I2C Slave Address Bit 5 */
+#define UCSA4_L                (0x0010)       /* I2C Slave Address Bit 4 */
+#define UCSA3_L                (0x0008)       /* I2C Slave Address Bit 3 */
+#define UCSA2_L                (0x0004)       /* I2C Slave Address Bit 2 */
+#define UCSA1_L                (0x0002)       /* I2C Slave Address Bit 1 */
+#define UCSA0_L                (0x0001)       /* I2C Slave Address Bit 0 */
+
+/* UCBxI2CSA Control Bits */
+#define UCSA9_H                (0x0002)       /* I2C Slave Address Bit 9 */
+#define UCSA8_H                (0x0001)       /* I2C Slave Address Bit 8 */
+
+/* UCAxIE UART Control Bits */
+#define UCTXCPTIE              (0x0008)       /* UART Transmit Complete Interrupt Enable */
+#define UCSTTIE                (0x0004)       /* UART Start Bit Interrupt Enalble */
+#define UCTXIE                 (0x0002)       /* UART Transmit Interrupt Enable */
+#define UCRXIE                 (0x0001)       /* UART Receive Interrupt Enable */
+
+/* UCAxIE/UCBxIE SPI Control Bits */
+
+/* UCBxIE I2C Control Bits */
+#define UCBIT9IE               (0x4000)       /* I2C Bit 9 Position Interrupt Enable 3 */
+#define UCTXIE3                (0x2000)       /* I2C Transmit Interrupt Enable 3 */
+#define UCRXIE3                (0x1000)       /* I2C Receive Interrupt Enable 3 */
+#define UCTXIE2                (0x0800)       /* I2C Transmit Interrupt Enable 2 */
+#define UCRXIE2                (0x0400)       /* I2C Receive Interrupt Enable 2 */
+#define UCTXIE1                (0x0200)       /* I2C Transmit Interrupt Enable 1 */
+#define UCRXIE1                (0x0100)       /* I2C Receive Interrupt Enable 1 */
+#define UCCLTOIE               (0x0080)       /* I2C Clock Low Timeout interrupt enable */
+#define UCBCNTIE               (0x0040)       /* I2C Automatic stop assertion interrupt enable */
+#define UCNACKIE               (0x0020)       /* I2C NACK Condition interrupt enable */
+#define UCALIE                 (0x0010)       /* I2C Arbitration Lost interrupt enable */
+#define UCSTPIE                (0x0008)       /* I2C STOP Condition interrupt enable */
+#define UCSTTIE                (0x0004)       /* I2C START Condition interrupt enable */
+#define UCTXIE0                (0x0002)       /* I2C Transmit Interrupt Enable 0 */
+#define UCRXIE0                (0x0001)       /* I2C Receive Interrupt Enable 0 */
+
+/* UCAxIFG UART Control Bits */
+#define UCTXCPTIFG             (0x0008)       /* UART Transmit Complete Interrupt Flag */
+#define UCSTTIFG               (0x0004)       /* UART Start Bit Interrupt Flag */
+#define UCTXIFG                (0x0002)       /* UART Transmit Interrupt Flag */
+#define UCRXIFG                (0x0001)       /* UART Receive Interrupt Flag */
+
+/* UCAxIFG/UCBxIFG SPI Control Bits */
+#define UCTXIFG                (0x0002)       /* SPI Transmit Interrupt Flag */
+#define UCRXIFG                (0x0001)       /* SPI Receive Interrupt Flag */
+
+/* UCBxIFG Control Bits */
+#define UCBIT9IFG              (0x4000)       /* I2C Bit 9 Possition Interrupt Flag 3 */
+#define UCTXIFG3               (0x2000)       /* I2C Transmit Interrupt Flag 3 */
+#define UCRXIFG3               (0x1000)       /* I2C Receive Interrupt Flag 3 */
+#define UCTXIFG2               (0x0800)       /* I2C Transmit Interrupt Flag 2 */
+#define UCRXIFG2               (0x0400)       /* I2C Receive Interrupt Flag 2 */
+#define UCTXIFG1               (0x0200)       /* I2C Transmit Interrupt Flag 1 */
+#define UCRXIFG1               (0x0100)       /* I2C Receive Interrupt Flag 1 */
+#define UCCLTOIFG              (0x0080)       /* I2C Clock low Timeout interrupt Flag */
+#define UCBCNTIFG              (0x0040)       /* I2C Byte counter interrupt flag */
+#define UCNACKIFG              (0x0020)       /* I2C NACK Condition interrupt Flag */
+#define UCALIFG                (0x0010)       /* I2C Arbitration Lost interrupt Flag */
+#define UCSTPIFG               (0x0008)       /* I2C STOP Condition interrupt Flag */
+#define UCSTTIFG               (0x0004)       /* I2C START Condition interrupt Flag */
+#define UCTXIFG0               (0x0002)       /* I2C Transmit Interrupt Flag 0 */
+#define UCRXIFG0               (0x0001)       /* I2C Receive Interrupt Flag 0 */
+
+/* USCI Interrupt Vector UART Definitions */
+#define USCI_NONE              (0x0000)       /* No Interrupt pending */
+#define USCI_UART_UCRXIFG      (0x0002)       /* Interrupt Vector: UCRXIFG */
+#define USCI_UART_UCTXIFG      (0x0004)       /* Interrupt Vector: UCTXIFG */
+#define USCI_UART_UCSTTIFG     (0x0006)       /* Interrupt Vector: UCSTTIFG */
+#define USCI_UART_UCTXCPTIFG   (0x0008)       /* Interrupt Vector: UCTXCPTIFG */
+
+/* USCI Interrupt Vector SPI Definitions */
+#define USCI_SPI_UCRXIFG       (0x0002)       /* Interrupt Vector: UCRXIFG */
+#define USCI_SPI_UCTXIFG       (0x0004)       /* Interrupt Vector: UCTXIFG */
+
+/* USCI Interrupt Vector I2C Definitions */
+#define USCI_I2C_UCALIFG       (0x0002)       /* Interrupt Vector: I2C Mode: UCALIFG */
+#define USCI_I2C_UCNACKIFG     (0x0004)       /* Interrupt Vector: I2C Mode: UCNACKIFG */
+#define USCI_I2C_UCSTTIFG      (0x0006)       /* Interrupt Vector: I2C Mode: UCSTTIFG*/
+#define USCI_I2C_UCSTPIFG      (0x0008)       /* Interrupt Vector: I2C Mode: UCSTPIFG*/
+#define USCI_I2C_UCRXIFG3      (0x000A)       /* Interrupt Vector: I2C Mode: UCRXIFG3 */
+#define USCI_I2C_UCTXIFG3      (0x000C)       /* Interrupt Vector: I2C Mode: UCTXIFG3 */
+#define USCI_I2C_UCRXIFG2      (0x000E)       /* Interrupt Vector: I2C Mode: UCRXIFG2 */
+#define USCI_I2C_UCTXIFG2      (0x0010)       /* Interrupt Vector: I2C Mode: UCTXIFG2 */
+#define USCI_I2C_UCRXIFG1      (0x0012)       /* Interrupt Vector: I2C Mode: UCRXIFG1 */
+#define USCI_I2C_UCTXIFG1      (0x0014)       /* Interrupt Vector: I2C Mode: UCTXIFG1 */
+#define USCI_I2C_UCRXIFG0      (0x0016)       /* Interrupt Vector: I2C Mode: UCRXIFG0 */
+#define USCI_I2C_UCTXIFG0      (0x0018)       /* Interrupt Vector: I2C Mode: UCTXIFG0 */
+#define USCI_I2C_UCBCNTIFG     (0x001A)       /* Interrupt Vector: I2C Mode: UCBCNTIFG */
+#define USCI_I2C_UCCLTOIFG     (0x001C)       /* Interrupt Vector: I2C Mode: UCCLTOIFG */
+#define USCI_I2C_UCBIT9IFG     (0x001E)       /* Interrupt Vector: I2C Mode: UCBIT9IFG */
+
+/************************************************************
+* WATCHDOG TIMER A
+************************************************************/
+#define __MSP430_HAS_WDT_A__                  /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_WDT_A__ 0x0150
+#define WDT_A_BASE             __MSP430_BASEADDRESS_WDT_A__
+
+sfr_w(WDTCTL);                                /* Watchdog Timer Control */
+sfr_b(WDTCTL_L);                              /* Watchdog Timer Control */
+sfr_b(WDTCTL_H);                              /* Watchdog Timer Control */
+/* The bit names have been prefixed with "WDT" */
+/* WDTCTL Control Bits */
+#define WDTIS0                 (0x0001)       /* WDT - Timer Interval Select 0 */
+#define WDTIS1                 (0x0002)       /* WDT - Timer Interval Select 1 */
+#define WDTIS2                 (0x0004)       /* WDT - Timer Interval Select 2 */
+#define WDTCNTCL               (0x0008)       /* WDT - Timer Clear */
+#define WDTTMSEL               (0x0010)       /* WDT - Timer Mode Select */
+#define WDTSSEL0               (0x0020)       /* WDT - Timer Clock Source Select 0 */
+#define WDTSSEL1               (0x0040)       /* WDT - Timer Clock Source Select 1 */
+#define WDTHOLD                (0x0080)       /* WDT - Timer hold */
+
+/* WDTCTL Control Bits */
+#define WDTIS0_L               (0x0001)       /* WDT - Timer Interval Select 0 */
+#define WDTIS1_L               (0x0002)       /* WDT - Timer Interval Select 1 */
+#define WDTIS2_L               (0x0004)       /* WDT - Timer Interval Select 2 */
+#define WDTCNTCL_L             (0x0008)       /* WDT - Timer Clear */
+#define WDTTMSEL_L             (0x0010)       /* WDT - Timer Mode Select */
+#define WDTSSEL0_L             (0x0020)       /* WDT - Timer Clock Source Select 0 */
+#define WDTSSEL1_L             (0x0040)       /* WDT - Timer Clock Source Select 1 */
+#define WDTHOLD_L              (0x0080)       /* WDT - Timer hold */
+
+#define WDTPW                  (0x5A00)
+
+#define WDTIS_0                (0x0000)       /* WDT - Timer Interval Select: /2G */
+#define WDTIS_1                (0x0001)       /* WDT - Timer Interval Select: /128M */
+#define WDTIS_2                (0x0002)       /* WDT - Timer Interval Select: /8192k */
+#define WDTIS_3                (0x0003)       /* WDT - Timer Interval Select: /512k */
+#define WDTIS_4                (0x0004)       /* WDT - Timer Interval Select: /32k */
+#define WDTIS_5                (0x0005)       /* WDT - Timer Interval Select: /8192 */
+#define WDTIS_6                (0x0006)       /* WDT - Timer Interval Select: /512 */
+#define WDTIS_7                (0x0007)       /* WDT - Timer Interval Select: /64 */
+#define WDTIS__2G              (0x0000)       /* WDT - Timer Interval Select: /2G */
+#define WDTIS__128M            (0x0001)       /* WDT - Timer Interval Select: /128M */
+#define WDTIS__8192K           (0x0002)       /* WDT - Timer Interval Select: /8192k */
+#define WDTIS__512K            (0x0003)       /* WDT - Timer Interval Select: /512k */
+#define WDTIS__32K             (0x0004)       /* WDT - Timer Interval Select: /32k */
+#define WDTIS__8192            (0x0005)       /* WDT - Timer Interval Select: /8192 */
+#define WDTIS__512             (0x0006)       /* WDT - Timer Interval Select: /512 */
+#define WDTIS__64              (0x0007)       /* WDT - Timer Interval Select: /64 */
+
+#define WDTSSEL_0              (0x0000)       /* WDT - Timer Clock Source Select: SMCLK */
+#define WDTSSEL_1              (0x0020)       /* WDT - Timer Clock Source Select: ACLK */
+#define WDTSSEL_2              (0x0040)       /* WDT - Timer Clock Source Select: VLO_CLK */
+#define WDTSSEL_3              (0x0060)       /* WDT - Timer Clock Source Select: reserved */
+#define WDTSSEL__SMCLK         (0x0000)       /* WDT - Timer Clock Source Select: SMCLK */
+#define WDTSSEL__ACLK          (0x0020)       /* WDT - Timer Clock Source Select: ACLK */
+#define WDTSSEL__VLO           (0x0040)       /* WDT - Timer Clock Source Select: VLO_CLK */
+
+/* WDT-interval times [1ms] coded with Bits 0-2 */
+/* WDT is clocked by fSMCLK (assumed 1MHz) */
+#define WDT_MDLY_32         (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2)                         /* 32ms interval (default) */
+#define WDT_MDLY_8          (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0)                  /* 8ms     " */
+#define WDT_MDLY_0_5        (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1)                  /* 0.5ms   " */
+#define WDT_MDLY_0_064      (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0)           /* 0.064ms " */
+/* WDT is clocked by fACLK (assumed 32KHz) */
+#define WDT_ADLY_1000       (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0)                /* 1000ms  " */
+#define WDT_ADLY_250        (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0)         /* 250ms   " */
+#define WDT_ADLY_16         (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1)         /* 16ms    " */
+#define WDT_ADLY_1_9        (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0)  /* 1.9ms   " */
+/* Watchdog mode -> reset after expired time */
+/* WDT is clocked by fSMCLK (assumed 1MHz) */
+#define WDT_MRST_32         (WDTPW+WDTCNTCL+WDTIS2)                                  /* 32ms interval (default) */
+#define WDT_MRST_8          (WDTPW+WDTCNTCL+WDTIS2+WDTIS0)                           /* 8ms     " */
+#define WDT_MRST_0_5        (WDTPW+WDTCNTCL+WDTIS2+WDTIS1)                           /* 0.5ms   " */
+#define WDT_MRST_0_064      (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0)                    /* 0.064ms " */
+/* WDT is clocked by fACLK (assumed 32KHz) */
+#define WDT_ARST_1000       (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2)                         /* 1000ms  " */
+#define WDT_ARST_250        (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0)                  /* 250ms   " */
+#define WDT_ARST_16         (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1)                  /* 16ms    " */
+#define WDT_ARST_1_9        (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0)           /* 1.9ms   " */
+
+
+/************************************************************
+* TLV Descriptors
+************************************************************/
+#define __MSP430_HAS_TLV__                    /* Definition to show that Module is available */
+#define TLV_BASE               __MSP430_BASEADDRESS_TLV__
+
+#define TLV_CRC_LENGTH         (0x1A01)       /* CRC length of the TLV structure */
+#define TLV_CRC_VALUE          (0x1A02)       /* CRC value of the TLV structure */
+#define TLV_START              (0x1A08)       /* Start Address of the TLV structure */
+#define TLV_END                (0x1AFF)       /* End Address of the TLV structure */
+
+#define TLV_LDTAG              (0x01)         /*  Legacy descriptor (1xx, 2xx, 4xx families) */
+#define TLV_PDTAG              (0x02)         /*  Peripheral discovery descriptor */
+#define TLV_Reserved3          (0x03)         /*  Future usage */
+#define TLV_Reserved4          (0x04)         /*  Future usage */
+#define TLV_BLANK              (0x05)         /*  Blank descriptor */
+#define TLV_Reserved6          (0x06)         /*  Future usage */
+#define TLV_Reserved7          (0x07)         /*  Serial Number */
+#define TLV_DIERECORD          (0x08)         /*  Die Record  */
+#define TLV_ADCCAL             (0x11)         /*  ADC12 calibration */
+#define TLV_ADC12CAL           (0x11)         /*  ADC12 calibration */
+#define TLV_ADC10CAL           (0x13)         /*  ADC10 calibration */
+#define TLV_REFCAL             (0x12)         /*  REF calibration */
+#define TLV_TAGEXT             (0xFE)         /*  Tag extender */
+#define TLV_TAGEND             (0xFF)         //  Tag End of Table
+
+/************************************************************
+* Interrupt Vectors (offset from 0xFF80 + 0x10 for Password)
+************************************************************/
+
+
+#define AES256_VECTOR           (31)                     /* 0xFFCC AES256 */
+#define RTC_VECTOR              (32)                     /* 0xFFCE RTC */
+#define PORT4_VECTOR            (33)                     /* 0xFFD0 Port 4 */
+#define PORT3_VECTOR            (34)                     /* 0xFFD2 Port 3 */
+#define TIMER3_A1_VECTOR        (35)                     /* 0xFFD4 Timer3_A2 CC1, TA */
+#define TIMER3_A0_VECTOR        (36)                     /* 0xFFD6 Timer3_A2 CC0 */
+#define PORT2_VECTOR            (37)                     /* 0xFFD8 Port 2 */
+#define TIMER2_A1_VECTOR        (38)                     /* 0xFFDA Timer2_A2 CC1, TA */
+#define TIMER2_A0_VECTOR        (39)                     /* 0xFFDC Timer2_A2 CC0 */
+#define PORT1_VECTOR            (40)                     /* 0xFFDE Port 1 */
+#define TIMER1_A1_VECTOR        (41)                     /* 0xFFE0 Timer1_A3 CC1-2, TA */
+#define TIMER1_A0_VECTOR        (42)                     /* 0xFFE2 Timer1_A3 CC0 */
+#define DMA_VECTOR              (43)                     /* 0xFFE4 DMA */
+#define USCI_A1_VECTOR          (44)                     /* 0xFFE6 USCI A1 Receive/Transmit */
+#define TIMER0_A1_VECTOR        (45)                     /* 0xFFE8 Timer0_A3 CC1-2, TA */
+#define TIMER0_A0_VECTOR        (46)                     /* 0xFFEA Timer0_A3 CC0 */
+#define ADC12_VECTOR            (47)                     /* 0xFFEC ADC */
+#define USCI_B0_VECTOR          (48)                     /* 0xFFEE USCI B0 Receive/Transmit */
+#define USCI_A0_VECTOR          (49)                     /* 0xFFF0 USCI A0 Receive/Transmit */
+#define WDT_VECTOR              (50)                     /* 0xFFF2 Watchdog Timer */
+#define TIMER0_B1_VECTOR        (51)                     /* 0xFFF4 Timer0_B7 CC1-6, TB */
+#define TIMER0_B0_VECTOR        (52)                     /* 0xFFF6 Timer0_B7 CC0 */
+#define COMP_E_VECTOR           (53)                     /* 0xFFF8 Comparator E */
+#define UNMI_VECTOR             (54)                     /* 0xFFFA User Non-maskable */
+#define SYSNMI_VECTOR           (55)                     /* 0xFFFC System Non-maskable */
+#define RESET_VECTOR            ("reset")                /* 0xFFFE Reset [Highest Priority] */
+
+/************************************************************
+* End of Modules
+************************************************************/
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif /* #ifndef __MSP430FR5969 */
+
diff --git a/os/common/ext/MSP430/inc/msp430fr6989.h b/os/common/ext/MSP430/inc/msp430fr6989.h
new file mode 100644
index 0000000..1b25e9d
--- /dev/null
+++ b/os/common/ext/MSP430/inc/msp430fr6989.h
@@ -0,0 +1,6315 @@
+/* ============================================================================ */
+/* Copyright (c) 2016, Texas Instruments Incorporated                           */
+/*  All rights reserved.                                                        */
+/*                                                                              */
+/*  Redistribution and use in source and binary forms, with or without          */
+/*  modification, are permitted provided that the following conditions          */
+/*  are met:                                                                    */
+/*                                                                              */
+/*  *  Redistributions of source code must retain the above copyright           */
+/*     notice, this list of conditions and the following disclaimer.            */
+/*                                                                              */
+/*  *  Redistributions in binary form must reproduce the above copyright        */
+/*     notice, this list of conditions and the following disclaimer in the      */
+/*     documentation and/or other materials provided with the distribution.     */
+/*                                                                              */
+/*  *  Neither the name of Texas Instruments Incorporated nor the names of      */
+/*     its contributors may be used to endorse or promote products derived      */
+/*     from this software without specific prior written permission.            */
+/*                                                                              */
+/*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */
+/*  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,       */
+/*  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR      */
+/*  PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR            */
+/*  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,       */
+/*  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,         */
+/*  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */
+/*  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,    */
+/*  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR     */
+/*  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,              */
+/*  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                          */
+/* ============================================================================ */
+
+/********************************************************************
+*
+* Standard register and bit definitions for the Texas Instruments
+* MSP430 microcontroller.
+*
+* This file supports assembler and C development for
+* MSP430FR6989 devices.
+*
+* Texas Instruments, Version 1.1
+*
+* Rev. 1.0, Setup
+* Rev. 1.1, ESI: Renamed bit ESIVCC2 to ESIVMIDEN, renamed bit ESIVSS to ESISHTSM
+*
+*
+********************************************************************/
+
+#ifndef __MSP430FR6989
+#define __MSP430FR6989
+
+#define __MSP430_HAS_MSP430XV2_CPU__                /* Definition to show that it has MSP430XV2 CPU */
+#define __MSP430FR5XX_6XX_FAMILY__
+
+#define __MSP430_HEADER_VERSION__ 1198
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*----------------------------------------------------------------------------*/
+/* PERIPHERAL FILE MAP                                                        */
+/*----------------------------------------------------------------------------*/
+
+#define __MSP430_TI_HEADERS__
+
+#include <iomacros.h>
+
+
+/************************************************************
+* STANDARD BITS
+************************************************************/
+
+#define BIT0                   (0x0001)
+#define BIT1                   (0x0002)
+#define BIT2                   (0x0004)
+#define BIT3                   (0x0008)
+#define BIT4                   (0x0010)
+#define BIT5                   (0x0020)
+#define BIT6                   (0x0040)
+#define BIT7                   (0x0080)
+#define BIT8                   (0x0100)
+#define BIT9                   (0x0200)
+#define BITA                   (0x0400)
+#define BITB                   (0x0800)
+#define BITC                   (0x1000)
+#define BITD                   (0x2000)
+#define BITE                   (0x4000)
+#define BITF                   (0x8000)
+
+/************************************************************
+* STATUS REGISTER BITS
+************************************************************/
+
+#define C                      (0x0001)
+#define Z                      (0x0002)
+#define N                      (0x0004)
+#define V                      (0x0100)
+#define GIE                    (0x0008)
+#define CPUOFF                 (0x0010)
+#define OSCOFF                 (0x0020)
+#define SCG0                   (0x0040)
+#define SCG1                   (0x0080)
+
+/* Low Power Modes coded with Bits 4-7 in SR */
+
+#ifndef __STDC__ /* Begin #defines for assembler */
+#define LPM0                   (CPUOFF)
+#define LPM1                   (SCG0+CPUOFF)
+#define LPM2                   (SCG1+CPUOFF)
+#define LPM3                   (SCG1+SCG0+CPUOFF)
+#define LPM4                   (SCG1+SCG0+OSCOFF+CPUOFF)
+/* End #defines for assembler */
+
+#else /* Begin #defines for C */
+#define LPM0_bits              (CPUOFF)
+#define LPM1_bits              (SCG0+CPUOFF)
+#define LPM2_bits              (SCG1+CPUOFF)
+#define LPM3_bits              (SCG1+SCG0+CPUOFF)
+#define LPM4_bits              (SCG1+SCG0+OSCOFF+CPUOFF)
+
+#include "in430.h"
+
+#define LPM0      __bis_SR_register(LPM0_bits)         /* Enter Low Power Mode 0 */
+#define LPM0_EXIT __bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */
+#define LPM1      __bis_SR_register(LPM1_bits)         /* Enter Low Power Mode 1 */
+#define LPM1_EXIT __bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */
+#define LPM2      __bis_SR_register(LPM2_bits)         /* Enter Low Power Mode 2 */
+#define LPM2_EXIT __bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */
+#define LPM3      __bis_SR_register(LPM3_bits)         /* Enter Low Power Mode 3 */
+#define LPM3_EXIT __bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */
+#define LPM4      __bis_SR_register(LPM4_bits)         /* Enter Low Power Mode 4 */
+#define LPM4_EXIT __bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */
+#endif /* End #defines for C */
+
+/************************************************************
+* PERIPHERAL FILE MAP
+************************************************************/
+
+/************************************************************
+* ADC12_B
+************************************************************/
+#define __MSP430_HAS_ADC12_B__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_ADC12_B__ 0x0800
+#define ADC12_B_BASE           __MSP430_BASEADDRESS_ADC12_B__
+
+sfr_w(ADC12CTL0);                             /* ADC12 B Control 0 */
+sfr_b(ADC12CTL0_L);                           /* ADC12 B Control 0 */
+sfr_b(ADC12CTL0_H);                           /* ADC12 B Control 0 */
+sfr_w(ADC12CTL1);                             /* ADC12 B Control 1 */
+sfr_b(ADC12CTL1_L);                           /* ADC12 B Control 1 */
+sfr_b(ADC12CTL1_H);                           /* ADC12 B Control 1 */
+sfr_w(ADC12CTL2);                             /* ADC12 B Control 2 */
+sfr_b(ADC12CTL2_L);                           /* ADC12 B Control 2 */
+sfr_b(ADC12CTL2_H);                           /* ADC12 B Control 2 */
+sfr_w(ADC12CTL3);                             /* ADC12 B Control 3 */
+sfr_b(ADC12CTL3_L);                           /* ADC12 B Control 3 */
+sfr_b(ADC12CTL3_H);                           /* ADC12 B Control 3 */
+sfr_w(ADC12LO);                               /* ADC12 B Window Comparator High Threshold */
+sfr_b(ADC12LO_L);                             /* ADC12 B Window Comparator High Threshold */
+sfr_b(ADC12LO_H);                             /* ADC12 B Window Comparator High Threshold */
+sfr_w(ADC12HI);                               /* ADC12 B Window Comparator High Threshold */
+sfr_b(ADC12HI_L);                             /* ADC12 B Window Comparator High Threshold */
+sfr_b(ADC12HI_H);                             /* ADC12 B Window Comparator High Threshold */
+sfr_w(ADC12IFGR0);                            /* ADC12 B Interrupt Flag 0 */
+sfr_b(ADC12IFGR0_L);                          /* ADC12 B Interrupt Flag 0 */
+sfr_b(ADC12IFGR0_H);                          /* ADC12 B Interrupt Flag 0 */
+sfr_w(ADC12IFGR1);                            /* ADC12 B Interrupt Flag 1 */
+sfr_b(ADC12IFGR1_L);                          /* ADC12 B Interrupt Flag 1 */
+sfr_b(ADC12IFGR1_H);                          /* ADC12 B Interrupt Flag 1 */
+sfr_w(ADC12IFGR2);                            /* ADC12 B Interrupt Flag 2 */
+sfr_b(ADC12IFGR2_L);                          /* ADC12 B Interrupt Flag 2 */
+sfr_b(ADC12IFGR2_H);                          /* ADC12 B Interrupt Flag 2 */
+sfr_w(ADC12IER0);                             /* ADC12 B Interrupt Enable 0 */
+sfr_b(ADC12IER0_L);                           /* ADC12 B Interrupt Enable 0 */
+sfr_b(ADC12IER0_H);                           /* ADC12 B Interrupt Enable 0 */
+sfr_w(ADC12IER1);                             /* ADC12 B Interrupt Enable 1 */
+sfr_b(ADC12IER1_L);                           /* ADC12 B Interrupt Enable 1 */
+sfr_b(ADC12IER1_H);                           /* ADC12 B Interrupt Enable 1 */
+sfr_w(ADC12IER2);                             /* ADC12 B Interrupt Enable 2 */
+sfr_b(ADC12IER2_L);                           /* ADC12 B Interrupt Enable 2 */
+sfr_b(ADC12IER2_H);                           /* ADC12 B Interrupt Enable 2 */
+sfr_w(ADC12IV);                               /* ADC12 B Interrupt Vector Word */
+sfr_b(ADC12IV_L);                             /* ADC12 B Interrupt Vector Word */
+sfr_b(ADC12IV_H);                             /* ADC12 B Interrupt Vector Word */
+
+sfr_w(ADC12MCTL0);                            /* ADC12 Memory Control 0 */
+sfr_b(ADC12MCTL0_L);                          /* ADC12 Memory Control 0 */
+sfr_b(ADC12MCTL0_H);                          /* ADC12 Memory Control 0 */
+sfr_w(ADC12MCTL1);                            /* ADC12 Memory Control 1 */
+sfr_b(ADC12MCTL1_L);                          /* ADC12 Memory Control 1 */
+sfr_b(ADC12MCTL1_H);                          /* ADC12 Memory Control 1 */
+sfr_w(ADC12MCTL2);                            /* ADC12 Memory Control 2 */
+sfr_b(ADC12MCTL2_L);                          /* ADC12 Memory Control 2 */
+sfr_b(ADC12MCTL2_H);                          /* ADC12 Memory Control 2 */
+sfr_w(ADC12MCTL3);                            /* ADC12 Memory Control 3 */
+sfr_b(ADC12MCTL3_L);                          /* ADC12 Memory Control 3 */
+sfr_b(ADC12MCTL3_H);                          /* ADC12 Memory Control 3 */
+sfr_w(ADC12MCTL4);                            /* ADC12 Memory Control 4 */
+sfr_b(ADC12MCTL4_L);                          /* ADC12 Memory Control 4 */
+sfr_b(ADC12MCTL4_H);                          /* ADC12 Memory Control 4 */
+sfr_w(ADC12MCTL5);                            /* ADC12 Memory Control 5 */
+sfr_b(ADC12MCTL5_L);                          /* ADC12 Memory Control 5 */
+sfr_b(ADC12MCTL5_H);                          /* ADC12 Memory Control 5 */
+sfr_w(ADC12MCTL6);                            /* ADC12 Memory Control 6 */
+sfr_b(ADC12MCTL6_L);                          /* ADC12 Memory Control 6 */
+sfr_b(ADC12MCTL6_H);                          /* ADC12 Memory Control 6 */
+sfr_w(ADC12MCTL7);                            /* ADC12 Memory Control 7 */
+sfr_b(ADC12MCTL7_L);                          /* ADC12 Memory Control 7 */
+sfr_b(ADC12MCTL7_H);                          /* ADC12 Memory Control 7 */
+sfr_w(ADC12MCTL8);                            /* ADC12 Memory Control 8 */
+sfr_b(ADC12MCTL8_L);                          /* ADC12 Memory Control 8 */
+sfr_b(ADC12MCTL8_H);                          /* ADC12 Memory Control 8 */
+sfr_w(ADC12MCTL9);                            /* ADC12 Memory Control 9 */
+sfr_b(ADC12MCTL9_L);                          /* ADC12 Memory Control 9 */
+sfr_b(ADC12MCTL9_H);                          /* ADC12 Memory Control 9 */
+sfr_w(ADC12MCTL10);                           /* ADC12 Memory Control 10 */
+sfr_b(ADC12MCTL10_L);                         /* ADC12 Memory Control 10 */
+sfr_b(ADC12MCTL10_H);                         /* ADC12 Memory Control 10 */
+sfr_w(ADC12MCTL11);                           /* ADC12 Memory Control 11 */
+sfr_b(ADC12MCTL11_L);                         /* ADC12 Memory Control 11 */
+sfr_b(ADC12MCTL11_H);                         /* ADC12 Memory Control 11 */
+sfr_w(ADC12MCTL12);                           /* ADC12 Memory Control 12 */
+sfr_b(ADC12MCTL12_L);                         /* ADC12 Memory Control 12 */
+sfr_b(ADC12MCTL12_H);                         /* ADC12 Memory Control 12 */
+sfr_w(ADC12MCTL13);                           /* ADC12 Memory Control 13 */
+sfr_b(ADC12MCTL13_L);                         /* ADC12 Memory Control 13 */
+sfr_b(ADC12MCTL13_H);                         /* ADC12 Memory Control 13 */
+sfr_w(ADC12MCTL14);                           /* ADC12 Memory Control 14 */
+sfr_b(ADC12MCTL14_L);                         /* ADC12 Memory Control 14 */
+sfr_b(ADC12MCTL14_H);                         /* ADC12 Memory Control 14 */
+sfr_w(ADC12MCTL15);                           /* ADC12 Memory Control 15 */
+sfr_b(ADC12MCTL15_L);                         /* ADC12 Memory Control 15 */
+sfr_b(ADC12MCTL15_H);                         /* ADC12 Memory Control 15 */
+sfr_w(ADC12MCTL16);                           /* ADC12 Memory Control 16 */
+sfr_b(ADC12MCTL16_L);                         /* ADC12 Memory Control 16 */
+sfr_b(ADC12MCTL16_H);                         /* ADC12 Memory Control 16 */
+sfr_w(ADC12MCTL17);                           /* ADC12 Memory Control 17 */
+sfr_b(ADC12MCTL17_L);                         /* ADC12 Memory Control 17 */
+sfr_b(ADC12MCTL17_H);                         /* ADC12 Memory Control 17 */
+sfr_w(ADC12MCTL18);                           /* ADC12 Memory Control 18 */
+sfr_b(ADC12MCTL18_L);                         /* ADC12 Memory Control 18 */
+sfr_b(ADC12MCTL18_H);                         /* ADC12 Memory Control 18 */
+sfr_w(ADC12MCTL19);                           /* ADC12 Memory Control 19 */
+sfr_b(ADC12MCTL19_L);                         /* ADC12 Memory Control 19 */
+sfr_b(ADC12MCTL19_H);                         /* ADC12 Memory Control 19 */
+sfr_w(ADC12MCTL20);                           /* ADC12 Memory Control 20 */
+sfr_b(ADC12MCTL20_L);                         /* ADC12 Memory Control 20 */
+sfr_b(ADC12MCTL20_H);                         /* ADC12 Memory Control 20 */
+sfr_w(ADC12MCTL21);                           /* ADC12 Memory Control 21 */
+sfr_b(ADC12MCTL21_L);                         /* ADC12 Memory Control 21 */
+sfr_b(ADC12MCTL21_H);                         /* ADC12 Memory Control 21 */
+sfr_w(ADC12MCTL22);                           /* ADC12 Memory Control 22 */
+sfr_b(ADC12MCTL22_L);                         /* ADC12 Memory Control 22 */
+sfr_b(ADC12MCTL22_H);                         /* ADC12 Memory Control 22 */
+sfr_w(ADC12MCTL23);                           /* ADC12 Memory Control 23 */
+sfr_b(ADC12MCTL23_L);                         /* ADC12 Memory Control 23 */
+sfr_b(ADC12MCTL23_H);                         /* ADC12 Memory Control 23 */
+sfr_w(ADC12MCTL24);                           /* ADC12 Memory Control 24 */
+sfr_b(ADC12MCTL24_L);                         /* ADC12 Memory Control 24 */
+sfr_b(ADC12MCTL24_H);                         /* ADC12 Memory Control 24 */
+sfr_w(ADC12MCTL25);                           /* ADC12 Memory Control 25 */
+sfr_b(ADC12MCTL25_L);                         /* ADC12 Memory Control 25 */
+sfr_b(ADC12MCTL25_H);                         /* ADC12 Memory Control 25 */
+sfr_w(ADC12MCTL26);                           /* ADC12 Memory Control 26 */
+sfr_b(ADC12MCTL26_L);                         /* ADC12 Memory Control 26 */
+sfr_b(ADC12MCTL26_H);                         /* ADC12 Memory Control 26 */
+sfr_w(ADC12MCTL27);                           /* ADC12 Memory Control 27 */
+sfr_b(ADC12MCTL27_L);                         /* ADC12 Memory Control 27 */
+sfr_b(ADC12MCTL27_H);                         /* ADC12 Memory Control 27 */
+sfr_w(ADC12MCTL28);                           /* ADC12 Memory Control 28 */
+sfr_b(ADC12MCTL28_L);                         /* ADC12 Memory Control 28 */
+sfr_b(ADC12MCTL28_H);                         /* ADC12 Memory Control 28 */
+sfr_w(ADC12MCTL29);                           /* ADC12 Memory Control 29 */
+sfr_b(ADC12MCTL29_L);                         /* ADC12 Memory Control 29 */
+sfr_b(ADC12MCTL29_H);                         /* ADC12 Memory Control 29 */
+sfr_w(ADC12MCTL30);                           /* ADC12 Memory Control 30 */
+sfr_b(ADC12MCTL30_L);                         /* ADC12 Memory Control 30 */
+sfr_b(ADC12MCTL30_H);                         /* ADC12 Memory Control 30 */
+sfr_w(ADC12MCTL31);                           /* ADC12 Memory Control 31 */
+sfr_b(ADC12MCTL31_L);                         /* ADC12 Memory Control 31 */
+sfr_b(ADC12MCTL31_H);                         /* ADC12 Memory Control 31 */
+#define ADC12MCTL_             ADC12MCTL      /* ADC12 Memory Control */
+#ifndef __STDC__
+#define ADC12MCTL              ADC12MCTL0     /* ADC12 Memory Control (for assembler) */
+#else
+#define ADC12MCTL              ((volatile char*)       &ADC12MCTL0) /* ADC12 Memory Control (for C) */
+#endif
+
+sfr_w(ADC12MEM0);                             /* ADC12 Conversion Memory 0 */
+sfr_b(ADC12MEM0_L);                           /* ADC12 Conversion Memory 0 */
+sfr_b(ADC12MEM0_H);                           /* ADC12 Conversion Memory 0 */
+sfr_w(ADC12MEM1);                             /* ADC12 Conversion Memory 1 */
+sfr_b(ADC12MEM1_L);                           /* ADC12 Conversion Memory 1 */
+sfr_b(ADC12MEM1_H);                           /* ADC12 Conversion Memory 1 */
+sfr_w(ADC12MEM2);                             /* ADC12 Conversion Memory 2 */
+sfr_b(ADC12MEM2_L);                           /* ADC12 Conversion Memory 2 */
+sfr_b(ADC12MEM2_H);                           /* ADC12 Conversion Memory 2 */
+sfr_w(ADC12MEM3);                             /* ADC12 Conversion Memory 3 */
+sfr_b(ADC12MEM3_L);                           /* ADC12 Conversion Memory 3 */
+sfr_b(ADC12MEM3_H);                           /* ADC12 Conversion Memory 3 */
+sfr_w(ADC12MEM4);                             /* ADC12 Conversion Memory 4 */
+sfr_b(ADC12MEM4_L);                           /* ADC12 Conversion Memory 4 */
+sfr_b(ADC12MEM4_H);                           /* ADC12 Conversion Memory 4 */
+sfr_w(ADC12MEM5);                             /* ADC12 Conversion Memory 5 */
+sfr_b(ADC12MEM5_L);                           /* ADC12 Conversion Memory 5 */
+sfr_b(ADC12MEM5_H);                           /* ADC12 Conversion Memory 5 */
+sfr_w(ADC12MEM6);                             /* ADC12 Conversion Memory 6 */
+sfr_b(ADC12MEM6_L);                           /* ADC12 Conversion Memory 6 */
+sfr_b(ADC12MEM6_H);                           /* ADC12 Conversion Memory 6 */
+sfr_w(ADC12MEM7);                             /* ADC12 Conversion Memory 7 */
+sfr_b(ADC12MEM7_L);                           /* ADC12 Conversion Memory 7 */
+sfr_b(ADC12MEM7_H);                           /* ADC12 Conversion Memory 7 */
+sfr_w(ADC12MEM8);                             /* ADC12 Conversion Memory 8 */
+sfr_b(ADC12MEM8_L);                           /* ADC12 Conversion Memory 8 */
+sfr_b(ADC12MEM8_H);                           /* ADC12 Conversion Memory 8 */
+sfr_w(ADC12MEM9);                             /* ADC12 Conversion Memory 9 */
+sfr_b(ADC12MEM9_L);                           /* ADC12 Conversion Memory 9 */
+sfr_b(ADC12MEM9_H);                           /* ADC12 Conversion Memory 9 */
+sfr_w(ADC12MEM10);                            /* ADC12 Conversion Memory 10 */
+sfr_b(ADC12MEM10_L);                          /* ADC12 Conversion Memory 10 */
+sfr_b(ADC12MEM10_H);                          /* ADC12 Conversion Memory 10 */
+sfr_w(ADC12MEM11);                            /* ADC12 Conversion Memory 11 */
+sfr_b(ADC12MEM11_L);                          /* ADC12 Conversion Memory 11 */
+sfr_b(ADC12MEM11_H);                          /* ADC12 Conversion Memory 11 */
+sfr_w(ADC12MEM12);                            /* ADC12 Conversion Memory 12 */
+sfr_b(ADC12MEM12_L);                          /* ADC12 Conversion Memory 12 */
+sfr_b(ADC12MEM12_H);                          /* ADC12 Conversion Memory 12 */
+sfr_w(ADC12MEM13);                            /* ADC12 Conversion Memory 13 */
+sfr_b(ADC12MEM13_L);                          /* ADC12 Conversion Memory 13 */
+sfr_b(ADC12MEM13_H);                          /* ADC12 Conversion Memory 13 */
+sfr_w(ADC12MEM14);                            /* ADC12 Conversion Memory 14 */
+sfr_b(ADC12MEM14_L);                          /* ADC12 Conversion Memory 14 */
+sfr_b(ADC12MEM14_H);                          /* ADC12 Conversion Memory 14 */
+sfr_w(ADC12MEM15);                            /* ADC12 Conversion Memory 15 */
+sfr_b(ADC12MEM15_L);                          /* ADC12 Conversion Memory 15 */
+sfr_b(ADC12MEM15_H);                          /* ADC12 Conversion Memory 15 */
+sfr_w(ADC12MEM16);                            /* ADC12 Conversion Memory 16 */
+sfr_b(ADC12MEM16_L);                          /* ADC12 Conversion Memory 16 */
+sfr_b(ADC12MEM16_H);                          /* ADC12 Conversion Memory 16 */
+sfr_w(ADC12MEM17);                            /* ADC12 Conversion Memory 17 */
+sfr_b(ADC12MEM17_L);                          /* ADC12 Conversion Memory 17 */
+sfr_b(ADC12MEM17_H);                          /* ADC12 Conversion Memory 17 */
+sfr_w(ADC12MEM18);                            /* ADC12 Conversion Memory 18 */
+sfr_b(ADC12MEM18_L);                          /* ADC12 Conversion Memory 18 */
+sfr_b(ADC12MEM18_H);                          /* ADC12 Conversion Memory 18 */
+sfr_w(ADC12MEM19);                            /* ADC12 Conversion Memory 19 */
+sfr_b(ADC12MEM19_L);                          /* ADC12 Conversion Memory 19 */
+sfr_b(ADC12MEM19_H);                          /* ADC12 Conversion Memory 19 */
+sfr_w(ADC12MEM20);                            /* ADC12 Conversion Memory 20 */
+sfr_b(ADC12MEM20_L);                          /* ADC12 Conversion Memory 20 */
+sfr_b(ADC12MEM20_H);                          /* ADC12 Conversion Memory 20 */
+sfr_w(ADC12MEM21);                            /* ADC12 Conversion Memory 21 */
+sfr_b(ADC12MEM21_L);                          /* ADC12 Conversion Memory 21 */
+sfr_b(ADC12MEM21_H);                          /* ADC12 Conversion Memory 21 */
+sfr_w(ADC12MEM22);                            /* ADC12 Conversion Memory 22 */
+sfr_b(ADC12MEM22_L);                          /* ADC12 Conversion Memory 22 */
+sfr_b(ADC12MEM22_H);                          /* ADC12 Conversion Memory 22 */
+sfr_w(ADC12MEM23);                            /* ADC12 Conversion Memory 23 */
+sfr_b(ADC12MEM23_L);                          /* ADC12 Conversion Memory 23 */
+sfr_b(ADC12MEM23_H);                          /* ADC12 Conversion Memory 23 */
+sfr_w(ADC12MEM24);                            /* ADC12 Conversion Memory 24 */
+sfr_b(ADC12MEM24_L);                          /* ADC12 Conversion Memory 24 */
+sfr_b(ADC12MEM24_H);                          /* ADC12 Conversion Memory 24 */
+sfr_w(ADC12MEM25);                            /* ADC12 Conversion Memory 25 */
+sfr_b(ADC12MEM25_L);                          /* ADC12 Conversion Memory 25 */
+sfr_b(ADC12MEM25_H);                          /* ADC12 Conversion Memory 25 */
+sfr_w(ADC12MEM26);                            /* ADC12 Conversion Memory 26 */
+sfr_b(ADC12MEM26_L);                          /* ADC12 Conversion Memory 26 */
+sfr_b(ADC12MEM26_H);                          /* ADC12 Conversion Memory 26 */
+sfr_w(ADC12MEM27);                            /* ADC12 Conversion Memory 27 */
+sfr_b(ADC12MEM27_L);                          /* ADC12 Conversion Memory 27 */
+sfr_b(ADC12MEM27_H);                          /* ADC12 Conversion Memory 27 */
+sfr_w(ADC12MEM28);                            /* ADC12 Conversion Memory 28 */
+sfr_b(ADC12MEM28_L);                          /* ADC12 Conversion Memory 28 */
+sfr_b(ADC12MEM28_H);                          /* ADC12 Conversion Memory 28 */
+sfr_w(ADC12MEM29);                            /* ADC12 Conversion Memory 29 */
+sfr_b(ADC12MEM29_L);                          /* ADC12 Conversion Memory 29 */
+sfr_b(ADC12MEM29_H);                          /* ADC12 Conversion Memory 29 */
+sfr_w(ADC12MEM30);                            /* ADC12 Conversion Memory 30 */
+sfr_b(ADC12MEM30_L);                          /* ADC12 Conversion Memory 30 */
+sfr_b(ADC12MEM30_H);                          /* ADC12 Conversion Memory 30 */
+sfr_w(ADC12MEM31);                            /* ADC12 Conversion Memory 31 */
+sfr_b(ADC12MEM31_L);                          /* ADC12 Conversion Memory 31 */
+sfr_b(ADC12MEM31_H);                          /* ADC12 Conversion Memory 31 */
+#define ADC12MEM_              ADC12MEM       /* ADC12 Conversion Memory */
+#ifndef __STDC__
+#define ADC12MEM               ADC12MEM0      /* ADC12 Conversion Memory (for assembler) */
+#else
+#define ADC12MEM               ((volatile int*)        &ADC12MEM0) /* ADC12 Conversion Memory (for C) */
+#endif
+
+/* ADC12CTL0 Control Bits */
+#define ADC12SC                (0x0001)       /* ADC12 Start Conversion */
+#define ADC12ENC               (0x0002)       /* ADC12 Enable Conversion */
+#define ADC12ON                (0x0010)       /* ADC12 On/enable */
+#define ADC12MSC               (0x0080)       /* ADC12 Multiple SampleConversion */
+#define ADC12SHT00             (0x0100)       /* ADC12 Sample Hold 0 Select Bit: 0 */
+#define ADC12SHT01             (0x0200)       /* ADC12 Sample Hold 0 Select Bit: 1 */
+#define ADC12SHT02             (0x0400)       /* ADC12 Sample Hold 0 Select Bit: 2 */
+#define ADC12SHT03             (0x0800)       /* ADC12 Sample Hold 0 Select Bit: 3 */
+#define ADC12SHT10             (0x1000)       /* ADC12 Sample Hold 1 Select Bit: 0 */
+#define ADC12SHT11             (0x2000)       /* ADC12 Sample Hold 1 Select Bit: 1 */
+#define ADC12SHT12             (0x4000)       /* ADC12 Sample Hold 1 Select Bit: 2 */
+#define ADC12SHT13             (0x8000)       /* ADC12 Sample Hold 1 Select Bit: 3 */
+
+/* ADC12CTL0 Control Bits */
+#define ADC12SC_L              (0x0001)       /* ADC12 Start Conversion */
+#define ADC12ENC_L             (0x0002)       /* ADC12 Enable Conversion */
+#define ADC12ON_L              (0x0010)       /* ADC12 On/enable */
+#define ADC12MSC_L             (0x0080)       /* ADC12 Multiple SampleConversion */
+
+/* ADC12CTL0 Control Bits */
+#define ADC12SHT00_H           (0x0001)       /* ADC12 Sample Hold 0 Select Bit: 0 */
+#define ADC12SHT01_H           (0x0002)       /* ADC12 Sample Hold 0 Select Bit: 1 */
+#define ADC12SHT02_H           (0x0004)       /* ADC12 Sample Hold 0 Select Bit: 2 */
+#define ADC12SHT03_H           (0x0008)       /* ADC12 Sample Hold 0 Select Bit: 3 */
+#define ADC12SHT10_H           (0x0010)       /* ADC12 Sample Hold 1 Select Bit: 0 */
+#define ADC12SHT11_H           (0x0020)       /* ADC12 Sample Hold 1 Select Bit: 1 */
+#define ADC12SHT12_H           (0x0040)       /* ADC12 Sample Hold 1 Select Bit: 2 */
+#define ADC12SHT13_H           (0x0080)       /* ADC12 Sample Hold 1 Select Bit: 3 */
+
+#define ADC12SHT0_0            (0x0000)       /* ADC12 Sample Hold 0 Select Bit: 0 */
+#define ADC12SHT0_1            (0x0100)       /* ADC12 Sample Hold 0 Select Bit: 1 */
+#define ADC12SHT0_2            (0x0200)       /* ADC12 Sample Hold 0 Select Bit: 2 */
+#define ADC12SHT0_3            (0x0300)       /* ADC12 Sample Hold 0 Select Bit: 3 */
+#define ADC12SHT0_4            (0x0400)       /* ADC12 Sample Hold 0 Select Bit: 4 */
+#define ADC12SHT0_5            (0x0500)       /* ADC12 Sample Hold 0 Select Bit: 5 */
+#define ADC12SHT0_6            (0x0600)       /* ADC12 Sample Hold 0 Select Bit: 6 */
+#define ADC12SHT0_7            (0x0700)       /* ADC12 Sample Hold 0 Select Bit: 7 */
+#define ADC12SHT0_8            (0x0800)       /* ADC12 Sample Hold 0 Select Bit: 8 */
+#define ADC12SHT0_9            (0x0900)       /* ADC12 Sample Hold 0 Select Bit: 9 */
+#define ADC12SHT0_10           (0x0A00)       /* ADC12 Sample Hold 0 Select Bit: 10 */
+#define ADC12SHT0_11           (0x0B00)       /* ADC12 Sample Hold 0 Select Bit: 11 */
+#define ADC12SHT0_12           (0x0C00)       /* ADC12 Sample Hold 0 Select Bit: 12 */
+#define ADC12SHT0_13           (0x0D00)       /* ADC12 Sample Hold 0 Select Bit: 13 */
+#define ADC12SHT0_14           (0x0E00)       /* ADC12 Sample Hold 0 Select Bit: 14 */
+#define ADC12SHT0_15           (0x0F00)       /* ADC12 Sample Hold 0 Select Bit: 15 */
+
+#define ADC12SHT1_0            (0x0000)       /* ADC12 Sample Hold 1 Select Bit: 0 */
+#define ADC12SHT1_1            (0x1000)       /* ADC12 Sample Hold 1 Select Bit: 1 */
+#define ADC12SHT1_2            (0x2000)       /* ADC12 Sample Hold 1 Select Bit: 2 */
+#define ADC12SHT1_3            (0x3000)       /* ADC12 Sample Hold 1 Select Bit: 3 */
+#define ADC12SHT1_4            (0x4000)       /* ADC12 Sample Hold 1 Select Bit: 4 */
+#define ADC12SHT1_5            (0x5000)       /* ADC12 Sample Hold 1 Select Bit: 5 */
+#define ADC12SHT1_6            (0x6000)       /* ADC12 Sample Hold 1 Select Bit: 6 */
+#define ADC12SHT1_7            (0x7000)       /* ADC12 Sample Hold 1 Select Bit: 7 */
+#define ADC12SHT1_8            (0x8000)       /* ADC12 Sample Hold 1 Select Bit: 8 */
+#define ADC12SHT1_9            (0x9000)       /* ADC12 Sample Hold 1 Select Bit: 9 */
+#define ADC12SHT1_10           (0xA000)       /* ADC12 Sample Hold 1 Select Bit: 10 */
+#define ADC12SHT1_11           (0xB000)       /* ADC12 Sample Hold 1 Select Bit: 11 */
+#define ADC12SHT1_12           (0xC000)       /* ADC12 Sample Hold 1 Select Bit: 12 */
+#define ADC12SHT1_13           (0xD000)       /* ADC12 Sample Hold 1 Select Bit: 13 */
+#define ADC12SHT1_14           (0xE000)       /* ADC12 Sample Hold 1 Select Bit: 14 */
+#define ADC12SHT1_15           (0xF000)       /* ADC12 Sample Hold 1 Select Bit: 15 */
+
+/* ADC12CTL1 Control Bits */
+#define ADC12BUSY              (0x0001)       /* ADC12 Busy */
+#define ADC12CONSEQ0           (0x0002)       /* ADC12 Conversion Sequence Select Bit: 0 */
+#define ADC12CONSEQ1           (0x0004)       /* ADC12 Conversion Sequence Select Bit: 1 */
+#define ADC12SSEL0             (0x0008)       /* ADC12 Clock Source Select Bit: 0 */
+#define ADC12SSEL1             (0x0010)       /* ADC12 Clock Source Select Bit: 1 */
+#define ADC12DIV0              (0x0020)       /* ADC12 Clock Divider Select Bit: 0 */
+#define ADC12DIV1              (0x0040)       /* ADC12 Clock Divider Select Bit: 1 */
+#define ADC12DIV2              (0x0080)       /* ADC12 Clock Divider Select Bit: 2 */
+#define ADC12ISSH              (0x0100)       /* ADC12 Invert Sample Hold Signal */
+#define ADC12SHP               (0x0200)       /* ADC12 Sample/Hold Pulse Mode */
+#define ADC12SHS0              (0x0400)       /* ADC12 Sample/Hold Source Bit: 0 */
+#define ADC12SHS1              (0x0800)       /* ADC12 Sample/Hold Source Bit: 1 */
+#define ADC12SHS2              (0x1000)       /* ADC12 Sample/Hold Source Bit: 2 */
+#define ADC12PDIV0             (0x2000)       /* ADC12 Predivider Bit: 0 */
+#define ADC12PDIV1             (0x4000)       /* ADC12 Predivider Bit: 1 */
+
+/* ADC12CTL1 Control Bits */
+#define ADC12BUSY_L            (0x0001)       /* ADC12 Busy */
+#define ADC12CONSEQ0_L         (0x0002)       /* ADC12 Conversion Sequence Select Bit: 0 */
+#define ADC12CONSEQ1_L         (0x0004)       /* ADC12 Conversion Sequence Select Bit: 1 */
+#define ADC12SSEL0_L           (0x0008)       /* ADC12 Clock Source Select Bit: 0 */
+#define ADC12SSEL1_L           (0x0010)       /* ADC12 Clock Source Select Bit: 1 */
+#define ADC12DIV0_L            (0x0020)       /* ADC12 Clock Divider Select Bit: 0 */
+#define ADC12DIV1_L            (0x0040)       /* ADC12 Clock Divider Select Bit: 1 */
+#define ADC12DIV2_L            (0x0080)       /* ADC12 Clock Divider Select Bit: 2 */
+
+/* ADC12CTL1 Control Bits */
+#define ADC12ISSH_H            (0x0001)       /* ADC12 Invert Sample Hold Signal */
+#define ADC12SHP_H             (0x0002)       /* ADC12 Sample/Hold Pulse Mode */
+#define ADC12SHS0_H            (0x0004)       /* ADC12 Sample/Hold Source Bit: 0 */
+#define ADC12SHS1_H            (0x0008)       /* ADC12 Sample/Hold Source Bit: 1 */
+#define ADC12SHS2_H            (0x0010)       /* ADC12 Sample/Hold Source Bit: 2 */
+#define ADC12PDIV0_H           (0x0020)       /* ADC12 Predivider Bit: 0 */
+#define ADC12PDIV1_H           (0x0040)       /* ADC12 Predivider Bit: 1 */
+
+#define ADC12CONSEQ_0          (0x0000)       /* ADC12 Conversion Sequence Select: 0 */
+#define ADC12CONSEQ_1          (0x0002)       /* ADC12 Conversion Sequence Select: 1 */
+#define ADC12CONSEQ_2          (0x0004)       /* ADC12 Conversion Sequence Select: 2 */
+#define ADC12CONSEQ_3          (0x0006)       /* ADC12 Conversion Sequence Select: 3 */
+
+#define ADC12SSEL_0            (0x0000)       /* ADC12 Clock Source Select: 0 */
+#define ADC12SSEL_1            (0x0008)       /* ADC12 Clock Source Select: 1 */
+#define ADC12SSEL_2            (0x0010)       /* ADC12 Clock Source Select: 2 */
+#define ADC12SSEL_3            (0x0018)       /* ADC12 Clock Source Select: 3 */
+
+#define ADC12DIV_0             (0x0000)       /* ADC12 Clock Divider Select: 0 */
+#define ADC12DIV_1             (0x0020)       /* ADC12 Clock Divider Select: 1 */
+#define ADC12DIV_2             (0x0040)       /* ADC12 Clock Divider Select: 2 */
+#define ADC12DIV_3             (0x0060)       /* ADC12 Clock Divider Select: 3 */
+#define ADC12DIV_4             (0x0080)       /* ADC12 Clock Divider Select: 4 */
+#define ADC12DIV_5             (0x00A0)       /* ADC12 Clock Divider Select: 5 */
+#define ADC12DIV_6             (0x00C0)       /* ADC12 Clock Divider Select: 6 */
+#define ADC12DIV_7             (0x00E0)       /* ADC12 Clock Divider Select: 7 */
+
+#define ADC12SHS_0             (0x0000)       /* ADC12 Sample/Hold Source: 0 */
+#define ADC12SHS_1             (0x0400)       /* ADC12 Sample/Hold Source: 1 */
+#define ADC12SHS_2             (0x0800)       /* ADC12 Sample/Hold Source: 2 */
+#define ADC12SHS_3             (0x0C00)       /* ADC12 Sample/Hold Source: 3 */
+#define ADC12SHS_4             (0x1000)       /* ADC12 Sample/Hold Source: 4 */
+#define ADC12SHS_5             (0x1400)       /* ADC12 Sample/Hold Source: 5 */
+#define ADC12SHS_6             (0x1800)       /* ADC12 Sample/Hold Source: 6 */
+#define ADC12SHS_7             (0x1C00)       /* ADC12 Sample/Hold Source: 7 */
+
+#define ADC12PDIV_0            (0x0000)       /* ADC12 Clock predivider Select 0 */
+#define ADC12PDIV_1            (0x2000)       /* ADC12 Clock predivider Select 1 */
+#define ADC12PDIV_2            (0x4000)       /* ADC12 Clock predivider Select 2 */
+#define ADC12PDIV_3            (0x6000)       /* ADC12 Clock predivider Select 3 */
+#define ADC12PDIV__1           (0x0000)       /* ADC12 Clock predivider Select: /1 */
+#define ADC12PDIV__4           (0x2000)       /* ADC12 Clock predivider Select: /4 */
+#define ADC12PDIV__32          (0x4000)       /* ADC12 Clock predivider Select: /32 */
+#define ADC12PDIV__64          (0x6000)       /* ADC12 Clock predivider Select: /64 */
+
+/* ADC12CTL2 Control Bits */
+#define ADC12PWRMD             (0x0001)       /* ADC12 Power Mode */
+#define ADC12DF                (0x0008)       /* ADC12 Data Format */
+#define ADC12RES0              (0x0010)       /* ADC12 Resolution Bit: 0 */
+#define ADC12RES1              (0x0020)       /* ADC12 Resolution Bit: 1 */
+
+/* ADC12CTL2 Control Bits */
+#define ADC12PWRMD_L           (0x0001)       /* ADC12 Power Mode */
+#define ADC12DF_L              (0x0008)       /* ADC12 Data Format */
+#define ADC12RES0_L            (0x0010)       /* ADC12 Resolution Bit: 0 */
+#define ADC12RES1_L            (0x0020)       /* ADC12 Resolution Bit: 1 */
+
+#define ADC12RES_0             (0x0000)       /* ADC12+ Resolution : 8 Bit */
+#define ADC12RES_1             (0x0010)       /* ADC12+ Resolution : 10 Bit */
+#define ADC12RES_2             (0x0020)       /* ADC12+ Resolution : 12 Bit */
+#define ADC12RES_3             (0x0030)       /* ADC12+ Resolution : reserved */
+
+#define ADC12RES__8BIT         (0x0000)       /* ADC12+ Resolution : 8 Bit */
+#define ADC12RES__10BIT        (0x0010)       /* ADC12+ Resolution : 10 Bit */
+#define ADC12RES__12BIT        (0x0020)       /* ADC12+ Resolution : 12 Bit */
+
+/* ADC12CTL3 Control Bits */
+#define ADC12CSTARTADD0        (0x0001)       /* ADC12 Conversion Start Address Bit: 0 */
+#define ADC12CSTARTADD1        (0x0002)       /* ADC12 Conversion Start Address Bit: 1 */
+#define ADC12CSTARTADD2        (0x0004)       /* ADC12 Conversion Start Address Bit: 2 */
+#define ADC12CSTARTADD3        (0x0008)       /* ADC12 Conversion Start Address Bit: 3 */
+#define ADC12CSTARTADD4        (0x0010)       /* ADC12 Conversion Start Address Bit: 4 */
+#define ADC12BATMAP            (0x0040)       /* ADC12 Internal AVCC/2 select */
+#define ADC12TCMAP             (0x0080)       /* ADC12 Internal TempSensor select */
+#define ADC12ICH0MAP           (0x0100)       /* ADC12 Internal Channel 0 select */
+#define ADC12ICH1MAP           (0x0200)       /* ADC12 Internal Channel 1 select */
+#define ADC12ICH2MAP           (0x0400)       /* ADC12 Internal Channel 2 select */
+#define ADC12ICH3MAP           (0x0800)       /* ADC12 Internal Channel 3 select */
+
+/* ADC12CTL3 Control Bits */
+#define ADC12CSTARTADD0_L      (0x0001)       /* ADC12 Conversion Start Address Bit: 0 */
+#define ADC12CSTARTADD1_L      (0x0002)       /* ADC12 Conversion Start Address Bit: 1 */
+#define ADC12CSTARTADD2_L      (0x0004)       /* ADC12 Conversion Start Address Bit: 2 */
+#define ADC12CSTARTADD3_L      (0x0008)       /* ADC12 Conversion Start Address Bit: 3 */
+#define ADC12CSTARTADD4_L      (0x0010)       /* ADC12 Conversion Start Address Bit: 4 */
+#define ADC12BATMAP_L          (0x0040)       /* ADC12 Internal AVCC/2 select */
+#define ADC12TCMAP_L           (0x0080)       /* ADC12 Internal TempSensor select */
+
+/* ADC12CTL3 Control Bits */
+#define ADC12ICH0MAP_H         (0x0001)       /* ADC12 Internal Channel 0 select */
+#define ADC12ICH1MAP_H         (0x0002)       /* ADC12 Internal Channel 1 select */
+#define ADC12ICH2MAP_H         (0x0004)       /* ADC12 Internal Channel 2 select */
+#define ADC12ICH3MAP_H         (0x0008)       /* ADC12 Internal Channel 3 select */
+
+#define ADC12CSTARTADD_0       (0x0000)       /* ADC12 Conversion Start Address: 0 */
+#define ADC12CSTARTADD_1       (0x0001)       /* ADC12 Conversion Start Address: 1 */
+#define ADC12CSTARTADD_2       (0x0002)       /* ADC12 Conversion Start Address: 2 */
+#define ADC12CSTARTADD_3       (0x0003)       /* ADC12 Conversion Start Address: 3 */
+#define ADC12CSTARTADD_4       (0x0004)       /* ADC12 Conversion Start Address: 4 */
+#define ADC12CSTARTADD_5       (0x0005)       /* ADC12 Conversion Start Address: 5 */
+#define ADC12CSTARTADD_6       (0x0006)       /* ADC12 Conversion Start Address: 6 */
+#define ADC12CSTARTADD_7       (0x0007)       /* ADC12 Conversion Start Address: 7 */
+#define ADC12CSTARTADD_8       (0x0008)       /* ADC12 Conversion Start Address: 8 */
+#define ADC12CSTARTADD_9       (0x0009)       /* ADC12 Conversion Start Address: 9 */
+#define ADC12CSTARTADD_10      (0x000A)       /* ADC12 Conversion Start Address: 10 */
+#define ADC12CSTARTADD_11      (0x000B)       /* ADC12 Conversion Start Address: 11 */
+#define ADC12CSTARTADD_12      (0x000C)       /* ADC12 Conversion Start Address: 12 */
+#define ADC12CSTARTADD_13      (0x000D)       /* ADC12 Conversion Start Address: 13 */
+#define ADC12CSTARTADD_14      (0x000E)       /* ADC12 Conversion Start Address: 14 */
+#define ADC12CSTARTADD_15      (0x000F)       /* ADC12 Conversion Start Address: 15 */
+#define ADC12CSTARTADD_16      (0x0010)       /* ADC12 Conversion Start Address: 16 */
+#define ADC12CSTARTADD_17      (0x0011)       /* ADC12 Conversion Start Address: 17 */
+#define ADC12CSTARTADD_18      (0x0012)       /* ADC12 Conversion Start Address: 18 */
+#define ADC12CSTARTADD_19      (0x0013)       /* ADC12 Conversion Start Address: 19 */
+#define ADC12CSTARTADD_20      (0x0014)       /* ADC12 Conversion Start Address: 20 */
+#define ADC12CSTARTADD_21      (0x0015)       /* ADC12 Conversion Start Address: 21 */
+#define ADC12CSTARTADD_22      (0x0016)       /* ADC12 Conversion Start Address: 22 */
+#define ADC12CSTARTADD_23      (0x0017)       /* ADC12 Conversion Start Address: 23 */
+#define ADC12CSTARTADD_24      (0x0018)       /* ADC12 Conversion Start Address: 24 */
+#define ADC12CSTARTADD_25      (0x0019)       /* ADC12 Conversion Start Address: 25 */
+#define ADC12CSTARTADD_26      (0x001A)       /* ADC12 Conversion Start Address: 26 */
+#define ADC12CSTARTADD_27      (0x001B)       /* ADC12 Conversion Start Address: 27 */
+#define ADC12CSTARTADD_28      (0x001C)       /* ADC12 Conversion Start Address: 28 */
+#define ADC12CSTARTADD_29      (0x001D)       /* ADC12 Conversion Start Address: 29 */
+#define ADC12CSTARTADD_30      (0x001E)       /* ADC12 Conversion Start Address: 30 */
+#define ADC12CSTARTADD_31      (0x001F)       /* ADC12 Conversion Start Address: 31 */
+
+/* ADC12MCTLx Control Bits */
+#define ADC12INCH0             (0x0001)       /* ADC12 Input Channel Select Bit 0 */
+#define ADC12INCH1             (0x0002)       /* ADC12 Input Channel Select Bit 1 */
+#define ADC12INCH2             (0x0004)       /* ADC12 Input Channel Select Bit 2 */
+#define ADC12INCH3             (0x0008)       /* ADC12 Input Channel Select Bit 3 */
+#define ADC12INCH4             (0x0010)       /* ADC12 Input Channel Select Bit 4 */
+#define ADC12EOS               (0x0080)       /* ADC12 End of Sequence */
+#define ADC12VRSEL0            (0x0100)       /* ADC12 VR Select Bit 0 */
+#define ADC12VRSEL1            (0x0200)       /* ADC12 VR Select Bit 1 */
+#define ADC12VRSEL2            (0x0400)       /* ADC12 VR Select Bit 2 */
+#define ADC12VRSEL3            (0x0800)       /* ADC12 VR Select Bit 3 */
+#define ADC12DIF               (0x2000)       /* ADC12 Differential mode (only for even Registers) */
+#define ADC12WINC              (0x4000)       /* ADC12 Comparator window enable */
+
+/* ADC12MCTLx Control Bits */
+#define ADC12INCH0_L           (0x0001)       /* ADC12 Input Channel Select Bit 0 */
+#define ADC12INCH1_L           (0x0002)       /* ADC12 Input Channel Select Bit 1 */
+#define ADC12INCH2_L           (0x0004)       /* ADC12 Input Channel Select Bit 2 */
+#define ADC12INCH3_L           (0x0008)       /* ADC12 Input Channel Select Bit 3 */
+#define ADC12INCH4_L           (0x0010)       /* ADC12 Input Channel Select Bit 4 */
+#define ADC12EOS_L             (0x0080)       /* ADC12 End of Sequence */
+
+/* ADC12MCTLx Control Bits */
+#define ADC12VRSEL0_H          (0x0001)       /* ADC12 VR Select Bit 0 */
+#define ADC12VRSEL1_H          (0x0002)       /* ADC12 VR Select Bit 1 */
+#define ADC12VRSEL2_H          (0x0004)       /* ADC12 VR Select Bit 2 */
+#define ADC12VRSEL3_H          (0x0008)       /* ADC12 VR Select Bit 3 */
+#define ADC12DIF_H             (0x0020)       /* ADC12 Differential mode (only for even Registers) */
+#define ADC12WINC_H            (0x0040)       /* ADC12 Comparator window enable */
+
+#define ADC12INCH_0            (0x0000)       /* ADC12 Input Channel 0 */
+#define ADC12INCH_1            (0x0001)       /* ADC12 Input Channel 1 */
+#define ADC12INCH_2            (0x0002)       /* ADC12 Input Channel 2 */
+#define ADC12INCH_3            (0x0003)       /* ADC12 Input Channel 3 */
+#define ADC12INCH_4            (0x0004)       /* ADC12 Input Channel 4 */
+#define ADC12INCH_5            (0x0005)       /* ADC12 Input Channel 5 */
+#define ADC12INCH_6            (0x0006)       /* ADC12 Input Channel 6 */
+#define ADC12INCH_7            (0x0007)       /* ADC12 Input Channel 7 */
+#define ADC12INCH_8            (0x0008)       /* ADC12 Input Channel 8 */
+#define ADC12INCH_9            (0x0009)       /* ADC12 Input Channel 9 */
+#define ADC12INCH_10           (0x000A)       /* ADC12 Input Channel 10 */
+#define ADC12INCH_11           (0x000B)       /* ADC12 Input Channel 11 */
+#define ADC12INCH_12           (0x000C)       /* ADC12 Input Channel 12 */
+#define ADC12INCH_13           (0x000D)       /* ADC12 Input Channel 13 */
+#define ADC12INCH_14           (0x000E)       /* ADC12 Input Channel 14 */
+#define ADC12INCH_15           (0x000F)       /* ADC12 Input Channel 15 */
+#define ADC12INCH_16           (0x0010)       /* ADC12 Input Channel 16 */
+#define ADC12INCH_17           (0x0011)       /* ADC12 Input Channel 17 */
+#define ADC12INCH_18           (0x0012)       /* ADC12 Input Channel 18 */
+#define ADC12INCH_19           (0x0013)       /* ADC12 Input Channel 19 */
+#define ADC12INCH_20           (0x0014)       /* ADC12 Input Channel 20 */
+#define ADC12INCH_21           (0x0015)       /* ADC12 Input Channel 21 */
+#define ADC12INCH_22           (0x0016)       /* ADC12 Input Channel 22 */
+#define ADC12INCH_23           (0x0017)       /* ADC12 Input Channel 23 */
+#define ADC12INCH_24           (0x0018)       /* ADC12 Input Channel 24 */
+#define ADC12INCH_25           (0x0019)       /* ADC12 Input Channel 25 */
+#define ADC12INCH_26           (0x001A)       /* ADC12 Input Channel 26 */
+#define ADC12INCH_27           (0x001B)       /* ADC12 Input Channel 27 */
+#define ADC12INCH_28           (0x001C)       /* ADC12 Input Channel 28 */
+#define ADC12INCH_29           (0x001D)       /* ADC12 Input Channel 29 */
+#define ADC12INCH_30           (0x001E)       /* ADC12 Input Channel 30 */
+#define ADC12INCH_31           (0x001F)       /* ADC12 Input Channel 31 */
+
+#define ADC12VRSEL_0           (0x0000)       /* ADC12 Select Reference 0 */
+#define ADC12VRSEL_1           (0x0100)       /* ADC12 Select Reference 1 */
+#define ADC12VRSEL_2           (0x0200)       /* ADC12 Select Reference 2 */
+#define ADC12VRSEL_3           (0x0300)       /* ADC12 Select Reference 3 */
+#define ADC12VRSEL_4           (0x0400)       /* ADC12 Select Reference 4 */
+#define ADC12VRSEL_5           (0x0500)       /* ADC12 Select Reference 5 */
+#define ADC12VRSEL_6           (0x0600)       /* ADC12 Select Reference 6 */
+#define ADC12VRSEL_7           (0x0700)       /* ADC12 Select Reference 7 */
+#define ADC12VRSEL_8           (0x0800)       /* ADC12 Select Reference 8  */
+#define ADC12VRSEL_9           (0x0900)       /* ADC12 Select Reference 9  */
+#define ADC12VRSEL_10          (0x0A00)       /* ADC12 Select Reference 10 */
+#define ADC12VRSEL_11          (0x0B00)       /* ADC12 Select Reference 11 */
+#define ADC12VRSEL_12          (0x0C00)       /* ADC12 Select Reference 12 */
+#define ADC12VRSEL_13          (0x0D00)       /* ADC12 Select Reference 13 */
+#define ADC12VRSEL_14          (0x0E00)       /* ADC12 Select Reference 14 */
+#define ADC12VRSEL_15          (0x0F00)       /* ADC12 Select Reference 15 */
+
+/* ADC12HI Control Bits */
+
+/* ADC12LO Control Bits */
+
+/* ADC12IER0 Control Bits */
+#define ADC12IE0               (0x0001)       /* ADC12 Memory 0 Interrupt Enable */
+#define ADC12IE1               (0x0002)       /* ADC12 Memory 1 Interrupt Enable */
+#define ADC12IE2               (0x0004)       /* ADC12 Memory 2 Interrupt Enable */
+#define ADC12IE3               (0x0008)       /* ADC12 Memory 3 Interrupt Enable */
+#define ADC12IE4               (0x0010)       /* ADC12 Memory 4 Interrupt Enable */
+#define ADC12IE5               (0x0020)       /* ADC12 Memory 5 Interrupt Enable */
+#define ADC12IE6               (0x0040)       /* ADC12 Memory 6 Interrupt Enable */
+#define ADC12IE7               (0x0080)       /* ADC12 Memory 7 Interrupt Enable */
+#define ADC12IE8               (0x0100)       /* ADC12 Memory 8 Interrupt Enable */
+#define ADC12IE9               (0x0200)       /* ADC12 Memory 9 Interrupt Enable */
+#define ADC12IE10              (0x0400)       /* ADC12 Memory 10 Interrupt Enable */
+#define ADC12IE11              (0x0800)       /* ADC12 Memory 11 Interrupt Enable */
+#define ADC12IE12              (0x1000)       /* ADC12 Memory 12 Interrupt Enable */
+#define ADC12IE13              (0x2000)       /* ADC12 Memory 13 Interrupt Enable */
+#define ADC12IE14              (0x4000)       /* ADC12 Memory 14 Interrupt Enable */
+#define ADC12IE15              (0x8000)       /* ADC12 Memory 15 Interrupt Enable */
+
+/* ADC12IER0 Control Bits */
+#define ADC12IE0_L             (0x0001)       /* ADC12 Memory 0 Interrupt Enable */
+#define ADC12IE1_L             (0x0002)       /* ADC12 Memory 1 Interrupt Enable */
+#define ADC12IE2_L             (0x0004)       /* ADC12 Memory 2 Interrupt Enable */
+#define ADC12IE3_L             (0x0008)       /* ADC12 Memory 3 Interrupt Enable */
+#define ADC12IE4_L             (0x0010)       /* ADC12 Memory 4 Interrupt Enable */
+#define ADC12IE5_L             (0x0020)       /* ADC12 Memory 5 Interrupt Enable */
+#define ADC12IE6_L             (0x0040)       /* ADC12 Memory 6 Interrupt Enable */
+#define ADC12IE7_L             (0x0080)       /* ADC12 Memory 7 Interrupt Enable */
+
+/* ADC12IER0 Control Bits */
+#define ADC12IE8_H             (0x0001)       /* ADC12 Memory 8 Interrupt Enable */
+#define ADC12IE9_H             (0x0002)       /* ADC12 Memory 9 Interrupt Enable */
+#define ADC12IE10_H            (0x0004)       /* ADC12 Memory 10 Interrupt Enable */
+#define ADC12IE11_H            (0x0008)       /* ADC12 Memory 11 Interrupt Enable */
+#define ADC12IE12_H            (0x0010)       /* ADC12 Memory 12 Interrupt Enable */
+#define ADC12IE13_H            (0x0020)       /* ADC12 Memory 13 Interrupt Enable */
+#define ADC12IE14_H            (0x0040)       /* ADC12 Memory 14 Interrupt Enable */
+#define ADC12IE15_H            (0x0080)       /* ADC12 Memory 15 Interrupt Enable */
+
+/* ADC12IER1 Control Bits */
+#define ADC12IE16              (0x0001)       /* ADC12 Memory 16 Interrupt Enable */
+#define ADC12IE17              (0x0002)       /* ADC12 Memory 17 Interrupt Enable */
+#define ADC12IE18              (0x0004)       /* ADC12 Memory 18 Interrupt Enable */
+#define ADC12IE19              (0x0008)       /* ADC12 Memory 19 Interrupt Enable */
+#define ADC12IE20              (0x0010)       /* ADC12 Memory 20 Interrupt Enable */
+#define ADC12IE21              (0x0020)       /* ADC12 Memory 21 Interrupt Enable */
+#define ADC12IE22              (0x0040)       /* ADC12 Memory 22 Interrupt Enable */
+#define ADC12IE23              (0x0080)       /* ADC12 Memory 23 Interrupt Enable */
+#define ADC12IE24              (0x0100)       /* ADC12 Memory 24 Interrupt Enable */
+#define ADC12IE25              (0x0200)       /* ADC12 Memory 25 Interrupt Enable */
+#define ADC12IE26              (0x0400)       /* ADC12 Memory 26 Interrupt Enable */
+#define ADC12IE27              (0x0800)       /* ADC12 Memory 27 Interrupt Enable */
+#define ADC12IE28              (0x1000)       /* ADC12 Memory 28 Interrupt Enable */
+#define ADC12IE29              (0x2000)       /* ADC12 Memory 29 Interrupt Enable */
+#define ADC12IE30              (0x4000)       /* ADC12 Memory 30 Interrupt Enable */
+#define ADC12IE31              (0x8000)       /* ADC12 Memory 31 Interrupt Enable */
+
+/* ADC12IER1 Control Bits */
+#define ADC12IE16_L            (0x0001)       /* ADC12 Memory 16 Interrupt Enable */
+#define ADC12IE17_L            (0x0002)       /* ADC12 Memory 17 Interrupt Enable */
+#define ADC12IE18_L            (0x0004)       /* ADC12 Memory 18 Interrupt Enable */
+#define ADC12IE19_L            (0x0008)       /* ADC12 Memory 19 Interrupt Enable */
+#define ADC12IE20_L            (0x0010)       /* ADC12 Memory 20 Interrupt Enable */
+#define ADC12IE21_L            (0x0020)       /* ADC12 Memory 21 Interrupt Enable */
+#define ADC12IE22_L            (0x0040)       /* ADC12 Memory 22 Interrupt Enable */
+#define ADC12IE23_L            (0x0080)       /* ADC12 Memory 23 Interrupt Enable */
+
+/* ADC12IER1 Control Bits */
+#define ADC12IE24_H            (0x0001)       /* ADC12 Memory 24 Interrupt Enable */
+#define ADC12IE25_H            (0x0002)       /* ADC12 Memory 25 Interrupt Enable */
+#define ADC12IE26_H            (0x0004)       /* ADC12 Memory 26 Interrupt Enable */
+#define ADC12IE27_H            (0x0008)       /* ADC12 Memory 27 Interrupt Enable */
+#define ADC12IE28_H            (0x0010)       /* ADC12 Memory 28 Interrupt Enable */
+#define ADC12IE29_H            (0x0020)       /* ADC12 Memory 29 Interrupt Enable */
+#define ADC12IE30_H            (0x0040)       /* ADC12 Memory 30 Interrupt Enable */
+#define ADC12IE31_H            (0x0080)       /* ADC12 Memory 31 Interrupt Enable */
+
+/* ADC12IER2 Control Bits */
+#define ADC12INIE              (0x0002)       /* ADC12 Interrupt enable for the inside of window of the Window comparator */
+#define ADC12LOIE              (0x0004)       /* ADC12 Interrupt enable for lower threshold of the Window comparator */
+#define ADC12HIIE              (0x0008)       /* ADC12 Interrupt enable for upper threshold of the Window comparator */
+#define ADC12OVIE              (0x0010)       /* ADC12 ADC12MEMx Overflow interrupt enable */
+#define ADC12TOVIE             (0x0020)       /* ADC12 Timer Overflow interrupt enable */
+#define ADC12RDYIE             (0x0040)       /* ADC12 local buffered reference ready interrupt enable */
+
+/* ADC12IER2 Control Bits */
+#define ADC12INIE_L            (0x0002)       /* ADC12 Interrupt enable for the inside of window of the Window comparator */
+#define ADC12LOIE_L            (0x0004)       /* ADC12 Interrupt enable for lower threshold of the Window comparator */
+#define ADC12HIIE_L            (0x0008)       /* ADC12 Interrupt enable for upper threshold of the Window comparator */
+#define ADC12OVIE_L            (0x0010)       /* ADC12 ADC12MEMx Overflow interrupt enable */
+#define ADC12TOVIE_L           (0x0020)       /* ADC12 Timer Overflow interrupt enable */
+#define ADC12RDYIE_L           (0x0040)       /* ADC12 local buffered reference ready interrupt enable */
+
+/* ADC12IFGR0 Control Bits */
+#define ADC12IFG0              (0x0001)       /* ADC12 Memory 0 Interrupt Flag */
+#define ADC12IFG1              (0x0002)       /* ADC12 Memory 1 Interrupt Flag */
+#define ADC12IFG2              (0x0004)       /* ADC12 Memory 2 Interrupt Flag */
+#define ADC12IFG3              (0x0008)       /* ADC12 Memory 3 Interrupt Flag */
+#define ADC12IFG4              (0x0010)       /* ADC12 Memory 4 Interrupt Flag */
+#define ADC12IFG5              (0x0020)       /* ADC12 Memory 5 Interrupt Flag */
+#define ADC12IFG6              (0x0040)       /* ADC12 Memory 6 Interrupt Flag */
+#define ADC12IFG7              (0x0080)       /* ADC12 Memory 7 Interrupt Flag */
+#define ADC12IFG8              (0x0100)       /* ADC12 Memory 8 Interrupt Flag */
+#define ADC12IFG9              (0x0200)       /* ADC12 Memory 9 Interrupt Flag */
+#define ADC12IFG10             (0x0400)       /* ADC12 Memory 10 Interrupt Flag */
+#define ADC12IFG11             (0x0800)       /* ADC12 Memory 11 Interrupt Flag */
+#define ADC12IFG12             (0x1000)       /* ADC12 Memory 12 Interrupt Flag */
+#define ADC12IFG13             (0x2000)       /* ADC12 Memory 13 Interrupt Flag */
+#define ADC12IFG14             (0x4000)       /* ADC12 Memory 14 Interrupt Flag */
+#define ADC12IFG15             (0x8000)       /* ADC12 Memory 15 Interrupt Flag */
+
+/* ADC12IFGR0 Control Bits */
+#define ADC12IFG0_L            (0x0001)       /* ADC12 Memory 0 Interrupt Flag */
+#define ADC12IFG1_L            (0x0002)       /* ADC12 Memory 1 Interrupt Flag */
+#define ADC12IFG2_L            (0x0004)       /* ADC12 Memory 2 Interrupt Flag */
+#define ADC12IFG3_L            (0x0008)       /* ADC12 Memory 3 Interrupt Flag */
+#define ADC12IFG4_L            (0x0010)       /* ADC12 Memory 4 Interrupt Flag */
+#define ADC12IFG5_L            (0x0020)       /* ADC12 Memory 5 Interrupt Flag */
+#define ADC12IFG6_L            (0x0040)       /* ADC12 Memory 6 Interrupt Flag */
+#define ADC12IFG7_L            (0x0080)       /* ADC12 Memory 7 Interrupt Flag */
+
+/* ADC12IFGR0 Control Bits */
+#define ADC12IFG8_H            (0x0001)       /* ADC12 Memory 8 Interrupt Flag */
+#define ADC12IFG9_H            (0x0002)       /* ADC12 Memory 9 Interrupt Flag */
+#define ADC12IFG10_H           (0x0004)       /* ADC12 Memory 10 Interrupt Flag */
+#define ADC12IFG11_H           (0x0008)       /* ADC12 Memory 11 Interrupt Flag */
+#define ADC12IFG12_H           (0x0010)       /* ADC12 Memory 12 Interrupt Flag */
+#define ADC12IFG13_H           (0x0020)       /* ADC12 Memory 13 Interrupt Flag */
+#define ADC12IFG14_H           (0x0040)       /* ADC12 Memory 14 Interrupt Flag */
+#define ADC12IFG15_H           (0x0080)       /* ADC12 Memory 15 Interrupt Flag */
+
+/* ADC12IFGR1 Control Bits */
+#define ADC12IFG16             (0x0001)       /* ADC12 Memory 16 Interrupt Flag */
+#define ADC12IFG17             (0x0002)       /* ADC12 Memory 17 Interrupt Flag */
+#define ADC12IFG18             (0x0004)       /* ADC12 Memory 18 Interrupt Flag */
+#define ADC12IFG19             (0x0008)       /* ADC12 Memory 19 Interrupt Flag */
+#define ADC12IFG20             (0x0010)       /* ADC12 Memory 20 Interrupt Flag */
+#define ADC12IFG21             (0x0020)       /* ADC12 Memory 21 Interrupt Flag */
+#define ADC12IFG22             (0x0040)       /* ADC12 Memory 22 Interrupt Flag */
+#define ADC12IFG23             (0x0080)       /* ADC12 Memory 23 Interrupt Flag */
+#define ADC12IFG24             (0x0100)       /* ADC12 Memory 24 Interrupt Flag */
+#define ADC12IFG25             (0x0200)       /* ADC12 Memory 25 Interrupt Flag */
+#define ADC12IFG26             (0x0400)       /* ADC12 Memory 26 Interrupt Flag */
+#define ADC12IFG27             (0x0800)       /* ADC12 Memory 27 Interrupt Flag */
+#define ADC12IFG28             (0x1000)       /* ADC12 Memory 28 Interrupt Flag */
+#define ADC12IFG29             (0x2000)       /* ADC12 Memory 29 Interrupt Flag */
+#define ADC12IFG30             (0x4000)       /* ADC12 Memory 30 Interrupt Flag */
+#define ADC12IFG31             (0x8000)       /* ADC12 Memory 31 Interrupt Flag */
+
+/* ADC12IFGR1 Control Bits */
+#define ADC12IFG16_L           (0x0001)       /* ADC12 Memory 16 Interrupt Flag */
+#define ADC12IFG17_L           (0x0002)       /* ADC12 Memory 17 Interrupt Flag */
+#define ADC12IFG18_L           (0x0004)       /* ADC12 Memory 18 Interrupt Flag */
+#define ADC12IFG19_L           (0x0008)       /* ADC12 Memory 19 Interrupt Flag */
+#define ADC12IFG20_L           (0x0010)       /* ADC12 Memory 20 Interrupt Flag */
+#define ADC12IFG21_L           (0x0020)       /* ADC12 Memory 21 Interrupt Flag */
+#define ADC12IFG22_L           (0x0040)       /* ADC12 Memory 22 Interrupt Flag */
+#define ADC12IFG23_L           (0x0080)       /* ADC12 Memory 23 Interrupt Flag */
+
+/* ADC12IFGR1 Control Bits */
+#define ADC12IFG24_H           (0x0001)       /* ADC12 Memory 24 Interrupt Flag */
+#define ADC12IFG25_H           (0x0002)       /* ADC12 Memory 25 Interrupt Flag */
+#define ADC12IFG26_H           (0x0004)       /* ADC12 Memory 26 Interrupt Flag */
+#define ADC12IFG27_H           (0x0008)       /* ADC12 Memory 27 Interrupt Flag */
+#define ADC12IFG28_H           (0x0010)       /* ADC12 Memory 28 Interrupt Flag */
+#define ADC12IFG29_H           (0x0020)       /* ADC12 Memory 29 Interrupt Flag */
+#define ADC12IFG30_H           (0x0040)       /* ADC12 Memory 30 Interrupt Flag */
+#define ADC12IFG31_H           (0x0080)       /* ADC12 Memory 31 Interrupt Flag */
+
+/* ADC12IFGR2 Control Bits */
+#define ADC12INIFG             (0x0002)       /* ADC12 Interrupt Flag for the inside of window of the Window comparator */
+#define ADC12LOIFG             (0x0004)       /* ADC12 Interrupt Flag for lower threshold of the Window comparator */
+#define ADC12HIIFG             (0x0008)       /* ADC12 Interrupt Flag for upper threshold of the Window comparator */
+#define ADC12OVIFG             (0x0010)       /* ADC12 ADC12MEMx Overflow interrupt Flag */
+#define ADC12TOVIFG            (0x0020)       /* ADC12 Timer Overflow interrupt Flag */
+#define ADC12RDYIFG            (0x0040)       /* ADC12 local buffered reference ready interrupt Flag */
+
+/* ADC12IFGR2 Control Bits */
+#define ADC12INIFG_L           (0x0002)       /* ADC12 Interrupt Flag for the inside of window of the Window comparator */
+#define ADC12LOIFG_L           (0x0004)       /* ADC12 Interrupt Flag for lower threshold of the Window comparator */
+#define ADC12HIIFG_L           (0x0008)       /* ADC12 Interrupt Flag for upper threshold of the Window comparator */
+#define ADC12OVIFG_L           (0x0010)       /* ADC12 ADC12MEMx Overflow interrupt Flag */
+#define ADC12TOVIFG_L          (0x0020)       /* ADC12 Timer Overflow interrupt Flag */
+#define ADC12RDYIFG_L          (0x0040)       /* ADC12 local buffered reference ready interrupt Flag */
+
+/* ADC12IV Definitions */
+#define ADC12IV_NONE           (0x0000)       /* No Interrupt pending */
+#define ADC12IV_ADC12OVIFG     (0x0002)       /* ADC12OVIFG */
+#define ADC12IV_ADC12TOVIFG    (0x0004)       /* ADC12TOVIFG */
+#define ADC12IV_ADC12HIIFG     (0x0006)       /* ADC12HIIFG */
+#define ADC12IV_ADC12LOIFG     (0x0008)       /* ADC12LOIFG */
+#define ADC12IV_ADC12INIFG     (0x000A)       /* ADC12INIFG */
+#define ADC12IV_ADC12IFG0      (0x000C)       /* ADC12IFG0 */
+#define ADC12IV_ADC12IFG1      (0x000E)       /* ADC12IFG1 */
+#define ADC12IV_ADC12IFG2      (0x0010)       /* ADC12IFG2 */
+#define ADC12IV_ADC12IFG3      (0x0012)       /* ADC12IFG3 */
+#define ADC12IV_ADC12IFG4      (0x0014)       /* ADC12IFG4 */
+#define ADC12IV_ADC12IFG5      (0x0016)       /* ADC12IFG5 */
+#define ADC12IV_ADC12IFG6      (0x0018)       /* ADC12IFG6 */
+#define ADC12IV_ADC12IFG7      (0x001A)       /* ADC12IFG7 */
+#define ADC12IV_ADC12IFG8      (0x001C)       /* ADC12IFG8 */
+#define ADC12IV_ADC12IFG9      (0x001E)       /* ADC12IFG9 */
+#define ADC12IV_ADC12IFG10     (0x0020)       /* ADC12IFG10 */
+#define ADC12IV_ADC12IFG11     (0x0022)       /* ADC12IFG11 */
+#define ADC12IV_ADC12IFG12     (0x0024)       /* ADC12IFG12 */
+#define ADC12IV_ADC12IFG13     (0x0026)       /* ADC12IFG13 */
+#define ADC12IV_ADC12IFG14     (0x0028)       /* ADC12IFG14 */
+#define ADC12IV_ADC12IFG15     (0x002A)       /* ADC12IFG15 */
+#define ADC12IV_ADC12IFG16     (0x002C)       /* ADC12IFG16 */
+#define ADC12IV_ADC12IFG17     (0x002E)       /* ADC12IFG17 */
+#define ADC12IV_ADC12IFG18     (0x0030)       /* ADC12IFG18 */
+#define ADC12IV_ADC12IFG19     (0x0032)       /* ADC12IFG19 */
+#define ADC12IV_ADC12IFG20     (0x0034)       /* ADC12IFG20 */
+#define ADC12IV_ADC12IFG21     (0x0036)       /* ADC12IFG21 */
+#define ADC12IV_ADC12IFG22     (0x0038)       /* ADC12IFG22 */
+#define ADC12IV_ADC12IFG23     (0x003A)       /* ADC12IFG23 */
+#define ADC12IV_ADC12IFG24     (0x003C)       /* ADC12IFG24 */
+#define ADC12IV_ADC12IFG25     (0x003E)       /* ADC12IFG25 */
+#define ADC12IV_ADC12IFG26     (0x0040)       /* ADC12IFG26 */
+#define ADC12IV_ADC12IFG27     (0x0042)       /* ADC12IFG27 */
+#define ADC12IV_ADC12IFG28     (0x0044)       /* ADC12IFG28 */
+#define ADC12IV_ADC12IFG29     (0x0046)       /* ADC12IFG29 */
+#define ADC12IV_ADC12IFG30     (0x0048)       /* ADC12IFG30 */
+#define ADC12IV_ADC12IFG31     (0x004A)       /* ADC12IFG31 */
+#define ADC12IV_ADC12RDYIFG    (0x004C)       /* ADC12RDYIFG */
+
+
+/************************************************************
+* AES256 Accelerator
+************************************************************/
+#define __MSP430_HAS_AES256__                 /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_AES256__ 0x09C0
+#define AES256_BASE            __MSP430_BASEADDRESS_AES256__
+
+sfr_w(AESACTL0);                              /* AES accelerator control register 0 */
+sfr_b(AESACTL0_L);                            /* AES accelerator control register 0 */
+sfr_b(AESACTL0_H);                            /* AES accelerator control register 0 */
+sfr_w(AESACTL1);                              /* AES accelerator control register 1 */
+sfr_b(AESACTL1_L);                            /* AES accelerator control register 1 */
+sfr_b(AESACTL1_H);                            /* AES accelerator control register 1 */
+sfr_w(AESASTAT);                              /* AES accelerator status register */
+sfr_b(AESASTAT_L);                            /* AES accelerator status register */
+sfr_b(AESASTAT_H);                            /* AES accelerator status register */
+sfr_w(AESAKEY);                               /* AES accelerator key register */
+sfr_b(AESAKEY_L);                             /* AES accelerator key register */
+sfr_b(AESAKEY_H);                             /* AES accelerator key register */
+sfr_w(AESADIN);                               /* AES accelerator data in register */
+sfr_b(AESADIN_L);                             /* AES accelerator data in register */
+sfr_b(AESADIN_H);                             /* AES accelerator data in register */
+sfr_w(AESADOUT);                              /* AES accelerator data out register  */
+sfr_b(AESADOUT_L);                            /* AES accelerator data out register  */
+sfr_b(AESADOUT_H);                            /* AES accelerator data out register  */
+sfr_w(AESAXDIN);                              /* AES accelerator XORed data in register */
+sfr_b(AESAXDIN_L);                            /* AES accelerator XORed data in register */
+sfr_b(AESAXDIN_H);                            /* AES accelerator XORed data in register */
+sfr_w(AESAXIN);                               /* AES accelerator XORed data in register (no trigger)  */
+sfr_b(AESAXIN_L);                             /* AES accelerator XORed data in register (no trigger)  */
+sfr_b(AESAXIN_H);                             /* AES accelerator XORed data in register (no trigger)  */
+
+/* AESACTL0 Control Bits */
+#define AESOP0                 (0x0001)       /* AES Operation Bit: 0 */
+#define AESOP1                 (0x0002)       /* AES Operation Bit: 1 */
+#define AESKL0                 (0x0004)       /* AES Key length Bit: 0 */
+#define AESKL1                 (0x0008)       /* AES Key length Bit: 1 */
+#define AESTRIG                (0x0010)       /* AES Trigger Select */
+#define AESCM0                 (0x0020)       /* AES Cipher mode select Bit: 0 */
+#define AESCM1                 (0x0040)       /* AES Cipher mode select Bit: 1 */
+#define AESSWRST               (0x0080)       /* AES Software Reset */
+#define AESRDYIFG              (0x0100)       /* AES ready interrupt flag */
+#define AESERRFG               (0x0800)       /* AES Error Flag */
+#define AESRDYIE               (0x1000)       /* AES ready interrupt enable*/
+#define AESCMEN                (0x8000)       /* AES DMA cipher mode enable*/
+
+/* AESACTL0 Control Bits */
+#define AESOP0_L               (0x0001)       /* AES Operation Bit: 0 */
+#define AESOP1_L               (0x0002)       /* AES Operation Bit: 1 */
+#define AESKL0_L               (0x0004)       /* AES Key length Bit: 0 */
+#define AESKL1_L               (0x0008)       /* AES Key length Bit: 1 */
+#define AESTRIG_L              (0x0010)       /* AES Trigger Select */
+#define AESCM0_L               (0x0020)       /* AES Cipher mode select Bit: 0 */
+#define AESCM1_L               (0x0040)       /* AES Cipher mode select Bit: 1 */
+#define AESSWRST_L             (0x0080)       /* AES Software Reset */
+
+/* AESACTL0 Control Bits */
+#define AESRDYIFG_H            (0x0001)       /* AES ready interrupt flag */
+#define AESERRFG_H             (0x0008)       /* AES Error Flag */
+#define AESRDYIE_H             (0x0010)       /* AES ready interrupt enable*/
+#define AESCMEN_H              (0x0080)       /* AES DMA cipher mode enable*/
+
+#define AESOP_0                (0x0000)       /* AES Operation: Encrypt */
+#define AESOP_1                (0x0001)       /* AES Operation: Decrypt (same Key) */
+#define AESOP_2                (0x0002)       /* AES Operation: Generate first round Key */
+#define AESOP_3                (0x0003)       /* AES Operation: Decrypt (first round Key) */
+
+#define AESKL_0                (0x0000)       /* AES Key length: AES128 */
+#define AESKL_1                (0x0004)       /* AES Key length: AES192 */
+#define AESKL_2                (0x0008)       /* AES Key length: AES256 */
+#define AESKL__128             (0x0000)       /* AES Key length: AES128 */
+#define AESKL__192             (0x0004)       /* AES Key length: AES192 */
+#define AESKL__256             (0x0008)       /* AES Key length: AES256 */
+
+#define AESCM_0                (0x0000)       /* AES Cipher mode select: ECB */
+#define AESCM_1                (0x0020)       /* AES Cipher mode select: CBC */
+#define AESCM_2                (0x0040)       /* AES Cipher mode select: OFB */
+#define AESCM_3                (0x0060)       /* AES Cipher mode select: CFB */
+#define AESCM__ECB             (0x0000)       /* AES Cipher mode select: ECB */
+#define AESCM__CBC             (0x0020)       /* AES Cipher mode select: CBC */
+#define AESCM__OFB             (0x0040)       /* AES Cipher mode select: OFB */
+#define AESCM__CFB             (0x0060)       /* AES Cipher mode select: CFB */
+
+/* AESACTL1 Control Bits */
+#define AESBLKCNT0             (0x0001)       /* AES Cipher Block Counter Bit: 0 */
+#define AESBLKCNT1             (0x0002)       /* AES Cipher Block Counter Bit: 1 */
+#define AESBLKCNT2             (0x0004)       /* AES Cipher Block Counter Bit: 2 */
+#define AESBLKCNT3             (0x0008)       /* AES Cipher Block Counter Bit: 3 */
+#define AESBLKCNT4             (0x0010)       /* AES Cipher Block Counter Bit: 4 */
+#define AESBLKCNT5             (0x0020)       /* AES Cipher Block Counter Bit: 5 */
+#define AESBLKCNT6             (0x0040)       /* AES Cipher Block Counter Bit: 6 */
+#define AESBLKCNT7             (0x0080)       /* AES Cipher Block Counter Bit: 7 */
+
+/* AESACTL1 Control Bits */
+#define AESBLKCNT0_L           (0x0001)       /* AES Cipher Block Counter Bit: 0 */
+#define AESBLKCNT1_L           (0x0002)       /* AES Cipher Block Counter Bit: 1 */
+#define AESBLKCNT2_L           (0x0004)       /* AES Cipher Block Counter Bit: 2 */
+#define AESBLKCNT3_L           (0x0008)       /* AES Cipher Block Counter Bit: 3 */
+#define AESBLKCNT4_L           (0x0010)       /* AES Cipher Block Counter Bit: 4 */
+#define AESBLKCNT5_L           (0x0020)       /* AES Cipher Block Counter Bit: 5 */
+#define AESBLKCNT6_L           (0x0040)       /* AES Cipher Block Counter Bit: 6 */
+#define AESBLKCNT7_L           (0x0080)       /* AES Cipher Block Counter Bit: 7 */
+
+/* AESASTAT Control Bits */
+#define AESBUSY                (0x0001)       /* AES Busy */
+#define AESKEYWR               (0x0002)       /* AES All 16 bytes written to AESAKEY */
+#define AESDINWR               (0x0004)       /* AES All 16 bytes written to AESADIN */
+#define AESDOUTRD              (0x0008)       /* AES All 16 bytes read from AESADOUT */
+#define AESKEYCNT0             (0x0010)       /* AES Bytes written via AESAKEY Bit: 0 */
+#define AESKEYCNT1             (0x0020)       /* AES Bytes written via AESAKEY Bit: 1 */
+#define AESKEYCNT2             (0x0040)       /* AES Bytes written via AESAKEY Bit: 2 */
+#define AESKEYCNT3             (0x0080)       /* AES Bytes written via AESAKEY Bit: 3 */
+#define AESDINCNT0             (0x0100)       /* AES Bytes written via AESADIN Bit: 0 */
+#define AESDINCNT1             (0x0200)       /* AES Bytes written via AESADIN Bit: 1 */
+#define AESDINCNT2             (0x0400)       /* AES Bytes written via AESADIN Bit: 2 */
+#define AESDINCNT3             (0x0800)       /* AES Bytes written via AESADIN Bit: 3 */
+#define AESDOUTCNT0            (0x1000)       /* AES Bytes read via AESADOUT Bit: 0 */
+#define AESDOUTCNT1            (0x2000)       /* AES Bytes read via AESADOUT Bit: 1 */
+#define AESDOUTCNT2            (0x4000)       /* AES Bytes read via AESADOUT Bit: 2 */
+#define AESDOUTCNT3            (0x8000)       /* AES Bytes read via AESADOUT Bit: 3 */
+
+/* AESASTAT Control Bits */
+#define AESBUSY_L              (0x0001)       /* AES Busy */
+#define AESKEYWR_L             (0x0002)       /* AES All 16 bytes written to AESAKEY */
+#define AESDINWR_L             (0x0004)       /* AES All 16 bytes written to AESADIN */
+#define AESDOUTRD_L            (0x0008)       /* AES All 16 bytes read from AESADOUT */
+#define AESKEYCNT0_L           (0x0010)       /* AES Bytes written via AESAKEY Bit: 0 */
+#define AESKEYCNT1_L           (0x0020)       /* AES Bytes written via AESAKEY Bit: 1 */
+#define AESKEYCNT2_L           (0x0040)       /* AES Bytes written via AESAKEY Bit: 2 */
+#define AESKEYCNT3_L           (0x0080)       /* AES Bytes written via AESAKEY Bit: 3 */
+
+/* AESASTAT Control Bits */
+#define AESDINCNT0_H           (0x0001)       /* AES Bytes written via AESADIN Bit: 0 */
+#define AESDINCNT1_H           (0x0002)       /* AES Bytes written via AESADIN Bit: 1 */
+#define AESDINCNT2_H           (0x0004)       /* AES Bytes written via AESADIN Bit: 2 */
+#define AESDINCNT3_H           (0x0008)       /* AES Bytes written via AESADIN Bit: 3 */
+#define AESDOUTCNT0_H          (0x0010)       /* AES Bytes read via AESADOUT Bit: 0 */
+#define AESDOUTCNT1_H          (0x0020)       /* AES Bytes read via AESADOUT Bit: 1 */
+#define AESDOUTCNT2_H          (0x0040)       /* AES Bytes read via AESADOUT Bit: 2 */
+#define AESDOUTCNT3_H          (0x0080)       /* AES Bytes read via AESADOUT Bit: 3 */
+
+/************************************************************
+* Capacitive_Touch_IO 0
+************************************************************/
+#define __MSP430_HAS_CAP_TOUCH_IO_0__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_CAP_TOUCH_IO_0__ 0x0430
+#define CAP_TOUCH_0_BASE       __MSP430_BASEADDRESS_CAP_TOUCH_IO_0__
+
+sfr_w(CAPTIO0CTL);                            /* Capacitive_Touch_IO 0 control register */
+sfr_b(CAPTIO0CTL_L);                          /* Capacitive_Touch_IO 0 control register */
+sfr_b(CAPTIO0CTL_H);                          /* Capacitive_Touch_IO 0 control register */
+
+#define  CAPSIO0CTL            CAPTIO0CTL     /* legacy define */
+
+/************************************************************
+* Capacitive_Touch_IO 1
+************************************************************/
+#define __MSP430_HAS_CAP_TOUCH_IO_1__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_CAP_TOUCH_IO_1__ 0x0470
+#define CAP_TOUCH_1_BASE       __MSP430_BASEADDRESS_CAP_TOUCH_IO_1__
+
+sfr_w(CAPTIO1CTL);                            /* Capacitive_Touch_IO 1 control register */
+sfr_b(CAPTIO1CTL_L);                          /* Capacitive_Touch_IO 1 control register */
+sfr_b(CAPTIO1CTL_H);                          /* Capacitive_Touch_IO 1 control register */
+
+#define  CAPSIO1CTL            CAPTIO1CTL     /* legacy define */
+
+/* CAPTIOxCTL Control Bits */
+#define CAPTIOPISEL0           (0x0002)       /* CapTouchIO Pin Select Bit: 0 */
+#define CAPTIOPISEL1           (0x0004)       /* CapTouchIO Pin Select Bit: 1 */
+#define CAPTIOPISEL2           (0x0008)       /* CapTouchIO Pin Select Bit: 2 */
+#define CAPTIOPOSEL0           (0x0010)       /* CapTouchIO Port Select Bit: 0 */
+#define CAPTIOPOSEL1           (0x0020)       /* CapTouchIO Port Select Bit: 1 */
+#define CAPTIOPOSEL2           (0x0040)       /* CapTouchIO Port Select Bit: 2 */
+#define CAPTIOPOSEL3           (0x0080)       /* CapTouchIO Port Select Bit: 3 */
+#define CAPTIOEN               (0x0100)       /* CapTouchIO Enable */
+#define CAPTIO                 (0x0200)       /* CapTouchIO state */
+
+/* CAPTIOxCTL Control Bits */
+#define CAPTIOPISEL0_L         (0x0002)       /* CapTouchIO Pin Select Bit: 0 */
+#define CAPTIOPISEL1_L         (0x0004)       /* CapTouchIO Pin Select Bit: 1 */
+#define CAPTIOPISEL2_L         (0x0008)       /* CapTouchIO Pin Select Bit: 2 */
+#define CAPTIOPOSEL0_L         (0x0010)       /* CapTouchIO Port Select Bit: 0 */
+#define CAPTIOPOSEL1_L         (0x0020)       /* CapTouchIO Port Select Bit: 1 */
+#define CAPTIOPOSEL2_L         (0x0040)       /* CapTouchIO Port Select Bit: 2 */
+#define CAPTIOPOSEL3_L         (0x0080)       /* CapTouchIO Port Select Bit: 3 */
+
+/* CAPTIOxCTL Control Bits */
+#define CAPTIOEN_H             (0x0001)       /* CapTouchIO Enable */
+#define CAPTIO_H               (0x0002)       /* CapTouchIO state */
+
+/* Legacy defines */
+#define CAPSIOPISEL0           (0x0002)       /* CapTouchIO Pin Select Bit: 0 */
+#define CAPSIOPISEL1           (0x0004)       /* CapTouchIO Pin Select Bit: 1 */
+#define CAPSIOPISEL2           (0x0008)       /* CapTouchIO Pin Select Bit: 2 */
+#define CAPSIOPOSEL0           (0x0010)       /* CapTouchIO Port Select Bit: 0 */
+#define CAPSIOPOSEL1           (0x0020)       /* CapTouchIO Port Select Bit: 1 */
+#define CAPSIOPOSEL2           (0x0040)       /* CapTouchIO Port Select Bit: 2 */
+#define CAPSIOPOSEL3           (0x0080)       /* CapTouchIO Port Select Bit: 3 */
+#define CAPSIOEN               (0x0100)       /* CapTouchIO Enable */
+#define CAPSIO                 (0x0200)       /* CapTouchIO state */
+
+/************************************************************
+* Comparator E
+************************************************************/
+#define __MSP430_HAS_COMP_E__                 /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_COMP_E__ 0x08C0
+#define COMP_E_BASE            __MSP430_BASEADDRESS_COMP_E__
+
+sfr_w(CECTL0);                                /* Comparator E Control Register 0 */
+sfr_b(CECTL0_L);                              /* Comparator E Control Register 0 */
+sfr_b(CECTL0_H);                              /* Comparator E Control Register 0 */
+sfr_w(CECTL1);                                /* Comparator E Control Register 1 */
+sfr_b(CECTL1_L);                              /* Comparator E Control Register 1 */
+sfr_b(CECTL1_H);                              /* Comparator E Control Register 1 */
+sfr_w(CECTL2);                                /* Comparator E Control Register 2 */
+sfr_b(CECTL2_L);                              /* Comparator E Control Register 2 */
+sfr_b(CECTL2_H);                              /* Comparator E Control Register 2 */
+sfr_w(CECTL3);                                /* Comparator E Control Register 3 */
+sfr_b(CECTL3_L);                              /* Comparator E Control Register 3 */
+sfr_b(CECTL3_H);                              /* Comparator E Control Register 3 */
+sfr_w(CEINT);                                 /* Comparator E Interrupt Register */
+sfr_b(CEINT_L);                               /* Comparator E Interrupt Register */
+sfr_b(CEINT_H);                               /* Comparator E Interrupt Register */
+sfr_w(CEIV);                                  /* Comparator E Interrupt Vector Word */
+sfr_b(CEIV_L);                                /* Comparator E Interrupt Vector Word */
+sfr_b(CEIV_H);                                /* Comparator E Interrupt Vector Word */
+
+/* CECTL0 Control Bits */
+#define CEIPSEL0               (0x0001)       /* Comp. E Pos. Channel Input Select 0 */
+#define CEIPSEL1               (0x0002)       /* Comp. E Pos. Channel Input Select 1 */
+#define CEIPSEL2               (0x0004)       /* Comp. E Pos. Channel Input Select 2 */
+#define CEIPSEL3               (0x0008)       /* Comp. E Pos. Channel Input Select 3 */
+//#define RESERVED            (0x0010)  /* Comp. E */
+//#define RESERVED            (0x0020)  /* Comp. E */
+//#define RESERVED            (0x0040)  /* Comp. E */
+#define CEIPEN                 (0x0080)       /* Comp. E Pos. Channel Input Enable */
+#define CEIMSEL0               (0x0100)       /* Comp. E Neg. Channel Input Select 0 */
+#define CEIMSEL1               (0x0200)       /* Comp. E Neg. Channel Input Select 1 */
+#define CEIMSEL2               (0x0400)       /* Comp. E Neg. Channel Input Select 2 */
+#define CEIMSEL3               (0x0800)       /* Comp. E Neg. Channel Input Select 3 */
+//#define RESERVED            (0x1000)  /* Comp. E */
+//#define RESERVED            (0x2000)  /* Comp. E */
+//#define RESERVED            (0x4000)  /* Comp. E */
+#define CEIMEN                 (0x8000)       /* Comp. E Neg. Channel Input Enable */
+
+/* CECTL0 Control Bits */
+#define CEIPSEL0_L             (0x0001)       /* Comp. E Pos. Channel Input Select 0 */
+#define CEIPSEL1_L             (0x0002)       /* Comp. E Pos. Channel Input Select 1 */
+#define CEIPSEL2_L             (0x0004)       /* Comp. E Pos. Channel Input Select 2 */
+#define CEIPSEL3_L             (0x0008)       /* Comp. E Pos. Channel Input Select 3 */
+//#define RESERVED            (0x0010)  /* Comp. E */
+//#define RESERVED            (0x0020)  /* Comp. E */
+//#define RESERVED            (0x0040)  /* Comp. E */
+#define CEIPEN_L               (0x0080)       /* Comp. E Pos. Channel Input Enable */
+//#define RESERVED            (0x1000)  /* Comp. E */
+//#define RESERVED            (0x2000)  /* Comp. E */
+//#define RESERVED            (0x4000)  /* Comp. E */
+
+/* CECTL0 Control Bits */
+//#define RESERVED            (0x0010)  /* Comp. E */
+//#define RESERVED            (0x0020)  /* Comp. E */
+//#define RESERVED            (0x0040)  /* Comp. E */
+#define CEIMSEL0_H             (0x0001)       /* Comp. E Neg. Channel Input Select 0 */
+#define CEIMSEL1_H             (0x0002)       /* Comp. E Neg. Channel Input Select 1 */
+#define CEIMSEL2_H             (0x0004)       /* Comp. E Neg. Channel Input Select 2 */
+#define CEIMSEL3_H             (0x0008)       /* Comp. E Neg. Channel Input Select 3 */
+//#define RESERVED            (0x1000)  /* Comp. E */
+//#define RESERVED            (0x2000)  /* Comp. E */
+//#define RESERVED            (0x4000)  /* Comp. E */
+#define CEIMEN_H               (0x0080)       /* Comp. E Neg. Channel Input Enable */
+
+#define CEIPSEL_0              (0x0000)       /* Comp. E V+ terminal Input Select: Channel 0 */
+#define CEIPSEL_1              (0x0001)       /* Comp. E V+ terminal Input Select: Channel 1 */
+#define CEIPSEL_2              (0x0002)       /* Comp. E V+ terminal Input Select: Channel 2 */
+#define CEIPSEL_3              (0x0003)       /* Comp. E V+ terminal Input Select: Channel 3 */
+#define CEIPSEL_4              (0x0004)       /* Comp. E V+ terminal Input Select: Channel 4 */
+#define CEIPSEL_5              (0x0005)       /* Comp. E V+ terminal Input Select: Channel 5 */
+#define CEIPSEL_6              (0x0006)       /* Comp. E V+ terminal Input Select: Channel 6 */
+#define CEIPSEL_7              (0x0007)       /* Comp. E V+ terminal Input Select: Channel 7 */
+#define CEIPSEL_8              (0x0008)       /* Comp. E V+ terminal Input Select: Channel 8 */
+#define CEIPSEL_9              (0x0009)       /* Comp. E V+ terminal Input Select: Channel 9 */
+#define CEIPSEL_10             (0x000A)       /* Comp. E V+ terminal Input Select: Channel 10 */
+#define CEIPSEL_11             (0x000B)       /* Comp. E V+ terminal Input Select: Channel 11 */
+#define CEIPSEL_12             (0x000C)       /* Comp. E V+ terminal Input Select: Channel 12 */
+#define CEIPSEL_13             (0x000D)       /* Comp. E V+ terminal Input Select: Channel 13 */
+#define CEIPSEL_14             (0x000E)       /* Comp. E V+ terminal Input Select: Channel 14 */
+#define CEIPSEL_15             (0x000F)       /* Comp. E V+ terminal Input Select: Channel 15 */
+
+#define CEIMSEL_0              (0x0000)       /* Comp. E V- Terminal Input Select: Channel 0 */
+#define CEIMSEL_1              (0x0100)       /* Comp. E V- Terminal Input Select: Channel 1 */
+#define CEIMSEL_2              (0x0200)       /* Comp. E V- Terminal Input Select: Channel 2 */
+#define CEIMSEL_3              (0x0300)       /* Comp. E V- Terminal Input Select: Channel 3 */
+#define CEIMSEL_4              (0x0400)       /* Comp. E V- Terminal Input Select: Channel 4 */
+#define CEIMSEL_5              (0x0500)       /* Comp. E V- Terminal Input Select: Channel 5 */
+#define CEIMSEL_6              (0x0600)       /* Comp. E V- Terminal Input Select: Channel 6 */
+#define CEIMSEL_7              (0x0700)       /* Comp. E V- Terminal Input Select: Channel 7 */
+#define CEIMSEL_8              (0x0800)       /* Comp. E V- terminal Input Select: Channel 8 */
+#define CEIMSEL_9              (0x0900)       /* Comp. E V- terminal Input Select: Channel 9 */
+#define CEIMSEL_10             (0x0A00)       /* Comp. E V- terminal Input Select: Channel 10 */
+#define CEIMSEL_11             (0x0B00)       /* Comp. E V- terminal Input Select: Channel 11 */
+#define CEIMSEL_12             (0x0C00)       /* Comp. E V- terminal Input Select: Channel 12 */
+#define CEIMSEL_13             (0x0D00)       /* Comp. E V- terminal Input Select: Channel 13 */
+#define CEIMSEL_14             (0x0E00)       /* Comp. E V- terminal Input Select: Channel 14 */
+#define CEIMSEL_15             (0x0F00)       /* Comp. E V- terminal Input Select: Channel 15 */
+
+/* CECTL1 Control Bits */
+#define CEOUT                  (0x0001)       /* Comp. E Output */
+#define CEOUTPOL               (0x0002)       /* Comp. E Output Polarity */
+#define CEF                    (0x0004)       /* Comp. E Enable Output Filter */
+#define CEIES                  (0x0008)       /* Comp. E Interrupt Edge Select */
+#define CESHORT                (0x0010)       /* Comp. E Input Short */
+#define CEEX                   (0x0020)       /* Comp. E Exchange Inputs */
+#define CEFDLY0                (0x0040)       /* Comp. E Filter delay Bit 0 */
+#define CEFDLY1                (0x0080)       /* Comp. E Filter delay Bit 1 */
+#define CEPWRMD0               (0x0100)       /* Comp. E Power mode Bit 0 */
+#define CEPWRMD1               (0x0200)       /* Comp. E Power mode Bit 1 */
+#define CEON                   (0x0400)       /* Comp. E enable */
+#define CEMRVL                 (0x0800)       /* Comp. E CEMRV Level */
+#define CEMRVS                 (0x1000)       /* Comp. E Output selects between VREF0 or VREF1*/
+//#define RESERVED            (0x2000)  /* Comp. E */
+//#define RESERVED            (0x4000)  /* Comp. E */
+//#define RESERVED            (0x8000)  /* Comp. E */
+
+/* CECTL1 Control Bits */
+#define CEOUT_L                (0x0001)       /* Comp. E Output */
+#define CEOUTPOL_L             (0x0002)       /* Comp. E Output Polarity */
+#define CEF_L                  (0x0004)       /* Comp. E Enable Output Filter */
+#define CEIES_L                (0x0008)       /* Comp. E Interrupt Edge Select */
+#define CESHORT_L              (0x0010)       /* Comp. E Input Short */
+#define CEEX_L                 (0x0020)       /* Comp. E Exchange Inputs */
+#define CEFDLY0_L              (0x0040)       /* Comp. E Filter delay Bit 0 */
+#define CEFDLY1_L              (0x0080)       /* Comp. E Filter delay Bit 1 */
+//#define RESERVED            (0x2000)  /* Comp. E */
+//#define RESERVED            (0x4000)  /* Comp. E */
+//#define RESERVED            (0x8000)  /* Comp. E */
+
+/* CECTL1 Control Bits */
+#define CEPWRMD0_H             (0x0001)       /* Comp. E Power mode Bit 0 */
+#define CEPWRMD1_H             (0x0002)       /* Comp. E Power mode Bit 1 */
+#define CEON_H                 (0x0004)       /* Comp. E enable */
+#define CEMRVL_H               (0x0008)       /* Comp. E CEMRV Level */
+#define CEMRVS_H               (0x0010)       /* Comp. E Output selects between VREF0 or VREF1*/
+//#define RESERVED            (0x2000)  /* Comp. E */
+//#define RESERVED            (0x4000)  /* Comp. E */
+//#define RESERVED            (0x8000)  /* Comp. E */
+
+#define CEPWRMD_0              (0x0000)       /* Comp. E Power mode 0 */
+#define CEPWRMD_1              (0x0100)       /* Comp. E Power mode 1 */
+#define CEPWRMD_2              (0x0200)       /* Comp. E Power mode 2 */
+#define CEPWRMD_3              (0x0300)       /* Comp. E Power mode 3*/
+
+#define CEFDLY_0               (0x0000)       /* Comp. E Filter delay 0 : 450ns */
+#define CEFDLY_1               (0x0040)       /* Comp. E Filter delay 1 : 900ns */
+#define CEFDLY_2               (0x0080)       /* Comp. E Filter delay 2 : 1800ns */
+#define CEFDLY_3               (0x00C0)       /* Comp. E Filter delay 3 : 3600ns */
+
+/* CECTL2 Control Bits */
+#define CEREF00                (0x0001)       /* Comp. E Reference 0 Resistor Select Bit : 0 */
+#define CEREF01                (0x0002)       /* Comp. E Reference 0 Resistor Select Bit : 1 */
+#define CEREF02                (0x0004)       /* Comp. E Reference 0 Resistor Select Bit : 2 */
+#define CEREF03                (0x0008)       /* Comp. E Reference 0 Resistor Select Bit : 3 */
+#define CEREF04                (0x0010)       /* Comp. E Reference 0 Resistor Select Bit : 4 */
+#define CERSEL                 (0x0020)       /* Comp. E Reference select */
+#define CERS0                  (0x0040)       /* Comp. E Reference Source Bit : 0 */
+#define CERS1                  (0x0080)       /* Comp. E Reference Source Bit : 1 */
+#define CEREF10                (0x0100)       /* Comp. E Reference 1 Resistor Select Bit : 0 */
+#define CEREF11                (0x0200)       /* Comp. E Reference 1 Resistor Select Bit : 1 */
+#define CEREF12                (0x0400)       /* Comp. E Reference 1 Resistor Select Bit : 2 */
+#define CEREF13                (0x0800)       /* Comp. E Reference 1 Resistor Select Bit : 3 */
+#define CEREF14                (0x1000)       /* Comp. E Reference 1 Resistor Select Bit : 4 */
+#define CEREFL0                (0x2000)       /* Comp. E Reference voltage level Bit : 0 */
+#define CEREFL1                (0x4000)       /* Comp. E Reference voltage level Bit : 1 */
+#define CEREFACC               (0x8000)       /* Comp. E Reference Accuracy */
+
+/* CECTL2 Control Bits */
+#define CEREF00_L              (0x0001)       /* Comp. E Reference 0 Resistor Select Bit : 0 */
+#define CEREF01_L              (0x0002)       /* Comp. E Reference 0 Resistor Select Bit : 1 */
+#define CEREF02_L              (0x0004)       /* Comp. E Reference 0 Resistor Select Bit : 2 */
+#define CEREF03_L              (0x0008)       /* Comp. E Reference 0 Resistor Select Bit : 3 */
+#define CEREF04_L              (0x0010)       /* Comp. E Reference 0 Resistor Select Bit : 4 */
+#define CERSEL_L               (0x0020)       /* Comp. E Reference select */
+#define CERS0_L                (0x0040)       /* Comp. E Reference Source Bit : 0 */
+#define CERS1_L                (0x0080)       /* Comp. E Reference Source Bit : 1 */
+
+/* CECTL2 Control Bits */
+#define CEREF10_H              (0x0001)       /* Comp. E Reference 1 Resistor Select Bit : 0 */
+#define CEREF11_H              (0x0002)       /* Comp. E Reference 1 Resistor Select Bit : 1 */
+#define CEREF12_H              (0x0004)       /* Comp. E Reference 1 Resistor Select Bit : 2 */
+#define CEREF13_H              (0x0008)       /* Comp. E Reference 1 Resistor Select Bit : 3 */
+#define CEREF14_H              (0x0010)       /* Comp. E Reference 1 Resistor Select Bit : 4 */
+#define CEREFL0_H              (0x0020)       /* Comp. E Reference voltage level Bit : 0 */
+#define CEREFL1_H              (0x0040)       /* Comp. E Reference voltage level Bit : 1 */
+#define CEREFACC_H             (0x0080)       /* Comp. E Reference Accuracy */
+
+#define CEREF0_0               (0x0000)       /* Comp. E Int. Ref.0 Select 0 : 1/32 */
+#define CEREF0_1               (0x0001)       /* Comp. E Int. Ref.0 Select 1 : 2/32 */
+#define CEREF0_2               (0x0002)       /* Comp. E Int. Ref.0 Select 2 : 3/32 */
+#define CEREF0_3               (0x0003)       /* Comp. E Int. Ref.0 Select 3 : 4/32 */
+#define CEREF0_4               (0x0004)       /* Comp. E Int. Ref.0 Select 4 : 5/32 */
+#define CEREF0_5               (0x0005)       /* Comp. E Int. Ref.0 Select 5 : 6/32 */
+#define CEREF0_6               (0x0006)       /* Comp. E Int. Ref.0 Select 6 : 7/32 */
+#define CEREF0_7               (0x0007)       /* Comp. E Int. Ref.0 Select 7 : 8/32 */
+#define CEREF0_8               (0x0008)       /* Comp. E Int. Ref.0 Select 0 : 9/32 */
+#define CEREF0_9               (0x0009)       /* Comp. E Int. Ref.0 Select 1 : 10/32 */
+#define CEREF0_10              (0x000A)       /* Comp. E Int. Ref.0 Select 2 : 11/32 */
+#define CEREF0_11              (0x000B)       /* Comp. E Int. Ref.0 Select 3 : 12/32 */
+#define CEREF0_12              (0x000C)       /* Comp. E Int. Ref.0 Select 4 : 13/32 */
+#define CEREF0_13              (0x000D)       /* Comp. E Int. Ref.0 Select 5 : 14/32 */
+#define CEREF0_14              (0x000E)       /* Comp. E Int. Ref.0 Select 6 : 15/32 */
+#define CEREF0_15              (0x000F)       /* Comp. E Int. Ref.0 Select 7 : 16/32 */
+#define CEREF0_16              (0x0010)       /* Comp. E Int. Ref.0 Select 0 : 17/32 */
+#define CEREF0_17              (0x0011)       /* Comp. E Int. Ref.0 Select 1 : 18/32 */
+#define CEREF0_18              (0x0012)       /* Comp. E Int. Ref.0 Select 2 : 19/32 */
+#define CEREF0_19              (0x0013)       /* Comp. E Int. Ref.0 Select 3 : 20/32 */
+#define CEREF0_20              (0x0014)       /* Comp. E Int. Ref.0 Select 4 : 21/32 */
+#define CEREF0_21              (0x0015)       /* Comp. E Int. Ref.0 Select 5 : 22/32 */
+#define CEREF0_22              (0x0016)       /* Comp. E Int. Ref.0 Select 6 : 23/32 */
+#define CEREF0_23              (0x0017)       /* Comp. E Int. Ref.0 Select 7 : 24/32 */
+#define CEREF0_24              (0x0018)       /* Comp. E Int. Ref.0 Select 0 : 25/32 */
+#define CEREF0_25              (0x0019)       /* Comp. E Int. Ref.0 Select 1 : 26/32 */
+#define CEREF0_26              (0x001A)       /* Comp. E Int. Ref.0 Select 2 : 27/32 */
+#define CEREF0_27              (0x001B)       /* Comp. E Int. Ref.0 Select 3 : 28/32 */
+#define CEREF0_28              (0x001C)       /* Comp. E Int. Ref.0 Select 4 : 29/32 */
+#define CEREF0_29              (0x001D)       /* Comp. E Int. Ref.0 Select 5 : 30/32 */
+#define CEREF0_30              (0x001E)       /* Comp. E Int. Ref.0 Select 6 : 31/32 */
+#define CEREF0_31              (0x001F)       /* Comp. E Int. Ref.0 Select 7 : 32/32 */
+
+#define CERS_0                 (0x0000)       /* Comp. E Reference Source 0 : Off */
+#define CERS_1                 (0x0040)       /* Comp. E Reference Source 1 : Vcc */
+#define CERS_2                 (0x0080)       /* Comp. E Reference Source 2 : Shared Ref. */
+#define CERS_3                 (0x00C0)       /* Comp. E Reference Source 3 : Shared Ref. / Off */
+
+#define CEREF1_0               (0x0000)       /* Comp. E Int. Ref.1 Select 0 : 1/32 */
+#define CEREF1_1               (0x0100)       /* Comp. E Int. Ref.1 Select 1 : 2/32 */
+#define CEREF1_2               (0x0200)       /* Comp. E Int. Ref.1 Select 2 : 3/32 */
+#define CEREF1_3               (0x0300)       /* Comp. E Int. Ref.1 Select 3 : 4/32 */
+#define CEREF1_4               (0x0400)       /* Comp. E Int. Ref.1 Select 4 : 5/32 */
+#define CEREF1_5               (0x0500)       /* Comp. E Int. Ref.1 Select 5 : 6/32 */
+#define CEREF1_6               (0x0600)       /* Comp. E Int. Ref.1 Select 6 : 7/32 */
+#define CEREF1_7               (0x0700)       /* Comp. E Int. Ref.1 Select 7 : 8/32 */
+#define CEREF1_8               (0x0800)       /* Comp. E Int. Ref.1 Select 0 : 9/32 */
+#define CEREF1_9               (0x0900)       /* Comp. E Int. Ref.1 Select 1 : 10/32 */
+#define CEREF1_10              (0x0A00)       /* Comp. E Int. Ref.1 Select 2 : 11/32 */
+#define CEREF1_11              (0x0B00)       /* Comp. E Int. Ref.1 Select 3 : 12/32 */
+#define CEREF1_12              (0x0C00)       /* Comp. E Int. Ref.1 Select 4 : 13/32 */
+#define CEREF1_13              (0x0D00)       /* Comp. E Int. Ref.1 Select 5 : 14/32 */
+#define CEREF1_14              (0x0E00)       /* Comp. E Int. Ref.1 Select 6 : 15/32 */
+#define CEREF1_15              (0x0F00)       /* Comp. E Int. Ref.1 Select 7 : 16/32 */
+#define CEREF1_16              (0x1000)       /* Comp. E Int. Ref.1 Select 0 : 17/32 */
+#define CEREF1_17              (0x1100)       /* Comp. E Int. Ref.1 Select 1 : 18/32 */
+#define CEREF1_18              (0x1200)       /* Comp. E Int. Ref.1 Select 2 : 19/32 */
+#define CEREF1_19              (0x1300)       /* Comp. E Int. Ref.1 Select 3 : 20/32 */
+#define CEREF1_20              (0x1400)       /* Comp. E Int. Ref.1 Select 4 : 21/32 */
+#define CEREF1_21              (0x1500)       /* Comp. E Int. Ref.1 Select 5 : 22/32 */
+#define CEREF1_22              (0x1600)       /* Comp. E Int. Ref.1 Select 6 : 23/32 */
+#define CEREF1_23              (0x1700)       /* Comp. E Int. Ref.1 Select 7 : 24/32 */
+#define CEREF1_24              (0x1800)       /* Comp. E Int. Ref.1 Select 0 : 25/32 */
+#define CEREF1_25              (0x1900)       /* Comp. E Int. Ref.1 Select 1 : 26/32 */
+#define CEREF1_26              (0x1A00)       /* Comp. E Int. Ref.1 Select 2 : 27/32 */
+#define CEREF1_27              (0x1B00)       /* Comp. E Int. Ref.1 Select 3 : 28/32 */
+#define CEREF1_28              (0x1C00)       /* Comp. E Int. Ref.1 Select 4 : 29/32 */
+#define CEREF1_29              (0x1D00)       /* Comp. E Int. Ref.1 Select 5 : 30/32 */
+#define CEREF1_30              (0x1E00)       /* Comp. E Int. Ref.1 Select 6 : 31/32 */
+#define CEREF1_31              (0x1F00)       /* Comp. E Int. Ref.1 Select 7 : 32/32 */
+
+#define CEREFL_0               (0x0000)       /* Comp. E Reference voltage level 0 : None */
+#define CEREFL_1               (0x2000)       /* Comp. E Reference voltage level 1 : 1.2V */
+#define CEREFL_2               (0x4000)       /* Comp. E Reference voltage level 2 : 2.0V  */
+#define CEREFL_3               (0x6000)       /* Comp. E Reference voltage level 3 : 2.5V  */
+
+#define CEPD0                  (0x0001)       /* Comp. E Disable Input Buffer of Port Register .0 */
+#define CEPD1                  (0x0002)       /* Comp. E Disable Input Buffer of Port Register .1 */
+#define CEPD2                  (0x0004)       /* Comp. E Disable Input Buffer of Port Register .2 */
+#define CEPD3                  (0x0008)       /* Comp. E Disable Input Buffer of Port Register .3 */
+#define CEPD4                  (0x0010)       /* Comp. E Disable Input Buffer of Port Register .4 */
+#define CEPD5                  (0x0020)       /* Comp. E Disable Input Buffer of Port Register .5 */
+#define CEPD6                  (0x0040)       /* Comp. E Disable Input Buffer of Port Register .6 */
+#define CEPD7                  (0x0080)       /* Comp. E Disable Input Buffer of Port Register .7 */
+#define CEPD8                  (0x0100)       /* Comp. E Disable Input Buffer of Port Register .8 */
+#define CEPD9                  (0x0200)       /* Comp. E Disable Input Buffer of Port Register .9 */
+#define CEPD10                 (0x0400)       /* Comp. E Disable Input Buffer of Port Register .10 */
+#define CEPD11                 (0x0800)       /* Comp. E Disable Input Buffer of Port Register .11 */
+#define CEPD12                 (0x1000)       /* Comp. E Disable Input Buffer of Port Register .12 */
+#define CEPD13                 (0x2000)       /* Comp. E Disable Input Buffer of Port Register .13 */
+#define CEPD14                 (0x4000)       /* Comp. E Disable Input Buffer of Port Register .14 */
+#define CEPD15                 (0x8000)       /* Comp. E Disable Input Buffer of Port Register .15 */
+
+#define CEPD0_L                (0x0001)       /* Comp. E Disable Input Buffer of Port Register .0 */
+#define CEPD1_L                (0x0002)       /* Comp. E Disable Input Buffer of Port Register .1 */
+#define CEPD2_L                (0x0004)       /* Comp. E Disable Input Buffer of Port Register .2 */
+#define CEPD3_L                (0x0008)       /* Comp. E Disable Input Buffer of Port Register .3 */
+#define CEPD4_L                (0x0010)       /* Comp. E Disable Input Buffer of Port Register .4 */
+#define CEPD5_L                (0x0020)       /* Comp. E Disable Input Buffer of Port Register .5 */
+#define CEPD6_L                (0x0040)       /* Comp. E Disable Input Buffer of Port Register .6 */
+#define CEPD7_L                (0x0080)       /* Comp. E Disable Input Buffer of Port Register .7 */
+
+#define CEPD8_H                (0x0001)       /* Comp. E Disable Input Buffer of Port Register .8 */
+#define CEPD9_H                (0x0002)       /* Comp. E Disable Input Buffer of Port Register .9 */
+#define CEPD10_H               (0x0004)       /* Comp. E Disable Input Buffer of Port Register .10 */
+#define CEPD11_H               (0x0008)       /* Comp. E Disable Input Buffer of Port Register .11 */
+#define CEPD12_H               (0x0010)       /* Comp. E Disable Input Buffer of Port Register .12 */
+#define CEPD13_H               (0x0020)       /* Comp. E Disable Input Buffer of Port Register .13 */
+#define CEPD14_H               (0x0040)       /* Comp. E Disable Input Buffer of Port Register .14 */
+#define CEPD15_H               (0x0080)       /* Comp. E Disable Input Buffer of Port Register .15 */
+
+/* CEINT Control Bits */
+#define CEIFG                  (0x0001)       /* Comp. E Interrupt Flag */
+#define CEIIFG                 (0x0002)       /* Comp. E Interrupt Flag Inverted Polarity */
+//#define RESERVED             (0x0004)  /* Comp. E */
+//#define RESERVED             (0x0008)  /* Comp. E */
+#define CERDYIFG               (0x0010)       /* Comp. E Comparator_E ready interrupt flag */
+//#define RESERVED             (0x0020)  /* Comp. E */
+//#define RESERVED             (0x0040)  /* Comp. E */
+//#define RESERVED             (0x0080)  /* Comp. E */
+#define CEIE                   (0x0100)       /* Comp. E Interrupt Enable */
+#define CEIIE                  (0x0200)       /* Comp. E Interrupt Enable Inverted Polarity */
+//#define RESERVED             (0x0400)  /* Comp. E */
+//#define RESERVED             (0x0800)  /* Comp. E */
+#define CERDYIE                (0x1000)       /* Comp. E Comparator_E ready interrupt enable */
+//#define RESERVED             (0x2000)  /* Comp. E */
+//#define RESERVED             (0x4000)  /* Comp. E */
+//#define RESERVED             (0x8000)  /* Comp. E */
+
+/* CEINT Control Bits */
+#define CEIFG_L                (0x0001)       /* Comp. E Interrupt Flag */
+#define CEIIFG_L               (0x0002)       /* Comp. E Interrupt Flag Inverted Polarity */
+//#define RESERVED             (0x0004)  /* Comp. E */
+//#define RESERVED             (0x0008)  /* Comp. E */
+#define CERDYIFG_L             (0x0010)       /* Comp. E Comparator_E ready interrupt flag */
+//#define RESERVED             (0x0020)  /* Comp. E */
+//#define RESERVED             (0x0040)  /* Comp. E */
+//#define RESERVED             (0x0080)  /* Comp. E */
+//#define RESERVED             (0x0400)  /* Comp. E */
+//#define RESERVED             (0x0800)  /* Comp. E */
+//#define RESERVED             (0x2000)  /* Comp. E */
+//#define RESERVED             (0x4000)  /* Comp. E */
+//#define RESERVED             (0x8000)  /* Comp. E */
+
+/* CEINT Control Bits */
+//#define RESERVED             (0x0004)  /* Comp. E */
+//#define RESERVED             (0x0008)  /* Comp. E */
+//#define RESERVED             (0x0020)  /* Comp. E */
+//#define RESERVED             (0x0040)  /* Comp. E */
+//#define RESERVED             (0x0080)  /* Comp. E */
+#define CEIE_H                 (0x0001)       /* Comp. E Interrupt Enable */
+#define CEIIE_H                (0x0002)       /* Comp. E Interrupt Enable Inverted Polarity */
+//#define RESERVED             (0x0400)  /* Comp. E */
+//#define RESERVED             (0x0800)  /* Comp. E */
+#define CERDYIE_H              (0x0010)       /* Comp. E Comparator_E ready interrupt enable */
+//#define RESERVED             (0x2000)  /* Comp. E */
+//#define RESERVED             (0x4000)  /* Comp. E */
+//#define RESERVED             (0x8000)  /* Comp. E */
+
+/* CEIV Definitions */
+#define CEIV_NONE              (0x0000)       /* No Interrupt pending */
+#define CEIV_CEIFG             (0x0002)       /* CEIFG */
+#define CEIV_CEIIFG            (0x0004)       /* CEIIFG */
+#define CEIV_CERDYIFG          (0x000A)       /* CERDYIFG */
+
+/*************************************************************
+* CRC Module
+*************************************************************/
+#define __MSP430_HAS_CRC__                    /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_CRC__ 0x0150
+#define CRC_BASE               __MSP430_BASEADDRESS_CRC__
+
+sfr_w(CRCDI);                                 /* CRC Data In Register */
+sfr_b(CRCDI_L);                               /* CRC Data In Register */
+sfr_b(CRCDI_H);                               /* CRC Data In Register */
+sfr_w(CRCDIRB);                               /* CRC data in reverse byte Register */
+sfr_b(CRCDIRB_L);                             /* CRC data in reverse byte Register */
+sfr_b(CRCDIRB_H);                             /* CRC data in reverse byte Register */
+sfr_w(CRCINIRES);                             /* CRC Initialisation Register and Result Register */
+sfr_b(CRCINIRES_L);                           /* CRC Initialisation Register and Result Register */
+sfr_b(CRCINIRES_H);                           /* CRC Initialisation Register and Result Register */
+sfr_w(CRCRESR);                               /* CRC reverse result Register */
+sfr_b(CRCRESR_L);                             /* CRC reverse result Register */
+sfr_b(CRCRESR_H);                             /* CRC reverse result Register */
+
+/*************************************************************
+* CRC Module
+*************************************************************/
+#define __MSP430_HAS_CRC32__                  /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_CRC32__ 0x0980
+#define CRC32_BASE             __MSP430_BASEADDRESS_CRC32__
+
+
+//sfrl    CRC32DIL0              (0x0980)  /* CRC32 Data In */
+sfr_w(CRC32DIW0);                             /* CRC32 Data In */
+sfr_b(CRC32DIW0_L);                           /* CRC32 Data In */
+sfr_b(CRC32DIW0_H);                           /* CRC32 Data In */
+sfr_w(CRC32DIW1);                             /* CRC32 Data In */
+sfr_b(CRC32DIW1_L);                           /* CRC32 Data In */
+sfr_b(CRC32DIW1_H);                           /* CRC32 Data In */
+#define CRC32DIB0              CRC32DIW0_L
+
+//sfrl    CRC32DIRBL0            (0x0984)  /* CRC32 Data In Reversed Bit */
+sfr_w(CRC32DIRBW1);                           /* CRC32 Data In Reversed Bit */
+sfr_b(CRC32DIRBW1_L);                         /* CRC32 Data In Reversed Bit */
+sfr_b(CRC32DIRBW1_H);                         /* CRC32 Data In Reversed Bit */
+sfr_w(CRC32DIRBW0);                           /* CRC32 Data In Reversed Bit */
+sfr_b(CRC32DIRBW0_L);                         /* CRC32 Data In Reversed Bit */
+sfr_b(CRC32DIRBW0_H);                         /* CRC32 Data In Reversed Bit */
+#define CRC32DIRBB0            CRC32DIRBW0_H
+
+//sfrl    CRC32INIRESL0          (0x0988)  /* CRC32 Initialization and Result */
+sfr_w(CRC32INIRESW0);                         /* CRC32 Initialization and Result */
+sfr_b(CRC32INIRESW0_L);                       /* CRC32 Initialization and Result */
+sfr_b(CRC32INIRESW0_H);                       /* CRC32 Initialization and Result */
+sfr_w(CRC32INIRESW1);                         /* CRC32 Initialization and Result */
+sfr_b(CRC32INIRESW1_L);                       /* CRC32 Initialization and Result */
+sfr_b(CRC32INIRESW1_H);                       /* CRC32 Initialization and Result */
+#define CRC32RESB0             CRC32INIRESW0_L
+#define CRC32RESB1             CRC32INIRESW0_H
+#define CRC32RESB2             CRC32INIRESW1_L
+#define CRC32RESB3             CRC32INIRESW1_H
+
+//sfrl    CRC32RESRL0            (0x098C)  /* CRC32 Result Reverse */
+sfr_w(CRC32RESRW1);                           /* CRC32 Result Reverse */
+sfr_b(CRC32RESRW1_L);                         /* CRC32 Result Reverse */
+sfr_b(CRC32RESRW1_H);                         /* CRC32 Result Reverse */
+sfr_w(CRC32RESRW0);                           /* CRC32 Result Reverse */
+sfr_b(CRC32RESRW0_L);                         /* CRC32 Result Reverse */
+sfr_b(CRC32RESRW0_H);                         /* CRC32 Result Reverse */
+#define CRC32RESRB3            CRC32RESRW1_L
+#define CRC32RESRB2            CRC32RESRW1_H
+#define CRC32RESRB1            CRC32RESRW0_L
+#define CRC32RESRB0            CRC32RESRW0_H
+
+//sfrl    CRC16DIL0              (0x0990)  /* CRC16 Data Input */
+sfr_w(CRC16DIW0);                             /* CRC16 Data Input */
+sfr_b(CRC16DIW0_L);                           /* CRC16 Data Input */
+sfr_b(CRC16DIW0_H);                           /* CRC16 Data Input */
+sfr_w(CRC16DIW1);                             /* CRC16 Data Input */
+sfr_b(CRC16DIW1_L);                           /* CRC16 Data Input */
+sfr_b(CRC16DIW1_H);                           /* CRC16 Data Input */
+#define CRC16DIB0              CRC16DIW0_L
+//sfrl    CRC16DIRBL0            (0x0994)  /* CRC16 Data In Reverse */
+sfr_w(CRC16DIRBW1);                           /* CRC16 Data In Reverse */
+sfr_b(CRC16DIRBW1_L);                         /* CRC16 Data In Reverse */
+sfr_b(CRC16DIRBW1_H);                         /* CRC16 Data In Reverse */
+sfr_w(CRC16DIRBW0);                           /* CRC16 Data In Reverse */
+sfr_b(CRC16DIRBW0_L);                         /* CRC16 Data In Reverse */
+sfr_b(CRC16DIRBW0_H);                         /* CRC16 Data In Reverse */
+#define CRC16DIRBB0            CRC16DIRBW0_L
+
+//sfrl    CRC16INIRESL0          (0x0998)  /* CRC16 Init and Result */
+sfr_w(CRC16INIRESW0);                         /* CRC16 Init and Result */
+sfr_b(CRC16INIRESW0_L);                       /* CRC16 Init and Result */
+sfr_b(CRC16INIRESW0_H);                       /* CRC16 Init and Result */
+#define CRC16INIRESB1          CRC16INIRESW0_H
+#define CRC16INIRESB0          CRC16INIRESW0_L
+
+//sfrl    CRC16RESRL0            (0x099E)  /* CRC16 Result Reverse */
+sfr_w(CRC16RESRW0);                           /* CRC16 Result Reverse */
+sfr_b(CRC16RESRW0_L);                         /* CRC16 Result Reverse */
+sfr_b(CRC16RESRW0_H);                         /* CRC16 Result Reverse */
+sfr_w(CRC16RESRW1);                           /* CRC16 Result Reverse */
+sfr_b(CRC16RESRW1_L);                         /* CRC16 Result Reverse */
+sfr_b(CRC16RESRW1_H);                         /* CRC16 Result Reverse */
+#define CRC16RESRB1            CRC16RESRW0_L
+#define CRC16RESRB0            CRC16RESRW0_H
+
+/************************************************************
+* CLOCK SYSTEM
+************************************************************/
+#define __MSP430_HAS_CS__                     /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_CS__ 0x0160
+#define CS_BASE                __MSP430_BASEADDRESS_CS__
+
+sfr_w(CSCTL0);                                /* CS Control Register 0 */
+sfr_b(CSCTL0_L);                              /* CS Control Register 0 */
+sfr_b(CSCTL0_H);                              /* CS Control Register 0 */
+sfr_w(CSCTL1);                                /* CS Control Register 1 */
+sfr_b(CSCTL1_L);                              /* CS Control Register 1 */
+sfr_b(CSCTL1_H);                              /* CS Control Register 1 */
+sfr_w(CSCTL2);                                /* CS Control Register 2 */
+sfr_b(CSCTL2_L);                              /* CS Control Register 2 */
+sfr_b(CSCTL2_H);                              /* CS Control Register 2 */
+sfr_w(CSCTL3);                                /* CS Control Register 3 */
+sfr_b(CSCTL3_L);                              /* CS Control Register 3 */
+sfr_b(CSCTL3_H);                              /* CS Control Register 3 */
+sfr_w(CSCTL4);                                /* CS Control Register 4 */
+sfr_b(CSCTL4_L);                              /* CS Control Register 4 */
+sfr_b(CSCTL4_H);                              /* CS Control Register 4 */
+sfr_w(CSCTL5);                                /* CS Control Register 5 */
+sfr_b(CSCTL5_L);                              /* CS Control Register 5 */
+sfr_b(CSCTL5_H);                              /* CS Control Register 5 */
+sfr_w(CSCTL6);                                /* CS Control Register 6 */
+sfr_b(CSCTL6_L);                              /* CS Control Register 6 */
+sfr_b(CSCTL6_H);                              /* CS Control Register 6 */
+
+/* CSCTL0 Control Bits */
+
+#define CSKEY                  (0xA500)       /* CS Password */
+#define CSKEY_H                (0xA5)         /* CS Password for high byte access */
+
+/* CSCTL1 Control Bits */
+#define DCOFSEL0               (0x0002)       /* DCO frequency select Bit: 0 */
+#define DCOFSEL1               (0x0004)       /* DCO frequency select Bit: 1 */
+#define DCOFSEL2               (0x0008)       /* DCO frequency select Bit: 2 */
+#define DCORSEL                (0x0040)       /* DCO range select. */
+
+/* CSCTL1 Control Bits */
+#define DCOFSEL0_L             (0x0002)       /* DCO frequency select Bit: 0 */
+#define DCOFSEL1_L             (0x0004)       /* DCO frequency select Bit: 1 */
+#define DCOFSEL2_L             (0x0008)       /* DCO frequency select Bit: 2 */
+#define DCORSEL_L              (0x0040)       /* DCO range select. */
+
+#define DCOFSEL_0              (0x0000)       /* DCO frequency select: 0 */
+#define DCOFSEL_1              (0x0002)       /* DCO frequency select: 1 */
+#define DCOFSEL_2              (0x0004)       /* DCO frequency select: 2 */
+#define DCOFSEL_3              (0x0006)       /* DCO frequency select: 3 */
+#define DCOFSEL_4              (0x0008)       /* DCO frequency select: 4 */
+#define DCOFSEL_5              (0x000A)       /* DCO frequency select: 5 */
+#define DCOFSEL_6              (0x000C)       /* DCO frequency select: 6 */
+#define DCOFSEL_7              (0x000E)       /* DCO frequency select: 7 */
+
+/* CSCTL2 Control Bits */
+#define SELM0                  (0x0001)       /* MCLK Source Select Bit: 0 */
+#define SELM1                  (0x0002)       /* MCLK Source Select Bit: 1 */
+#define SELM2                  (0x0004)       /* MCLK Source Select Bit: 2 */
+//#define RESERVED            (0x0004)    /* RESERVED */
+//#define RESERVED            (0x0008)    /* RESERVED */
+#define SELS0                  (0x0010)       /* SMCLK Source Select Bit: 0 */
+#define SELS1                  (0x0020)       /* SMCLK Source Select Bit: 1 */
+#define SELS2                  (0x0040)       /* SMCLK Source Select Bit: 2 */
+//#define RESERVED            (0x0040)    /* RESERVED */
+//#define RESERVED            (0x0080)    /* RESERVED */
+#define SELA0                  (0x0100)       /* ACLK Source Select Bit: 0 */
+#define SELA1                  (0x0200)       /* ACLK Source Select Bit: 1 */
+#define SELA2                  (0x0400)       /* ACLK Source Select Bit: 2 */
+//#define RESERVED            (0x0400)    /* RESERVED */
+//#define RESERVED            (0x0800)    /* RESERVED */
+//#define RESERVED            (0x1000)    /* RESERVED */
+//#define RESERVED            (0x2000)    /* RESERVED */
+//#define RESERVED            (0x4000)    /* RESERVED */
+//#define RESERVED            (0x8000)    /* RESERVED */
+
+/* CSCTL2 Control Bits */
+#define SELM0_L                (0x0001)       /* MCLK Source Select Bit: 0 */
+#define SELM1_L                (0x0002)       /* MCLK Source Select Bit: 1 */
+#define SELM2_L                (0x0004)       /* MCLK Source Select Bit: 2 */
+//#define RESERVED            (0x0004)    /* RESERVED */
+//#define RESERVED            (0x0008)    /* RESERVED */
+#define SELS0_L                (0x0010)       /* SMCLK Source Select Bit: 0 */
+#define SELS1_L                (0x0020)       /* SMCLK Source Select Bit: 1 */
+#define SELS2_L                (0x0040)       /* SMCLK Source Select Bit: 2 */
+//#define RESERVED            (0x0040)    /* RESERVED */
+//#define RESERVED            (0x0080)    /* RESERVED */
+//#define RESERVED            (0x0400)    /* RESERVED */
+//#define RESERVED            (0x0800)    /* RESERVED */
+//#define RESERVED            (0x1000)    /* RESERVED */
+//#define RESERVED            (0x2000)    /* RESERVED */
+//#define RESERVED            (0x4000)    /* RESERVED */
+//#define RESERVED            (0x8000)    /* RESERVED */
+
+/* CSCTL2 Control Bits */
+//#define RESERVED            (0x0004)    /* RESERVED */
+//#define RESERVED            (0x0008)    /* RESERVED */
+//#define RESERVED            (0x0040)    /* RESERVED */
+//#define RESERVED            (0x0080)    /* RESERVED */
+#define SELA0_H                (0x0001)       /* ACLK Source Select Bit: 0 */
+#define SELA1_H                (0x0002)       /* ACLK Source Select Bit: 1 */
+#define SELA2_H                (0x0004)       /* ACLK Source Select Bit: 2 */
+//#define RESERVED            (0x0400)    /* RESERVED */
+//#define RESERVED            (0x0800)    /* RESERVED */
+//#define RESERVED            (0x1000)    /* RESERVED */
+//#define RESERVED            (0x2000)    /* RESERVED */
+//#define RESERVED            (0x4000)    /* RESERVED */
+//#define RESERVED            (0x8000)    /* RESERVED */
+
+#define SELM_0                 (0x0000)       /* MCLK Source Select 0 */
+#define SELM_1                 (0x0001)       /* MCLK Source Select 1 */
+#define SELM_2                 (0x0002)       /* MCLK Source Select 2 */
+#define SELM_3                 (0x0003)       /* MCLK Source Select 3 */
+#define SELM_4                 (0x0004)       /* MCLK Source Select 4 */
+#define SELM_5                 (0x0005)       /* MCLK Source Select 5 */
+#define SELM_6                 (0x0006)       /* MCLK Source Select 6 */
+#define SELM_7                 (0x0007)       /* MCLK Source Select 7 */
+#define SELM__LFXTCLK          (0x0000)       /* MCLK Source Select LFXTCLK */
+#define SELM__VLOCLK           (0x0001)       /* MCLK Source Select VLOCLK */
+#define SELM__LFMODCLK         (0x0002)       /* MCLK Source Select LFMODOSC */
+#define SELM__LFMODOSC         (0x0002)       /* MCLK Source Select LFMODOSC (legacy) */
+#define SELM__DCOCLK           (0x0003)       /* MCLK Source Select DCOCLK */
+#define SELM__MODCLK           (0x0004)       /* MCLK Source Select MODOSC */
+#define SELM__MODOSC           (0x0004)       /* MCLK Source Select MODOSC (legacy) */
+#define SELM__HFXTCLK          (0x0005)       /* MCLK Source Select HFXTCLK */
+
+#define SELS_0                 (0x0000)       /* SMCLK Source Select 0 */
+#define SELS_1                 (0x0010)       /* SMCLK Source Select 1 */
+#define SELS_2                 (0x0020)       /* SMCLK Source Select 2 */
+#define SELS_3                 (0x0030)       /* SMCLK Source Select 3 */
+#define SELS_4                 (0x0040)       /* SMCLK Source Select 4 */
+#define SELS_5                 (0x0050)       /* SMCLK Source Select 5 */
+#define SELS_6                 (0x0060)       /* SMCLK Source Select 6 */
+#define SELS_7                 (0x0070)       /* SMCLK Source Select 7 */
+#define SELS__LFXTCLK          (0x0000)       /* SMCLK Source Select LFXTCLK */
+#define SELS__VLOCLK           (0x0010)       /* SMCLK Source Select VLOCLK */
+#define SELS__LFMODCLK         (0x0020)       /* SMCLK Source Select LFMODOSC */
+#define SELS__LFMODOSC         (0x0020)       /* SMCLK Source Select LFMODOSC (legacy) */
+#define SELS__DCOCLK           (0x0030)       /* SMCLK Source Select DCOCLK */
+#define SELS__MODCLK           (0x0040)       /* SMCLK Source Select MODOSC */
+#define SELS__MODOSC           (0x0040)       /* SMCLK Source Select MODOSC (legacy) */
+#define SELS__HFXTCLK          (0x0050)       /* SMCLK Source Select HFXTCLK */
+
+#define SELA_0                 (0x0000)       /* ACLK Source Select 0 */
+#define SELA_1                 (0x0100)       /* ACLK Source Select 1 */
+#define SELA_2                 (0x0200)       /* ACLK Source Select 2 */
+#define SELA_3                 (0x0300)       /* ACLK Source Select 3 */
+#define SELA_4                 (0x0400)       /* ACLK Source Select 4 */
+#define SELA_5                 (0x0500)       /* ACLK Source Select 5 */
+#define SELA_6                 (0x0600)       /* ACLK Source Select 6 */
+#define SELA_7                 (0x0700)       /* ACLK Source Select 7 */
+#define SELA__LFXTCLK          (0x0000)       /* ACLK Source Select LFXTCLK */
+#define SELA__VLOCLK           (0x0100)       /* ACLK Source Select VLOCLK */
+#define SELA__LFMODCLK         (0x0200)       /* ACLK Source Select LFMODOSC */
+#define SELA__LFMODOSC         (0x0200)       /* ACLK Source Select LFMODOSC (legacy) */
+
+/* CSCTL3 Control Bits */
+#define DIVM0                  (0x0001)       /* MCLK Divider Bit: 0 */
+#define DIVM1                  (0x0002)       /* MCLK Divider Bit: 1 */
+#define DIVM2                  (0x0004)       /* MCLK Divider Bit: 2 */
+//#define RESERVED            (0x0004)    /* RESERVED */
+//#define RESERVED            (0x0008)    /* RESERVED */
+#define DIVS0                  (0x0010)       /* SMCLK Divider Bit: 0 */
+#define DIVS1                  (0x0020)       /* SMCLK Divider Bit: 1 */
+#define DIVS2                  (0x0040)       /* SMCLK Divider Bit: 2 */
+//#define RESERVED            (0x0040)    /* RESERVED */
+//#define RESERVED            (0x0080)    /* RESERVED */
+#define DIVA0                  (0x0100)       /* ACLK Divider Bit: 0 */
+#define DIVA1                  (0x0200)       /* ACLK Divider Bit: 1 */
+#define DIVA2                  (0x0400)       /* ACLK Divider Bit: 2 */
+//#define RESERVED            (0x0400)    /* RESERVED */
+//#define RESERVED            (0x0800)    /* RESERVED */
+//#define RESERVED            (0x1000)    /* RESERVED */
+//#define RESERVED            (0x2000)    /* RESERVED */
+//#define RESERVED            (0x4000)    /* RESERVED */
+//#define RESERVED            (0x8000)    /* RESERVED */
+
+/* CSCTL3 Control Bits */
+#define DIVM0_L                (0x0001)       /* MCLK Divider Bit: 0 */
+#define DIVM1_L                (0x0002)       /* MCLK Divider Bit: 1 */
+#define DIVM2_L                (0x0004)       /* MCLK Divider Bit: 2 */
+//#define RESERVED            (0x0004)    /* RESERVED */
+//#define RESERVED            (0x0008)    /* RESERVED */
+#define DIVS0_L                (0x0010)       /* SMCLK Divider Bit: 0 */
+#define DIVS1_L                (0x0020)       /* SMCLK Divider Bit: 1 */
+#define DIVS2_L                (0x0040)       /* SMCLK Divider Bit: 2 */
+//#define RESERVED            (0x0040)    /* RESERVED */
+//#define RESERVED            (0x0080)    /* RESERVED */
+//#define RESERVED            (0x0400)    /* RESERVED */
+//#define RESERVED            (0x0800)    /* RESERVED */
+//#define RESERVED            (0x1000)    /* RESERVED */
+//#define RESERVED            (0x2000)    /* RESERVED */
+//#define RESERVED            (0x4000)    /* RESERVED */
+//#define RESERVED            (0x8000)    /* RESERVED */
+
+/* CSCTL3 Control Bits */
+//#define RESERVED            (0x0004)    /* RESERVED */
+//#define RESERVED            (0x0008)    /* RESERVED */
+//#define RESERVED            (0x0040)    /* RESERVED */
+//#define RESERVED            (0x0080)    /* RESERVED */
+#define DIVA0_H                (0x0001)       /* ACLK Divider Bit: 0 */
+#define DIVA1_H                (0x0002)       /* ACLK Divider Bit: 1 */
+#define DIVA2_H                (0x0004)       /* ACLK Divider Bit: 2 */
+//#define RESERVED            (0x0400)    /* RESERVED */
+//#define RESERVED            (0x0800)    /* RESERVED */
+//#define RESERVED            (0x1000)    /* RESERVED */
+//#define RESERVED            (0x2000)    /* RESERVED */
+//#define RESERVED            (0x4000)    /* RESERVED */
+//#define RESERVED            (0x8000)    /* RESERVED */
+
+#define DIVM_0                 (0x0000)       /* MCLK Source Divider 0 */
+#define DIVM_1                 (0x0001)       /* MCLK Source Divider 1 */
+#define DIVM_2                 (0x0002)       /* MCLK Source Divider 2 */
+#define DIVM_3                 (0x0003)       /* MCLK Source Divider 3 */
+#define DIVM_4                 (0x0004)       /* MCLK Source Divider 4 */
+#define DIVM_5                 (0x0005)       /* MCLK Source Divider 5 */
+#define DIVM__1                (0x0000)       /* MCLK Source Divider f(MCLK)/1 */
+#define DIVM__2                (0x0001)       /* MCLK Source Divider f(MCLK)/2 */
+#define DIVM__4                (0x0002)       /* MCLK Source Divider f(MCLK)/4 */
+#define DIVM__8                (0x0003)       /* MCLK Source Divider f(MCLK)/8 */
+#define DIVM__16               (0x0004)       /* MCLK Source Divider f(MCLK)/16 */
+#define DIVM__32               (0x0005)       /* MCLK Source Divider f(MCLK)/32 */
+
+#define DIVS_0                 (0x0000)       /* SMCLK Source Divider 0 */
+#define DIVS_1                 (0x0010)       /* SMCLK Source Divider 1 */
+#define DIVS_2                 (0x0020)       /* SMCLK Source Divider 2 */
+#define DIVS_3                 (0x0030)       /* SMCLK Source Divider 3 */
+#define DIVS_4                 (0x0040)       /* SMCLK Source Divider 4 */
+#define DIVS_5                 (0x0050)       /* SMCLK Source Divider 5 */
+#define DIVS__1                (0x0000)       /* SMCLK Source Divider f(SMCLK)/1 */
+#define DIVS__2                (0x0010)       /* SMCLK Source Divider f(SMCLK)/2 */
+#define DIVS__4                (0x0020)       /* SMCLK Source Divider f(SMCLK)/4 */
+#define DIVS__8                (0x0030)       /* SMCLK Source Divider f(SMCLK)/8 */
+#define DIVS__16               (0x0040)       /* SMCLK Source Divider f(SMCLK)/16 */
+#define DIVS__32               (0x0050)       /* SMCLK Source Divider f(SMCLK)/32 */
+
+#define DIVA_0                 (0x0000)       /* ACLK Source Divider 0 */
+#define DIVA_1                 (0x0100)       /* ACLK Source Divider 1 */
+#define DIVA_2                 (0x0200)       /* ACLK Source Divider 2 */
+#define DIVA_3                 (0x0300)       /* ACLK Source Divider 3 */
+#define DIVA_4                 (0x0400)       /* ACLK Source Divider 4 */
+#define DIVA_5                 (0x0500)       /* ACLK Source Divider 5 */
+#define DIVA__1                (0x0000)       /* ACLK Source Divider f(ACLK)/1 */
+#define DIVA__2                (0x0100)       /* ACLK Source Divider f(ACLK)/2 */
+#define DIVA__4                (0x0200)       /* ACLK Source Divider f(ACLK)/4 */
+#define DIVA__8                (0x0300)       /* ACLK Source Divider f(ACLK)/8 */
+#define DIVA__16               (0x0400)       /* ACLK Source Divider f(ACLK)/16 */
+#define DIVA__32               (0x0500)       /* ACLK Source Divider f(ACLK)/32 */
+
+/* CSCTL4 Control Bits */
+#define LFXTOFF                (0x0001)       /* Low Frequency Oscillator (LFXT) disable */
+#define SMCLKOFF               (0x0002)       /* SMCLK Off */
+#define VLOOFF                 (0x0008)       /* VLO Off */
+#define LFXTBYPASS             (0x0010)       /* LFXT bypass mode : 0: internal 1:sourced from external pin */
+#define LFXTDRIVE0             (0x0040)       /* LFXT Drive Level mode Bit 0 */
+#define LFXTDRIVE1             (0x0080)       /* LFXT Drive Level mode Bit 1 */
+#define HFXTOFF                (0x0100)       /* High Frequency Oscillator disable */
+#define HFFREQ0                (0x0400)       /* HFXT frequency selection Bit 1 */
+#define HFFREQ1                (0x0800)       /* HFXT frequency selection Bit 0 */
+#define HFXTBYPASS             (0x1000)       /* HFXT bypass mode : 0: internal 1:sourced from external pin */
+#define HFXTDRIVE0             (0x4000)       /* HFXT Drive Level mode Bit 0 */
+#define HFXTDRIVE1             (0x8000)       /* HFXT Drive Level mode Bit 1 */
+
+/* CSCTL4 Control Bits */
+#define LFXTOFF_L              (0x0001)       /* Low Frequency Oscillator (LFXT) disable */
+#define SMCLKOFF_L             (0x0002)       /* SMCLK Off */
+#define VLOOFF_L               (0x0008)       /* VLO Off */
+#define LFXTBYPASS_L           (0x0010)       /* LFXT bypass mode : 0: internal 1:sourced from external pin */
+#define LFXTDRIVE0_L           (0x0040)       /* LFXT Drive Level mode Bit 0 */
+#define LFXTDRIVE1_L           (0x0080)       /* LFXT Drive Level mode Bit 1 */
+
+/* CSCTL4 Control Bits */
+#define HFXTOFF_H              (0x0001)       /* High Frequency Oscillator disable */
+#define HFFREQ0_H              (0x0004)       /* HFXT frequency selection Bit 1 */
+#define HFFREQ1_H              (0x0008)       /* HFXT frequency selection Bit 0 */
+#define HFXTBYPASS_H           (0x0010)       /* HFXT bypass mode : 0: internal 1:sourced from external pin */
+#define HFXTDRIVE0_H           (0x0040)       /* HFXT Drive Level mode Bit 0 */
+#define HFXTDRIVE1_H           (0x0080)       /* HFXT Drive Level mode Bit 1 */
+
+#define LFXTDRIVE_0            (0x0000)       /* LFXT Drive Level mode: 0 */
+#define LFXTDRIVE_1            (0x0040)       /* LFXT Drive Level mode: 1 */
+#define LFXTDRIVE_2            (0x0080)       /* LFXT Drive Level mode: 2 */
+#define LFXTDRIVE_3            (0x00C0)       /* LFXT Drive Level mode: 3 */
+
+#define HFFREQ_0               (0x0000)       /* HFXT frequency selection: 0 */
+#define HFFREQ_1               (0x0400)       /* HFXT frequency selection: 1 */
+#define HFFREQ_2               (0x0800)       /* HFXT frequency selection: 2 */
+#define HFFREQ_3               (0x0C00)       /* HFXT frequency selection: 3 */
+
+#define HFXTDRIVE_0            (0x0000)       /* HFXT Drive Level mode: 0 */
+#define HFXTDRIVE_1            (0x4000)       /* HFXT Drive Level mode: 1 */
+#define HFXTDRIVE_2            (0x8000)       /* HFXT Drive Level mode: 2 */
+#define HFXTDRIVE_3            (0xC000)       /* HFXT Drive Level mode: 3 */
+
+/* CSCTL5 Control Bits */
+#define LFXTOFFG               (0x0001)       /* LFXT Low Frequency Oscillator Fault Flag */
+#define HFXTOFFG               (0x0002)       /* HFXT High Frequency Oscillator Fault Flag */
+#define ENSTFCNT1              (0x0040)       /* Enable start counter for XT1 */
+#define ENSTFCNT2              (0x0080)       /* Enable start counter for XT2 */
+
+/* CSCTL5 Control Bits */
+#define LFXTOFFG_L             (0x0001)       /* LFXT Low Frequency Oscillator Fault Flag */
+#define HFXTOFFG_L             (0x0002)       /* HFXT High Frequency Oscillator Fault Flag */
+#define ENSTFCNT1_L            (0x0040)       /* Enable start counter for XT1 */
+#define ENSTFCNT2_L            (0x0080)       /* Enable start counter for XT2 */
+
+/* CSCTL6 Control Bits */
+#define ACLKREQEN              (0x0001)       /* ACLK Clock Request Enable */
+#define MCLKREQEN              (0x0002)       /* MCLK Clock Request Enable */
+#define SMCLKREQEN             (0x0004)       /* SMCLK Clock Request Enable */
+#define MODCLKREQEN            (0x0008)       /* MODOSC Clock Request Enable */
+
+/* CSCTL6 Control Bits */
+#define ACLKREQEN_L            (0x0001)       /* ACLK Clock Request Enable */
+#define MCLKREQEN_L            (0x0002)       /* MCLK Clock Request Enable */
+#define SMCLKREQEN_L           (0x0004)       /* SMCLK Clock Request Enable */
+#define MODCLKREQEN_L          (0x0008)       /* MODOSC Clock Request Enable */
+
+/************************************************************
+* DMA_X
+************************************************************/
+#define __MSP430_HAS_DMAX_3__                 /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_DMAX_3__ 0x0500
+#define DMA_BASE               __MSP430_BASEADDRESS_DMAX_3__
+
+sfr_w(DMACTL0);                               /* DMA Module Control 0 */
+sfr_b(DMACTL0_L);                             /* DMA Module Control 0 */
+sfr_b(DMACTL0_H);                             /* DMA Module Control 0 */
+sfr_w(DMACTL1);                               /* DMA Module Control 1 */
+sfr_b(DMACTL1_L);                             /* DMA Module Control 1 */
+sfr_b(DMACTL1_H);                             /* DMA Module Control 1 */
+sfr_w(DMACTL2);                               /* DMA Module Control 2 */
+sfr_b(DMACTL2_L);                             /* DMA Module Control 2 */
+sfr_b(DMACTL2_H);                             /* DMA Module Control 2 */
+sfr_w(DMACTL3);                               /* DMA Module Control 3 */
+sfr_b(DMACTL3_L);                             /* DMA Module Control 3 */
+sfr_b(DMACTL3_H);                             /* DMA Module Control 3 */
+sfr_w(DMACTL4);                               /* DMA Module Control 4 */
+sfr_b(DMACTL4_L);                             /* DMA Module Control 4 */
+sfr_b(DMACTL4_H);                             /* DMA Module Control 4 */
+sfr_w(DMAIV);                                 /* DMA Interrupt Vector Word */
+sfr_b(DMAIV_L);                               /* DMA Interrupt Vector Word */
+sfr_b(DMAIV_H);                               /* DMA Interrupt Vector Word */
+
+sfr_w(DMA0CTL);                               /* DMA Channel 0 Control */
+sfr_b(DMA0CTL_L);                             /* DMA Channel 0 Control */
+sfr_b(DMA0CTL_H);                             /* DMA Channel 0 Control */
+sfr_l(DMA0SA);                                /* DMA Channel 0 Source Address */
+sfr_w(DMA0SAL);                               /* DMA Channel 0 Source Address */
+sfr_w(DMA0SAH);                               /* DMA Channel 0 Source Address */
+sfr_l(DMA0DA);                                /* DMA Channel 0 Destination Address */
+sfr_w(DMA0DAL);                               /* DMA Channel 0 Destination Address */
+sfr_w(DMA0DAH);                               /* DMA Channel 0 Destination Address */
+sfr_w(DMA0SZ);                                /* DMA Channel 0 Transfer Size */
+
+sfr_w(DMA1CTL);                               /* DMA Channel 1 Control */
+sfr_b(DMA1CTL_L);                             /* DMA Channel 1 Control */
+sfr_b(DMA1CTL_H);                             /* DMA Channel 1 Control */
+sfr_l(DMA1SA);                                /* DMA Channel 1 Source Address */
+sfr_w(DMA1SAL);                               /* DMA Channel 1 Source Address */
+sfr_w(DMA1SAH);                               /* DMA Channel 1 Source Address */
+sfr_l(DMA1DA);                                /* DMA Channel 1 Destination Address */
+sfr_w(DMA1DAL);                               /* DMA Channel 1 Destination Address */
+sfr_w(DMA1DAH);                               /* DMA Channel 1 Destination Address */
+sfr_w(DMA1SZ);                                /* DMA Channel 1 Transfer Size */
+
+sfr_w(DMA2CTL);                               /* DMA Channel 2 Control */
+sfr_b(DMA2CTL_L);                             /* DMA Channel 2 Control */
+sfr_b(DMA2CTL_H);                             /* DMA Channel 2 Control */
+sfr_l(DMA2SA);                                /* DMA Channel 2 Source Address */
+sfr_w(DMA2SAL);                               /* DMA Channel 2 Source Address */
+sfr_w(DMA2SAH);                               /* DMA Channel 2 Source Address */
+sfr_l(DMA2DA);                                /* DMA Channel 2 Destination Address */
+sfr_w(DMA2DAL);                               /* DMA Channel 2 Destination Address */
+sfr_w(DMA2DAH);                               /* DMA Channel 2 Destination Address */
+sfr_w(DMA2SZ);                                /* DMA Channel 2 Transfer Size */
+
+/* DMACTL0 Control Bits */
+#define DMA0TSEL0              (0x0001)       /* DMA channel 0 transfer select bit 0 */
+#define DMA0TSEL1              (0x0002)       /* DMA channel 0 transfer select bit 1 */
+#define DMA0TSEL2              (0x0004)       /* DMA channel 0 transfer select bit 2 */
+#define DMA0TSEL3              (0x0008)       /* DMA channel 0 transfer select bit 3 */
+#define DMA0TSEL4              (0x0010)       /* DMA channel 0 transfer select bit 4 */
+#define DMA1TSEL0              (0x0100)       /* DMA channel 1 transfer select bit 0 */
+#define DMA1TSEL1              (0x0200)       /* DMA channel 1 transfer select bit 1 */
+#define DMA1TSEL2              (0x0400)       /* DMA channel 1 transfer select bit 2 */
+#define DMA1TSEL3              (0x0800)       /* DMA channel 1 transfer select bit 3 */
+#define DMA1TSEL4              (0x1000)       /* DMA channel 1 transfer select bit 4 */
+
+/* DMACTL0 Control Bits */
+#define DMA0TSEL0_L            (0x0001)       /* DMA channel 0 transfer select bit 0 */
+#define DMA0TSEL1_L            (0x0002)       /* DMA channel 0 transfer select bit 1 */
+#define DMA0TSEL2_L            (0x0004)       /* DMA channel 0 transfer select bit 2 */
+#define DMA0TSEL3_L            (0x0008)       /* DMA channel 0 transfer select bit 3 */
+#define DMA0TSEL4_L            (0x0010)       /* DMA channel 0 transfer select bit 4 */
+
+/* DMACTL0 Control Bits */
+#define DMA1TSEL0_H            (0x0001)       /* DMA channel 1 transfer select bit 0 */
+#define DMA1TSEL1_H            (0x0002)       /* DMA channel 1 transfer select bit 1 */
+#define DMA1TSEL2_H            (0x0004)       /* DMA channel 1 transfer select bit 2 */
+#define DMA1TSEL3_H            (0x0008)       /* DMA channel 1 transfer select bit 3 */
+#define DMA1TSEL4_H            (0x0010)       /* DMA channel 1 transfer select bit 4 */
+
+/* DMACTL01 Control Bits */
+#define DMA2TSEL0              (0x0001)       /* DMA channel 2 transfer select bit 0 */
+#define DMA2TSEL1              (0x0002)       /* DMA channel 2 transfer select bit 1 */
+#define DMA2TSEL2              (0x0004)       /* DMA channel 2 transfer select bit 2 */
+#define DMA2TSEL3              (0x0008)       /* DMA channel 2 transfer select bit 3 */
+#define DMA2TSEL4              (0x0010)       /* DMA channel 2 transfer select bit 4 */
+
+/* DMACTL01 Control Bits */
+#define DMA2TSEL0_L            (0x0001)       /* DMA channel 2 transfer select bit 0 */
+#define DMA2TSEL1_L            (0x0002)       /* DMA channel 2 transfer select bit 1 */
+#define DMA2TSEL2_L            (0x0004)       /* DMA channel 2 transfer select bit 2 */
+#define DMA2TSEL3_L            (0x0008)       /* DMA channel 2 transfer select bit 3 */
+#define DMA2TSEL4_L            (0x0010)       /* DMA channel 2 transfer select bit 4 */
+
+/* DMACTL4 Control Bits */
+#define ENNMI                  (0x0001)       /* Enable NMI interruption of DMA */
+#define ROUNDROBIN             (0x0002)       /* Round-Robin DMA channel priorities */
+#define DMARMWDIS              (0x0004)       /* Inhibited DMA transfers during read-modify-write CPU operations */
+
+/* DMACTL4 Control Bits */
+#define ENNMI_L                (0x0001)       /* Enable NMI interruption of DMA */
+#define ROUNDROBIN_L           (0x0002)       /* Round-Robin DMA channel priorities */
+#define DMARMWDIS_L            (0x0004)       /* Inhibited DMA transfers during read-modify-write CPU operations */
+
+/* DMAxCTL Control Bits */
+#define DMAREQ                 (0x0001)       /* Initiate DMA transfer with DMATSEL */
+#define DMAABORT               (0x0002)       /* DMA transfer aborted by NMI */
+#define DMAIE                  (0x0004)       /* DMA interrupt enable */
+#define DMAIFG                 (0x0008)       /* DMA interrupt flag */
+#define DMAEN                  (0x0010)       /* DMA enable */
+#define DMALEVEL               (0x0020)       /* DMA level sensitive trigger select */
+#define DMASRCBYTE             (0x0040)       /* DMA source byte */
+#define DMADSTBYTE             (0x0080)       /* DMA destination byte */
+#define DMASRCINCR0            (0x0100)       /* DMA source increment bit 0 */
+#define DMASRCINCR1            (0x0200)       /* DMA source increment bit 1 */
+#define DMADSTINCR0            (0x0400)       /* DMA destination increment bit 0 */
+#define DMADSTINCR1            (0x0800)       /* DMA destination increment bit 1 */
+#define DMADT0                 (0x1000)       /* DMA transfer mode bit 0 */
+#define DMADT1                 (0x2000)       /* DMA transfer mode bit 1 */
+#define DMADT2                 (0x4000)       /* DMA transfer mode bit 2 */
+
+/* DMAxCTL Control Bits */
+#define DMAREQ_L               (0x0001)       /* Initiate DMA transfer with DMATSEL */
+#define DMAABORT_L             (0x0002)       /* DMA transfer aborted by NMI */
+#define DMAIE_L                (0x0004)       /* DMA interrupt enable */
+#define DMAIFG_L               (0x0008)       /* DMA interrupt flag */
+#define DMAEN_L                (0x0010)       /* DMA enable */
+#define DMALEVEL_L             (0x0020)       /* DMA level sensitive trigger select */
+#define DMASRCBYTE_L           (0x0040)       /* DMA source byte */
+#define DMADSTBYTE_L           (0x0080)       /* DMA destination byte */
+
+/* DMAxCTL Control Bits */
+#define DMASRCINCR0_H          (0x0001)       /* DMA source increment bit 0 */
+#define DMASRCINCR1_H          (0x0002)       /* DMA source increment bit 1 */
+#define DMADSTINCR0_H          (0x0004)       /* DMA destination increment bit 0 */
+#define DMADSTINCR1_H          (0x0008)       /* DMA destination increment bit 1 */
+#define DMADT0_H               (0x0010)       /* DMA transfer mode bit 0 */
+#define DMADT1_H               (0x0020)       /* DMA transfer mode bit 1 */
+#define DMADT2_H               (0x0040)       /* DMA transfer mode bit 2 */
+
+#define DMASWDW                (0x0000)       /* DMA transfer: source word to destination word */
+#define DMASBDW                (0x0040)       /* DMA transfer: source byte to destination word */
+#define DMASWDB                (0x0080)       /* DMA transfer: source word to destination byte */
+#define DMASBDB                (0x00C0)       /* DMA transfer: source byte to destination byte */
+
+#define DMASRCINCR_0           (0x0000)       /* DMA source increment 0: source address unchanged */
+#define DMASRCINCR_1           (0x0100)       /* DMA source increment 1: source address unchanged */
+#define DMASRCINCR_2           (0x0200)       /* DMA source increment 2: source address decremented */
+#define DMASRCINCR_3           (0x0300)       /* DMA source increment 3: source address incremented */
+
+#define DMADSTINCR_0           (0x0000)       /* DMA destination increment 0: destination address unchanged */
+#define DMADSTINCR_1           (0x0400)       /* DMA destination increment 1: destination address unchanged */
+#define DMADSTINCR_2           (0x0800)       /* DMA destination increment 2: destination address decremented */
+#define DMADSTINCR_3           (0x0C00)       /* DMA destination increment 3: destination address incremented */
+
+#define DMADT_0                (0x0000)       /* DMA transfer mode 0: Single transfer */
+#define DMADT_1                (0x1000)       /* DMA transfer mode 1: Block transfer */
+#define DMADT_2                (0x2000)       /* DMA transfer mode 2: Burst-Block transfer */
+#define DMADT_3                (0x3000)       /* DMA transfer mode 3: Burst-Block transfer */
+#define DMADT_4                (0x4000)       /* DMA transfer mode 4: Repeated Single transfer */
+#define DMADT_5                (0x5000)       /* DMA transfer mode 5: Repeated Block transfer */
+#define DMADT_6                (0x6000)       /* DMA transfer mode 6: Repeated Burst-Block transfer */
+#define DMADT_7                (0x7000)       /* DMA transfer mode 7: Repeated Burst-Block transfer */
+
+/* DMAIV Definitions */
+#define DMAIV_NONE             (0x0000)       /* No Interrupt pending */
+#define DMAIV_DMA0IFG          (0x0002)       /* DMA0IFG*/
+#define DMAIV_DMA1IFG          (0x0004)       /* DMA1IFG*/
+#define DMAIV_DMA2IFG          (0x0006)       /* DMA2IFG*/
+
+#define DMA0TSEL_0             (0x0000)       /* DMA channel 0 transfer select 0:  DMA_REQ (sw) */
+#define DMA0TSEL_1             (0x0001)       /* DMA channel 0 transfer select 1:  */
+#define DMA0TSEL_2             (0x0002)       /* DMA channel 0 transfer select 2:  */
+#define DMA0TSEL_3             (0x0003)       /* DMA channel 0 transfer select 3:  */
+#define DMA0TSEL_4             (0x0004)       /* DMA channel 0 transfer select 4:  */
+#define DMA0TSEL_5             (0x0005)       /* DMA channel 0 transfer select 5:  */
+#define DMA0TSEL_6             (0x0006)       /* DMA channel 0 transfer select 6:  */
+#define DMA0TSEL_7             (0x0007)       /* DMA channel 0 transfer select 7:  */
+#define DMA0TSEL_8             (0x0008)       /* DMA channel 0 transfer select 8:  */
+#define DMA0TSEL_9             (0x0009)       /* DMA channel 0 transfer select 9:  */
+#define DMA0TSEL_10            (0x000A)       /* DMA channel 0 transfer select 10: */
+#define DMA0TSEL_11            (0x000B)       /* DMA channel 0 transfer select 11: */
+#define DMA0TSEL_12            (0x000C)       /* DMA channel 0 transfer select 12: */
+#define DMA0TSEL_13            (0x000D)       /* DMA channel 0 transfer select 13: */
+#define DMA0TSEL_14            (0x000E)       /* DMA channel 0 transfer select 14: */
+#define DMA0TSEL_15            (0x000F)       /* DMA channel 0 transfer select 15: */
+#define DMA0TSEL_16            (0x0010)       /* DMA channel 0 transfer select 16: */
+#define DMA0TSEL_17            (0x0011)       /* DMA channel 0 transfer select 17: */
+#define DMA0TSEL_18            (0x0012)       /* DMA channel 0 transfer select 18: */
+#define DMA0TSEL_19            (0x0013)       /* DMA channel 0 transfer select 19: */
+#define DMA0TSEL_20            (0x0014)       /* DMA channel 0 transfer select 20: */
+#define DMA0TSEL_21            (0x0015)       /* DMA channel 0 transfer select 21: */
+#define DMA0TSEL_22            (0x0016)       /* DMA channel 0 transfer select 22: */
+#define DMA0TSEL_23            (0x0017)       /* DMA channel 0 transfer select 23: */
+#define DMA0TSEL_24            (0x0018)       /* DMA channel 0 transfer select 24: */
+#define DMA0TSEL_25            (0x0019)       /* DMA channel 0 transfer select 25: */
+#define DMA0TSEL_26            (0x001A)       /* DMA channel 0 transfer select 26: */
+#define DMA0TSEL_27            (0x001B)       /* DMA channel 0 transfer select 27: */
+#define DMA0TSEL_28            (0x001C)       /* DMA channel 0 transfer select 28: */
+#define DMA0TSEL_29            (0x001D)       /* DMA channel 0 transfer select 29: */
+#define DMA0TSEL_30            (0x001E)       /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */
+#define DMA0TSEL_31            (0x001F)       /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */
+
+#define DMA1TSEL_0             (0x0000)       /* DMA channel 1 transfer select 0:  DMA_REQ (sw) */
+#define DMA1TSEL_1             (0x0100)       /* DMA channel 1 transfer select 1:  */
+#define DMA1TSEL_2             (0x0200)       /* DMA channel 1 transfer select 2:  */
+#define DMA1TSEL_3             (0x0300)       /* DMA channel 1 transfer select 3:  */
+#define DMA1TSEL_4             (0x0400)       /* DMA channel 1 transfer select 4:  */
+#define DMA1TSEL_5             (0x0500)       /* DMA channel 1 transfer select 5:  */
+#define DMA1TSEL_6             (0x0600)       /* DMA channel 1 transfer select 6:  */
+#define DMA1TSEL_7             (0x0700)       /* DMA channel 1 transfer select 7:  */
+#define DMA1TSEL_8             (0x0800)       /* DMA channel 1 transfer select 8:  */
+#define DMA1TSEL_9             (0x0900)       /* DMA channel 1 transfer select 9:  */
+#define DMA1TSEL_10            (0x0A00)       /* DMA channel 1 transfer select 10: */
+#define DMA1TSEL_11            (0x0B00)       /* DMA channel 1 transfer select 11: */
+#define DMA1TSEL_12            (0x0C00)       /* DMA channel 1 transfer select 12: */
+#define DMA1TSEL_13            (0x0D00)       /* DMA channel 1 transfer select 13: */
+#define DMA1TSEL_14            (0x0E00)       /* DMA channel 1 transfer select 14: */
+#define DMA1TSEL_15            (0x0F00)       /* DMA channel 1 transfer select 15: */
+#define DMA1TSEL_16            (0x1000)       /* DMA channel 1 transfer select 16: */
+#define DMA1TSEL_17            (0x1100)       /* DMA channel 1 transfer select 17: */
+#define DMA1TSEL_18            (0x1200)       /* DMA channel 1 transfer select 18: */
+#define DMA1TSEL_19            (0x1300)       /* DMA channel 1 transfer select 19: */
+#define DMA1TSEL_20            (0x1400)       /* DMA channel 1 transfer select 20: */
+#define DMA1TSEL_21            (0x1500)       /* DMA channel 1 transfer select 21: */
+#define DMA1TSEL_22            (0x1600)       /* DMA channel 1 transfer select 22: */
+#define DMA1TSEL_23            (0x1700)       /* DMA channel 1 transfer select 23: */
+#define DMA1TSEL_24            (0x1800)       /* DMA channel 1 transfer select 24: */
+#define DMA1TSEL_25            (0x1900)       /* DMA channel 1 transfer select 25: */
+#define DMA1TSEL_26            (0x1A00)       /* DMA channel 1 transfer select 26: */
+#define DMA1TSEL_27            (0x1B00)       /* DMA channel 1 transfer select 27: */
+#define DMA1TSEL_28            (0x1C00)       /* DMA channel 1 transfer select 28: */
+#define DMA1TSEL_29            (0x1D00)       /* DMA channel 1 transfer select 29: */
+#define DMA1TSEL_30            (0x1E00)       /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */
+#define DMA1TSEL_31            (0x1F00)       /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */
+
+#define DMA2TSEL_0             (0x0000)       /* DMA channel 2 transfer select 0:  DMA_REQ (sw) */
+#define DMA2TSEL_1             (0x0001)       /* DMA channel 2 transfer select 1:  */
+#define DMA2TSEL_2             (0x0002)       /* DMA channel 2 transfer select 2:  */
+#define DMA2TSEL_3             (0x0003)       /* DMA channel 2 transfer select 3:  */
+#define DMA2TSEL_4             (0x0004)       /* DMA channel 2 transfer select 4:  */
+#define DMA2TSEL_5             (0x0005)       /* DMA channel 2 transfer select 5:  */
+#define DMA2TSEL_6             (0x0006)       /* DMA channel 2 transfer select 6:  */
+#define DMA2TSEL_7             (0x0007)       /* DMA channel 2 transfer select 7:  */
+#define DMA2TSEL_8             (0x0008)       /* DMA channel 2 transfer select 8:  */
+#define DMA2TSEL_9             (0x0009)       /* DMA channel 2 transfer select 9:  */
+#define DMA2TSEL_10            (0x000A)       /* DMA channel 2 transfer select 10: */
+#define DMA2TSEL_11            (0x000B)       /* DMA channel 2 transfer select 11: */
+#define DMA2TSEL_12            (0x000C)       /* DMA channel 2 transfer select 12: */
+#define DMA2TSEL_13            (0x000D)       /* DMA channel 2 transfer select 13: */
+#define DMA2TSEL_14            (0x000E)       /* DMA channel 2 transfer select 14: */
+#define DMA2TSEL_15            (0x000F)       /* DMA channel 2 transfer select 15: */
+#define DMA2TSEL_16            (0x0010)       /* DMA channel 2 transfer select 16: */
+#define DMA2TSEL_17            (0x0011)       /* DMA channel 2 transfer select 17: */
+#define DMA2TSEL_18            (0x0012)       /* DMA channel 2 transfer select 18: */
+#define DMA2TSEL_19            (0x0013)       /* DMA channel 2 transfer select 19: */
+#define DMA2TSEL_20            (0x0014)       /* DMA channel 2 transfer select 20: */
+#define DMA2TSEL_21            (0x0015)       /* DMA channel 2 transfer select 21: */
+#define DMA2TSEL_22            (0x0016)       /* DMA channel 2 transfer select 22: */
+#define DMA2TSEL_23            (0x0017)       /* DMA channel 2 transfer select 23: */
+#define DMA2TSEL_24            (0x0018)       /* DMA channel 2 transfer select 24: */
+#define DMA2TSEL_25            (0x0019)       /* DMA channel 2 transfer select 25: */
+#define DMA2TSEL_26            (0x001A)       /* DMA channel 2 transfer select 26: */
+#define DMA2TSEL_27            (0x001B)       /* DMA channel 2 transfer select 27: */
+#define DMA2TSEL_28            (0x001C)       /* DMA channel 2 transfer select 28: */
+#define DMA2TSEL_29            (0x001D)       /* DMA channel 2 transfer select 29: */
+#define DMA2TSEL_30            (0x001E)       /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */
+#define DMA2TSEL_31            (0x001F)       /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */
+
+#define DMA0TSEL__DMAREQ       (0x0000)       /* DMA channel 0 transfer select 0:  DMA_REQ (sw) */
+#define DMA0TSEL__TA0CCR0      (0x0001)       /* DMA channel 0 transfer select 1:  TA0CCR0 */
+#define DMA0TSEL__TA0CCR2      (0x0002)       /* DMA channel 0 transfer select 2:  TA0CCR2 */
+#define DMA0TSEL__TA1CCR0      (0x0003)       /* DMA channel 0 transfer select 3:  TA1CCR0 */
+#define DMA0TSEL__TA1CCR2      (0x0004)       /* DMA channel 0 transfer select 4:  TA1CCR2 */
+#define DMA0TSEL__TA2CCR0      (0x0005)       /* DMA channel 0 transfer select 3:  TA2CCR0 */
+#define DMA0TSEL__TA3CCR0      (0x0006)       /* DMA channel 0 transfer select 4:  TA3CCR0 */
+#define DMA0TSEL__TB0CCR0      (0x0007)       /* DMA channel 0 transfer select 7:  TB0CCR0 */
+#define DMA0TSEL__TB0CCR2      (0x0008)       /* DMA channel 0 transfer select 8:  TB0CCR2 */
+#define DMA0TSEL__RES9         (0x0009)       /* DMA channel 0 transfer select 9:  RES9 */
+#define DMA0TSEL__RES10        (0x000A)       /* DMA channel 0 transfer select 10: RES10 */
+#define DMA0TSEL__AES_Trigger_0 (0x000B)       /* DMA channel 0 transfer select 11: AES Trigger 0 */
+#define DMA0TSEL__AES_Trigger_1 (0x000C)       /* DMA channel 0 transfer select 12: AES Trigger 1 */
+#define DMA0TSEL__AES_Trigger_2 (0x000D)       /* DMA channel 0 transfer select 13: AES Trigger 2 */
+#define DMA0TSEL__UCA0RXIFG    (0x000E)       /* DMA channel 0 transfer select 14: UCA0RXIFG */
+#define DMA0TSEL__UCA0TXIFG    (0x000F)       /* DMA channel 0 transfer select 15: UCA0TXIFG */
+#define DMA0TSEL__UCA1RXIFG    (0x0010)       /* DMA channel 0 transfer select 16: UCA1RXIFG */
+#define DMA0TSEL__UCA1TXIFG    (0x0011)       /* DMA channel 0 transfer select 17: UCA1TXIFG */
+#define DMA0TSEL__UCB0RXIFG0   (0x0012)       /* DMA channel 0 transfer select 18: UCB0RXIFG0 */
+#define DMA0TSEL__UCB0TXIFG0   (0x0013)       /* DMA channel 0 transfer select 19: UCB0TXIFG0 */
+#define DMA0TSEL__UCB0RXIFG1   (0x0014)       /* DMA channel 0 transfer select 20: UCB0RXIFG1 */
+#define DMA0TSEL__UCB0TXIFG1   (0x0015)       /* DMA channel 0 transfer select 21: UCB0TXIFG1 */
+#define DMA0TSEL__UCB0RXIFG2   (0x0016)       /* DMA channel 0 transfer select 22: UCB0RXIFG2 */
+#define DMA0TSEL__UCB0TXIFG2   (0x0017)       /* DMA channel 0 transfer select 23: UCB0TXIFG2 */
+#define DMA0TSEL__UCB1RXIFG0   (0x0018)       /* DMA channel 0 transfer select 24: UCB1RXIFG0 */
+#define DMA0TSEL__UCB1TXIFG0   (0x0019)       /* DMA channel 0 transfer select 25: UCB1TXIFG0 */
+#define DMA0TSEL__ADC12IFG     (0x001A)       /* DMA channel 0 transfer select 26: ADC12IFG */
+#define DMA0TSEL__RES27        (0x001B)       /* DMA channel 0 transfer select 27: RES27 */
+//#define DMA0TSEL__RES28      (0x001C) /* DMA channel 0 transfer select 28: RES28 */
+#define DMA0TSEL__ESI          (0x001C)       /* DMA channel 0 transfer select 28: ESI */
+#define DMA0TSEL__MPY          (0x001D)       /* DMA channel 0 transfer select 29: MPY */
+#define DMA0TSEL__DMA2IFG      (0x001E)       /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */
+#define DMA0TSEL__DMAE0        (0x001F)       /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */
+
+#define DMA1TSEL__DMAREQ       (0x0000)       /* DMA channel 1 transfer select 0:  DMA_REQ (sw) */
+#define DMA1TSEL__TA0CCR0      (0x0100)       /* DMA channel 1 transfer select 1:  TA0CCR0 */
+#define DMA1TSEL__TA0CCR2      (0x0200)       /* DMA channel 1 transfer select 2:  TA0CCR2 */
+#define DMA1TSEL__TA1CCR0      (0x0300)       /* DMA channel 1 transfer select 3:  TA1CCR0 */
+#define DMA1TSEL__TA1CCR2      (0x0400)       /* DMA channel 1 transfer select 4:  TA1CCR2 */
+#define DMA1TSEL__TA2CCR0      (0x0500)       /* DMA channel 1 transfer select 5:  TA2CCR0 */
+#define DMA1TSEL__TA3CCR0      (0x0600)       /* DMA channel 1 transfer select 6:  TA3CCR0 */
+#define DMA1TSEL__TB0CCR0      (0x0700)       /* DMA channel 1 transfer select 7:  TB0CCR0 */
+#define DMA1TSEL__TB0CCR2      (0x0800)       /* DMA channel 1 transfer select 8:  TB0CCR2 */
+#define DMA1TSEL__RES9         (0x0900)       /* DMA channel 1 transfer select 9:  RES9 */
+#define DMA1TSEL__RES10        (0x0A00)       /* DMA channel 1 transfer select 10: RES10 */
+#define DMA1TSEL__AES_Trigger_0 (0x0B00)       /* DMA channel 1 transfer select 11: AES Trigger 0 */
+#define DMA1TSEL__AES_Trigger_1 (0x0C00)       /* DMA channel 1 transfer select 12: AES Trigger 1 */
+#define DMA1TSEL__AES_Trigger_2 (0x0D00)       /* DMA channel 1 transfer select 13: AES Trigger 2 */
+#define DMA1TSEL__UCA0RXIFG    (0x0E00)       /* DMA channel 1 transfer select 14: UCA0RXIFG */
+#define DMA1TSEL__UCA0TXIFG    (0x0F00)       /* DMA channel 1 transfer select 15: UCA0TXIFG */
+#define DMA1TSEL__UCA1RXIFG    (0x1000)       /* DMA channel 1 transfer select 16: UCA1RXIFG */
+#define DMA1TSEL__UCA1TXIFG    (0x1100)       /* DMA channel 1 transfer select 17: UCA1TXIFG */
+#define DMA1TSEL__UCB0RXIFG0   (0x1200)       /* DMA channel 1 transfer select 18: UCB0RXIFG0 */
+#define DMA1TSEL__UCB0TXIFG0   (0x1300)       /* DMA channel 1 transfer select 19: UCB0TXIFG0 */
+#define DMA1TSEL__UCB0RXIFG1   (0x1400)       /* DMA channel 1 transfer select 20: UCB0RXIFG1 */
+#define DMA1TSEL__UCB0TXIFG1   (0x1500)       /* DMA channel 1 transfer select 21: UCB0TXIFG1 */
+#define DMA1TSEL__UCB0RXIFG2   (0x1600)       /* DMA channel 1 transfer select 22: UCB0RXIFG2 */
+#define DMA1TSEL__UCB0TXIFG2   (0x1700)       /* DMA channel 1 transfer select 23: UCB0TXIFG2 */
+#define DMA1TSEL__UCB1RXIFG0   (0x1800)       /* DMA channel 1 transfer select 24: UCB1RXIFG0 */
+#define DMA1TSEL__UCB1TXIFG0   (0x1900)       /* DMA channel 1 transfer select 25: UCB1TXIFG0 */
+#define DMA1TSEL__ADC12IFG     (0x1A00)       /* DMA channel 1 transfer select 26: ADC12IFG */
+#define DMA1TSEL__RES27        (0x1B00)       /* DMA channel 1 transfer select 27: RES27 */
+#define DMA1TSEL__ESI          (0x1C00)       /* DMA channel 1 transfer select 28: ESI */
+#define DMA1TSEL__MPY          (0x1D00)       /* DMA channel 1 transfer select 29: MPY */
+#define DMA1TSEL__DMA0IFG      (0x1E00)       /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */
+#define DMA1TSEL__DMAE0        (0x1F00)       /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */
+
+#define DMA2TSEL__DMAREQ       (0x0000)       /* DMA channel 2 transfer select 0:  DMA_REQ (sw) */
+#define DMA2TSEL__TA0CCR0      (0x0001)       /* DMA channel 2 transfer select 1:  TA0CCR0 */
+#define DMA2TSEL__TA0CCR2      (0x0002)       /* DMA channel 2 transfer select 2:  TA0CCR2 */
+#define DMA2TSEL__TA1CCR0      (0x0003)       /* DMA channel 2 transfer select 3:  TA1CCR0 */
+#define DMA2TSEL__TA1CCR2      (0x0004)       /* DMA channel 2 transfer select 4:  TA1CCR2 */
+#define DMA2TSEL__TA2CCR0      (0x0005)       /* DMA channel 2 transfer select 5:  TA2CCR0 */
+#define DMA2TSEL__TA3CCR0      (0x0006)       /* DMA channel 2 transfer select 6:  TA3CCR0 */
+#define DMA2TSEL__TB0CCR0      (0x0007)       /* DMA channel 2 transfer select 7:  TB0CCR0 */
+#define DMA2TSEL__TB0CCR2      (0x0008)       /* DMA channel 2 transfer select 8:  TB0CCR2 */
+#define DMA2TSEL__RES9         (0x0009)       /* DMA channel 2 transfer select 9:  RES9 */
+#define DMA2TSEL__RES10        (0x000A)       /* DMA channel 2 transfer select 10: RES10 */
+#define DMA2TSEL__AES_Trigger_0 (0x000B)       /* DMA channel 2 transfer select 11: AES Trigger 0 */
+#define DMA2TSEL__AES_Trigger_1 (0x000C)       /* DMA channel 2 transfer select 12: AES Trigger 1 */
+#define DMA2TSEL__AES_Trigger_2 (0x000D)       /* DMA channel 2 transfer select 13: AES Trigger 2 */
+#define DMA2TSEL__UCA0RXIFG    (0x000E)       /* DMA channel 2 transfer select 14: UCA0RXIFG */
+#define DMA2TSEL__UCA0TXIFG    (0x000F)       /* DMA channel 2 transfer select 15: UCA0TXIFG */
+#define DMA2TSEL__UCA1RXIFG    (0x0010)       /* DMA channel 2 transfer select 16: UCA1RXIFG */
+#define DMA2TSEL__UCA1TXIFG    (0x0011)       /* DMA channel 2 transfer select 17: UCA1TXIFG */
+#define DMA2TSEL__UCB0RXIFG0   (0x0012)       /* DMA channel 2 transfer select 18: UCB0RXIFG0 */
+#define DMA2TSEL__UCB0TXIFG0   (0x0013)       /* DMA channel 2 transfer select 19: UCB0TXIFG0 */
+#define DMA2TSEL__UCB0RXIFG1   (0x0014)       /* DMA channel 2 transfer select 20: UCB0RXIFG1 */
+#define DMA2TSEL__UCB0TXIFG1   (0x0015)       /* DMA channel 2 transfer select 21: UCB0TXIFG1 */
+#define DMA2TSEL__UCB0RXIFG2   (0x0016)       /* DMA channel 2 transfer select 22: UCB0RXIFG2 */
+#define DMA2TSEL__UCB0TXIFG2   (0x0017)       /* DMA channel 2 transfer select 23: UCB0TXIFG2 */
+#define DMA2TSEL__UCB1RXIFG0   (0x0018)       /* DMA channel 2 transfer select 24: UCB1RXIFG0 */
+#define DMA2TSEL__UCB1TXIFG0   (0x0019)       /* DMA channel 2 transfer select 25: UCB1TXIFG0 */
+#define DMA2TSEL__ADC12IFG     (0x001A)       /* DMA channel 2 transfer select 26: ADC12IFG */
+#define DMA2TSEL__RES27        (0x001B)       /* DMA channel 2 transfer select 27: RES27 */
+#define DMA2TSEL__ESI          (0x001C)       /* DMA channel 2 transfer select 28: ESI */
+#define DMA2TSEL__MPY          (0x001D)       /* DMA channel 2 transfer select 29: MPY */
+#define DMA2TSEL__DMA1IFG      (0x001E)       /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */
+#define DMA2TSEL__DMAE0        (0x001F)       /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */
+
+/************************************************************
+* EXTENDED SCAN INTERFACE
+************************************************************/
+#define __MSP430_HAS_ESI__                    /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_ESI__ 0x0D00
+#define ESI_BASE               __MSP430_BASEADDRESS_ESI__
+
+sfr_w(ESIDEBUG1);                             /* ESI debug register 1 */
+sfr_b(ESIDEBUG1_L);                           /* ESI debug register 1 */
+sfr_b(ESIDEBUG1_H);                           /* ESI debug register 1 */
+sfr_w(ESIDEBUG2);                             /* ESI debug register 2 */
+sfr_b(ESIDEBUG2_L);                           /* ESI debug register 2 */
+sfr_b(ESIDEBUG2_H);                           /* ESI debug register 2 */
+sfr_w(ESIDEBUG3);                             /* ESI debug register 3 */
+sfr_b(ESIDEBUG3_L);                           /* ESI debug register 3 */
+sfr_b(ESIDEBUG3_H);                           /* ESI debug register 3 */
+sfr_w(ESIDEBUG4);                             /* ESI debug register 4 */
+sfr_b(ESIDEBUG4_L);                           /* ESI debug register 4 */
+sfr_b(ESIDEBUG4_H);                           /* ESI debug register 4 */
+sfr_w(ESIDEBUG5);                             /* ESI debug register 5 */
+sfr_b(ESIDEBUG5_L);                           /* ESI debug register 5 */
+sfr_b(ESIDEBUG5_H);                           /* ESI debug register 5 */
+sfr_w(ESICNT0);                               /* ESI PSM counter 0 */
+sfr_b(ESICNT0_L);                             /* ESI PSM counter 0 */
+sfr_b(ESICNT0_H);                             /* ESI PSM counter 0 */
+sfr_w(ESICNT1);                               /* ESI PSM counter 1 */
+sfr_b(ESICNT1_L);                             /* ESI PSM counter 1 */
+sfr_b(ESICNT1_H);                             /* ESI PSM counter 1 */
+sfr_w(ESICNT2);                               /* ESI PSM counter 2 */
+sfr_b(ESICNT2_L);                             /* ESI PSM counter 2 */
+sfr_b(ESICNT2_H);                             /* ESI PSM counter 2 */
+sfr_w(ESICNT3);                               /* ESI oscillator counter register */
+sfr_b(ESICNT3_L);                             /* ESI oscillator counter register */
+sfr_b(ESICNT3_H);                             /* ESI oscillator counter register */
+sfr_w(ESIIV);                                 /* ESI interrupt vector */
+sfr_b(ESIIV_L);                               /* ESI interrupt vector */
+sfr_b(ESIIV_H);                               /* ESI interrupt vector */
+sfr_w(ESIINT1);                               /* ESI interrupt register 1 */
+sfr_b(ESIINT1_L);                             /* ESI interrupt register 1 */
+sfr_b(ESIINT1_H);                             /* ESI interrupt register 1 */
+sfr_w(ESIINT2);                               /* ESI interrupt register 2 */
+sfr_b(ESIINT2_L);                             /* ESI interrupt register 2 */
+sfr_b(ESIINT2_H);                             /* ESI interrupt register 2 */
+sfr_w(ESIAFE);                                /* ESI AFE control register */
+sfr_b(ESIAFE_L);                              /* ESI AFE control register */
+sfr_b(ESIAFE_H);                              /* ESI AFE control register */
+sfr_w(ESIPPU);                                /* ESI PPU control register */
+sfr_b(ESIPPU_L);                              /* ESI PPU control register */
+sfr_b(ESIPPU_H);                              /* ESI PPU control register */
+sfr_w(ESITSM);                                /* ESI TSM control register */
+sfr_b(ESITSM_L);                              /* ESI TSM control register */
+sfr_b(ESITSM_H);                              /* ESI TSM control register */
+sfr_w(ESIPSM);                                /* ESI PSM control register */
+sfr_b(ESIPSM_L);                              /* ESI PSM control register */
+sfr_b(ESIPSM_H);                              /* ESI PSM control register */
+sfr_w(ESIOSC);                                /* ESI oscillator control register*/
+sfr_b(ESIOSC_L);                              /* ESI oscillator control register*/
+sfr_b(ESIOSC_H);                              /* ESI oscillator control register*/
+sfr_w(ESICTL);                                /* ESI control register */
+sfr_b(ESICTL_L);                              /* ESI control register */
+sfr_b(ESICTL_H);                              /* ESI control register */
+sfr_w(ESITHR1);                               /* ESI PSM Counter Threshold 1 register */
+sfr_b(ESITHR1_L);                             /* ESI PSM Counter Threshold 1 register */
+sfr_b(ESITHR1_H);                             /* ESI PSM Counter Threshold 1 register */
+sfr_w(ESITHR2);                               /* ESI PSM Counter Threshold 2 register */
+sfr_b(ESITHR2_L);                             /* ESI PSM Counter Threshold 2 register */
+sfr_b(ESITHR2_H);                             /* ESI PSM Counter Threshold 2 register */
+sfr_w(ESIDAC1R0);                             /* ESI DAC1 register 0 */
+sfr_b(ESIDAC1R0_L);                           /* ESI DAC1 register 0 */
+sfr_b(ESIDAC1R0_H);                           /* ESI DAC1 register 0 */
+sfr_w(ESIDAC1R1);                             /* ESI DAC1 register 1 */
+sfr_b(ESIDAC1R1_L);                           /* ESI DAC1 register 1 */
+sfr_b(ESIDAC1R1_H);                           /* ESI DAC1 register 1 */
+sfr_w(ESIDAC1R2);                             /* ESI DAC1 register 2 */
+sfr_b(ESIDAC1R2_L);                           /* ESI DAC1 register 2 */
+sfr_b(ESIDAC1R2_H);                           /* ESI DAC1 register 2 */
+sfr_w(ESIDAC1R3);                             /* ESI DAC1 register 3 */
+sfr_b(ESIDAC1R3_L);                           /* ESI DAC1 register 3 */
+sfr_b(ESIDAC1R3_H);                           /* ESI DAC1 register 3 */
+sfr_w(ESIDAC1R4);                             /* ESI DAC1 register 4 */
+sfr_b(ESIDAC1R4_L);                           /* ESI DAC1 register 4 */
+sfr_b(ESIDAC1R4_H);                           /* ESI DAC1 register 4 */
+sfr_w(ESIDAC1R5);                             /* ESI DAC1 register 5 */
+sfr_b(ESIDAC1R5_L);                           /* ESI DAC1 register 5 */
+sfr_b(ESIDAC1R5_H);                           /* ESI DAC1 register 5 */
+sfr_w(ESIDAC1R6);                             /* ESI DAC1 register 6 */
+sfr_b(ESIDAC1R6_L);                           /* ESI DAC1 register 6 */
+sfr_b(ESIDAC1R6_H);                           /* ESI DAC1 register 6 */
+sfr_w(ESIDAC1R7);                             /* ESI DAC1 register 7 */
+sfr_b(ESIDAC1R7_L);                           /* ESI DAC1 register 7 */
+sfr_b(ESIDAC1R7_H);                           /* ESI DAC1 register 7 */
+sfr_w(ESIDAC2R0);                             /* ESI DAC2 register 0 */
+sfr_b(ESIDAC2R0_L);                           /* ESI DAC2 register 0 */
+sfr_b(ESIDAC2R0_H);                           /* ESI DAC2 register 0 */
+sfr_w(ESIDAC2R1);                             /* ESI DAC2 register 1 */
+sfr_b(ESIDAC2R1_L);                           /* ESI DAC2 register 1 */
+sfr_b(ESIDAC2R1_H);                           /* ESI DAC2 register 1 */
+sfr_w(ESIDAC2R2);                             /* ESI DAC2 register 2 */
+sfr_b(ESIDAC2R2_L);                           /* ESI DAC2 register 2 */
+sfr_b(ESIDAC2R2_H);                           /* ESI DAC2 register 2 */
+sfr_w(ESIDAC2R3);                             /* ESI DAC2 register 3 */
+sfr_b(ESIDAC2R3_L);                           /* ESI DAC2 register 3 */
+sfr_b(ESIDAC2R3_H);                           /* ESI DAC2 register 3 */
+sfr_w(ESIDAC2R4);                             /* ESI DAC2 register 4 */
+sfr_b(ESIDAC2R4_L);                           /* ESI DAC2 register 4 */
+sfr_b(ESIDAC2R4_H);                           /* ESI DAC2 register 4 */
+sfr_w(ESIDAC2R5);                             /* ESI DAC2 register 5 */
+sfr_b(ESIDAC2R5_L);                           /* ESI DAC2 register 5 */
+sfr_b(ESIDAC2R5_H);                           /* ESI DAC2 register 5 */
+sfr_w(ESIDAC2R6);                             /* ESI DAC2 register 6 */
+sfr_b(ESIDAC2R6_L);                           /* ESI DAC2 register 6 */
+sfr_b(ESIDAC2R6_H);                           /* ESI DAC2 register 6 */
+sfr_w(ESIDAC2R7);                             /* ESI DAC2 register 7 */
+sfr_b(ESIDAC2R7_L);                           /* ESI DAC2 register 7 */
+sfr_b(ESIDAC2R7_H);                           /* ESI DAC2 register 7 */
+sfr_w(ESITSM0);                               /* ESI TSM 0 */
+sfr_b(ESITSM0_L);                             /* ESI TSM 0 */
+sfr_b(ESITSM0_H);                             /* ESI TSM 0 */
+sfr_w(ESITSM1);                               /* ESI TSM 1 */
+sfr_b(ESITSM1_L);                             /* ESI TSM 1 */
+sfr_b(ESITSM1_H);                             /* ESI TSM 1 */
+sfr_w(ESITSM2);                               /* ESI TSM 2 */
+sfr_b(ESITSM2_L);                             /* ESI TSM 2 */
+sfr_b(ESITSM2_H);                             /* ESI TSM 2 */
+sfr_w(ESITSM3);                               /* ESI TSM 3 */
+sfr_b(ESITSM3_L);                             /* ESI TSM 3 */
+sfr_b(ESITSM3_H);                             /* ESI TSM 3 */
+sfr_w(ESITSM4);                               /* ESI TSM 4 */
+sfr_b(ESITSM4_L);                             /* ESI TSM 4 */
+sfr_b(ESITSM4_H);                             /* ESI TSM 4 */
+sfr_w(ESITSM5);                               /* ESI TSM 5 */
+sfr_b(ESITSM5_L);                             /* ESI TSM 5 */
+sfr_b(ESITSM5_H);                             /* ESI TSM 5 */
+sfr_w(ESITSM6);                               /* ESI TSM 6 */
+sfr_b(ESITSM6_L);                             /* ESI TSM 6 */
+sfr_b(ESITSM6_H);                             /* ESI TSM 6 */
+sfr_w(ESITSM7);                               /* ESI TSM 7 */
+sfr_b(ESITSM7_L);                             /* ESI TSM 7 */
+sfr_b(ESITSM7_H);                             /* ESI TSM 7 */
+sfr_w(ESITSM8);                               /* ESI TSM 8 */
+sfr_b(ESITSM8_L);                             /* ESI TSM 8 */
+sfr_b(ESITSM8_H);                             /* ESI TSM 8 */
+sfr_w(ESITSM9);                               /* ESI TSM 9 */
+sfr_b(ESITSM9_L);                             /* ESI TSM 9 */
+sfr_b(ESITSM9_H);                             /* ESI TSM 9 */
+sfr_w(ESITSM10);                              /* ESI TSM 10 */
+sfr_b(ESITSM10_L);                            /* ESI TSM 10 */
+sfr_b(ESITSM10_H);                            /* ESI TSM 10 */
+sfr_w(ESITSM11);                              /* ESI TSM 11 */
+sfr_b(ESITSM11_L);                            /* ESI TSM 11 */
+sfr_b(ESITSM11_H);                            /* ESI TSM 11 */
+sfr_w(ESITSM12);                              /* ESI TSM 12 */
+sfr_b(ESITSM12_L);                            /* ESI TSM 12 */
+sfr_b(ESITSM12_H);                            /* ESI TSM 12 */
+sfr_w(ESITSM13);                              /* ESI TSM 13 */
+sfr_b(ESITSM13_L);                            /* ESI TSM 13 */
+sfr_b(ESITSM13_H);                            /* ESI TSM 13 */
+sfr_w(ESITSM14);                              /* ESI TSM 14 */
+sfr_b(ESITSM14_L);                            /* ESI TSM 14 */
+sfr_b(ESITSM14_H);                            /* ESI TSM 14 */
+sfr_w(ESITSM15);                              /* ESI TSM 15 */
+sfr_b(ESITSM15_L);                            /* ESI TSM 15 */
+sfr_b(ESITSM15_H);                            /* ESI TSM 15 */
+sfr_w(ESITSM16);                              /* ESI TSM 16 */
+sfr_b(ESITSM16_L);                            /* ESI TSM 16 */
+sfr_b(ESITSM16_H);                            /* ESI TSM 16 */
+sfr_w(ESITSM17);                              /* ESI TSM 17 */
+sfr_b(ESITSM17_L);                            /* ESI TSM 17 */
+sfr_b(ESITSM17_H);                            /* ESI TSM 17 */
+sfr_w(ESITSM18);                              /* ESI TSM 18 */
+sfr_b(ESITSM18_L);                            /* ESI TSM 18 */
+sfr_b(ESITSM18_H);                            /* ESI TSM 18 */
+sfr_w(ESITSM19);                              /* ESI TSM 19 */
+sfr_b(ESITSM19_L);                            /* ESI TSM 19 */
+sfr_b(ESITSM19_H);                            /* ESI TSM 19 */
+sfr_w(ESITSM20);                              /* ESI TSM 20 */
+sfr_b(ESITSM20_L);                            /* ESI TSM 20 */
+sfr_b(ESITSM20_H);                            /* ESI TSM 20 */
+sfr_w(ESITSM21);                              /* ESI TSM 21 */
+sfr_b(ESITSM21_L);                            /* ESI TSM 21 */
+sfr_b(ESITSM21_H);                            /* ESI TSM 21 */
+sfr_w(ESITSM22);                              /* ESI TSM 22 */
+sfr_b(ESITSM22_L);                            /* ESI TSM 22 */
+sfr_b(ESITSM22_H);                            /* ESI TSM 22 */
+sfr_w(ESITSM23);                              /* ESI TSM 23 */
+sfr_b(ESITSM23_L);                            /* ESI TSM 23 */
+sfr_b(ESITSM23_H);                            /* ESI TSM 23 */
+sfr_w(ESITSM24);                              /* ESI TSM 24 */
+sfr_b(ESITSM24_L);                            /* ESI TSM 24 */
+sfr_b(ESITSM24_H);                            /* ESI TSM 24 */
+sfr_w(ESITSM25);                              /* ESI TSM 25 */
+sfr_b(ESITSM25_L);                            /* ESI TSM 25 */
+sfr_b(ESITSM25_H);                            /* ESI TSM 25 */
+sfr_w(ESITSM26);                              /* ESI TSM 26 */
+sfr_b(ESITSM26_L);                            /* ESI TSM 26 */
+sfr_b(ESITSM26_H);                            /* ESI TSM 26 */
+sfr_w(ESITSM27);                              /* ESI TSM 27 */
+sfr_b(ESITSM27_L);                            /* ESI TSM 27 */
+sfr_b(ESITSM27_H);                            /* ESI TSM 27 */
+sfr_w(ESITSM28);                              /* ESI TSM 28 */
+sfr_b(ESITSM28_L);                            /* ESI TSM 28 */
+sfr_b(ESITSM28_H);                            /* ESI TSM 28 */
+sfr_w(ESITSM29);                              /* ESI TSM 29 */
+sfr_b(ESITSM29_L);                            /* ESI TSM 29 */
+sfr_b(ESITSM29_H);                            /* ESI TSM 29 */
+sfr_w(ESITSM30);                              /* ESI TSM 30 */
+sfr_b(ESITSM30_L);                            /* ESI TSM 30 */
+sfr_b(ESITSM30_H);                            /* ESI TSM 30 */
+sfr_w(ESITSM31);                              /* ESI TSM 31 */
+sfr_b(ESITSM31_L);                            /* ESI TSM 31 */
+sfr_b(ESITSM31_H);                            /* ESI TSM 31 */
+
+/* ESIIV Control Bits */
+
+#define ESIIV_NONE             (0x0000)       /* No ESI Interrupt Pending */
+#define ESIIV_ESIIFG1          (0x0002)       /* rising edge of the ESISTOP(tsm) */
+#define ESIIV_ESIIFG0          (0x0004)       /* ESIOUT0 to ESIOUT3 conditions selected by ESIIFGSETx bits */
+#define ESIIV_ESIIFG8          (0x0006)       /* ESIOUT4 to ESIOUT7 conditions selected by ESIIFGSET2x bits */
+#define ESIIV_ESIIFG3          (0x0008)       /* ESICNT1 counter conditions selected with the ESITHR1 and ESITHR2 registers */
+#define ESIIV_ESIIFG6          (0x000A)       /* PSM transitions to a state with a Q7 bit */
+#define ESIIV_ESIIFG5          (0x000C)       /* PSM transitions to a state with a Q6 bit */
+#define ESIIV_ESIIFG4          (0x000E)       /* ESICNT2 counter conditions selected with the ESIIS2x bits */
+#define ESIIV_ESIIFG7          (0x0010)       /* ESICNT0 counter conditions selected with the ESIIS0x bits */
+#define ESIIV_ESIIFG2          (0x0012)       /* start of a TSM sequence */
+
+/* ESIINT1 Control Bits */
+#define ESIIFGSET22            (0x8000)       /* ESIIFG8 interrupt flag source */
+#define ESIIFGSET21            (0x4000)       /* ESIIFG8 interrupt flag source */
+#define ESIIFGSET20            (0x2000)       /* ESIIFG8 interrupt flag source */
+#define ESIIFGSET12            (0x1000)       /* ESIIFG0 interrupt flag source */
+#define ESIIFGSET11            (0x0800)       /* ESIIFG0 interrupt flag source */
+#define ESIIFGSET10            (0x0400)       /* ESIIFG0 interrupt flag source */
+#define ESIIE8                 (0x0100)       /* Interrupt enable */
+#define ESIIE7                 (0x0080)       /* Interrupt enable */
+#define ESIIE6                 (0x0040)       /* Interrupt enable */
+#define ESIIE5                 (0x0020)       /* Interrupt enable */
+#define ESIIE4                 (0x0010)       /* Interrupt enable */
+#define ESIIE3                 (0x0008)       /* Interrupt enable */
+#define ESIIE2                 (0x0004)       /* Interrupt enable */
+#define ESIIE1                 (0x0002)       /* Interrupt enable */
+#define ESIIE0                 (0x0001)       /* Interrupt enable */
+
+/* ESIINT1 Control Bits */
+#define ESIIE7_L               (0x0080)       /* Interrupt enable */
+#define ESIIE6_L               (0x0040)       /* Interrupt enable */
+#define ESIIE5_L               (0x0020)       /* Interrupt enable */
+#define ESIIE4_L               (0x0010)       /* Interrupt enable */
+#define ESIIE3_L               (0x0008)       /* Interrupt enable */
+#define ESIIE2_L               (0x0004)       /* Interrupt enable */
+#define ESIIE1_L               (0x0002)       /* Interrupt enable */
+#define ESIIE0_L               (0x0001)       /* Interrupt enable */
+
+/* ESIINT1 Control Bits */
+#define ESIIFGSET22_H          (0x0080)       /* ESIIFG8 interrupt flag source */
+#define ESIIFGSET21_H          (0x0040)       /* ESIIFG8 interrupt flag source */
+#define ESIIFGSET20_H          (0x0020)       /* ESIIFG8 interrupt flag source */
+#define ESIIFGSET12_H          (0x0010)       /* ESIIFG0 interrupt flag source */
+#define ESIIFGSET11_H          (0x0008)       /* ESIIFG0 interrupt flag source */
+#define ESIIFGSET10_H          (0x0004)       /* ESIIFG0 interrupt flag source */
+#define ESIIE8_H               (0x0001)       /* Interrupt enable */
+
+#define ESIIFGSET2_0           (0x0000)       /* ESIIFG8 is set when ESIOUT4 is set */
+#define ESIIFGSET2_1           (0x2000)       /* ESIIFG8 is set when ESIOUT4 is reset */
+#define ESIIFGSET2_2           (0x4000)       /* ESIIFG8 is set when ESIOUT5 is set */
+#define ESIIFGSET2_3           (0x6000)       /* ESIIFG8 is set when ESIOUT5 is reset */
+#define ESIIFGSET2_4           (0x8000)       /* ESIIFG8 is set when ESIOUT6 is set */
+#define ESIIFGSET2_5           (0xA000)       /* ESIIFG8 is set when ESIOUT6 is reset */
+#define ESIIFGSET2_6           (0xC000)       /* ESIIFG8 is set when ESIOUT7 is set */
+#define ESIIFGSET2_7           (0xE000)       /* ESIIFG8 is set when ESIOUT7 is reset */
+#define ESIIFGSET1_0           (0x0000)       /* ESIIFG0 is set when ESIOUT0 is set */
+#define ESIIFGSET1_1           (0x0400)       /* ESIIFG0 is set when ESIOUT0 is reset */
+#define ESIIFGSET1_2           (0x0800)       /* ESIIFG0 is set when ESIOUT1 is set */
+#define ESIIFGSET1_3           (0x0C00)       /* ESIIFG0 is set when ESIOUT1 is reset */
+#define ESIIFGSET1_4           (0x1000)       /* ESIIFG0 is set when ESIOUT2 is set */
+#define ESIIFGSET1_5           (0x1400)       /* ESIIFG0 is set when ESIOUT2 is reset */
+#define ESIIFGSET1_6           (0x1800)       /* ESIIFG0 is set when ESIOUT3 is set */
+#define ESIIFGSET1_7           (0x1C00)       /* ESIIFG0 is set when ESIOUT3 is reset */
+
+/* ESIINT2 Control Bits */
+#define ESIIS21                (0x4000)       /* SIFIFG4 interrupt flag source */
+#define ESIIS20                (0x2000)       /* SIFIFG4 interrupt flag source */
+#define ESIIS01                (0x0800)       /* SIFIFG7 interrupt flag source */
+#define ESIIS00                (0x0400)       /* SIFIFG7 interrupt flag source */
+#define ESIIFG8                (0x0100)       /* ESIIFG8 interrupt pending */
+#define ESIIFG7                (0x0080)       /* ESIIFG7 interrupt pending */
+#define ESIIFG6                (0x0040)       /* ESIIFG6 interrupt pending */
+#define ESIIFG5                (0x0020)       /* ESIIFG5 interrupt pending */
+#define ESIIFG4                (0x0010)       /* ESIIFG4 interrupt pending */
+#define ESIIFG3                (0x0008)       /* ESIIFG3 interrupt pending */
+#define ESIIFG2                (0x0004)       /* ESIIFG2 interrupt pending */
+#define ESIIFG1                (0x0002)       /* ESIIFG1 interrupt pending */
+#define ESIIFG0                (0x0001)       /* ESIIFG0 interrupt pending */
+
+/* ESIINT2 Control Bits */
+#define ESIIFG7_L              (0x0080)       /* ESIIFG7 interrupt pending */
+#define ESIIFG6_L              (0x0040)       /* ESIIFG6 interrupt pending */
+#define ESIIFG5_L              (0x0020)       /* ESIIFG5 interrupt pending */
+#define ESIIFG4_L              (0x0010)       /* ESIIFG4 interrupt pending */
+#define ESIIFG3_L              (0x0008)       /* ESIIFG3 interrupt pending */
+#define ESIIFG2_L              (0x0004)       /* ESIIFG2 interrupt pending */
+#define ESIIFG1_L              (0x0002)       /* ESIIFG1 interrupt pending */
+#define ESIIFG0_L              (0x0001)       /* ESIIFG0 interrupt pending */
+
+/* ESIINT2 Control Bits */
+#define ESIIS21_H              (0x0040)       /* SIFIFG4 interrupt flag source */
+#define ESIIS20_H              (0x0020)       /* SIFIFG4 interrupt flag source */
+#define ESIIS01_H              (0x0008)       /* SIFIFG7 interrupt flag source */
+#define ESIIS00_H              (0x0004)       /* SIFIFG7 interrupt flag source */
+#define ESIIFG8_H              (0x0001)       /* ESIIFG8 interrupt pending */
+
+#define ESIIS2_0               (0x0000)       /* SIFIFG4 interrupt flag source: SIFCNT2 */
+#define ESIIS2_1               (0x2000)       /* SIFIFG4 interrupt flag source: SIFCNT2 MOD 4 */
+#define ESIIS2_2               (0x4000)       /* SIFIFG4 interrupt flag source: SIFCNT2 MOD 256 */
+#define ESIIS2_3               (0x6000)       /* SIFIFG4 interrupt flag source: SIFCNT2 decrements from 01h to 00h */
+#define ESIIS0_0               (0x0000)       /* SIFIFG7 interrupt flag source: SIFCNT0 */
+#define ESIIS0_1               (0x0400)       /* SIFIFG7 interrupt flag source: SIFCNT0 MOD 4 */
+#define ESIIS0_2               (0x0800)       /* SIFIFG7 interrupt flag source: SIFCNT0 MOD 256 */
+#define ESIIS0_3               (0x0C00)       /* SIFIFG7 interrupt flag source: SIFCNT0 increments from FFFFh to 00h */
+
+/* ESIAFE Control Bits */
+#define ESIDAC2EN              (0x0800)       /* Enable ESIDAC(tsm) control for DAC in AFE2 */
+#define ESICA2EN               (0x0400)       /* Enable ESICA(tsm) control for comparator in AFE2 */
+#define ESICA2INV              (0x0200)       /* Invert AFE2's comparator output */
+#define ESICA1INV              (0x0100)       /* Invert AFE1's comparator output */
+#define ESICA2X                (0x0080)       /* AFE2's comparator input select */
+#define ESICA1X                (0x0040)       /* AFE1's comparator input select */
+#define ESICISEL               (0x0020)       /* Comparator input select for AFE1 only */
+#define ESICACI3               (0x0010)       /* Comparator input select for AFE1 only */
+#define ESISHTSM               (0x0008)       /* Sample-and-hold ESIVSS select */
+#define ESIVMIDEN              (0x0004)       /* Mid-voltage generator */
+#define ESISH                  (0x0002)       /* Sample-and-hold enable */
+#define ESITEN                 (0x0001)       /* Excitation enable */
+
+/* ESIAFE Control Bits */
+#define ESICA2X_L              (0x0080)       /* AFE2's comparator input select */
+#define ESICA1X_L              (0x0040)       /* AFE1's comparator input select */
+#define ESICISEL_L             (0x0020)       /* Comparator input select for AFE1 only */
+#define ESICACI3_L             (0x0010)       /* Comparator input select for AFE1 only */
+#define ESISHTSM_L             (0x0008)       /* Sample-and-hold ESIVSS select */
+#define ESIVMIDEN_L            (0x0004)       /* Mid-voltage generator */
+#define ESISH_L                (0x0002)       /* Sample-and-hold enable */
+#define ESITEN_L               (0x0001)       /* Excitation enable */
+
+/* ESIAFE Control Bits */
+#define ESIDAC2EN_H            (0x0008)       /* Enable ESIDAC(tsm) control for DAC in AFE2 */
+#define ESICA2EN_H             (0x0004)       /* Enable ESICA(tsm) control for comparator in AFE2 */
+#define ESICA2INV_H            (0x0002)       /* Invert AFE2's comparator output */
+#define ESICA1INV_H            (0x0001)       /* Invert AFE1's comparator output */
+
+#define ESIVSS                 (0x0008)       /* legacy define: Sample-and-hold ESIVSS select */
+#define ESIVCC2                (0x0004)       /* legacy define: Mid-voltage generator */
+
+/* ESIPPU Control Bits */
+#define ESITCHOUT1             (0x0200)       /* Latched AFE1 comparator output for test channel 1 */
+#define ESITCHOUT0             (0x0100)       /* Lachted AFE1 comparator output for test channel 0 */
+#define ESIOUT7                (0x0080)       /* Latched AFE2 comparator output when ESICH3 input is selected */
+#define ESIOUT6                (0x0040)       /* Latched AFE2 comparator output when ESICH2 input is selected */
+#define ESIOUT5                (0x0020)       /* Latched AFE2 comparator output when ESICH1 input is selected */
+#define ESIOUT4                (0x0010)       /* Latched AFE2 comparator output when ESICH0 input is selected */
+#define ESIOUT3                (0x0008)       /* Latched AFE1 comparator output when ESICH3 input is selected */
+#define ESIOUT2                (0x0004)       /* Latched AFE1 comparator output when ESICH2 input is selected */
+#define ESIOUT1                (0x0002)       /* Latched AFE1 comparator output when ESICH1 input is selected */
+#define ESIOUT0                (0x0001)       /* Latched AFE1 comparator output when ESICH0 input is selected */
+
+/* ESIPPU Control Bits */
+#define ESIOUT7_L              (0x0080)       /* Latched AFE2 comparator output when ESICH3 input is selected */
+#define ESIOUT6_L              (0x0040)       /* Latched AFE2 comparator output when ESICH2 input is selected */
+#define ESIOUT5_L              (0x0020)       /* Latched AFE2 comparator output when ESICH1 input is selected */
+#define ESIOUT4_L              (0x0010)       /* Latched AFE2 comparator output when ESICH0 input is selected */
+#define ESIOUT3_L              (0x0008)       /* Latched AFE1 comparator output when ESICH3 input is selected */
+#define ESIOUT2_L              (0x0004)       /* Latched AFE1 comparator output when ESICH2 input is selected */
+#define ESIOUT1_L              (0x0002)       /* Latched AFE1 comparator output when ESICH1 input is selected */
+#define ESIOUT0_L              (0x0001)       /* Latched AFE1 comparator output when ESICH0 input is selected */
+
+/* ESIPPU Control Bits */
+#define ESITCHOUT1_H           (0x0002)       /* Latched AFE1 comparator output for test channel 1 */
+#define ESITCHOUT0_H           (0x0001)       /* Lachted AFE1 comparator output for test channel 0 */
+
+/* ESITSM Control Bits */
+#define ESICLKAZSEL            (0x4000)       /* Functionality selection of ESITSMx bit5 */
+#define ESITSMTRG1             (0x2000)       /* TSM start trigger selection */
+#define ESITSMTRG0             (0x1000)       /* TSM start trigger selection */
+#define ESISTART               (0x0800)       /* TSM software start trigger */
+#define ESITSMRP               (0x0400)       /* TSM repeat modee */
+#define ESIDIV3B2              (0x0200)       /* TSM start trigger ACLK divider */
+#define ESIDIV3B1              (0x0100)       /* TSM start trigger ACLK divider */
+#define ESIDIV3B0              (0x0080)       /* TSM start trigger ACLK divider */
+#define ESIDIV3A2              (0x0040)       /* TSM start trigger ACLK divider */
+#define ESIDIV3A1              (0x0020)       /* TSM start trigger ACLK divider */
+#define ESIDIV3A0              (0x0010)       /* TSM start trigger ACLK divider */
+#define ESIDIV21               (0x0008)       /* ACLK divider */
+#define ESIDIV20               (0x0004)       /* ACLK divider */
+#define ESIDIV11               (0x0002)       /* TSM SMCLK divider */
+#define ESIDIV10               (0x0001)       /* TSM SMCLK divider */
+
+/* ESITSM Control Bits */
+#define ESIDIV3B0_L            (0x0080)       /* TSM start trigger ACLK divider */
+#define ESIDIV3A2_L            (0x0040)       /* TSM start trigger ACLK divider */
+#define ESIDIV3A1_L            (0x0020)       /* TSM start trigger ACLK divider */
+#define ESIDIV3A0_L            (0x0010)       /* TSM start trigger ACLK divider */
+#define ESIDIV21_L             (0x0008)       /* ACLK divider */
+#define ESIDIV20_L             (0x0004)       /* ACLK divider */
+#define ESIDIV11_L             (0x0002)       /* TSM SMCLK divider */
+#define ESIDIV10_L             (0x0001)       /* TSM SMCLK divider */
+
+/* ESITSM Control Bits */
+#define ESICLKAZSEL_H          (0x0040)       /* Functionality selection of ESITSMx bit5 */
+#define ESITSMTRG1_H           (0x0020)       /* TSM start trigger selection */
+#define ESITSMTRG0_H           (0x0010)       /* TSM start trigger selection */
+#define ESISTART_H             (0x0008)       /* TSM software start trigger */
+#define ESITSMRP_H             (0x0004)       /* TSM repeat modee */
+#define ESIDIV3B2_H            (0x0002)       /* TSM start trigger ACLK divider */
+#define ESIDIV3B1_H            (0x0001)       /* TSM start trigger ACLK divider */
+
+#define ESITSMTRG_0            (0x0000)       /* Halt mode */
+#define ESITSMTRG_1            (0x1000)       /* TSM start trigger ACLK divider */
+#define ESITSMTRG_2            (0x2000)       /* Software trigger for TSM */
+#define ESITSMTRG_3            (0x3000)       /* Either the ACLK divider or the ESISTART biT */
+#define ESIDIV3B_0             (0x0000)       /* TSM start trigger ACLK divider */
+#define ESIDIV3B_1             (0x0080)       /* TSM start trigger ACLK divider */
+#define ESIDIV3B_2             (0x0100)       /* TSM start trigger ACLK divider */
+#define ESIDIV3B_3             (0x0180)       /* TSM start trigger ACLK divider */
+#define ESIDIV3B_4             (0x0200)       /* TSM start trigger ACLK divider */
+#define ESIDIV3B_5             (0x0280)       /* TSM start trigger ACLK divider */
+#define ESIDIV3B_6             (0x0300)       /* TSM start trigger ACLK divider */
+#define ESIDIV3B_7             (0x0380)       /* TSM start trigger ACLK divider */
+#define ESIDIV3A_0             (0x0000)       /* TSM start trigger ACLK divider */
+#define ESIDIV3A_1             (0x0010)       /* TSM start trigger ACLK divider */
+#define ESIDIV3A_2             (0x0020)       /* TSM start trigger ACLK divider */
+#define ESIDIV3A_3             (0x0030)       /* TSM start trigger ACLK divider */
+#define ESIDIV3A_4             (0x0040)       /* TSM start trigger ACLK divider */
+#define ESIDIV3A_5             (0x0050)       /* TSM start trigger ACLK divider */
+#define ESIDIV3A_6             (0x0060)       /* TSM start trigger ACLK divider */
+#define ESIDIV3A_7             (0x0070)       /* TSM start trigger ACLK divider */
+#define ESIDIV2_0              (0x0000)       /* ACLK divider mode: 0 */
+#define ESIDIV2_1              (0x0004)       /* ACLK divider mode: 1 */
+#define ESIDIV2_2              (0x0008)       /* ACLK divider mode: 2 */
+#define ESIDIV2_3              (0x000C)       /* ACLK divider mode: 3 */
+#define ESIDIV2__1             (0x0000)       /* ACLK divider = /1 */
+#define ESIDIV2__2             (0x0004)       /* ACLK divider = /2 */
+#define ESIDIV2__4             (0x0008)       /* ACLK divider = /4 */
+#define ESIDIV2__8             (0x000C)       /* ACLK divider = /8 */
+#define ESIDIV1_0              (0x0000)       /* TSM SMCLK/ESIOSC divider mode: 0 */
+#define ESIDIV1_1              (0x0001)       /* TSM SMCLK/ESIOSC divider mode: 1 */
+#define ESIDIV1_2              (0x0002)       /* TSM SMCLK/ESIOSC divider mode: 2 */
+#define ESIDIV1_3              (0x0003)       /* TSM SMCLK/ESIOSC divider mode: 3 */
+#define ESIDIV1__1             (0x0000)       /* TSM SMCLK/ESIOSC divider = /1 */
+#define ESIDIV1__2             (0x0001)       /* TSM SMCLK/ESIOSC divider = /2 */
+#define ESIDIV1__4             (0x0002)       /* TSM SMCLK/ESIOSC divider = /4 */
+#define ESIDIV1__8             (0x0003)       /* TSM SMCLK/ESIOSC divider = /8 */
+
+/* ESIPSM Control Bits */
+#define ESICNT2RST             (0x8000)       /* ESI Counter 2 reset */
+#define ESICNT1RST             (0x4000)       /* ESI Counter 1 reset */
+#define ESICNT0RST             (0x2000)       /* ESI Counter 0 reset */
+#define ESITEST4SEL1           (0x0200)       /* Output signal selection for SIFTEST4 pin */
+#define ESITEST4SEL0           (0x0100)       /* Output signal selection for SIFTEST4 pin */
+#define ESIV2SEL               (0x0080)       /* Source Selection for V2 bit*/
+#define ESICNT2EN              (0x0020)       /* ESICNT2 enable (down counter) */
+#define ESICNT1EN              (0x0010)       /* ESICNT1 enable (up/down counter) */
+#define ESICNT0EN              (0x0008)       /* ESICNT0 enable (up counter) */
+#define ESIQ7TRG               (0x0004)       /* Enabling to use Q7 as trigger for a TSM sequence */
+#define ESIQ6EN                (0x0001)       /* Q6 enable */
+
+/* ESIPSM Control Bits */
+#define ESIV2SEL_L             (0x0080)       /* Source Selection for V2 bit*/
+#define ESICNT2EN_L            (0x0020)       /* ESICNT2 enable (down counter) */
+#define ESICNT1EN_L            (0x0010)       /* ESICNT1 enable (up/down counter) */
+#define ESICNT0EN_L            (0x0008)       /* ESICNT0 enable (up counter) */
+#define ESIQ7TRG_L             (0x0004)       /* Enabling to use Q7 as trigger for a TSM sequence */
+#define ESIQ6EN_L              (0x0001)       /* Q6 enable */
+
+/* ESIPSM Control Bits */
+#define ESICNT2RST_H           (0x0080)       /* ESI Counter 2 reset */
+#define ESICNT1RST_H           (0x0040)       /* ESI Counter 1 reset */
+#define ESICNT0RST_H           (0x0020)       /* ESI Counter 0 reset */
+#define ESITEST4SEL1_H         (0x0002)       /* Output signal selection for SIFTEST4 pin */
+#define ESITEST4SEL0_H         (0x0001)       /* Output signal selection for SIFTEST4 pin */
+
+#define ESITEST4SEL_0          (0x0000)       /* Q1 signal from PSM table */
+#define ESITEST4SEL_1          (0x0100)       /* Q2 signal from PSM table */
+#define ESITEST4SEL_2          (0x0200)       /* TSM clock signal from Timing State Machine */
+#define ESITEST4SEL_3          (0x0300)       /* AFE1's comparator output signal Comp1Out */
+
+/* ESIOSC Control Bits */
+#define ESICLKFQ5              (0x2000)       /* Internal oscillator frequency adjust */
+#define ESICLKFQ4              (0x1000)       /* Internal oscillator frequency adjust */
+#define ESICLKFQ3              (0x0800)       /* Internal oscillator frequency adjust */
+#define ESICLKFQ2              (0x0400)       /* Internal oscillator frequency adjust */
+#define ESICLKFQ1              (0x0200)       /* Internal oscillator frequency adjust */
+#define ESICLKFQ0              (0x0100)       /* Internal oscillator frequency adjust */
+#define ESICLKGON              (0x0002)       /* Internal oscillator control */
+#define ESIHFSEL               (0x0001)       /* Internal oscillator enable */
+
+/* ESIOSC Control Bits */
+#define ESICLKGON_L            (0x0002)       /* Internal oscillator control */
+#define ESIHFSEL_L             (0x0001)       /* Internal oscillator enable */
+
+/* ESIOSC Control Bits */
+#define ESICLKFQ5_H            (0x0020)       /* Internal oscillator frequency adjust */
+#define ESICLKFQ4_H            (0x0010)       /* Internal oscillator frequency adjust */
+#define ESICLKFQ3_H            (0x0008)       /* Internal oscillator frequency adjust */
+#define ESICLKFQ2_H            (0x0004)       /* Internal oscillator frequency adjust */
+#define ESICLKFQ1_H            (0x0002)       /* Internal oscillator frequency adjust */
+#define ESICLKFQ0_H            (0x0001)       /* Internal oscillator frequency adjust */
+
+/* ESICTL Control Bits */
+#define ESIS3SEL2              (0x8000)       /* PPUS3 source select */
+#define ESIS3SEL1              (0x4000)       /* PPUS3 source select */
+#define ESIS3SEL0              (0x2000)       /* PPUS3 source select */
+#define ESIS2SEL2              (0x1000)       /* PPUS2 source select */
+#define ESIS2SEL1              (0x0800)       /* PPUS2 source select */
+#define ESIS2SEL0              (0x0400)       /* PPUS2 source select */
+#define ESIS1SEL2              (0x0200)       /* PPUS1 source select */
+#define ESIS1SEL1              (0x0100)       /* PPUS1 source select */
+#define ESIS1SEL0              (0x0080)       /* PPUS1 source select */
+#define ESITCH11               (0x0040)       /* select the comparator input for test channel 1 */
+#define ESITCH10               (0x0020)       /* select the comparator input for test channel 1 */
+#define ESITCH01               (0x0010)       /* select the comparator input for test channel 0 */
+#define ESITCH00               (0x0008)       /* select the comparator input for test channel 0 */
+#define ESICS                  (0x0004)       /* Comparator output/Timer_A input selection */
+#define ESITESTD               (0x0002)       /* Test cycle insertion */
+#define ESIEN                  (0x0001)       /* Extended Scan interface enable */
+
+/* ESICTL Control Bits */
+#define ESIS1SEL0_L            (0x0080)       /* PPUS1 source select */
+#define ESITCH11_L             (0x0040)       /* select the comparator input for test channel 1 */
+#define ESITCH10_L             (0x0020)       /* select the comparator input for test channel 1 */
+#define ESITCH01_L             (0x0010)       /* select the comparator input for test channel 0 */
+#define ESITCH00_L             (0x0008)       /* select the comparator input for test channel 0 */
+#define ESICS_L                (0x0004)       /* Comparator output/Timer_A input selection */
+#define ESITESTD_L             (0x0002)       /* Test cycle insertion */
+#define ESIEN_L                (0x0001)       /* Extended Scan interface enable */
+
+/* ESICTL Control Bits */
+#define ESIS3SEL2_H            (0x0080)       /* PPUS3 source select */
+#define ESIS3SEL1_H            (0x0040)       /* PPUS3 source select */
+#define ESIS3SEL0_H            (0x0020)       /* PPUS3 source select */
+#define ESIS2SEL2_H            (0x0010)       /* PPUS2 source select */
+#define ESIS2SEL1_H            (0x0008)       /* PPUS2 source select */
+#define ESIS2SEL0_H            (0x0004)       /* PPUS2 source select */
+#define ESIS1SEL2_H            (0x0002)       /* PPUS1 source select */
+#define ESIS1SEL1_H            (0x0001)       /* PPUS1 source select */
+
+#define ESIS3SEL_0             (0x0000)       /* ESIOUT0 is the PPUS3 source */
+#define ESIS3SEL_1             (0x2000)       /* ESIOUT1 is the PPUS3 source */
+#define ESIS3SEL_2             (0x4000)       /* ESIOUT2 is the PPUS3 source */
+#define ESIS3SEL_3             (0x6000)       /* ESIOUT3 is the PPUS3 source */
+#define ESIS3SEL_4             (0x8000)       /* ESIOUT4 is the PPUS3 source */
+#define ESIS3SEL_5             (0xA000)       /* ESIOUT5 is the PPUS3 source */
+#define ESIS3SEL_6             (0xC000)       /* ESIOUT6 is the PPUS3 source */
+#define ESIS3SEL_7             (0xE000)       /* ESIOUT7 is the PPUS3 source */
+#define ESIS2SEL_0             (0x0000)       /* ESIOUT0 is the PPUS2 source */
+#define ESIS2SEL_1             (0x0400)       /* ESIOUT1 is the PPUS2 source */
+#define ESIS2SEL_2             (0x0800)       /* ESIOUT2 is the PPUS2 source */
+#define ESIS2SEL_3             (0x0C00)       /* ESIOUT3 is the PPUS2 source */
+#define ESIS2SEL_4             (0x1000)       /* ESIOUT4 is the PPUS2 source */
+#define ESIS2SEL_5             (0x1400)       /* ESIOUT5 is the PPUS2 source */
+#define ESIS2SEL_6             (0x1800)       /* ESIOUT6 is the PPUS2 source */
+#define ESIS2SEL_7             (0x1C00)       /* ESIOUT7 is the PPUS2 source */
+#define ESIS1SEL_0             (0x0000)       /* ESIOUT0 is the PPUS1 source */
+#define ESIS1SEL_1             (0x0080)       /* ESIOUT1 is the PPUS1 source */
+#define ESIS1SEL_2             (0x0100)       /* ESIOUT2 is the PPUS1 source */
+#define ESIS1SEL_3             (0x0180)       /* ESIOUT3 is the PPUS1 source */
+#define ESIS1SEL_4             (0x0200)       /* ESIOUT4 is the PPUS1 source */
+#define ESIS1SEL_5             (0x0280)       /* ESIOUT5 is the PPUS1 source */
+#define ESIS1SEL_6             (0x0300)       /* ESIOUT6 is the PPUS1 source */
+#define ESIS1SEL_7             (0x0380)       /* ESIOUT7 is the PPUS1 source */
+#define ESITCH1_0              (0x0000)       /* Comparator input is ESICH0 when ESICAX = 0; Comparator input is ESICI0 when ESICAX = 1 */
+#define ESITCH1_1              (0x0400)       /* Comparator input is ESICH1 when ESICAX = 0; Comparator input is ESICI1 when ESICAX = 1 */
+#define ESITCH1_2              (0x0800)       /* Comparator input is ESICH2 when ESICAX = 0; Comparator input is ESICI2 when ESICAX = 1 */
+#define ESITCH1_3              (0x0C00)       /* Comparator input is ESICH3 when ESICAX = 0; Comparator input is ESICI3 when ESICAX = 1 */
+#define ESITCH0_0              (0x0000)       /* Comparator input is ESICH0 when ESICAX = 0; Comparator input is ESICI0 when ESICAX = 1 */
+#define ESITCH0_1              (0x0008)       /* Comparator input is ESICH1 when ESICAX = 0; Comparator input is ESICI1 when ESICAX = 1 */
+#define ESITCH0_2              (0x0010)       /* Comparator input is ESICH2 when ESICAX = 0; Comparator input is ESICI2 when ESICAX = 1 */
+#define ESITCH0_3              (0x0018)       /* Comparator input is ESICH3 when ESICAX = 0; Comparator input is ESICI3 when ESICAX = 1 */
+
+/* Timing State Machine Control Bits */
+#define ESIREPEAT4             (0x8000)       /* These bits together with the ESICLK bit configure the duration of this state */
+#define ESIREPEAT3             (0x4000)       /* ESIREPEATx selects the number of clock cycles for this state. The number of clock cycles = ESIREPEATx + 1 */
+#define ESIREPEAT2             (0x2000)       /* */
+#define ESIREPEAT1             (0x1000)       /* */
+#define ESIREPEAT0             (0x0800)       /* */
+#define ESICLK                 (0x0400)       /* This bit selects the clock source for the TSM */
+#define ESISTOP                (0x0200)       /* This bit indicates the end of the TSM sequence */
+#define ESIDAC                 (0x0100)       /* TSM DAC on */
+#define ESITESTS1              (0x0080)       /* TSM test cycle control */
+#define ESIRSON                (0x0040)       /* Internal output latches enabled */
+#define ESICLKON               (0x0020)       /* High-frequency clock on */
+#define ESICA                  (0x0010)       /* TSM comparator on */
+#define ESIEX                  (0x0008)       /* Excitation and sample-and-hold */
+#define ESILCEN                (0x0004)       /* LC enable */
+#define ESICH1                 (0x0002)       /* Input channel select */
+#define ESICH0                 (0x0001)       /* Input channel select */
+
+/* Timing State Machine Control Bits */
+#define ESITESTS1_L            (0x0080)       /* TSM test cycle control */
+#define ESIRSON_L              (0x0040)       /* Internal output latches enabled */
+#define ESICLKON_L             (0x0020)       /* High-frequency clock on */
+#define ESICA_L                (0x0010)       /* TSM comparator on */
+#define ESIEX_L                (0x0008)       /* Excitation and sample-and-hold */
+#define ESILCEN_L              (0x0004)       /* LC enable */
+#define ESICH1_L               (0x0002)       /* Input channel select */
+#define ESICH0_L               (0x0001)       /* Input channel select */
+
+/* Timing State Machine Control Bits */
+#define ESIREPEAT4_H           (0x0080)       /* These bits together with the ESICLK bit configure the duration of this state */
+#define ESIREPEAT3_H           (0x0040)       /* ESIREPEATx selects the number of clock cycles for this state. The number of clock cycles = ESIREPEATx + 1 */
+#define ESIREPEAT2_H           (0x0020)       /* */
+#define ESIREPEAT1_H           (0x0010)       /* */
+#define ESIREPEAT0_H           (0x0008)       /* */
+#define ESICLK_H               (0x0004)       /* This bit selects the clock source for the TSM */
+#define ESISTOP_H              (0x0002)       /* This bit indicates the end of the TSM sequence */
+#define ESIDAC_H               (0x0001)       /* TSM DAC on */
+
+#define ESICAAZ                (0x0020)       /* Comparator Offset calibration annulation */
+
+#define ESIREPEAT_0            (0x0000)       /* These bits configure the duration of this state */
+#define ESIREPEAT_1            (0x0800)       /* ESIREPEATx selects the number of clock cycles for this state. The number of clock cycles = ESIREPEATx + 1 */
+#define ESIREPEAT_2            (0x1000)
+#define ESIREPEAT_3            (0x1800)
+#define ESIREPEAT_4            (0x2000)
+#define ESIREPEAT_5            (0x2800)
+#define ESIREPEAT_6            (0x3000)
+#define ESIREPEAT_7            (0x3800)
+#define ESIREPEAT_8            (0x4000)
+#define ESIREPEAT_9            (0x4800)
+#define ESIREPEAT_10           (0x5000)
+#define ESIREPEAT_11           (0x5800)
+#define ESIREPEAT_12           (0x6000)
+#define ESIREPEAT_13           (0x6800)
+#define ESIREPEAT_14           (0x7000)
+#define ESIREPEAT_15           (0x7800)
+#define ESIREPEAT_16           (0x8000)
+#define ESIREPEAT_17           (0x8800)
+#define ESIREPEAT_18           (0x9000)
+#define ESIREPEAT_19           (0x9800)
+#define ESIREPEAT_20           (0xA000)
+#define ESIREPEAT_21           (0xA800)
+#define ESIREPEAT_22           (0xB000)
+#define ESIREPEAT_23           (0xB800)
+#define ESIREPEAT_24           (0xC000)
+#define ESIREPEAT_25           (0xC800)
+#define ESIREPEAT_26           (0xD000)
+#define ESIREPEAT_27           (0xD800)
+#define ESIREPEAT_28           (0xE000)
+#define ESIREPEAT_29           (0xE800)
+#define ESIREPEAT_30           (0xF000)
+#define ESIREPEAT_31           (0xF800)
+#define ESICH_0                (0x0000)       /* Input channel select: ESICH0 */
+#define ESICH_1                (0x0001)       /* Input channel select: ESICH1 */
+#define ESICH_2                (0x0002)       /* Input channel select: ESICH2 */
+#define ESICH_3                (0x0003)       /* Input channel select: ESICH3 */
+/************************************************************
+* EXTENDED SCAN INTERFACE RAM
+************************************************************/
+#define __MSP430_HAS_ESI_RAM__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_ESI_RAM__ 0x0E00
+#define ESI_RAM_BASE           __MSP430_BASEADDRESS_ESI_RAM__
+
+sfr_b(ESIRAM0);                               /* ESI RAM 0 */
+sfr_b(ESIRAM1);                               /* ESI RAM 1 */
+sfr_b(ESIRAM2);                               /* ESI RAM 2 */
+sfr_b(ESIRAM3);                               /* ESI RAM 3 */
+sfr_b(ESIRAM4);                               /* ESI RAM 4 */
+sfr_b(ESIRAM5);                               /* ESI RAM 5 */
+sfr_b(ESIRAM6);                               /* ESI RAM 6 */
+sfr_b(ESIRAM7);                               /* ESI RAM 7 */
+sfr_b(ESIRAM8);                               /* ESI RAM 8 */
+sfr_b(ESIRAM9);                               /* ESI RAM 9 */
+sfr_b(ESIRAM10);                              /* ESI RAM 10 */
+sfr_b(ESIRAM11);                              /* ESI RAM 11 */
+sfr_b(ESIRAM12);                              /* ESI RAM 12 */
+sfr_b(ESIRAM13);                              /* ESI RAM 13 */
+sfr_b(ESIRAM14);                              /* ESI RAM 14 */
+sfr_b(ESIRAM15);                              /* ESI RAM 15 */
+sfr_b(ESIRAM16);                              /* ESI RAM 16 */
+sfr_b(ESIRAM17);                              /* ESI RAM 17 */
+sfr_b(ESIRAM18);                              /* ESI RAM 18 */
+sfr_b(ESIRAM19);                              /* ESI RAM 19 */
+sfr_b(ESIRAM20);                              /* ESI RAM 20 */
+sfr_b(ESIRAM21);                              /* ESI RAM 21 */
+sfr_b(ESIRAM22);                              /* ESI RAM 22 */
+sfr_b(ESIRAM23);                              /* ESI RAM 23 */
+sfr_b(ESIRAM24);                              /* ESI RAM 24 */
+sfr_b(ESIRAM25);                              /* ESI RAM 25 */
+sfr_b(ESIRAM26);                              /* ESI RAM 26 */
+sfr_b(ESIRAM27);                              /* ESI RAM 27 */
+sfr_b(ESIRAM28);                              /* ESI RAM 28 */
+sfr_b(ESIRAM29);                              /* ESI RAM 29 */
+sfr_b(ESIRAM30);                              /* ESI RAM 30 */
+sfr_b(ESIRAM31);                              /* ESI RAM 31 */
+sfr_b(ESIRAM32);                              /* ESI RAM 32 */
+sfr_b(ESIRAM33);                              /* ESI RAM 33 */
+sfr_b(ESIRAM34);                              /* ESI RAM 34 */
+sfr_b(ESIRAM35);                              /* ESI RAM 35 */
+sfr_b(ESIRAM36);                              /* ESI RAM 36 */
+sfr_b(ESIRAM37);                              /* ESI RAM 37 */
+sfr_b(ESIRAM38);                              /* ESI RAM 38 */
+sfr_b(ESIRAM39);                              /* ESI RAM 39 */
+sfr_b(ESIRAM40);                              /* ESI RAM 40 */
+sfr_b(ESIRAM41);                              /* ESI RAM 41 */
+sfr_b(ESIRAM42);                              /* ESI RAM 42 */
+sfr_b(ESIRAM43);                              /* ESI RAM 43 */
+sfr_b(ESIRAM44);                              /* ESI RAM 44 */
+sfr_b(ESIRAM45);                              /* ESI RAM 45 */
+sfr_b(ESIRAM46);                              /* ESI RAM 46 */
+sfr_b(ESIRAM47);                              /* ESI RAM 47 */
+sfr_b(ESIRAM48);                              /* ESI RAM 48 */
+sfr_b(ESIRAM49);                              /* ESI RAM 49 */
+sfr_b(ESIRAM50);                              /* ESI RAM 50 */
+sfr_b(ESIRAM51);                              /* ESI RAM 51 */
+sfr_b(ESIRAM52);                              /* ESI RAM 52 */
+sfr_b(ESIRAM53);                              /* ESI RAM 53 */
+sfr_b(ESIRAM54);                              /* ESI RAM 54 */
+sfr_b(ESIRAM55);                              /* ESI RAM 55 */
+sfr_b(ESIRAM56);                              /* ESI RAM 56 */
+sfr_b(ESIRAM57);                              /* ESI RAM 57 */
+sfr_b(ESIRAM58);                              /* ESI RAM 58 */
+sfr_b(ESIRAM59);                              /* ESI RAM 59 */
+sfr_b(ESIRAM60);                              /* ESI RAM 60 */
+sfr_b(ESIRAM61);                              /* ESI RAM 61 */
+sfr_b(ESIRAM62);                              /* ESI RAM 62 */
+sfr_b(ESIRAM63);                              /* ESI RAM 63 */
+sfr_b(ESIRAM64);                              /* ESI RAM 64 */
+sfr_b(ESIRAM65);                              /* ESI RAM 65 */
+sfr_b(ESIRAM66);                              /* ESI RAM 66 */
+sfr_b(ESIRAM67);                              /* ESI RAM 67 */
+sfr_b(ESIRAM68);                              /* ESI RAM 68 */
+sfr_b(ESIRAM69);                              /* ESI RAM 69 */
+sfr_b(ESIRAM70);                              /* ESI RAM 70 */
+sfr_b(ESIRAM71);                              /* ESI RAM 71 */
+sfr_b(ESIRAM72);                              /* ESI RAM 72 */
+sfr_b(ESIRAM73);                              /* ESI RAM 73 */
+sfr_b(ESIRAM74);                              /* ESI RAM 74 */
+sfr_b(ESIRAM75);                              /* ESI RAM 75 */
+sfr_b(ESIRAM76);                              /* ESI RAM 76 */
+sfr_b(ESIRAM77);                              /* ESI RAM 77 */
+sfr_b(ESIRAM78);                              /* ESI RAM 78 */
+sfr_b(ESIRAM79);                              /* ESI RAM 79 */
+sfr_b(ESIRAM80);                              /* ESI RAM 80 */
+sfr_b(ESIRAM81);                              /* ESI RAM 81 */
+sfr_b(ESIRAM82);                              /* ESI RAM 82 */
+sfr_b(ESIRAM83);                              /* ESI RAM 83 */
+sfr_b(ESIRAM84);                              /* ESI RAM 84 */
+sfr_b(ESIRAM85);                              /* ESI RAM 85 */
+sfr_b(ESIRAM86);                              /* ESI RAM 86 */
+sfr_b(ESIRAM87);                              /* ESI RAM 87 */
+sfr_b(ESIRAM88);                              /* ESI RAM 88 */
+sfr_b(ESIRAM89);                              /* ESI RAM 89 */
+sfr_b(ESIRAM90);                              /* ESI RAM 90 */
+sfr_b(ESIRAM91);                              /* ESI RAM 91 */
+sfr_b(ESIRAM92);                              /* ESI RAM 92 */
+sfr_b(ESIRAM93);                              /* ESI RAM 93 */
+sfr_b(ESIRAM94);                              /* ESI RAM 94 */
+sfr_b(ESIRAM95);                              /* ESI RAM 95 */
+sfr_b(ESIRAM96);                              /* ESI RAM 96 */
+sfr_b(ESIRAM97);                              /* ESI RAM 97 */
+sfr_b(ESIRAM98);                              /* ESI RAM 98 */
+sfr_b(ESIRAM99);                              /* ESI RAM 99 */
+sfr_b(ESIRAM100);                             /* ESI RAM 100 */
+sfr_b(ESIRAM101);                             /* ESI RAM 101 */
+sfr_b(ESIRAM102);                             /* ESI RAM 102 */
+sfr_b(ESIRAM103);                             /* ESI RAM 103 */
+sfr_b(ESIRAM104);                             /* ESI RAM 104 */
+sfr_b(ESIRAM105);                             /* ESI RAM 105 */
+sfr_b(ESIRAM106);                             /* ESI RAM 106 */
+sfr_b(ESIRAM107);                             /* ESI RAM 107 */
+sfr_b(ESIRAM108);                             /* ESI RAM 108 */
+sfr_b(ESIRAM109);                             /* ESI RAM 109 */
+sfr_b(ESIRAM110);                             /* ESI RAM 110 */
+sfr_b(ESIRAM111);                             /* ESI RAM 111 */
+sfr_b(ESIRAM112);                             /* ESI RAM 112 */
+sfr_b(ESIRAM113);                             /* ESI RAM 113 */
+sfr_b(ESIRAM114);                             /* ESI RAM 114 */
+sfr_b(ESIRAM115);                             /* ESI RAM 115 */
+sfr_b(ESIRAM116);                             /* ESI RAM 116 */
+sfr_b(ESIRAM117);                             /* ESI RAM 117 */
+sfr_b(ESIRAM118);                             /* ESI RAM 118 */
+sfr_b(ESIRAM119);                             /* ESI RAM 119 */
+sfr_b(ESIRAM120);                             /* ESI RAM 120 */
+sfr_b(ESIRAM121);                             /* ESI RAM 121 */
+sfr_b(ESIRAM122);                             /* ESI RAM 122 */
+sfr_b(ESIRAM123);                             /* ESI RAM 123 */
+sfr_b(ESIRAM124);                             /* ESI RAM 124 */
+sfr_b(ESIRAM125);                             /* ESI RAM 125 */
+sfr_b(ESIRAM126);                             /* ESI RAM 126 */
+sfr_b(ESIRAM127);                             /* ESI RAM 127 */
+/*************************************************************
+* FRAM Memory
+*************************************************************/
+#define __MSP430_HAS_FRAM__                   /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_FRAM__ 0x0140
+#define FRAM_BASE              __MSP430_BASEADDRESS_FRAM__
+#define __MSP430_HAS_GC__                     /* Definition to show that Module is available */
+
+sfr_w(FRCTL0);                                /* FRAM Controller Control 0 */
+sfr_b(FRCTL0_L);                              /* FRAM Controller Control 0 */
+sfr_b(FRCTL0_H);                              /* FRAM Controller Control 0 */
+sfr_w(GCCTL0);                                /* General Control 0 */
+sfr_b(GCCTL0_L);                              /* General Control 0 */
+sfr_b(GCCTL0_H);                              /* General Control 0 */
+sfr_w(GCCTL1);                                /* General Control 1 */
+sfr_b(GCCTL1_L);                              /* General Control 1 */
+sfr_b(GCCTL1_H);                              /* General Control 1 */
+
+#define FRCTLPW                (0xA500)       /* FRAM password for write */
+#define FRPW                   (0x9600)       /* FRAM password returned by read */
+#define FWPW                   (0xA500)       /* FRAM password for write */
+#define FXPW                   (0x3300)       /* for use with XOR instruction */
+
+/* FRCTL0 Control Bits */
+//#define RESERVED            (0x0001)  /* RESERVED */
+//#define RESERVED            (0x0002)  /* RESERVED */
+//#define RESERVED            (0x0004)  /* RESERVED */
+#define NWAITS0                (0x0010)       /* FRAM Wait state control Bit: 0 */
+#define NWAITS1                (0x0020)       /* FRAM Wait state control Bit: 1 */
+#define NWAITS2                (0x0040)       /* FRAM Wait state control Bit: 2 */
+//#define RESERVED            (0x0080)  /* RESERVED */
+
+/* FRCTL0 Control Bits */
+//#define RESERVED            (0x0001)  /* RESERVED */
+//#define RESERVED            (0x0002)  /* RESERVED */
+//#define RESERVED            (0x0004)  /* RESERVED */
+#define NWAITS0_L              (0x0010)       /* FRAM Wait state control Bit: 0 */
+#define NWAITS1_L              (0x0020)       /* FRAM Wait state control Bit: 1 */
+#define NWAITS2_L              (0x0040)       /* FRAM Wait state control Bit: 2 */
+//#define RESERVED            (0x0080)  /* RESERVED */
+
+#define NWAITS_0               (0x0000)       /* FRAM Wait state control: 0 */
+#define NWAITS_1               (0x0010)       /* FRAM Wait state control: 1 */
+#define NWAITS_2               (0x0020)       /* FRAM Wait state control: 2 */
+#define NWAITS_3               (0x0030)       /* FRAM Wait state control: 3 */
+#define NWAITS_4               (0x0040)       /* FRAM Wait state control: 4 */
+#define NWAITS_5               (0x0050)       /* FRAM Wait state control: 5 */
+#define NWAITS_6               (0x0060)       /* FRAM Wait state control: 6 */
+#define NWAITS_7               (0x0070)       /* FRAM Wait state control: 7 */
+
+/* GCCTL0 Control Bits */
+//#define RESERVED            (0x0001)  /* RESERVED */
+#define FRLPMPWR               (0x0002)       /* FRAM Enable FRAM auto power up after LPM */
+#define FRPWR                  (0x0004)       /* FRAM Power Control */
+#define ACCTEIE                (0x0008)       /* RESERVED */
+//#define RESERVED            (0x0010)  /* RESERVED */
+#define CBDIE                  (0x0020)       /* Enable NMI event if correctable bit error detected */
+#define UBDIE                  (0x0040)       /* Enable NMI event if uncorrectable bit error detected */
+#define UBDRSTEN               (0x0080)       /* Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected */
+
+/* GCCTL0 Control Bits */
+//#define RESERVED            (0x0001)  /* RESERVED */
+#define FRLPMPWR_L             (0x0002)       /* FRAM Enable FRAM auto power up after LPM */
+#define FRPWR_L                (0x0004)       /* FRAM Power Control */
+#define ACCTEIE_L              (0x0008)       /* RESERVED */
+//#define RESERVED            (0x0010)  /* RESERVED */
+#define CBDIE_L                (0x0020)       /* Enable NMI event if correctable bit error detected */
+#define UBDIE_L                (0x0040)       /* Enable NMI event if uncorrectable bit error detected */
+#define UBDRSTEN_L             (0x0080)       /* Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected */
+
+/* GCCTL1 Control Bits */
+//#define RESERVED            (0x0001)  /* RESERVED */
+#define CBDIFG                 (0x0002)       /* FRAM correctable bit error flag */
+#define UBDIFG                 (0x0004)       /* FRAM uncorrectable bit error flag */
+#define ACCTEIFG               (0x0008)       /* Access time error flag */
+
+/* GCCTL1 Control Bits */
+//#define RESERVED            (0x0001)  /* RESERVED */
+#define CBDIFG_L               (0x0002)       /* FRAM correctable bit error flag */
+#define UBDIFG_L               (0x0004)       /* FRAM uncorrectable bit error flag */
+#define ACCTEIFG_L             (0x0008)       /* Access time error flag */
+
+/************************************************************
+* LCD_C
+************************************************************/
+#define __MSP430_HAS_LCD_C__                  /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_LCD_C__ 0x0A00
+#define LCD_C_BASE             __MSP430_BASEADDRESS_LCD_C__
+
+sfr_w(LCDCCTL0);                              /* LCD_C Control Register 0 */
+sfr_b(LCDCCTL0_L);                            /* LCD_C Control Register 0 */
+sfr_b(LCDCCTL0_H);                            /* LCD_C Control Register 0 */
+sfr_w(LCDCCTL1);                              /* LCD_C Control Register 1 */
+sfr_b(LCDCCTL1_L);                            /* LCD_C Control Register 1 */
+sfr_b(LCDCCTL1_H);                            /* LCD_C Control Register 1 */
+sfr_w(LCDCBLKCTL);                            /* LCD_C blinking control register */
+sfr_b(LCDCBLKCTL_L);                          /* LCD_C blinking control register */
+sfr_b(LCDCBLKCTL_H);                          /* LCD_C blinking control register */
+sfr_w(LCDCMEMCTL);                            /* LCD_C memory control register */
+sfr_b(LCDCMEMCTL_L);                          /* LCD_C memory control register */
+sfr_b(LCDCMEMCTL_H);                          /* LCD_C memory control register */
+sfr_w(LCDCVCTL);                              /* LCD_C Voltage Control Register */
+sfr_b(LCDCVCTL_L);                            /* LCD_C Voltage Control Register */
+sfr_b(LCDCVCTL_H);                            /* LCD_C Voltage Control Register */
+sfr_w(LCDCPCTL0);                             /* LCD_C Port Control Register 0 */
+sfr_b(LCDCPCTL0_L);                           /* LCD_C Port Control Register 0 */
+sfr_b(LCDCPCTL0_H);                           /* LCD_C Port Control Register 0 */
+sfr_w(LCDCPCTL1);                             /* LCD_C Port Control Register 1 */
+sfr_b(LCDCPCTL1_L);                           /* LCD_C Port Control Register 1 */
+sfr_b(LCDCPCTL1_H);                           /* LCD_C Port Control Register 1 */
+sfr_w(LCDCPCTL2);                             /* LCD_C Port Control Register 2 */
+sfr_b(LCDCPCTL2_L);                           /* LCD_C Port Control Register 2 */
+sfr_b(LCDCPCTL2_H);                           /* LCD_C Port Control Register 2 */
+sfr_w(LCDCCPCTL);                             /* LCD_C Charge Pump Control Register 3 */
+sfr_b(LCDCCPCTL_L);                           /* LCD_C Charge Pump Control Register 3 */
+sfr_b(LCDCCPCTL_H);                           /* LCD_C Charge Pump Control Register 3 */
+sfr_w(LCDCIV);                                /* LCD_C Interrupt Vector Register */
+
+// LCDCCTL0
+#define LCDON                  (0x0001)       /* LCD_C LCD On */
+#define LCDLP                  (0x0002)       /* LCD_C Low Power Waveform */
+#define LCDSON                 (0x0004)       /* LCD_C LCD Segments On */
+#define LCDMX0                 (0x0008)       /* LCD_C Mux Rate Bit: 0 */
+#define LCDMX1                 (0x0010)       /* LCD_C Mux Rate Bit: 1 */
+#define LCDMX2                 (0x0020)       /* LCD_C Mux Rate Bit: 2 */
+//#define RESERVED            (0x0040)  /* LCD_C RESERVED */
+#define LCDSSEL                (0x0080)       /* LCD_C Clock Select */
+#define LCDPRE0                (0x0100)       /* LCD_C LCD frequency pre-scaler Bit: 0 */
+#define LCDPRE1                (0x0200)       /* LCD_C LCD frequency pre-scaler Bit: 1 */
+#define LCDPRE2                (0x0400)       /* LCD_C LCD frequency pre-scaler Bit: 2 */
+#define LCDDIV0                (0x0800)       /* LCD_C LCD frequency divider Bit: 0 */
+#define LCDDIV1                (0x1000)       /* LCD_C LCD frequency divider Bit: 1 */
+#define LCDDIV2                (0x2000)       /* LCD_C LCD frequency divider Bit: 2 */
+#define LCDDIV3                (0x4000)       /* LCD_C LCD frequency divider Bit: 3 */
+#define LCDDIV4                (0x8000)       /* LCD_C LCD frequency divider Bit: 4 */
+
+// LCDCCTL0
+#define LCDON_L                (0x0001)       /* LCD_C LCD On */
+#define LCDLP_L                (0x0002)       /* LCD_C Low Power Waveform */
+#define LCDSON_L               (0x0004)       /* LCD_C LCD Segments On */
+#define LCDMX0_L               (0x0008)       /* LCD_C Mux Rate Bit: 0 */
+#define LCDMX1_L               (0x0010)       /* LCD_C Mux Rate Bit: 1 */
+#define LCDMX2_L               (0x0020)       /* LCD_C Mux Rate Bit: 2 */
+//#define RESERVED            (0x0040)  /* LCD_C RESERVED */
+#define LCDSSEL_L              (0x0080)       /* LCD_C Clock Select */
+
+// LCDCCTL0
+//#define RESERVED            (0x0040)  /* LCD_C RESERVED */
+#define LCDPRE0_H              (0x0001)       /* LCD_C LCD frequency pre-scaler Bit: 0 */
+#define LCDPRE1_H              (0x0002)       /* LCD_C LCD frequency pre-scaler Bit: 1 */
+#define LCDPRE2_H              (0x0004)       /* LCD_C LCD frequency pre-scaler Bit: 2 */
+#define LCDDIV0_H              (0x0008)       /* LCD_C LCD frequency divider Bit: 0 */
+#define LCDDIV1_H              (0x0010)       /* LCD_C LCD frequency divider Bit: 1 */
+#define LCDDIV2_H              (0x0020)       /* LCD_C LCD frequency divider Bit: 2 */
+#define LCDDIV3_H              (0x0040)       /* LCD_C LCD frequency divider Bit: 3 */
+#define LCDDIV4_H              (0x0080)       /* LCD_C LCD frequency divider Bit: 4 */
+
+#define LCDPRE_0               (0x0000)       /* LCD_C LCD frequency pre-scaler: /1 */
+#define LCDPRE_1               (0x0100)       /* LCD_C LCD frequency pre-scaler: /2 */
+#define LCDPRE_2               (0x0200)       /* LCD_C LCD frequency pre-scaler: /4 */
+#define LCDPRE_3               (0x0300)       /* LCD_C LCD frequency pre-scaler: /8 */
+#define LCDPRE_4               (0x0400)       /* LCD_C LCD frequency pre-scaler: /16 */
+#define LCDPRE_5               (0x0500)       /* LCD_C LCD frequency pre-scaler: /32 */
+#define LCDPRE__1              (0x0000)       /* LCD_C LCD frequency pre-scaler: /1 */
+#define LCDPRE__2              (0x0100)       /* LCD_C LCD frequency pre-scaler: /2 */
+#define LCDPRE__4              (0x0200)       /* LCD_C LCD frequency pre-scaler: /4 */
+#define LCDPRE__8              (0x0300)       /* LCD_C LCD frequency pre-scaler: /8 */
+#define LCDPRE__16             (0x0400)       /* LCD_C LCD frequency pre-scaler: /16 */
+#define LCDPRE__32             (0x0500)       /* LCD_C LCD frequency pre-scaler: /32 */
+
+#define LCDDIV_0               (0x0000)       /* LCD_C LCD frequency divider: /1 */
+#define LCDDIV_1               (0x0800)       /* LCD_C LCD frequency divider: /2 */
+#define LCDDIV_2               (0x1000)       /* LCD_C LCD frequency divider: /3 */
+#define LCDDIV_3               (0x1800)       /* LCD_C LCD frequency divider: /4 */
+#define LCDDIV_4               (0x2000)       /* LCD_C LCD frequency divider: /5 */
+#define LCDDIV_5               (0x2800)       /* LCD_C LCD frequency divider: /6 */
+#define LCDDIV_6               (0x3000)       /* LCD_C LCD frequency divider: /7 */
+#define LCDDIV_7               (0x3800)       /* LCD_C LCD frequency divider: /8 */
+#define LCDDIV_8               (0x4000)       /* LCD_C LCD frequency divider: /9 */
+#define LCDDIV_9               (0x4800)       /* LCD_C LCD frequency divider: /10 */
+#define LCDDIV_10              (0x5000)       /* LCD_C LCD frequency divider: /11 */
+#define LCDDIV_11              (0x5800)       /* LCD_C LCD frequency divider: /12 */
+#define LCDDIV_12              (0x6000)       /* LCD_C LCD frequency divider: /13 */
+#define LCDDIV_13              (0x6800)       /* LCD_C LCD frequency divider: /14 */
+#define LCDDIV_14              (0x7000)       /* LCD_C LCD frequency divider: /15 */
+#define LCDDIV_15              (0x7800)       /* LCD_C LCD frequency divider: /16 */
+#define LCDDIV_16              (0x8000)       /* LCD_C LCD frequency divider: /17 */
+#define LCDDIV_17              (0x8800)       /* LCD_C LCD frequency divider: /18 */
+#define LCDDIV_18              (0x9000)       /* LCD_C LCD frequency divider: /19 */
+#define LCDDIV_19              (0x9800)       /* LCD_C LCD frequency divider: /20 */
+#define LCDDIV_20              (0xA000)       /* LCD_C LCD frequency divider: /21 */
+#define LCDDIV_21              (0xA800)       /* LCD_C LCD frequency divider: /22 */
+#define LCDDIV_22              (0xB000)       /* LCD_C LCD frequency divider: /23 */
+#define LCDDIV_23              (0xB800)       /* LCD_C LCD frequency divider: /24 */
+#define LCDDIV_24              (0xC000)       /* LCD_C LCD frequency divider: /25 */
+#define LCDDIV_25              (0xC800)       /* LCD_C LCD frequency divider: /26 */
+#define LCDDIV_26              (0xD000)       /* LCD_C LCD frequency divider: /27 */
+#define LCDDIV_27              (0xD800)       /* LCD_C LCD frequency divider: /28 */
+#define LCDDIV_28              (0xE000)       /* LCD_C LCD frequency divider: /29 */
+#define LCDDIV_29              (0xE800)       /* LCD_C LCD frequency divider: /30 */
+#define LCDDIV_30              (0xF000)       /* LCD_C LCD frequency divider: /31 */
+#define LCDDIV_31              (0xF800)       /* LCD_C LCD frequency divider: /32 */
+#define LCDDIV__1              (0x0000)       /* LCD_C LCD frequency divider: /1 */
+#define LCDDIV__2              (0x0800)       /* LCD_C LCD frequency divider: /2 */
+#define LCDDIV__3              (0x1000)       /* LCD_C LCD frequency divider: /3 */
+#define LCDDIV__4              (0x1800)       /* LCD_C LCD frequency divider: /4 */
+#define LCDDIV__5              (0x2000)       /* LCD_C LCD frequency divider: /5 */
+#define LCDDIV__6              (0x2800)       /* LCD_C LCD frequency divider: /6 */
+#define LCDDIV__7              (0x3000)       /* LCD_C LCD frequency divider: /7 */
+#define LCDDIV__8              (0x3800)       /* LCD_C LCD frequency divider: /8 */
+#define LCDDIV__9              (0x4000)       /* LCD_C LCD frequency divider: /9 */
+#define LCDDIV__10             (0x4800)       /* LCD_C LCD frequency divider: /10 */
+#define LCDDIV__11             (0x5000)       /* LCD_C LCD frequency divider: /11 */
+#define LCDDIV__12             (0x5800)       /* LCD_C LCD frequency divider: /12 */
+#define LCDDIV__13             (0x6000)       /* LCD_C LCD frequency divider: /13 */
+#define LCDDIV__14             (0x6800)       /* LCD_C LCD frequency divider: /14 */
+#define LCDDIV__15             (0x7000)       /* LCD_C LCD frequency divider: /15 */
+#define LCDDIV__16             (0x7800)       /* LCD_C LCD frequency divider: /16 */
+#define LCDDIV__17             (0x8000)       /* LCD_C LCD frequency divider: /17 */
+#define LCDDIV__18             (0x8800)       /* LCD_C LCD frequency divider: /18 */
+#define LCDDIV__19             (0x9000)       /* LCD_C LCD frequency divider: /19 */
+#define LCDDIV__20             (0x9800)       /* LCD_C LCD frequency divider: /20 */
+#define LCDDIV__21             (0xA000)       /* LCD_C LCD frequency divider: /21 */
+#define LCDDIV__22             (0xA800)       /* LCD_C LCD frequency divider: /22 */
+#define LCDDIV__23             (0xB000)       /* LCD_C LCD frequency divider: /23 */
+#define LCDDIV__24             (0xB800)       /* LCD_C LCD frequency divider: /24 */
+#define LCDDIV__25             (0xC000)       /* LCD_C LCD frequency divider: /25 */
+#define LCDDIV__26             (0xC800)       /* LCD_C LCD frequency divider: /26 */
+#define LCDDIV__27             (0xD000)       /* LCD_C LCD frequency divider: /27 */
+#define LCDDIV__28             (0xD800)       /* LCD_C LCD frequency divider: /28 */
+#define LCDDIV__29             (0xE000)       /* LCD_C LCD frequency divider: /29 */
+#define LCDDIV__30             (0xE800)       /* LCD_C LCD frequency divider: /30 */
+#define LCDDIV__31             (0xF000)       /* LCD_C LCD frequency divider: /31 */
+#define LCDDIV__32             (0xF800)       /* LCD_C LCD frequency divider: /32 */
+
+/* Display modes coded with Bits 2-4 */
+#define LCDSTATIC              (LCDSON)
+#define LCD2MUX                (LCDMX0+LCDSON)
+#define LCD3MUX                (LCDMX1+LCDSON)
+#define LCD4MUX                (LCDMX1+LCDMX0+LCDSON)
+#define LCD5MUX                (LCDMX2+LCDSON)
+#define LCD6MUX                (LCDMX2+LCDMX0+LCDSON)
+#define LCD7MUX                (LCDMX2+LCDMX1+LCDSON)
+#define LCD8MUX                (LCDMX2+LCDMX1+LCDMX0+LCDSON)
+
+// LCDCCTL1
+#define LCDFRMIFG              (0x0001)       /* LCD_C LCD frame interrupt flag */
+#define LCDBLKOFFIFG           (0x0002)       /* LCD_C LCD blinking off interrupt flag, */
+#define LCDBLKONIFG            (0x0004)       /* LCD_C LCD blinking on interrupt flag, */
+#define LCDNOCAPIFG            (0x0008)       /* LCD_C No cpacitance connected interrupt flag */
+#define LCDFRMIE               (0x0100)       /* LCD_C LCD frame interrupt enable */
+#define LCDBLKOFFIE            (0x0200)       /* LCD_C LCD blinking off interrupt flag, */
+#define LCDBLKONIE             (0x0400)       /* LCD_C LCD blinking on interrupt flag, */
+#define LCDNOCAPIE             (0x0800)       /* LCD_C No cpacitance connected interrupt enable */
+
+// LCDCCTL1
+#define LCDFRMIFG_L            (0x0001)       /* LCD_C LCD frame interrupt flag */
+#define LCDBLKOFFIFG_L         (0x0002)       /* LCD_C LCD blinking off interrupt flag, */
+#define LCDBLKONIFG_L          (0x0004)       /* LCD_C LCD blinking on interrupt flag, */
+#define LCDNOCAPIFG_L          (0x0008)       /* LCD_C No cpacitance connected interrupt flag */
+
+// LCDCCTL1
+#define LCDFRMIE_H             (0x0001)       /* LCD_C LCD frame interrupt enable */
+#define LCDBLKOFFIE_H          (0x0002)       /* LCD_C LCD blinking off interrupt flag, */
+#define LCDBLKONIE_H           (0x0004)       /* LCD_C LCD blinking on interrupt flag, */
+#define LCDNOCAPIE_H           (0x0008)       /* LCD_C No cpacitance connected interrupt enable */
+
+// LCDCBLKCTL
+#define LCDBLKMOD0             (0x0001)       /* LCD_C Blinking mode Bit: 0 */
+#define LCDBLKMOD1             (0x0002)       /* LCD_C Blinking mode Bit: 1 */
+#define LCDBLKPRE0             (0x0004)       /* LCD_C Clock pre-scaler for blinking frequency Bit: 0 */
+#define LCDBLKPRE1             (0x0008)       /* LCD_C Clock pre-scaler for blinking frequency Bit: 1 */
+#define LCDBLKPRE2             (0x0010)       /* LCD_C Clock pre-scaler for blinking frequency Bit: 2 */
+#define LCDBLKDIV0             (0x0020)       /* LCD_C Clock divider for blinking frequency Bit: 0 */
+#define LCDBLKDIV1             (0x0040)       /* LCD_C Clock divider for blinking frequency Bit: 1 */
+#define LCDBLKDIV2             (0x0080)       /* LCD_C Clock divider for blinking frequency Bit: 2 */
+
+// LCDCBLKCTL
+#define LCDBLKMOD0_L           (0x0001)       /* LCD_C Blinking mode Bit: 0 */
+#define LCDBLKMOD1_L           (0x0002)       /* LCD_C Blinking mode Bit: 1 */
+#define LCDBLKPRE0_L           (0x0004)       /* LCD_C Clock pre-scaler for blinking frequency Bit: 0 */
+#define LCDBLKPRE1_L           (0x0008)       /* LCD_C Clock pre-scaler for blinking frequency Bit: 1 */
+#define LCDBLKPRE2_L           (0x0010)       /* LCD_C Clock pre-scaler for blinking frequency Bit: 2 */
+#define LCDBLKDIV0_L           (0x0020)       /* LCD_C Clock divider for blinking frequency Bit: 0 */
+#define LCDBLKDIV1_L           (0x0040)       /* LCD_C Clock divider for blinking frequency Bit: 1 */
+#define LCDBLKDIV2_L           (0x0080)       /* LCD_C Clock divider for blinking frequency Bit: 2 */
+
+#define LCDBLKMOD_0            (0x0000)       /* LCD_C Blinking mode: Off */
+#define LCDBLKMOD_1            (0x0001)       /* LCD_C Blinking mode: Individual */
+#define LCDBLKMOD_2            (0x0002)       /* LCD_C Blinking mode: All */
+#define LCDBLKMOD_3            (0x0003)       /* LCD_C Blinking mode: Switching */
+
+#define LCDBLKPRE_0            (0x0000)       /* LCD_C Clock pre-scaler for blinking frequency: 0 */
+#define LCDBLKPRE_1            (0x0004)       /* LCD_C Clock pre-scaler for blinking frequency: 1 */
+#define LCDBLKPRE_2            (0x0008)       /* LCD_C Clock pre-scaler for blinking frequency: 2 */
+#define LCDBLKPRE_3            (0x000C)       /* LCD_C Clock pre-scaler for blinking frequency: 3 */
+#define LCDBLKPRE_4            (0x0010)       /* LCD_C Clock pre-scaler for blinking frequency: 4 */
+#define LCDBLKPRE_5            (0x0014)       /* LCD_C Clock pre-scaler for blinking frequency: 5 */
+#define LCDBLKPRE_6            (0x0018)       /* LCD_C Clock pre-scaler for blinking frequency: 6 */
+#define LCDBLKPRE_7            (0x001C)       /* LCD_C Clock pre-scaler for blinking frequency: 7 */
+
+#define LCDBLKPRE__512         (0x0000)       /* LCD_C Clock pre-scaler for blinking frequency: 512   */
+#define LCDBLKPRE__1024        (0x0004)       /* LCD_C Clock pre-scaler for blinking frequency: 1024  */
+#define LCDBLKPRE__2048        (0x0008)       /* LCD_C Clock pre-scaler for blinking frequency: 2048  */
+#define LCDBLKPRE__4096        (0x000C)       /* LCD_C Clock pre-scaler for blinking frequency: 4096  */
+#define LCDBLKPRE__8192        (0x0010)       /* LCD_C Clock pre-scaler for blinking frequency: 8192  */
+#define LCDBLKPRE__16384       (0x0014)       /* LCD_C Clock pre-scaler for blinking frequency: 16384 */
+#define LCDBLKPRE__32768       (0x0018)       /* LCD_C Clock pre-scaler for blinking frequency: 32768 */
+#define LCDBLKPRE__65536       (0x001C)       /* LCD_C Clock pre-scaler for blinking frequency: 65536 */
+
+#define LCDBLKDIV_0            (0x0000)       /* LCD_C Clock divider for blinking frequency: 0 */
+#define LCDBLKDIV_1            (0x0020)       /* LCD_C Clock divider for blinking frequency: 1 */
+#define LCDBLKDIV_2            (0x0040)       /* LCD_C Clock divider for blinking frequency: 2 */
+#define LCDBLKDIV_3            (0x0060)       /* LCD_C Clock divider for blinking frequency: 3 */
+#define LCDBLKDIV_4            (0x0080)       /* LCD_C Clock divider for blinking frequency: 4 */
+#define LCDBLKDIV_5            (0x00A0)       /* LCD_C Clock divider for blinking frequency: 5 */
+#define LCDBLKDIV_6            (0x00C0)       /* LCD_C Clock divider for blinking frequency: 6 */
+#define LCDBLKDIV_7            (0x00E0)       /* LCD_C Clock divider for blinking frequency: 7 */
+
+#define LCDBLKDIV__1           (0x0000)       /* LCD_C Clock divider for blinking frequency: /1 */
+#define LCDBLKDIV__2           (0x0020)       /* LCD_C Clock divider for blinking frequency: /2 */
+#define LCDBLKDIV__3           (0x0040)       /* LCD_C Clock divider for blinking frequency: /3 */
+#define LCDBLKDIV__4           (0x0060)       /* LCD_C Clock divider for blinking frequency: /4 */
+#define LCDBLKDIV__5           (0x0080)       /* LCD_C Clock divider for blinking frequency: /5 */
+#define LCDBLKDIV__6           (0x00A0)       /* LCD_C Clock divider for blinking frequency: /6 */
+#define LCDBLKDIV__7           (0x00C0)       /* LCD_C Clock divider for blinking frequency: /7 */
+#define LCDBLKDIV__8           (0x00E0)       /* LCD_C Clock divider for blinking frequency: /8 */
+
+// LCDCMEMCTL
+#define LCDDISP                (0x0001)       /* LCD_C LCD memory registers for display */
+#define LCDCLRM                (0x0002)       /* LCD_C Clear LCD memory */
+#define LCDCLRBM               (0x0004)       /* LCD_C Clear LCD blinking memory */
+
+// LCDCMEMCTL
+#define LCDDISP_L              (0x0001)       /* LCD_C LCD memory registers for display */
+#define LCDCLRM_L              (0x0002)       /* LCD_C Clear LCD memory */
+#define LCDCLRBM_L             (0x0004)       /* LCD_C Clear LCD blinking memory */
+
+// LCDCVCTL
+#define LCD2B                  (0x0001)       /* Selects 1/2 bias. */
+#define VLCDREF0               (0x0002)       /* Selects reference voltage for regulated charge pump: 0 */
+#define VLCDREF1               (0x0004)       /* Selects reference voltage for regulated charge pump: 1 */
+#define LCDCPEN                (0x0008)       /* LCD Voltage Charge Pump Enable. */
+#define VLCDEXT                (0x0010)       /* Select external source for VLCD. */
+#define LCDEXTBIAS             (0x0020)       /* V2 - V4 voltage select. */
+#define R03EXT                 (0x0040)       /* Selects external connections for LCD mid voltages. */
+#define LCDREXT                (0x0080)       /* Selects external connection for lowest LCD voltage. */
+#define VLCD0                  (0x0200)       /* VLCD select: 0 */
+#define VLCD1                  (0x0400)       /* VLCD select: 1 */
+#define VLCD2                  (0x0800)       /* VLCD select: 2 */
+#define VLCD3                  (0x1000)       /* VLCD select: 3 */
+#define VLCD4                  (0x2000)       /* VLCD select: 4 */
+#define VLCD5                  (0x4000)       /* VLCD select: 5 */
+
+// LCDCVCTL
+#define LCD2B_L                (0x0001)       /* Selects 1/2 bias. */
+#define VLCDREF0_L             (0x0002)       /* Selects reference voltage for regulated charge pump: 0 */
+#define VLCDREF1_L             (0x0004)       /* Selects reference voltage for regulated charge pump: 1 */
+#define LCDCPEN_L              (0x0008)       /* LCD Voltage Charge Pump Enable. */
+#define VLCDEXT_L              (0x0010)       /* Select external source for VLCD. */
+#define LCDEXTBIAS_L           (0x0020)       /* V2 - V4 voltage select. */
+#define R03EXT_L               (0x0040)       /* Selects external connections for LCD mid voltages. */
+#define LCDREXT_L              (0x0080)       /* Selects external connection for lowest LCD voltage. */
+
+// LCDCVCTL
+#define VLCD0_H                (0x0002)       /* VLCD select: 0 */
+#define VLCD1_H                (0x0004)       /* VLCD select: 1 */
+#define VLCD2_H                (0x0008)       /* VLCD select: 2 */
+#define VLCD3_H                (0x0010)       /* VLCD select: 3 */
+#define VLCD4_H                (0x0020)       /* VLCD select: 4 */
+#define VLCD5_H                (0x0040)       /* VLCD select: 5 */
+
+/* Reference voltage source select for the regulated charge pump */
+#define VLCDREF_0              (0x0000)       /* Internal */
+#define VLCDREF_1              (0x0002)       /* External */
+#define VLCDREF_2              (0x0004)       /* Reserved */
+#define VLCDREF_3              (0x0006)       /* Reserved */
+
+/* Charge pump voltage selections */
+#define VLCD_0                 (0x0000)       /* Charge pump disabled */
+#define VLCD_1                 (0x0200)       /* VLCD = 2.60V */
+#define VLCD_2                 (0x0400)       /* VLCD = 2.66V */
+#define VLCD_3                 (0x0600)       /* VLCD = 2.72V */
+#define VLCD_4                 (0x0800)       /* VLCD = 2.78V */
+#define VLCD_5                 (0x0A00)       /* VLCD = 2.84V */
+#define VLCD_6                 (0x0C00)       /* VLCD = 2.90V */
+#define VLCD_7                 (0x0E00)       /* VLCD = 2.96V */
+#define VLCD_8                 (0x1000)       /* VLCD = 3.02V */
+#define VLCD_9                 (0x1200)       /* VLCD = 3.08V */
+#define VLCD_10                (0x1400)       /* VLCD = 3.14V */
+#define VLCD_11                (0x1600)       /* VLCD = 3.20V */
+#define VLCD_12                (0x1800)       /* VLCD = 3.26V */
+#define VLCD_13                (0x1A00)       /* VLCD = 3.32V */
+#define VLCD_14                (0x1C00)       /* VLCD = 3.38V */
+#define VLCD_15                (0x1E00)       /* VLCD = 3.44V */
+
+#define VLCD_DISABLED          (0x0000)       /* Charge pump disabled */
+#define VLCD_2_60              (0x0200)       /* VLCD = 2.60V */
+#define VLCD_2_66              (0x0400)       /* VLCD = 2.66V */
+#define VLCD_2_72              (0x0600)       /* VLCD = 2.72V */
+#define VLCD_2_78              (0x0800)       /* VLCD = 2.78V */
+#define VLCD_2_84              (0x0A00)       /* VLCD = 2.84V */
+#define VLCD_2_90              (0x0C00)       /* VLCD = 2.90V */
+#define VLCD_2_96              (0x0E00)       /* VLCD = 2.96V */
+#define VLCD_3_02              (0x1000)       /* VLCD = 3.02V */
+#define VLCD_3_08              (0x1200)       /* VLCD = 3.08V */
+#define VLCD_3_14              (0x1400)       /* VLCD = 3.14V */
+#define VLCD_3_20              (0x1600)       /* VLCD = 3.20V */
+#define VLCD_3_26              (0x1800)       /* VLCD = 3.26V */
+#define VLCD_3_32              (0x1A00)       /* VLCD = 3.32V */
+#define VLCD_3_38              (0x1C00)       /* VLCD = 3.38V */
+#define VLCD_3_44              (0x1E00)       /* VLCD = 3.44V */
+
+// LCDCPCTL0
+#define LCDS0                  (0x0001)       /* LCD Segment  0 enable. */
+#define LCDS1                  (0x0002)       /* LCD Segment  1 enable. */
+#define LCDS2                  (0x0004)       /* LCD Segment  2 enable. */
+#define LCDS3                  (0x0008)       /* LCD Segment  3 enable. */
+#define LCDS4                  (0x0010)       /* LCD Segment  4 enable. */
+#define LCDS5                  (0x0020)       /* LCD Segment  5 enable. */
+#define LCDS6                  (0x0040)       /* LCD Segment  6 enable. */
+#define LCDS7                  (0x0080)       /* LCD Segment  7 enable. */
+#define LCDS8                  (0x0100)       /* LCD Segment  8 enable. */
+#define LCDS9                  (0x0200)       /* LCD Segment  9 enable. */
+#define LCDS10                 (0x0400)       /* LCD Segment 10 enable. */
+#define LCDS11                 (0x0800)       /* LCD Segment 11 enable. */
+#define LCDS12                 (0x1000)       /* LCD Segment 12 enable. */
+#define LCDS13                 (0x2000)       /* LCD Segment 13 enable. */
+#define LCDS14                 (0x4000)       /* LCD Segment 14 enable. */
+#define LCDS15                 (0x8000)       /* LCD Segment 15 enable. */
+
+// LCDCPCTL0
+#define LCDS0_L                (0x0001)       /* LCD Segment  0 enable. */
+#define LCDS1_L                (0x0002)       /* LCD Segment  1 enable. */
+#define LCDS2_L                (0x0004)       /* LCD Segment  2 enable. */
+#define LCDS3_L                (0x0008)       /* LCD Segment  3 enable. */
+#define LCDS4_L                (0x0010)       /* LCD Segment  4 enable. */
+#define LCDS5_L                (0x0020)       /* LCD Segment  5 enable. */
+#define LCDS6_L                (0x0040)       /* LCD Segment  6 enable. */
+#define LCDS7_L                (0x0080)       /* LCD Segment  7 enable. */
+
+// LCDCPCTL0
+#define LCDS8_H                (0x0001)       /* LCD Segment  8 enable. */
+#define LCDS9_H                (0x0002)       /* LCD Segment  9 enable. */
+#define LCDS10_H               (0x0004)       /* LCD Segment 10 enable. */
+#define LCDS11_H               (0x0008)       /* LCD Segment 11 enable. */
+#define LCDS12_H               (0x0010)       /* LCD Segment 12 enable. */
+#define LCDS13_H               (0x0020)       /* LCD Segment 13 enable. */
+#define LCDS14_H               (0x0040)       /* LCD Segment 14 enable. */
+#define LCDS15_H               (0x0080)       /* LCD Segment 15 enable. */
+
+// LCDCPCTL1
+#define LCDS16                 (0x0001)       /* LCD Segment 16 enable. */
+#define LCDS17                 (0x0002)       /* LCD Segment 17 enable. */
+#define LCDS18                 (0x0004)       /* LCD Segment 18 enable. */
+#define LCDS19                 (0x0008)       /* LCD Segment 19 enable. */
+#define LCDS20                 (0x0010)       /* LCD Segment 20 enable. */
+#define LCDS21                 (0x0020)       /* LCD Segment 21 enable. */
+#define LCDS22                 (0x0040)       /* LCD Segment 22 enable. */
+#define LCDS23                 (0x0080)       /* LCD Segment 23 enable. */
+#define LCDS24                 (0x0100)       /* LCD Segment 24 enable. */
+#define LCDS25                 (0x0200)       /* LCD Segment 25 enable. */
+#define LCDS26                 (0x0400)       /* LCD Segment 26 enable. */
+#define LCDS27                 (0x0800)       /* LCD Segment 27 enable. */
+#define LCDS28                 (0x1000)       /* LCD Segment 28 enable. */
+#define LCDS29                 (0x2000)       /* LCD Segment 29 enable. */
+#define LCDS30                 (0x4000)       /* LCD Segment 30 enable. */
+#define LCDS31                 (0x8000)       /* LCD Segment 31 enable. */
+
+// LCDCPCTL1
+#define LCDS16_L               (0x0001)       /* LCD Segment 16 enable. */
+#define LCDS17_L               (0x0002)       /* LCD Segment 17 enable. */
+#define LCDS18_L               (0x0004)       /* LCD Segment 18 enable. */
+#define LCDS19_L               (0x0008)       /* LCD Segment 19 enable. */
+#define LCDS20_L               (0x0010)       /* LCD Segment 20 enable. */
+#define LCDS21_L               (0x0020)       /* LCD Segment 21 enable. */
+#define LCDS22_L               (0x0040)       /* LCD Segment 22 enable. */
+#define LCDS23_L               (0x0080)       /* LCD Segment 23 enable. */
+
+// LCDCPCTL1
+#define LCDS24_H               (0x0001)       /* LCD Segment 24 enable. */
+#define LCDS25_H               (0x0002)       /* LCD Segment 25 enable. */
+#define LCDS26_H               (0x0004)       /* LCD Segment 26 enable. */
+#define LCDS27_H               (0x0008)       /* LCD Segment 27 enable. */
+#define LCDS28_H               (0x0010)       /* LCD Segment 28 enable. */
+#define LCDS29_H               (0x0020)       /* LCD Segment 29 enable. */
+#define LCDS30_H               (0x0040)       /* LCD Segment 30 enable. */
+#define LCDS31_H               (0x0080)       /* LCD Segment 31 enable. */
+
+// LCDCPCTL2
+#define LCDS32                 (0x0001)       /* LCD Segment 32 enable. */
+#define LCDS33                 (0x0002)       /* LCD Segment 33 enable. */
+#define LCDS34                 (0x0004)       /* LCD Segment 34 enable. */
+#define LCDS35                 (0x0008)       /* LCD Segment 35 enable. */
+#define LCDS36                 (0x0010)       /* LCD Segment 36 enable. */
+#define LCDS37                 (0x0020)       /* LCD Segment 37 enable. */
+#define LCDS38                 (0x0040)       /* LCD Segment 38 enable. */
+#define LCDS39                 (0x0080)       /* LCD Segment 39 enable. */
+#define LCDS40                 (0x0100)       /* LCD Segment 40 enable. */
+#define LCDS41                 (0x0200)       /* LCD Segment 41 enable. */
+#define LCDS42                 (0x0400)       /* LCD Segment 42 enable. */
+#define LCDS43                 (0x0800)       /* LCD Segment 43 enable. */
+#define LCDS44                 (0x1000)       /* LCD Segment 44 enable. */
+#define LCDS45                 (0x2000)       /* LCD Segment 45 enable. */
+#define LCDS46                 (0x4000)       /* LCD Segment 46 enable. */
+#define LCDS47                 (0x8000)       /* LCD Segment 47 enable. */
+
+// LCDCPCTL2
+#define LCDS32_L               (0x0001)       /* LCD Segment 32 enable. */
+#define LCDS33_L               (0x0002)       /* LCD Segment 33 enable. */
+#define LCDS34_L               (0x0004)       /* LCD Segment 34 enable. */
+#define LCDS35_L               (0x0008)       /* LCD Segment 35 enable. */
+#define LCDS36_L               (0x0010)       /* LCD Segment 36 enable. */
+#define LCDS37_L               (0x0020)       /* LCD Segment 37 enable. */
+#define LCDS38_L               (0x0040)       /* LCD Segment 38 enable. */
+#define LCDS39_L               (0x0080)       /* LCD Segment 39 enable. */
+
+// LCDCPCTL2
+#define LCDS40_H               (0x0001)       /* LCD Segment 40 enable. */
+#define LCDS41_H               (0x0002)       /* LCD Segment 41 enable. */
+#define LCDS42_H               (0x0004)       /* LCD Segment 42 enable. */
+#define LCDS43_H               (0x0008)       /* LCD Segment 43 enable. */
+#define LCDS44_H               (0x0010)       /* LCD Segment 44 enable. */
+#define LCDS45_H               (0x0020)       /* LCD Segment 45 enable. */
+#define LCDS46_H               (0x0040)       /* LCD Segment 46 enable. */
+#define LCDS47_H               (0x0080)       /* LCD Segment 47 enable. */
+
+// LCDCCPCTL
+#define LCDCPDIS0              (0x0001)       /* LCD charge pump disable */
+#define LCDCPDIS1              (0x0002)       /* LCD charge pump disable */
+#define LCDCPDIS2              (0x0004)       /* LCD charge pump disable */
+#define LCDCPDIS3              (0x0008)       /* LCD charge pump disable */
+#define LCDCPDIS4              (0x0010)       /* LCD charge pump disable */
+#define LCDCPDIS5              (0x0020)       /* LCD charge pump disable */
+#define LCDCPDIS6              (0x0040)       /* LCD charge pump disable */
+#define LCDCPDIS7              (0x0080)       /* LCD charge pump disable */
+#define LCDCPCLKSYNC           (0x8000)       /* LCD charge pump clock synchronization */
+
+// LCDCCPCTL
+#define LCDCPDIS0_L            (0x0001)       /* LCD charge pump disable */
+#define LCDCPDIS1_L            (0x0002)       /* LCD charge pump disable */
+#define LCDCPDIS2_L            (0x0004)       /* LCD charge pump disable */
+#define LCDCPDIS3_L            (0x0008)       /* LCD charge pump disable */
+#define LCDCPDIS4_L            (0x0010)       /* LCD charge pump disable */
+#define LCDCPDIS5_L            (0x0020)       /* LCD charge pump disable */
+#define LCDCPDIS6_L            (0x0040)       /* LCD charge pump disable */
+#define LCDCPDIS7_L            (0x0080)       /* LCD charge pump disable */
+
+// LCDCCPCTL
+#define LCDCPCLKSYNC_H         (0x0080)       /* LCD charge pump clock synchronization */
+
+sfr_b(LCDM1);                                 /* LCD Memory 1 */
+#define LCDMEM_                LCDM1          /* LCD Memory */
+#ifndef __STDC__
+#define LCDMEM                 LCDM1          /* LCD Memory (for assembler) */
+#else
+#define LCDMEM                 ((volatile char*)       &LCDM1) /* LCD Memory (for C) */
+#endif
+sfr_b(LCDM2);                                 /* LCD Memory 2 */
+sfr_b(LCDM3);                                 /* LCD Memory 3 */
+sfr_b(LCDM4);                                 /* LCD Memory 4 */
+sfr_b(LCDM5);                                 /* LCD Memory 5 */
+sfr_b(LCDM6);                                 /* LCD Memory 6 */
+sfr_b(LCDM7);                                 /* LCD Memory 7 */
+sfr_b(LCDM8);                                 /* LCD Memory 8 */
+sfr_b(LCDM9);                                 /* LCD Memory 9 */
+sfr_b(LCDM10);                                /* LCD Memory 10 */
+sfr_b(LCDM11);                                /* LCD Memory 11 */
+sfr_b(LCDM12);                                /* LCD Memory 12 */
+sfr_b(LCDM13);                                /* LCD Memory 13 */
+sfr_b(LCDM14);                                /* LCD Memory 14 */
+sfr_b(LCDM15);                                /* LCD Memory 15 */
+sfr_b(LCDM16);                                /* LCD Memory 16 */
+sfr_b(LCDM17);                                /* LCD Memory 17 */
+sfr_b(LCDM18);                                /* LCD Memory 18 */
+sfr_b(LCDM19);                                /* LCD Memory 19 */
+sfr_b(LCDM20);                                /* LCD Memory 20 */
+sfr_b(LCDM21);                                /* LCD Memory 21 */
+sfr_b(LCDM22);                                /* LCD Memory 22 */
+sfr_b(LCDM23);                                /* LCD Memory 23 */
+sfr_b(LCDM24);                                /* LCD Memory 24 */
+sfr_b(LCDM25);                                /* LCD Memory 25 */
+sfr_b(LCDM26);                                /* LCD Memory 26 */
+sfr_b(LCDM27);                                /* LCD Memory 27 */
+sfr_b(LCDM28);                                /* LCD Memory 28 */
+sfr_b(LCDM29);                                /* LCD Memory 29 */
+sfr_b(LCDM30);                                /* LCD Memory 30 */
+sfr_b(LCDM31);                                /* LCD Memory 31 */
+sfr_b(LCDM32);                                /* LCD Memory 32 */
+sfr_b(LCDM33);                                /* LCD Memory 33 */
+sfr_b(LCDM34);                                /* LCD Memory 34 */
+sfr_b(LCDM35);                                /* LCD Memory 35 */
+sfr_b(LCDM36);                                /* LCD Memory 36 */
+sfr_b(LCDM37);                                /* LCD Memory 37 */
+sfr_b(LCDM38);                                /* LCD Memory 38 */
+sfr_b(LCDM39);                                /* LCD Memory 39 */
+sfr_b(LCDM40);                                /* LCD Memory 40 */
+sfr_b(LCDM41);                                /* LCD Memory 41 */
+sfr_b(LCDM42);                                /* LCD Memory 42 */
+sfr_b(LCDM43);                                /* LCD Memory 43 */
+
+sfr_b(LCDBM1);                                /* LCD Blinking Memory 1 */
+#define LCDBMEM_               LCDBM1         /* LCD Blinking Memory */
+#ifndef __STDC__
+#define LCDBMEM                (LCDBM1)       /* LCD Blinking Memory (for assembler) */
+#else
+#define LCDBMEM                ((volatile char*)       &LCDBM1) /* LCD Blinking Memory (for C) */
+#endif
+sfr_b(LCDBM2);                                /* LCD Blinking Memory 2 */
+sfr_b(LCDBM3);                                /* LCD Blinking Memory 3 */
+sfr_b(LCDBM4);                                /* LCD Blinking Memory 4 */
+sfr_b(LCDBM5);                                /* LCD Blinking Memory 5 */
+sfr_b(LCDBM6);                                /* LCD Blinking Memory 6 */
+sfr_b(LCDBM7);                                /* LCD Blinking Memory 7 */
+sfr_b(LCDBM8);                                /* LCD Blinking Memory 8 */
+sfr_b(LCDBM9);                                /* LCD Blinking Memory 9 */
+sfr_b(LCDBM10);                               /* LCD Blinking Memory 10 */
+sfr_b(LCDBM11);                               /* LCD Blinking Memory 11 */
+sfr_b(LCDBM12);                               /* LCD Blinking Memory 12 */
+sfr_b(LCDBM13);                               /* LCD Blinking Memory 13 */
+sfr_b(LCDBM14);                               /* LCD Blinking Memory 14 */
+sfr_b(LCDBM15);                               /* LCD Blinking Memory 15 */
+sfr_b(LCDBM16);                               /* LCD Blinking Memory 16 */
+sfr_b(LCDBM17);                               /* LCD Blinking Memory 17 */
+sfr_b(LCDBM18);                               /* LCD Blinking Memory 18 */
+sfr_b(LCDBM19);                               /* LCD Blinking Memory 19 */
+sfr_b(LCDBM20);                               /* LCD Blinking Memory 20 */
+sfr_b(LCDBM21);                               /* LCD Blinking Memory 21 */
+sfr_b(LCDBM22);                               /* LCD Blinking Memory 22 */
+
+/* LCDCIV Definitions */
+#define LCDCIV_NONE            (0x0000)       /* No Interrupt pending */
+#define LCDCIV_LCDNOCAPIFG     (0x0002)       /* No capacitor connected */
+#define LCDCIV_LCDCLKOFFIFG    (0x0004)       /* Blink, segments off */
+#define LCDCIV_LCDCLKONIFG     (0x0006)       /* Blink, segments on */
+#define LCDCIV_LCDFRMIFG       (0x0008)       /* Frame interrupt */
+
+/************************************************************
+* Memory Protection Unit
+************************************************************/
+#define __MSP430_HAS_MPU__                    /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_MPU__ 0x05A0
+#define MPU_BASE               __MSP430_BASEADDRESS_MPU__
+
+sfr_w(MPUCTL0);                               /* MPU Control Register 0 */
+sfr_b(MPUCTL0_L);                             /* MPU Control Register 0 */
+sfr_b(MPUCTL0_H);                             /* MPU Control Register 0 */
+sfr_w(MPUCTL1);                               /* MPU Control Register 1 */
+sfr_b(MPUCTL1_L);                             /* MPU Control Register 1 */
+sfr_b(MPUCTL1_H);                             /* MPU Control Register 1 */
+sfr_w(MPUSEGB2);                              /* MPU Segmentation Border 2 Register */
+sfr_b(MPUSEGB2_L);                            /* MPU Segmentation Border 2 Register */
+sfr_b(MPUSEGB2_H);                            /* MPU Segmentation Border 2 Register */
+sfr_w(MPUSEGB1);                              /* MPU Segmentation Border 1 Register */
+sfr_b(MPUSEGB1_L);                            /* MPU Segmentation Border 1 Register */
+sfr_b(MPUSEGB1_H);                            /* MPU Segmentation Border 1 Register */
+sfr_w(MPUSAM);                                /* MPU Access Management Register */
+sfr_b(MPUSAM_L);                              /* MPU Access Management Register */
+sfr_b(MPUSAM_H);                              /* MPU Access Management Register */
+sfr_w(MPUIPC0);                               /* MPU IP Control 0 Register */
+sfr_b(MPUIPC0_L);                             /* MPU IP Control 0 Register */
+sfr_b(MPUIPC0_H);                             /* MPU IP Control 0 Register */
+sfr_w(MPUIPSEGB2);                            /* MPU IP Segment Border 2 Register */
+sfr_b(MPUIPSEGB2_L);                          /* MPU IP Segment Border 2 Register */
+sfr_b(MPUIPSEGB2_H);                          /* MPU IP Segment Border 2 Register */
+sfr_w(MPUIPSEGB1);                            /* MPU IP Segment Border 1 Register */
+sfr_b(MPUIPSEGB1_L);                          /* MPU IP Segment Border 1 Register */
+sfr_b(MPUIPSEGB1_H);                          /* MPU IP Segment Border 1 Register */
+
+/* MPUCTL0 Control Bits */
+#define MPUENA                 (0x0001)       /* MPU Enable */
+#define MPULOCK                (0x0002)       /* MPU Lock */
+#define MPUSEGIE               (0x0010)       /* MPU Enable NMI on Segment violation */
+
+/* MPUCTL0 Control Bits */
+#define MPUENA_L               (0x0001)       /* MPU Enable */
+#define MPULOCK_L              (0x0002)       /* MPU Lock */
+#define MPUSEGIE_L             (0x0010)       /* MPU Enable NMI on Segment violation */
+
+#define MPUPW                  (0xA500)       /* MPU Access Password */
+#define MPUPW_H                (0xA5)         /* MPU Access Password */
+
+/* MPUCTL1 Control Bits */
+#define MPUSEG1IFG             (0x0001)       /* MPU Main Memory Segment 1 violation interupt flag */
+#define MPUSEG2IFG             (0x0002)       /* MPU Main Memory Segment 2 violation interupt flag */
+#define MPUSEG3IFG             (0x0004)       /* MPU Main Memory Segment 3 violation interupt flag */
+#define MPUSEGIIFG             (0x0008)       /* MPU Info Memory Segment violation interupt flag */
+#define MPUSEGIPIFG            (0x0010)       /* MPU IP Memory Segment violation interupt flag */
+
+/* MPUCTL1 Control Bits */
+#define MPUSEG1IFG_L           (0x0001)       /* MPU Main Memory Segment 1 violation interupt flag */
+#define MPUSEG2IFG_L           (0x0002)       /* MPU Main Memory Segment 2 violation interupt flag */
+#define MPUSEG3IFG_L           (0x0004)       /* MPU Main Memory Segment 3 violation interupt flag */
+#define MPUSEGIIFG_L           (0x0008)       /* MPU Info Memory Segment violation interupt flag */
+#define MPUSEGIPIFG_L          (0x0010)       /* MPU IP Memory Segment violation interupt flag */
+
+/* MPUSEGB2 Control Bits */
+
+/* MPUSEGB2 Control Bits */
+
+/* MPUSEGB2 Control Bits */
+
+/* MPUSEGB1 Control Bits */
+
+/* MPUSEGB1 Control Bits */
+
+/* MPUSEGB1 Control Bits */
+
+/* MPUSAM Control Bits */
+#define MPUSEG1RE              (0x0001)       /* MPU Main memory Segment 1 Read enable */
+#define MPUSEG1WE              (0x0002)       /* MPU Main memory Segment 1 Write enable */
+#define MPUSEG1XE              (0x0004)       /* MPU Main memory Segment 1 Execute enable */
+#define MPUSEG1VS              (0x0008)       /* MPU Main memory Segment 1 Violation select */
+#define MPUSEG2RE              (0x0010)       /* MPU Main memory Segment 2 Read enable */
+#define MPUSEG2WE              (0x0020)       /* MPU Main memory Segment 2 Write enable */
+#define MPUSEG2XE              (0x0040)       /* MPU Main memory Segment 2 Execute enable */
+#define MPUSEG2VS              (0x0080)       /* MPU Main memory Segment 2 Violation select */
+#define MPUSEG3RE              (0x0100)       /* MPU Main memory Segment 3 Read enable */
+#define MPUSEG3WE              (0x0200)       /* MPU Main memory Segment 3 Write enable */
+#define MPUSEG3XE              (0x0400)       /* MPU Main memory Segment 3 Execute enable */
+#define MPUSEG3VS              (0x0800)       /* MPU Main memory Segment 3 Violation select */
+#define MPUSEGIRE              (0x1000)       /* MPU Info memory Segment Read enable */
+#define MPUSEGIWE              (0x2000)       /* MPU Info memory Segment Write enable */
+#define MPUSEGIXE              (0x4000)       /* MPU Info memory Segment Execute enable */
+#define MPUSEGIVS              (0x8000)       /* MPU Info memory Segment Violation select */
+
+/* MPUSAM Control Bits */
+#define MPUSEG1RE_L            (0x0001)       /* MPU Main memory Segment 1 Read enable */
+#define MPUSEG1WE_L            (0x0002)       /* MPU Main memory Segment 1 Write enable */
+#define MPUSEG1XE_L            (0x0004)       /* MPU Main memory Segment 1 Execute enable */
+#define MPUSEG1VS_L            (0x0008)       /* MPU Main memory Segment 1 Violation select */
+#define MPUSEG2RE_L            (0x0010)       /* MPU Main memory Segment 2 Read enable */
+#define MPUSEG2WE_L            (0x0020)       /* MPU Main memory Segment 2 Write enable */
+#define MPUSEG2XE_L            (0x0040)       /* MPU Main memory Segment 2 Execute enable */
+#define MPUSEG2VS_L            (0x0080)       /* MPU Main memory Segment 2 Violation select */
+
+/* MPUSAM Control Bits */
+#define MPUSEG3RE_H            (0x0001)       /* MPU Main memory Segment 3 Read enable */
+#define MPUSEG3WE_H            (0x0002)       /* MPU Main memory Segment 3 Write enable */
+#define MPUSEG3XE_H            (0x0004)       /* MPU Main memory Segment 3 Execute enable */
+#define MPUSEG3VS_H            (0x0008)       /* MPU Main memory Segment 3 Violation select */
+#define MPUSEGIRE_H            (0x0010)       /* MPU Info memory Segment Read enable */
+#define MPUSEGIWE_H            (0x0020)       /* MPU Info memory Segment Write enable */
+#define MPUSEGIXE_H            (0x0040)       /* MPU Info memory Segment Execute enable */
+#define MPUSEGIVS_H            (0x0080)       /* MPU Info memory Segment Violation select */
+
+/* MPUIPC0 Control Bits */
+#define MPUIPVS                (0x0020)       /* MPU MPU IP protection segment Violation Select */
+#define MPUIPENA               (0x0040)       /* MPU MPU IP Protection Enable */
+#define MPUIPLOCK              (0x0080)       /* MPU IP Protection Lock */
+
+/* MPUIPC0 Control Bits */
+#define MPUIPVS_L              (0x0020)       /* MPU MPU IP protection segment Violation Select */
+#define MPUIPENA_L             (0x0040)       /* MPU MPU IP Protection Enable */
+#define MPUIPLOCK_L            (0x0080)       /* MPU IP Protection Lock */
+
+/* MPUIPSEGB2 Control Bits */
+
+/* MPUIPSEGB2 Control Bits */
+
+/* MPUIPSEGB2 Control Bits */
+
+/* MPUIPSEGB1 Control Bits */
+
+/* MPUIPSEGB1 Control Bits */
+
+/* MPUIPSEGB1 Control Bits */
+
+/************************************************************
+* HARDWARE MULTIPLIER 32Bit
+************************************************************/
+#define __MSP430_HAS_MPY32__                  /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_MPY32__ 0x04C0
+#define MPY32_BASE             __MSP430_BASEADDRESS_MPY32__
+
+sfr_w(MPY);                                   /* Multiply Unsigned/Operand 1 */
+sfr_b(MPY_L);                                 /* Multiply Unsigned/Operand 1 */
+sfr_b(MPY_H);                                 /* Multiply Unsigned/Operand 1 */
+sfr_w(MPYS);                                  /* Multiply Signed/Operand 1 */
+sfr_b(MPYS_L);                                /* Multiply Signed/Operand 1 */
+sfr_b(MPYS_H);                                /* Multiply Signed/Operand 1 */
+sfr_w(MAC);                                   /* Multiply Unsigned and Accumulate/Operand 1 */
+sfr_b(MAC_L);                                 /* Multiply Unsigned and Accumulate/Operand 1 */
+sfr_b(MAC_H);                                 /* Multiply Unsigned and Accumulate/Operand 1 */
+sfr_w(MACS);                                  /* Multiply Signed and Accumulate/Operand 1 */
+sfr_b(MACS_L);                                /* Multiply Signed and Accumulate/Operand 1 */
+sfr_b(MACS_H);                                /* Multiply Signed and Accumulate/Operand 1 */
+sfr_w(OP2);                                   /* Operand 2 */
+sfr_b(OP2_L);                                 /* Operand 2 */
+sfr_b(OP2_H);                                 /* Operand 2 */
+sfr_w(RESLO);                                 /* Result Low Word */
+sfr_b(RESLO_L);                               /* Result Low Word */
+sfr_b(RESLO_H);                               /* Result Low Word */
+sfr_w(RESHI);                                 /* Result High Word */
+sfr_b(RESHI_L);                               /* Result High Word */
+sfr_b(RESHI_H);                               /* Result High Word */
+sfr_w(SUMEXT);                                /* Sum Extend */
+sfr_b(SUMEXT_L);                              /* Sum Extend */
+sfr_b(SUMEXT_H);                              /* Sum Extend */
+
+sfr_w(MPY32L);                                /* 32-bit operand 1 - multiply - low word */
+sfr_b(MPY32L_L);                              /* 32-bit operand 1 - multiply - low word */
+sfr_b(MPY32L_H);                              /* 32-bit operand 1 - multiply - low word */
+sfr_w(MPY32H);                                /* 32-bit operand 1 - multiply - high word */
+sfr_b(MPY32H_L);                              /* 32-bit operand 1 - multiply - high word */
+sfr_b(MPY32H_H);                              /* 32-bit operand 1 - multiply - high word */
+sfr_w(MPYS32L);                               /* 32-bit operand 1 - signed multiply - low word */
+sfr_b(MPYS32L_L);                             /* 32-bit operand 1 - signed multiply - low word */
+sfr_b(MPYS32L_H);                             /* 32-bit operand 1 - signed multiply - low word */
+sfr_w(MPYS32H);                               /* 32-bit operand 1 - signed multiply - high word */
+sfr_b(MPYS32H_L);                             /* 32-bit operand 1 - signed multiply - high word */
+sfr_b(MPYS32H_H);                             /* 32-bit operand 1 - signed multiply - high word */
+sfr_w(MAC32L);                                /* 32-bit operand 1 - multiply accumulate - low word */
+sfr_b(MAC32L_L);                              /* 32-bit operand 1 - multiply accumulate - low word */
+sfr_b(MAC32L_H);                              /* 32-bit operand 1 - multiply accumulate - low word */
+sfr_w(MAC32H);                                /* 32-bit operand 1 - multiply accumulate - high word */
+sfr_b(MAC32H_L);                              /* 32-bit operand 1 - multiply accumulate - high word */
+sfr_b(MAC32H_H);                              /* 32-bit operand 1 - multiply accumulate - high word */
+sfr_w(MACS32L);                               /* 32-bit operand 1 - signed multiply accumulate - low word */
+sfr_b(MACS32L_L);                             /* 32-bit operand 1 - signed multiply accumulate - low word */
+sfr_b(MACS32L_H);                             /* 32-bit operand 1 - signed multiply accumulate - low word */
+sfr_w(MACS32H);                               /* 32-bit operand 1 - signed multiply accumulate - high word */
+sfr_b(MACS32H_L);                             /* 32-bit operand 1 - signed multiply accumulate - high word */
+sfr_b(MACS32H_H);                             /* 32-bit operand 1 - signed multiply accumulate - high word */
+sfr_w(OP2L);                                  /* 32-bit operand 2 - low word */
+sfr_b(OP2L_L);                                /* 32-bit operand 2 - low word */
+sfr_b(OP2L_H);                                /* 32-bit operand 2 - low word */
+sfr_w(OP2H);                                  /* 32-bit operand 2 - high word */
+sfr_b(OP2H_L);                                /* 32-bit operand 2 - high word */
+sfr_b(OP2H_H);                                /* 32-bit operand 2 - high word */
+sfr_w(RES0);                                  /* 32x32-bit result 0 - least significant word */
+sfr_b(RES0_L);                                /* 32x32-bit result 0 - least significant word */
+sfr_b(RES0_H);                                /* 32x32-bit result 0 - least significant word */
+sfr_w(RES1);                                  /* 32x32-bit result 1 */
+sfr_b(RES1_L);                                /* 32x32-bit result 1 */
+sfr_b(RES1_H);                                /* 32x32-bit result 1 */
+sfr_w(RES2);                                  /* 32x32-bit result 2 */
+sfr_b(RES2_L);                                /* 32x32-bit result 2 */
+sfr_b(RES2_H);                                /* 32x32-bit result 2 */
+sfr_w(RES3);                                  /* 32x32-bit result 3 - most significant word */
+sfr_b(RES3_L);                                /* 32x32-bit result 3 - most significant word */
+sfr_b(RES3_H);                                /* 32x32-bit result 3 - most significant word */
+sfr_w(MPY32CTL0);                             /* MPY32 Control Register 0 */
+sfr_b(MPY32CTL0_L);                           /* MPY32 Control Register 0 */
+sfr_b(MPY32CTL0_H);                           /* MPY32 Control Register 0 */
+
+#define MPY_B                  MPY_L          /* Multiply Unsigned/Operand 1 (Byte Access) */
+#define MPYS_B                 MPYS_L         /* Multiply Signed/Operand 1 (Byte Access) */
+#define MAC_B                  MAC_L          /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */
+#define MACS_B                 MACS_L         /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */
+#define OP2_B                  OP2_L          /* Operand 2 (Byte Access) */
+#define MPY32L_B               MPY32L_L       /* 32-bit operand 1 - multiply - low word (Byte Access) */
+#define MPY32H_B               MPY32H_L       /* 32-bit operand 1 - multiply - high word (Byte Access) */
+#define MPYS32L_B              MPYS32L_L      /* 32-bit operand 1 - signed multiply - low word (Byte Access) */
+#define MPYS32H_B              MPYS32H_L      /* 32-bit operand 1 - signed multiply - high word (Byte Access) */
+#define MAC32L_B               MAC32L_L       /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */
+#define MAC32H_B               MAC32H_L       /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */
+#define MACS32L_B              MACS32L_L      /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */
+#define MACS32H_B              MACS32H_L      /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */
+#define OP2L_B                 OP2L_L         /* 32-bit operand 2 - low word (Byte Access) */
+#define OP2H_B                 OP2H_L         /* 32-bit operand 2 - high word (Byte Access) */
+
+/* MPY32CTL0 Control Bits */
+#define MPYC                   (0x0001)       /* Carry of the multiplier */
+//#define RESERVED            (0x0002)  /* Reserved */
+#define MPYFRAC                (0x0004)       /* Fractional mode */
+#define MPYSAT                 (0x0008)       /* Saturation mode */
+#define MPYM0                  (0x0010)       /* Multiplier mode Bit:0 */
+#define MPYM1                  (0x0020)       /* Multiplier mode Bit:1 */
+#define OP1_32                 (0x0040)       /* Bit-width of operand 1 0:16Bit / 1:32Bit */
+#define OP2_32                 (0x0080)       /* Bit-width of operand 2 0:16Bit / 1:32Bit */
+#define MPYDLYWRTEN            (0x0100)       /* Delayed write enable */
+#define MPYDLY32               (0x0200)       /* Delayed write mode */
+
+/* MPY32CTL0 Control Bits */
+#define MPYC_L                 (0x0001)       /* Carry of the multiplier */
+//#define RESERVED            (0x0002)  /* Reserved */
+#define MPYFRAC_L              (0x0004)       /* Fractional mode */
+#define MPYSAT_L               (0x0008)       /* Saturation mode */
+#define MPYM0_L                (0x0010)       /* Multiplier mode Bit:0 */
+#define MPYM1_L                (0x0020)       /* Multiplier mode Bit:1 */
+#define OP1_32_L               (0x0040)       /* Bit-width of operand 1 0:16Bit / 1:32Bit */
+#define OP2_32_L               (0x0080)       /* Bit-width of operand 2 0:16Bit / 1:32Bit */
+
+/* MPY32CTL0 Control Bits */
+//#define RESERVED            (0x0002)  /* Reserved */
+#define MPYDLYWRTEN_H          (0x0001)       /* Delayed write enable */
+#define MPYDLY32_H             (0x0002)       /* Delayed write mode */
+
+#define MPYM_0                 (0x0000)       /* Multiplier mode: MPY */
+#define MPYM_1                 (0x0010)       /* Multiplier mode: MPYS */
+#define MPYM_2                 (0x0020)       /* Multiplier mode: MAC */
+#define MPYM_3                 (0x0030)       /* Multiplier mode: MACS */
+#define MPYM__MPY              (0x0000)       /* Multiplier mode: MPY */
+#define MPYM__MPYS             (0x0010)       /* Multiplier mode: MPYS */
+#define MPYM__MAC              (0x0020)       /* Multiplier mode: MAC */
+#define MPYM__MACS             (0x0030)       /* Multiplier mode: MACS */
+
+/************************************************************
+* PMM - Power Management System for FRAM
+************************************************************/
+#define __MSP430_HAS_PMM_FRAM__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PMM_FRAM__ 0x0120
+#define PMM_BASE               __MSP430_BASEADDRESS_PMM_FRAM__
+
+sfr_w(PMMCTL0);                               /* PMM Control 0 */
+sfr_b(PMMCTL0_L);                             /* PMM Control 0 */
+sfr_b(PMMCTL0_H);                             /* PMM Control 0 */
+sfr_w(PMMIFG);                                /* PMM Interrupt Flag */
+sfr_b(PMMIFG_L);                              /* PMM Interrupt Flag */
+sfr_b(PMMIFG_H);                              /* PMM Interrupt Flag */
+sfr_w(PM5CTL0);                               /* PMM Power Mode 5 Control Register 0 */
+sfr_b(PM5CTL0_L);                             /* PMM Power Mode 5 Control Register 0 */
+sfr_b(PM5CTL0_H);                             /* PMM Power Mode 5 Control Register 0 */
+
+#define PMMPW                  (0xA500)       /* PMM Register Write Password */
+#define PMMPW_H                (0xA5)         /* PMM Register Write Password for high word access */
+
+/* PMMCTL0 Control Bits */
+#define PMMSWBOR               (0x0004)       /* PMM Software BOR */
+#define PMMSWPOR               (0x0008)       /* PMM Software POR */
+#define PMMREGOFF              (0x0010)       /* PMM Turn Regulator off */
+#define SVSHE                  (0x0040)       /* SVS high side enable */
+#define PMMLPRST               (0x0080)       /* PMM Low-Power Reset Enable */
+
+/* PMMCTL0 Control Bits */
+#define PMMSWBOR_L             (0x0004)       /* PMM Software BOR */
+#define PMMSWPOR_L             (0x0008)       /* PMM Software POR */
+#define PMMREGOFF_L            (0x0010)       /* PMM Turn Regulator off */
+#define SVSHE_L                (0x0040)       /* SVS high side enable */
+#define PMMLPRST_L             (0x0080)       /* PMM Low-Power Reset Enable */
+
+/* PMMIFG Control Bits */
+#define PMMBORIFG              (0x0100)       /* PMM Software BOR interrupt flag */
+#define PMMRSTIFG              (0x0200)       /* PMM RESET pin interrupt flag */
+#define PMMPORIFG              (0x0400)       /* PMM Software POR interrupt flag */
+#define SVSHIFG                (0x2000)       /* SVS low side interrupt flag */
+#define PMMLPM5IFG             (0x8000)       /* LPM5 indication Flag */
+
+/* PMMIFG Control Bits */
+#define PMMBORIFG_H            (0x0001)       /* PMM Software BOR interrupt flag */
+#define PMMRSTIFG_H            (0x0002)       /* PMM RESET pin interrupt flag */
+#define PMMPORIFG_H            (0x0004)       /* PMM Software POR interrupt flag */
+#define SVSHIFG_H              (0x0020)       /* SVS low side interrupt flag */
+#define PMMLPM5IFG_H           (0x0080)       /* LPM5 indication Flag */
+
+/* PM5CTL0 Power Mode 5 Control Bits */
+#define LOCKLPM5               (0x0001)       /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
+
+/* PM5CTL0 Power Mode 5 Control Bits */
+#define LOCKLPM5_L             (0x0001)       /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
+
+
+/************************************************************
+* DIGITAL I/O Port1/2 Pull up / Pull down Resistors
+************************************************************/
+#define __MSP430_HAS_PORT1_R__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORT1_R__ 0x0200
+#define P1_BASE                __MSP430_BASEADDRESS_PORT1_R__
+#define __MSP430_HAS_PORT2_R__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORT2_R__ 0x0200
+#define P2_BASE                __MSP430_BASEADDRESS_PORT2_R__
+#define __MSP430_HAS_PORTA_R__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORTA_R__ 0x0200
+#define PA_BASE                __MSP430_BASEADDRESS_PORTA_R__
+#define __MSP430_HAS_P1SEL0__                 /* Define for DriverLib */
+#define __MSP430_HAS_P2SEL0__                 /* Define for DriverLib */
+#define __MSP430_HAS_PASEL0__                 /* Define for DriverLib */
+#define __MSP430_HAS_P1SEL1__                 /* Define for DriverLib */
+#define __MSP430_HAS_P2SEL1__                 /* Define for DriverLib */
+#define __MSP430_HAS_PASEL1__                 /* Define for DriverLib */
+
+sfr_w(PAIN);                                  /* Port A Input */
+sfr_b(PAIN_L);                                /* Port A Input */
+sfr_b(PAIN_H);                                /* Port A Input */
+sfr_w(PAOUT);                                 /* Port A Output */
+sfr_b(PAOUT_L);                               /* Port A Output */
+sfr_b(PAOUT_H);                               /* Port A Output */
+sfr_w(PADIR);                                 /* Port A Direction */
+sfr_b(PADIR_L);                               /* Port A Direction */
+sfr_b(PADIR_H);                               /* Port A Direction */
+sfr_w(PAREN);                                 /* Port A Resistor Enable */
+sfr_b(PAREN_L);                               /* Port A Resistor Enable */
+sfr_b(PAREN_H);                               /* Port A Resistor Enable */
+sfr_w(PASEL0);                                /* Port A Selection 0 */
+sfr_b(PASEL0_L);                              /* Port A Selection 0 */
+sfr_b(PASEL0_H);                              /* Port A Selection 0 */
+sfr_w(PASEL1);                                /* Port A Selection 1 */
+sfr_b(PASEL1_L);                              /* Port A Selection 1 */
+sfr_b(PASEL1_H);                              /* Port A Selection 1 */
+sfr_w(PASELC);                                /* Port A Complement Selection */
+sfr_b(PASELC_L);                              /* Port A Complement Selection */
+sfr_b(PASELC_H);                              /* Port A Complement Selection */
+sfr_w(PAIES);                                 /* Port A Interrupt Edge Select */
+sfr_b(PAIES_L);                               /* Port A Interrupt Edge Select */
+sfr_b(PAIES_H);                               /* Port A Interrupt Edge Select */
+sfr_w(PAIE);                                  /* Port A Interrupt Enable */
+sfr_b(PAIE_L);                                /* Port A Interrupt Enable */
+sfr_b(PAIE_H);                                /* Port A Interrupt Enable */
+sfr_w(PAIFG);                                 /* Port A Interrupt Flag */
+sfr_b(PAIFG_L);                               /* Port A Interrupt Flag */
+sfr_b(PAIFG_H);                               /* Port A Interrupt Flag */
+
+
+sfr_w(P1IV);                                  /* Port 1 Interrupt Vector Word */
+sfr_w(P2IV);                                  /* Port 2 Interrupt Vector Word */
+#define P1IN                   (PAIN_L)       /* Port 1 Input */
+#define P1OUT                  (PAOUT_L)      /* Port 1 Output */
+#define P1DIR                  (PADIR_L)      /* Port 1 Direction */
+#define P1REN                  (PAREN_L)      /* Port 1 Resistor Enable */
+#define P1SEL0                 (PASEL0_L)     /* Port 1 Selection 0 */
+#define P1SEL1                 (PASEL1_L)     /* Port 1 Selection 1 */
+#define P1SELC                 (PASELC_L)     /* Port 1 Complement Selection */
+#define P1IES                  (PAIES_L)      /* Port 1 Interrupt Edge Select */
+#define P1IE                   (PAIE_L)       /* Port 1 Interrupt Enable */
+#define P1IFG                  (PAIFG_L)      /* Port 1 Interrupt Flag */
+
+//Definitions for P1IV
+#define P1IV_NONE              (0x0000)       /* No Interrupt pending */
+#define P1IV_P1IFG0            (0x0002)       /* P1IV P1IFG.0 */
+#define P1IV_P1IFG1            (0x0004)       /* P1IV P1IFG.1 */
+#define P1IV_P1IFG2            (0x0006)       /* P1IV P1IFG.2 */
+#define P1IV_P1IFG3            (0x0008)       /* P1IV P1IFG.3 */
+#define P1IV_P1IFG4            (0x000A)       /* P1IV P1IFG.4 */
+#define P1IV_P1IFG5            (0x000C)       /* P1IV P1IFG.5 */
+#define P1IV_P1IFG6            (0x000E)       /* P1IV P1IFG.6 */
+#define P1IV_P1IFG7            (0x0010)       /* P1IV P1IFG.7 */
+
+#define P2IN                   (PAIN_H)       /* Port 2 Input */
+#define P2OUT                  (PAOUT_H)      /* Port 2 Output */
+#define P2DIR                  (PADIR_H)      /* Port 2 Direction */
+#define P2REN                  (PAREN_H)      /* Port 2 Resistor Enable */
+#define P2SEL0                 (PASEL0_H)     /* Port 2 Selection 0 */
+#define P2SEL1                 (PASEL1_H)     /* Port 2 Selection 1 */
+#define P2SELC                 (PASELC_H)     /* Port 2 Complement Selection */
+#define P2IES                  (PAIES_H)      /* Port 2 Interrupt Edge Select */
+#define P2IE                   (PAIE_H)       /* Port 2 Interrupt Enable */
+#define P2IFG                  (PAIFG_H)      /* Port 2 Interrupt Flag */
+
+//Definitions for P2IV
+#define P2IV_NONE              (0x0000)       /* No Interrupt pending */
+#define P2IV_P2IFG0            (0x0002)       /* P2IV P2IFG.0 */
+#define P2IV_P2IFG1            (0x0004)       /* P2IV P2IFG.1 */
+#define P2IV_P2IFG2            (0x0006)       /* P2IV P2IFG.2 */
+#define P2IV_P2IFG3            (0x0008)       /* P2IV P2IFG.3 */
+#define P2IV_P2IFG4            (0x000A)       /* P2IV P2IFG.4 */
+#define P2IV_P2IFG5            (0x000C)       /* P2IV P2IFG.5 */
+#define P2IV_P2IFG6            (0x000E)       /* P2IV P2IFG.6 */
+#define P2IV_P2IFG7            (0x0010)       /* P2IV P2IFG.7 */
+
+
+/************************************************************
+* DIGITAL I/O Port3/4 Pull up / Pull down Resistors
+************************************************************/
+#define __MSP430_HAS_PORT3_R__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORT3_R__ 0x0220
+#define P3_BASE                __MSP430_BASEADDRESS_PORT3_R__
+#define __MSP430_HAS_PORT4_R__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORT4_R__ 0x0220
+#define P4_BASE                __MSP430_BASEADDRESS_PORT4_R__
+#define __MSP430_HAS_PORTB_R__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORTB_R__ 0x0220
+#define PB_BASE                __MSP430_BASEADDRESS_PORTB_R__
+#define __MSP430_HAS_P3SEL0__                 /* Define for DriverLib */
+#define __MSP430_HAS_P4SEL0__                 /* Define for DriverLib */
+#define __MSP430_HAS_PBSEL0__                 /* Define for DriverLib */
+#define __MSP430_HAS_P3SEL1__                 /* Define for DriverLib */
+#define __MSP430_HAS_P4SEL1__                 /* Define for DriverLib */
+#define __MSP430_HAS_PBSEL1__                 /* Define for DriverLib */
+
+sfr_w(PBIN);                                  /* Port B Input */
+sfr_b(PBIN_L);                                /* Port B Input */
+sfr_b(PBIN_H);                                /* Port B Input */
+sfr_w(PBOUT);                                 /* Port B Output */
+sfr_b(PBOUT_L);                               /* Port B Output */
+sfr_b(PBOUT_H);                               /* Port B Output */
+sfr_w(PBDIR);                                 /* Port B Direction */
+sfr_b(PBDIR_L);                               /* Port B Direction */
+sfr_b(PBDIR_H);                               /* Port B Direction */
+sfr_w(PBREN);                                 /* Port B Resistor Enable */
+sfr_b(PBREN_L);                               /* Port B Resistor Enable */
+sfr_b(PBREN_H);                               /* Port B Resistor Enable */
+sfr_w(PBSEL0);                                /* Port B Selection 0 */
+sfr_b(PBSEL0_L);                              /* Port B Selection 0 */
+sfr_b(PBSEL0_H);                              /* Port B Selection 0 */
+sfr_w(PBSEL1);                                /* Port B Selection 1 */
+sfr_b(PBSEL1_L);                              /* Port B Selection 1 */
+sfr_b(PBSEL1_H);                              /* Port B Selection 1 */
+sfr_w(PBSELC);                                /* Port B Complement Selection */
+sfr_b(PBSELC_L);                              /* Port B Complement Selection */
+sfr_b(PBSELC_H);                              /* Port B Complement Selection */
+sfr_w(PBIES);                                 /* Port B Interrupt Edge Select */
+sfr_b(PBIES_L);                               /* Port B Interrupt Edge Select */
+sfr_b(PBIES_H);                               /* Port B Interrupt Edge Select */
+sfr_w(PBIE);                                  /* Port B Interrupt Enable */
+sfr_b(PBIE_L);                                /* Port B Interrupt Enable */
+sfr_b(PBIE_H);                                /* Port B Interrupt Enable */
+sfr_w(PBIFG);                                 /* Port B Interrupt Flag */
+sfr_b(PBIFG_L);                               /* Port B Interrupt Flag */
+sfr_b(PBIFG_H);                               /* Port B Interrupt Flag */
+
+
+sfr_w(P3IV);                                  /* Port 3 Interrupt Vector Word */
+sfr_w(P4IV);                                  /* Port 4 Interrupt Vector Word */
+#define P3IN                   (PBIN_L)       /* Port 3 Input */
+#define P3OUT                  (PBOUT_L)      /* Port 3 Output */
+#define P3DIR                  (PBDIR_L)      /* Port 3 Direction */
+#define P3REN                  (PBREN_L)      /* Port 3 Resistor Enable */
+#define P3SEL0                 (PBSEL0_L)     /* Port 3 Selection 0 */
+#define P3SEL1                 (PBSEL1_L)     /* Port 3 Selection 1 */
+#define P3SELC                 (PBSELC_L)     /* Port 3 Complement Selection */
+#define P3IES                  (PBIES_L)      /* Port 3 Interrupt Edge Select */
+#define P3IE                   (PBIE_L)       /* Port 3 Interrupt Enable */
+#define P3IFG                  (PBIFG_L)      /* Port 3 Interrupt Flag */
+
+//Definitions for P3IV
+#define P3IV_NONE              (0x0000)       /* No Interrupt pending */
+#define P3IV_P3IFG0            (0x0002)       /* P3IV P3IFG.0 */
+#define P3IV_P3IFG1            (0x0004)       /* P3IV P3IFG.1 */
+#define P3IV_P3IFG2            (0x0006)       /* P3IV P3IFG.2 */
+#define P3IV_P3IFG3            (0x0008)       /* P3IV P3IFG.3 */
+#define P3IV_P3IFG4            (0x000A)       /* P3IV P3IFG.4 */
+#define P3IV_P3IFG5            (0x000C)       /* P3IV P3IFG.5 */
+#define P3IV_P3IFG6            (0x000E)       /* P3IV P3IFG.6 */
+#define P3IV_P3IFG7            (0x0010)       /* P3IV P3IFG.7 */
+
+#define P4IN                   (PBIN_H)       /* Port 4 Input */
+#define P4OUT                  (PBOUT_H)      /* Port 4 Output */
+#define P4DIR                  (PBDIR_H)      /* Port 4 Direction */
+#define P4REN                  (PBREN_H)      /* Port 4 Resistor Enable */
+#define P4SEL0                 (PBSEL0_H)     /* Port 4 Selection 0 */
+#define P4SEL1                 (PBSEL1_H)     /* Port 4 Selection 1 */
+#define P4SELC                 (PBSELC_H)     /* Port 4 Complement Selection */
+#define P4IES                  (PBIES_H)      /* Port 4 Interrupt Edge Select */
+#define P4IE                   (PBIE_H)       /* Port 4 Interrupt Enable */
+#define P4IFG                  (PBIFG_H)      /* Port 4 Interrupt Flag */
+
+//Definitions for P4IV
+#define P4IV_NONE              (0x0000)       /* No Interrupt pending */
+#define P4IV_P4IFG0            (0x0002)       /* P4IV P4IFG.0 */
+#define P4IV_P4IFG1            (0x0004)       /* P4IV P4IFG.1 */
+#define P4IV_P4IFG2            (0x0006)       /* P4IV P4IFG.2 */
+#define P4IV_P4IFG3            (0x0008)       /* P4IV P4IFG.3 */
+#define P4IV_P4IFG4            (0x000A)       /* P4IV P4IFG.4 */
+#define P4IV_P4IFG5            (0x000C)       /* P4IV P4IFG.5 */
+#define P4IV_P4IFG6            (0x000E)       /* P4IV P4IFG.6 */
+#define P4IV_P4IFG7            (0x0010)       /* P4IV P4IFG.7 */
+
+
+/************************************************************
+* DIGITAL I/O Port5/6 Pull up / Pull down Resistors
+************************************************************/
+#define __MSP430_HAS_PORT5_R__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORT5_R__ 0x0240
+#define P5_BASE                __MSP430_BASEADDRESS_PORT5_R__
+#define __MSP430_HAS_PORT6_R__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORT6_R__ 0x0240
+#define P6_BASE                __MSP430_BASEADDRESS_PORT6_R__
+#define __MSP430_HAS_PORTC_R__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORTC_R__ 0x0240
+#define PC_BASE                __MSP430_BASEADDRESS_PORTC_R__
+#define __MSP430_HAS_P5SEL0__                 /* Define for DriverLib */
+#define __MSP430_HAS_P6SEL0__                 /* Define for DriverLib */
+#define __MSP430_HAS_PCSEL0__                 /* Define for DriverLib */
+#define __MSP430_HAS_P5SEL1__                 /* Define for DriverLib */
+#define __MSP430_HAS_P6SEL1__                 /* Define for DriverLib */
+#define __MSP430_HAS_PCSEL1__                 /* Define for DriverLib */
+
+sfr_w(PCIN);                                  /* Port C Input */
+sfr_b(PCIN_L);                                /* Port C Input */
+sfr_b(PCIN_H);                                /* Port C Input */
+sfr_w(PCOUT);                                 /* Port C Output */
+sfr_b(PCOUT_L);                               /* Port C Output */
+sfr_b(PCOUT_H);                               /* Port C Output */
+sfr_w(PCDIR);                                 /* Port C Direction */
+sfr_b(PCDIR_L);                               /* Port C Direction */
+sfr_b(PCDIR_H);                               /* Port C Direction */
+sfr_w(PCREN);                                 /* Port C Resistor Enable */
+sfr_b(PCREN_L);                               /* Port C Resistor Enable */
+sfr_b(PCREN_H);                               /* Port C Resistor Enable */
+sfr_w(PCSEL0);                                /* Port C Selection 0 */
+sfr_b(PCSEL0_L);                              /* Port C Selection 0 */
+sfr_b(PCSEL0_H);                              /* Port C Selection 0 */
+sfr_w(PCSEL1);                                /* Port C Selection 1 */
+sfr_b(PCSEL1_L);                              /* Port C Selection 1 */
+sfr_b(PCSEL1_H);                              /* Port C Selection 1 */
+sfr_w(PCSELC);                                /* Port C Complement Selection */
+sfr_b(PCSELC_L);                              /* Port C Complement Selection */
+sfr_b(PCSELC_H);                              /* Port C Complement Selection */
+
+
+#define P5IN                   (PCIN_L)       /* Port 5 Input */
+#define P5OUT                  (PCOUT_L)      /* Port 5 Output */
+#define P5DIR                  (PCDIR_L)      /* Port 5 Direction */
+#define P5REN                  (PCREN_L)      /* Port 5 Resistor Enable */
+#define P5SEL0                 (PCSEL0_L)     /* Port 5 Selection 0 */
+#define P5SEL1                 (PCSEL1_L)     /* Port 5 Selection 1 */
+#define P5SELC                 (PCSELC_L)     /* Port 5 Complement Selection */
+
+#define P6IN                   (PCIN_H)       /* Port 6 Input */
+#define P6OUT                  (PCOUT_H)      /* Port 6 Output */
+#define P6DIR                  (PCDIR_H)      /* Port 6 Direction */
+#define P6REN                  (PCREN_H)      /* Port 6 Resistor Enable */
+#define P6SEL0                 (PCSEL0_H)     /* Port 6 Selection 0 */
+#define P6SEL1                 (PCSEL1_H)     /* Port 6 Selection 1 */
+#define P6SELC                 (PCSELC_H)     /* Port 6 Complement Selection */
+
+
+/************************************************************
+* DIGITAL I/O Port7/8 Pull up / Pull down Resistors
+************************************************************/
+#define __MSP430_HAS_PORT7_R__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORT7_R__ 0x0260
+#define P7_BASE                __MSP430_BASEADDRESS_PORT7_R__
+#define __MSP430_HAS_PORT8_R__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORT8_R__ 0x0260
+#define P8_BASE                __MSP430_BASEADDRESS_PORT8_R__
+#define __MSP430_HAS_PORTD_R__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORTD_R__ 0x0260
+#define PD_BASE                __MSP430_BASEADDRESS_PORTD_R__
+#define __MSP430_HAS_P7SEL0__                 /* Define for DriverLib */
+#define __MSP430_HAS_P8SEL0__                 /* Define for DriverLib */
+#define __MSP430_HAS_PDSEL0__                 /* Define for DriverLib */
+#define __MSP430_HAS_P7SEL1__                 /* Define for DriverLib */
+#define __MSP430_HAS_P8SEL1__                 /* Define for DriverLib */
+#define __MSP430_HAS_PDSEL1__                 /* Define for DriverLib */
+
+sfr_w(PDIN);                                  /* Port D Input */
+sfr_b(PDIN_L);                                /* Port D Input */
+sfr_b(PDIN_H);                                /* Port D Input */
+sfr_w(PDOUT);                                 /* Port D Output */
+sfr_b(PDOUT_L);                               /* Port D Output */
+sfr_b(PDOUT_H);                               /* Port D Output */
+sfr_w(PDDIR);                                 /* Port D Direction */
+sfr_b(PDDIR_L);                               /* Port D Direction */
+sfr_b(PDDIR_H);                               /* Port D Direction */
+sfr_w(PDREN);                                 /* Port D Resistor Enable */
+sfr_b(PDREN_L);                               /* Port D Resistor Enable */
+sfr_b(PDREN_H);                               /* Port D Resistor Enable */
+sfr_w(PDSEL0);                                /* Port D Selection 0 */
+sfr_b(PDSEL0_L);                              /* Port D Selection 0 */
+sfr_b(PDSEL0_H);                              /* Port D Selection 0 */
+sfr_w(PDSEL1);                                /* Port D Selection 1 */
+sfr_b(PDSEL1_L);                              /* Port D Selection 1 */
+sfr_b(PDSEL1_H);                              /* Port D Selection 1 */
+sfr_w(PDSELC);                                /* Port D Complement Selection */
+sfr_b(PDSELC_L);                              /* Port D Complement Selection */
+sfr_b(PDSELC_H);                              /* Port D Complement Selection */
+
+
+#define P7IN                   (PDIN_L)       /* Port 7 Input */
+#define P7OUT                  (PDOUT_L)      /* Port 7 Output */
+#define P7DIR                  (PDDIR_L)      /* Port 7 Direction */
+#define P7REN                  (PDREN_L)      /* Port 7 Resistor Enable */
+#define P7SEL0                 (PDSEL0_L)     /* Port 7 Selection 0 */
+#define P7SEL1                 (PDSEL1_L)     /* Port 7 Selection 1 */
+#define P7SELC                 (PDSELC_L)     /* Port 7 Complement Selection */
+
+#define P8IN                   (PDIN_H)       /* Port 8 Input */
+#define P8OUT                  (PDOUT_H)      /* Port 8 Output */
+#define P8DIR                  (PDDIR_H)      /* Port 8 Direction */
+#define P8REN                  (PDREN_H)      /* Port 8 Resistor Enable */
+#define P8SEL0                 (PDSEL0_H)     /* Port 8 Selection 0 */
+#define P8SEL1                 (PDSEL1_H)     /* Port 8 Selection 1 */
+#define P8SELC                 (PDSELC_H)     /* Port 8 Complement Selection */
+
+
+/************************************************************
+* DIGITAL I/O Port9/10 Pull up / Pull down Resistors
+************************************************************/
+#define __MSP430_HAS_PORT9_R__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORT9_R__ 0x0280
+#define P9_BASE                __MSP430_BASEADDRESS_PORT9_R__
+#define __MSP430_HAS_PORT10_R__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORT10_R__ 0x0280
+#define P10_BASE               __MSP430_BASEADDRESS_PORT10_R__
+#define __MSP430_HAS_PORTE_R__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORTE_R__ 0x0280
+#define PE_BASE                __MSP430_BASEADDRESS_PORTE_R__
+#define __MSP430_HAS_P9SEL0__                 /* Define for DriverLib */
+#define __MSP430_HAS_P10SEL0__                /* Define for DriverLib */
+#define __MSP430_HAS_PESEL0__                 /* Define for DriverLib */
+#define __MSP430_HAS_P9SEL1__                 /* Define for DriverLib */
+#define __MSP430_HAS_P10SEL1__                /* Define for DriverLib */
+#define __MSP430_HAS_PESEL1__                 /* Define for DriverLib */
+
+sfr_w(PEIN);                                  /* Port E Input */
+sfr_b(PEIN_L);                                /* Port E Input */
+sfr_b(PEIN_H);                                /* Port E Input */
+sfr_w(PEOUT);                                 /* Port E Output */
+sfr_b(PEOUT_L);                               /* Port E Output */
+sfr_b(PEOUT_H);                               /* Port E Output */
+sfr_w(PEDIR);                                 /* Port E Direction */
+sfr_b(PEDIR_L);                               /* Port E Direction */
+sfr_b(PEDIR_H);                               /* Port E Direction */
+sfr_w(PEREN);                                 /* Port E Resistor Enable */
+sfr_b(PEREN_L);                               /* Port E Resistor Enable */
+sfr_b(PEREN_H);                               /* Port E Resistor Enable */
+sfr_w(PESEL0);                                /* Port E Selection 0 */
+sfr_b(PESEL0_L);                              /* Port E Selection 0 */
+sfr_b(PESEL0_H);                              /* Port E Selection 0 */
+sfr_w(PESEL1);                                /* Port E Selection 1 */
+sfr_b(PESEL1_L);                              /* Port E Selection 1 */
+sfr_b(PESEL1_H);                              /* Port E Selection 1 */
+sfr_w(PESELC);                                /* Port E Complement Selection */
+sfr_b(PESELC_L);                              /* Port E Complement Selection */
+sfr_b(PESELC_H);                              /* Port E Complement Selection */
+
+
+#define P9IN                   (PEIN_L)       /* Port 9 Input */
+#define P9OUT                  (PEOUT_L)      /* Port 9 Output */
+#define P9DIR                  (PEDIR_L)      /* Port 9 Direction */
+#define P9REN                  (PEREN_L)      /* Port 9 Resistor Enable */
+#define P9SEL0                 (PESEL0_L)     /* Port 9 Selection 0 */
+#define P9SEL1                 (PESEL1_L)     /* Port 9 Selection 1 */
+#define P9SELC                 (PESELC_L)     /* Port 9 Complement Selection */
+
+#define P10IN                  (PEIN_H)       /* Port 10 Input */
+#define P10OUT                 (PEOUT_H)      /* Port 10 Output */
+#define P10DIR                 (PEDIR_H)      /* Port 10 Direction */
+#define P10REN                 (PEREN_H)      /* Port 10 Resistor Enable */
+#define P10SEL0                (PESEL0_H)     /* Port 10 Selection 0 */
+#define P10SEL1                (PESEL1_H)     /* Port 10 Selection 1 */
+#define P10SELC                (PESELC_H)     /* Port 10 Complement Selection */
+
+
+/************************************************************
+* DIGITAL I/O PortJ Pull up / Pull down Resistors
+************************************************************/
+#define __MSP430_HAS_PORTJ_R__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORTJ_R__ 0x0320
+#define PJ_BASE                __MSP430_BASEADDRESS_PORTJ_R__
+#define __MSP430_HAS_PJSEL0__                 /* Define for DriverLib */
+#define __MSP430_HAS_PJSEL1__                 /* Define for DriverLib */
+
+sfr_w(PJIN);                                  /* Port J Input */
+sfr_b(PJIN_L);                                /* Port J Input */
+sfr_b(PJIN_H);                                /* Port J Input */
+sfr_w(PJOUT);                                 /* Port J Output */
+sfr_b(PJOUT_L);                               /* Port J Output */
+sfr_b(PJOUT_H);                               /* Port J Output */
+sfr_w(PJDIR);                                 /* Port J Direction */
+sfr_b(PJDIR_L);                               /* Port J Direction */
+sfr_b(PJDIR_H);                               /* Port J Direction */
+sfr_w(PJREN);                                 /* Port J Resistor Enable */
+sfr_b(PJREN_L);                               /* Port J Resistor Enable */
+sfr_b(PJREN_H);                               /* Port J Resistor Enable */
+sfr_w(PJSEL0);                                /* Port J Selection 0 */
+sfr_b(PJSEL0_L);                              /* Port J Selection 0 */
+sfr_b(PJSEL0_H);                              /* Port J Selection 0 */
+sfr_w(PJSEL1);                                /* Port J Selection 1 */
+sfr_b(PJSEL1_L);                              /* Port J Selection 1 */
+sfr_b(PJSEL1_H);                              /* Port J Selection 1 */
+sfr_w(PJSELC);                                /* Port J Complement Selection */
+sfr_b(PJSELC_L);                              /* Port J Complement Selection */
+sfr_b(PJSELC_H);                              /* Port J Complement Selection */
+
+/*************************************************************
+* RAM Control Module for FRAM
+*************************************************************/
+#define __MSP430_HAS_RC_FRAM__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_RC_FRAM__ 0x0158
+#define RAM_BASE               __MSP430_BASEADDRESS_RC_FRAM__
+
+sfr_w(RCCTL0);                                /* Ram Controller Control Register */
+sfr_b(RCCTL0_L);                              /* Ram Controller Control Register */
+sfr_b(RCCTL0_H);                              /* Ram Controller Control Register */
+
+/* RCCTL0 Control Bits */
+#define RCRS0OFF0              (0x0001)       /* RAM Controller RAM Sector 0 Off Bit: 0 */
+#define RCRS0OFF1              (0x0002)       /* RAM Controller RAM Sector 0 Off Bit: 1 */
+#define RCRS1OFF0              (0x0004)       /* RAM Controller RAM Sector 1 Off Bit: 0 */
+#define RCRS1OFF1              (0x0008)       /* RAM Controller RAM Sector 1 Off Bit: 1 */
+#define RCRS2OFF0              (0x0010)       /* RAM Controller RAM Sector 2 Off Bit: 0 */
+#define RCRS2OFF1              (0x0020)       /* RAM Controller RAM Sector 2 Off Bit: 1 */
+#define RCRS3OFF0              (0x0040)       /* RAM Controller RAM Sector 3 Off Bit: 0 */
+#define RCRS3OFF1              (0x0080)       /* RAM Controller RAM Sector 3 Off Bit: 1 */
+
+/* RCCTL0 Control Bits */
+#define RCRS0OFF0_L            (0x0001)       /* RAM Controller RAM Sector 0 Off Bit: 0 */
+#define RCRS0OFF1_L            (0x0002)       /* RAM Controller RAM Sector 0 Off Bit: 1 */
+#define RCRS1OFF0_L            (0x0004)       /* RAM Controller RAM Sector 1 Off Bit: 0 */
+#define RCRS1OFF1_L            (0x0008)       /* RAM Controller RAM Sector 1 Off Bit: 1 */
+#define RCRS2OFF0_L            (0x0010)       /* RAM Controller RAM Sector 2 Off Bit: 0 */
+#define RCRS2OFF1_L            (0x0020)       /* RAM Controller RAM Sector 2 Off Bit: 1 */
+#define RCRS3OFF0_L            (0x0040)       /* RAM Controller RAM Sector 3 Off Bit: 0 */
+#define RCRS3OFF1_L            (0x0080)       /* RAM Controller RAM Sector 3 Off Bit: 1 */
+
+#define RCKEY                  (0x5A00)
+
+#define RCRS0OFF_0             (0x0000)       /* RAM Controller RAM Sector 0 Off : 0 */
+#define RCRS0OFF_1             (0x0001)       /* RAM Controller RAM Sector 0 Off : 1 */
+#define RCRS0OFF_2             (0x0002)       /* RAM Controller RAM Sector 0 Off : 2 */
+#define RCRS0OFF_3             (0x0003)       /* RAM Controller RAM Sector 0 Off : 3 */
+#define RCRS1OFF_0             (0x0000)       /* RAM Controller RAM Sector 1 Off : 0 */
+#define RCRS1OFF_1             (0x0004)       /* RAM Controller RAM Sector 1 Off : 1 */
+#define RCRS1OFF_2             (0x0008)       /* RAM Controller RAM Sector 1 Off : 2 */
+#define RCRS1OFF_3             (0x000C)       /* RAM Controller RAM Sector 1 Off : 3 */
+#define RCRS2OFF_0             (0x0000)       /* RAM Controller RAM Sector 2 Off : 0 */
+#define RCRS2OFF_1             (0x0010)       /* RAM Controller RAM Sector 2 Off : 1 */
+#define RCRS2OFF_2             (0x0020)       /* RAM Controller RAM Sector 2 Off : 2 */
+#define RCRS2OFF_3             (0x0030)       /* RAM Controller RAM Sector 2 Off : 3 */
+#define RCRS3OFF_0             (0x0000)       /* RAM Controller RAM Sector 3 Off : 0 */
+#define RCRS3OFF_1             (0x0040)       /* RAM Controller RAM Sector 3 Off : 1 */
+#define RCRS3OFF_2             (0x0080)       /* RAM Controller RAM Sector 3 Off : 2 */
+#define RCRS3OFF_3             (0x00C0)       /* RAM Controller RAM Sector 3 Off : 3 */
+
+/************************************************************
+* Shared Reference
+************************************************************/
+#define __MSP430_HAS_REF_A__                  /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_REF_A__ 0x01B0
+#define REF_A_BASE             __MSP430_BASEADDRESS_REF_A__
+
+sfr_w(REFCTL0);                               /* REF Shared Reference control register 0 */
+sfr_b(REFCTL0_L);                             /* REF Shared Reference control register 0 */
+sfr_b(REFCTL0_H);                             /* REF Shared Reference control register 0 */
+
+/* REFCTL0 Control Bits */
+#define REFON                  (0x0001)       /* REF Reference On */
+#define REFOUT                 (0x0002)       /* REF Reference output Buffer On */
+//#define RESERVED            (0x0004)  /* Reserved */
+#define REFTCOFF               (0x0008)       /* REF Temp.Sensor off */
+#define REFVSEL0               (0x0010)       /* REF Reference Voltage Level Select Bit:0 */
+#define REFVSEL1               (0x0020)       /* REF Reference Voltage Level Select Bit:1 */
+#define REFGENOT               (0x0040)       /* REF Reference generator one-time trigger */
+#define REFBGOT                (0x0080)       /* REF Bandgap and bandgap buffer one-time trigger */
+#define REFGENACT              (0x0100)       /* REF Reference generator active */
+#define REFBGACT               (0x0200)       /* REF Reference bandgap active */
+#define REFGENBUSY             (0x0400)       /* REF Reference generator busy */
+#define BGMODE                 (0x0800)       /* REF Bandgap mode */
+#define REFGENRDY              (0x1000)       /* REF Reference generator ready */
+#define REFBGRDY               (0x2000)       /* REF Reference bandgap ready */
+//#define RESERVED            (0x4000)  /* Reserved */
+//#define RESERVED            (0x8000)  /* Reserved */
+
+/* REFCTL0 Control Bits */
+#define REFON_L                (0x0001)       /* REF Reference On */
+#define REFOUT_L               (0x0002)       /* REF Reference output Buffer On */
+//#define RESERVED            (0x0004)  /* Reserved */
+#define REFTCOFF_L             (0x0008)       /* REF Temp.Sensor off */
+#define REFVSEL0_L             (0x0010)       /* REF Reference Voltage Level Select Bit:0 */
+#define REFVSEL1_L             (0x0020)       /* REF Reference Voltage Level Select Bit:1 */
+#define REFGENOT_L             (0x0040)       /* REF Reference generator one-time trigger */
+#define REFBGOT_L              (0x0080)       /* REF Bandgap and bandgap buffer one-time trigger */
+//#define RESERVED            (0x4000)  /* Reserved */
+//#define RESERVED            (0x8000)  /* Reserved */
+
+/* REFCTL0 Control Bits */
+//#define RESERVED            (0x0004)  /* Reserved */
+#define REFGENACT_H            (0x0001)       /* REF Reference generator active */
+#define REFBGACT_H             (0x0002)       /* REF Reference bandgap active */
+#define REFGENBUSY_H           (0x0004)       /* REF Reference generator busy */
+#define BGMODE_H               (0x0008)       /* REF Bandgap mode */
+#define REFGENRDY_H            (0x0010)       /* REF Reference generator ready */
+#define REFBGRDY_H             (0x0020)       /* REF Reference bandgap ready */
+//#define RESERVED            (0x4000)  /* Reserved */
+//#define RESERVED            (0x8000)  /* Reserved */
+
+#define REFVSEL_0              (0x0000)       /* REF Reference Voltage Level Select 1.2V */
+#define REFVSEL_1              (0x0010)       /* REF Reference Voltage Level Select 2.0V */
+#define REFVSEL_2              (0x0020)       /* REF Reference Voltage Level Select 2.5V */
+#define REFVSEL_3              (0x0030)       /* REF Reference Voltage Level Select 2.5V */
+
+/************************************************************
+* Real Time Clock
+************************************************************/
+#define __MSP430_HAS_RTC_C__                  /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_RTC_C__ 0x04A0
+#define RTC_C_BASE             __MSP430_BASEADDRESS_RTC_C__
+
+sfr_w(RTCCTL0);                               /* Real Timer Clock Control 0/Key */
+sfr_b(RTCCTL0_L);                             /* Real Timer Clock Control 0/Key */
+sfr_b(RTCCTL0_H);                             /* Real Timer Clock Control 0/Key */
+#define RTCPWD                 RTCCTL0_H
+sfr_w(RTCCTL13);                              /* Real Timer Clock Control 1/3 */
+sfr_b(RTCCTL13_L);                            /* Real Timer Clock Control 1/3 */
+sfr_b(RTCCTL13_H);                            /* Real Timer Clock Control 1/3 */
+#define RTCCTL1                RTCCTL13_L
+#define RTCCTL3                RTCCTL13_H
+sfr_w(RTCOCAL);                               /* Real Timer Clock Offset Calibartion */
+sfr_b(RTCOCAL_L);                             /* Real Timer Clock Offset Calibartion */
+sfr_b(RTCOCAL_H);                             /* Real Timer Clock Offset Calibartion */
+sfr_w(RTCTCMP);                               /* Real Timer Temperature Compensation */
+sfr_b(RTCTCMP_L);                             /* Real Timer Temperature Compensation */
+sfr_b(RTCTCMP_H);                             /* Real Timer Temperature Compensation */
+sfr_w(RTCPS0CTL);                             /* Real Timer Prescale Timer 0 Control */
+sfr_b(RTCPS0CTL_L);                           /* Real Timer Prescale Timer 0 Control */
+sfr_b(RTCPS0CTL_H);                           /* Real Timer Prescale Timer 0 Control */
+sfr_w(RTCPS1CTL);                             /* Real Timer Prescale Timer 1 Control */
+sfr_b(RTCPS1CTL_L);                           /* Real Timer Prescale Timer 1 Control */
+sfr_b(RTCPS1CTL_H);                           /* Real Timer Prescale Timer 1 Control */
+sfr_w(RTCPS);                                 /* Real Timer Prescale Timer Control */
+sfr_b(RTCPS_L);                               /* Real Timer Prescale Timer Control */
+sfr_b(RTCPS_H);                               /* Real Timer Prescale Timer Control */
+sfr_w(RTCIV);                                 /* Real Time Clock Interrupt Vector */
+sfr_w(RTCTIM0);                               /* Real Time Clock Time 0 */
+sfr_b(RTCTIM0_L);                             /* Real Time Clock Time 0 */
+sfr_b(RTCTIM0_H);                             /* Real Time Clock Time 0 */
+sfr_w(RTCTIM1);                               /* Real Time Clock Time 1 */
+sfr_b(RTCTIM1_L);                             /* Real Time Clock Time 1 */
+sfr_b(RTCTIM1_H);                             /* Real Time Clock Time 1 */
+sfr_w(RTCDATE);                               /* Real Time Clock Date */
+sfr_b(RTCDATE_L);                             /* Real Time Clock Date */
+sfr_b(RTCDATE_H);                             /* Real Time Clock Date */
+sfr_w(RTCYEAR);                               /* Real Time Clock Year */
+sfr_b(RTCYEAR_L);                             /* Real Time Clock Year */
+sfr_b(RTCYEAR_H);                             /* Real Time Clock Year */
+sfr_w(RTCAMINHR);                             /* Real Time Clock Alarm Min/Hour */
+sfr_b(RTCAMINHR_L);                           /* Real Time Clock Alarm Min/Hour */
+sfr_b(RTCAMINHR_H);                           /* Real Time Clock Alarm Min/Hour */
+sfr_w(RTCADOWDAY);                            /* Real Time Clock Alarm day of week/day */
+sfr_b(RTCADOWDAY_L);                          /* Real Time Clock Alarm day of week/day */
+sfr_b(RTCADOWDAY_H);                          /* Real Time Clock Alarm day of week/day */
+sfr_w(BIN2BCD);                               /* Real Time Binary-to-BCD conversion register */
+sfr_w(BCD2BIN);                               /* Real Time BCD-to-binary conversion register */
+
+#define RTCSEC                 RTCTIM0_L
+#define RTCMIN                 RTCTIM0_H
+#define RTCHOUR                RTCTIM1_L
+#define RTCDOW                 RTCTIM1_H
+#define RTCDAY                 RTCDATE_L
+#define RTCMON                 RTCDATE_H
+#define RTCYEARL               RTCYEAR_L
+#define RT0PS                  RTCPS_L
+#define RT1PS                  RTCPS_H
+#define RTCAMIN                RTCAMINHR_L    /* Real Time Clock Alarm Min */
+#define RTCAHOUR               RTCAMINHR_H    /* Real Time Clock Alarm Hour */
+#define RTCADOW                RTCADOWDAY_L   /* Real Time Clock Alarm day of week */
+#define RTCADAY                RTCADOWDAY_H   /* Real Time Clock Alarm day */
+
+/* RTCCTL0 Control Bits */
+#define RTCOFIE                (0x0080)       /* RTC 32kHz cyrstal oscillator fault interrupt enable */
+#define RTCTEVIE               (0x0040)       /* RTC Time Event Interrupt Enable Flag */
+#define RTCAIE                 (0x0020)       /* RTC Alarm Interrupt Enable Flag */
+#define RTCRDYIE               (0x0010)       /* RTC Ready Interrupt Enable Flag */
+#define RTCOFIFG               (0x0008)       /* RTC 32kHz cyrstal oscillator fault interrupt flag */
+#define RTCTEVIFG              (0x0004)       /* RTC Time Event Interrupt Flag */
+#define RTCAIFG                (0x0002)       /* RTC Alarm Interrupt Flag */
+#define RTCRDYIFG              (0x0001)       /* RTC Ready Interrupt Flag */
+
+/* RTCCTL0 Control Bits */
+#define RTCOFIE_L              (0x0080)       /* RTC 32kHz cyrstal oscillator fault interrupt enable */
+#define RTCTEVIE_L             (0x0040)       /* RTC Time Event Interrupt Enable Flag */
+#define RTCAIE_L               (0x0020)       /* RTC Alarm Interrupt Enable Flag */
+#define RTCRDYIE_L             (0x0010)       /* RTC Ready Interrupt Enable Flag */
+#define RTCOFIFG_L             (0x0008)       /* RTC 32kHz cyrstal oscillator fault interrupt flag */
+#define RTCTEVIFG_L            (0x0004)       /* RTC Time Event Interrupt Flag */
+#define RTCAIFG_L              (0x0002)       /* RTC Alarm Interrupt Flag */
+#define RTCRDYIFG_L            (0x0001)       /* RTC Ready Interrupt Flag */
+
+#define RTCKEY                 (0xA500)       /* RTC Key for RTC write access */
+#define RTCKEY_H               (0xA5)         /* RTC Key for RTC write access (high word) */
+
+/* RTCCTL13 Control Bits */
+#define RTCCALF1               (0x0200)       /* RTC Calibration Frequency Bit 1 */
+#define RTCCALF0               (0x0100)       /* RTC Calibration Frequency Bit 0 */
+#define RTCBCD                 (0x0080)       /* RTC BCD  0:Binary / 1:BCD */
+#define RTCHOLD                (0x0040)       /* RTC Hold */
+#define RTCMODE                (0x0020)       /* RTC Mode 0:Counter / 1: Calendar */
+#define RTCRDY                 (0x0010)       /* RTC Ready */
+#define RTCSSEL1               (0x0008)       /* RTC Source Select 1 */
+#define RTCSSEL0               (0x0004)       /* RTC Source Select 0 */
+#define RTCTEV1                (0x0002)       /* RTC Time Event 1 */
+#define RTCTEV0                (0x0001)       /* RTC Time Event 0 */
+
+/* RTCCTL13 Control Bits */
+#define RTCBCD_L               (0x0080)       /* RTC BCD  0:Binary / 1:BCD */
+#define RTCHOLD_L              (0x0040)       /* RTC Hold */
+#define RTCMODE_L              (0x0020)       /* RTC Mode 0:Counter / 1: Calendar */
+#define RTCRDY_L               (0x0010)       /* RTC Ready */
+#define RTCSSEL1_L             (0x0008)       /* RTC Source Select 1 */
+#define RTCSSEL0_L             (0x0004)       /* RTC Source Select 0 */
+#define RTCTEV1_L              (0x0002)       /* RTC Time Event 1 */
+#define RTCTEV0_L              (0x0001)       /* RTC Time Event 0 */
+
+/* RTCCTL13 Control Bits */
+#define RTCCALF1_H             (0x0002)       /* RTC Calibration Frequency Bit 1 */
+#define RTCCALF0_H             (0x0001)       /* RTC Calibration Frequency Bit 0 */
+
+#define RTCSSEL_0              (0x0000)       /* RTC Source Select ACLK */
+#define RTCSSEL_1              (0x0004)       /* RTC Source Select SMCLK */
+#define RTCSSEL_2              (0x0008)       /* RTC Source Select RT1PS */
+#define RTCSSEL_3              (0x000C)       /* RTC Source Select RT1PS */
+#define RTCSSEL__LFXT          (0x0000)       /* RTC Source Select LFXT */
+#define RTCSSEL__RT1PS         (0x0008)       /* RTC Source Select RT1PS */
+
+#define RTCSSEL__ACLK          (0x0000)       /* Legacy define */
+
+#define RTCTEV_0               (0x0000)       /* RTC Time Event: 0 (Min. changed) */
+#define RTCTEV_1               (0x0001)       /* RTC Time Event: 1 (Hour changed) */
+#define RTCTEV_2               (0x0002)       /* RTC Time Event: 2 (12:00 changed) */
+#define RTCTEV_3               (0x0003)       /* RTC Time Event: 3 (00:00 changed) */
+#define RTCTEV__MIN            (0x0000)       /* RTC Time Event: 0 (Min. changed) */
+#define RTCTEV__HOUR           (0x0001)       /* RTC Time Event: 1 (Hour changed) */
+#define RTCTEV__0000           (0x0002)       /* RTC Time Event: 2 (00:00 changed) */
+#define RTCTEV__1200           (0x0003)       /* RTC Time Event: 3 (12:00 changed) */
+
+#define RTCCALF_0              (0x0000)       /* RTC Calibration Frequency: No Output */
+#define RTCCALF_1              (0x0100)       /* RTC Calibration Frequency: 512 Hz */
+#define RTCCALF_2              (0x0200)       /* RTC Calibration Frequency: 256 Hz */
+#define RTCCALF_3              (0x0300)       /* RTC Calibration Frequency: 1 Hz */
+
+/* RTCOCAL Control Bits */
+#define RTCOCALS               (0x8000)       /* RTC Offset Calibration Sign */
+#define RTCOCAL7               (0x0080)       /* RTC Offset Calibration Bit 7 */
+#define RTCOCAL6               (0x0040)       /* RTC Offset Calibration Bit 6 */
+#define RTCOCAL5               (0x0020)       /* RTC Offset Calibration Bit 5 */
+#define RTCOCAL4               (0x0010)       /* RTC Offset Calibration Bit 4 */
+#define RTCOCAL3               (0x0008)       /* RTC Offset Calibration Bit 3 */
+#define RTCOCAL2               (0x0004)       /* RTC Offset Calibration Bit 2 */
+#define RTCOCAL1               (0x0002)       /* RTC Offset Calibration Bit 1 */
+#define RTCOCAL0               (0x0001)       /* RTC Offset Calibration Bit 0 */
+
+/* RTCOCAL Control Bits */
+#define RTCOCAL7_L             (0x0080)       /* RTC Offset Calibration Bit 7 */
+#define RTCOCAL6_L             (0x0040)       /* RTC Offset Calibration Bit 6 */
+#define RTCOCAL5_L             (0x0020)       /* RTC Offset Calibration Bit 5 */
+#define RTCOCAL4_L             (0x0010)       /* RTC Offset Calibration Bit 4 */
+#define RTCOCAL3_L             (0x0008)       /* RTC Offset Calibration Bit 3 */
+#define RTCOCAL2_L             (0x0004)       /* RTC Offset Calibration Bit 2 */
+#define RTCOCAL1_L             (0x0002)       /* RTC Offset Calibration Bit 1 */
+#define RTCOCAL0_L             (0x0001)       /* RTC Offset Calibration Bit 0 */
+
+/* RTCOCAL Control Bits */
+#define RTCOCALS_H             (0x0080)       /* RTC Offset Calibration Sign */
+
+/* RTCTCMP Control Bits */
+#define RTCTCMPS               (0x8000)       /* RTC Temperature Compensation Sign */
+#define RTCTCRDY               (0x4000)       /* RTC Temperature compensation ready */
+#define RTCTCOK                (0x2000)       /* RTC Temperature compensation write OK */
+#define RTCTCMP7               (0x0080)       /* RTC Temperature Compensation Bit 7 */
+#define RTCTCMP6               (0x0040)       /* RTC Temperature Compensation Bit 6 */
+#define RTCTCMP5               (0x0020)       /* RTC Temperature Compensation Bit 5 */
+#define RTCTCMP4               (0x0010)       /* RTC Temperature Compensation Bit 4 */
+#define RTCTCMP3               (0x0008)       /* RTC Temperature Compensation Bit 3 */
+#define RTCTCMP2               (0x0004)       /* RTC Temperature Compensation Bit 2 */
+#define RTCTCMP1               (0x0002)       /* RTC Temperature Compensation Bit 1 */
+#define RTCTCMP0               (0x0001)       /* RTC Temperature Compensation Bit 0 */
+
+/* RTCTCMP Control Bits */
+#define RTCTCMP7_L             (0x0080)       /* RTC Temperature Compensation Bit 7 */
+#define RTCTCMP6_L             (0x0040)       /* RTC Temperature Compensation Bit 6 */
+#define RTCTCMP5_L             (0x0020)       /* RTC Temperature Compensation Bit 5 */
+#define RTCTCMP4_L             (0x0010)       /* RTC Temperature Compensation Bit 4 */
+#define RTCTCMP3_L             (0x0008)       /* RTC Temperature Compensation Bit 3 */
+#define RTCTCMP2_L             (0x0004)       /* RTC Temperature Compensation Bit 2 */
+#define RTCTCMP1_L             (0x0002)       /* RTC Temperature Compensation Bit 1 */
+#define RTCTCMP0_L             (0x0001)       /* RTC Temperature Compensation Bit 0 */
+
+/* RTCTCMP Control Bits */
+#define RTCTCMPS_H             (0x0080)       /* RTC Temperature Compensation Sign */
+#define RTCTCRDY_H             (0x0040)       /* RTC Temperature compensation ready */
+#define RTCTCOK_H              (0x0020)       /* RTC Temperature compensation write OK */
+
+#define RTCAE                  (0x80)         /* Real Time Clock Alarm enable */
+
+/* RTCPS0CTL Control Bits */
+//#define Reserved          (0x8000)
+//#define Reserved          (0x4000)
+#define RT0PSDIV2              (0x2000)       /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
+#define RT0PSDIV1              (0x1000)       /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
+#define RT0PSDIV0              (0x0800)       /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
+//#define Reserved          (0x0400)
+//#define Reserved          (0x0200)
+#define RT0PSHOLD              (0x0100)       /* RTC Prescale Timer 0 Hold */
+//#define Reserved          (0x0080)
+//#define Reserved          (0x0040)
+//#define Reserved          (0x0020)
+#define RT0IP2                 (0x0010)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
+#define RT0IP1                 (0x0008)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
+#define RT0IP0                 (0x0004)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
+#define RT0PSIE                (0x0002)       /* RTC Prescale Timer 0 Interrupt Enable Flag */
+#define RT0PSIFG               (0x0001)       /* RTC Prescale Timer 0 Interrupt Flag */
+
+/* RTCPS0CTL Control Bits */
+//#define Reserved          (0x8000)
+//#define Reserved          (0x4000)
+//#define Reserved          (0x0400)
+//#define Reserved          (0x0200)
+//#define Reserved          (0x0080)
+//#define Reserved          (0x0040)
+//#define Reserved          (0x0020)
+#define RT0IP2_L               (0x0010)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
+#define RT0IP1_L               (0x0008)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
+#define RT0IP0_L               (0x0004)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
+#define RT0PSIE_L              (0x0002)       /* RTC Prescale Timer 0 Interrupt Enable Flag */
+#define RT0PSIFG_L             (0x0001)       /* RTC Prescale Timer 0 Interrupt Flag */
+
+/* RTCPS0CTL Control Bits */
+//#define Reserved          (0x8000)
+//#define Reserved          (0x4000)
+#define RT0PSDIV2_H            (0x0020)       /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
+#define RT0PSDIV1_H            (0x0010)       /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
+#define RT0PSDIV0_H            (0x0008)       /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
+//#define Reserved          (0x0400)
+//#define Reserved          (0x0200)
+#define RT0PSHOLD_H            (0x0001)       /* RTC Prescale Timer 0 Hold */
+//#define Reserved          (0x0080)
+//#define Reserved          (0x0040)
+//#define Reserved          (0x0020)
+
+#define RT0IP_0                (0x0000)       /* RTC Prescale Timer 0 Interrupt Interval /2 */
+#define RT0IP_1                (0x0004)       /* RTC Prescale Timer 0 Interrupt Interval /4 */
+#define RT0IP_2                (0x0008)       /* RTC Prescale Timer 0 Interrupt Interval /8 */
+#define RT0IP_3                (0x000C)       /* RTC Prescale Timer 0 Interrupt Interval /16 */
+#define RT0IP_4                (0x0010)       /* RTC Prescale Timer 0 Interrupt Interval /32 */
+#define RT0IP_5                (0x0014)       /* RTC Prescale Timer 0 Interrupt Interval /64 */
+#define RT0IP_6                (0x0018)       /* RTC Prescale Timer 0 Interrupt Interval /128 */
+#define RT0IP_7                (0x001C)       /* RTC Prescale Timer 0 Interrupt Interval /256 */
+
+#define RT0PSDIV_0             (0x0000)       /* RTC Prescale Timer 0 Clock Divide: /2 */
+#define RT0PSDIV_1             (0x0800)       /* RTC Prescale Timer 0 Clock Divide: /4 */
+#define RT0PSDIV_2             (0x1000)       /* RTC Prescale Timer 0 Clock Divide: /8 */
+#define RT0PSDIV_3             (0x1800)       /* RTC Prescale Timer 0 Clock Divide: /16 */
+#define RT0PSDIV_4             (0x2000)       /* RTC Prescale Timer 0 Clock Divide: /32 */
+#define RT0PSDIV_5             (0x2800)       /* RTC Prescale Timer 0 Clock Divide: /64 */
+#define RT0PSDIV_6             (0x3000)       /* RTC Prescale Timer 0 Clock Divide: /128 */
+#define RT0PSDIV_7             (0x3800)       /* RTC Prescale Timer 0 Clock Divide: /256 */
+
+/* RTCPS1CTL Control Bits */
+#define RT1SSEL1               (0x8000)       /* RTC Prescale Timer 1 Source Select Bit: 1 */
+#define RT1SSEL0               (0x4000)       /* RTC Prescale Timer 1 Source Select Bit: 0 */
+#define RT1PSDIV2              (0x2000)       /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
+#define RT1PSDIV1              (0x1000)       /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
+#define RT1PSDIV0              (0x0800)       /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
+//#define Reserved          (0x0400)
+//#define Reserved          (0x0200)
+#define RT1PSHOLD              (0x0100)       /* RTC Prescale Timer 1 Hold */
+//#define Reserved          (0x0080)
+//#define Reserved          (0x0040)
+//#define Reserved          (0x0020)
+#define RT1IP2                 (0x0010)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
+#define RT1IP1                 (0x0008)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
+#define RT1IP0                 (0x0004)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
+#define RT1PSIE                (0x0002)       /* RTC Prescale Timer 1 Interrupt Enable Flag */
+#define RT1PSIFG               (0x0001)       /* RTC Prescale Timer 1 Interrupt Flag */
+
+/* RTCPS1CTL Control Bits */
+//#define Reserved          (0x0400)
+//#define Reserved          (0x0200)
+//#define Reserved          (0x0080)
+//#define Reserved          (0x0040)
+//#define Reserved          (0x0020)
+#define RT1IP2_L               (0x0010)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
+#define RT1IP1_L               (0x0008)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
+#define RT1IP0_L               (0x0004)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
+#define RT1PSIE_L              (0x0002)       /* RTC Prescale Timer 1 Interrupt Enable Flag */
+#define RT1PSIFG_L             (0x0001)       /* RTC Prescale Timer 1 Interrupt Flag */
+
+/* RTCPS1CTL Control Bits */
+#define RT1SSEL1_H             (0x0080)       /* RTC Prescale Timer 1 Source Select Bit: 1 */
+#define RT1SSEL0_H             (0x0040)       /* RTC Prescale Timer 1 Source Select Bit: 0 */
+#define RT1PSDIV2_H            (0x0020)       /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
+#define RT1PSDIV1_H            (0x0010)       /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
+#define RT1PSDIV0_H            (0x0008)       /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
+//#define Reserved          (0x0400)
+//#define Reserved          (0x0200)
+#define RT1PSHOLD_H            (0x0001)       /* RTC Prescale Timer 1 Hold */
+//#define Reserved          (0x0080)
+//#define Reserved          (0x0040)
+//#define Reserved          (0x0020)
+
+#define RT1IP_0                (0x0000)       /* RTC Prescale Timer 1 Interrupt Interval /2 */
+#define RT1IP_1                (0x0004)       /* RTC Prescale Timer 1 Interrupt Interval /4 */
+#define RT1IP_2                (0x0008)       /* RTC Prescale Timer 1 Interrupt Interval /8 */
+#define RT1IP_3                (0x000C)       /* RTC Prescale Timer 1 Interrupt Interval /16 */
+#define RT1IP_4                (0x0010)       /* RTC Prescale Timer 1 Interrupt Interval /32 */
+#define RT1IP_5                (0x0014)       /* RTC Prescale Timer 1 Interrupt Interval /64 */
+#define RT1IP_6                (0x0018)       /* RTC Prescale Timer 1 Interrupt Interval /128 */
+#define RT1IP_7                (0x001C)       /* RTC Prescale Timer 1 Interrupt Interval /256 */
+
+#define RT1PSDIV_0             (0x0000)       /* RTC Prescale Timer 1 Clock Divide: /2 */
+#define RT1PSDIV_1             (0x0800)       /* RTC Prescale Timer 1 Clock Divide: /4 */
+#define RT1PSDIV_2             (0x1000)       /* RTC Prescale Timer 1 Clock Divide: /8 */
+#define RT1PSDIV_3             (0x1800)       /* RTC Prescale Timer 1 Clock Divide: /16 */
+#define RT1PSDIV_4             (0x2000)       /* RTC Prescale Timer 1 Clock Divide: /32 */
+#define RT1PSDIV_5             (0x2800)       /* RTC Prescale Timer 1 Clock Divide: /64 */
+#define RT1PSDIV_6             (0x3000)       /* RTC Prescale Timer 1 Clock Divide: /128 */
+#define RT1PSDIV_7             (0x3800)       /* RTC Prescale Timer 1 Clock Divide: /256 */
+
+#define RT1SSEL_0              (0x0000)       /* RTC Prescale Timer 1 Source Select: 0 */
+#define RT1SSEL_1              (0x4000)       /* RTC Prescale Timer 1 Source Select: 1 */
+#define RT1SSEL_2              (0x8000)       /* RTC Prescale Timer 1 Source Select: 2 */
+#define RT1SSEL_3              (0xC000)       /* RTC Prescale Timer 1 Source Select: 3 */
+
+/* RTC Definitions */
+#define RTCIV_NONE             (0x0000)       /* No Interrupt pending */
+#define RTCIV_RTCOFIFG         (0x0002)       /* RTC Osc fault: RTCOFIFG */
+#define RTCIV_RTCRDYIFG        (0x0004)       /* RTC ready: RTCRDYIFG */
+#define RTCIV_RTCTEVIFG        (0x0006)       /* RTC interval timer: RTCTEVIFG */
+#define RTCIV_RTCAIFG          (0x0008)       /* RTC user alarm: RTCAIFG */
+#define RTCIV_RT0PSIFG         (0x000A)       /* RTC prescaler 0: RT0PSIFG */
+#define RTCIV_RT1PSIFG         (0x000C)       /* RTC prescaler 1: RT1PSIFG */
+
+/* Legacy Definitions */
+#define RTC_NONE               (0x0000)       /* No Interrupt pending */
+#define RTC_RTCOFIFG           (0x0002)       /* RTC Osc fault: RTCOFIFG */
+#define RTC_RTCRDYIFG          (0x0004)       /* RTC ready: RTCRDYIFG */
+#define RTC_RTCTEVIFG          (0x0006)       /* RTC interval timer: RTCTEVIFG */
+#define RTC_RTCAIFG            (0x0008)       /* RTC user alarm: RTCAIFG */
+#define RTC_RT0PSIFG           (0x000A)       /* RTC prescaler 0: RT0PSIFG */
+#define RTC_RT1PSIFG           (0x000C)       /* RTC prescaler 1: RT1PSIFG */
+
+/************************************************************
+* SFR - Special Function Register Module
+************************************************************/
+#define __MSP430_HAS_SFR__                    /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_SFR__ 0x0100
+#define SFR_BASE               __MSP430_BASEADDRESS_SFR__
+
+sfr_w(SFRIE1);                                /* Interrupt Enable 1 */
+sfr_b(SFRIE1_L);                              /* Interrupt Enable 1 */
+sfr_b(SFRIE1_H);                              /* Interrupt Enable 1 */
+
+/* SFRIE1 Control Bits */
+#define WDTIE                  (0x0001)       /* WDT Interrupt Enable */
+#define OFIE                   (0x0002)       /* Osc Fault Enable */
+//#define Reserved          (0x0004)
+#define VMAIE                  (0x0008)       /* Vacant Memory Interrupt Enable */
+#define NMIIE                  (0x0010)       /* NMI Interrupt Enable */
+#define JMBINIE                (0x0040)       /* JTAG Mail Box input Interrupt Enable */
+#define JMBOUTIE               (0x0080)       /* JTAG Mail Box output Interrupt Enable */
+
+#define WDTIE_L                (0x0001)       /* WDT Interrupt Enable */
+#define OFIE_L                 (0x0002)       /* Osc Fault Enable */
+//#define Reserved          (0x0004)
+#define VMAIE_L                (0x0008)       /* Vacant Memory Interrupt Enable */
+#define NMIIE_L                (0x0010)       /* NMI Interrupt Enable */
+#define JMBINIE_L              (0x0040)       /* JTAG Mail Box input Interrupt Enable */
+#define JMBOUTIE_L             (0x0080)       /* JTAG Mail Box output Interrupt Enable */
+
+sfr_w(SFRIFG1);                               /* Interrupt Flag 1 */
+sfr_b(SFRIFG1_L);                             /* Interrupt Flag 1 */
+sfr_b(SFRIFG1_H);                             /* Interrupt Flag 1 */
+/* SFRIFG1 Control Bits */
+#define WDTIFG                 (0x0001)       /* WDT Interrupt Flag */
+#define OFIFG                  (0x0002)       /* Osc Fault Flag */
+//#define Reserved          (0x0004)
+#define VMAIFG                 (0x0008)       /* Vacant Memory Interrupt Flag */
+#define NMIIFG                 (0x0010)       /* NMI Interrupt Flag */
+//#define Reserved          (0x0020)
+#define JMBINIFG               (0x0040)       /* JTAG Mail Box input Interrupt Flag */
+#define JMBOUTIFG              (0x0080)       /* JTAG Mail Box output Interrupt Flag */
+
+#define WDTIFG_L               (0x0001)       /* WDT Interrupt Flag */
+#define OFIFG_L                (0x0002)       /* Osc Fault Flag */
+//#define Reserved          (0x0004)
+#define VMAIFG_L               (0x0008)       /* Vacant Memory Interrupt Flag */
+#define NMIIFG_L               (0x0010)       /* NMI Interrupt Flag */
+//#define Reserved          (0x0020)
+#define JMBINIFG_L             (0x0040)       /* JTAG Mail Box input Interrupt Flag */
+#define JMBOUTIFG_L            (0x0080)       /* JTAG Mail Box output Interrupt Flag */
+
+sfr_w(SFRRPCR);                               /* RESET Pin Control Register */
+sfr_b(SFRRPCR_L);                             /* RESET Pin Control Register */
+sfr_b(SFRRPCR_H);                             /* RESET Pin Control Register */
+/* SFRRPCR Control Bits */
+#define SYSNMI                 (0x0001)       /* NMI select */
+#define SYSNMIIES              (0x0002)       /* NMI edge select */
+#define SYSRSTUP               (0x0004)       /* RESET Pin pull down/up select */
+#define SYSRSTRE               (0x0008)       /* RESET Pin Resistor enable */
+
+#define SYSNMI_L               (0x0001)       /* NMI select */
+#define SYSNMIIES_L            (0x0002)       /* NMI edge select */
+#define SYSRSTUP_L             (0x0004)       /* RESET Pin pull down/up select */
+#define SYSRSTRE_L             (0x0008)       /* RESET Pin Resistor enable */
+
+/************************************************************
+* SYS - System Module
+************************************************************/
+#define __MSP430_HAS_SYS__                    /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_SYS__ 0x0180
+#define SYS_BASE               __MSP430_BASEADDRESS_SYS__
+
+sfr_w(SYSCTL);                                /* System control */
+sfr_b(SYSCTL_L);                              /* System control */
+sfr_b(SYSCTL_H);                              /* System control */
+sfr_w(SYSJMBC);                               /* JTAG mailbox control */
+sfr_b(SYSJMBC_L);                             /* JTAG mailbox control */
+sfr_b(SYSJMBC_H);                             /* JTAG mailbox control */
+sfr_w(SYSJMBI0);                              /* JTAG mailbox input 0 */
+sfr_b(SYSJMBI0_L);                            /* JTAG mailbox input 0 */
+sfr_b(SYSJMBI0_H);                            /* JTAG mailbox input 0 */
+sfr_w(SYSJMBI1);                              /* JTAG mailbox input 1 */
+sfr_b(SYSJMBI1_L);                            /* JTAG mailbox input 1 */
+sfr_b(SYSJMBI1_H);                            /* JTAG mailbox input 1 */
+sfr_w(SYSJMBO0);                              /* JTAG mailbox output 0 */
+sfr_b(SYSJMBO0_L);                            /* JTAG mailbox output 0 */
+sfr_b(SYSJMBO0_H);                            /* JTAG mailbox output 0 */
+sfr_w(SYSJMBO1);                              /* JTAG mailbox output 1 */
+sfr_b(SYSJMBO1_L);                            /* JTAG mailbox output 1 */
+sfr_b(SYSJMBO1_H);                            /* JTAG mailbox output 1 */
+
+sfr_w(SYSUNIV);                               /* User NMI vector generator */
+sfr_b(SYSUNIV_L);                             /* User NMI vector generator */
+sfr_b(SYSUNIV_H);                             /* User NMI vector generator */
+sfr_w(SYSSNIV);                               /* System NMI vector generator */
+sfr_b(SYSSNIV_L);                             /* System NMI vector generator */
+sfr_b(SYSSNIV_H);                             /* System NMI vector generator */
+sfr_w(SYSRSTIV);                              /* Reset vector generator */
+sfr_b(SYSRSTIV_L);                            /* Reset vector generator */
+sfr_b(SYSRSTIV_H);                            /* Reset vector generator */
+
+/* SYSCTL Control Bits */
+#define SYSRIVECT              (0x0001)       /* SYS - RAM based interrupt vectors */
+//#define RESERVED            (0x0002)  /* SYS - Reserved */
+#define SYSPMMPE               (0x0004)       /* SYS - PMM access protect */
+//#define RESERVED            (0x0008)  /* SYS - Reserved */
+#define SYSBSLIND              (0x0010)       /* SYS - TCK/RST indication detected */
+#define SYSJTAGPIN             (0x0020)       /* SYS - Dedicated JTAG pins enabled */
+//#define RESERVED            (0x0040)  /* SYS - Reserved */
+//#define RESERVED            (0x0080)  /* SYS - Reserved */
+//#define RESERVED            (0x0100)  /* SYS - Reserved */
+//#define RESERVED            (0x0200)  /* SYS - Reserved */
+//#define RESERVED            (0x0400)  /* SYS - Reserved */
+//#define RESERVED            (0x0800)  /* SYS - Reserved */
+//#define RESERVED            (0x1000)  /* SYS - Reserved */
+//#define RESERVED            (0x2000)  /* SYS - Reserved */
+//#define RESERVED            (0x4000)  /* SYS - Reserved */
+//#define RESERVED            (0x8000)  /* SYS - Reserved */
+
+/* SYSCTL Control Bits */
+#define SYSRIVECT_L            (0x0001)       /* SYS - RAM based interrupt vectors */
+//#define RESERVED            (0x0002)  /* SYS - Reserved */
+#define SYSPMMPE_L             (0x0004)       /* SYS - PMM access protect */
+//#define RESERVED            (0x0008)  /* SYS - Reserved */
+#define SYSBSLIND_L            (0x0010)       /* SYS - TCK/RST indication detected */
+#define SYSJTAGPIN_L           (0x0020)       /* SYS - Dedicated JTAG pins enabled */
+//#define RESERVED            (0x0040)  /* SYS - Reserved */
+//#define RESERVED            (0x0080)  /* SYS - Reserved */
+//#define RESERVED            (0x0100)  /* SYS - Reserved */
+//#define RESERVED            (0x0200)  /* SYS - Reserved */
+//#define RESERVED            (0x0400)  /* SYS - Reserved */
+//#define RESERVED            (0x0800)  /* SYS - Reserved */
+//#define RESERVED            (0x1000)  /* SYS - Reserved */
+//#define RESERVED            (0x2000)  /* SYS - Reserved */
+//#define RESERVED            (0x4000)  /* SYS - Reserved */
+//#define RESERVED            (0x8000)  /* SYS - Reserved */
+
+/* SYSJMBC Control Bits */
+#define JMBIN0FG               (0x0001)       /* SYS - Incoming JTAG Mailbox 0 Flag */
+#define JMBIN1FG               (0x0002)       /* SYS - Incoming JTAG Mailbox 1 Flag */
+#define JMBOUT0FG              (0x0004)       /* SYS - Outgoing JTAG Mailbox 0 Flag */
+#define JMBOUT1FG              (0x0008)       /* SYS - Outgoing JTAG Mailbox 1 Flag */
+#define JMBMODE                (0x0010)       /* SYS - JMB 16/32 Bit Mode */
+//#define RESERVED            (0x0020)  /* SYS - Reserved */
+#define JMBCLR0OFF             (0x0040)       /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
+#define JMBCLR1OFF             (0x0080)       /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
+//#define RESERVED            (0x0100)  /* SYS - Reserved */
+//#define RESERVED            (0x0200)  /* SYS - Reserved */
+//#define RESERVED            (0x0400)  /* SYS - Reserved */
+//#define RESERVED            (0x0800)  /* SYS - Reserved */
+//#define RESERVED            (0x1000)  /* SYS - Reserved */
+//#define RESERVED            (0x2000)  /* SYS - Reserved */
+//#define RESERVED            (0x4000)  /* SYS - Reserved */
+//#define RESERVED            (0x8000)  /* SYS - Reserved */
+
+/* SYSJMBC Control Bits */
+#define JMBIN0FG_L             (0x0001)       /* SYS - Incoming JTAG Mailbox 0 Flag */
+#define JMBIN1FG_L             (0x0002)       /* SYS - Incoming JTAG Mailbox 1 Flag */
+#define JMBOUT0FG_L            (0x0004)       /* SYS - Outgoing JTAG Mailbox 0 Flag */
+#define JMBOUT1FG_L            (0x0008)       /* SYS - Outgoing JTAG Mailbox 1 Flag */
+#define JMBMODE_L              (0x0010)       /* SYS - JMB 16/32 Bit Mode */
+//#define RESERVED            (0x0020)  /* SYS - Reserved */
+#define JMBCLR0OFF_L           (0x0040)       /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
+#define JMBCLR1OFF_L           (0x0080)       /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
+//#define RESERVED            (0x0100)  /* SYS - Reserved */
+//#define RESERVED            (0x0200)  /* SYS - Reserved */
+//#define RESERVED            (0x0400)  /* SYS - Reserved */
+//#define RESERVED            (0x0800)  /* SYS - Reserved */
+//#define RESERVED            (0x1000)  /* SYS - Reserved */
+//#define RESERVED            (0x2000)  /* SYS - Reserved */
+//#define RESERVED            (0x4000)  /* SYS - Reserved */
+//#define RESERVED            (0x8000)  /* SYS - Reserved */
+
+
+/* SYSUNIV Definitions */
+#define SYSUNIV_NONE           (0x0000)       /* No Interrupt pending */
+#define SYSUNIV_NMIIFG         (0x0002)       /* SYSUNIV : NMIIFG */
+#define SYSUNIV_OFIFG          (0x0004)       /* SYSUNIV : Osc. Fail - OFIFG */
+
+/* SYSSNIV Definitions */
+#define SYSSNIV_NONE           (0x0000)       /* No Interrupt pending */
+#define SYSSNIV_RES02          (0x0002)       /* SYSSNIV : Reserved */
+#define SYSSNIV_UBDIFG         (0x0004)       /* SYSSNIV : FRAM Uncorrectable bit Error */
+#define SYSSNIV_RES06          (0x0006)       /* SYSSNIV : Reserved */
+#define SYSSNIV_MPUSEGPIFG     (0x0008)       /* SYSSNIV : MPUSEGPIFG violation */
+#define SYSSNIV_MPUSEGIIFG     (0x000A)       /* SYSSNIV : MPUSEGIIFG violation */
+#define SYSSNIV_MPUSEG1IFG     (0x000C)       /* SYSSNIV : MPUSEG1IFG violation */
+#define SYSSNIV_MPUSEG2IFG     (0x000E)       /* SYSSNIV : MPUSEG2IFG violation */
+#define SYSSNIV_MPUSEG3IFG     (0x0010)       /* SYSSNIV : MPUSEG3IFG violation */
+#define SYSSNIV_VMAIFG         (0x0012)       /* SYSSNIV : VMAIFG */
+#define SYSSNIV_JMBINIFG       (0x0014)       /* SYSSNIV : JMBINIFG */
+#define SYSSNIV_JMBOUTIFG      (0x0016)       /* SYSSNIV : JMBOUTIFG */
+#define SYSSNIV_CBDIFG         (0x0018)       /* SYSSNIV : FRAM Correctable Bit error */
+
+/* SYSRSTIV Definitions */
+#define SYSRSTIV_NONE          (0x0000)       /* No Interrupt pending */
+#define SYSRSTIV_BOR           (0x0002)       /* SYSRSTIV : BOR */
+#define SYSRSTIV_RSTNMI        (0x0004)       /* SYSRSTIV : RST/NMI */
+#define SYSRSTIV_DOBOR         (0x0006)       /* SYSRSTIV : Do BOR */
+#define SYSRSTIV_LPM5WU        (0x0008)       /* SYSRSTIV : Port LPM5 Wake Up */
+#define SYSRSTIV_SECYV         (0x000A)       /* SYSRSTIV : Security violation */
+#define SYSRSTIV_RES0C         (0x000C)       /* SYSRSTIV : Reserved */
+#define SYSRSTIV_SVSHIFG       (0x000E)       /* SYSRSTIV : SVSHIFG */
+#define SYSRSTIV_RES10         (0x0010)       /* SYSRSTIV : Reserved */
+#define SYSRSTIV_RES12         (0x0012)       /* SYSRSTIV : Reserved */
+#define SYSRSTIV_DOPOR         (0x0014)       /* SYSRSTIV : Do POR */
+#define SYSRSTIV_WDTTO         (0x0016)       /* SYSRSTIV : WDT Time out */
+#define SYSRSTIV_WDTKEY        (0x0018)       /* SYSRSTIV : WDTKEY violation */
+#define SYSRSTIV_FRCTLPW       (0x001A)       /* SYSRSTIV : FRAM Key violation */
+#define SYSRSTIV_UBDIFG        (0x001C)       /* SYSRSTIV : FRAM Uncorrectable bit Error */
+#define SYSRSTIV_PERF          (0x001E)       /* SYSRSTIV : peripheral/config area fetch */
+#define SYSRSTIV_PMMPW         (0x0020)       /* SYSRSTIV : PMM Password violation */
+#define SYSRSTIV_MPUPW         (0x0022)       /* SYSRSTIV : MPU Password violation */
+#define SYSRSTIV_CSPW          (0x0024)       /* SYSRSTIV : CS Password violation */
+#define SYSRSTIV_MPUSEGPIFG    (0x0026)       /* SYSRSTIV : MPUSEGPIFG violation */
+#define SYSRSTIV_MPUSEGIIFG    (0x0028)       /* SYSRSTIV : MPUSEGIIFG violation */
+#define SYSRSTIV_MPUSEG1IFG    (0x002A)       /* SYSRSTIV : MPUSEG1IFG violation */
+#define SYSRSTIV_MPUSEG2IFG    (0x002C)       /* SYSRSTIV : MPUSEG2IFG violation */
+#define SYSRSTIV_MPUSEG3IFG    (0x002E)       /* SYSRSTIV : MPUSEG3IFG violation */
+#define SYSRSTIV_ACCTEIFG      (0x0030)       /* SYSRSTIV : ACCTEIFG access time error */
+
+/************************************************************
+* Timer0_A3
+************************************************************/
+#define __MSP430_HAS_T0A3__                   /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_T0A3__ 0x0340
+#define TIMER_A0_BASE          __MSP430_BASEADDRESS_T0A3__
+
+sfr_w(TA0CTL);                                /* Timer0_A3 Control */
+sfr_w(TA0CCTL0);                              /* Timer0_A3 Capture/Compare Control 0 */
+sfr_w(TA0CCTL1);                              /* Timer0_A3 Capture/Compare Control 1 */
+sfr_w(TA0CCTL2);                              /* Timer0_A3 Capture/Compare Control 2 */
+sfr_w(TA0R);                                  /* Timer0_A3 */
+sfr_w(TA0CCR0);                               /* Timer0_A3 Capture/Compare 0 */
+sfr_w(TA0CCR1);                               /* Timer0_A3 Capture/Compare 1 */
+sfr_w(TA0CCR2);                               /* Timer0_A3 Capture/Compare 2 */
+sfr_w(TA0IV);                                 /* Timer0_A3 Interrupt Vector Word */
+sfr_w(TA0EX0);                                /* Timer0_A3 Expansion Register 0 */
+
+/* TAxCTL Control Bits */
+#define TASSEL1                (0x0200)       /* Timer A clock source select 1 */
+#define TASSEL0                (0x0100)       /* Timer A clock source select 0 */
+#define ID1                    (0x0080)       /* Timer A clock input divider 1 */
+#define ID0                    (0x0040)       /* Timer A clock input divider 0 */
+#define MC1                    (0x0020)       /* Timer A mode control 1 */
+#define MC0                    (0x0010)       /* Timer A mode control 0 */
+#define TACLR                  (0x0004)       /* Timer A counter clear */
+#define TAIE                   (0x0002)       /* Timer A counter interrupt enable */
+#define TAIFG                  (0x0001)       /* Timer A counter interrupt flag */
+
+#define MC_0                   (0x0000)       /* Timer A mode control: 0 - Stop */
+#define MC_1                   (0x0010)       /* Timer A mode control: 1 - Up to CCR0 */
+#define MC_2                   (0x0020)       /* Timer A mode control: 2 - Continuous up */
+#define MC_3                   (0x0030)       /* Timer A mode control: 3 - Up/Down */
+#define ID_0                   (0x0000)       /* Timer A input divider: 0 - /1 */
+#define ID_1                   (0x0040)       /* Timer A input divider: 1 - /2 */
+#define ID_2                   (0x0080)       /* Timer A input divider: 2 - /4 */
+#define ID_3                   (0x00C0)       /* Timer A input divider: 3 - /8 */
+#define TASSEL_0               (0x0000)       /* Timer A clock source select: 0 - TACLK */
+#define TASSEL_1               (0x0100)       /* Timer A clock source select: 1 - ACLK  */
+#define TASSEL_2               (0x0200)       /* Timer A clock source select: 2 - SMCLK */
+#define TASSEL_3               (0x0300)       /* Timer A clock source select: 3 - INCLK */
+#define MC__STOP               (0x0000)       /* Timer A mode control: 0 - Stop */
+#define MC__UP                 (0x0010)       /* Timer A mode control: 1 - Up to CCR0 */
+#define MC__CONTINUOUS         (0x0020)       /* Timer A mode control: 2 - Continuous up */
+#define MC__CONTINOUS          (0x0020)       /* Legacy define */
+#define MC__UPDOWN             (0x0030)       /* Timer A mode control: 3 - Up/Down */
+#define ID__1                  (0x0000)       /* Timer A input divider: 0 - /1 */
+#define ID__2                  (0x0040)       /* Timer A input divider: 1 - /2 */
+#define ID__4                  (0x0080)       /* Timer A input divider: 2 - /4 */
+#define ID__8                  (0x00C0)       /* Timer A input divider: 3 - /8 */
+#define TASSEL__TACLK          (0x0000)       /* Timer A clock source select: 0 - TACLK */
+#define TASSEL__ACLK           (0x0100)       /* Timer A clock source select: 1 - ACLK  */
+#define TASSEL__SMCLK          (0x0200)       /* Timer A clock source select: 2 - SMCLK */
+#define TASSEL__INCLK          (0x0300)       /* Timer A clock source select: 3 - INCLK */
+
+/* TAxCCTLx Control Bits */
+#define CM1                    (0x8000)       /* Capture mode 1 */
+#define CM0                    (0x4000)       /* Capture mode 0 */
+#define CCIS1                  (0x2000)       /* Capture input select 1 */
+#define CCIS0                  (0x1000)       /* Capture input select 0 */
+#define SCS                    (0x0800)       /* Capture sychronize */
+#define SCCI                   (0x0400)       /* Latched capture signal (read) */
+#define CAP                    (0x0100)       /* Capture mode: 1 /Compare mode : 0 */
+#define OUTMOD2                (0x0080)       /* Output mode 2 */
+#define OUTMOD1                (0x0040)       /* Output mode 1 */
+#define OUTMOD0                (0x0020)       /* Output mode 0 */
+#define CCIE                   (0x0010)       /* Capture/compare interrupt enable */
+#define CCI                    (0x0008)       /* Capture input signal (read) */
+#define OUT                    (0x0004)       /* PWM Output signal if output mode 0 */
+#define COV                    (0x0002)       /* Capture/compare overflow flag */
+#define CCIFG                  (0x0001)       /* Capture/compare interrupt flag */
+
+#define OUTMOD_0               (0x0000)       /* PWM output mode: 0 - output only */
+#define OUTMOD_1               (0x0020)       /* PWM output mode: 1 - set */
+#define OUTMOD_2               (0x0040)       /* PWM output mode: 2 - PWM toggle/reset */
+#define OUTMOD_3               (0x0060)       /* PWM output mode: 3 - PWM set/reset */
+#define OUTMOD_4               (0x0080)       /* PWM output mode: 4 - toggle */
+#define OUTMOD_5               (0x00A0)       /* PWM output mode: 5 - Reset */
+#define OUTMOD_6               (0x00C0)       /* PWM output mode: 6 - PWM toggle/set */
+#define OUTMOD_7               (0x00E0)       /* PWM output mode: 7 - PWM reset/set */
+#define CCIS_0                 (0x0000)       /* Capture input select: 0 - CCIxA */
+#define CCIS_1                 (0x1000)       /* Capture input select: 1 - CCIxB */
+#define CCIS_2                 (0x2000)       /* Capture input select: 2 - GND */
+#define CCIS_3                 (0x3000)       /* Capture input select: 3 - Vcc */
+#define CM_0                   (0x0000)       /* Capture mode: 0 - disabled */
+#define CM_1                   (0x4000)       /* Capture mode: 1 - pos. edge */
+#define CM_2                   (0x8000)       /* Capture mode: 1 - neg. edge */
+#define CM_3                   (0xC000)       /* Capture mode: 1 - both edges */
+
+/* TAxEX0 Control Bits */
+#define TAIDEX0                (0x0001)       /* Timer A Input divider expansion Bit: 0 */
+#define TAIDEX1                (0x0002)       /* Timer A Input divider expansion Bit: 1 */
+#define TAIDEX2                (0x0004)       /* Timer A Input divider expansion Bit: 2 */
+
+#define TAIDEX_0               (0x0000)       /* Timer A Input divider expansion : /1 */
+#define TAIDEX_1               (0x0001)       /* Timer A Input divider expansion : /2 */
+#define TAIDEX_2               (0x0002)       /* Timer A Input divider expansion : /3 */
+#define TAIDEX_3               (0x0003)       /* Timer A Input divider expansion : /4 */
+#define TAIDEX_4               (0x0004)       /* Timer A Input divider expansion : /5 */
+#define TAIDEX_5               (0x0005)       /* Timer A Input divider expansion : /6 */
+#define TAIDEX_6               (0x0006)       /* Timer A Input divider expansion : /7 */
+#define TAIDEX_7               (0x0007)       /* Timer A Input divider expansion : /8 */
+
+/* T0A3IV Definitions */
+#define TA0IV_NONE             (0x0000)       /* No Interrupt pending */
+#define TA0IV_TACCR1           (0x0002)       /* TA0CCR1_CCIFG */
+#define TA0IV_TACCR2           (0x0004)       /* TA0CCR2_CCIFG */
+#define TA0IV_3                (0x0006)       /* Reserved */
+#define TA0IV_4                (0x0008)       /* Reserved */
+#define TA0IV_5                (0x000A)       /* Reserved */
+#define TA0IV_6                (0x000C)       /* Reserved */
+#define TA0IV_TAIFG            (0x000E)       /* TA0IFG */
+
+/* Legacy Defines */
+#define TA0IV_TA0CCR1          (0x0002)       /* TA0CCR1_CCIFG */
+#define TA0IV_TA0CCR2          (0x0004)       /* TA0CCR2_CCIFG */
+#define TA0IV_TA0IFG           (0x000E)       /* TA0IFG */
+
+/************************************************************
+* Timer1_A3
+************************************************************/
+#define __MSP430_HAS_T1A3__                   /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_T1A3__ 0x0380
+#define TIMER_A1_BASE          __MSP430_BASEADDRESS_T1A3__
+
+sfr_w(TA1CTL);                                /* Timer1_A3 Control */
+sfr_w(TA1CCTL0);                              /* Timer1_A3 Capture/Compare Control 0 */
+sfr_w(TA1CCTL1);                              /* Timer1_A3 Capture/Compare Control 1 */
+sfr_w(TA1CCTL2);                              /* Timer1_A3 Capture/Compare Control 2 */
+sfr_w(TA1R);                                  /* Timer1_A3 */
+sfr_w(TA1CCR0);                               /* Timer1_A3 Capture/Compare 0 */
+sfr_w(TA1CCR1);                               /* Timer1_A3 Capture/Compare 1 */
+sfr_w(TA1CCR2);                               /* Timer1_A3 Capture/Compare 2 */
+sfr_w(TA1IV);                                 /* Timer1_A3 Interrupt Vector Word */
+sfr_w(TA1EX0);                                /* Timer1_A3 Expansion Register 0 */
+
+/* Bits are already defined within the Timer0_Ax */
+
+/* TA1IV Definitions */
+#define TA1IV_NONE             (0x0000)       /* No Interrupt pending */
+#define TA1IV_TACCR1           (0x0002)       /* TA1CCR1_CCIFG */
+#define TA1IV_TACCR2           (0x0004)       /* TA1CCR2_CCIFG */
+#define TA1IV_3                (0x0006)       /* Reserved */
+#define TA1IV_4                (0x0008)       /* Reserved */
+#define TA1IV_5                (0x000A)       /* Reserved */
+#define TA1IV_6                (0x000C)       /* Reserved */
+#define TA1IV_TAIFG            (0x000E)       /* TA1IFG */
+
+/* Legacy Defines */
+#define TA1IV_TA1CCR1          (0x0002)       /* TA1CCR1_CCIFG */
+#define TA1IV_TA1CCR2          (0x0004)       /* TA1CCR2_CCIFG */
+#define TA1IV_TA1IFG           (0x000E)       /* TA1IFG */
+
+/************************************************************
+* Timer2_A2
+************************************************************/
+#define __MSP430_HAS_T2A2__                   /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_T2A2__ 0x0400
+#define TIMER_A2_BASE          __MSP430_BASEADDRESS_T2A2__
+
+sfr_w(TA2CTL);                                /* Timer2_A2 Control */
+sfr_w(TA2CCTL0);                              /* Timer2_A2 Capture/Compare Control 0 */
+sfr_w(TA2CCTL1);                              /* Timer2_A2 Capture/Compare Control 1 */
+sfr_w(TA2R);                                  /* Timer2_A2 */
+sfr_w(TA2CCR0);                               /* Timer2_A2 Capture/Compare 0 */
+sfr_w(TA2CCR1);                               /* Timer2_A2 Capture/Compare 1 */
+sfr_w(TA2IV);                                 /* Timer2_A2 Interrupt Vector Word */
+sfr_w(TA2EX0);                                /* Timer2_A2 Expansion Register 0 */
+
+/* Bits are already defined within the Timer0_Ax */
+
+/* TA2IV Definitions */
+#define TA2IV_NONE             (0x0000)       /* No Interrupt pending */
+#define TA2IV_TACCR1           (0x0002)       /* TA2CCR1_CCIFG */
+#define TA2IV_3                (0x0006)       /* Reserved */
+#define TA2IV_4                (0x0008)       /* Reserved */
+#define TA2IV_5                (0x000A)       /* Reserved */
+#define TA2IV_6                (0x000C)       /* Reserved */
+#define TA2IV_TAIFG            (0x000E)       /* TA2IFG */
+
+/* Legacy Defines */
+#define TA2IV_TA2CCR1          (0x0002)       /* TA2CCR1_CCIFG */
+#define TA2IV_TA2IFG           (0x000E)       /* TA2IFG */
+
+/************************************************************
+* Timer3_A5
+************************************************************/
+#define __MSP430_HAS_T3A5__                   /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_T3A5__ 0x0440
+#define TIMER_A3_BASE          __MSP430_BASEADDRESS_T3A5__
+
+sfr_w(TA3CTL);                                /* Timer3_A5 Control */
+sfr_w(TA3CCTL0);                              /* Timer3_A5 Capture/Compare Control 0 */
+sfr_w(TA3CCTL1);                              /* Timer3_A5 Capture/Compare Control 1 */
+sfr_w(TA3CCTL2);                              /* Timer3_A5 Capture/Compare Control 2 */
+sfr_w(TA3CCTL3);                              /* Timer3_A5 Capture/Compare Control 3 */
+sfr_w(TA3CCTL4);                              /* Timer3_A5 Capture/Compare Control 4 */
+sfr_w(TA3R);                                  /* Timer3_A5 */
+sfr_w(TA3CCR0);                               /* Timer3_A5 Capture/Compare 0 */
+sfr_w(TA3CCR1);                               /* Timer3_A5 Capture/Compare 1 */
+sfr_w(TA3CCR2);                               /* Timer3_A5 Capture/Compare 2 */
+sfr_w(TA3CCR3);                               /* Timer3_A5 Capture/Compare 3 */
+sfr_w(TA3CCR4);                               /* Timer3_A5 Capture/Compare 4 */
+sfr_w(TA3IV);                                 /* Timer3_A5 Interrupt Vector Word */
+sfr_w(TA3EX0);                                /* Timer3_A5 Expansion Register 0 */
+
+/* Bits are already defined within the Timer0_Ax */
+
+/* TA3IV Definitions */
+#define TA3IV_NONE             (0x0000)       /* No Interrupt pending */
+#define TA3IV_TACCR1           (0x0002)       /* TA3CCR1_CCIFG */
+#define TA3IV_TACCR2           (0x0004)       /* TA3CCR2_CCIFG */
+#define TA3IV_TACCR3           (0x0006)       /* TA3CCR3_CCIFG */
+#define TA3IV_TACCR4           (0x0008)       /* TA3CCR4_CCIFG */
+#define TA3IV_TAIFG            (0x000E)       /* TA3IFG */
+
+/* Legacy Defines */
+#define TA3IV_TA3CCR1          (0x0002)       /* TA3CCR1_CCIFG */
+#define TA3IV_TA3CCR2          (0x0004)       /* TA3CCR2_CCIFG */
+#define TA3IV_TA3CCR3          (0x0006)       /* TA3CCR3_CCIFG */
+#define TA3IV_TA3CCR4          (0x0008)       /* TA3CCR4_CCIFG */
+#define TA3IV_TA3IFG           (0x000E)       /* TA3IFG */
+
+/************************************************************
+* Timer0_B7
+************************************************************/
+#define __MSP430_HAS_T0B7__                   /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_T0B7__ 0x03C0
+#define TIMER_B0_BASE          __MSP430_BASEADDRESS_T0B7__
+
+sfr_w(TB0CTL);                                /* Timer0_B7 Control */
+sfr_w(TB0CCTL0);                              /* Timer0_B7 Capture/Compare Control 0 */
+sfr_w(TB0CCTL1);                              /* Timer0_B7 Capture/Compare Control 1 */
+sfr_w(TB0CCTL2);                              /* Timer0_B7 Capture/Compare Control 2 */
+sfr_w(TB0CCTL3);                              /* Timer0_B7 Capture/Compare Control 3 */
+sfr_w(TB0CCTL4);                              /* Timer0_B7 Capture/Compare Control 4 */
+sfr_w(TB0CCTL5);                              /* Timer0_B7 Capture/Compare Control 5 */
+sfr_w(TB0CCTL6);                              /* Timer0_B7 Capture/Compare Control 6 */
+sfr_w(TB0R);                                  /* Timer0_B7 */
+sfr_w(TB0CCR0);                               /* Timer0_B7 Capture/Compare 0 */
+sfr_w(TB0CCR1);                               /* Timer0_B7 Capture/Compare 1 */
+sfr_w(TB0CCR2);                               /* Timer0_B7 Capture/Compare 2 */
+sfr_w(TB0CCR3);                               /* Timer0_B7 Capture/Compare 3 */
+sfr_w(TB0CCR4);                               /* Timer0_B7 Capture/Compare 4 */
+sfr_w(TB0CCR5);                               /* Timer0_B7 Capture/Compare 5 */
+sfr_w(TB0CCR6);                               /* Timer0_B7 Capture/Compare 6 */
+sfr_w(TB0EX0);                                /* Timer0_B7 Expansion Register 0 */
+sfr_w(TB0IV);                                 /* Timer0_B7 Interrupt Vector Word */
+
+/* Legacy Type Definitions for TimerB */
+#define TBCTL                  TB0CTL         /* Timer0_B7 Control */
+#define TBCCTL0                TB0CCTL0       /* Timer0_B7 Capture/Compare Control 0 */
+#define TBCCTL1                TB0CCTL1       /* Timer0_B7 Capture/Compare Control 1 */
+#define TBCCTL2                TB0CCTL2       /* Timer0_B7 Capture/Compare Control 2 */
+#define TBCCTL3                TB0CCTL3       /* Timer0_B7 Capture/Compare Control 3 */
+#define TBCCTL4                TB0CCTL4       /* Timer0_B7 Capture/Compare Control 4 */
+#define TBCCTL5                TB0CCTL5       /* Timer0_B7 Capture/Compare Control 5 */
+#define TBCCTL6                TB0CCTL6       /* Timer0_B7 Capture/Compare Control 6 */
+#define TBR                    TB0R           /* Timer0_B7 */
+#define TBCCR0                 TB0CCR0        /* Timer0_B7 Capture/Compare 0 */
+#define TBCCR1                 TB0CCR1        /* Timer0_B7 Capture/Compare 1 */
+#define TBCCR2                 TB0CCR2        /* Timer0_B7 Capture/Compare 2 */
+#define TBCCR3                 TB0CCR3        /* Timer0_B7 Capture/Compare 3 */
+#define TBCCR4                 TB0CCR4        /* Timer0_B7 Capture/Compare 4 */
+#define TBCCR5                 TB0CCR5        /* Timer0_B7 Capture/Compare 5 */
+#define TBCCR6                 TB0CCR6        /* Timer0_B7 Capture/Compare 6 */
+#define TBEX0                  TB0EX0         /* Timer0_B7 Expansion Register 0 */
+#define TBIV                   TB0IV          /* Timer0_B7 Interrupt Vector Word */
+#define TIMERB1_VECTOR       TIMER0_B1_VECTOR /* Timer0_B7 CC1-6, TB */
+#define TIMERB0_VECTOR       TIMER0_B0_VECTOR /* Timer0_B7 CC0 */
+
+/* TBxCTL Control Bits */
+#define TBCLGRP1               (0x4000)       /* Timer0_B7 Compare latch load group 1 */
+#define TBCLGRP0               (0x2000)       /* Timer0_B7 Compare latch load group 0 */
+#define CNTL1                  (0x1000)       /* Counter lenght 1 */
+#define CNTL0                  (0x0800)       /* Counter lenght 0 */
+#define TBSSEL1                (0x0200)       /* Clock source 1 */
+#define TBSSEL0                (0x0100)       /* Clock source 0 */
+#define TBCLR                  (0x0004)       /* Timer0_B7 counter clear */
+#define TBIE                   (0x0002)       /* Timer0_B7 interrupt enable */
+#define TBIFG                  (0x0001)       /* Timer0_B7 interrupt flag */
+
+#define SHR1                   (0x4000)       /* Timer0_B7 Compare latch load group 1 */
+#define SHR0                   (0x2000)       /* Timer0_B7 Compare latch load group 0 */
+
+#define TBSSEL_0               (0x0000)       /* Clock Source: TBCLK */
+#define TBSSEL_1               (0x0100)       /* Clock Source: ACLK  */
+#define TBSSEL_2               (0x0200)       /* Clock Source: SMCLK */
+#define TBSSEL_3               (0x0300)       /* Clock Source: INCLK */
+#define CNTL_0                 (0x0000)       /* Counter lenght: 16 bit */
+#define CNTL_1                 (0x0800)       /* Counter lenght: 12 bit */
+#define CNTL_2                 (0x1000)       /* Counter lenght: 10 bit */
+#define CNTL_3                 (0x1800)       /* Counter lenght:  8 bit */
+#define SHR_0                  (0x0000)       /* Timer0_B7 Group: 0 - individually */
+#define SHR_1                  (0x2000)       /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
+#define SHR_2                  (0x4000)       /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/
+#define SHR_3                  (0x6000)       /* Timer0_B7 Group: 3 - 1 group (all) */
+#define TBCLGRP_0              (0x0000)       /* Timer0_B7 Group: 0 - individually */
+#define TBCLGRP_1              (0x2000)       /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
+#define TBCLGRP_2              (0x4000)       /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/
+#define TBCLGRP_3              (0x6000)       /* Timer0_B7 Group: 3 - 1 group (all) */
+#define TBSSEL__TBCLK          (0x0000)       /* Timer0_B7 clock source select: 0 - TBCLK */
+#define TBSSEL__TACLK          (0x0000)       /* Timer0_B7 clock source select: 0 - TBCLK (legacy) */
+#define TBSSEL__ACLK           (0x0100)       /* Timer0_B7 clock source select: 1 - ACLK  */
+#define TBSSEL__SMCLK          (0x0200)       /* Timer0_B7 clock source select: 2 - SMCLK */
+#define TBSSEL__INCLK          (0x0300)       /* Timer0_B7 clock source select: 3 - INCLK */
+#define CNTL__16               (0x0000)       /* Counter lenght: 16 bit */
+#define CNTL__12               (0x0800)       /* Counter lenght: 12 bit */
+#define CNTL__10               (0x1000)       /* Counter lenght: 10 bit */
+#define CNTL__8                (0x1800)       /* Counter lenght:  8 bit */
+
+/* Additional Timer B Control Register bits are defined in Timer A */
+/* TBxCCTLx Control Bits */
+#define CLLD1                  (0x0400)       /* Compare latch load source 1 */
+#define CLLD0                  (0x0200)       /* Compare latch load source 0 */
+
+#define SLSHR1                 (0x0400)       /* Compare latch load source 1 */
+#define SLSHR0                 (0x0200)       /* Compare latch load source 0 */
+
+#define SLSHR_0                (0x0000)       /* Compare latch load sourec : 0 - immediate */
+#define SLSHR_1                (0x0200)       /* Compare latch load sourec : 1 - TBR counts to 0 */
+#define SLSHR_2                (0x0400)       /* Compare latch load sourec : 2 - up/down */
+#define SLSHR_3                (0x0600)       /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
+
+#define CLLD_0                 (0x0000)       /* Compare latch load sourec : 0 - immediate */
+#define CLLD_1                 (0x0200)       /* Compare latch load sourec : 1 - TBR counts to 0 */
+#define CLLD_2                 (0x0400)       /* Compare latch load sourec : 2 - up/down */
+#define CLLD_3                 (0x0600)       /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
+
+/* TBxEX0 Control Bits */
+#define TBIDEX0                (0x0001)       /* Timer0_B7 Input divider expansion Bit: 0 */
+#define TBIDEX1                (0x0002)       /* Timer0_B7 Input divider expansion Bit: 1 */
+#define TBIDEX2                (0x0004)       /* Timer0_B7 Input divider expansion Bit: 2 */
+
+#define TBIDEX_0               (0x0000)       /* Timer0_B7 Input divider expansion : /1 */
+#define TBIDEX_1               (0x0001)       /* Timer0_B7 Input divider expansion : /2 */
+#define TBIDEX_2               (0x0002)       /* Timer0_B7 Input divider expansion : /3 */
+#define TBIDEX_3               (0x0003)       /* Timer0_B7 Input divider expansion : /4 */
+#define TBIDEX_4               (0x0004)       /* Timer0_B7 Input divider expansion : /5 */
+#define TBIDEX_5               (0x0005)       /* Timer0_B7 Input divider expansion : /6 */
+#define TBIDEX_6               (0x0006)       /* Timer0_B7 Input divider expansion : /7 */
+#define TBIDEX_7               (0x0007)       /* Timer0_B7 Input divider expansion : /8 */
+#define TBIDEX__1              (0x0000)       /* Timer0_B7 Input divider expansion : /1 */
+#define TBIDEX__2              (0x0001)       /* Timer0_B7 Input divider expansion : /2 */
+#define TBIDEX__3              (0x0002)       /* Timer0_B7 Input divider expansion : /3 */
+#define TBIDEX__4              (0x0003)       /* Timer0_B7 Input divider expansion : /4 */
+#define TBIDEX__5              (0x0004)       /* Timer0_B7 Input divider expansion : /5 */
+#define TBIDEX__6              (0x0005)       /* Timer0_B7 Input divider expansion : /6 */
+#define TBIDEX__7              (0x0006)       /* Timer0_B7 Input divider expansion : /7 */
+#define TBIDEX__8              (0x0007)       /* Timer0_B7 Input divider expansion : /8 */
+
+/* TB0IV Definitions */
+#define TB0IV_NONE             (0x0000)       /* No Interrupt pending */
+#define TB0IV_TBCCR1           (0x0002)       /* TB0CCR1_CCIFG */
+#define TB0IV_TBCCR2           (0x0004)       /* TB0CCR2_CCIFG */
+#define TB0IV_TBCCR3           (0x0006)       /* TB0CCR3_CCIFG */
+#define TB0IV_TBCCR4           (0x0008)       /* TB0CCR4_CCIFG */
+#define TB0IV_TBCCR5           (0x000A)       /* TB0CCR5_CCIFG */
+#define TB0IV_TBCCR6           (0x000C)       /* TB0CCR6_CCIFG */
+#define TB0IV_TBIFG            (0x000E)       /* TB0IFG */
+
+/* Legacy Defines */
+#define TB0IV_TB0CCR1          (0x0002)       /* TB0CCR1_CCIFG */
+#define TB0IV_TB0CCR2          (0x0004)       /* TB0CCR2_CCIFG */
+#define TB0IV_TB0CCR3          (0x0006)       /* TB0CCR3_CCIFG */
+#define TB0IV_TB0CCR4          (0x0008)       /* TB0CCR4_CCIFG */
+#define TB0IV_TB0CCR5          (0x000A)       /* TB0CCR5_CCIFG */
+#define TB0IV_TB0CCR6          (0x000C)       /* TB0CCR6_CCIFG */
+#define TB0IV_TB0IFG           (0x000E)       /* TB0IFG */
+
+
+/************************************************************
+* USCI A0
+************************************************************/
+#define __MSP430_HAS_EUSCI_A0__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_EUSCI_A0__ 0x05C0
+#define EUSCI_A0_BASE          __MSP430_BASEADDRESS_EUSCI_A0__
+
+sfr_w(UCA0CTLW0);                             /* USCI A0 Control Word Register 0 */
+sfr_b(UCA0CTLW0_L);                           /* USCI A0 Control Word Register 0 */
+sfr_b(UCA0CTLW0_H);                           /* USCI A0 Control Word Register 0 */
+#define UCA0CTL1               UCA0CTLW0_L    /* USCI A0 Control Register 1 */
+#define UCA0CTL0               UCA0CTLW0_H    /* USCI A0 Control Register 0 */
+sfr_w(UCA0CTLW1);                             /* USCI A0 Control Word Register 1 */
+sfr_b(UCA0CTLW1_L);                           /* USCI A0 Control Word Register 1 */
+sfr_b(UCA0CTLW1_H);                           /* USCI A0 Control Word Register 1 */
+sfr_w(UCA0BRW);                               /* USCI A0 Baud Word Rate 0 */
+sfr_b(UCA0BRW_L);                             /* USCI A0 Baud Word Rate 0 */
+sfr_b(UCA0BRW_H);                             /* USCI A0 Baud Word Rate 0 */
+#define UCA0BR0                UCA0BRW_L      /* USCI A0 Baud Rate 0 */
+#define UCA0BR1                UCA0BRW_H      /* USCI A0 Baud Rate 1 */
+sfr_w(UCA0MCTLW);                             /* USCI A0 Modulation Control */
+sfr_b(UCA0MCTLW_L);                           /* USCI A0 Modulation Control */
+sfr_b(UCA0MCTLW_H);                           /* USCI A0 Modulation Control */
+sfr_b(UCA0STATW);                             /* USCI A0 Status Register */
+sfr_w(UCA0RXBUF);                             /* USCI A0 Receive Buffer */
+sfr_b(UCA0RXBUF_L);                           /* USCI A0 Receive Buffer */
+sfr_b(UCA0RXBUF_H);                           /* USCI A0 Receive Buffer */
+sfr_w(UCA0TXBUF);                             /* USCI A0 Transmit Buffer */
+sfr_b(UCA0TXBUF_L);                           /* USCI A0 Transmit Buffer */
+sfr_b(UCA0TXBUF_H);                           /* USCI A0 Transmit Buffer */
+sfr_b(UCA0ABCTL);                             /* USCI A0 LIN Control */
+sfr_w(UCA0IRCTL);                             /* USCI A0 IrDA Transmit Control */
+sfr_b(UCA0IRCTL_L);                           /* USCI A0 IrDA Transmit Control */
+sfr_b(UCA0IRCTL_H);                           /* USCI A0 IrDA Transmit Control */
+#define UCA0IRTCTL             UCA0IRCTL_L    /* USCI A0 IrDA Transmit Control */
+#define UCA0IRRCTL             UCA0IRCTL_H    /* USCI A0 IrDA Receive Control */
+sfr_w(UCA0IE);                                /* USCI A0 Interrupt Enable Register */
+sfr_b(UCA0IE_L);                              /* USCI A0 Interrupt Enable Register */
+sfr_b(UCA0IE_H);                              /* USCI A0 Interrupt Enable Register */
+sfr_w(UCA0IFG);                               /* USCI A0 Interrupt Flags Register */
+sfr_b(UCA0IFG_L);                             /* USCI A0 Interrupt Flags Register */
+sfr_b(UCA0IFG_H);                             /* USCI A0 Interrupt Flags Register */
+sfr_w(UCA0IV);                                /* USCI A0 Interrupt Vector Register */
+
+
+/************************************************************
+* USCI A1
+************************************************************/
+#define __MSP430_HAS_EUSCI_A1__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_EUSCI_A1__ 0x05E0
+#define EUSCI_A1_BASE          __MSP430_BASEADDRESS_EUSCI_A1__
+
+sfr_w(UCA1CTLW0);                             /* USCI A1 Control Word Register 0 */
+sfr_b(UCA1CTLW0_L);                           /* USCI A1 Control Word Register 0 */
+sfr_b(UCA1CTLW0_H);                           /* USCI A1 Control Word Register 0 */
+#define UCA1CTL1               UCA1CTLW0_L    /* USCI A1 Control Register 1 */
+#define UCA1CTL0               UCA1CTLW0_H    /* USCI A1 Control Register 0 */
+sfr_w(UCA1CTLW1);                             /* USCI A1 Control Word Register 1 */
+sfr_b(UCA1CTLW1_L);                           /* USCI A1 Control Word Register 1 */
+sfr_b(UCA1CTLW1_H);                           /* USCI A1 Control Word Register 1 */
+sfr_w(UCA1BRW);                               /* USCI A1 Baud Word Rate 0 */
+sfr_b(UCA1BRW_L);                             /* USCI A1 Baud Word Rate 0 */
+sfr_b(UCA1BRW_H);                             /* USCI A1 Baud Word Rate 0 */
+#define UCA1BR0                UCA1BRW_L      /* USCI A1 Baud Rate 0 */
+#define UCA1BR1                UCA1BRW_H      /* USCI A1 Baud Rate 1 */
+sfr_w(UCA1MCTLW);                             /* USCI A1 Modulation Control */
+sfr_b(UCA1MCTLW_L);                           /* USCI A1 Modulation Control */
+sfr_b(UCA1MCTLW_H);                           /* USCI A1 Modulation Control */
+sfr_b(UCA1STATW);                             /* USCI A1 Status Register */
+sfr_w(UCA1RXBUF);                             /* USCI A1 Receive Buffer */
+sfr_b(UCA1RXBUF_L);                           /* USCI A1 Receive Buffer */
+sfr_b(UCA1RXBUF_H);                           /* USCI A1 Receive Buffer */
+sfr_w(UCA1TXBUF);                             /* USCI A1 Transmit Buffer */
+sfr_b(UCA1TXBUF_L);                           /* USCI A1 Transmit Buffer */
+sfr_b(UCA1TXBUF_H);                           /* USCI A1 Transmit Buffer */
+sfr_b(UCA1ABCTL);                             /* USCI A1 LIN Control */
+sfr_w(UCA1IRCTL);                             /* USCI A1 IrDA Transmit Control */
+sfr_b(UCA1IRCTL_L);                           /* USCI A1 IrDA Transmit Control */
+sfr_b(UCA1IRCTL_H);                           /* USCI A1 IrDA Transmit Control */
+#define UCA1IRTCTL             UCA1IRCTL_L    /* USCI A1 IrDA Transmit Control */
+#define UCA1IRRCTL             UCA1IRCTL_H    /* USCI A1 IrDA Receive Control */
+sfr_w(UCA1IE);                                /* USCI A1 Interrupt Enable Register */
+sfr_b(UCA1IE_L);                              /* USCI A1 Interrupt Enable Register */
+sfr_b(UCA1IE_H);                              /* USCI A1 Interrupt Enable Register */
+sfr_w(UCA1IFG);                               /* USCI A1 Interrupt Flags Register */
+sfr_b(UCA1IFG_L);                             /* USCI A1 Interrupt Flags Register */
+sfr_b(UCA1IFG_H);                             /* USCI A1 Interrupt Flags Register */
+sfr_w(UCA1IV);                                /* USCI A1 Interrupt Vector Register */
+
+
+/************************************************************
+* USCI B0
+************************************************************/
+#define __MSP430_HAS_EUSCI_B0__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_EUSCI_B0__ 0x0640
+#define EUSCI_B0_BASE          __MSP430_BASEADDRESS_EUSCI_B0__
+
+
+sfr_w(UCB0CTLW0);                             /* USCI B0 Control Word Register 0 */
+sfr_b(UCB0CTLW0_L);                           /* USCI B0 Control Word Register 0 */
+sfr_b(UCB0CTLW0_H);                           /* USCI B0 Control Word Register 0 */
+#define UCB0CTL1               UCB0CTLW0_L    /* USCI B0 Control Register 1 */
+#define UCB0CTL0               UCB0CTLW0_H    /* USCI B0 Control Register 0 */
+sfr_w(UCB0CTLW1);                             /* USCI B0 Control Word Register 1 */
+sfr_b(UCB0CTLW1_L);                           /* USCI B0 Control Word Register 1 */
+sfr_b(UCB0CTLW1_H);                           /* USCI B0 Control Word Register 1 */
+sfr_w(UCB0BRW);                               /* USCI B0 Baud Word Rate 0 */
+sfr_b(UCB0BRW_L);                             /* USCI B0 Baud Word Rate 0 */
+sfr_b(UCB0BRW_H);                             /* USCI B0 Baud Word Rate 0 */
+#define UCB0BR0                UCB0BRW_L      /* USCI B0 Baud Rate 0 */
+#define UCB0BR1                UCB0BRW_H      /* USCI B0 Baud Rate 1 */
+sfr_w(UCB0STATW);                             /* USCI B0 Status Word Register */
+sfr_b(UCB0STATW_L);                           /* USCI B0 Status Word Register */
+sfr_b(UCB0STATW_H);                           /* USCI B0 Status Word Register */
+#define UCB0STAT               UCB0STATW_L    /* USCI B0 Status Register */
+#define UCB0BCNT               UCB0STATW_H    /* USCI B0 Byte Counter Register */
+sfr_w(UCB0TBCNT);                             /* USCI B0 Byte Counter Threshold Register */
+sfr_b(UCB0TBCNT_L);                           /* USCI B0 Byte Counter Threshold Register */
+sfr_b(UCB0TBCNT_H);                           /* USCI B0 Byte Counter Threshold Register */
+sfr_w(UCB0RXBUF);                             /* USCI B0 Receive Buffer */
+sfr_b(UCB0RXBUF_L);                           /* USCI B0 Receive Buffer */
+sfr_b(UCB0RXBUF_H);                           /* USCI B0 Receive Buffer */
+sfr_w(UCB0TXBUF);                             /* USCI B0 Transmit Buffer */
+sfr_b(UCB0TXBUF_L);                           /* USCI B0 Transmit Buffer */
+sfr_b(UCB0TXBUF_H);                           /* USCI B0 Transmit Buffer */
+sfr_w(UCB0I2COA0);                            /* USCI B0 I2C Own Address 0 */
+sfr_b(UCB0I2COA0_L);                          /* USCI B0 I2C Own Address 0 */
+sfr_b(UCB0I2COA0_H);                          /* USCI B0 I2C Own Address 0 */
+sfr_w(UCB0I2COA1);                            /* USCI B0 I2C Own Address 1 */
+sfr_b(UCB0I2COA1_L);                          /* USCI B0 I2C Own Address 1 */
+sfr_b(UCB0I2COA1_H);                          /* USCI B0 I2C Own Address 1 */
+sfr_w(UCB0I2COA2);                            /* USCI B0 I2C Own Address 2 */
+sfr_b(UCB0I2COA2_L);                          /* USCI B0 I2C Own Address 2 */
+sfr_b(UCB0I2COA2_H);                          /* USCI B0 I2C Own Address 2 */
+sfr_w(UCB0I2COA3);                            /* USCI B0 I2C Own Address 3 */
+sfr_b(UCB0I2COA3_L);                          /* USCI B0 I2C Own Address 3 */
+sfr_b(UCB0I2COA3_H);                          /* USCI B0 I2C Own Address 3 */
+sfr_w(UCB0ADDRX);                             /* USCI B0 Received Address Register */
+sfr_b(UCB0ADDRX_L);                           /* USCI B0 Received Address Register */
+sfr_b(UCB0ADDRX_H);                           /* USCI B0 Received Address Register */
+sfr_w(UCB0ADDMASK);                           /* USCI B0 Address Mask Register */
+sfr_b(UCB0ADDMASK_L);                         /* USCI B0 Address Mask Register */
+sfr_b(UCB0ADDMASK_H);                         /* USCI B0 Address Mask Register */
+sfr_w(UCB0I2CSA);                             /* USCI B0 I2C Slave Address */
+sfr_b(UCB0I2CSA_L);                           /* USCI B0 I2C Slave Address */
+sfr_b(UCB0I2CSA_H);                           /* USCI B0 I2C Slave Address */
+sfr_w(UCB0IE);                                /* USCI B0 Interrupt Enable Register */
+sfr_b(UCB0IE_L);                              /* USCI B0 Interrupt Enable Register */
+sfr_b(UCB0IE_H);                              /* USCI B0 Interrupt Enable Register */
+sfr_w(UCB0IFG);                               /* USCI B0 Interrupt Flags Register */
+sfr_b(UCB0IFG_L);                             /* USCI B0 Interrupt Flags Register */
+sfr_b(UCB0IFG_H);                             /* USCI B0 Interrupt Flags Register */
+sfr_w(UCB0IV);                                /* USCI B0 Interrupt Vector Register */
+
+/************************************************************
+* USCI B1
+************************************************************/
+#define __MSP430_HAS_EUSCI_B1__                /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_EUSCI_B1__ 0x0680
+#define EUSCI_B1_BASE          __MSP430_BASEADDRESS_EUSCI_B1__
+
+
+sfr_w(UCB1CTLW0);                             /* USCI B1 Control Word Register 0 */
+sfr_b(UCB1CTLW0_L);                           /* USCI B1 Control Word Register 0 */
+sfr_b(UCB1CTLW0_H);                           /* USCI B1 Control Word Register 0 */
+#define UCB1CTL1               UCB1CTLW0_L    /* USCI B1 Control Register 1 */
+#define UCB1CTL0               UCB1CTLW0_H    /* USCI B1 Control Register 0 */
+sfr_w(UCB1CTLW1);                             /* USCI B1 Control Word Register 1 */
+sfr_b(UCB1CTLW1_L);                           /* USCI B1 Control Word Register 1 */
+sfr_b(UCB1CTLW1_H);                           /* USCI B1 Control Word Register 1 */
+sfr_w(UCB1BRW);                               /* USCI B1 Baud Word Rate 0 */
+sfr_b(UCB1BRW_L);                             /* USCI B1 Baud Word Rate 0 */
+sfr_b(UCB1BRW_H);                             /* USCI B1 Baud Word Rate 0 */
+#define UCB1BR0                UCB1BRW_L      /* USCI B1 Baud Rate 0 */
+#define UCB1BR1                UCB1BRW_H      /* USCI B1 Baud Rate 1 */
+sfr_w(UCB1STATW);                             /* USCI B1 Status Word Register */
+sfr_b(UCB1STATW_L);                           /* USCI B1 Status Word Register */
+sfr_b(UCB1STATW_H);                           /* USCI B1 Status Word Register */
+#define UCB1STAT               UCB1STATW_L    /* USCI B1 Status Register */
+#define UCB1BCNT               UCB1STATW_H    /* USCI B1 Byte Counter Register */
+sfr_w(UCB1TBCNT);                             /* USCI B1 Byte Counter Threshold Register */
+sfr_b(UCB1TBCNT_L);                           /* USCI B1 Byte Counter Threshold Register */
+sfr_b(UCB1TBCNT_H);                           /* USCI B1 Byte Counter Threshold Register */
+sfr_w(UCB1RXBUF);                             /* USCI B1 Receive Buffer */
+sfr_b(UCB1RXBUF_L);                           /* USCI B1 Receive Buffer */
+sfr_b(UCB1RXBUF_H);                           /* USCI B1 Receive Buffer */
+sfr_w(UCB1TXBUF);                             /* USCI B1 Transmit Buffer */
+sfr_b(UCB1TXBUF_L);                           /* USCI B1 Transmit Buffer */
+sfr_b(UCB1TXBUF_H);                           /* USCI B1 Transmit Buffer */
+sfr_w(UCB1I2COA0);                            /* USCI B1 I2C Own Address 0 */
+sfr_b(UCB1I2COA0_L);                          /* USCI B1 I2C Own Address 0 */
+sfr_b(UCB1I2COA0_H);                          /* USCI B1 I2C Own Address 0 */
+sfr_w(UCB1I2COA1);                            /* USCI B1 I2C Own Address 1 */
+sfr_b(UCB1I2COA1_L);                          /* USCI B1 I2C Own Address 1 */
+sfr_b(UCB1I2COA1_H);                          /* USCI B1 I2C Own Address 1 */
+sfr_w(UCB1I2COA2);                            /* USCI B1 I2C Own Address 2 */
+sfr_b(UCB1I2COA2_L);                          /* USCI B1 I2C Own Address 2 */
+sfr_b(UCB1I2COA2_H);                          /* USCI B1 I2C Own Address 2 */
+sfr_w(UCB1I2COA3);                            /* USCI B1 I2C Own Address 3 */
+sfr_b(UCB1I2COA3_L);                          /* USCI B1 I2C Own Address 3 */
+sfr_b(UCB1I2COA3_H);                          /* USCI B1 I2C Own Address 3 */
+sfr_w(UCB1ADDRX);                             /* USCI B1 Received Address Register */
+sfr_b(UCB1ADDRX_L);                           /* USCI B1 Received Address Register */
+sfr_b(UCB1ADDRX_H);                           /* USCI B1 Received Address Register */
+sfr_w(UCB1ADDMASK);                           /* USCI B1 Address Mask Register */
+sfr_b(UCB1ADDMASK_L);                         /* USCI B1 Address Mask Register */
+sfr_b(UCB1ADDMASK_H);                         /* USCI B1 Address Mask Register */
+sfr_w(UCB1I2CSA);                             /* USCI B1 I2C Slave Address */
+sfr_b(UCB1I2CSA_L);                           /* USCI B1 I2C Slave Address */
+sfr_b(UCB1I2CSA_H);                           /* USCI B1 I2C Slave Address */
+sfr_w(UCB1IE);                                /* USCI B1 Interrupt Enable Register */
+sfr_b(UCB1IE_L);                              /* USCI B1 Interrupt Enable Register */
+sfr_b(UCB1IE_H);                              /* USCI B1 Interrupt Enable Register */
+sfr_w(UCB1IFG);                               /* USCI B1 Interrupt Flags Register */
+sfr_b(UCB1IFG_L);                             /* USCI B1 Interrupt Flags Register */
+sfr_b(UCB1IFG_H);                             /* USCI B1 Interrupt Flags Register */
+sfr_w(UCB1IV);                                /* USCI B1 Interrupt Vector Register */
+
+// UCAxCTLW0 UART-Mode Control Bits
+#define UCPEN                  (0x8000)       /* Async. Mode: Parity enable */
+#define UCPAR                  (0x4000)       /* Async. Mode: Parity     0:odd / 1:even */
+#define UCMSB                  (0x2000)       /* Async. Mode: MSB first  0:LSB / 1:MSB */
+#define UC7BIT                 (0x1000)       /* Async. Mode: Data Bits  0:8-bits / 1:7-bits */
+#define UCSPB                  (0x0800)       /* Async. Mode: Stop Bits  0:one / 1: two */
+#define UCMODE1                (0x0400)       /* Async. Mode: USCI Mode 1 */
+#define UCMODE0                (0x0200)       /* Async. Mode: USCI Mode 0 */
+#define UCSYNC                 (0x0100)       /* Sync-Mode  0:UART-Mode / 1:SPI-Mode */
+#define UCSSEL1                (0x0080)       /* USCI 0 Clock Source Select 1 */
+#define UCSSEL0                (0x0040)       /* USCI 0 Clock Source Select 0 */
+#define UCRXEIE                (0x0020)       /* RX Error interrupt enable */
+#define UCBRKIE                (0x0010)       /* Break interrupt enable */
+#define UCDORM                 (0x0008)       /* Dormant (Sleep) Mode */
+#define UCTXADDR               (0x0004)       /* Send next Data as Address */
+#define UCTXBRK                (0x0002)       /* Send next Data as Break */
+#define UCSWRST                (0x0001)       /* USCI Software Reset */
+
+// UCAxCTLW0 UART-Mode Control Bits
+#define UCSSEL1_L              (0x0080)       /* USCI 0 Clock Source Select 1 */
+#define UCSSEL0_L              (0x0040)       /* USCI 0 Clock Source Select 0 */
+#define UCRXEIE_L              (0x0020)       /* RX Error interrupt enable */
+#define UCBRKIE_L              (0x0010)       /* Break interrupt enable */
+#define UCDORM_L               (0x0008)       /* Dormant (Sleep) Mode */
+#define UCTXADDR_L             (0x0004)       /* Send next Data as Address */
+#define UCTXBRK_L              (0x0002)       /* Send next Data as Break */
+#define UCSWRST_L              (0x0001)       /* USCI Software Reset */
+
+// UCAxCTLW0 UART-Mode Control Bits
+#define UCPEN_H                (0x0080)       /* Async. Mode: Parity enable */
+#define UCPAR_H                (0x0040)       /* Async. Mode: Parity     0:odd / 1:even */
+#define UCMSB_H                (0x0020)       /* Async. Mode: MSB first  0:LSB / 1:MSB */
+#define UC7BIT_H               (0x0010)       /* Async. Mode: Data Bits  0:8-bits / 1:7-bits */
+#define UCSPB_H                (0x0008)       /* Async. Mode: Stop Bits  0:one / 1: two */
+#define UCMODE1_H              (0x0004)       /* Async. Mode: USCI Mode 1 */
+#define UCMODE0_H              (0x0002)       /* Async. Mode: USCI Mode 0 */
+#define UCSYNC_H               (0x0001)       /* Sync-Mode  0:UART-Mode / 1:SPI-Mode */
+
+// UCxxCTLW0 SPI-Mode Control Bits
+#define UCCKPH                 (0x8000)       /* Sync. Mode: Clock Phase */
+#define UCCKPL                 (0x4000)       /* Sync. Mode: Clock Polarity */
+#define UCMST                  (0x0800)       /* Sync. Mode: Master Select */
+//#define res               (0x0020)    /* reserved */
+//#define res               (0x0010)    /* reserved */
+//#define res               (0x0008)    /* reserved */
+//#define res               (0x0004)    /* reserved */
+#define UCSTEM                 (0x0002)       /* USCI STE Mode */
+
+// UCBxCTLW0 I2C-Mode Control Bits
+#define UCA10                  (0x8000)       /* 10-bit Address Mode */
+#define UCSLA10                (0x4000)       /* 10-bit Slave Address Mode */
+#define UCMM                   (0x2000)       /* Multi-Master Environment */
+//#define res               (0x1000)    /* reserved */
+//#define res               (0x0100)    /* reserved */
+#define UCTXACK                (0x0020)       /* Transmit ACK */
+#define UCTR                   (0x0010)       /* Transmit/Receive Select/Flag */
+#define UCTXNACK               (0x0008)       /* Transmit NACK */
+#define UCTXSTP                (0x0004)       /* Transmit STOP */
+#define UCTXSTT                (0x0002)       /* Transmit START */
+
+// UCBxCTLW0 I2C-Mode Control Bits
+//#define res               (0x1000)    /* reserved */
+//#define res               (0x0100)    /* reserved */
+#define UCTXACK_L              (0x0020)       /* Transmit ACK */
+#define UCTR_L                 (0x0010)       /* Transmit/Receive Select/Flag */
+#define UCTXNACK_L             (0x0008)       /* Transmit NACK */
+#define UCTXSTP_L              (0x0004)       /* Transmit STOP */
+#define UCTXSTT_L              (0x0002)       /* Transmit START */
+
+// UCBxCTLW0 I2C-Mode Control Bits
+#define UCA10_H                (0x0080)       /* 10-bit Address Mode */
+#define UCSLA10_H              (0x0040)       /* 10-bit Slave Address Mode */
+#define UCMM_H                 (0x0020)       /* Multi-Master Environment */
+//#define res               (0x1000)    /* reserved */
+//#define res               (0x0100)    /* reserved */
+
+#define UCMODE_0               (0x0000)       /* Sync. Mode: USCI Mode: 0 */
+#define UCMODE_1               (0x0200)       /* Sync. Mode: USCI Mode: 1 */
+#define UCMODE_2               (0x0400)       /* Sync. Mode: USCI Mode: 2 */
+#define UCMODE_3               (0x0600)       /* Sync. Mode: USCI Mode: 3 */
+
+#define UCSSEL_0               (0x0000)       /* USCI 0 Clock Source: 0 */
+#define UCSSEL_1               (0x0040)       /* USCI 0 Clock Source: 1 */
+#define UCSSEL_2               (0x0080)       /* USCI 0 Clock Source: 2 */
+#define UCSSEL_3               (0x00C0)       /* USCI 0 Clock Source: 3 */
+#define UCSSEL__UCLK           (0x0000)       /* USCI 0 Clock Source: UCLK */
+#define UCSSEL__ACLK           (0x0040)       /* USCI 0 Clock Source: ACLK */
+#define UCSSEL__SMCLK          (0x0080)       /* USCI 0 Clock Source: SMCLK */
+
+// UCAxCTLW1 UART-Mode Control Bits
+#define UCGLIT1                (0x0002)       /* USCI Deglitch Time Bit 1 */
+#define UCGLIT0                (0x0001)       /* USCI Deglitch Time Bit 0 */
+
+// UCAxCTLW1 UART-Mode Control Bits
+#define UCGLIT1_L              (0x0002)       /* USCI Deglitch Time Bit 1 */
+#define UCGLIT0_L              (0x0001)       /* USCI Deglitch Time Bit 0 */
+
+// UCBxCTLW1 I2C-Mode Control Bits
+#define UCETXINT               (0x0100)       /* USCI Early UCTXIFG0 */
+#define UCCLTO1                (0x0080)       /* USCI Clock low timeout Bit: 1 */
+#define UCCLTO0                (0x0040)       /* USCI Clock low timeout Bit: 0 */
+#define UCSTPNACK              (0x0020)       /* USCI Acknowledge Stop last byte */
+#define UCSWACK                (0x0010)       /* USCI Software controlled ACK */
+#define UCASTP1                (0x0008)       /* USCI Automatic Stop condition generation Bit: 1 */
+#define UCASTP0                (0x0004)       /* USCI Automatic Stop condition generation Bit: 0 */
+#define UCGLIT1                (0x0002)       /* USCI Deglitch time Bit: 1 */
+#define UCGLIT0                (0x0001)       /* USCI Deglitch time Bit: 0 */
+
+// UCBxCTLW1 I2C-Mode Control Bits
+#define UCCLTO1_L              (0x0080)       /* USCI Clock low timeout Bit: 1 */
+#define UCCLTO0_L              (0x0040)       /* USCI Clock low timeout Bit: 0 */
+#define UCSTPNACK_L            (0x0020)       /* USCI Acknowledge Stop last byte */
+#define UCSWACK_L              (0x0010)       /* USCI Software controlled ACK */
+#define UCASTP1_L              (0x0008)       /* USCI Automatic Stop condition generation Bit: 1 */
+#define UCASTP0_L              (0x0004)       /* USCI Automatic Stop condition generation Bit: 0 */
+#define UCGLIT1_L              (0x0002)       /* USCI Deglitch time Bit: 1 */
+#define UCGLIT0_L              (0x0001)       /* USCI Deglitch time Bit: 0 */
+
+// UCBxCTLW1 I2C-Mode Control Bits
+#define UCETXINT_H             (0x0001)       /* USCI Early UCTXIFG0 */
+
+#define UCGLIT_0               (0x0000)       /* USCI Deglitch time: 0 */
+#define UCGLIT_1               (0x0001)       /* USCI Deglitch time: 1 */
+#define UCGLIT_2               (0x0002)       /* USCI Deglitch time: 2 */
+#define UCGLIT_3               (0x0003)       /* USCI Deglitch time: 3 */
+
+#define UCASTP_0               (0x0000)       /* USCI Automatic Stop condition generation: 0 */
+#define UCASTP_1               (0x0004)       /* USCI Automatic Stop condition generation: 1 */
+#define UCASTP_2               (0x0008)       /* USCI Automatic Stop condition generation: 2 */
+#define UCASTP_3               (0x000C)       /* USCI Automatic Stop condition generation: 3 */
+
+#define UCCLTO_0               (0x0000)       /* USCI Clock low timeout: 0 */
+#define UCCLTO_1               (0x0040)       /* USCI Clock low timeout: 1 */
+#define UCCLTO_2               (0x0080)       /* USCI Clock low timeout: 2 */
+#define UCCLTO_3               (0x00C0)       /* USCI Clock low timeout: 3 */
+
+/* UCAxMCTLW Control Bits */
+#define UCBRS7                 (0x8000)       /* USCI Second Stage Modulation Select 7 */
+#define UCBRS6                 (0x4000)       /* USCI Second Stage Modulation Select 6 */
+#define UCBRS5                 (0x2000)       /* USCI Second Stage Modulation Select 5 */
+#define UCBRS4                 (0x1000)       /* USCI Second Stage Modulation Select 4 */
+#define UCBRS3                 (0x0800)       /* USCI Second Stage Modulation Select 3 */
+#define UCBRS2                 (0x0400)       /* USCI Second Stage Modulation Select 2 */
+#define UCBRS1                 (0x0200)       /* USCI Second Stage Modulation Select 1 */
+#define UCBRS0                 (0x0100)       /* USCI Second Stage Modulation Select 0 */
+#define UCBRF3                 (0x0080)       /* USCI First Stage Modulation Select 3 */
+#define UCBRF2                 (0x0040)       /* USCI First Stage Modulation Select 2 */
+#define UCBRF1                 (0x0020)       /* USCI First Stage Modulation Select 1 */
+#define UCBRF0                 (0x0010)       /* USCI First Stage Modulation Select 0 */
+#define UCOS16                 (0x0001)       /* USCI 16-times Oversampling enable */
+
+/* UCAxMCTLW Control Bits */
+#define UCBRF3_L               (0x0080)       /* USCI First Stage Modulation Select 3 */
+#define UCBRF2_L               (0x0040)       /* USCI First Stage Modulation Select 2 */
+#define UCBRF1_L               (0x0020)       /* USCI First Stage Modulation Select 1 */
+#define UCBRF0_L               (0x0010)       /* USCI First Stage Modulation Select 0 */
+#define UCOS16_L               (0x0001)       /* USCI 16-times Oversampling enable */
+
+/* UCAxMCTLW Control Bits */
+#define UCBRS7_H               (0x0080)       /* USCI Second Stage Modulation Select 7 */
+#define UCBRS6_H               (0x0040)       /* USCI Second Stage Modulation Select 6 */
+#define UCBRS5_H               (0x0020)       /* USCI Second Stage Modulation Select 5 */
+#define UCBRS4_H               (0x0010)       /* USCI Second Stage Modulation Select 4 */
+#define UCBRS3_H               (0x0008)       /* USCI Second Stage Modulation Select 3 */
+#define UCBRS2_H               (0x0004)       /* USCI Second Stage Modulation Select 2 */
+#define UCBRS1_H               (0x0002)       /* USCI Second Stage Modulation Select 1 */
+#define UCBRS0_H               (0x0001)       /* USCI Second Stage Modulation Select 0 */
+
+#define UCBRF_0                (0x00)         /* USCI First Stage Modulation: 0 */
+#define UCBRF_1                (0x10)         /* USCI First Stage Modulation: 1 */
+#define UCBRF_2                (0x20)         /* USCI First Stage Modulation: 2 */
+#define UCBRF_3                (0x30)         /* USCI First Stage Modulation: 3 */
+#define UCBRF_4                (0x40)         /* USCI First Stage Modulation: 4 */
+#define UCBRF_5                (0x50)         /* USCI First Stage Modulation: 5 */
+#define UCBRF_6                (0x60)         /* USCI First Stage Modulation: 6 */
+#define UCBRF_7                (0x70)         /* USCI First Stage Modulation: 7 */
+#define UCBRF_8                (0x80)         /* USCI First Stage Modulation: 8 */
+#define UCBRF_9                (0x90)         /* USCI First Stage Modulation: 9 */
+#define UCBRF_10               (0xA0)         /* USCI First Stage Modulation: A */
+#define UCBRF_11               (0xB0)         /* USCI First Stage Modulation: B */
+#define UCBRF_12               (0xC0)         /* USCI First Stage Modulation: C */
+#define UCBRF_13               (0xD0)         /* USCI First Stage Modulation: D */
+#define UCBRF_14               (0xE0)         /* USCI First Stage Modulation: E */
+#define UCBRF_15               (0xF0)         /* USCI First Stage Modulation: F */
+
+/* UCAxSTATW Control Bits */
+#define UCLISTEN               (0x0080)       /* USCI Listen mode */
+#define UCFE                   (0x0040)       /* USCI Frame Error Flag */
+#define UCOE                   (0x0020)       /* USCI Overrun Error Flag */
+#define UCPE                   (0x0010)       /* USCI Parity Error Flag */
+#define UCBRK                  (0x0008)       /* USCI Break received */
+#define UCRXERR                (0x0004)       /* USCI RX Error Flag */
+#define UCADDR                 (0x0002)       /* USCI Address received Flag */
+#define UCBUSY                 (0x0001)       /* USCI Busy Flag */
+#define UCIDLE                 (0x0002)       /* USCI Idle line detected Flag */
+
+/* UCBxSTATW I2C Control Bits */
+#define UCBCNT7                (0x8000)       /* USCI Byte Counter Bit 7 */
+#define UCBCNT6                (0x4000)       /* USCI Byte Counter Bit 6 */
+#define UCBCNT5                (0x2000)       /* USCI Byte Counter Bit 5 */
+#define UCBCNT4                (0x1000)       /* USCI Byte Counter Bit 4 */
+#define UCBCNT3                (0x0800)       /* USCI Byte Counter Bit 3 */
+#define UCBCNT2                (0x0400)       /* USCI Byte Counter Bit 2 */
+#define UCBCNT1                (0x0200)       /* USCI Byte Counter Bit 1 */
+#define UCBCNT0                (0x0100)       /* USCI Byte Counter Bit 0 */
+#define UCSCLLOW               (0x0040)       /* SCL low */
+#define UCGC                   (0x0020)       /* General Call address received Flag */
+#define UCBBUSY                (0x0010)       /* Bus Busy Flag */
+
+/* UCBxTBCNT I2C Control Bits */
+#define UCTBCNT7               (0x0080)       /* USCI Byte Counter Bit 7 */
+#define UCTBCNT6               (0x0040)       /* USCI Byte Counter Bit 6 */
+#define UCTBCNT5               (0x0020)       /* USCI Byte Counter Bit 5 */
+#define UCTBCNT4               (0x0010)       /* USCI Byte Counter Bit 4 */
+#define UCTBCNT3               (0x0008)       /* USCI Byte Counter Bit 3 */
+#define UCTBCNT2               (0x0004)       /* USCI Byte Counter Bit 2 */
+#define UCTBCNT1               (0x0002)       /* USCI Byte Counter Bit 1 */
+#define UCTBCNT0               (0x0001)       /* USCI Byte Counter Bit 0 */
+
+/* UCAxIRCTL Control Bits */
+#define UCIRRXFL5              (0x8000)       /* IRDA Receive Filter Length 5 */
+#define UCIRRXFL4              (0x4000)       /* IRDA Receive Filter Length 4 */
+#define UCIRRXFL3              (0x2000)       /* IRDA Receive Filter Length 3 */
+#define UCIRRXFL2              (0x1000)       /* IRDA Receive Filter Length 2 */
+#define UCIRRXFL1              (0x0800)       /* IRDA Receive Filter Length 1 */
+#define UCIRRXFL0              (0x0400)       /* IRDA Receive Filter Length 0 */
+#define UCIRRXPL               (0x0200)       /* IRDA Receive Input Polarity */
+#define UCIRRXFE               (0x0100)       /* IRDA Receive Filter enable */
+#define UCIRTXPL5              (0x0080)       /* IRDA Transmit Pulse Length 5 */
+#define UCIRTXPL4              (0x0040)       /* IRDA Transmit Pulse Length 4 */
+#define UCIRTXPL3              (0x0020)       /* IRDA Transmit Pulse Length 3 */
+#define UCIRTXPL2              (0x0010)       /* IRDA Transmit Pulse Length 2 */
+#define UCIRTXPL1              (0x0008)       /* IRDA Transmit Pulse Length 1 */
+#define UCIRTXPL0              (0x0004)       /* IRDA Transmit Pulse Length 0 */
+#define UCIRTXCLK              (0x0002)       /* IRDA Transmit Pulse Clock Select */
+#define UCIREN                 (0x0001)       /* IRDA Encoder/Decoder enable */
+
+/* UCAxIRCTL Control Bits */
+#define UCIRTXPL5_L            (0x0080)       /* IRDA Transmit Pulse Length 5 */
+#define UCIRTXPL4_L            (0x0040)       /* IRDA Transmit Pulse Length 4 */
+#define UCIRTXPL3_L            (0x0020)       /* IRDA Transmit Pulse Length 3 */
+#define UCIRTXPL2_L            (0x0010)       /* IRDA Transmit Pulse Length 2 */
+#define UCIRTXPL1_L            (0x0008)       /* IRDA Transmit Pulse Length 1 */
+#define UCIRTXPL0_L            (0x0004)       /* IRDA Transmit Pulse Length 0 */
+#define UCIRTXCLK_L            (0x0002)       /* IRDA Transmit Pulse Clock Select */
+#define UCIREN_L               (0x0001)       /* IRDA Encoder/Decoder enable */
+
+/* UCAxIRCTL Control Bits */
+#define UCIRRXFL5_H            (0x0080)       /* IRDA Receive Filter Length 5 */
+#define UCIRRXFL4_H            (0x0040)       /* IRDA Receive Filter Length 4 */
+#define UCIRRXFL3_H            (0x0020)       /* IRDA Receive Filter Length 3 */
+#define UCIRRXFL2_H            (0x0010)       /* IRDA Receive Filter Length 2 */
+#define UCIRRXFL1_H            (0x0008)       /* IRDA Receive Filter Length 1 */
+#define UCIRRXFL0_H            (0x0004)       /* IRDA Receive Filter Length 0 */
+#define UCIRRXPL_H             (0x0002)       /* IRDA Receive Input Polarity */
+#define UCIRRXFE_H             (0x0001)       /* IRDA Receive Filter enable */
+
+/* UCAxABCTL Control Bits */
+//#define res               (0x80)    /* reserved */
+//#define res               (0x40)    /* reserved */
+#define UCDELIM1               (0x20)         /* Break Sync Delimiter 1 */
+#define UCDELIM0               (0x10)         /* Break Sync Delimiter 0 */
+#define UCSTOE                 (0x08)         /* Sync-Field Timeout error */
+#define UCBTOE                 (0x04)         /* Break Timeout error */
+//#define res               (0x02)    /* reserved */
+#define UCABDEN                (0x01)         /* Auto Baud Rate detect enable */
+
+/* UCBxI2COA0 Control Bits */
+#define UCGCEN                 (0x8000)       /* I2C General Call enable */
+#define UCOAEN                 (0x0400)       /* I2C Own Address enable */
+#define UCOA9                  (0x0200)       /* I2C Own Address Bit 9 */
+#define UCOA8                  (0x0100)       /* I2C Own Address Bit 8 */
+#define UCOA7                  (0x0080)       /* I2C Own Address Bit 7 */
+#define UCOA6                  (0x0040)       /* I2C Own Address Bit 6 */
+#define UCOA5                  (0x0020)       /* I2C Own Address Bit 5 */
+#define UCOA4                  (0x0010)       /* I2C Own Address Bit 4 */
+#define UCOA3                  (0x0008)       /* I2C Own Address Bit 3 */
+#define UCOA2                  (0x0004)       /* I2C Own Address Bit 2 */
+#define UCOA1                  (0x0002)       /* I2C Own Address Bit 1 */
+#define UCOA0                  (0x0001)       /* I2C Own Address Bit 0 */
+
+/* UCBxI2COA0 Control Bits */
+#define UCOA7_L                (0x0080)       /* I2C Own Address Bit 7 */
+#define UCOA6_L                (0x0040)       /* I2C Own Address Bit 6 */
+#define UCOA5_L                (0x0020)       /* I2C Own Address Bit 5 */
+#define UCOA4_L                (0x0010)       /* I2C Own Address Bit 4 */
+#define UCOA3_L                (0x0008)       /* I2C Own Address Bit 3 */
+#define UCOA2_L                (0x0004)       /* I2C Own Address Bit 2 */
+#define UCOA1_L                (0x0002)       /* I2C Own Address Bit 1 */
+#define UCOA0_L                (0x0001)       /* I2C Own Address Bit 0 */
+
+/* UCBxI2COA0 Control Bits */
+#define UCGCEN_H               (0x0080)       /* I2C General Call enable */
+#define UCOAEN_H               (0x0004)       /* I2C Own Address enable */
+#define UCOA9_H                (0x0002)       /* I2C Own Address Bit 9 */
+#define UCOA8_H                (0x0001)       /* I2C Own Address Bit 8 */
+
+/* UCBxI2COAx Control Bits */
+#define UCOAEN                 (0x0400)       /* I2C Own Address enable */
+#define UCOA9                  (0x0200)       /* I2C Own Address Bit 9 */
+#define UCOA8                  (0x0100)       /* I2C Own Address Bit 8 */
+#define UCOA7                  (0x0080)       /* I2C Own Address Bit 7 */
+#define UCOA6                  (0x0040)       /* I2C Own Address Bit 6 */
+#define UCOA5                  (0x0020)       /* I2C Own Address Bit 5 */
+#define UCOA4                  (0x0010)       /* I2C Own Address Bit 4 */
+#define UCOA3                  (0x0008)       /* I2C Own Address Bit 3 */
+#define UCOA2                  (0x0004)       /* I2C Own Address Bit 2 */
+#define UCOA1                  (0x0002)       /* I2C Own Address Bit 1 */
+#define UCOA0                  (0x0001)       /* I2C Own Address Bit 0 */
+
+/* UCBxI2COAx Control Bits */
+#define UCOA7_L                (0x0080)       /* I2C Own Address Bit 7 */
+#define UCOA6_L                (0x0040)       /* I2C Own Address Bit 6 */
+#define UCOA5_L                (0x0020)       /* I2C Own Address Bit 5 */
+#define UCOA4_L                (0x0010)       /* I2C Own Address Bit 4 */
+#define UCOA3_L                (0x0008)       /* I2C Own Address Bit 3 */
+#define UCOA2_L                (0x0004)       /* I2C Own Address Bit 2 */
+#define UCOA1_L                (0x0002)       /* I2C Own Address Bit 1 */
+#define UCOA0_L                (0x0001)       /* I2C Own Address Bit 0 */
+
+/* UCBxI2COAx Control Bits */
+#define UCOAEN_H               (0x0004)       /* I2C Own Address enable */
+#define UCOA9_H                (0x0002)       /* I2C Own Address Bit 9 */
+#define UCOA8_H                (0x0001)       /* I2C Own Address Bit 8 */
+
+/* UCBxADDRX Control Bits */
+#define UCADDRX9               (0x0200)       /* I2C Receive Address Bit 9 */
+#define UCADDRX8               (0x0100)       /* I2C Receive Address Bit 8 */
+#define UCADDRX7               (0x0080)       /* I2C Receive Address Bit 7 */
+#define UCADDRX6               (0x0040)       /* I2C Receive Address Bit 6 */
+#define UCADDRX5               (0x0020)       /* I2C Receive Address Bit 5 */
+#define UCADDRX4               (0x0010)       /* I2C Receive Address Bit 4 */
+#define UCADDRX3               (0x0008)       /* I2C Receive Address Bit 3 */
+#define UCADDRX2               (0x0004)       /* I2C Receive Address Bit 2 */
+#define UCADDRX1               (0x0002)       /* I2C Receive Address Bit 1 */
+#define UCADDRX0               (0x0001)       /* I2C Receive Address Bit 0 */
+
+/* UCBxADDRX Control Bits */
+#define UCADDRX7_L             (0x0080)       /* I2C Receive Address Bit 7 */
+#define UCADDRX6_L             (0x0040)       /* I2C Receive Address Bit 6 */
+#define UCADDRX5_L             (0x0020)       /* I2C Receive Address Bit 5 */
+#define UCADDRX4_L             (0x0010)       /* I2C Receive Address Bit 4 */
+#define UCADDRX3_L             (0x0008)       /* I2C Receive Address Bit 3 */
+#define UCADDRX2_L             (0x0004)       /* I2C Receive Address Bit 2 */
+#define UCADDRX1_L             (0x0002)       /* I2C Receive Address Bit 1 */
+#define UCADDRX0_L             (0x0001)       /* I2C Receive Address Bit 0 */
+
+/* UCBxADDRX Control Bits */
+#define UCADDRX9_H             (0x0002)       /* I2C Receive Address Bit 9 */
+#define UCADDRX8_H             (0x0001)       /* I2C Receive Address Bit 8 */
+
+/* UCBxADDMASK Control Bits */
+#define UCADDMASK9             (0x0200)       /* I2C Address Mask Bit 9 */
+#define UCADDMASK8             (0x0100)       /* I2C Address Mask Bit 8 */
+#define UCADDMASK7             (0x0080)       /* I2C Address Mask Bit 7 */
+#define UCADDMASK6             (0x0040)       /* I2C Address Mask Bit 6 */
+#define UCADDMASK5             (0x0020)       /* I2C Address Mask Bit 5 */
+#define UCADDMASK4             (0x0010)       /* I2C Address Mask Bit 4 */
+#define UCADDMASK3             (0x0008)       /* I2C Address Mask Bit 3 */
+#define UCADDMASK2             (0x0004)       /* I2C Address Mask Bit 2 */
+#define UCADDMASK1             (0x0002)       /* I2C Address Mask Bit 1 */
+#define UCADDMASK0             (0x0001)       /* I2C Address Mask Bit 0 */
+
+/* UCBxADDMASK Control Bits */
+#define UCADDMASK7_L           (0x0080)       /* I2C Address Mask Bit 7 */
+#define UCADDMASK6_L           (0x0040)       /* I2C Address Mask Bit 6 */
+#define UCADDMASK5_L           (0x0020)       /* I2C Address Mask Bit 5 */
+#define UCADDMASK4_L           (0x0010)       /* I2C Address Mask Bit 4 */
+#define UCADDMASK3_L           (0x0008)       /* I2C Address Mask Bit 3 */
+#define UCADDMASK2_L           (0x0004)       /* I2C Address Mask Bit 2 */
+#define UCADDMASK1_L           (0x0002)       /* I2C Address Mask Bit 1 */
+#define UCADDMASK0_L           (0x0001)       /* I2C Address Mask Bit 0 */
+
+/* UCBxADDMASK Control Bits */
+#define UCADDMASK9_H           (0x0002)       /* I2C Address Mask Bit 9 */
+#define UCADDMASK8_H           (0x0001)       /* I2C Address Mask Bit 8 */
+
+/* UCBxI2CSA Control Bits */
+#define UCSA9                  (0x0200)       /* I2C Slave Address Bit 9 */
+#define UCSA8                  (0x0100)       /* I2C Slave Address Bit 8 */
+#define UCSA7                  (0x0080)       /* I2C Slave Address Bit 7 */
+#define UCSA6                  (0x0040)       /* I2C Slave Address Bit 6 */
+#define UCSA5                  (0x0020)       /* I2C Slave Address Bit 5 */
+#define UCSA4                  (0x0010)       /* I2C Slave Address Bit 4 */
+#define UCSA3                  (0x0008)       /* I2C Slave Address Bit 3 */
+#define UCSA2                  (0x0004)       /* I2C Slave Address Bit 2 */
+#define UCSA1                  (0x0002)       /* I2C Slave Address Bit 1 */
+#define UCSA0                  (0x0001)       /* I2C Slave Address Bit 0 */
+
+/* UCBxI2CSA Control Bits */
+#define UCSA7_L                (0x0080)       /* I2C Slave Address Bit 7 */
+#define UCSA6_L                (0x0040)       /* I2C Slave Address Bit 6 */
+#define UCSA5_L                (0x0020)       /* I2C Slave Address Bit 5 */
+#define UCSA4_L                (0x0010)       /* I2C Slave Address Bit 4 */
+#define UCSA3_L                (0x0008)       /* I2C Slave Address Bit 3 */
+#define UCSA2_L                (0x0004)       /* I2C Slave Address Bit 2 */
+#define UCSA1_L                (0x0002)       /* I2C Slave Address Bit 1 */
+#define UCSA0_L                (0x0001)       /* I2C Slave Address Bit 0 */
+
+/* UCBxI2CSA Control Bits */
+#define UCSA9_H                (0x0002)       /* I2C Slave Address Bit 9 */
+#define UCSA8_H                (0x0001)       /* I2C Slave Address Bit 8 */
+
+/* UCAxIE UART Control Bits */
+#define UCTXCPTIE              (0x0008)       /* UART Transmit Complete Interrupt Enable */
+#define UCSTTIE                (0x0004)       /* UART Start Bit Interrupt Enalble */
+#define UCTXIE                 (0x0002)       /* UART Transmit Interrupt Enable */
+#define UCRXIE                 (0x0001)       /* UART Receive Interrupt Enable */
+
+/* UCAxIE/UCBxIE SPI Control Bits */
+
+/* UCBxIE I2C Control Bits */
+#define UCBIT9IE               (0x4000)       /* I2C Bit 9 Position Interrupt Enable 3 */
+#define UCTXIE3                (0x2000)       /* I2C Transmit Interrupt Enable 3 */
+#define UCRXIE3                (0x1000)       /* I2C Receive Interrupt Enable 3 */
+#define UCTXIE2                (0x0800)       /* I2C Transmit Interrupt Enable 2 */
+#define UCRXIE2                (0x0400)       /* I2C Receive Interrupt Enable 2 */
+#define UCTXIE1                (0x0200)       /* I2C Transmit Interrupt Enable 1 */
+#define UCRXIE1                (0x0100)       /* I2C Receive Interrupt Enable 1 */
+#define UCCLTOIE               (0x0080)       /* I2C Clock Low Timeout interrupt enable */
+#define UCBCNTIE               (0x0040)       /* I2C Automatic stop assertion interrupt enable */
+#define UCNACKIE               (0x0020)       /* I2C NACK Condition interrupt enable */
+#define UCALIE                 (0x0010)       /* I2C Arbitration Lost interrupt enable */
+#define UCSTPIE                (0x0008)       /* I2C STOP Condition interrupt enable */
+#define UCSTTIE                (0x0004)       /* I2C START Condition interrupt enable */
+#define UCTXIE0                (0x0002)       /* I2C Transmit Interrupt Enable 0 */
+#define UCRXIE0                (0x0001)       /* I2C Receive Interrupt Enable 0 */
+
+/* UCAxIFG UART Control Bits */
+#define UCTXCPTIFG             (0x0008)       /* UART Transmit Complete Interrupt Flag */
+#define UCSTTIFG               (0x0004)       /* UART Start Bit Interrupt Flag */
+#define UCTXIFG                (0x0002)       /* UART Transmit Interrupt Flag */
+#define UCRXIFG                (0x0001)       /* UART Receive Interrupt Flag */
+
+/* UCAxIFG/UCBxIFG SPI Control Bits */
+#define UCTXIFG                (0x0002)       /* SPI Transmit Interrupt Flag */
+#define UCRXIFG                (0x0001)       /* SPI Receive Interrupt Flag */
+
+/* UCBxIFG Control Bits */
+#define UCBIT9IFG              (0x4000)       /* I2C Bit 9 Possition Interrupt Flag 3 */
+#define UCTXIFG3               (0x2000)       /* I2C Transmit Interrupt Flag 3 */
+#define UCRXIFG3               (0x1000)       /* I2C Receive Interrupt Flag 3 */
+#define UCTXIFG2               (0x0800)       /* I2C Transmit Interrupt Flag 2 */
+#define UCRXIFG2               (0x0400)       /* I2C Receive Interrupt Flag 2 */
+#define UCTXIFG1               (0x0200)       /* I2C Transmit Interrupt Flag 1 */
+#define UCRXIFG1               (0x0100)       /* I2C Receive Interrupt Flag 1 */
+#define UCCLTOIFG              (0x0080)       /* I2C Clock low Timeout interrupt Flag */
+#define UCBCNTIFG              (0x0040)       /* I2C Byte counter interrupt flag */
+#define UCNACKIFG              (0x0020)       /* I2C NACK Condition interrupt Flag */
+#define UCALIFG                (0x0010)       /* I2C Arbitration Lost interrupt Flag */
+#define UCSTPIFG               (0x0008)       /* I2C STOP Condition interrupt Flag */
+#define UCSTTIFG               (0x0004)       /* I2C START Condition interrupt Flag */
+#define UCTXIFG0               (0x0002)       /* I2C Transmit Interrupt Flag 0 */
+#define UCRXIFG0               (0x0001)       /* I2C Receive Interrupt Flag 0 */
+
+/* USCI Interrupt Vector UART Definitions */
+#define USCI_NONE              (0x0000)       /* No Interrupt pending */
+#define USCI_UART_UCRXIFG      (0x0002)       /* Interrupt Vector: UCRXIFG */
+#define USCI_UART_UCTXIFG      (0x0004)       /* Interrupt Vector: UCTXIFG */
+#define USCI_UART_UCSTTIFG     (0x0006)       /* Interrupt Vector: UCSTTIFG */
+#define USCI_UART_UCTXCPTIFG   (0x0008)       /* Interrupt Vector: UCTXCPTIFG */
+
+/* USCI Interrupt Vector SPI Definitions */
+#define USCI_SPI_UCRXIFG       (0x0002)       /* Interrupt Vector: UCRXIFG */
+#define USCI_SPI_UCTXIFG       (0x0004)       /* Interrupt Vector: UCTXIFG */
+
+/* USCI Interrupt Vector I2C Definitions */
+#define USCI_I2C_UCALIFG       (0x0002)       /* Interrupt Vector: I2C Mode: UCALIFG */
+#define USCI_I2C_UCNACKIFG     (0x0004)       /* Interrupt Vector: I2C Mode: UCNACKIFG */
+#define USCI_I2C_UCSTTIFG      (0x0006)       /* Interrupt Vector: I2C Mode: UCSTTIFG*/
+#define USCI_I2C_UCSTPIFG      (0x0008)       /* Interrupt Vector: I2C Mode: UCSTPIFG*/
+#define USCI_I2C_UCRXIFG3      (0x000A)       /* Interrupt Vector: I2C Mode: UCRXIFG3 */
+#define USCI_I2C_UCTXIFG3      (0x000C)       /* Interrupt Vector: I2C Mode: UCTXIFG3 */
+#define USCI_I2C_UCRXIFG2      (0x000E)       /* Interrupt Vector: I2C Mode: UCRXIFG2 */
+#define USCI_I2C_UCTXIFG2      (0x0010)       /* Interrupt Vector: I2C Mode: UCTXIFG2 */
+#define USCI_I2C_UCRXIFG1      (0x0012)       /* Interrupt Vector: I2C Mode: UCRXIFG1 */
+#define USCI_I2C_UCTXIFG1      (0x0014)       /* Interrupt Vector: I2C Mode: UCTXIFG1 */
+#define USCI_I2C_UCRXIFG0      (0x0016)       /* Interrupt Vector: I2C Mode: UCRXIFG0 */
+#define USCI_I2C_UCTXIFG0      (0x0018)       /* Interrupt Vector: I2C Mode: UCTXIFG0 */
+#define USCI_I2C_UCBCNTIFG     (0x001A)       /* Interrupt Vector: I2C Mode: UCBCNTIFG */
+#define USCI_I2C_UCCLTOIFG     (0x001C)       /* Interrupt Vector: I2C Mode: UCCLTOIFG */
+#define USCI_I2C_UCBIT9IFG     (0x001E)       /* Interrupt Vector: I2C Mode: UCBIT9IFG */
+
+/************************************************************
+* WATCHDOG TIMER A
+************************************************************/
+#define __MSP430_HAS_WDT_A__                  /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_WDT_A__ 0x0150
+#define WDT_A_BASE             __MSP430_BASEADDRESS_WDT_A__
+
+sfr_w(WDTCTL);                                /* Watchdog Timer Control */
+sfr_b(WDTCTL_L);                              /* Watchdog Timer Control */
+sfr_b(WDTCTL_H);                              /* Watchdog Timer Control */
+/* The bit names have been prefixed with "WDT" */
+/* WDTCTL Control Bits */
+#define WDTIS0                 (0x0001)       /* WDT - Timer Interval Select 0 */
+#define WDTIS1                 (0x0002)       /* WDT - Timer Interval Select 1 */
+#define WDTIS2                 (0x0004)       /* WDT - Timer Interval Select 2 */
+#define WDTCNTCL               (0x0008)       /* WDT - Timer Clear */
+#define WDTTMSEL               (0x0010)       /* WDT - Timer Mode Select */
+#define WDTSSEL0               (0x0020)       /* WDT - Timer Clock Source Select 0 */
+#define WDTSSEL1               (0x0040)       /* WDT - Timer Clock Source Select 1 */
+#define WDTHOLD                (0x0080)       /* WDT - Timer hold */
+
+/* WDTCTL Control Bits */
+#define WDTIS0_L               (0x0001)       /* WDT - Timer Interval Select 0 */
+#define WDTIS1_L               (0x0002)       /* WDT - Timer Interval Select 1 */
+#define WDTIS2_L               (0x0004)       /* WDT - Timer Interval Select 2 */
+#define WDTCNTCL_L             (0x0008)       /* WDT - Timer Clear */
+#define WDTTMSEL_L             (0x0010)       /* WDT - Timer Mode Select */
+#define WDTSSEL0_L             (0x0020)       /* WDT - Timer Clock Source Select 0 */
+#define WDTSSEL1_L             (0x0040)       /* WDT - Timer Clock Source Select 1 */
+#define WDTHOLD_L              (0x0080)       /* WDT - Timer hold */
+
+#define WDTPW                  (0x5A00)
+
+#define WDTIS_0                (0x0000)       /* WDT - Timer Interval Select: /2G */
+#define WDTIS_1                (0x0001)       /* WDT - Timer Interval Select: /128M */
+#define WDTIS_2                (0x0002)       /* WDT - Timer Interval Select: /8192k */
+#define WDTIS_3                (0x0003)       /* WDT - Timer Interval Select: /512k */
+#define WDTIS_4                (0x0004)       /* WDT - Timer Interval Select: /32k */
+#define WDTIS_5                (0x0005)       /* WDT - Timer Interval Select: /8192 */
+#define WDTIS_6                (0x0006)       /* WDT - Timer Interval Select: /512 */
+#define WDTIS_7                (0x0007)       /* WDT - Timer Interval Select: /64 */
+#define WDTIS__2G              (0x0000)       /* WDT - Timer Interval Select: /2G */
+#define WDTIS__128M            (0x0001)       /* WDT - Timer Interval Select: /128M */
+#define WDTIS__8192K           (0x0002)       /* WDT - Timer Interval Select: /8192k */
+#define WDTIS__512K            (0x0003)       /* WDT - Timer Interval Select: /512k */
+#define WDTIS__32K             (0x0004)       /* WDT - Timer Interval Select: /32k */
+#define WDTIS__8192            (0x0005)       /* WDT - Timer Interval Select: /8192 */
+#define WDTIS__512             (0x0006)       /* WDT - Timer Interval Select: /512 */
+#define WDTIS__64              (0x0007)       /* WDT - Timer Interval Select: /64 */
+
+#define WDTSSEL_0              (0x0000)       /* WDT - Timer Clock Source Select: SMCLK */
+#define WDTSSEL_1              (0x0020)       /* WDT - Timer Clock Source Select: ACLK */
+#define WDTSSEL_2              (0x0040)       /* WDT - Timer Clock Source Select: VLO_CLK */
+#define WDTSSEL_3              (0x0060)       /* WDT - Timer Clock Source Select: reserved */
+#define WDTSSEL__SMCLK         (0x0000)       /* WDT - Timer Clock Source Select: SMCLK */
+#define WDTSSEL__ACLK          (0x0020)       /* WDT - Timer Clock Source Select: ACLK */
+#define WDTSSEL__VLO           (0x0040)       /* WDT - Timer Clock Source Select: VLO_CLK */
+
+/* WDT-interval times [1ms] coded with Bits 0-2 */
+/* WDT is clocked by fSMCLK (assumed 1MHz) */
+#define WDT_MDLY_32         (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2)                         /* 32ms interval (default) */
+#define WDT_MDLY_8          (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0)                  /* 8ms     " */
+#define WDT_MDLY_0_5        (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1)                  /* 0.5ms   " */
+#define WDT_MDLY_0_064      (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0)           /* 0.064ms " */
+/* WDT is clocked by fACLK (assumed 32KHz) */
+#define WDT_ADLY_1000       (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0)                /* 1000ms  " */
+#define WDT_ADLY_250        (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0)         /* 250ms   " */
+#define WDT_ADLY_16         (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1)         /* 16ms    " */
+#define WDT_ADLY_1_9        (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0)  /* 1.9ms   " */
+/* Watchdog mode -> reset after expired time */
+/* WDT is clocked by fSMCLK (assumed 1MHz) */
+#define WDT_MRST_32         (WDTPW+WDTCNTCL+WDTIS2)                                  /* 32ms interval (default) */
+#define WDT_MRST_8          (WDTPW+WDTCNTCL+WDTIS2+WDTIS0)                           /* 8ms     " */
+#define WDT_MRST_0_5        (WDTPW+WDTCNTCL+WDTIS2+WDTIS1)                           /* 0.5ms   " */
+#define WDT_MRST_0_064      (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0)                    /* 0.064ms " */
+/* WDT is clocked by fACLK (assumed 32KHz) */
+#define WDT_ARST_1000       (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2)                         /* 1000ms  " */
+#define WDT_ARST_250        (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0)                  /* 250ms   " */
+#define WDT_ARST_16         (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1)                  /* 16ms    " */
+#define WDT_ARST_1_9        (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0)           /* 1.9ms   " */
+
+
+/************************************************************
+* TLV Descriptors
+************************************************************/
+#define __MSP430_HAS_TLV__                    /* Definition to show that Module is available */
+#define TLV_BASE               __MSP430_BASEADDRESS_TLV__
+
+#define TLV_CRC_LENGTH         (0x1A01)       /* CRC length of the TLV structure */
+#define TLV_CRC_VALUE          (0x1A02)       /* CRC value of the TLV structure */
+#define TLV_START              (0x1A08)       /* Start Address of the TLV structure */
+#define TLV_END                (0x1AFF)       /* End Address of the TLV structure */
+
+#define TLV_LDTAG              (0x01)         /*  Legacy descriptor (1xx, 2xx, 4xx families) */
+#define TLV_PDTAG              (0x02)         /*  Peripheral discovery descriptor */
+#define TLV_Reserved3          (0x03)         /*  Future usage */
+#define TLV_Reserved4          (0x04)         /*  Future usage */
+#define TLV_BLANK              (0x05)         /*  Blank descriptor */
+#define TLV_Reserved6          (0x06)         /*  Future usage */
+#define TLV_Reserved7          (0x07)         /*  Serial Number */
+#define TLV_DIERECORD          (0x08)         /*  Die Record  */
+#define TLV_ADCCAL             (0x11)         /*  ADC12 calibration */
+#define TLV_ADC12CAL           (0x11)         /*  ADC12 calibration */
+#define TLV_ADC10CAL           (0x13)         /*  ADC10 calibration */
+#define TLV_REFCAL             (0x12)         /*  REF calibration */
+#define TLV_TAGEXT             (0xFE)         /*  Tag extender */
+#define TLV_TAGEND             (0xFF)         //  Tag End of Table
+
+/************************************************************
+* Interrupt Vectors (offset from 0xFF80 + 0x10 for Password)
+************************************************************/
+
+
+#define AES256_VECTOR           (28)                     /* 0xFFC6 AES256 */
+#define RTC_VECTOR              (29)                     /* 0xFFC8 RTC */
+#define LCD_C_VECTOR            (30)                     /* 0xFFCA LCD C */
+#define PORT4_VECTOR            (31)                     /* 0xFFCC Port 4 */
+#define PORT3_VECTOR            (32)                     /* 0xFFCE Port 3 */
+#define TIMER3_A1_VECTOR        (33)                     /* 0xFFD0 Timer3_A2 CC1, TA */
+#define TIMER3_A0_VECTOR        (34)                     /* 0xFFD2 Timer3_A2 CC0 */
+#define PORT2_VECTOR            (35)                     /* 0xFFD4 Port 2 */
+#define TIMER2_A1_VECTOR        (36)                     /* 0xFFD6 Timer2_A3 CC1, TA */
+#define TIMER2_A0_VECTOR        (37)                     /* 0xFFD8 Timer2_A3 CC0 */
+#define PORT1_VECTOR            (38)                     /* 0xFFDA Port 1 */
+#define TIMER1_A1_VECTOR        (39)                     /* 0xFFDC Timer1_A3 CC1-2, TA1 */
+#define TIMER1_A0_VECTOR        (40)                     /* 0xFFDE Timer1_A3 CC0 */
+#define DMA_VECTOR              (41)                     /* 0xFFE0 DMA */
+#define USCI_B1_VECTOR          (42)                     /* 0xFFE2 USCI B1 Receive/Transmit */
+#define USCI_A1_VECTOR          (43)                     /* 0xFFE4 USCI A1 Receive/Transmit */
+#define TIMER0_A1_VECTOR        (44)                     /* 0xFFE6 Timer0_A5 CC1-4, TA */
+#define TIMER0_A0_VECTOR        (45)                     /* 0xFFE8 Timer0_A5 CC0 */
+#define ADC12_VECTOR            (46)                     /* 0xFFEA ADC */
+#define USCI_B0_VECTOR          (47)                     /* 0xFFEC USCI B0 Receive/Transmit */
+#define USCI_A0_VECTOR          (48)                     /* 0xFFEE USCI A0 Receive/Transmit */
+#define ESCAN_IF_VECTOR         (49)                     /* 0xFFF0 Extended Scan IF */
+#define WDT_VECTOR              (50)                     /* 0xFFF2 Watchdog Timer */
+#define TIMER0_B1_VECTOR        (51)                     /* 0xFFF4 Timer0_B3 CC1-2, TB */
+#define TIMER0_B0_VECTOR        (52)                     /* 0xFFF6 Timer0_B3 CC0 */
+#define COMP_E_VECTOR           (53)                     /* 0xFFF8 Comparator E */
+#define UNMI_VECTOR             (54)                     /* 0xFFFA User Non-maskable */
+#define SYSNMI_VECTOR           (55)                     /* 0xFFFC System Non-maskable */
+#define RESET_VECTOR            ("reset")                /* 0xFFFE Reset [Highest Priority] */
+
+/************************************************************
+* End of Modules
+************************************************************/
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif /* #ifndef __MSP430FR6989 */
+
diff --git a/os/common/ext/TivaWare/inc/asmdefs.h b/os/common/ext/TivaWare/inc/asmdefs.h
new file mode 100644
index 0000000..062cb09
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/asmdefs.h
@@ -0,0 +1,227 @@
+//*****************************************************************************
+//
+// asmdefs.h - Macros to allow assembly code be portable among toolchains.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __ASMDEFS_H__
+#define __ASMDEFS_H__
+
+//*****************************************************************************
+//
+// The defines required for code_red.
+//
+//*****************************************************************************
+#ifdef codered
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+    .syntax unified
+    .thumb
+
+//
+// Section headers.
+//
+#define __LIBRARY__             @
+#define __TEXT__                .text
+#define __DATA__                .data
+#define __BSS__                 .bss
+#define __TEXT_NOROOT__         .text
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__               .balign 4
+#define __END__                 .end
+#define __EXPORT__              .globl
+#define __IMPORT__              .extern
+#define __LABEL__               :
+#define __STR__                 .ascii
+#define __THUMB_LABEL__         .thumb_func
+#define __WORD__                .word
+#define __INLINE_DATA__
+
+#endif // codered
+
+//*****************************************************************************
+//
+// The defines required for EW-ARM.
+//
+//*****************************************************************************
+#ifdef ewarm
+
+//
+// Section headers.
+//
+#define __LIBRARY__             module
+#define __TEXT__                rseg CODE:CODE(2)
+#define __DATA__                rseg DATA:DATA(2)
+#define __BSS__                 rseg DATA:DATA(2)
+#define __TEXT_NOROOT__         rseg CODE:CODE:NOROOT(2)
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__               alignrom 2
+#define __END__                 end
+#define __EXPORT__              export
+#define __IMPORT__              import
+#define __LABEL__
+#define __STR__                 dcb
+#define __THUMB_LABEL__         thumb
+#define __WORD__                dcd
+#define __INLINE_DATA__         data
+
+#endif // ewarm
+
+//*****************************************************************************
+//
+// The defines required for GCC.
+//
+//*****************************************************************************
+#if defined(gcc)
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+    .syntax unified
+    .thumb
+
+//
+// Section headers.
+//
+#define __LIBRARY__             @
+#define __TEXT__                .text
+#define __DATA__                .data
+#define __BSS__                 .bss
+#define __TEXT_NOROOT__         .text
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__               .balign 4
+#define __END__                 .end
+#define __EXPORT__              .globl
+#define __IMPORT__              .extern
+#define __LABEL__               :
+#define __STR__                 .ascii
+#define __THUMB_LABEL__         .thumb_func
+#define __WORD__                .word
+#define __INLINE_DATA__
+
+#endif // gcc
+
+//*****************************************************************************
+//
+// The defines required for RV-MDK.
+//
+//*****************************************************************************
+#ifdef rvmdk
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+    thumb
+    require8
+    preserve8
+
+//
+// Section headers.
+//
+#define __LIBRARY__             ;
+#define __TEXT__                area ||.text||, code, readonly, align=2
+#define __DATA__                area ||.data||, data, align=2
+#define __BSS__                 area ||.bss||, noinit, align=2
+#define __TEXT_NOROOT__         area ||.text||, code, readonly, align=2
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__               align 4
+#define __END__                 end
+#define __EXPORT__              export
+#define __IMPORT__              import
+#define __LABEL__
+#define __STR__                 dcb
+#define __THUMB_LABEL__
+#define __WORD__                dcd
+#define __INLINE_DATA__
+
+#endif // rvmdk
+
+//*****************************************************************************
+//
+// The defines required for Sourcery G++.
+//
+//*****************************************************************************
+#if defined(sourcerygxx)
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+    .syntax unified
+    .thumb
+
+//
+// Section headers.
+//
+#define __LIBRARY__             @
+#define __TEXT__                .text
+#define __DATA__                .data
+#define __BSS__                 .bss
+#define __TEXT_NOROOT__         .text
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__               .balign 4
+#define __END__                 .end
+#define __EXPORT__              .globl
+#define __IMPORT__              .extern
+#define __LABEL__               :
+#define __STR__                 .ascii
+#define __THUMB_LABEL__         .thumb_func
+#define __WORD__                .word
+#define __INLINE_DATA__
+
+#endif // sourcerygxx
+
+#endif // __ASMDEF_H__
diff --git a/os/common/ext/TivaWare/inc/hw_adc.h b/os/common/ext/TivaWare/inc/hw_adc.h
new file mode 100644
index 0000000..27a384f
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_adc.h
@@ -0,0 +1,1306 @@
+//*****************************************************************************
+//
+// hw_adc.h - Macros used when accessing the ADC hardware.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_ADC_H__
+#define __HW_ADC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the ADC register offsets.
+//
+//*****************************************************************************
+#define ADC_O_ACTSS             0x00000000  // ADC Active Sample Sequencer
+#define ADC_O_RIS               0x00000004  // ADC Raw Interrupt Status
+#define ADC_O_IM                0x00000008  // ADC Interrupt Mask
+#define ADC_O_ISC               0x0000000C  // ADC Interrupt Status and Clear
+#define ADC_O_OSTAT             0x00000010  // ADC Overflow Status
+#define ADC_O_EMUX              0x00000014  // ADC Event Multiplexer Select
+#define ADC_O_USTAT             0x00000018  // ADC Underflow Status
+#define ADC_O_TSSEL             0x0000001C  // ADC Trigger Source Select
+#define ADC_O_SSPRI             0x00000020  // ADC Sample Sequencer Priority
+#define ADC_O_SPC               0x00000024  // ADC Sample Phase Control
+#define ADC_O_PSSI              0x00000028  // ADC Processor Sample Sequence
+                                            // Initiate
+#define ADC_O_SAC               0x00000030  // ADC Sample Averaging Control
+#define ADC_O_DCISC             0x00000034  // ADC Digital Comparator Interrupt
+                                            // Status and Clear
+#define ADC_O_CTL               0x00000038  // ADC Control
+#define ADC_O_SSMUX0            0x00000040  // ADC Sample Sequence Input
+                                            // Multiplexer Select 0
+#define ADC_O_SSCTL0            0x00000044  // ADC Sample Sequence Control 0
+#define ADC_O_SSFIFO0           0x00000048  // ADC Sample Sequence Result FIFO
+                                            // 0
+#define ADC_O_SSFSTAT0          0x0000004C  // ADC Sample Sequence FIFO 0
+                                            // Status
+#define ADC_O_SSOP0             0x00000050  // ADC Sample Sequence 0 Operation
+#define ADC_O_SSDC0             0x00000054  // ADC Sample Sequence 0 Digital
+                                            // Comparator Select
+#define ADC_O_SSEMUX0           0x00000058  // ADC Sample Sequence Extended
+                                            // Input Multiplexer Select 0
+#define ADC_O_SSTSH0            0x0000005C  // ADC Sample Sequence 0 Sample and
+                                            // Hold Time
+#define ADC_O_SSMUX1            0x00000060  // ADC Sample Sequence Input
+                                            // Multiplexer Select 1
+#define ADC_O_SSCTL1            0x00000064  // ADC Sample Sequence Control 1
+#define ADC_O_SSFIFO1           0x00000068  // ADC Sample Sequence Result FIFO
+                                            // 1
+#define ADC_O_SSFSTAT1          0x0000006C  // ADC Sample Sequence FIFO 1
+                                            // Status
+#define ADC_O_SSOP1             0x00000070  // ADC Sample Sequence 1 Operation
+#define ADC_O_SSDC1             0x00000074  // ADC Sample Sequence 1 Digital
+                                            // Comparator Select
+#define ADC_O_SSEMUX1           0x00000078  // ADC Sample Sequence Extended
+                                            // Input Multiplexer Select 1
+#define ADC_O_SSTSH1            0x0000007C  // ADC Sample Sequence 1 Sample and
+                                            // Hold Time
+#define ADC_O_SSMUX2            0x00000080  // ADC Sample Sequence Input
+                                            // Multiplexer Select 2
+#define ADC_O_SSCTL2            0x00000084  // ADC Sample Sequence Control 2
+#define ADC_O_SSFIFO2           0x00000088  // ADC Sample Sequence Result FIFO
+                                            // 2
+#define ADC_O_SSFSTAT2          0x0000008C  // ADC Sample Sequence FIFO 2
+                                            // Status
+#define ADC_O_SSOP2             0x00000090  // ADC Sample Sequence 2 Operation
+#define ADC_O_SSDC2             0x00000094  // ADC Sample Sequence 2 Digital
+                                            // Comparator Select
+#define ADC_O_SSEMUX2           0x00000098  // ADC Sample Sequence Extended
+                                            // Input Multiplexer Select 2
+#define ADC_O_SSTSH2            0x0000009C  // ADC Sample Sequence 2 Sample and
+                                            // Hold Time
+#define ADC_O_SSMUX3            0x000000A0  // ADC Sample Sequence Input
+                                            // Multiplexer Select 3
+#define ADC_O_SSCTL3            0x000000A4  // ADC Sample Sequence Control 3
+#define ADC_O_SSFIFO3           0x000000A8  // ADC Sample Sequence Result FIFO
+                                            // 3
+#define ADC_O_SSFSTAT3          0x000000AC  // ADC Sample Sequence FIFO 3
+                                            // Status
+#define ADC_O_SSOP3             0x000000B0  // ADC Sample Sequence 3 Operation
+#define ADC_O_SSDC3             0x000000B4  // ADC Sample Sequence 3 Digital
+                                            // Comparator Select
+#define ADC_O_SSEMUX3           0x000000B8  // ADC Sample Sequence Extended
+                                            // Input Multiplexer Select 3
+#define ADC_O_SSTSH3            0x000000BC  // ADC Sample Sequence 3 Sample and
+                                            // Hold Time
+#define ADC_O_DCRIC             0x00000D00  // ADC Digital Comparator Reset
+                                            // Initial Conditions
+#define ADC_O_DCCTL0            0x00000E00  // ADC Digital Comparator Control 0
+#define ADC_O_DCCTL1            0x00000E04  // ADC Digital Comparator Control 1
+#define ADC_O_DCCTL2            0x00000E08  // ADC Digital Comparator Control 2
+#define ADC_O_DCCTL3            0x00000E0C  // ADC Digital Comparator Control 3
+#define ADC_O_DCCTL4            0x00000E10  // ADC Digital Comparator Control 4
+#define ADC_O_DCCTL5            0x00000E14  // ADC Digital Comparator Control 5
+#define ADC_O_DCCTL6            0x00000E18  // ADC Digital Comparator Control 6
+#define ADC_O_DCCTL7            0x00000E1C  // ADC Digital Comparator Control 7
+#define ADC_O_DCCMP0            0x00000E40  // ADC Digital Comparator Range 0
+#define ADC_O_DCCMP1            0x00000E44  // ADC Digital Comparator Range 1
+#define ADC_O_DCCMP2            0x00000E48  // ADC Digital Comparator Range 2
+#define ADC_O_DCCMP3            0x00000E4C  // ADC Digital Comparator Range 3
+#define ADC_O_DCCMP4            0x00000E50  // ADC Digital Comparator Range 4
+#define ADC_O_DCCMP5            0x00000E54  // ADC Digital Comparator Range 5
+#define ADC_O_DCCMP6            0x00000E58  // ADC Digital Comparator Range 6
+#define ADC_O_DCCMP7            0x00000E5C  // ADC Digital Comparator Range 7
+#define ADC_O_PP                0x00000FC0  // ADC Peripheral Properties
+#define ADC_O_PC                0x00000FC4  // ADC Peripheral Configuration
+#define ADC_O_CC                0x00000FC8  // ADC Clock Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ACTSS register.
+//
+//*****************************************************************************
+#define ADC_ACTSS_BUSY          0x00010000  // ADC Busy
+#define ADC_ACTSS_ADEN3         0x00000800  // ADC SS3 DMA Enable
+#define ADC_ACTSS_ADEN2         0x00000400  // ADC SS2 DMA Enable
+#define ADC_ACTSS_ADEN1         0x00000200  // ADC SS1 DMA Enable
+#define ADC_ACTSS_ADEN0         0x00000100  // ADC SS1 DMA Enable
+#define ADC_ACTSS_ASEN3         0x00000008  // ADC SS3 Enable
+#define ADC_ACTSS_ASEN2         0x00000004  // ADC SS2 Enable
+#define ADC_ACTSS_ASEN1         0x00000002  // ADC SS1 Enable
+#define ADC_ACTSS_ASEN0         0x00000001  // ADC SS0 Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_RIS register.
+//
+//*****************************************************************************
+#define ADC_RIS_INRDC           0x00010000  // Digital Comparator Raw Interrupt
+                                            // Status
+#define ADC_RIS_DMAINR3         0x00000800  // SS3 DMA Raw Interrupt Status
+#define ADC_RIS_DMAINR2         0x00000400  // SS2 DMA Raw Interrupt Status
+#define ADC_RIS_DMAINR1         0x00000200  // SS1 DMA Raw Interrupt Status
+#define ADC_RIS_DMAINR0         0x00000100  // SS0 DMA Raw Interrupt Status
+#define ADC_RIS_INR3            0x00000008  // SS3 Raw Interrupt Status
+#define ADC_RIS_INR2            0x00000004  // SS2 Raw Interrupt Status
+#define ADC_RIS_INR1            0x00000002  // SS1 Raw Interrupt Status
+#define ADC_RIS_INR0            0x00000001  // SS0 Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_IM register.
+//
+//*****************************************************************************
+#define ADC_IM_DCONSS3          0x00080000  // Digital Comparator Interrupt on
+                                            // SS3
+#define ADC_IM_DCONSS2          0x00040000  // Digital Comparator Interrupt on
+                                            // SS2
+#define ADC_IM_DCONSS1          0x00020000  // Digital Comparator Interrupt on
+                                            // SS1
+#define ADC_IM_DCONSS0          0x00010000  // Digital Comparator Interrupt on
+                                            // SS0
+#define ADC_IM_DMAMASK3         0x00000800  // SS3 DMA Interrupt Mask
+#define ADC_IM_DMAMASK2         0x00000400  // SS2 DMA Interrupt Mask
+#define ADC_IM_DMAMASK1         0x00000200  // SS1 DMA Interrupt Mask
+#define ADC_IM_DMAMASK0         0x00000100  // SS0 DMA Interrupt Mask
+#define ADC_IM_MASK3            0x00000008  // SS3 Interrupt Mask
+#define ADC_IM_MASK2            0x00000004  // SS2 Interrupt Mask
+#define ADC_IM_MASK1            0x00000002  // SS1 Interrupt Mask
+#define ADC_IM_MASK0            0x00000001  // SS0 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ISC register.
+//
+//*****************************************************************************
+#define ADC_ISC_DCINSS3         0x00080000  // Digital Comparator Interrupt
+                                            // Status on SS3
+#define ADC_ISC_DCINSS2         0x00040000  // Digital Comparator Interrupt
+                                            // Status on SS2
+#define ADC_ISC_DCINSS1         0x00020000  // Digital Comparator Interrupt
+                                            // Status on SS1
+#define ADC_ISC_DCINSS0         0x00010000  // Digital Comparator Interrupt
+                                            // Status on SS0
+#define ADC_ISC_DMAIN3          0x00000800  // SS3 DMA Interrupt Status and
+                                            // Clear
+#define ADC_ISC_DMAIN2          0x00000400  // SS2 DMA Interrupt Status and
+                                            // Clear
+#define ADC_ISC_DMAIN1          0x00000200  // SS1 DMA Interrupt Status and
+                                            // Clear
+#define ADC_ISC_DMAIN0          0x00000100  // SS0 DMA Interrupt Status and
+                                            // Clear
+#define ADC_ISC_IN3             0x00000008  // SS3 Interrupt Status and Clear
+#define ADC_ISC_IN2             0x00000004  // SS2 Interrupt Status and Clear
+#define ADC_ISC_IN1             0x00000002  // SS1 Interrupt Status and Clear
+#define ADC_ISC_IN0             0x00000001  // SS0 Interrupt Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_OSTAT register.
+//
+//*****************************************************************************
+#define ADC_OSTAT_OV3           0x00000008  // SS3 FIFO Overflow
+#define ADC_OSTAT_OV2           0x00000004  // SS2 FIFO Overflow
+#define ADC_OSTAT_OV1           0x00000002  // SS1 FIFO Overflow
+#define ADC_OSTAT_OV0           0x00000001  // SS0 FIFO Overflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_EMUX register.
+//
+//*****************************************************************************
+#define ADC_EMUX_EM3_M          0x0000F000  // SS3 Trigger Select
+#define ADC_EMUX_EM3_PROCESSOR  0x00000000  // Processor (default)
+#define ADC_EMUX_EM3_COMP0      0x00001000  // Analog Comparator 0
+#define ADC_EMUX_EM3_COMP1      0x00002000  // Analog Comparator 1
+#define ADC_EMUX_EM3_COMP2      0x00003000  // Analog Comparator 2
+#define ADC_EMUX_EM3_EXTERNAL   0x00004000  // External (GPIO Pins)
+#define ADC_EMUX_EM3_TIMER      0x00005000  // Timer
+#define ADC_EMUX_EM3_PWM0       0x00006000  // PWM generator 0
+#define ADC_EMUX_EM3_PWM1       0x00007000  // PWM generator 1
+#define ADC_EMUX_EM3_PWM2       0x00008000  // PWM generator 2
+#define ADC_EMUX_EM3_PWM3       0x00009000  // PWM generator 3
+#define ADC_EMUX_EM3_NEVER      0x0000E000  // Never Trigger
+#define ADC_EMUX_EM3_ALWAYS     0x0000F000  // Always (continuously sample)
+#define ADC_EMUX_EM2_M          0x00000F00  // SS2 Trigger Select
+#define ADC_EMUX_EM2_PROCESSOR  0x00000000  // Processor (default)
+#define ADC_EMUX_EM2_COMP0      0x00000100  // Analog Comparator 0
+#define ADC_EMUX_EM2_COMP1      0x00000200  // Analog Comparator 1
+#define ADC_EMUX_EM2_COMP2      0x00000300  // Analog Comparator 2
+#define ADC_EMUX_EM2_EXTERNAL   0x00000400  // External (GPIO Pins)
+#define ADC_EMUX_EM2_TIMER      0x00000500  // Timer
+#define ADC_EMUX_EM2_PWM0       0x00000600  // PWM generator 0
+#define ADC_EMUX_EM2_PWM1       0x00000700  // PWM generator 1
+#define ADC_EMUX_EM2_PWM2       0x00000800  // PWM generator 2
+#define ADC_EMUX_EM2_PWM3       0x00000900  // PWM generator 3
+#define ADC_EMUX_EM2_NEVER      0x00000E00  // Never Trigger
+#define ADC_EMUX_EM2_ALWAYS     0x00000F00  // Always (continuously sample)
+#define ADC_EMUX_EM1_M          0x000000F0  // SS1 Trigger Select
+#define ADC_EMUX_EM1_PROCESSOR  0x00000000  // Processor (default)
+#define ADC_EMUX_EM1_COMP0      0x00000010  // Analog Comparator 0
+#define ADC_EMUX_EM1_COMP1      0x00000020  // Analog Comparator 1
+#define ADC_EMUX_EM1_COMP2      0x00000030  // Analog Comparator 2
+#define ADC_EMUX_EM1_EXTERNAL   0x00000040  // External (GPIO Pins)
+#define ADC_EMUX_EM1_TIMER      0x00000050  // Timer
+#define ADC_EMUX_EM1_PWM0       0x00000060  // PWM generator 0
+#define ADC_EMUX_EM1_PWM1       0x00000070  // PWM generator 1
+#define ADC_EMUX_EM1_PWM2       0x00000080  // PWM generator 2
+#define ADC_EMUX_EM1_PWM3       0x00000090  // PWM generator 3
+#define ADC_EMUX_EM1_NEVER      0x000000E0  // Never Trigger
+#define ADC_EMUX_EM1_ALWAYS     0x000000F0  // Always (continuously sample)
+#define ADC_EMUX_EM0_M          0x0000000F  // SS0 Trigger Select
+#define ADC_EMUX_EM0_PROCESSOR  0x00000000  // Processor (default)
+#define ADC_EMUX_EM0_COMP0      0x00000001  // Analog Comparator 0
+#define ADC_EMUX_EM0_COMP1      0x00000002  // Analog Comparator 1
+#define ADC_EMUX_EM0_COMP2      0x00000003  // Analog Comparator 2
+#define ADC_EMUX_EM0_EXTERNAL   0x00000004  // External (GPIO Pins)
+#define ADC_EMUX_EM0_TIMER      0x00000005  // Timer
+#define ADC_EMUX_EM0_PWM0       0x00000006  // PWM generator 0
+#define ADC_EMUX_EM0_PWM1       0x00000007  // PWM generator 1
+#define ADC_EMUX_EM0_PWM2       0x00000008  // PWM generator 2
+#define ADC_EMUX_EM0_PWM3       0x00000009  // PWM generator 3
+#define ADC_EMUX_EM0_NEVER      0x0000000E  // Never Trigger
+#define ADC_EMUX_EM0_ALWAYS     0x0000000F  // Always (continuously sample)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_USTAT register.
+//
+//*****************************************************************************
+#define ADC_USTAT_UV3           0x00000008  // SS3 FIFO Underflow
+#define ADC_USTAT_UV2           0x00000004  // SS2 FIFO Underflow
+#define ADC_USTAT_UV1           0x00000002  // SS1 FIFO Underflow
+#define ADC_USTAT_UV0           0x00000001  // SS0 FIFO Underflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_TSSEL register.
+//
+//*****************************************************************************
+#define ADC_TSSEL_PS3_M         0x30000000  // Generator 3 PWM Module Trigger
+                                            // Select
+#define ADC_TSSEL_PS3_0         0x00000000  // Use Generator 3 (and its
+                                            // trigger) in PWM module 0
+#define ADC_TSSEL_PS3_1         0x10000000  // Use Generator 3 (and its
+                                            // trigger) in PWM module 1
+#define ADC_TSSEL_PS2_M         0x00300000  // Generator 2 PWM Module Trigger
+                                            // Select
+#define ADC_TSSEL_PS2_0         0x00000000  // Use Generator 2 (and its
+                                            // trigger) in PWM module 0
+#define ADC_TSSEL_PS2_1         0x00100000  // Use Generator 2 (and its
+                                            // trigger) in PWM module 1
+#define ADC_TSSEL_PS1_M         0x00003000  // Generator 1 PWM Module Trigger
+                                            // Select
+#define ADC_TSSEL_PS1_0         0x00000000  // Use Generator 1 (and its
+                                            // trigger) in PWM module 0
+#define ADC_TSSEL_PS1_1         0x00001000  // Use Generator 1 (and its
+                                            // trigger) in PWM module 1
+#define ADC_TSSEL_PS0_M         0x00000030  // Generator 0 PWM Module Trigger
+                                            // Select
+#define ADC_TSSEL_PS0_0         0x00000000  // Use Generator 0 (and its
+                                            // trigger) in PWM module 0
+#define ADC_TSSEL_PS0_1         0x00000010  // Use Generator 0 (and its
+                                            // trigger) in PWM module 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSPRI register.
+//
+//*****************************************************************************
+#define ADC_SSPRI_SS3_M         0x00003000  // SS3 Priority
+#define ADC_SSPRI_SS2_M         0x00000300  // SS2 Priority
+#define ADC_SSPRI_SS1_M         0x00000030  // SS1 Priority
+#define ADC_SSPRI_SS0_M         0x00000003  // SS0 Priority
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SPC register.
+//
+//*****************************************************************************
+#define ADC_SPC_PHASE_M         0x0000000F  // Phase Difference
+#define ADC_SPC_PHASE_0         0x00000000  // ADC sample lags by 0.0
+#define ADC_SPC_PHASE_22_5      0x00000001  // ADC sample lags by 22.5
+#define ADC_SPC_PHASE_45        0x00000002  // ADC sample lags by 45.0
+#define ADC_SPC_PHASE_67_5      0x00000003  // ADC sample lags by 67.5
+#define ADC_SPC_PHASE_90        0x00000004  // ADC sample lags by 90.0
+#define ADC_SPC_PHASE_112_5     0x00000005  // ADC sample lags by 112.5
+#define ADC_SPC_PHASE_135       0x00000006  // ADC sample lags by 135.0
+#define ADC_SPC_PHASE_157_5     0x00000007  // ADC sample lags by 157.5
+#define ADC_SPC_PHASE_180       0x00000008  // ADC sample lags by 180.0
+#define ADC_SPC_PHASE_202_5     0x00000009  // ADC sample lags by 202.5
+#define ADC_SPC_PHASE_225       0x0000000A  // ADC sample lags by 225.0
+#define ADC_SPC_PHASE_247_5     0x0000000B  // ADC sample lags by 247.5
+#define ADC_SPC_PHASE_270       0x0000000C  // ADC sample lags by 270.0
+#define ADC_SPC_PHASE_292_5     0x0000000D  // ADC sample lags by 292.5
+#define ADC_SPC_PHASE_315       0x0000000E  // ADC sample lags by 315.0
+#define ADC_SPC_PHASE_337_5     0x0000000F  // ADC sample lags by 337.5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PSSI register.
+//
+//*****************************************************************************
+#define ADC_PSSI_GSYNC          0x80000000  // Global Synchronize
+#define ADC_PSSI_SYNCWAIT       0x08000000  // Synchronize Wait
+#define ADC_PSSI_SS3            0x00000008  // SS3 Initiate
+#define ADC_PSSI_SS2            0x00000004  // SS2 Initiate
+#define ADC_PSSI_SS1            0x00000002  // SS1 Initiate
+#define ADC_PSSI_SS0            0x00000001  // SS0 Initiate
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SAC register.
+//
+//*****************************************************************************
+#define ADC_SAC_AVG_M           0x00000007  // Hardware Averaging Control
+#define ADC_SAC_AVG_OFF         0x00000000  // No hardware oversampling
+#define ADC_SAC_AVG_2X          0x00000001  // 2x hardware oversampling
+#define ADC_SAC_AVG_4X          0x00000002  // 4x hardware oversampling
+#define ADC_SAC_AVG_8X          0x00000003  // 8x hardware oversampling
+#define ADC_SAC_AVG_16X         0x00000004  // 16x hardware oversampling
+#define ADC_SAC_AVG_32X         0x00000005  // 32x hardware oversampling
+#define ADC_SAC_AVG_64X         0x00000006  // 64x hardware oversampling
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCISC register.
+//
+//*****************************************************************************
+#define ADC_DCISC_DCINT7        0x00000080  // Digital Comparator 7 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT6        0x00000040  // Digital Comparator 6 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT5        0x00000020  // Digital Comparator 5 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT4        0x00000010  // Digital Comparator 4 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT3        0x00000008  // Digital Comparator 3 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT2        0x00000004  // Digital Comparator 2 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT1        0x00000002  // Digital Comparator 1 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT0        0x00000001  // Digital Comparator 0 Interrupt
+                                            // Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_CTL register.
+//
+//*****************************************************************************
+#define ADC_CTL_VREF_M          0x00000003  // Voltage Reference Select
+#define ADC_CTL_VREF_INTERNAL   0x00000000  // VDDA and GNDA are the voltage
+                                            // references
+#define ADC_CTL_VREF_EXT_3V     0x00000001  // The external VREFA+ and VREFA-
+                                            // inputs are the voltage
+                                            // references
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX0 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX0_MUX7_M       0xF0000000  // 8th Sample Input Select
+#define ADC_SSMUX0_MUX6_M       0x0F000000  // 7th Sample Input Select
+#define ADC_SSMUX0_MUX5_M       0x00F00000  // 6th Sample Input Select
+#define ADC_SSMUX0_MUX4_M       0x000F0000  // 5th Sample Input Select
+#define ADC_SSMUX0_MUX3_M       0x0000F000  // 4th Sample Input Select
+#define ADC_SSMUX0_MUX2_M       0x00000F00  // 3rd Sample Input Select
+#define ADC_SSMUX0_MUX1_M       0x000000F0  // 2nd Sample Input Select
+#define ADC_SSMUX0_MUX0_M       0x0000000F  // 1st Sample Input Select
+#define ADC_SSMUX0_MUX7_S       28
+#define ADC_SSMUX0_MUX6_S       24
+#define ADC_SSMUX0_MUX5_S       20
+#define ADC_SSMUX0_MUX4_S       16
+#define ADC_SSMUX0_MUX3_S       12
+#define ADC_SSMUX0_MUX2_S       8
+#define ADC_SSMUX0_MUX1_S       4
+#define ADC_SSMUX0_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL0 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL0_TS7          0x80000000  // 8th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE7          0x40000000  // 8th Sample Interrupt Enable
+#define ADC_SSCTL0_END7         0x20000000  // 8th Sample is End of Sequence
+#define ADC_SSCTL0_D7           0x10000000  // 8th Sample Differential Input
+                                            // Select
+#define ADC_SSCTL0_TS6          0x08000000  // 7th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE6          0x04000000  // 7th Sample Interrupt Enable
+#define ADC_SSCTL0_END6         0x02000000  // 7th Sample is End of Sequence
+#define ADC_SSCTL0_D6           0x01000000  // 7th Sample Differential Input
+                                            // Select
+#define ADC_SSCTL0_TS5          0x00800000  // 6th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE5          0x00400000  // 6th Sample Interrupt Enable
+#define ADC_SSCTL0_END5         0x00200000  // 6th Sample is End of Sequence
+#define ADC_SSCTL0_D5           0x00100000  // 6th Sample Differential Input
+                                            // Select
+#define ADC_SSCTL0_TS4          0x00080000  // 5th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE4          0x00040000  // 5th Sample Interrupt Enable
+#define ADC_SSCTL0_END4         0x00020000  // 5th Sample is End of Sequence
+#define ADC_SSCTL0_D4           0x00010000  // 5th Sample Differential Input
+                                            // Select
+#define ADC_SSCTL0_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL0_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL0_D3           0x00001000  // 4th Sample Differential Input
+                                            // Select
+#define ADC_SSCTL0_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL0_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL0_D2           0x00000100  // 3rd Sample Differential Input
+                                            // Select
+#define ADC_SSCTL0_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL0_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL0_D1           0x00000010  // 2nd Sample Differential Input
+                                            // Select
+#define ADC_SSCTL0_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL0_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL0_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL0_D0           0x00000001  // 1st Sample Differential Input
+                                            // Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO0_DATA_M      0x00000FFF  // Conversion Result Data
+#define ADC_SSFIFO0_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT0_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT0_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT0_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT0_TPTR_M     0x0000000F  // FIFO Tail Pointer
+#define ADC_SSFSTAT0_HPTR_S     4
+#define ADC_SSFSTAT0_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP0 register.
+//
+//*****************************************************************************
+#define ADC_SSOP0_S7DCOP        0x10000000  // Sample 7 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S6DCOP        0x01000000  // Sample 6 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S5DCOP        0x00100000  // Sample 5 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S4DCOP        0x00010000  // Sample 4 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S3DCOP        0x00001000  // Sample 3 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S2DCOP        0x00000100  // Sample 2 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S1DCOP        0x00000010  // Sample 1 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S0DCOP        0x00000001  // Sample 0 Digital Comparator
+                                            // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC0 register.
+//
+//*****************************************************************************
+#define ADC_SSDC0_S7DCSEL_M     0xF0000000  // Sample 7 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S6DCSEL_M     0x0F000000  // Sample 6 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S5DCSEL_M     0x00F00000  // Sample 5 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S4DCSEL_M     0x000F0000  // Sample 4 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S3DCSEL_M     0x0000F000  // Sample 3 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S2DCSEL_M     0x00000F00  // Sample 2 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S1DCSEL_M     0x000000F0  // Sample 1 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S6DCSEL_S     24
+#define ADC_SSDC0_S5DCSEL_S     20
+#define ADC_SSDC0_S4DCSEL_S     16
+#define ADC_SSDC0_S3DCSEL_S     12
+#define ADC_SSDC0_S2DCSEL_S     8
+#define ADC_SSDC0_S1DCSEL_S     4
+#define ADC_SSDC0_S0DCSEL_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSEMUX0 register.
+//
+//*****************************************************************************
+#define ADC_SSEMUX0_EMUX7       0x10000000  // 8th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX0_EMUX6       0x01000000  // 7th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX0_EMUX5       0x00100000  // 6th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX0_EMUX4       0x00010000  // 5th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX0_EMUX3       0x00001000  // 4th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX0_EMUX2       0x00000100  // 3rd Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX0_EMUX1       0x00000010  // 2th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX0_EMUX0       0x00000001  // 1st Sample Input Select (Upper
+                                            // Bit)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSTSH0 register.
+//
+//*****************************************************************************
+#define ADC_SSTSH0_TSH7_M       0xF0000000  // 8th Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH0_TSH6_M       0x0F000000  // 7th Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH0_TSH5_M       0x00F00000  // 6th Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH0_TSH4_M       0x000F0000  // 5th Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH0_TSH3_M       0x0000F000  // 4th Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH0_TSH2_M       0x00000F00  // 3rd Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH0_TSH1_M       0x000000F0  // 2nd Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH0_TSH0_M       0x0000000F  // 1st Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH0_TSH7_S       28
+#define ADC_SSTSH0_TSH6_S       24
+#define ADC_SSTSH0_TSH5_S       20
+#define ADC_SSTSH0_TSH4_S       16
+#define ADC_SSTSH0_TSH3_S       12
+#define ADC_SSTSH0_TSH2_S       8
+#define ADC_SSTSH0_TSH1_S       4
+#define ADC_SSTSH0_TSH0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX1 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX1_MUX3_M       0x0000F000  // 4th Sample Input Select
+#define ADC_SSMUX1_MUX2_M       0x00000F00  // 3rd Sample Input Select
+#define ADC_SSMUX1_MUX1_M       0x000000F0  // 2nd Sample Input Select
+#define ADC_SSMUX1_MUX0_M       0x0000000F  // 1st Sample Input Select
+#define ADC_SSMUX1_MUX3_S       12
+#define ADC_SSMUX1_MUX2_S       8
+#define ADC_SSMUX1_MUX1_S       4
+#define ADC_SSMUX1_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL1 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL1_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL1_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL1_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL1_D3           0x00001000  // 4th Sample Differential Input
+                                            // Select
+#define ADC_SSCTL1_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL1_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL1_D2           0x00000100  // 3rd Sample Differential Input
+                                            // Select
+#define ADC_SSCTL1_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL1_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL1_D1           0x00000010  // 2nd Sample Differential Input
+                                            // Select
+#define ADC_SSCTL1_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL1_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL1_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL1_D0           0x00000001  // 1st Sample Differential Input
+                                            // Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO1_DATA_M      0x00000FFF  // Conversion Result Data
+#define ADC_SSFIFO1_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT1_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT1_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT1_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT1_TPTR_M     0x0000000F  // FIFO Tail Pointer
+#define ADC_SSFSTAT1_HPTR_S     4
+#define ADC_SSFSTAT1_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP1 register.
+//
+//*****************************************************************************
+#define ADC_SSOP1_S3DCOP        0x00001000  // Sample 3 Digital Comparator
+                                            // Operation
+#define ADC_SSOP1_S2DCOP        0x00000100  // Sample 2 Digital Comparator
+                                            // Operation
+#define ADC_SSOP1_S1DCOP        0x00000010  // Sample 1 Digital Comparator
+                                            // Operation
+#define ADC_SSOP1_S0DCOP        0x00000001  // Sample 0 Digital Comparator
+                                            // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC1 register.
+//
+//*****************************************************************************
+#define ADC_SSDC1_S3DCSEL_M     0x0000F000  // Sample 3 Digital Comparator
+                                            // Select
+#define ADC_SSDC1_S2DCSEL_M     0x00000F00  // Sample 2 Digital Comparator
+                                            // Select
+#define ADC_SSDC1_S1DCSEL_M     0x000000F0  // Sample 1 Digital Comparator
+                                            // Select
+#define ADC_SSDC1_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
+                                            // Select
+#define ADC_SSDC1_S2DCSEL_S     8
+#define ADC_SSDC1_S1DCSEL_S     4
+#define ADC_SSDC1_S0DCSEL_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSEMUX1 register.
+//
+//*****************************************************************************
+#define ADC_SSEMUX1_EMUX3       0x00001000  // 4th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX1_EMUX2       0x00000100  // 3rd Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX1_EMUX1       0x00000010  // 2th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX1_EMUX0       0x00000001  // 1st Sample Input Select (Upper
+                                            // Bit)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSTSH1 register.
+//
+//*****************************************************************************
+#define ADC_SSTSH1_TSH3_M       0x0000F000  // 4th Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH1_TSH2_M       0x00000F00  // 3rd Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH1_TSH1_M       0x000000F0  // 2nd Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH1_TSH0_M       0x0000000F  // 1st Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH1_TSH3_S       12
+#define ADC_SSTSH1_TSH2_S       8
+#define ADC_SSTSH1_TSH1_S       4
+#define ADC_SSTSH1_TSH0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX2_MUX3_M       0x0000F000  // 4th Sample Input Select
+#define ADC_SSMUX2_MUX2_M       0x00000F00  // 3rd Sample Input Select
+#define ADC_SSMUX2_MUX1_M       0x000000F0  // 2nd Sample Input Select
+#define ADC_SSMUX2_MUX0_M       0x0000000F  // 1st Sample Input Select
+#define ADC_SSMUX2_MUX3_S       12
+#define ADC_SSMUX2_MUX2_S       8
+#define ADC_SSMUX2_MUX1_S       4
+#define ADC_SSMUX2_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL2 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL2_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL2_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL2_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL2_D3           0x00001000  // 4th Sample Differential Input
+                                            // Select
+#define ADC_SSCTL2_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL2_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL2_D2           0x00000100  // 3rd Sample Differential Input
+                                            // Select
+#define ADC_SSCTL2_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL2_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL2_D1           0x00000010  // 2nd Sample Differential Input
+                                            // Select
+#define ADC_SSCTL2_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL2_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL2_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL2_D0           0x00000001  // 1st Sample Differential Input
+                                            // Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO2_DATA_M      0x00000FFF  // Conversion Result Data
+#define ADC_SSFIFO2_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT2_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT2_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT2_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT2_TPTR_M     0x0000000F  // FIFO Tail Pointer
+#define ADC_SSFSTAT2_HPTR_S     4
+#define ADC_SSFSTAT2_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP2 register.
+//
+//*****************************************************************************
+#define ADC_SSOP2_S3DCOP        0x00001000  // Sample 3 Digital Comparator
+                                            // Operation
+#define ADC_SSOP2_S2DCOP        0x00000100  // Sample 2 Digital Comparator
+                                            // Operation
+#define ADC_SSOP2_S1DCOP        0x00000010  // Sample 1 Digital Comparator
+                                            // Operation
+#define ADC_SSOP2_S0DCOP        0x00000001  // Sample 0 Digital Comparator
+                                            // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC2 register.
+//
+//*****************************************************************************
+#define ADC_SSDC2_S3DCSEL_M     0x0000F000  // Sample 3 Digital Comparator
+                                            // Select
+#define ADC_SSDC2_S2DCSEL_M     0x00000F00  // Sample 2 Digital Comparator
+                                            // Select
+#define ADC_SSDC2_S1DCSEL_M     0x000000F0  // Sample 1 Digital Comparator
+                                            // Select
+#define ADC_SSDC2_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
+                                            // Select
+#define ADC_SSDC2_S2DCSEL_S     8
+#define ADC_SSDC2_S1DCSEL_S     4
+#define ADC_SSDC2_S0DCSEL_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSEMUX2 register.
+//
+//*****************************************************************************
+#define ADC_SSEMUX2_EMUX3       0x00001000  // 4th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX2_EMUX2       0x00000100  // 3rd Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX2_EMUX1       0x00000010  // 2th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX2_EMUX0       0x00000001  // 1st Sample Input Select (Upper
+                                            // Bit)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSTSH2 register.
+//
+//*****************************************************************************
+#define ADC_SSTSH2_TSH3_M       0x0000F000  // 4th Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH2_TSH2_M       0x00000F00  // 3rd Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH2_TSH1_M       0x000000F0  // 2nd Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH2_TSH0_M       0x0000000F  // 1st Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH2_TSH3_S       12
+#define ADC_SSTSH2_TSH2_S       8
+#define ADC_SSTSH2_TSH1_S       4
+#define ADC_SSTSH2_TSH0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX3 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX3_MUX0_M       0x0000000F  // 1st Sample Input Select
+#define ADC_SSMUX3_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL3 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL3_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL3_IE0          0x00000004  // Sample Interrupt Enable
+#define ADC_SSCTL3_END0         0x00000002  // End of Sequence
+#define ADC_SSCTL3_D0           0x00000001  // Sample Differential Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO3_DATA_M      0x00000FFF  // Conversion Result Data
+#define ADC_SSFIFO3_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT3_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT3_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT3_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT3_TPTR_M     0x0000000F  // FIFO Tail Pointer
+#define ADC_SSFSTAT3_HPTR_S     4
+#define ADC_SSFSTAT3_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP3 register.
+//
+//*****************************************************************************
+#define ADC_SSOP3_S0DCOP        0x00000001  // Sample 0 Digital Comparator
+                                            // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC3 register.
+//
+//*****************************************************************************
+#define ADC_SSDC3_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
+                                            // Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSEMUX3 register.
+//
+//*****************************************************************************
+#define ADC_SSEMUX3_EMUX0       0x00000001  // 1st Sample Input Select (Upper
+                                            // Bit)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSTSH3 register.
+//
+//*****************************************************************************
+#define ADC_SSTSH3_TSH0_M       0x0000000F  // 1st Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH3_TSH0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCRIC register.
+//
+//*****************************************************************************
+#define ADC_DCRIC_DCTRIG7       0x00800000  // Digital Comparator Trigger 7
+#define ADC_DCRIC_DCTRIG6       0x00400000  // Digital Comparator Trigger 6
+#define ADC_DCRIC_DCTRIG5       0x00200000  // Digital Comparator Trigger 5
+#define ADC_DCRIC_DCTRIG4       0x00100000  // Digital Comparator Trigger 4
+#define ADC_DCRIC_DCTRIG3       0x00080000  // Digital Comparator Trigger 3
+#define ADC_DCRIC_DCTRIG2       0x00040000  // Digital Comparator Trigger 2
+#define ADC_DCRIC_DCTRIG1       0x00020000  // Digital Comparator Trigger 1
+#define ADC_DCRIC_DCTRIG0       0x00010000  // Digital Comparator Trigger 0
+#define ADC_DCRIC_DCINT7        0x00000080  // Digital Comparator Interrupt 7
+#define ADC_DCRIC_DCINT6        0x00000040  // Digital Comparator Interrupt 6
+#define ADC_DCRIC_DCINT5        0x00000020  // Digital Comparator Interrupt 5
+#define ADC_DCRIC_DCINT4        0x00000010  // Digital Comparator Interrupt 4
+#define ADC_DCRIC_DCINT3        0x00000008  // Digital Comparator Interrupt 3
+#define ADC_DCRIC_DCINT2        0x00000004  // Digital Comparator Interrupt 2
+#define ADC_DCRIC_DCINT1        0x00000002  // Digital Comparator Interrupt 1
+#define ADC_DCRIC_DCINT0        0x00000001  // Digital Comparator Interrupt 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL0 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL0_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL0_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL0_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL0_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL0_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL0_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL0_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL0_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL0_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL0_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL0_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL0_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL0_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL0_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL0_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL0_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL0_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL0_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL0_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL0_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL1 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL1_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL1_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL1_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL1_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL1_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL1_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL1_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL1_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL1_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL1_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL1_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL1_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL1_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL1_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL1_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL1_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL1_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL1_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL1_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL1_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL2 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL2_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL2_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL2_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL2_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL2_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL2_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL2_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL2_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL2_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL2_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL2_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL2_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL2_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL2_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL2_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL2_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL2_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL2_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL2_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL2_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL3 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL3_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL3_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL3_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL3_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL3_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL3_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL3_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL3_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL3_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL3_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL3_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL3_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL3_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL3_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL3_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL3_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL3_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL3_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL3_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL3_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL4 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL4_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL4_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL4_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL4_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL4_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL4_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL4_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL4_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL4_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL4_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL4_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL4_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL4_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL4_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL4_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL4_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL4_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL4_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL4_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL4_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL5 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL5_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL5_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL5_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL5_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL5_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL5_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL5_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL5_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL5_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL5_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL5_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL5_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL5_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL5_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL5_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL5_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL5_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL5_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL5_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL5_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL6 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL6_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL6_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL6_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL6_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL6_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL6_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL6_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL6_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL6_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL6_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL6_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL6_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL6_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL6_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL6_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL6_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL6_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL6_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL6_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL6_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL7 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL7_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL7_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL7_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL7_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL7_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL7_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL7_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL7_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL7_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL7_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL7_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL7_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL7_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL7_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL7_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL7_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL7_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL7_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL7_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL7_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP0 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP0_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP0_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP0_COMP1_S      16
+#define ADC_DCCMP0_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP1 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP1_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP1_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP1_COMP1_S      16
+#define ADC_DCCMP1_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP2 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP2_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP2_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP2_COMP1_S      16
+#define ADC_DCCMP2_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP3 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP3_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP3_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP3_COMP1_S      16
+#define ADC_DCCMP3_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP4 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP4_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP4_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP4_COMP1_S      16
+#define ADC_DCCMP4_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP5 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP5_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP5_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP5_COMP1_S      16
+#define ADC_DCCMP5_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP6 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP6_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP6_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP6_COMP1_S      16
+#define ADC_DCCMP6_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP7 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP7_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP7_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP7_COMP1_S      16
+#define ADC_DCCMP7_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PP register.
+//
+//*****************************************************************************
+#define ADC_PP_APSHT            0x01000000  // Application-Programmable
+                                            // Sample-and-Hold Time
+#define ADC_PP_TS               0x00800000  // Temperature Sensor
+#define ADC_PP_RSL_M            0x007C0000  // Resolution
+#define ADC_PP_TYPE_M           0x00030000  // ADC Architecture
+#define ADC_PP_TYPE_SAR         0x00000000  // SAR
+#define ADC_PP_DC_M             0x0000FC00  // Digital Comparator Count
+#define ADC_PP_CH_M             0x000003F0  // ADC Channel Count
+#define ADC_PP_MCR_M            0x0000000F  // Maximum Conversion Rate
+#define ADC_PP_MCR_FULL         0x00000007  // Full conversion rate (FCONV) as
+                                            // defined by TADC and NSH
+#define ADC_PP_MSR_M            0x0000000F  // Maximum ADC Sample Rate
+#define ADC_PP_MSR_125K         0x00000001  // 125 ksps
+#define ADC_PP_MSR_250K         0x00000003  // 250 ksps
+#define ADC_PP_MSR_500K         0x00000005  // 500 ksps
+#define ADC_PP_MSR_1M           0x00000007  // 1 Msps
+#define ADC_PP_RSL_S            18
+#define ADC_PP_DC_S             10
+#define ADC_PP_CH_S             4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PC register.
+//
+//*****************************************************************************
+#define ADC_PC_SR_M             0x0000000F  // ADC Sample Rate
+#define ADC_PC_SR_125K          0x00000001  // 125 ksps
+#define ADC_PC_SR_250K          0x00000003  // 250 ksps
+#define ADC_PC_SR_500K          0x00000005  // 500 ksps
+#define ADC_PC_SR_1M            0x00000007  // 1 Msps
+#define ADC_PC_MCR_M            0x0000000F  // Conversion Rate
+#define ADC_PC_MCR_1_8          0x00000001  // Eighth conversion rate. After a
+                                            // conversion completes, the logic
+                                            // pauses for 112 TADC periods
+                                            // before starting the next
+                                            // conversion
+#define ADC_PC_MCR_1_4          0x00000003  // Quarter conversion rate. After a
+                                            // conversion completes, the logic
+                                            // pauses for 48 TADC periods
+                                            // before starting the next
+                                            // conversion
+#define ADC_PC_MCR_1_2          0x00000005  // Half conversion rate. After a
+                                            // conversion completes, the logic
+                                            // pauses for 16 TADC periods
+                                            // before starting the next
+                                            // conversion
+#define ADC_PC_MCR_FULL         0x00000007  // Full conversion rate (FCONV) as
+                                            // defined by TADC and NSH
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_CC register.
+//
+//*****************************************************************************
+#define ADC_CC_CLKDIV_M         0x000003F0  // PLL VCO Clock Divisor
+#define ADC_CC_CS_M             0x0000000F  // ADC Clock Source
+#define ADC_CC_CS_SYSPLL        0x00000000  // PLL VCO divided by CLKDIV
+#define ADC_CC_CS_PIOSC         0x00000001  // PIOSC
+#define ADC_CC_CS_MOSC          0x00000002  // MOSC
+#define ADC_CC_CLKDIV_S         4
+
+#endif // __HW_ADC_H__
diff --git a/os/common/ext/TivaWare/inc/hw_aes.h b/os/common/ext/TivaWare/inc/hw_aes.h
new file mode 100644
index 0000000..49dda1e
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_aes.h
@@ -0,0 +1,545 @@
+//*****************************************************************************
+//
+// hw_aes.h - Macros used when accessing the AES hardware.
+//
+// Copyright (c) 2012-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_AES_H__
+#define __HW_AES_H__
+
+//*****************************************************************************
+//
+// The following are defines for the AES register offsets.
+//
+//*****************************************************************************
+#define AES_O_KEY2_6            0x00000000  // AES Key 2_6
+#define AES_O_KEY2_7            0x00000004  // AES Key 2_7
+#define AES_O_KEY2_4            0x00000008  // AES Key 2_4
+#define AES_O_KEY2_5            0x0000000C  // AES Key 2_5
+#define AES_O_KEY2_2            0x00000010  // AES Key 2_2
+#define AES_O_KEY2_3            0x00000014  // AES Key 2_3
+#define AES_O_KEY2_0            0x00000018  // AES Key 2_0
+#define AES_O_KEY2_1            0x0000001C  // AES Key 2_1
+#define AES_O_KEY1_6            0x00000020  // AES Key 1_6
+#define AES_O_KEY1_7            0x00000024  // AES Key 1_7
+#define AES_O_KEY1_4            0x00000028  // AES Key 1_4
+#define AES_O_KEY1_5            0x0000002C  // AES Key 1_5
+#define AES_O_KEY1_2            0x00000030  // AES Key 1_2
+#define AES_O_KEY1_3            0x00000034  // AES Key 1_3
+#define AES_O_KEY1_0            0x00000038  // AES Key 1_0
+#define AES_O_KEY1_1            0x0000003C  // AES Key 1_1
+#define AES_O_IV_IN_0           0x00000040  // AES Initialization Vector Input
+                                            // 0
+#define AES_O_IV_IN_1           0x00000044  // AES Initialization Vector Input
+                                            // 1
+#define AES_O_IV_IN_2           0x00000048  // AES Initialization Vector Input
+                                            // 2
+#define AES_O_IV_IN_3           0x0000004C  // AES Initialization Vector Input
+                                            // 3
+#define AES_O_CTRL              0x00000050  // AES Control
+#define AES_O_C_LENGTH_0        0x00000054  // AES Crypto Data Length 0
+#define AES_O_C_LENGTH_1        0x00000058  // AES Crypto Data Length 1
+#define AES_O_AUTH_LENGTH       0x0000005C  // AES Authentication Data Length
+#define AES_O_DATA_IN_0         0x00000060  // AES Data RW Plaintext/Ciphertext
+                                            // 0
+#define AES_O_DATA_IN_1         0x00000064  // AES Data RW Plaintext/Ciphertext
+                                            // 1
+#define AES_O_DATA_IN_2         0x00000068  // AES Data RW Plaintext/Ciphertext
+                                            // 2
+#define AES_O_DATA_IN_3         0x0000006C  // AES Data RW Plaintext/Ciphertext
+                                            // 3
+#define AES_O_TAG_OUT_0         0x00000070  // AES Hash Tag Out 0
+#define AES_O_TAG_OUT_1         0x00000074  // AES Hash Tag Out 1
+#define AES_O_TAG_OUT_2         0x00000078  // AES Hash Tag Out 2
+#define AES_O_TAG_OUT_3         0x0000007C  // AES Hash Tag Out 3
+#define AES_O_REVISION          0x00000080  // AES IP Revision Identifier
+#define AES_O_SYSCONFIG         0x00000084  // AES System Configuration
+#define AES_O_SYSSTATUS         0x00000088  // AES System Status
+#define AES_O_IRQSTATUS         0x0000008C  // AES Interrupt Status
+#define AES_O_IRQENABLE         0x00000090  // AES Interrupt Enable
+#define AES_O_DIRTYBITS         0x00000094  // AES Dirty Bits
+#define AES_O_DMAIM             0xFFFFA020  // AES DMA Interrupt Mask
+#define AES_O_DMARIS            0xFFFFA024  // AES DMA Raw Interrupt Status
+#define AES_O_DMAMIS            0xFFFFA028  // AES DMA Masked Interrupt Status
+#define AES_O_DMAIC             0xFFFFA02C  // AES DMA Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_6 register.
+//
+//*****************************************************************************
+#define AES_KEY2_6_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY2_6_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_7 register.
+//
+//*****************************************************************************
+#define AES_KEY2_7_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY2_7_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_4 register.
+//
+//*****************************************************************************
+#define AES_KEY2_4_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY2_4_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_5 register.
+//
+//*****************************************************************************
+#define AES_KEY2_5_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY2_5_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_2 register.
+//
+//*****************************************************************************
+#define AES_KEY2_2_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY2_2_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_3 register.
+//
+//*****************************************************************************
+#define AES_KEY2_3_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY2_3_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_0 register.
+//
+//*****************************************************************************
+#define AES_KEY2_0_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY2_0_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_1 register.
+//
+//*****************************************************************************
+#define AES_KEY2_1_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY2_1_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_6 register.
+//
+//*****************************************************************************
+#define AES_KEY1_6_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY1_6_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_7 register.
+//
+//*****************************************************************************
+#define AES_KEY1_7_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY1_7_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_4 register.
+//
+//*****************************************************************************
+#define AES_KEY1_4_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY1_4_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_5 register.
+//
+//*****************************************************************************
+#define AES_KEY1_5_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY1_5_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_2 register.
+//
+//*****************************************************************************
+#define AES_KEY1_2_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY1_2_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_3 register.
+//
+//*****************************************************************************
+#define AES_KEY1_3_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY1_3_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_0 register.
+//
+//*****************************************************************************
+#define AES_KEY1_0_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY1_0_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_1 register.
+//
+//*****************************************************************************
+#define AES_KEY1_1_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY1_1_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IV_IN_0 register.
+//
+//*****************************************************************************
+#define AES_IV_IN_0_DATA_M      0xFFFFFFFF  // Initialization Vector Input
+#define AES_IV_IN_0_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IV_IN_1 register.
+//
+//*****************************************************************************
+#define AES_IV_IN_1_DATA_M      0xFFFFFFFF  // Initialization Vector Input
+#define AES_IV_IN_1_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IV_IN_2 register.
+//
+//*****************************************************************************
+#define AES_IV_IN_2_DATA_M      0xFFFFFFFF  // Initialization Vector Input
+#define AES_IV_IN_2_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IV_IN_3 register.
+//
+//*****************************************************************************
+#define AES_IV_IN_3_DATA_M      0xFFFFFFFF  // Initialization Vector Input
+#define AES_IV_IN_3_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_CTRL register.
+//
+//*****************************************************************************
+#define AES_CTRL_CTXTRDY        0x80000000  // Context Data Registers Ready
+#define AES_CTRL_SVCTXTRDY      0x40000000  // AES TAG/IV Block(s) Ready
+#define AES_CTRL_SAVE_CONTEXT   0x20000000  // TAG or Result IV Save
+#define AES_CTRL_CCM_M_M        0x01C00000  // Counter with CBC-MAC (CCM)
+#define AES_CTRL_CCM_L_M        0x00380000  // L Value
+#define AES_CTRL_CCM_L_2        0x00080000  // width = 2
+#define AES_CTRL_CCM_L_4        0x00180000  // width = 4
+#define AES_CTRL_CCM_L_8        0x00380000  // width = 8
+#define AES_CTRL_CCM            0x00040000  // AES-CCM Mode Enable
+#define AES_CTRL_GCM_M          0x00030000  // AES-GCM Mode Enable
+#define AES_CTRL_GCM_NOP        0x00000000  // No operation
+#define AES_CTRL_GCM_HLY0ZERO   0x00010000  // GHASH with H loaded and
+                                            // Y0-encrypted forced to zero
+#define AES_CTRL_GCM_HLY0CALC   0x00020000  // GHASH with H loaded and
+                                            // Y0-encrypted calculated
+                                            // internally
+#define AES_CTRL_GCM_HY0CALC    0x00030000  // Autonomous GHASH (both H and
+                                            // Y0-encrypted calculated
+                                            // internally)
+#define AES_CTRL_CBCMAC         0x00008000  // AES-CBC MAC Enable
+#define AES_CTRL_F9             0x00004000  // AES f9 Mode Enable
+#define AES_CTRL_F8             0x00002000  // AES f8 Mode Enable
+#define AES_CTRL_XTS_M          0x00001800  // AES-XTS Operation Enabled
+#define AES_CTRL_XTS_NOP        0x00000000  // No operation
+#define AES_CTRL_XTS_TWEAKJL    0x00000800  // Previous/intermediate tweak
+                                            // value and j loaded (value is
+                                            // loaded via IV, j is loaded via
+                                            // the AAD length register)
+#define AES_CTRL_XTS_K2IJL      0x00001000  // Key2, n and j are loaded (n is
+                                            // loaded via IV, j is loaded via
+                                            // the AAD length register)
+#define AES_CTRL_XTS_K2ILJ0     0x00001800  // Key2 and n are loaded; j=0 (n is
+                                            // loaded via IV)
+#define AES_CTRL_CFB            0x00000400  // Full block AES cipher feedback
+                                            // mode (CFB128) Enable
+#define AES_CTRL_ICM            0x00000200  // AES Integer Counter Mode (ICM)
+                                            // Enable
+#define AES_CTRL_CTR_WIDTH_M    0x00000180  // AES-CTR Mode Counter Width
+#define AES_CTRL_CTR_WIDTH_32   0x00000000  // Counter is 32 bits
+#define AES_CTRL_CTR_WIDTH_64   0x00000080  // Counter is 64 bits
+#define AES_CTRL_CTR_WIDTH_96   0x00000100  // Counter is 96 bits
+#define AES_CTRL_CTR_WIDTH_128  0x00000180  // Counter is 128 bits
+#define AES_CTRL_CTR            0x00000040  // Counter Mode
+#define AES_CTRL_MODE           0x00000020  // ECB/CBC Mode
+#define AES_CTRL_KEY_SIZE_M     0x00000018  // Key Size
+#define AES_CTRL_KEY_SIZE_128   0x00000008  // Key is 128 bits
+#define AES_CTRL_KEY_SIZE_192   0x00000010  // Key is 192 bits
+#define AES_CTRL_KEY_SIZE_256   0x00000018  // Key is 256 bits
+#define AES_CTRL_DIRECTION      0x00000004  // Encryption/Decryption Selection
+#define AES_CTRL_INPUT_READY    0x00000002  // Input Ready Status
+#define AES_CTRL_OUTPUT_READY   0x00000001  // Output Ready Status
+#define AES_CTRL_CCM_M_S        22
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_C_LENGTH_0
+// register.
+//
+//*****************************************************************************
+#define AES_C_LENGTH_0_LENGTH_M 0xFFFFFFFF  // Data Length
+#define AES_C_LENGTH_0_LENGTH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_C_LENGTH_1
+// register.
+//
+//*****************************************************************************
+#define AES_C_LENGTH_1_LENGTH_M 0xFFFFFFFF  // Data Length
+#define AES_C_LENGTH_1_LENGTH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_AUTH_LENGTH
+// register.
+//
+//*****************************************************************************
+#define AES_AUTH_LENGTH_AUTH_M  0xFFFFFFFF  // Authentication Data Length
+#define AES_AUTH_LENGTH_AUTH_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DATA_IN_0
+// register.
+//
+//*****************************************************************************
+#define AES_DATA_IN_0_DATA_M    0xFFFFFFFF  // Secure Data RW
+                                            // Plaintext/Ciphertext
+#define AES_DATA_IN_0_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DATA_IN_1
+// register.
+//
+//*****************************************************************************
+#define AES_DATA_IN_1_DATA_M    0xFFFFFFFF  // Secure Data RW
+                                            // Plaintext/Ciphertext
+#define AES_DATA_IN_1_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DATA_IN_2
+// register.
+//
+//*****************************************************************************
+#define AES_DATA_IN_2_DATA_M    0xFFFFFFFF  // Secure Data RW
+                                            // Plaintext/Ciphertext
+#define AES_DATA_IN_2_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DATA_IN_3
+// register.
+//
+//*****************************************************************************
+#define AES_DATA_IN_3_DATA_M    0xFFFFFFFF  // Secure Data RW
+                                            // Plaintext/Ciphertext
+#define AES_DATA_IN_3_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_TAG_OUT_0
+// register.
+//
+//*****************************************************************************
+#define AES_TAG_OUT_0_HASH_M    0xFFFFFFFF  // Hash Result
+#define AES_TAG_OUT_0_HASH_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_TAG_OUT_1
+// register.
+//
+//*****************************************************************************
+#define AES_TAG_OUT_1_HASH_M    0xFFFFFFFF  // Hash Result
+#define AES_TAG_OUT_1_HASH_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_TAG_OUT_2
+// register.
+//
+//*****************************************************************************
+#define AES_TAG_OUT_2_HASH_M    0xFFFFFFFF  // Hash Result
+#define AES_TAG_OUT_2_HASH_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_TAG_OUT_3
+// register.
+//
+//*****************************************************************************
+#define AES_TAG_OUT_3_HASH_M    0xFFFFFFFF  // Hash Result
+#define AES_TAG_OUT_3_HASH_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_REVISION register.
+//
+//*****************************************************************************
+#define AES_REVISION_M          0xFFFFFFFF  // Revision number
+#define AES_REVISION_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_SYSCONFIG
+// register.
+//
+//*****************************************************************************
+#define AES_SYSCONFIG_K3        0x00001000  // K3 Select
+#define AES_SYSCONFIG_KEYENC    0x00000800  // Key Encoding
+#define AES_SYSCONFIG_MAP_CONTEXT_OUT_ON_DATA_OUT                             \
+                                0x00000200  // Map Context Out on Data Out
+                                            // Enable
+#define AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN                                  \
+                                0x00000100  // DMA Request Context Out Enable
+#define AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN                                   \
+                                0x00000080  // DMA Request Context In Enable
+#define AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN                                     \
+                                0x00000040  // DMA Request Data Out Enable
+#define AES_SYSCONFIG_DMA_REQ_DATA_IN_EN                                      \
+                                0x00000020  // DMA Request Data In Enable
+#define AES_SYSCONFIG_SOFTRESET 0x00000002  // Soft reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_SYSSTATUS
+// register.
+//
+//*****************************************************************************
+#define AES_SYSSTATUS_RESETDONE 0x00000001  // Reset Done
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IRQSTATUS
+// register.
+//
+//*****************************************************************************
+#define AES_IRQSTATUS_CONTEXT_OUT                                             \
+                                0x00000008  // Context Output Interrupt Status
+#define AES_IRQSTATUS_DATA_OUT  0x00000004  // Data Out Interrupt Status
+#define AES_IRQSTATUS_DATA_IN   0x00000002  // Data In Interrupt Status
+#define AES_IRQSTATUS_CONTEXT_IN                                              \
+                                0x00000001  // Context In Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IRQENABLE
+// register.
+//
+//*****************************************************************************
+#define AES_IRQENABLE_CONTEXT_OUT                                             \
+                                0x00000008  // Context Out Interrupt Enable
+#define AES_IRQENABLE_DATA_OUT  0x00000004  // Data Out Interrupt Enable
+#define AES_IRQENABLE_DATA_IN   0x00000002  // Data In Interrupt Enable
+#define AES_IRQENABLE_CONTEXT_IN                                              \
+                                0x00000001  // Context In Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DIRTYBITS
+// register.
+//
+//*****************************************************************************
+#define AES_DIRTYBITS_S_DIRTY   0x00000002  // AES Dirty Bit
+#define AES_DIRTYBITS_S_ACCESS  0x00000001  // AES Access Bit
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DMAIM register.
+//
+//*****************************************************************************
+#define AES_DMAIM_DOUT          0x00000008  // Data Out DMA Done Interrupt Mask
+#define AES_DMAIM_DIN           0x00000004  // Data In DMA Done Interrupt Mask
+#define AES_DMAIM_COUT          0x00000002  // Context Out DMA Done Interrupt
+                                            // Mask
+#define AES_DMAIM_CIN           0x00000001  // Context In DMA Done Interrupt
+                                            // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DMARIS register.
+//
+//*****************************************************************************
+#define AES_DMARIS_DOUT         0x00000008  // Data Out DMA Done Raw Interrupt
+                                            // Status
+#define AES_DMARIS_DIN          0x00000004  // Data In DMA Done Raw Interrupt
+                                            // Status
+#define AES_DMARIS_COUT         0x00000002  // Context Out DMA Done Raw
+                                            // Interrupt Status
+#define AES_DMARIS_CIN          0x00000001  // Context In DMA Done Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DMAMIS register.
+//
+//*****************************************************************************
+#define AES_DMAMIS_DOUT         0x00000008  // Data Out DMA Done Masked
+                                            // Interrupt Status
+#define AES_DMAMIS_DIN          0x00000004  // Data In DMA Done Masked
+                                            // Interrupt Status
+#define AES_DMAMIS_COUT         0x00000002  // Context Out DMA Done Masked
+                                            // Interrupt Status
+#define AES_DMAMIS_CIN          0x00000001  // Context In DMA Done Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DMAIC register.
+//
+//*****************************************************************************
+#define AES_DMAIC_DOUT          0x00000008  // Data Out DMA Done Interrupt
+                                            // Clear
+#define AES_DMAIC_DIN           0x00000004  // Data In DMA Done Interrupt Clear
+#define AES_DMAIC_COUT          0x00000002  // Context Out DMA Done Masked
+                                            // Interrupt Status
+#define AES_DMAIC_CIN           0x00000001  // Context In DMA Done Raw
+                                            // Interrupt Status
+
+#endif // __HW_AES_H__
diff --git a/os/common/ext/TivaWare/inc/hw_can.h b/os/common/ext/TivaWare/inc/hw_can.h
new file mode 100644
index 0000000..a683e67
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_can.h
@@ -0,0 +1,462 @@
+//*****************************************************************************
+//
+// hw_can.h - Defines and macros used when accessing the CAN controllers.
+//
+// Copyright (c) 2006-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_CAN_H__
+#define __HW_CAN_H__
+
+//*****************************************************************************
+//
+// The following are defines for the CAN register offsets.
+//
+//*****************************************************************************
+#define CAN_O_CTL               0x00000000  // CAN Control
+#define CAN_O_STS               0x00000004  // CAN Status
+#define CAN_O_ERR               0x00000008  // CAN Error Counter
+#define CAN_O_BIT               0x0000000C  // CAN Bit Timing
+#define CAN_O_INT               0x00000010  // CAN Interrupt
+#define CAN_O_TST               0x00000014  // CAN Test
+#define CAN_O_BRPE              0x00000018  // CAN Baud Rate Prescaler
+                                            // Extension
+#define CAN_O_IF1CRQ            0x00000020  // CAN IF1 Command Request
+#define CAN_O_IF1CMSK           0x00000024  // CAN IF1 Command Mask
+#define CAN_O_IF1MSK1           0x00000028  // CAN IF1 Mask 1
+#define CAN_O_IF1MSK2           0x0000002C  // CAN IF1 Mask 2
+#define CAN_O_IF1ARB1           0x00000030  // CAN IF1 Arbitration 1
+#define CAN_O_IF1ARB2           0x00000034  // CAN IF1 Arbitration 2
+#define CAN_O_IF1MCTL           0x00000038  // CAN IF1 Message Control
+#define CAN_O_IF1DA1            0x0000003C  // CAN IF1 Data A1
+#define CAN_O_IF1DA2            0x00000040  // CAN IF1 Data A2
+#define CAN_O_IF1DB1            0x00000044  // CAN IF1 Data B1
+#define CAN_O_IF1DB2            0x00000048  // CAN IF1 Data B2
+#define CAN_O_IF2CRQ            0x00000080  // CAN IF2 Command Request
+#define CAN_O_IF2CMSK           0x00000084  // CAN IF2 Command Mask
+#define CAN_O_IF2MSK1           0x00000088  // CAN IF2 Mask 1
+#define CAN_O_IF2MSK2           0x0000008C  // CAN IF2 Mask 2
+#define CAN_O_IF2ARB1           0x00000090  // CAN IF2 Arbitration 1
+#define CAN_O_IF2ARB2           0x00000094  // CAN IF2 Arbitration 2
+#define CAN_O_IF2MCTL           0x00000098  // CAN IF2 Message Control
+#define CAN_O_IF2DA1            0x0000009C  // CAN IF2 Data A1
+#define CAN_O_IF2DA2            0x000000A0  // CAN IF2 Data A2
+#define CAN_O_IF2DB1            0x000000A4  // CAN IF2 Data B1
+#define CAN_O_IF2DB2            0x000000A8  // CAN IF2 Data B2
+#define CAN_O_TXRQ1             0x00000100  // CAN Transmission Request 1
+#define CAN_O_TXRQ2             0x00000104  // CAN Transmission Request 2
+#define CAN_O_NWDA1             0x00000120  // CAN New Data 1
+#define CAN_O_NWDA2             0x00000124  // CAN New Data 2
+#define CAN_O_MSG1INT           0x00000140  // CAN Message 1 Interrupt Pending
+#define CAN_O_MSG2INT           0x00000144  // CAN Message 2 Interrupt Pending
+#define CAN_O_MSG1VAL           0x00000160  // CAN Message 1 Valid
+#define CAN_O_MSG2VAL           0x00000164  // CAN Message 2 Valid
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_CTL register.
+//
+//*****************************************************************************
+#define CAN_CTL_TEST            0x00000080  // Test Mode Enable
+#define CAN_CTL_CCE             0x00000040  // Configuration Change Enable
+#define CAN_CTL_DAR             0x00000020  // Disable Automatic-Retransmission
+#define CAN_CTL_EIE             0x00000008  // Error Interrupt Enable
+#define CAN_CTL_SIE             0x00000004  // Status Interrupt Enable
+#define CAN_CTL_IE              0x00000002  // CAN Interrupt Enable
+#define CAN_CTL_INIT            0x00000001  // Initialization
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_STS register.
+//
+//*****************************************************************************
+#define CAN_STS_BOFF            0x00000080  // Bus-Off Status
+#define CAN_STS_EWARN           0x00000040  // Warning Status
+#define CAN_STS_EPASS           0x00000020  // Error Passive
+#define CAN_STS_RXOK            0x00000010  // Received a Message Successfully
+#define CAN_STS_TXOK            0x00000008  // Transmitted a Message
+                                            // Successfully
+#define CAN_STS_LEC_M           0x00000007  // Last Error Code
+#define CAN_STS_LEC_NONE        0x00000000  // No Error
+#define CAN_STS_LEC_STUFF       0x00000001  // Stuff Error
+#define CAN_STS_LEC_FORM        0x00000002  // Format Error
+#define CAN_STS_LEC_ACK         0x00000003  // ACK Error
+#define CAN_STS_LEC_BIT1        0x00000004  // Bit 1 Error
+#define CAN_STS_LEC_BIT0        0x00000005  // Bit 0 Error
+#define CAN_STS_LEC_CRC         0x00000006  // CRC Error
+#define CAN_STS_LEC_NOEVENT     0x00000007  // No Event
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_ERR register.
+//
+//*****************************************************************************
+#define CAN_ERR_RP              0x00008000  // Received Error Passive
+#define CAN_ERR_REC_M           0x00007F00  // Receive Error Counter
+#define CAN_ERR_TEC_M           0x000000FF  // Transmit Error Counter
+#define CAN_ERR_REC_S           8
+#define CAN_ERR_TEC_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_BIT register.
+//
+//*****************************************************************************
+#define CAN_BIT_TSEG2_M         0x00007000  // Time Segment after Sample Point
+#define CAN_BIT_TSEG1_M         0x00000F00  // Time Segment Before Sample Point
+#define CAN_BIT_SJW_M           0x000000C0  // (Re)Synchronization Jump Width
+#define CAN_BIT_BRP_M           0x0000003F  // Baud Rate Prescaler
+#define CAN_BIT_TSEG2_S         12
+#define CAN_BIT_TSEG1_S         8
+#define CAN_BIT_SJW_S           6
+#define CAN_BIT_BRP_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_INT register.
+//
+//*****************************************************************************
+#define CAN_INT_INTID_M         0x0000FFFF  // Interrupt Identifier
+#define CAN_INT_INTID_NONE      0x00000000  // No interrupt pending
+#define CAN_INT_INTID_STATUS    0x00008000  // Status Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TST register.
+//
+//*****************************************************************************
+#define CAN_TST_RX              0x00000080  // Receive Observation
+#define CAN_TST_TX_M            0x00000060  // Transmit Control
+#define CAN_TST_TX_CANCTL       0x00000000  // CAN Module Control
+#define CAN_TST_TX_SAMPLE       0x00000020  // Sample Point
+#define CAN_TST_TX_DOMINANT     0x00000040  // Driven Low
+#define CAN_TST_TX_RECESSIVE    0x00000060  // Driven High
+#define CAN_TST_LBACK           0x00000010  // Loopback Mode
+#define CAN_TST_SILENT          0x00000008  // Silent Mode
+#define CAN_TST_BASIC           0x00000004  // Basic Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_BRPE register.
+//
+//*****************************************************************************
+#define CAN_BRPE_BRPE_M         0x0000000F  // Baud Rate Prescaler Extension
+#define CAN_BRPE_BRPE_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF1CRQ_BUSY         0x00008000  // Busy Flag
+#define CAN_IF1CRQ_MNUM_M       0x0000003F  // Message Number
+#define CAN_IF1CRQ_MNUM_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF1CMSK_WRNRD       0x00000080  // Write, Not Read
+#define CAN_IF1CMSK_MASK        0x00000040  // Access Mask Bits
+#define CAN_IF1CMSK_ARB         0x00000020  // Access Arbitration Bits
+#define CAN_IF1CMSK_CONTROL     0x00000010  // Access Control Bits
+#define CAN_IF1CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit
+#define CAN_IF1CMSK_NEWDAT      0x00000004  // Access New Data
+#define CAN_IF1CMSK_TXRQST      0x00000004  // Access Transmission Request
+#define CAN_IF1CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3
+#define CAN_IF1CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask
+#define CAN_IF1MSK1_IDMSK_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK2_MXTD        0x00008000  // Mask Extended Identifier
+#define CAN_IF1MSK2_MDIR        0x00004000  // Mask Message Direction
+#define CAN_IF1MSK2_IDMSK_M     0x00001FFF  // Identifier Mask
+#define CAN_IF1MSK2_IDMSK_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB1_ID_M        0x0000FFFF  // Message Identifier
+#define CAN_IF1ARB1_ID_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB2_MSGVAL      0x00008000  // Message Valid
+#define CAN_IF1ARB2_XTD         0x00004000  // Extended Identifier
+#define CAN_IF1ARB2_DIR         0x00002000  // Message Direction
+#define CAN_IF1ARB2_ID_M        0x00001FFF  // Message Identifier
+#define CAN_IF1ARB2_ID_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF1MCTL_NEWDAT      0x00008000  // New Data
+#define CAN_IF1MCTL_MSGLST      0x00004000  // Message Lost
+#define CAN_IF1MCTL_INTPND      0x00002000  // Interrupt Pending
+#define CAN_IF1MCTL_UMASK       0x00001000  // Use Acceptance Mask
+#define CAN_IF1MCTL_TXIE        0x00000800  // Transmit Interrupt Enable
+#define CAN_IF1MCTL_RXIE        0x00000400  // Receive Interrupt Enable
+#define CAN_IF1MCTL_RMTEN       0x00000200  // Remote Enable
+#define CAN_IF1MCTL_TXRQST      0x00000100  // Transmit Request
+#define CAN_IF1MCTL_EOB         0x00000080  // End of Buffer
+#define CAN_IF1MCTL_DLC_M       0x0000000F  // Data Length Code
+#define CAN_IF1MCTL_DLC_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA1_DATA_M       0x0000FFFF  // Data
+#define CAN_IF1DA1_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA2_DATA_M       0x0000FFFF  // Data
+#define CAN_IF1DA2_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB1_DATA_M       0x0000FFFF  // Data
+#define CAN_IF1DB1_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB2_DATA_M       0x0000FFFF  // Data
+#define CAN_IF1DB2_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF2CRQ_BUSY         0x00008000  // Busy Flag
+#define CAN_IF2CRQ_MNUM_M       0x0000003F  // Message Number
+#define CAN_IF2CRQ_MNUM_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF2CMSK_WRNRD       0x00000080  // Write, Not Read
+#define CAN_IF2CMSK_MASK        0x00000040  // Access Mask Bits
+#define CAN_IF2CMSK_ARB         0x00000020  // Access Arbitration Bits
+#define CAN_IF2CMSK_CONTROL     0x00000010  // Access Control Bits
+#define CAN_IF2CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit
+#define CAN_IF2CMSK_NEWDAT      0x00000004  // Access New Data
+#define CAN_IF2CMSK_TXRQST      0x00000004  // Access Transmission Request
+#define CAN_IF2CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3
+#define CAN_IF2CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask
+#define CAN_IF2MSK1_IDMSK_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK2_MXTD        0x00008000  // Mask Extended Identifier
+#define CAN_IF2MSK2_MDIR        0x00004000  // Mask Message Direction
+#define CAN_IF2MSK2_IDMSK_M     0x00001FFF  // Identifier Mask
+#define CAN_IF2MSK2_IDMSK_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB1_ID_M        0x0000FFFF  // Message Identifier
+#define CAN_IF2ARB1_ID_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB2_MSGVAL      0x00008000  // Message Valid
+#define CAN_IF2ARB2_XTD         0x00004000  // Extended Identifier
+#define CAN_IF2ARB2_DIR         0x00002000  // Message Direction
+#define CAN_IF2ARB2_ID_M        0x00001FFF  // Message Identifier
+#define CAN_IF2ARB2_ID_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF2MCTL_NEWDAT      0x00008000  // New Data
+#define CAN_IF2MCTL_MSGLST      0x00004000  // Message Lost
+#define CAN_IF2MCTL_INTPND      0x00002000  // Interrupt Pending
+#define CAN_IF2MCTL_UMASK       0x00001000  // Use Acceptance Mask
+#define CAN_IF2MCTL_TXIE        0x00000800  // Transmit Interrupt Enable
+#define CAN_IF2MCTL_RXIE        0x00000400  // Receive Interrupt Enable
+#define CAN_IF2MCTL_RMTEN       0x00000200  // Remote Enable
+#define CAN_IF2MCTL_TXRQST      0x00000100  // Transmit Request
+#define CAN_IF2MCTL_EOB         0x00000080  // End of Buffer
+#define CAN_IF2MCTL_DLC_M       0x0000000F  // Data Length Code
+#define CAN_IF2MCTL_DLC_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA1_DATA_M       0x0000FFFF  // Data
+#define CAN_IF2DA1_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA2_DATA_M       0x0000FFFF  // Data
+#define CAN_IF2DA2_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB1_DATA_M       0x0000FFFF  // Data
+#define CAN_IF2DB1_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB2_DATA_M       0x0000FFFF  // Data
+#define CAN_IF2DB2_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ1 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ1_TXRQST_M      0x0000FFFF  // Transmission Request Bits
+#define CAN_TXRQ1_TXRQST_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ2 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ2_TXRQST_M      0x0000FFFF  // Transmission Request Bits
+#define CAN_TXRQ2_TXRQST_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA1 register.
+//
+//*****************************************************************************
+#define CAN_NWDA1_NEWDAT_M      0x0000FFFF  // New Data Bits
+#define CAN_NWDA1_NEWDAT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA2 register.
+//
+//*****************************************************************************
+#define CAN_NWDA2_NEWDAT_M      0x0000FFFF  // New Data Bits
+#define CAN_NWDA2_NEWDAT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1INT register.
+//
+//*****************************************************************************
+#define CAN_MSG1INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits
+#define CAN_MSG1INT_INTPND_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2INT register.
+//
+//*****************************************************************************
+#define CAN_MSG2INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits
+#define CAN_MSG2INT_INTPND_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG1VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits
+#define CAN_MSG1VAL_MSGVAL_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG2VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits
+#define CAN_MSG2VAL_MSGVAL_S    0
+
+#endif // __HW_CAN_H__
diff --git a/os/common/ext/TivaWare/inc/hw_ccm.h b/os/common/ext/TivaWare/inc/hw_ccm.h
new file mode 100644
index 0000000..19041b6
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_ccm.h
@@ -0,0 +1,115 @@
+//*****************************************************************************
+//
+// hw_ccm.h - Macros used when accessing the CCM hardware.
+//
+// Copyright (c) 2012-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_CCM_H__
+#define __HW_CCM_H__
+
+//*****************************************************************************
+//
+// The following are defines for the EC register offsets.
+//
+//*****************************************************************************
+#define CCM_O_CRCCTRL           0x00000400  // CRC Control
+#define CCM_O_CRCSEED           0x00000410  // CRC SEED/Context
+#define CCM_O_CRCDIN            0x00000414  // CRC Data Input
+#define CCM_O_CRCRSLTPP         0x00000418  // CRC Post Processing Result
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CCM_O_CRCCTRL register.
+//
+//*****************************************************************************
+#define CCM_CRCCTRL_INIT_M      0x00006000  // CRC Initialization
+#define CCM_CRCCTRL_INIT_SEED   0x00000000  // Use the CRCSEED register context
+                                            // as the starting value
+#define CCM_CRCCTRL_INIT_0      0x00004000  // Initialize to all '0s'
+#define CCM_CRCCTRL_INIT_1      0x00006000  // Initialize to all '1s'
+#define CCM_CRCCTRL_SIZE        0x00001000  // Input Data Size
+#define CCM_CRCCTRL_RESINV      0x00000200  // Result Inverse Enable
+#define CCM_CRCCTRL_OBR         0x00000100  // Output Reverse Enable
+#define CCM_CRCCTRL_BR          0x00000080  // Bit reverse enable
+#define CCM_CRCCTRL_ENDIAN_M    0x00000030  // Endian Control
+#define CCM_CRCCTRL_ENDIAN_SBHW 0x00000000  // Configuration unchanged. (B3,
+                                            // B2, B1, B0)
+#define CCM_CRCCTRL_ENDIAN_SHW  0x00000010  // Bytes are swapped in half-words
+                                            // but half-words are not swapped
+                                            // (B2, B3, B0, B1)
+#define CCM_CRCCTRL_ENDIAN_SHWNB                                              \
+                                0x00000020  // Half-words are swapped but bytes
+                                            // are not swapped in half-word.
+                                            // (B1, B0, B3, B2)
+#define CCM_CRCCTRL_ENDIAN_SBSW 0x00000030  // Bytes are swapped in half-words
+                                            // and half-words are swapped. (B0,
+                                            // B1, B2, B3)
+#define CCM_CRCCTRL_TYPE_M      0x0000000F  // Operation Type
+#define CCM_CRCCTRL_TYPE_P8055  0x00000000  // Polynomial 0x8005
+#define CCM_CRCCTRL_TYPE_P1021  0x00000001  // Polynomial 0x1021
+#define CCM_CRCCTRL_TYPE_P4C11DB7                                             \
+                                0x00000002  // Polynomial 0x4C11DB7
+#define CCM_CRCCTRL_TYPE_P1EDC6F41                                            \
+                                0x00000003  // Polynomial 0x1EDC6F41
+#define CCM_CRCCTRL_TYPE_TCPCHKSUM                                            \
+                                0x00000008  // TCP checksum
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CCM_O_CRCSEED register.
+//
+//*****************************************************************************
+#define CCM_CRCSEED_SEED_M      0xFFFFFFFF  // SEED/Context Value
+#define CCM_CRCSEED_SEED_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CCM_O_CRCDIN register.
+//
+//*****************************************************************************
+#define CCM_CRCDIN_DATAIN_M     0xFFFFFFFF  // Data Input
+#define CCM_CRCDIN_DATAIN_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CCM_O_CRCRSLTPP
+// register.
+//
+//*****************************************************************************
+#define CCM_CRCRSLTPP_RSLTPP_M  0xFFFFFFFF  // Post Processing Result
+#define CCM_CRCRSLTPP_RSLTPP_S  0
+
+#endif // __HW_CCM_H__
diff --git a/os/common/ext/TivaWare/inc/hw_comp.h b/os/common/ext/TivaWare/inc/hw_comp.h
new file mode 100644
index 0000000..aea2f84
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_comp.h
@@ -0,0 +1,211 @@
+//*****************************************************************************
+//
+// hw_comp.h - Macros used when accessing the comparator hardware.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_COMP_H__
+#define __HW_COMP_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Comparator register offsets.
+//
+//*****************************************************************************
+#define COMP_O_ACMIS            0x00000000  // Analog Comparator Masked
+                                            // Interrupt Status
+#define COMP_O_ACRIS            0x00000004  // Analog Comparator Raw Interrupt
+                                            // Status
+#define COMP_O_ACINTEN          0x00000008  // Analog Comparator Interrupt
+                                            // Enable
+#define COMP_O_ACREFCTL         0x00000010  // Analog Comparator Reference
+                                            // Voltage Control
+#define COMP_O_ACSTAT0          0x00000020  // Analog Comparator Status 0
+#define COMP_O_ACCTL0           0x00000024  // Analog Comparator Control 0
+#define COMP_O_ACSTAT1          0x00000040  // Analog Comparator Status 1
+#define COMP_O_ACCTL1           0x00000044  // Analog Comparator Control 1
+#define COMP_O_ACSTAT2          0x00000060  // Analog Comparator Status 2
+#define COMP_O_ACCTL2           0x00000064  // Analog Comparator Control 2
+#define COMP_O_PP               0x00000FC0  // Analog Comparator Peripheral
+                                            // Properties
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACMIS register.
+//
+//*****************************************************************************
+#define COMP_ACMIS_IN2          0x00000004  // Comparator 2 Masked Interrupt
+                                            // Status
+#define COMP_ACMIS_IN1          0x00000002  // Comparator 1 Masked Interrupt
+                                            // Status
+#define COMP_ACMIS_IN0          0x00000001  // Comparator 0 Masked Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACRIS register.
+//
+//*****************************************************************************
+#define COMP_ACRIS_IN2          0x00000004  // Comparator 2 Interrupt Status
+#define COMP_ACRIS_IN1          0x00000002  // Comparator 1 Interrupt Status
+#define COMP_ACRIS_IN0          0x00000001  // Comparator 0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACINTEN register.
+//
+//*****************************************************************************
+#define COMP_ACINTEN_IN2        0x00000004  // Comparator 2 Interrupt Enable
+#define COMP_ACINTEN_IN1        0x00000002  // Comparator 1 Interrupt Enable
+#define COMP_ACINTEN_IN0        0x00000001  // Comparator 0 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACREFCTL
+// register.
+//
+//*****************************************************************************
+#define COMP_ACREFCTL_EN        0x00000200  // Resistor Ladder Enable
+#define COMP_ACREFCTL_RNG       0x00000100  // Resistor Ladder Range
+#define COMP_ACREFCTL_VREF_M    0x0000000F  // Resistor Ladder Voltage Ref
+#define COMP_ACREFCTL_VREF_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT0_OVAL       0x00000002  // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL0 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL0_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL0_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL0_ASRCP_PIN   0x00000000  // Pin value of Cn+
+#define COMP_ACCTL0_ASRCP_PIN0  0x00000200  // Pin value of C0+
+#define COMP_ACCTL0_ASRCP_REF   0x00000400  // Internal voltage reference
+#define COMP_ACCTL0_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL0_TSEN_M      0x00000060  // Trigger Sense
+#define COMP_ACCTL0_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
+#define COMP_ACCTL0_TSEN_FALL   0x00000020  // Falling edge
+#define COMP_ACCTL0_TSEN_RISE   0x00000040  // Rising edge
+#define COMP_ACCTL0_TSEN_BOTH   0x00000060  // Either edge
+#define COMP_ACCTL0_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL0_ISEN_M      0x0000000C  // Interrupt Sense
+#define COMP_ACCTL0_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
+#define COMP_ACCTL0_ISEN_FALL   0x00000004  // Falling edge
+#define COMP_ACCTL0_ISEN_RISE   0x00000008  // Rising edge
+#define COMP_ACCTL0_ISEN_BOTH   0x0000000C  // Either edge
+#define COMP_ACCTL0_CINV        0x00000002  // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT1_OVAL       0x00000002  // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL1 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL1_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL1_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL1_ASRCP_PIN   0x00000000  // Pin value of Cn+
+#define COMP_ACCTL1_ASRCP_PIN0  0x00000200  // Pin value of C0+
+#define COMP_ACCTL1_ASRCP_REF   0x00000400  // Internal voltage reference
+#define COMP_ACCTL1_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL1_TSEN_M      0x00000060  // Trigger Sense
+#define COMP_ACCTL1_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
+#define COMP_ACCTL1_TSEN_FALL   0x00000020  // Falling edge
+#define COMP_ACCTL1_TSEN_RISE   0x00000040  // Rising edge
+#define COMP_ACCTL1_TSEN_BOTH   0x00000060  // Either edge
+#define COMP_ACCTL1_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL1_ISEN_M      0x0000000C  // Interrupt Sense
+#define COMP_ACCTL1_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
+#define COMP_ACCTL1_ISEN_FALL   0x00000004  // Falling edge
+#define COMP_ACCTL1_ISEN_RISE   0x00000008  // Rising edge
+#define COMP_ACCTL1_ISEN_BOTH   0x0000000C  // Either edge
+#define COMP_ACCTL1_CINV        0x00000002  // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT2 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT2_OVAL       0x00000002  // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL2 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL2_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL2_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL2_ASRCP_PIN   0x00000000  // Pin value of Cn+
+#define COMP_ACCTL2_ASRCP_PIN0  0x00000200  // Pin value of C0+
+#define COMP_ACCTL2_ASRCP_REF   0x00000400  // Internal voltage reference
+#define COMP_ACCTL2_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL2_TSEN_M      0x00000060  // Trigger Sense
+#define COMP_ACCTL2_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
+#define COMP_ACCTL2_TSEN_FALL   0x00000020  // Falling edge
+#define COMP_ACCTL2_TSEN_RISE   0x00000040  // Rising edge
+#define COMP_ACCTL2_TSEN_BOTH   0x00000060  // Either edge
+#define COMP_ACCTL2_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL2_ISEN_M      0x0000000C  // Interrupt Sense
+#define COMP_ACCTL2_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
+#define COMP_ACCTL2_ISEN_FALL   0x00000004  // Falling edge
+#define COMP_ACCTL2_ISEN_RISE   0x00000008  // Rising edge
+#define COMP_ACCTL2_ISEN_BOTH   0x0000000C  // Either edge
+#define COMP_ACCTL2_CINV        0x00000002  // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_PP register.
+//
+//*****************************************************************************
+#define COMP_PP_C2O             0x00040000  // Comparator Output 2 Present
+#define COMP_PP_C1O             0x00020000  // Comparator Output 1 Present
+#define COMP_PP_C0O             0x00010000  // Comparator Output 0 Present
+#define COMP_PP_CMP2            0x00000004  // Comparator 2 Present
+#define COMP_PP_CMP1            0x00000002  // Comparator 1 Present
+#define COMP_PP_CMP0            0x00000001  // Comparator 0 Present
+
+#endif // __HW_COMP_H__
diff --git a/os/common/ext/TivaWare/inc/hw_des.h b/os/common/ext/TivaWare/inc/hw_des.h
new file mode 100644
index 0000000..da46c52
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_des.h
@@ -0,0 +1,310 @@
+//*****************************************************************************
+//
+// hw_des.h - Macros used when accessing the DES hardware.
+//
+// Copyright (c) 2012-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_DES_H__
+#define __HW_DES_H__
+
+//*****************************************************************************
+//
+// The following are defines for the DES register offsets.
+//
+//*****************************************************************************
+#define DES_O_KEY3_L            0x00000000  // DES Key 3 LSW for 192-Bit Key
+#define DES_O_KEY3_H            0x00000004  // DES Key 3 MSW for 192-Bit Key
+#define DES_O_KEY2_L            0x00000008  // DES Key 2 LSW for 128-Bit Key
+#define DES_O_KEY2_H            0x0000000C  // DES Key 2 MSW for 128-Bit Key
+#define DES_O_KEY1_L            0x00000010  // DES Key 1 LSW for 64-Bit Key
+#define DES_O_KEY1_H            0x00000014  // DES Key 1 MSW for 64-Bit Key
+#define DES_O_IV_L              0x00000018  // DES Initialization Vector
+#define DES_O_IV_H              0x0000001C  // DES Initialization Vector
+#define DES_O_CTRL              0x00000020  // DES Control
+#define DES_O_LENGTH            0x00000024  // DES Cryptographic Data Length
+#define DES_O_DATA_L            0x00000028  // DES LSW Data RW
+#define DES_O_DATA_H            0x0000002C  // DES MSW Data RW
+#define DES_O_REVISION          0x00000030  // DES Revision Number
+#define DES_O_SYSCONFIG         0x00000034  // DES System Configuration
+#define DES_O_SYSSTATUS         0x00000038  // DES System Status
+#define DES_O_IRQSTATUS         0x0000003C  // DES Interrupt Status
+#define DES_O_IRQENABLE         0x00000040  // DES Interrupt Enable
+#define DES_O_DIRTYBITS         0x00000044  // DES Dirty Bits
+#define DES_O_DMAIM             0xFFFF8030  // DES DMA Interrupt Mask
+#define DES_O_DMARIS            0xFFFF8034  // DES DMA Raw Interrupt Status
+#define DES_O_DMAMIS            0xFFFF8038  // DES DMA Masked Interrupt Status
+#define DES_O_DMAIC             0xFFFF803C  // DES DMA Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY3_L register.
+//
+//*****************************************************************************
+#define DES_KEY3_L_KEY_M        0xFFFFFFFF  // Key Data
+#define DES_KEY3_L_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY3_H register.
+//
+//*****************************************************************************
+#define DES_KEY3_H_KEY_M        0xFFFFFFFF  // Key Data
+#define DES_KEY3_H_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY2_L register.
+//
+//*****************************************************************************
+#define DES_KEY2_L_KEY_M        0xFFFFFFFF  // Key Data
+#define DES_KEY2_L_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY2_H register.
+//
+//*****************************************************************************
+#define DES_KEY2_H_KEY_M        0xFFFFFFFF  // Key Data
+#define DES_KEY2_H_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY1_L register.
+//
+//*****************************************************************************
+#define DES_KEY1_L_KEY_M        0xFFFFFFFF  // Key Data
+#define DES_KEY1_L_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY1_H register.
+//
+//*****************************************************************************
+#define DES_KEY1_H_KEY_M        0xFFFFFFFF  // Key Data
+#define DES_KEY1_H_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_IV_L register.
+//
+//*****************************************************************************
+#define DES_IV_L_M              0xFFFFFFFF  // Initialization vector for CBC,
+                                            // CFB modes (LSW)
+#define DES_IV_L_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_IV_H register.
+//
+//*****************************************************************************
+#define DES_IV_H_M              0xFFFFFFFF  // Initialization vector for CBC,
+                                            // CFB modes (MSW)
+#define DES_IV_H_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_CTRL register.
+//
+//*****************************************************************************
+#define DES_CTRL_CONTEXT        0x80000000  // If 1, this read-only status bit
+                                            // indicates that the context data
+                                            // registers can be overwritten and
+                                            // the host is permitted to write
+                                            // the next context
+#define DES_CTRL_MODE_M         0x00000030  // Select CBC, ECB or CFB mode0x0:
+                                            // ECB mode0x1: CBC mode0x2: CFB
+                                            // mode0x3: reserved
+#define DES_CTRL_TDES           0x00000008  // Select DES or triple DES
+                                            // encryption/decryption
+#define DES_CTRL_DIRECTION      0x00000004  // Select encryption/decryption
+                                            // 0x0: decryption is selected0x1:
+                                            // Encryption is selected
+#define DES_CTRL_INPUT_READY    0x00000002  // When 1, ready to encrypt/decrypt
+                                            // data
+#define DES_CTRL_OUTPUT_READY   0x00000001  // When 1, Data decrypted/encrypted
+                                            // ready
+#define DES_CTRL_MODE_S         4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_LENGTH register.
+//
+//*****************************************************************************
+#define DES_LENGTH_M            0xFFFFFFFF  // Cryptographic data length in
+                                            // bytes for all modes
+#define DES_LENGTH_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DATA_L register.
+//
+//*****************************************************************************
+#define DES_DATA_L_M            0xFFFFFFFF  // Data for encryption/decryption,
+                                            // LSW
+#define DES_DATA_L_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DATA_H register.
+//
+//*****************************************************************************
+#define DES_DATA_H_M            0xFFFFFFFF  // Data for encryption/decryption,
+                                            // MSW
+#define DES_DATA_H_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_REVISION register.
+//
+//*****************************************************************************
+#define DES_REVISION_M          0xFFFFFFFF  // Revision number
+#define DES_REVISION_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_SYSCONFIG
+// register.
+//
+//*****************************************************************************
+#define DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN                                   \
+                                0x00000080  // DMA Request Context In Enable
+#define DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN                                     \
+                                0x00000040  // DMA Request Data Out Enable
+#define DES_SYSCONFIG_DMA_REQ_DATA_IN_EN                                      \
+                                0x00000020  // DMA Request Data In Enable
+#define DES_SYSCONFIG_SIDLE_M   0x0000000C  // Sidle mode
+#define DES_SYSCONFIG_SIDLE_FORCE                                             \
+                                0x00000000  // Force-idle mode
+#define DES_SYSCONFIG_SOFTRESET 0x00000002  // Soft reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_SYSSTATUS
+// register.
+//
+//*****************************************************************************
+#define DES_SYSSTATUS_RESETDONE 0x00000001  // Reset Done
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_IRQSTATUS
+// register.
+//
+//*****************************************************************************
+#define DES_IRQSTATUS_DATA_OUT  0x00000004  // This bit indicates data output
+                                            // interrupt is active and triggers
+                                            // the interrupt output
+#define DES_IRQSTATUS_DATA_IN   0x00000002  // This bit indicates data input
+                                            // interrupt is active and triggers
+                                            // the interrupt output
+#define DES_IRQSTATUS_CONTEX_IN 0x00000001  // This bit indicates context
+                                            // interrupt is active and triggers
+                                            // the interrupt output
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_IRQENABLE
+// register.
+//
+//*****************************************************************************
+#define DES_IRQENABLE_M_DATA_OUT                                              \
+                                0x00000004  // If this bit is set to 1 the data
+                                            // output interrupt is enabled
+#define DES_IRQENABLE_M_DATA_IN 0x00000002  // If this bit is set to 1 the data
+                                            // input interrupt is enabled
+#define DES_IRQENABLE_M_CONTEX_IN                                             \
+                                0x00000001  // If this bit is set to 1 the
+                                            // context interrupt is enabled
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DIRTYBITS
+// register.
+//
+//*****************************************************************************
+#define DES_DIRTYBITS_S_DIRTY   0x00000002  // This bit is set to 1 by the
+                                            // module if any of the DES_*
+                                            // registers is written
+#define DES_DIRTYBITS_S_ACCESS  0x00000001  // This bit is set to 1 by the
+                                            // module if any of the DES_*
+                                            // registers is read
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DMAIM register.
+//
+//*****************************************************************************
+#define DES_DMAIM_DOUT          0x00000004  // Data Out DMA Done Interrupt Mask
+#define DES_DMAIM_DIN           0x00000002  // Data In DMA Done Interrupt Mask
+#define DES_DMAIM_CIN           0x00000001  // Context In DMA Done Interrupt
+                                            // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DMARIS register.
+//
+//*****************************************************************************
+#define DES_DMARIS_DOUT         0x00000004  // Data Out DMA Done Raw Interrupt
+                                            // Status
+#define DES_DMARIS_DIN          0x00000002  // Data In DMA Done Raw Interrupt
+                                            // Status
+#define DES_DMARIS_CIN          0x00000001  // Context In DMA Done Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DMAMIS register.
+//
+//*****************************************************************************
+#define DES_DMAMIS_DOUT         0x00000004  // Data Out DMA Done Masked
+                                            // Interrupt Status
+#define DES_DMAMIS_DIN          0x00000002  // Data In DMA Done Masked
+                                            // Interrupt Status
+#define DES_DMAMIS_CIN          0x00000001  // Context In DMA Done Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DMAIC register.
+//
+//*****************************************************************************
+#define DES_DMAIC_DOUT          0x00000004  // Data Out DMA Done Interrupt
+                                            // Clear
+#define DES_DMAIC_DIN           0x00000002  // Data In DMA Done Interrupt Clear
+#define DES_DMAIC_CIN           0x00000001  // Context In DMA Done Raw
+                                            // Interrupt Status
+
+#endif // __HW_DES_H__
diff --git a/os/common/ext/TivaWare/inc/hw_eeprom.h b/os/common/ext/TivaWare/inc/hw_eeprom.h
new file mode 100644
index 0000000..7ba282d
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_eeprom.h
@@ -0,0 +1,251 @@
+//*****************************************************************************
+//
+// hw_eeprom.h - Macros used when accessing the EEPROM controller.
+//
+// Copyright (c) 2011-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_EEPROM_H__
+#define __HW_EEPROM_H__
+
+//*****************************************************************************
+//
+// The following are defines for the EEPROM register offsets.
+//
+//*****************************************************************************
+#define EEPROM_EESIZE           0x400AF000  // EEPROM Size Information
+#define EEPROM_EEBLOCK          0x400AF004  // EEPROM Current Block
+#define EEPROM_EEOFFSET         0x400AF008  // EEPROM Current Offset
+#define EEPROM_EERDWR           0x400AF010  // EEPROM Read-Write
+#define EEPROM_EERDWRINC        0x400AF014  // EEPROM Read-Write with Increment
+#define EEPROM_EEDONE           0x400AF018  // EEPROM Done Status
+#define EEPROM_EESUPP           0x400AF01C  // EEPROM Support Control and
+                                            // Status
+#define EEPROM_EEUNLOCK         0x400AF020  // EEPROM Unlock
+#define EEPROM_EEPROT           0x400AF030  // EEPROM Protection
+#define EEPROM_EEPASS0          0x400AF034  // EEPROM Password
+#define EEPROM_EEPASS1          0x400AF038  // EEPROM Password
+#define EEPROM_EEPASS2          0x400AF03C  // EEPROM Password
+#define EEPROM_EEINT            0x400AF040  // EEPROM Interrupt
+#define EEPROM_EEHIDE0          0x400AF050  // EEPROM Block Hide 0
+#define EEPROM_EEHIDE           0x400AF050  // EEPROM Block Hide
+#define EEPROM_EEHIDE1          0x400AF054  // EEPROM Block Hide 1
+#define EEPROM_EEHIDE2          0x400AF058  // EEPROM Block Hide 2
+#define EEPROM_EEDBGME          0x400AF080  // EEPROM Debug Mass Erase
+#define EEPROM_PP               0x400AFFC0  // EEPROM Peripheral Properties
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EESIZE register.
+//
+//*****************************************************************************
+#define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF  // Number of 32-Bit Words
+#define EEPROM_EESIZE_BLKCNT_M  0x07FF0000  // Number of 16-Word Blocks
+#define EEPROM_EESIZE_WORDCNT_S 0
+#define EEPROM_EESIZE_BLKCNT_S  16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEBLOCK register.
+//
+//*****************************************************************************
+#define EEPROM_EEBLOCK_BLOCK_M  0x0000FFFF  // Current Block
+#define EEPROM_EEBLOCK_BLOCK_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEOFFSET
+// register.
+//
+//*****************************************************************************
+#define EEPROM_EEOFFSET_OFFSET_M                                              \
+                                0x0000000F  // Current Address Offset
+#define EEPROM_EEOFFSET_OFFSET_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EERDWR register.
+//
+//*****************************************************************************
+#define EEPROM_EERDWR_VALUE_M   0xFFFFFFFF  // EEPROM Read or Write Data
+#define EEPROM_EERDWR_VALUE_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EERDWRINC
+// register.
+//
+//*****************************************************************************
+#define EEPROM_EERDWRINC_VALUE_M                                              \
+                                0xFFFFFFFF  // EEPROM Read or Write Data with
+                                            // Increment
+#define EEPROM_EERDWRINC_VALUE_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEDONE register.
+//
+//*****************************************************************************
+#define EEPROM_EEDONE_WORKING   0x00000001  // EEPROM Working
+#define EEPROM_EEDONE_WKERASE   0x00000004  // Working on an Erase
+#define EEPROM_EEDONE_WKCOPY    0x00000008  // Working on a Copy
+#define EEPROM_EEDONE_NOPERM    0x00000010  // Write Without Permission
+#define EEPROM_EEDONE_WRBUSY    0x00000020  // Write Busy
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EESUPP register.
+//
+//*****************************************************************************
+#define EEPROM_EESUPP_ERETRY    0x00000004  // Erase Must Be Retried
+#define EEPROM_EESUPP_PRETRY    0x00000008  // Programming Must Be Retried
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEUNLOCK
+// register.
+//
+//*****************************************************************************
+#define EEPROM_EEUNLOCK_UNLOCK_M                                              \
+                                0xFFFFFFFF  // EEPROM Unlock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPROT register.
+//
+//*****************************************************************************
+#define EEPROM_EEPROT_PROT_M    0x00000007  // Protection Control
+#define EEPROM_EEPROT_PROT_RWNPW                                              \
+                                0x00000000  // This setting is the default. If
+                                            // there is no password, the block
+                                            // is not protected and is readable
+                                            // and writable
+#define EEPROM_EEPROT_PROT_RWPW 0x00000001  // If there is a password, the
+                                            // block is readable or writable
+                                            // only when unlocked
+#define EEPROM_EEPROT_PROT_RONPW                                              \
+                                0x00000002  // If there is no password, the
+                                            // block is readable, not writable
+#define EEPROM_EEPROT_ACC       0x00000008  // Access Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPASS0 register.
+//
+//*****************************************************************************
+#define EEPROM_EEPASS0_PASS_M   0xFFFFFFFF  // Password
+#define EEPROM_EEPASS0_PASS_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPASS1 register.
+//
+//*****************************************************************************
+#define EEPROM_EEPASS1_PASS_M   0xFFFFFFFF  // Password
+#define EEPROM_EEPASS1_PASS_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPASS2 register.
+//
+//*****************************************************************************
+#define EEPROM_EEPASS2_PASS_M   0xFFFFFFFF  // Password
+#define EEPROM_EEPASS2_PASS_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEINT register.
+//
+//*****************************************************************************
+#define EEPROM_EEINT_INT        0x00000001  // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEHIDE0 register.
+//
+//*****************************************************************************
+#define EEPROM_EEHIDE0_HN_M     0xFFFFFFFE  // Hide Block
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEHIDE register.
+//
+//*****************************************************************************
+#define EEPROM_EEHIDE_HN_M      0xFFFFFFFE  // Hide Block
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEHIDE1 register.
+//
+//*****************************************************************************
+#define EEPROM_EEHIDE1_HN_M     0xFFFFFFFF  // Hide Block
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEHIDE2 register.
+//
+//*****************************************************************************
+#define EEPROM_EEHIDE2_HN_M     0xFFFFFFFF  // Hide Block
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEDBGME register.
+//
+//*****************************************************************************
+#define EEPROM_EEDBGME_ME       0x00000001  // Mass Erase
+#define EEPROM_EEDBGME_KEY_M    0xFFFF0000  // Erase Key
+#define EEPROM_EEDBGME_KEY_S    16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_PP register.
+//
+//*****************************************************************************
+#define EEPROM_PP_SIZE_M        0x0000FFFF  // EEPROM Size
+#define EEPROM_PP_SIZE_64       0x00000000  // 64 bytes of EEPROM
+#define EEPROM_PP_SIZE_128      0x00000001  // 128 bytes of EEPROM
+#define EEPROM_PP_SIZE_256      0x00000003  // 256 bytes of EEPROM
+#define EEPROM_PP_SIZE_512      0x00000007  // 512 bytes of EEPROM
+#define EEPROM_PP_SIZE_1K       0x0000000F  // 1 KB of EEPROM
+#define EEPROM_PP_SIZE_2K       0x0000001F  // 2 KB of EEPROM
+#define EEPROM_PP_SIZE_3K       0x0000003F  // 3 KB of EEPROM
+#define EEPROM_PP_SIZE_4K       0x0000007F  // 4 KB of EEPROM
+#define EEPROM_PP_SIZE_5K       0x000000FF  // 5 KB of EEPROM
+#define EEPROM_PP_SIZE_6K       0x000001FF  // 6 KB of EEPROM
+#define EEPROM_PP_SIZE_S        0
+
+#endif // __HW_EEPROM_H__
diff --git a/os/common/ext/TivaWare/inc/hw_emac.h b/os/common/ext/TivaWare/inc/hw_emac.h
new file mode 100644
index 0000000..67cb03e
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_emac.h
@@ -0,0 +1,1839 @@
+//*****************************************************************************
+//
+// hw_emac.h - Macros used when accessing the EMAC hardware.
+//
+// Copyright (c) 2012-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_EMAC_H__
+#define __HW_EMAC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the EMAC register offsets.
+//
+//*****************************************************************************
+#define EMAC_O_CFG              0x00000000  // Ethernet MAC Configuration
+#define EMAC_O_FRAMEFLTR        0x00000004  // Ethernet MAC Frame Filter
+#define EMAC_O_HASHTBLH         0x00000008  // Ethernet MAC Hash Table High
+#define EMAC_O_HASHTBLL         0x0000000C  // Ethernet MAC Hash Table Low
+#define EMAC_O_MIIADDR          0x00000010  // Ethernet MAC MII Address
+#define EMAC_O_MIIDATA          0x00000014  // Ethernet MAC MII Data Register
+#define EMAC_O_FLOWCTL          0x00000018  // Ethernet MAC Flow Control
+#define EMAC_O_VLANTG           0x0000001C  // Ethernet MAC VLAN Tag
+#define EMAC_O_STATUS           0x00000024  // Ethernet MAC Status
+#define EMAC_O_RWUFF            0x00000028  // Ethernet MAC Remote Wake-Up
+                                            // Frame Filter
+#define EMAC_O_PMTCTLSTAT       0x0000002C  // Ethernet MAC PMT Control and
+                                            // Status Register
+#define EMAC_O_RIS              0x00000038  // Ethernet MAC Raw Interrupt
+                                            // Status
+#define EMAC_O_IM               0x0000003C  // Ethernet MAC Interrupt Mask
+#define EMAC_O_ADDR0H           0x00000040  // Ethernet MAC Address 0 High
+#define EMAC_O_ADDR0L           0x00000044  // Ethernet MAC Address 0 Low
+                                            // Register
+#define EMAC_O_ADDR1H           0x00000048  // Ethernet MAC Address 1 High
+#define EMAC_O_ADDR1L           0x0000004C  // Ethernet MAC Address 1 Low
+#define EMAC_O_ADDR2H           0x00000050  // Ethernet MAC Address 2 High
+#define EMAC_O_ADDR2L           0x00000054  // Ethernet MAC Address 2 Low
+#define EMAC_O_ADDR3H           0x00000058  // Ethernet MAC Address 3 High
+#define EMAC_O_ADDR3L           0x0000005C  // Ethernet MAC Address 3 Low
+#define EMAC_O_WDOGTO           0x000000DC  // Ethernet MAC Watchdog Timeout
+#define EMAC_O_MMCCTRL          0x00000100  // Ethernet MAC MMC Control
+#define EMAC_O_MMCRXRIS         0x00000104  // Ethernet MAC MMC Receive Raw
+                                            // Interrupt Status
+#define EMAC_O_MMCTXRIS         0x00000108  // Ethernet MAC MMC Transmit Raw
+                                            // Interrupt Status
+#define EMAC_O_MMCRXIM          0x0000010C  // Ethernet MAC MMC Receive
+                                            // Interrupt Mask
+#define EMAC_O_MMCTXIM          0x00000110  // Ethernet MAC MMC Transmit
+                                            // Interrupt Mask
+#define EMAC_O_TXCNTGB          0x00000118  // Ethernet MAC Transmit Frame
+                                            // Count for Good and Bad Frames
+#define EMAC_O_TXCNTSCOL        0x0000014C  // Ethernet MAC Transmit Frame
+                                            // Count for Frames Transmitted
+                                            // after Single Collision
+#define EMAC_O_TXCNTMCOL        0x00000150  // Ethernet MAC Transmit Frame
+                                            // Count for Frames Transmitted
+                                            // after Multiple Collisions
+#define EMAC_O_TXOCTCNTG        0x00000164  // Ethernet MAC Transmit Octet
+                                            // Count Good
+#define EMAC_O_RXCNTGB          0x00000180  // Ethernet MAC Receive Frame Count
+                                            // for Good and Bad Frames
+#define EMAC_O_RXCNTCRCERR      0x00000194  // Ethernet MAC Receive Frame Count
+                                            // for CRC Error Frames
+#define EMAC_O_RXCNTALGNERR     0x00000198  // Ethernet MAC Receive Frame Count
+                                            // for Alignment Error Frames
+#define EMAC_O_RXCNTGUNI        0x000001C4  // Ethernet MAC Receive Frame Count
+                                            // for Good Unicast Frames
+#define EMAC_O_VLNINCREP        0x00000584  // Ethernet MAC VLAN Tag Inclusion
+                                            // or Replacement
+#define EMAC_O_VLANHASH         0x00000588  // Ethernet MAC VLAN Hash Table
+#define EMAC_O_TIMSTCTRL        0x00000700  // Ethernet MAC Timestamp Control
+#define EMAC_O_SUBSECINC        0x00000704  // Ethernet MAC Sub-Second
+                                            // Increment
+#define EMAC_O_TIMSEC           0x00000708  // Ethernet MAC System Time -
+                                            // Seconds
+#define EMAC_O_TIMNANO          0x0000070C  // Ethernet MAC System Time -
+                                            // Nanoseconds
+#define EMAC_O_TIMSECU          0x00000710  // Ethernet MAC System Time -
+                                            // Seconds Update
+#define EMAC_O_TIMNANOU         0x00000714  // Ethernet MAC System Time -
+                                            // Nanoseconds Update
+#define EMAC_O_TIMADD           0x00000718  // Ethernet MAC Timestamp Addend
+#define EMAC_O_TARGSEC          0x0000071C  // Ethernet MAC Target Time Seconds
+#define EMAC_O_TARGNANO         0x00000720  // Ethernet MAC Target Time
+                                            // Nanoseconds
+#define EMAC_O_HWORDSEC         0x00000724  // Ethernet MAC System Time-Higher
+                                            // Word Seconds
+#define EMAC_O_TIMSTAT          0x00000728  // Ethernet MAC Timestamp Status
+#define EMAC_O_PPSCTRL          0x0000072C  // Ethernet MAC PPS Control
+#define EMAC_O_PPS0INTVL        0x00000760  // Ethernet MAC PPS0 Interval
+#define EMAC_O_PPS0WIDTH        0x00000764  // Ethernet MAC PPS0 Width
+#define EMAC_O_DMABUSMOD        0x00000C00  // Ethernet MAC DMA Bus Mode
+#define EMAC_O_TXPOLLD          0x00000C04  // Ethernet MAC Transmit Poll
+                                            // Demand
+#define EMAC_O_RXPOLLD          0x00000C08  // Ethernet MAC Receive Poll Demand
+#define EMAC_O_RXDLADDR         0x00000C0C  // Ethernet MAC Receive Descriptor
+                                            // List Address
+#define EMAC_O_TXDLADDR         0x00000C10  // Ethernet MAC Transmit Descriptor
+                                            // List Address
+#define EMAC_O_DMARIS           0x00000C14  // Ethernet MAC DMA Interrupt
+                                            // Status
+#define EMAC_O_DMAOPMODE        0x00000C18  // Ethernet MAC DMA Operation Mode
+#define EMAC_O_DMAIM            0x00000C1C  // Ethernet MAC DMA Interrupt Mask
+                                            // Register
+#define EMAC_O_MFBOC            0x00000C20  // Ethernet MAC Missed Frame and
+                                            // Buffer Overflow Counter
+#define EMAC_O_RXINTWDT         0x00000C24  // Ethernet MAC Receive Interrupt
+                                            // Watchdog Timer
+#define EMAC_O_HOSTXDESC        0x00000C48  // Ethernet MAC Current Host
+                                            // Transmit Descriptor
+#define EMAC_O_HOSRXDESC        0x00000C4C  // Ethernet MAC Current Host
+                                            // Receive Descriptor
+#define EMAC_O_HOSTXBA          0x00000C50  // Ethernet MAC Current Host
+                                            // Transmit Buffer Address
+#define EMAC_O_HOSRXBA          0x00000C54  // Ethernet MAC Current Host
+                                            // Receive Buffer Address
+#define EMAC_O_PP               0x00000FC0  // Ethernet MAC Peripheral Property
+                                            // Register
+#define EMAC_O_PC               0x00000FC4  // Ethernet MAC Peripheral
+                                            // Configuration Register
+#define EMAC_O_CC               0x00000FC8  // Ethernet MAC Clock Configuration
+                                            // Register
+#define EMAC_O_EPHYRIS          0x00000FD0  // Ethernet PHY Raw Interrupt
+                                            // Status
+#define EMAC_O_EPHYIM           0x00000FD4  // Ethernet PHY Interrupt Mask
+#define EMAC_O_EPHYMISC         0x00000FD8  // Ethernet PHY Masked Interrupt
+                                            // Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_CFG register.
+//
+//*****************************************************************************
+#define EMAC_CFG_TWOKPEN        0x08000000  // IEEE 802
+#define EMAC_CFG_CST            0x02000000  // CRC Stripping for Type Frames
+#define EMAC_CFG_WDDIS          0x00800000  // Watchdog Disable
+#define EMAC_CFG_JD             0x00400000  // Jabber Disable
+#define EMAC_CFG_JFEN           0x00100000  // Jumbo Frame Enable
+#define EMAC_CFG_IFG_M          0x000E0000  // Inter-Frame Gap (IFG)
+#define EMAC_CFG_IFG_96         0x00000000  // 96 bit times
+#define EMAC_CFG_IFG_88         0x00020000  // 88 bit times
+#define EMAC_CFG_IFG_80         0x00040000  // 80 bit times
+#define EMAC_CFG_IFG_72         0x00060000  // 72 bit times
+#define EMAC_CFG_IFG_64         0x00080000  // 64 bit times
+#define EMAC_CFG_IFG_56         0x000A0000  // 56 bit times
+#define EMAC_CFG_IFG_48         0x000C0000  // 48 bit times
+#define EMAC_CFG_IFG_40         0x000E0000  // 40 bit times
+#define EMAC_CFG_DISCRS         0x00010000  // Disable Carrier Sense During
+                                            // Transmission
+#define EMAC_CFG_PS             0x00008000  // Port Select
+#define EMAC_CFG_FES            0x00004000  // Speed
+#define EMAC_CFG_DRO            0x00002000  // Disable Receive Own
+#define EMAC_CFG_LOOPBM         0x00001000  // Loopback Mode
+#define EMAC_CFG_DUPM           0x00000800  // Duplex Mode
+#define EMAC_CFG_IPC            0x00000400  // Checksum Offload
+#define EMAC_CFG_DR             0x00000200  // Disable Retry
+#define EMAC_CFG_ACS            0x00000080  // Automatic Pad or CRC Stripping
+#define EMAC_CFG_BL_M           0x00000060  // Back-Off Limit
+#define EMAC_CFG_BL_1024        0x00000000  // k = min (n,10)
+#define EMAC_CFG_BL_256         0x00000020  // k = min (n,8)
+#define EMAC_CFG_BL_8           0x00000040  // k = min (n,4)
+#define EMAC_CFG_BL_2           0x00000060  // k = min (n,1)
+#define EMAC_CFG_DC             0x00000010  // Deferral Check
+#define EMAC_CFG_TE             0x00000008  // Transmitter Enable
+#define EMAC_CFG_RE             0x00000004  // Receiver Enable
+#define EMAC_CFG_PRELEN_M       0x00000003  // Preamble Length for Transmit
+                                            // Frames
+#define EMAC_CFG_PRELEN_7       0x00000000  // 7 bytes of preamble
+#define EMAC_CFG_PRELEN_5       0x00000001  // 5 bytes of preamble
+#define EMAC_CFG_PRELEN_3       0x00000002  // 3 bytes of preamble
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_FRAMEFLTR
+// register.
+//
+//*****************************************************************************
+#define EMAC_FRAMEFLTR_RA       0x80000000  // Receive All
+#define EMAC_FRAMEFLTR_VTFE     0x00010000  // VLAN Tag Filter Enable
+#define EMAC_FRAMEFLTR_HPF      0x00000400  // Hash or Perfect Filter
+#define EMAC_FRAMEFLTR_SAF      0x00000200  // Source Address Filter Enable
+#define EMAC_FRAMEFLTR_SAIF     0x00000100  // Source Address (SA) Inverse
+                                            // Filtering
+#define EMAC_FRAMEFLTR_PCF_M    0x000000C0  // Pass Control Frames
+#define EMAC_FRAMEFLTR_PCF_ALL  0x00000000  // The MAC filters all control
+                                            // frames from reaching application
+#define EMAC_FRAMEFLTR_PCF_PAUSE                                              \
+                                0x00000040  // MAC forwards all control frames
+                                            // except PAUSE control frames to
+                                            // application even if they fail
+                                            // the address filter
+#define EMAC_FRAMEFLTR_PCF_NONE 0x00000080  // MAC forwards all control frames
+                                            // to application even if they fail
+                                            // the address Filter
+#define EMAC_FRAMEFLTR_PCF_ADDR 0x000000C0  // MAC forwards control frames that
+                                            // pass the address Filter
+#define EMAC_FRAMEFLTR_DBF      0x00000020  // Disable Broadcast Frames
+#define EMAC_FRAMEFLTR_PM       0x00000010  // Pass All Multicast
+#define EMAC_FRAMEFLTR_DAIF     0x00000008  // Destination Address (DA) Inverse
+                                            // Filtering
+#define EMAC_FRAMEFLTR_HMC      0x00000004  // Hash Multicast
+#define EMAC_FRAMEFLTR_HUC      0x00000002  // Hash Unicast
+#define EMAC_FRAMEFLTR_PR       0x00000001  // Promiscuous Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_HASHTBLH
+// register.
+//
+//*****************************************************************************
+#define EMAC_HASHTBLH_HTH_M     0xFFFFFFFF  // Hash Table High
+#define EMAC_HASHTBLH_HTH_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_HASHTBLL
+// register.
+//
+//*****************************************************************************
+#define EMAC_HASHTBLL_HTL_M     0xFFFFFFFF  // Hash Table Low
+#define EMAC_HASHTBLL_HTL_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_MIIADDR register.
+//
+//*****************************************************************************
+#define EMAC_MIIADDR_PLA_M      0x0000F800  // Physical Layer Address
+#define EMAC_MIIADDR_MII_M      0x000007C0  // MII Register
+#define EMAC_MIIADDR_CR_M       0x0000003C  // Clock Reference Frequency
+                                            // Selection
+#define EMAC_MIIADDR_CR_60_100  0x00000000  // The frequency of the System
+                                            // Clock is 60 to 100 MHz providing
+                                            // a MDIO clock of SYSCLK/42
+#define EMAC_MIIADDR_CR_100_150 0x00000004  // The frequency of the System
+                                            // Clock is 100 to 150 MHz
+                                            // providing a MDIO clock of
+                                            // SYSCLK/62
+#define EMAC_MIIADDR_CR_20_35   0x00000008  // The frequency of the System
+                                            // Clock is 20-35 MHz providing a
+                                            // MDIO clock of System Clock/16
+#define EMAC_MIIADDR_CR_35_60   0x0000000C  // The frequency of the System
+                                            // Clock is 35 to 60 MHz providing
+                                            // a MDIO clock of System Clock/26
+#define EMAC_MIIADDR_MIIW       0x00000002  // MII Write
+#define EMAC_MIIADDR_MIIB       0x00000001  // MII Busy
+#define EMAC_MIIADDR_PLA_S      11
+#define EMAC_MIIADDR_MII_S      6
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_MIIDATA register.
+//
+//*****************************************************************************
+#define EMAC_MIIDATA_DATA_M     0x0000FFFF  // MII Data
+#define EMAC_MIIDATA_DATA_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_FLOWCTL register.
+//
+//*****************************************************************************
+#define EMAC_FLOWCTL_PT_M       0xFFFF0000  // Pause Time
+#define EMAC_FLOWCTL_DZQP       0x00000080  // Disable Zero-Quanta Pause
+#define EMAC_FLOWCTL_UP         0x00000008  // Unicast Pause Frame Detect
+#define EMAC_FLOWCTL_RFE        0x00000004  // Receive Flow Control Enable
+#define EMAC_FLOWCTL_TFE        0x00000002  // Transmit Flow Control Enable
+#define EMAC_FLOWCTL_FCBBPA     0x00000001  // Flow Control Busy or
+                                            // Back-pressure Activate
+#define EMAC_FLOWCTL_PT_S       16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_VLANTG register.
+//
+//*****************************************************************************
+#define EMAC_VLANTG_VTHM        0x00080000  // VLAN Tag Hash Table Match Enable
+#define EMAC_VLANTG_ESVL        0x00040000  // Enable S-VLAN
+#define EMAC_VLANTG_VTIM        0x00020000  // VLAN Tag Inverse Match Enable
+#define EMAC_VLANTG_ETV         0x00010000  // Enable 12-Bit VLAN Tag
+                                            // Comparison
+#define EMAC_VLANTG_VL_M        0x0000FFFF  // VLAN Tag Identifier for Receive
+                                            // Frames
+#define EMAC_VLANTG_VL_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_STATUS register.
+//
+//*****************************************************************************
+#define EMAC_STATUS_TXFF        0x02000000  // TX/RX Controller TX FIFO Full
+                                            // Status
+#define EMAC_STATUS_TXFE        0x01000000  // TX/RX Controller TX FIFO Not
+                                            // Empty Status
+#define EMAC_STATUS_TWC         0x00400000  // TX/RX Controller TX FIFO Write
+                                            // Controller Active Status
+#define EMAC_STATUS_TRC_M       0x00300000  // TX/RX Controller's TX FIFO Read
+                                            // Controller Status
+#define EMAC_STATUS_TRC_IDLE    0x00000000  // IDLE state
+#define EMAC_STATUS_TRC_READ    0x00100000  // READ state (transferring data to
+                                            // MAC transmitter)
+#define EMAC_STATUS_TRC_WAIT    0x00200000  // Waiting for TX Status from MAC
+                                            // transmitter
+#define EMAC_STATUS_TRC_WRFLUSH 0x00300000  // Writing the received TX Status
+                                            // or flushing the TX FIFO
+#define EMAC_STATUS_TXPAUSED    0x00080000  // MAC Transmitter PAUSE
+#define EMAC_STATUS_TFC_M       0x00060000  // MAC Transmit Frame Controller
+                                            // Status
+#define EMAC_STATUS_TFC_IDLE    0x00000000  // IDLE state
+#define EMAC_STATUS_TFC_STATUS  0x00020000  // Waiting for status of previous
+                                            // frame or IFG or backoff period
+                                            // to be over
+#define EMAC_STATUS_TFC_PAUSE   0x00040000  // Generating and transmitting a
+                                            // PAUSE control frame (in the
+                                            // full-duplex mode)
+#define EMAC_STATUS_TFC_INPUT   0x00060000  // Transferring input frame for
+                                            // transmission
+#define EMAC_STATUS_TPE         0x00010000  // MAC MII Transmit Protocol Engine
+                                            // Status
+#define EMAC_STATUS_RXF_M       0x00000300  // TX/RX Controller RX FIFO
+                                            // Fill-level Status
+#define EMAC_STATUS_RXF_EMPTY   0x00000000  // RX FIFO Empty
+#define EMAC_STATUS_RXF_BELOW   0x00000100  // RX FIFO fill level is below the
+                                            // flow-control deactivate
+                                            // threshold
+#define EMAC_STATUS_RXF_ABOVE   0x00000200  // RX FIFO fill level is above the
+                                            // flow-control activate threshold
+#define EMAC_STATUS_RXF_FULL    0x00000300  // RX FIFO Full
+#define EMAC_STATUS_RRC_M       0x00000060  // TX/RX Controller Read Controller
+                                            // State
+#define EMAC_STATUS_RRC_IDLE    0x00000000  // IDLE state
+#define EMAC_STATUS_RRC_STATUS  0x00000020  // Reading frame data
+#define EMAC_STATUS_RRC_DATA    0x00000040  // Reading frame status (or
+                                            // timestamp)
+#define EMAC_STATUS_RRC_FLUSH   0x00000060  // Flushing the frame data and
+                                            // status
+#define EMAC_STATUS_RWC         0x00000010  // TX/RX Controller RX FIFO Write
+                                            // Controller Active Status
+#define EMAC_STATUS_RFCFC_M     0x00000006  // MAC Receive Frame Controller
+                                            // FIFO Status
+#define EMAC_STATUS_RPE         0x00000001  // MAC MII Receive Protocol Engine
+                                            // Status
+#define EMAC_STATUS_RFCFC_S     1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_RWUFF register.
+//
+//*****************************************************************************
+#define EMAC_RWUFF_WAKEUPFIL_M  0xFFFFFFFF  // Remote Wake-Up Frame Filter
+#define EMAC_RWUFF_WAKEUPFIL_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_PMTCTLSTAT
+// register.
+//
+//*****************************************************************************
+#define EMAC_PMTCTLSTAT_WUPFRRST                                              \
+                                0x80000000  // Wake-Up Frame Filter Register
+                                            // Pointer Reset
+#define EMAC_PMTCTLSTAT_RWKPTR_M                                              \
+                                0x07000000  // Remote Wake-Up FIFO Pointer
+#define EMAC_PMTCTLSTAT_GLBLUCAST                                             \
+                                0x00000200  // Global Unicast
+#define EMAC_PMTCTLSTAT_WUPRX   0x00000040  // Wake-Up Frame Received
+#define EMAC_PMTCTLSTAT_MGKPRX  0x00000020  // Magic Packet Received
+#define EMAC_PMTCTLSTAT_WUPFREN 0x00000004  // Wake-Up Frame Enable
+#define EMAC_PMTCTLSTAT_MGKPKTEN                                              \
+                                0x00000002  // Magic Packet Enable
+#define EMAC_PMTCTLSTAT_PWRDWN  0x00000001  // Power Down
+#define EMAC_PMTCTLSTAT_RWKPTR_S                                              \
+                                24
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_RIS register.
+//
+//*****************************************************************************
+#define EMAC_RIS_TS             0x00000200  // Timestamp Interrupt Status
+#define EMAC_RIS_MMCTX          0x00000040  // MMC Transmit Interrupt Status
+#define EMAC_RIS_MMCRX          0x00000020  // MMC Receive Interrupt Status
+#define EMAC_RIS_MMC            0x00000010  // MMC Interrupt Status
+#define EMAC_RIS_PMT            0x00000008  // PMT Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_IM register.
+//
+//*****************************************************************************
+#define EMAC_IM_TSI             0x00000200  // Timestamp Interrupt Mask
+#define EMAC_IM_PMT             0x00000008  // PMT Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_ADDR0H register.
+//
+//*****************************************************************************
+#define EMAC_ADDR0H_AE          0x80000000  // Address Enable
+#define EMAC_ADDR0H_ADDRHI_M    0x0000FFFF  // MAC Address0 [47:32]
+#define EMAC_ADDR0H_ADDRHI_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_ADDR0L register.
+//
+//*****************************************************************************
+#define EMAC_ADDR0L_ADDRLO_M    0xFFFFFFFF  // MAC Address0 [31:0]
+#define EMAC_ADDR0L_ADDRLO_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_ADDR1H register.
+//
+//*****************************************************************************
+#define EMAC_ADDR1H_AE          0x80000000  // Address Enable
+#define EMAC_ADDR1H_SA          0x40000000  // Source Address
+#define EMAC_ADDR1H_MBC_M       0x3F000000  // Mask Byte Control
+#define EMAC_ADDR1H_ADDRHI_M    0x0000FFFF  // MAC Address1 [47:32]
+#define EMAC_ADDR1H_MBC_S       24
+#define EMAC_ADDR1H_ADDRHI_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_ADDR1L register.
+//
+//*****************************************************************************
+#define EMAC_ADDR1L_ADDRLO_M    0xFFFFFFFF  // MAC Address1 [31:0]
+#define EMAC_ADDR1L_ADDRLO_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_ADDR2H register.
+//
+//*****************************************************************************
+#define EMAC_ADDR2H_AE          0x80000000  // Address Enable
+#define EMAC_ADDR2H_SA          0x40000000  // Source Address
+#define EMAC_ADDR2H_MBC_M       0x3F000000  // Mask Byte Control
+#define EMAC_ADDR2H_ADDRHI_M    0x0000FFFF  // MAC Address2 [47:32]
+#define EMAC_ADDR2H_MBC_S       24
+#define EMAC_ADDR2H_ADDRHI_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_ADDR2L register.
+//
+//*****************************************************************************
+#define EMAC_ADDR2L_ADDRLO_M    0xFFFFFFFF  // MAC Address2 [31:0]
+#define EMAC_ADDR2L_ADDRLO_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_ADDR3H register.
+//
+//*****************************************************************************
+#define EMAC_ADDR3H_AE          0x80000000  // Address Enable
+#define EMAC_ADDR3H_SA          0x40000000  // Source Address
+#define EMAC_ADDR3H_MBC_M       0x3F000000  // Mask Byte Control
+#define EMAC_ADDR3H_ADDRHI_M    0x0000FFFF  // MAC Address3 [47:32]
+#define EMAC_ADDR3H_MBC_S       24
+#define EMAC_ADDR3H_ADDRHI_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_ADDR3L register.
+//
+//*****************************************************************************
+#define EMAC_ADDR3L_ADDRLO_M    0xFFFFFFFF  // MAC Address3 [31:0]
+#define EMAC_ADDR3L_ADDRLO_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_WDOGTO register.
+//
+//*****************************************************************************
+#define EMAC_WDOGTO_PWE         0x00010000  // Programmable Watchdog Enable
+#define EMAC_WDOGTO_WTO_M       0x00003FFF  // Watchdog Timeout
+#define EMAC_WDOGTO_WTO_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_MMCCTRL register.
+//
+//*****************************************************************************
+#define EMAC_MMCCTRL_UCDBC      0x00000100  // Update MMC Counters for Dropped
+                                            // Broadcast Frames
+#define EMAC_MMCCTRL_CNTPRSTLVL 0x00000020  // Full/Half Preset Level Value
+#define EMAC_MMCCTRL_CNTPRST    0x00000010  // Counters Preset
+#define EMAC_MMCCTRL_CNTFREEZ   0x00000008  // MMC Counter Freeze
+#define EMAC_MMCCTRL_RSTONRD    0x00000004  // Reset on Read
+#define EMAC_MMCCTRL_CNTSTPRO   0x00000002  // Counters Stop Rollover
+#define EMAC_MMCCTRL_CNTRST     0x00000001  // Counters Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_MMCRXRIS
+// register.
+//
+//*****************************************************************************
+#define EMAC_MMCRXRIS_UCGF      0x00020000  // MMC Receive Unicast Good Frame
+                                            // Counter Interrupt Status
+#define EMAC_MMCRXRIS_ALGNERR   0x00000040  // MMC Receive Alignment Error
+                                            // Frame Counter Interrupt Status
+#define EMAC_MMCRXRIS_CRCERR    0x00000020  // MMC Receive CRC Error Frame
+                                            // Counter Interrupt Status
+#define EMAC_MMCRXRIS_GBF       0x00000001  // MMC Receive Good Bad Frame
+                                            // Counter Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_MMCTXRIS
+// register.
+//
+//*****************************************************************************
+#define EMAC_MMCTXRIS_OCTCNT    0x00100000  // Octet Counter Interrupt Status
+#define EMAC_MMCTXRIS_MCOLLGF   0x00008000  // MMC Transmit Multiple Collision
+                                            // Good Frame Counter Interrupt
+                                            // Status
+#define EMAC_MMCTXRIS_SCOLLGF   0x00004000  // MMC Transmit Single Collision
+                                            // Good Frame Counter Interrupt
+                                            // Status
+#define EMAC_MMCTXRIS_GBF       0x00000002  // MMC Transmit Good Bad Frame
+                                            // Counter Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_MMCRXIM register.
+//
+//*****************************************************************************
+#define EMAC_MMCRXIM_UCGF       0x00020000  // MMC Receive Unicast Good Frame
+                                            // Counter Interrupt Mask
+#define EMAC_MMCRXIM_ALGNERR    0x00000040  // MMC Receive Alignment Error
+                                            // Frame Counter Interrupt Mask
+#define EMAC_MMCRXIM_CRCERR     0x00000020  // MMC Receive CRC Error Frame
+                                            // Counter Interrupt Mask
+#define EMAC_MMCRXIM_GBF        0x00000001  // MMC Receive Good Bad Frame
+                                            // Counter Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_MMCTXIM register.
+//
+//*****************************************************************************
+#define EMAC_MMCTXIM_OCTCNT     0x00100000  // MMC Transmit Good Octet Counter
+                                            // Interrupt Mask
+#define EMAC_MMCTXIM_MCOLLGF    0x00008000  // MMC Transmit Multiple Collision
+                                            // Good Frame Counter Interrupt
+                                            // Mask
+#define EMAC_MMCTXIM_SCOLLGF    0x00004000  // MMC Transmit Single Collision
+                                            // Good Frame Counter Interrupt
+                                            // Mask
+#define EMAC_MMCTXIM_GBF        0x00000002  // MMC Transmit Good Bad Frame
+                                            // Counter Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TXCNTGB register.
+//
+//*****************************************************************************
+#define EMAC_TXCNTGB_TXFRMGB_M  0xFFFFFFFF  // This field indicates the number
+                                            // of good and bad frames
+                                            // transmitted, exclusive of
+                                            // retried frames
+#define EMAC_TXCNTGB_TXFRMGB_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TXCNTSCOL
+// register.
+//
+//*****************************************************************************
+#define EMAC_TXCNTSCOL_TXSNGLCOLG_M                                           \
+                                0xFFFFFFFF  // This field indicates the number
+                                            // of successfully transmitted
+                                            // frames after a single collision
+                                            // in the half-duplex mode
+#define EMAC_TXCNTSCOL_TXSNGLCOLG_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TXCNTMCOL
+// register.
+//
+//*****************************************************************************
+#define EMAC_TXCNTMCOL_TXMULTCOLG_M                                           \
+                                0xFFFFFFFF  // This field indicates the number
+                                            // of successfully transmitted
+                                            // frames after multiple collisions
+                                            // in the half-duplex mode
+#define EMAC_TXCNTMCOL_TXMULTCOLG_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TXOCTCNTG
+// register.
+//
+//*****************************************************************************
+#define EMAC_TXOCTCNTG_TXOCTG_M 0xFFFFFFFF  // This field indicates the number
+                                            // of bytes transmitted, exclusive
+                                            // of preamble, in good frames
+#define EMAC_TXOCTCNTG_TXOCTG_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_RXCNTGB register.
+//
+//*****************************************************************************
+#define EMAC_RXCNTGB_RXFRMGB_M  0xFFFFFFFF  // This field indicates the number
+                                            // of received good and bad frames
+#define EMAC_RXCNTGB_RXFRMGB_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_RXCNTCRCERR
+// register.
+//
+//*****************************************************************************
+#define EMAC_RXCNTCRCERR_RXCRCERR_M                                           \
+                                0xFFFFFFFF  // This field indicates the number
+                                            // of frames received with CRC
+                                            // error
+#define EMAC_RXCNTCRCERR_RXCRCERR_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_RXCNTALGNERR
+// register.
+//
+//*****************************************************************************
+#define EMAC_RXCNTALGNERR_RXALGNERR_M                                         \
+                                0xFFFFFFFF  // This field indicates the number
+                                            // of frames received with
+                                            // alignment (dribble) error
+#define EMAC_RXCNTALGNERR_RXALGNERR_S                                         \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_RXCNTGUNI
+// register.
+//
+//*****************************************************************************
+#define EMAC_RXCNTGUNI_RXUCASTG_M                                             \
+                                0xFFFFFFFF  // This field indicates the number
+                                            // of received good unicast frames
+#define EMAC_RXCNTGUNI_RXUCASTG_S                                             \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_VLNINCREP
+// register.
+//
+//*****************************************************************************
+#define EMAC_VLNINCREP_CSVL     0x00080000  // C-VLAN or S-VLAN
+#define EMAC_VLNINCREP_VLP      0x00040000  // VLAN Priority Control
+#define EMAC_VLNINCREP_VLC_M    0x00030000  // VLAN Tag Control in Transmit
+                                            // Frames
+#define EMAC_VLNINCREP_VLC_NONE 0x00000000  // No VLAN tag deletion, insertion,
+                                            // or replacement
+#define EMAC_VLNINCREP_VLC_TAGDEL                                             \
+                                0x00010000  // VLAN tag deletion
+#define EMAC_VLNINCREP_VLC_TAGINS                                             \
+                                0x00020000  // VLAN tag insertion
+#define EMAC_VLNINCREP_VLC_TAGREP                                             \
+                                0x00030000  // VLAN tag replacement
+#define EMAC_VLNINCREP_VLT_M    0x0000FFFF  // VLAN Tag for Transmit Frames
+#define EMAC_VLNINCREP_VLT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_VLANHASH
+// register.
+//
+//*****************************************************************************
+#define EMAC_VLANHASH_VLHT_M    0x0000FFFF  // VLAN Hash Table
+#define EMAC_VLANHASH_VLHT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TIMSTCTRL
+// register.
+//
+//*****************************************************************************
+#define EMAC_TIMSTCTRL_PTPFLTR  0x00040000  // Enable MAC address for PTP Frame
+                                            // Filtering
+#define EMAC_TIMSTCTRL_SELPTP_M 0x00030000  // Select PTP packets for Taking
+                                            // Snapshots
+#define EMAC_TIMSTCTRL_TSMAST   0x00008000  // Enable Snapshot for Messages
+                                            // Relevant to Master
+#define EMAC_TIMSTCTRL_TSEVNT   0x00004000  // Enable Timestamp Snapshot for
+                                            // Event Messages
+#define EMAC_TIMSTCTRL_PTPIPV4  0x00002000  // Enable Processing of PTP Frames
+                                            // Sent over IPv4-UDP
+#define EMAC_TIMSTCTRL_PTPIPV6  0x00001000  // Enable Processing of PTP Frames
+                                            // Sent Over IPv6-UDP
+#define EMAC_TIMSTCTRL_PTPETH   0x00000800  // Enable Processing of PTP Over
+                                            // Ethernet Frames
+#define EMAC_TIMSTCTRL_PTPVER2  0x00000400  // Enable PTP Packet Processing For
+                                            // Version 2 Format
+#define EMAC_TIMSTCTRL_DGTLBIN  0x00000200  // Timestamp Digital or Binary
+                                            // Rollover Control
+#define EMAC_TIMSTCTRL_ALLF     0x00000100  // Enable Timestamp For All Frames
+#define EMAC_TIMSTCTRL_ADDREGUP 0x00000020  // Addend Register Update
+#define EMAC_TIMSTCTRL_INTTRIG  0x00000010  // Timestamp Interrupt Trigger
+                                            // Enable
+#define EMAC_TIMSTCTRL_TSUPDT   0x00000008  // Timestamp Update
+#define EMAC_TIMSTCTRL_TSINIT   0x00000004  // Timestamp Initialize
+#define EMAC_TIMSTCTRL_TSFCUPDT 0x00000002  // Timestamp Fine or Coarse Update
+#define EMAC_TIMSTCTRL_TSEN     0x00000001  // Timestamp Enable
+#define EMAC_TIMSTCTRL_SELPTP_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_SUBSECINC
+// register.
+//
+//*****************************************************************************
+#define EMAC_SUBSECINC_SSINC_M  0x000000FF  // Sub-second Increment Value
+#define EMAC_SUBSECINC_SSINC_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TIMSEC register.
+//
+//*****************************************************************************
+#define EMAC_TIMSEC_TSS_M       0xFFFFFFFF  // Timestamp Second
+#define EMAC_TIMSEC_TSS_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TIMNANO register.
+//
+//*****************************************************************************
+#define EMAC_TIMNANO_TSSS_M     0x7FFFFFFF  // Timestamp Sub-Seconds
+#define EMAC_TIMNANO_TSSS_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TIMSECU register.
+//
+//*****************************************************************************
+#define EMAC_TIMSECU_TSS_M      0xFFFFFFFF  // Timestamp Second
+#define EMAC_TIMSECU_TSS_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TIMNANOU
+// register.
+//
+//*****************************************************************************
+#define EMAC_TIMNANOU_ADDSUB    0x80000000  // Add or subtract time
+#define EMAC_TIMNANOU_TSSS_M    0x7FFFFFFF  // Timestamp Sub-Second
+#define EMAC_TIMNANOU_TSSS_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TIMADD register.
+//
+//*****************************************************************************
+#define EMAC_TIMADD_TSAR_M      0xFFFFFFFF  // Timestamp Addend Register
+#define EMAC_TIMADD_TSAR_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TARGSEC register.
+//
+//*****************************************************************************
+#define EMAC_TARGSEC_TSTR_M     0xFFFFFFFF  // Target Time Seconds Register
+#define EMAC_TARGSEC_TSTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TARGNANO
+// register.
+//
+//*****************************************************************************
+#define EMAC_TARGNANO_TRGTBUSY  0x80000000  // Target Time Register Busy
+#define EMAC_TARGNANO_TTSLO_M   0x7FFFFFFF  // Target Timestamp Low Register
+#define EMAC_TARGNANO_TTSLO_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_HWORDSEC
+// register.
+//
+//*****************************************************************************
+#define EMAC_HWORDSEC_TSHWR_M   0x0000FFFF  // Target Timestamp Higher Word
+                                            // Register
+#define EMAC_HWORDSEC_TSHWR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TIMSTAT register.
+//
+//*****************************************************************************
+#define EMAC_TIMSTAT_TSTARGT    0x00000002  // Timestamp Target Time Reached
+#define EMAC_TIMSTAT_TSSOVF     0x00000001  // Timestamp Seconds Overflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_PPSCTRL register.
+//
+//*****************************************************************************
+#define EMAC_PPSCTRL_TRGMODS0_M 0x00000060  // Target Time Register Mode for
+                                            // PPS0 Output
+#define EMAC_PPSCTRL_TRGMODS0_INTONLY                                         \
+                                0x00000000  // Indicates that the Target Time
+                                            // registers are programmed only
+                                            // for generating the interrupt
+                                            // event
+#define EMAC_PPSCTRL_TRGMODS0_INTPPS0                                         \
+                                0x00000040  // Indicates that the Target Time
+                                            // registers are programmed for
+                                            // generating the interrupt event
+                                            // and starting or stopping the
+                                            // generation of the EN0PPS output
+                                            // signal
+#define EMAC_PPSCTRL_TRGMODS0_PPS0ONLY                                        \
+                                0x00000060  // Indicates that the Target Time
+                                            // registers are programmed only
+                                            // for starting or stopping the
+                                            // generation of the EN0PPS output
+                                            // signal. No interrupt is asserted
+#define EMAC_PPSCTRL_PPSEN0     0x00000010  // Flexible PPS Output Mode Enable
+#define EMAC_PPSCTRL_PPSCTRL_M  0x0000000F  // EN0PPS Output Frequency Control
+                                            // (PPSCTRL) or Command Control
+                                            // (PPSCMD)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_PPS0INTVL
+// register.
+//
+//*****************************************************************************
+#define EMAC_PPS0INTVL_PPS0INT_M                                              \
+                                0xFFFFFFFF  // PPS0 Output Signal Interval
+#define EMAC_PPS0INTVL_PPS0INT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_PPS0WIDTH
+// register.
+//
+//*****************************************************************************
+#define EMAC_PPS0WIDTH_M        0xFFFFFFFF  // EN0PPS Output Signal Width
+#define EMAC_PPS0WIDTH_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_DMABUSMOD
+// register.
+//
+//*****************************************************************************
+#define EMAC_DMABUSMOD_RIB      0x80000000  // Rebuild Burst
+#define EMAC_DMABUSMOD_TXPR     0x08000000  // Transmit Priority
+#define EMAC_DMABUSMOD_MB       0x04000000  // Mixed Burst
+#define EMAC_DMABUSMOD_AAL      0x02000000  // Address Aligned Beats
+#define EMAC_DMABUSMOD_8XPBL    0x01000000  // 8 x Programmable Burst Length
+                                            // (PBL) Mode
+#define EMAC_DMABUSMOD_USP      0x00800000  // Use Separate Programmable Burst
+                                            // Length (PBL)
+#define EMAC_DMABUSMOD_RPBL_M   0x007E0000  // RX DMA Programmable Burst Length
+                                            // (PBL)
+#define EMAC_DMABUSMOD_FB       0x00010000  // Fixed Burst
+#define EMAC_DMABUSMOD_PR_M     0x0000C000  // Priority Ratio
+#define EMAC_DMABUSMOD_PBL_M    0x00003F00  // Programmable Burst Length
+#define EMAC_DMABUSMOD_ATDS     0x00000080  // Alternate Descriptor Size
+#define EMAC_DMABUSMOD_DSL_M    0x0000007C  // Descriptor Skip Length
+#define EMAC_DMABUSMOD_DA       0x00000002  // DMA Arbitration Scheme
+#define EMAC_DMABUSMOD_SWR      0x00000001  // DMA Software Reset
+#define EMAC_DMABUSMOD_RPBL_S   17
+#define EMAC_DMABUSMOD_PR_S     14
+#define EMAC_DMABUSMOD_PBL_S    8
+#define EMAC_DMABUSMOD_DSL_S    2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TXPOLLD register.
+//
+//*****************************************************************************
+#define EMAC_TXPOLLD_TPD_M      0xFFFFFFFF  // Transmit Poll Demand
+#define EMAC_TXPOLLD_TPD_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_RXPOLLD register.
+//
+//*****************************************************************************
+#define EMAC_RXPOLLD_RPD_M      0xFFFFFFFF  // Receive Poll Demand
+#define EMAC_RXPOLLD_RPD_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_RXDLADDR
+// register.
+//
+//*****************************************************************************
+#define EMAC_RXDLADDR_STRXLIST_M                                              \
+                                0xFFFFFFFC  // Start of Receive List
+#define EMAC_RXDLADDR_STRXLIST_S                                              \
+                                2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TXDLADDR
+// register.
+//
+//*****************************************************************************
+#define EMAC_TXDLADDR_TXDLADDR_M                                              \
+                                0xFFFFFFFC  // Start of Transmit List Base
+                                            // Address
+#define EMAC_TXDLADDR_TXDLADDR_S                                              \
+                                2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_DMARIS register.
+//
+//*****************************************************************************
+#define EMAC_DMARIS_TT          0x20000000  // Timestamp Trigger Interrupt
+                                            // Status
+#define EMAC_DMARIS_PMT         0x10000000  // MAC PMT Interrupt Status
+#define EMAC_DMARIS_MMC         0x08000000  // MAC MMC Interrupt
+#define EMAC_DMARIS_AE_M        0x03800000  // Access Error
+#define EMAC_DMARIS_AE_RXDMAWD  0x00000000  // Error during RX DMA Write Data
+                                            // Transfer
+#define EMAC_DMARIS_AE_TXDMARD  0x01800000  // Error during TX DMA Read Data
+                                            // Transfer
+#define EMAC_DMARIS_AE_RXDMADW  0x02000000  // Error during RX DMA Descriptor
+                                            // Write Access
+#define EMAC_DMARIS_AE_TXDMADW  0x02800000  // Error during TX DMA Descriptor
+                                            // Write Access
+#define EMAC_DMARIS_AE_RXDMADR  0x03000000  // Error during RX DMA Descriptor
+                                            // Read Access
+#define EMAC_DMARIS_AE_TXDMADR  0x03800000  // Error during TX DMA Descriptor
+                                            // Read Access
+#define EMAC_DMARIS_TS_M        0x00700000  // Transmit Process State
+#define EMAC_DMARIS_TS_STOP     0x00000000  // Stopped; Reset or Stop transmit
+                                            // command processed
+#define EMAC_DMARIS_TS_RUNTXTD  0x00100000  // Running; Fetching transmit
+                                            // transfer descriptor
+#define EMAC_DMARIS_TS_STATUS   0x00200000  // Running; Waiting for status
+#define EMAC_DMARIS_TS_RUNTX    0x00300000  // Running; Reading data from host
+                                            // memory buffer and queuing it to
+                                            // transmit buffer (TX FIFO)
+#define EMAC_DMARIS_TS_TSTAMP   0x00400000  // Writing Timestamp
+#define EMAC_DMARIS_TS_SUSPEND  0x00600000  // Suspended; Transmit descriptor
+                                            // unavailable or transmit buffer
+                                            // underflow
+#define EMAC_DMARIS_TS_RUNCTD   0x00700000  // Running; Closing transmit
+                                            // descriptor
+#define EMAC_DMARIS_RS_M        0x000E0000  // Received Process State
+#define EMAC_DMARIS_RS_STOP     0x00000000  // Stopped: Reset or stop receive
+                                            // command issued
+#define EMAC_DMARIS_RS_RUNRXTD  0x00020000  // Running: Fetching receive
+                                            // transfer descriptor
+#define EMAC_DMARIS_RS_RUNRXD   0x00060000  // Running: Waiting for receive
+                                            // packet
+#define EMAC_DMARIS_RS_SUSPEND  0x00080000  // Suspended: Receive descriptor
+                                            // unavailable
+#define EMAC_DMARIS_RS_RUNCRD   0x000A0000  // Running: Closing receive
+                                            // descriptor
+#define EMAC_DMARIS_RS_TSWS     0x000C0000  // Writing Timestamp
+#define EMAC_DMARIS_RS_RUNTXD   0x000E0000  // Running: Transferring the
+                                            // receive packet data from receive
+                                            // buffer to host memory
+#define EMAC_DMARIS_NIS         0x00010000  // Normal Interrupt Summary
+#define EMAC_DMARIS_AIS         0x00008000  // Abnormal Interrupt Summary
+#define EMAC_DMARIS_ERI         0x00004000  // Early Receive Interrupt
+#define EMAC_DMARIS_FBI         0x00002000  // Fatal Bus Error Interrupt
+#define EMAC_DMARIS_ETI         0x00000400  // Early Transmit Interrupt
+#define EMAC_DMARIS_RWT         0x00000200  // Receive Watchdog Timeout
+#define EMAC_DMARIS_RPS         0x00000100  // Receive Process Stopped
+#define EMAC_DMARIS_RU          0x00000080  // Receive Buffer Unavailable
+#define EMAC_DMARIS_RI          0x00000040  // Receive Interrupt
+#define EMAC_DMARIS_UNF         0x00000020  // Transmit Underflow
+#define EMAC_DMARIS_OVF         0x00000010  // Receive Overflow
+#define EMAC_DMARIS_TJT         0x00000008  // Transmit Jabber Timeout
+#define EMAC_DMARIS_TU          0x00000004  // Transmit Buffer Unavailable
+#define EMAC_DMARIS_TPS         0x00000002  // Transmit Process Stopped
+#define EMAC_DMARIS_TI          0x00000001  // Transmit Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_DMAOPMODE
+// register.
+//
+//*****************************************************************************
+#define EMAC_DMAOPMODE_DT       0x04000000  // Disable Dropping of TCP/IP
+                                            // Checksum Error Frames
+#define EMAC_DMAOPMODE_RSF      0x02000000  // Receive Store and Forward
+#define EMAC_DMAOPMODE_DFF      0x01000000  // Disable Flushing of Received
+                                            // Frames
+#define EMAC_DMAOPMODE_TSF      0x00200000  // Transmit Store and Forward
+#define EMAC_DMAOPMODE_FTF      0x00100000  // Flush Transmit FIFO
+#define EMAC_DMAOPMODE_TTC_M    0x0001C000  // Transmit Threshold Control
+#define EMAC_DMAOPMODE_TTC_64   0x00000000  // 64 bytes
+#define EMAC_DMAOPMODE_TTC_128  0x00004000  // 128 bytes
+#define EMAC_DMAOPMODE_TTC_192  0x00008000  // 192 bytes
+#define EMAC_DMAOPMODE_TTC_256  0x0000C000  // 256 bytes
+#define EMAC_DMAOPMODE_TTC_40   0x00010000  // 40 bytes
+#define EMAC_DMAOPMODE_TTC_32   0x00014000  // 32 bytes
+#define EMAC_DMAOPMODE_TTC_24   0x00018000  // 24 bytes
+#define EMAC_DMAOPMODE_TTC_16   0x0001C000  // 16 bytes
+#define EMAC_DMAOPMODE_ST       0x00002000  // Start or Stop Transmission
+                                            // Command
+#define EMAC_DMAOPMODE_FEF      0x00000080  // Forward Error Frames
+#define EMAC_DMAOPMODE_FUF      0x00000040  // Forward Undersized Good Frames
+#define EMAC_DMAOPMODE_DGF      0x00000020  // Drop Giant Frame Enable
+#define EMAC_DMAOPMODE_RTC_M    0x00000018  // Receive Threshold Control
+#define EMAC_DMAOPMODE_RTC_64   0x00000000  // 64 bytes
+#define EMAC_DMAOPMODE_RTC_32   0x00000008  // 32 bytes
+#define EMAC_DMAOPMODE_RTC_96   0x00000010  // 96 bytes
+#define EMAC_DMAOPMODE_RTC_128  0x00000018  // 128 bytes
+#define EMAC_DMAOPMODE_OSF      0x00000004  // Operate on Second Frame
+#define EMAC_DMAOPMODE_SR       0x00000002  // Start or Stop Receive
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_DMAIM register.
+//
+//*****************************************************************************
+#define EMAC_DMAIM_NIE          0x00010000  // Normal Interrupt Summary Enable
+#define EMAC_DMAIM_AIE          0x00008000  // Abnormal Interrupt Summary
+                                            // Enable
+#define EMAC_DMAIM_ERE          0x00004000  // Early Receive Interrupt Enable
+#define EMAC_DMAIM_FBE          0x00002000  // Fatal Bus Error Enable
+#define EMAC_DMAIM_ETE          0x00000400  // Early Transmit Interrupt Enable
+#define EMAC_DMAIM_RWE          0x00000200  // Receive Watchdog Timeout Enable
+#define EMAC_DMAIM_RSE          0x00000100  // Receive Stopped Enable
+#define EMAC_DMAIM_RUE          0x00000080  // Receive Buffer Unavailable
+                                            // Enable
+#define EMAC_DMAIM_RIE          0x00000040  // Receive Interrupt Enable
+#define EMAC_DMAIM_UNE          0x00000020  // Underflow Interrupt Enable
+#define EMAC_DMAIM_OVE          0x00000010  // Overflow Interrupt Enable
+#define EMAC_DMAIM_TJE          0x00000008  // Transmit Jabber Timeout Enable
+#define EMAC_DMAIM_TUE          0x00000004  // Transmit Buffer Unvailable
+                                            // Enable
+#define EMAC_DMAIM_TSE          0x00000002  // Transmit Stopped Enable
+#define EMAC_DMAIM_TIE          0x00000001  // Transmit Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_MFBOC register.
+//
+//*****************************************************************************
+#define EMAC_MFBOC_OVFCNTOVF    0x10000000  // Overflow Bit for FIFO Overflow
+                                            // Counter
+#define EMAC_MFBOC_OVFFRMCNT_M  0x0FFE0000  // Overflow Frame Counter
+#define EMAC_MFBOC_MISCNTOVF    0x00010000  // Overflow bit for Missed Frame
+                                            // Counter
+#define EMAC_MFBOC_MISFRMCNT_M  0x0000FFFF  // Missed Frame Counter
+#define EMAC_MFBOC_OVFFRMCNT_S  17
+#define EMAC_MFBOC_MISFRMCNT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_RXINTWDT
+// register.
+//
+//*****************************************************************************
+#define EMAC_RXINTWDT_RIWT_M    0x000000FF  // Receive Interrupt Watchdog Timer
+                                            // Count
+#define EMAC_RXINTWDT_RIWT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_HOSTXDESC
+// register.
+//
+//*****************************************************************************
+#define EMAC_HOSTXDESC_CURTXDESC_M                                            \
+                                0xFFFFFFFF  // Host Transmit Descriptor Address
+                                            // Pointer
+#define EMAC_HOSTXDESC_CURTXDESC_S                                            \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_HOSRXDESC
+// register.
+//
+//*****************************************************************************
+#define EMAC_HOSRXDESC_CURRXDESC_M                                            \
+                                0xFFFFFFFF  // Host Receive Descriptor Address
+                                            // Pointer
+#define EMAC_HOSRXDESC_CURRXDESC_S                                            \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_HOSTXBA register.
+//
+//*****************************************************************************
+#define EMAC_HOSTXBA_CURTXBUFA_M                                              \
+                                0xFFFFFFFF  // Host Transmit Buffer Address
+                                            // Pointer
+#define EMAC_HOSTXBA_CURTXBUFA_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_HOSRXBA register.
+//
+//*****************************************************************************
+#define EMAC_HOSRXBA_CURRXBUFA_M                                              \
+                                0xFFFFFFFF  // Host Receive Buffer Address
+                                            // Pointer
+#define EMAC_HOSRXBA_CURRXBUFA_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_PP register.
+//
+//*****************************************************************************
+#define EMAC_PP_MACTYPE_M       0x00000700  // Ethernet MAC Type
+#define EMAC_PP_MACTYPE_1       0x00000100  // Tiva TM4E129x-class MAC
+#define EMAC_PP_PHYTYPE_M       0x00000007  // Ethernet PHY Type
+#define EMAC_PP_PHYTYPE_NONE    0x00000000  // No PHY
+#define EMAC_PP_PHYTYPE_1       0x00000003  // Snowflake class PHY
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_PC register.
+//
+//*****************************************************************************
+#define EMAC_PC_PHYEXT          0x80000000  // PHY Select
+#define EMAC_PC_PINTFS_M        0x70000000  // Ethernet Interface Select
+#define EMAC_PC_PINTFS_IMII     0x00000000  // MII (default) Used for internal
+                                            // PHY or external PHY connected
+                                            // via MII
+#define EMAC_PC_PINTFS_RMII     0x40000000  // RMII: Used for external PHY
+                                            // connected via RMII
+#define EMAC_PC_DIGRESTART      0x02000000  // PHY Soft Restart
+#define EMAC_PC_NIBDETDIS       0x01000000  // Odd Nibble TXER Detection
+                                            // Disable
+#define EMAC_PC_RXERIDLE        0x00800000  // RXER Detection During Idle
+#define EMAC_PC_ISOMIILL        0x00400000  // Isolate MII in Link Loss
+#define EMAC_PC_LRR             0x00200000  // Link Loss Recovery
+#define EMAC_PC_TDRRUN          0x00100000  // TDR Auto Run
+#define EMAC_PC_FASTLDMODE_M    0x000F8000  // Fast Link Down Mode
+#define EMAC_PC_POLSWAP         0x00004000  // Polarity Swap
+#define EMAC_PC_MDISWAP         0x00002000  // MDI Swap
+#define EMAC_PC_RBSTMDIX        0x00001000  // Robust Auto MDI-X
+#define EMAC_PC_FASTMDIX        0x00000800  // Fast Auto MDI-X
+#define EMAC_PC_MDIXEN          0x00000400  // MDIX Enable
+#define EMAC_PC_FASTRXDV        0x00000200  // Fast RXDV Detection
+#define EMAC_PC_FASTLUPD        0x00000100  // FAST Link-Up in Parallel Detect
+#define EMAC_PC_EXTFD           0x00000080  // Extended Full Duplex Ability
+#define EMAC_PC_FASTANEN        0x00000040  // Fast Auto Negotiation Enable
+#define EMAC_PC_FASTANSEL_M     0x00000030  // Fast Auto Negotiation Select
+#define EMAC_PC_ANEN            0x00000008  // Auto Negotiation Enable
+#define EMAC_PC_ANMODE_M        0x00000006  // Auto Negotiation Mode
+#define EMAC_PC_ANMODE_10HD     0x00000000  // When ANEN = 0x0, the mode is
+                                            // 10Base-T, Half-Duplex
+#define EMAC_PC_ANMODE_10FD     0x00000002  // When ANEN = 0x0, the mode is
+                                            // 10Base-T, Full-Duplex
+#define EMAC_PC_ANMODE_100HD    0x00000004  // When ANEN = 0x0, the mode is
+                                            // 100Base-TX, Half-Duplex
+#define EMAC_PC_ANMODE_100FD    0x00000006  // When ANEN = 0x0, the mode is
+                                            // 100Base-TX, Full-Duplex
+#define EMAC_PC_PHYHOLD         0x00000001  // Ethernet PHY Hold
+#define EMAC_PC_FASTLDMODE_S    15
+#define EMAC_PC_FASTANSEL_S     4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_CC register.
+//
+//*****************************************************************************
+#define EMAC_CC_PTPCEN          0x00040000  // PTP Clock Reference Enable
+#define EMAC_CC_POL             0x00020000  // LED Polarity Control
+#define EMAC_CC_CLKEN           0x00010000  // EN0RREF_CLK Signal Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_EPHYRIS register.
+//
+//*****************************************************************************
+#define EMAC_EPHYRIS_INT        0x00000001  // Ethernet PHY Raw Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_EPHYIM register.
+//
+//*****************************************************************************
+#define EMAC_EPHYIM_INT         0x00000001  // Ethernet PHY Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_EPHYMISC
+// register.
+//
+//*****************************************************************************
+#define EMAC_EPHYMISC_INT       0x00000001  // Ethernet PHY Status and Clear
+                                            // register
+
+//*****************************************************************************
+//
+// The following are defines for the EPHY register offsets.
+//
+//*****************************************************************************
+#define EPHY_BMCR               0x00000000  // Ethernet PHY Basic Mode Control
+#define EPHY_BMSR               0x00000001  // Ethernet PHY Basic Mode Status
+#define EPHY_ID1                0x00000002  // Ethernet PHY Identifier Register
+                                            // 1
+#define EPHY_ID2                0x00000003  // Ethernet PHY Identifier Register
+                                            // 2
+#define EPHY_ANA                0x00000004  // Ethernet PHY Auto-Negotiation
+                                            // Advertisement
+#define EPHY_ANLPA              0x00000005  // Ethernet PHY Auto-Negotiation
+                                            // Link Partner Ability
+#define EPHY_ANER               0x00000006  // Ethernet PHY Auto-Negotiation
+                                            // Expansion
+#define EPHY_ANNPTR             0x00000007  // Ethernet PHY Auto-Negotiation
+                                            // Next Page TX
+#define EPHY_ANLNPTR            0x00000008  // Ethernet PHY Auto-Negotiation
+                                            // Link Partner Ability Next Page
+#define EPHY_CFG1               0x00000009  // Ethernet PHY Configuration 1
+#define EPHY_CFG2               0x0000000A  // Ethernet PHY Configuration 2
+#define EPHY_CFG3               0x0000000B  // Ethernet PHY Configuration 3
+#define EPHY_REGCTL             0x0000000D  // Ethernet PHY Register Control
+#define EPHY_ADDAR              0x0000000E  // Ethernet PHY Address or Data
+#define EPHY_STS                0x00000010  // Ethernet PHY Status
+#define EPHY_SCR                0x00000011  // Ethernet PHY Specific Control
+#define EPHY_MISR1              0x00000012  // Ethernet PHY MII Interrupt
+                                            // Status 1
+#define EPHY_MISR2              0x00000013  // Ethernet PHY MII Interrupt
+                                            // Status 2
+#define EPHY_FCSCR              0x00000014  // Ethernet PHY False Carrier Sense
+                                            // Counter
+#define EPHY_RXERCNT            0x00000015  // Ethernet PHY Receive Error Count
+#define EPHY_BISTCR             0x00000016  // Ethernet PHY BIST Control
+#define EPHY_LEDCR              0x00000018  // Ethernet PHY LED Control
+#define EPHY_CTL                0x00000019  // Ethernet PHY Control
+#define EPHY_10BTSC             0x0000001A  // Ethernet PHY 10Base-T
+                                            // Status/Control - MR26
+#define EPHY_BICSR1             0x0000001B  // Ethernet PHY BIST Control and
+                                            // Status 1
+#define EPHY_BICSR2             0x0000001C  // Ethernet PHY BIST Control and
+                                            // Status 2
+#define EPHY_CDCR               0x0000001E  // Ethernet PHY Cable Diagnostic
+                                            // Control
+#define EPHY_RCR                0x0000001F  // Ethernet PHY Reset Control
+#define EPHY_LEDCFG             0x00000025  // Ethernet PHY LED Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_BMCR register.
+//
+//*****************************************************************************
+#define EPHY_BMCR_MIIRESET      0x00008000  // MII Register reset
+#define EPHY_BMCR_MIILOOPBK     0x00004000  // MII Loopback
+#define EPHY_BMCR_SPEED         0x00002000  // Speed Select
+#define EPHY_BMCR_ANEN          0x00001000  // Auto-Negotiate Enable
+#define EPHY_BMCR_PWRDWN        0x00000800  // Power Down
+#define EPHY_BMCR_ISOLATE       0x00000400  // Port Isolate
+#define EPHY_BMCR_RESTARTAN     0x00000200  // Restart Auto-Negotiation
+#define EPHY_BMCR_DUPLEXM       0x00000100  // Duplex Mode
+#define EPHY_BMCR_COLLTST       0x00000080  // Collision Test
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_BMSR register.
+//
+//*****************************************************************************
+#define EPHY_BMSR_100BTXFD      0x00004000  // 100Base-TX Full Duplex Capable
+#define EPHY_BMSR_100BTXHD      0x00002000  // 100Base-TX Half Duplex Capable
+#define EPHY_BMSR_10BTFD        0x00001000  // 10 Base-T Full Duplex Capable
+#define EPHY_BMSR_10BTHD        0x00000800  // 10 Base-T Half Duplex Capable
+#define EPHY_BMSR_MFPRESUP      0x00000040  // Preamble Suppression Capable
+#define EPHY_BMSR_ANC           0x00000020  // Auto-Negotiation Complete
+#define EPHY_BMSR_RFAULT        0x00000010  // Remote Fault
+#define EPHY_BMSR_ANEN          0x00000008  // Auto Negotiation Enabled
+#define EPHY_BMSR_LINKSTAT      0x00000004  // Link Status
+#define EPHY_BMSR_JABBER        0x00000002  // Jabber Detect
+#define EPHY_BMSR_EXTEN         0x00000001  // Extended Capability Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_ID1 register.
+//
+//*****************************************************************************
+#define EPHY_ID1_OUIMSB_M       0x0000FFFF  // OUI Most Significant Bits
+#define EPHY_ID1_OUIMSB_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_ID2 register.
+//
+//*****************************************************************************
+#define EPHY_ID2_OUILSB_M       0x0000FC00  // OUI Least Significant Bits
+#define EPHY_ID2_VNDRMDL_M      0x000003F0  // Vendor Model Number
+#define EPHY_ID2_MDLREV_M       0x0000000F  // Model Revision Number
+#define EPHY_ID2_OUILSB_S       10
+#define EPHY_ID2_VNDRMDL_S      4
+#define EPHY_ID2_MDLREV_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_ANA register.
+//
+//*****************************************************************************
+#define EPHY_ANA_NP             0x00008000  // Next Page Indication
+#define EPHY_ANA_RF             0x00002000  // Remote Fault
+#define EPHY_ANA_ASMDUP         0x00000800  // Asymmetric PAUSE support for
+                                            // Full Duplex Links
+#define EPHY_ANA_PAUSE          0x00000400  // PAUSE Support for Full Duplex
+                                            // Links
+#define EPHY_ANA_100BT4         0x00000200  // 100Base-T4 Support
+#define EPHY_ANA_100BTXFD       0x00000100  // 100Base-TX Full Duplex Support
+#define EPHY_ANA_100BTX         0x00000080  // 100Base-TX Support
+#define EPHY_ANA_10BTFD         0x00000040  // 10Base-T Full Duplex Support
+#define EPHY_ANA_10BT           0x00000020  // 10Base-T Support
+#define EPHY_ANA_SELECT_M       0x0000001F  // Protocol Selection
+#define EPHY_ANA_SELECT_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_ANLPA register.
+//
+//*****************************************************************************
+#define EPHY_ANLPA_NP           0x00008000  // Next Page Indication
+#define EPHY_ANLPA_ACK          0x00004000  // Acknowledge
+#define EPHY_ANLPA_RF           0x00002000  // Remote Fault
+#define EPHY_ANLPA_ASMDUP       0x00000800  // Asymmetric PAUSE
+#define EPHY_ANLPA_PAUSE        0x00000400  // PAUSE
+#define EPHY_ANLPA_100BT4       0x00000200  // 100Base-T4 Support
+#define EPHY_ANLPA_100BTXFD     0x00000100  // 100Base-TX Full Duplex Support
+#define EPHY_ANLPA_100BTX       0x00000080  // 100Base-TX Support
+#define EPHY_ANLPA_10BTFD       0x00000040  // 10Base-T Full Duplex Support
+#define EPHY_ANLPA_10BT         0x00000020  // 10Base-T Support
+#define EPHY_ANLPA_SELECT_M     0x0000001F  // Protocol Selection
+#define EPHY_ANLPA_SELECT_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_ANER register.
+//
+//*****************************************************************************
+#define EPHY_ANER_PDF           0x00000010  // Parallel Detection Fault
+#define EPHY_ANER_LPNPABLE      0x00000008  // Link Partner Next Page Able
+#define EPHY_ANER_NPABLE        0x00000004  // Next Page Able
+#define EPHY_ANER_PAGERX        0x00000002  // Link Code Word Page Received
+#define EPHY_ANER_LPANABLE      0x00000001  // Link Partner Auto-Negotiation
+                                            // Able
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_ANNPTR register.
+//
+//*****************************************************************************
+#define EPHY_ANNPTR_NP          0x00008000  // Next Page Indication
+#define EPHY_ANNPTR_MP          0x00002000  // Message Page
+#define EPHY_ANNPTR_ACK2        0x00001000  // Acknowledge 2
+#define EPHY_ANNPTR_TOGTX       0x00000800  // Toggle
+#define EPHY_ANNPTR_CODE_M      0x000007FF  // Code
+#define EPHY_ANNPTR_CODE_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_ANLNPTR register.
+//
+//*****************************************************************************
+#define EPHY_ANLNPTR_NP         0x00008000  // Next Page Indication
+#define EPHY_ANLNPTR_ACK        0x00004000  // Acknowledge
+#define EPHY_ANLNPTR_MP         0x00002000  // Message Page
+#define EPHY_ANLNPTR_ACK2       0x00001000  // Acknowledge 2
+#define EPHY_ANLNPTR_TOG        0x00000800  // Toggle
+#define EPHY_ANLNPTR_CODE_M     0x000007FF  // Code
+#define EPHY_ANLNPTR_CODE_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_CFG1 register.
+//
+//*****************************************************************************
+#define EPHY_CFG1_DONE          0x00008000  // Configuration Done
+#define EPHY_CFG1_TDRAR         0x00000100  // TDR Auto-Run at Link Down
+#define EPHY_CFG1_LLR           0x00000080  // Link Loss Recovery
+#define EPHY_CFG1_FAMDIX        0x00000040  // Fast Auto MDI/MDIX
+#define EPHY_CFG1_RAMDIX        0x00000020  // Robust Auto MDI/MDIX
+#define EPHY_CFG1_FASTANEN      0x00000010  // Fast Auto Negotiation Enable
+#define EPHY_CFG1_FANSEL_M      0x0000000C  // Fast Auto-Negotiation Select
+                                            // Configuration
+#define EPHY_CFG1_FANSEL_BLT80  0x00000000  // Break Link Timer: 80 ms
+#define EPHY_CFG1_FANSEL_BLT120 0x00000004  // Break Link Timer: 120 ms
+#define EPHY_CFG1_FANSEL_BLT240 0x00000008  // Break Link Timer: 240 ms
+#define EPHY_CFG1_FRXDVDET      0x00000002  // FAST RXDV Detection
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_CFG2 register.
+//
+//*****************************************************************************
+#define EPHY_CFG2_FLUPPD        0x00000040  // Fast Link-Up in Parallel Detect
+                                            // Mode
+#define EPHY_CFG2_EXTFD         0x00000020  // Extended Full-Duplex Ability
+#define EPHY_CFG2_ENLEDLINK     0x00000010  // Enhanced LED Functionality
+#define EPHY_CFG2_ISOMIILL      0x00000008  // Isolate MII outputs when
+                                            // Enhanced Link is not Achievable
+#define EPHY_CFG2_RXERRIDLE     0x00000004  // Detection of Receive Symbol
+                                            // Error During IDLE State
+#define EPHY_CFG2_ODDNDETDIS    0x00000002  // Detection of Transmit Error
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_CFG3 register.
+//
+//*****************************************************************************
+#define EPHY_CFG3_POLSWAP       0x00000080  // Polarity Swap
+#define EPHY_CFG3_MDIMDIXS      0x00000040  // MDI/MDIX Swap
+#define EPHY_CFG3_FLDWNM_M      0x0000001F  // Fast Link Down Modes
+#define EPHY_CFG3_FLDWNM_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_REGCTL register.
+//
+//*****************************************************************************
+#define EPHY_REGCTL_FUNC_M      0x0000C000  // Function
+#define EPHY_REGCTL_FUNC_ADDR   0x00000000  // Address
+#define EPHY_REGCTL_FUNC_DATANI 0x00004000  // Data, no post increment
+#define EPHY_REGCTL_FUNC_DATAPIRW                                             \
+                                0x00008000  // Data, post increment on read and
+                                            // write
+#define EPHY_REGCTL_FUNC_DATAPIWO                                             \
+                                0x0000C000  // Data, post increment on write
+                                            // only
+#define EPHY_REGCTL_DEVAD_M     0x0000001F  // Device Address
+#define EPHY_REGCTL_DEVAD_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_ADDAR register.
+//
+//*****************************************************************************
+#define EPHY_ADDAR_ADDRDATA_M   0x0000FFFF  // Address or Data
+#define EPHY_ADDAR_ADDRDATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_STS register.
+//
+//*****************************************************************************
+#define EPHY_STS_MDIXM          0x00004000  // MDI-X Mode
+#define EPHY_STS_RXLERR         0x00002000  // Receive Error Latch
+#define EPHY_STS_POLSTAT        0x00001000  // Polarity Status
+#define EPHY_STS_FCSL           0x00000800  // False Carrier Sense Latch
+#define EPHY_STS_SD             0x00000400  // Signal Detect
+#define EPHY_STS_DL             0x00000200  // Descrambler Lock
+#define EPHY_STS_PAGERX         0x00000100  // Link Code Page Received
+#define EPHY_STS_MIIREQ         0x00000080  // MII Interrupt Pending
+#define EPHY_STS_RF             0x00000040  // Remote Fault
+#define EPHY_STS_JD             0x00000020  // Jabber Detect
+#define EPHY_STS_ANS            0x00000010  // Auto-Negotiation Status
+#define EPHY_STS_MIILB          0x00000008  // MII Loopback Status
+#define EPHY_STS_DUPLEX         0x00000004  // Duplex Status
+#define EPHY_STS_SPEED          0x00000002  // Speed Status
+#define EPHY_STS_LINK           0x00000001  // Link Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_SCR register.
+//
+//*****************************************************************************
+#define EPHY_SCR_DISCLK         0x00008000  // Disable CLK
+#define EPHY_SCR_PSEN           0x00004000  // Power Saving Modes Enable
+#define EPHY_SCR_PSMODE_M       0x00003000  // Power Saving Modes
+#define EPHY_SCR_PSMODE_NORMAL  0x00000000  // Normal: Normal operation mode.
+                                            // PHY is fully functional
+#define EPHY_SCR_PSMODE_LOWPWR  0x00001000  // IEEE Power Down
+#define EPHY_SCR_PSMODE_ACTWOL  0x00002000  // Active Sleep
+#define EPHY_SCR_PSMODE_PASWOL  0x00003000  // Passive Sleep
+#define EPHY_SCR_SBPYASS        0x00000800  // Scrambler Bypass
+#define EPHY_SCR_LBFIFO_M       0x00000300  // Loopback FIFO Depth
+#define EPHY_SCR_LBFIFO_4       0x00000000  // Four nibble FIFO
+#define EPHY_SCR_LBFIFO_5       0x00000100  // Five nibble FIFO
+#define EPHY_SCR_LBFIFO_6       0x00000200  // Six nibble FIFO
+#define EPHY_SCR_LBFIFO_8       0x00000300  // Eight nibble FIFO
+#define EPHY_SCR_COLFDM         0x00000010  // Collision in Full-Duplex Mode
+#define EPHY_SCR_TINT           0x00000004  // Test Interrupt
+#define EPHY_SCR_INTEN          0x00000002  // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_MISR1 register.
+//
+//*****************************************************************************
+#define EPHY_MISR1_LINKSTAT     0x00002000  // Change of Link Status Interrupt
+#define EPHY_MISR1_SPEED        0x00001000  // Change of Speed Status Interrupt
+#define EPHY_MISR1_DUPLEXM      0x00000800  // Change of Duplex Status
+                                            // Interrupt
+#define EPHY_MISR1_ANC          0x00000400  // Auto-Negotiation Complete
+                                            // Interrupt
+#define EPHY_MISR1_FCHF         0x00000200  // False Carrier Counter Half-Full
+                                            // Interrupt
+#define EPHY_MISR1_RXHF         0x00000100  // Receive Error Counter Half-Full
+                                            // Interrupt
+#define EPHY_MISR1_LINKSTATEN   0x00000020  // Link Status Interrupt Enable
+#define EPHY_MISR1_SPEEDEN      0x00000010  // Speed Change Interrupt Enable
+#define EPHY_MISR1_DUPLEXMEN    0x00000008  // Duplex Status Interrupt Enable
+#define EPHY_MISR1_ANCEN        0x00000004  // Auto-Negotiation Complete
+                                            // Interrupt Enable
+#define EPHY_MISR1_FCHFEN       0x00000002  // False Carrier Counter Register
+                                            // half-full Interrupt Enable
+#define EPHY_MISR1_RXHFEN       0x00000001  // Receive Error Counter Register
+                                            // Half-Full Event Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_MISR2 register.
+//
+//*****************************************************************************
+#define EPHY_MISR2_ANERR        0x00004000  // Auto-Negotiation Error Interrupt
+#define EPHY_MISR2_PAGERX       0x00002000  // Page Receive Interrupt
+#define EPHY_MISR2_LBFIFO       0x00001000  // Loopback FIFO Overflow/Underflow
+                                            // Event Interrupt
+#define EPHY_MISR2_MDICO        0x00000800  // MDI/MDIX Crossover Status
+                                            // Changed Interrupt
+#define EPHY_MISR2_SLEEP        0x00000400  // Sleep Mode Event Interrupt
+#define EPHY_MISR2_POLINT       0x00000200  // Polarity Changed Interrupt
+#define EPHY_MISR2_JABBER       0x00000100  // Jabber Detect Event Interrupt
+#define EPHY_MISR2_ANERREN      0x00000040  // Auto-Negotiation Error Interrupt
+                                            // Enable
+#define EPHY_MISR2_PAGERXEN     0x00000020  // Page Receive Interrupt Enable
+#define EPHY_MISR2_LBFIFOEN     0x00000010  // Loopback FIFO Overflow/Underflow
+                                            // Interrupt Enable
+#define EPHY_MISR2_MDICOEN      0x00000008  // MDI/MDIX Crossover Status
+                                            // Changed Interrupt Enable
+#define EPHY_MISR2_SLEEPEN      0x00000004  // Sleep Mode Event Interrupt
+                                            // Enable
+#define EPHY_MISR2_POLINTEN     0x00000002  // Polarity Changed Interrupt
+                                            // Enable
+#define EPHY_MISR2_JABBEREN     0x00000001  // Jabber Detect Event Interrupt
+                                            // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_FCSCR register.
+//
+//*****************************************************************************
+#define EPHY_FCSCR_FCSCNT_M     0x000000FF  // False Carrier Event Counter
+#define EPHY_FCSCR_FCSCNT_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_RXERCNT register.
+//
+//*****************************************************************************
+#define EPHY_RXERCNT_RXERRCNT_M 0x0000FFFF  // Receive Error Count
+#define EPHY_RXERCNT_RXERRCNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_BISTCR register.
+//
+//*****************************************************************************
+#define EPHY_BISTCR_PRBSM       0x00004000  // PRBS Single/Continuous Mode
+#define EPHY_BISTCR_PRBSPKT     0x00002000  // Generated PRBS Packets
+#define EPHY_BISTCR_PKTEN       0x00001000  // Packet Generation Enable
+#define EPHY_BISTCR_PRBSCHKLK   0x00000800  // PRBS Checker Lock Indication
+#define EPHY_BISTCR_PRBSCHKSYNC 0x00000400  // PRBS Checker Lock Sync Loss
+                                            // Indication
+#define EPHY_BISTCR_PKTGENSTAT  0x00000200  // Packet Generator Status
+                                            // Indication
+#define EPHY_BISTCR_PWRMODE     0x00000100  // Power Mode Indication
+#define EPHY_BISTCR_TXMIILB     0x00000040  // Transmit Data in MII Loopback
+                                            // Mode
+#define EPHY_BISTCR_LBMODE_M    0x0000001F  // Loopback Mode Select
+#define EPHY_BISTCR_LBMODE_NPCSIN                                             \
+                                0x00000001  // Near-end loopback: PCS Input
+                                            // Loopback
+#define EPHY_BISTCR_LBMODE_NPCSOUT                                            \
+                                0x00000002  // Near-end loopback: PCS Output
+                                            // Loopback (In 100Base-TX only)
+#define EPHY_BISTCR_LBMODE_NDIG 0x00000004  // Near-end loopback: Digital
+                                            // Loopback
+#define EPHY_BISTCR_LBMODE_NANA 0x00000008  // Near-end loopback: Analog
+                                            // Loopback (requires 100 Ohm
+                                            // termination)
+#define EPHY_BISTCR_LBMODE_FREV 0x00000010  // Far-end Loopback: Reverse
+                                            // Loopback
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_LEDCR register.
+//
+//*****************************************************************************
+#define EPHY_LEDCR_BLINKRATE_M  0x00000600  // LED Blinking Rate (ON/OFF
+                                            // duration):
+#define EPHY_LEDCR_BLINKRATE_20HZ                                             \
+                                0x00000000  // 20 Hz (50 ms)
+#define EPHY_LEDCR_BLINKRATE_10HZ                                             \
+                                0x00000200  // 10 Hz (100 ms)
+#define EPHY_LEDCR_BLINKRATE_5HZ                                              \
+                                0x00000400  // 5 Hz (200 ms)
+#define EPHY_LEDCR_BLINKRATE_2HZ                                              \
+                                0x00000600  // 2 Hz (500 ms)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_CTL register.
+//
+//*****************************************************************************
+#define EPHY_CTL_AUTOMDI        0x00008000  // Auto-MDIX Enable
+#define EPHY_CTL_FORCEMDI       0x00004000  // Force MDIX
+#define EPHY_CTL_PAUSERX        0x00002000  // Pause Receive Negotiated Status
+#define EPHY_CTL_PAUSETX        0x00001000  // Pause Transmit Negotiated Status
+#define EPHY_CTL_MIILNKSTAT     0x00000800  // MII Link Status
+#define EPHY_CTL_BYPLEDSTRCH    0x00000080  // Bypass LED Stretching
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_10BTSC register.
+//
+//*****************************************************************************
+#define EPHY_10BTSC_RXTHEN      0x00002000  // Lower Receiver Threshold Enable
+#define EPHY_10BTSC_SQUELCH_M   0x00001E00  // Squelch Configuration
+#define EPHY_10BTSC_NLPDIS      0x00000080  // Normal Link Pulse (NLP)
+                                            // Transmission Control
+#define EPHY_10BTSC_POLSTAT     0x00000010  // 10 Mb Polarity Status
+#define EPHY_10BTSC_JABBERD     0x00000001  // Jabber Disable
+#define EPHY_10BTSC_SQUELCH_S   9
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_BICSR1 register.
+//
+//*****************************************************************************
+#define EPHY_BICSR1_ERRCNT_M    0x0000FF00  // BIST Error Count
+#define EPHY_BICSR1_IPGLENGTH_M 0x000000FF  // BIST IPG Length
+#define EPHY_BICSR1_ERRCNT_S    8
+#define EPHY_BICSR1_IPGLENGTH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_BICSR2 register.
+//
+//*****************************************************************************
+#define EPHY_BICSR2_PKTLENGTH_M 0x000007FF  // BIST Packet Length
+#define EPHY_BICSR2_PKTLENGTH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_CDCR register.
+//
+//*****************************************************************************
+#define EPHY_CDCR_START         0x00008000  // Cable Diagnostic Process Start
+#define EPHY_CDCR_LINKQUAL_M    0x00000300  // Link Quality Indication
+#define EPHY_CDCR_LINKQUAL_GOOD 0x00000100  // Good Quality Link Indication
+#define EPHY_CDCR_LINKQUAL_MILD 0x00000200  // Mid- Quality Link Indication
+#define EPHY_CDCR_LINKQUAL_POOR 0x00000300  // Poor Quality Link Indication
+#define EPHY_CDCR_DONE          0x00000002  // Cable Diagnostic Process Done
+#define EPHY_CDCR_FAIL          0x00000001  // Cable Diagnostic Process Fail
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_RCR register.
+//
+//*****************************************************************************
+#define EPHY_RCR_SWRST          0x00008000  // Software Reset
+#define EPHY_RCR_SWRESTART      0x00004000  // Software Restart
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_LEDCFG register.
+//
+//*****************************************************************************
+#define EPHY_LEDCFG_LED2_M      0x00000F00  // LED2 Configuration
+#define EPHY_LEDCFG_LED2_LINK   0x00000000  // Link OK
+#define EPHY_LEDCFG_LED2_RXTX   0x00000100  // RX/TX Activity
+#define EPHY_LEDCFG_LED2_TX     0x00000200  // TX Activity
+#define EPHY_LEDCFG_LED2_RX     0x00000300  // RX Activity
+#define EPHY_LEDCFG_LED2_COL    0x00000400  // Collision
+#define EPHY_LEDCFG_LED2_100BT  0x00000500  // 100-Base TX
+#define EPHY_LEDCFG_LED2_10BT   0x00000600  // 10-Base TX
+#define EPHY_LEDCFG_LED2_FD     0x00000700  // Full Duplex
+#define EPHY_LEDCFG_LED2_LINKTXRX                                             \
+                                0x00000800  // Link OK/Blink on TX/RX Activity
+#define EPHY_LEDCFG_LED1_M      0x000000F0  // LED1 Configuration
+#define EPHY_LEDCFG_LED1_LINK   0x00000000  // Link OK
+#define EPHY_LEDCFG_LED1_RXTX   0x00000010  // RX/TX Activity
+#define EPHY_LEDCFG_LED1_TX     0x00000020  // TX Activity
+#define EPHY_LEDCFG_LED1_RX     0x00000030  // RX Activity
+#define EPHY_LEDCFG_LED1_COL    0x00000040  // Collision
+#define EPHY_LEDCFG_LED1_100BT  0x00000050  // 100-Base TX
+#define EPHY_LEDCFG_LED1_10BT   0x00000060  // 10-Base TX
+#define EPHY_LEDCFG_LED1_FD     0x00000070  // Full Duplex
+#define EPHY_LEDCFG_LED1_LINKTXRX                                             \
+                                0x00000080  // Link OK/Blink on TX/RX Activity
+#define EPHY_LEDCFG_LED0_M      0x0000000F  // LED0 Configuration
+#define EPHY_LEDCFG_LED0_LINK   0x00000000  // Link OK
+#define EPHY_LEDCFG_LED0_RXTX   0x00000001  // RX/TX Activity
+#define EPHY_LEDCFG_LED0_TX     0x00000002  // TX Activity
+#define EPHY_LEDCFG_LED0_RX     0x00000003  // RX Activity
+#define EPHY_LEDCFG_LED0_COL    0x00000004  // Collision
+#define EPHY_LEDCFG_LED0_100BT  0x00000005  // 100-Base TX
+#define EPHY_LEDCFG_LED0_10BT   0x00000006  // 10-Base TX
+#define EPHY_LEDCFG_LED0_FD     0x00000007  // Full Duplex
+#define EPHY_LEDCFG_LED0_LINKTXRX                                             \
+                                0x00000008  // Link OK/Blink on TX/RX Activity
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// EMAC_O_PPSCTRL register.
+//
+//*****************************************************************************
+#define EMAC_PPSCTRL_PPSCTRL_1HZ                                              \
+                                0x00000000  // When the PPSEN0 bit = 0x0, the
+                                            // EN0PPS signal is 1 pulse of the
+                                            // PTP reference clock.(of width
+                                            // clk_ptp_i) every second
+#define EMAC_PPSCTRL_PPSCTRL_2HZ                                              \
+                                0x00000001  // When the PPSEN0 bit = 0x0, the
+                                            // binary rollover is 2 Hz, and the
+                                            // digital rollover is 1 Hz
+#define EMAC_PPSCTRL_PPSCTRL_4HZ                                              \
+                                0x00000002  // When the PPSEN0 bit = 0x0, the
+                                            // binary rollover is 4 Hz, and the
+                                            // digital rollover is 2 Hz
+#define EMAC_PPSCTRL_PPSCTRL_8HZ                                              \
+                                0x00000003  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 8 Hz, and the
+                                            // digital rollover is 4 Hz,
+#define EMAC_PPSCTRL_PPSCTRL_16HZ                                             \
+                                0x00000004  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 16 Hz, and
+                                            // the digital rollover is 8 Hz
+#define EMAC_PPSCTRL_PPSCTRL_32HZ                                             \
+                                0x00000005  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 32 Hz, and
+                                            // the digital rollover is 16 Hz
+#define EMAC_PPSCTRL_PPSCTRL_64HZ                                             \
+                                0x00000006  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 64 Hz, and
+                                            // the digital rollover is 32 Hz
+#define EMAC_PPSCTRL_PPSCTRL_128HZ                                            \
+                                0x00000007  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 128 Hz, and
+                                            // the digital rollover is 64 Hz
+#define EMAC_PPSCTRL_PPSCTRL_256HZ                                            \
+                                0x00000008  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 256 Hz, and
+                                            // the digital rollover is 128 Hz
+#define EMAC_PPSCTRL_PPSCTRL_512HZ                                            \
+                                0x00000009  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 512 Hz, and
+                                            // the digital rollover is 256 Hz
+#define EMAC_PPSCTRL_PPSCTRL_1024HZ                                           \
+                                0x0000000A  // When the PPSEN0 bit = 0x0, the
+                                            // binary rollover is 1.024 kHz,
+                                            // and the digital rollover is 512
+                                            // Hz
+#define EMAC_PPSCTRL_PPSCTRL_2048HZ                                           \
+                                0x0000000B  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 2.048 kHz,
+                                            // and the digital rollover is
+                                            // 1.024 kHz
+#define EMAC_PPSCTRL_PPSCTRL_4096HZ                                           \
+                                0x0000000C  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 4.096 kHz,
+                                            // and the digital rollover is
+                                            // 2.048 kHz
+#define EMAC_PPSCTRL_PPSCTRL_8192HZ                                           \
+                                0x0000000D  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 8.192 kHz,
+                                            // and the digital rollover is
+                                            // 4.096 kHz
+#define EMAC_PPSCTRL_PPSCTRL_16384HZ                                          \
+                                0x0000000E  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 16.384 kHz,
+                                            // and the digital rollover is
+                                            // 8.092 kHz
+#define EMAC_PPSCTRL_PPSCTRL_32768HZ                                          \
+                                0x0000000F  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 32.768 KHz,
+                                            // and the digital rollover is
+                                            // 16.384 KHz
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the EMAC_O_CC
+// register.
+//
+//*****************************************************************************
+#define EMAC_CC_CS_PA7          0x00000001  // GPIO
+
+#endif
+
+#endif // __HW_EMAC_H__
diff --git a/os/common/ext/TivaWare/inc/hw_epi.h b/os/common/ext/TivaWare/inc/hw_epi.h
new file mode 100644
index 0000000..54b59c3
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_epi.h
@@ -0,0 +1,933 @@
+//*****************************************************************************
+//
+// hw_epi.h - Macros for use in accessing the EPI registers.
+//
+// Copyright (c) 2008-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_EPI_H__
+#define __HW_EPI_H__
+
+//*****************************************************************************
+//
+// The following are defines for the External Peripheral Interface register
+// offsets.
+//
+//*****************************************************************************
+#define EPI_O_CFG               0x00000000  // EPI Configuration
+#define EPI_O_BAUD              0x00000004  // EPI Main Baud Rate
+#define EPI_O_BAUD2             0x00000008  // EPI Main Baud Rate
+#define EPI_O_HB16CFG           0x00000010  // EPI Host-Bus 16 Configuration
+#define EPI_O_GPCFG             0x00000010  // EPI General-Purpose
+                                            // Configuration
+#define EPI_O_SDRAMCFG          0x00000010  // EPI SDRAM Configuration
+#define EPI_O_HB8CFG            0x00000010  // EPI Host-Bus 8 Configuration
+#define EPI_O_HB8CFG2           0x00000014  // EPI Host-Bus 8 Configuration 2
+#define EPI_O_HB16CFG2          0x00000014  // EPI Host-Bus 16 Configuration 2
+#define EPI_O_ADDRMAP           0x0000001C  // EPI Address Map
+#define EPI_O_RSIZE0            0x00000020  // EPI Read Size 0
+#define EPI_O_RADDR0            0x00000024  // EPI Read Address 0
+#define EPI_O_RPSTD0            0x00000028  // EPI Non-Blocking Read Data 0
+#define EPI_O_RSIZE1            0x00000030  // EPI Read Size 1
+#define EPI_O_RADDR1            0x00000034  // EPI Read Address 1
+#define EPI_O_RPSTD1            0x00000038  // EPI Non-Blocking Read Data 1
+#define EPI_O_STAT              0x00000060  // EPI Status
+#define EPI_O_RFIFOCNT          0x0000006C  // EPI Read FIFO Count
+#define EPI_O_READFIFO0         0x00000070  // EPI Read FIFO
+#define EPI_O_READFIFO1         0x00000074  // EPI Read FIFO Alias 1
+#define EPI_O_READFIFO2         0x00000078  // EPI Read FIFO Alias 2
+#define EPI_O_READFIFO3         0x0000007C  // EPI Read FIFO Alias 3
+#define EPI_O_READFIFO4         0x00000080  // EPI Read FIFO Alias 4
+#define EPI_O_READFIFO5         0x00000084  // EPI Read FIFO Alias 5
+#define EPI_O_READFIFO6         0x00000088  // EPI Read FIFO Alias 6
+#define EPI_O_READFIFO7         0x0000008C  // EPI Read FIFO Alias 7
+#define EPI_O_FIFOLVL           0x00000200  // EPI FIFO Level Selects
+#define EPI_O_WFIFOCNT          0x00000204  // EPI Write FIFO Count
+#define EPI_O_DMATXCNT          0x00000208  // EPI DMA Transmit Count
+#define EPI_O_IM                0x00000210  // EPI Interrupt Mask
+#define EPI_O_RIS               0x00000214  // EPI Raw Interrupt Status
+#define EPI_O_MIS               0x00000218  // EPI Masked Interrupt Status
+#define EPI_O_EISC              0x0000021C  // EPI Error and Interrupt Status
+                                            // and Clear
+#define EPI_O_HB8CFG3           0x00000308  // EPI Host-Bus 8 Configuration 3
+#define EPI_O_HB16CFG3          0x00000308  // EPI Host-Bus 16 Configuration 3
+#define EPI_O_HB16CFG4          0x0000030C  // EPI Host-Bus 16 Configuration 4
+#define EPI_O_HB8CFG4           0x0000030C  // EPI Host-Bus 8 Configuration 4
+#define EPI_O_HB8TIME           0x00000310  // EPI Host-Bus 8 Timing Extension
+#define EPI_O_HB16TIME          0x00000310  // EPI Host-Bus 16 Timing Extension
+#define EPI_O_HB8TIME2          0x00000314  // EPI Host-Bus 8 Timing Extension
+#define EPI_O_HB16TIME2         0x00000314  // EPI Host-Bus 16 Timing Extension
+#define EPI_O_HB16TIME3         0x00000318  // EPI Host-Bus 16 Timing Extension
+#define EPI_O_HB8TIME3          0x00000318  // EPI Host-Bus 8 Timing Extension
+#define EPI_O_HB8TIME4          0x0000031C  // EPI Host-Bus 8 Timing Extension
+#define EPI_O_HB16TIME4         0x0000031C  // EPI Host-Bus 16 Timing Extension
+#define EPI_O_HBPSRAM           0x00000360  // EPI Host-Bus PSRAM
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_CFG register.
+//
+//*****************************************************************************
+#define EPI_CFG_INTDIV          0x00000100  // Integer Clock Divider Enable
+#define EPI_CFG_BLKEN           0x00000010  // Block Enable
+#define EPI_CFG_MODE_M          0x0000000F  // Mode Select
+#define EPI_CFG_MODE_NONE       0x00000000  // General Purpose
+#define EPI_CFG_MODE_SDRAM      0x00000001  // SDRAM
+#define EPI_CFG_MODE_HB8        0x00000002  // 8-Bit Host-Bus (HB8)
+#define EPI_CFG_MODE_HB16       0x00000003  // 16-Bit Host-Bus (HB16)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_BAUD register.
+//
+//*****************************************************************************
+#define EPI_BAUD_COUNT1_M       0xFFFF0000  // Baud Rate Counter 1
+#define EPI_BAUD_COUNT0_M       0x0000FFFF  // Baud Rate Counter 0
+#define EPI_BAUD_COUNT1_S       16
+#define EPI_BAUD_COUNT0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_BAUD2 register.
+//
+//*****************************************************************************
+#define EPI_BAUD2_COUNT1_M      0xFFFF0000  // CS3n Baud Rate Counter 1
+#define EPI_BAUD2_COUNT0_M      0x0000FFFF  // CS2n Baud Rate Counter 0
+#define EPI_BAUD2_COUNT1_S      16
+#define EPI_BAUD2_COUNT0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16CFG register.
+//
+//*****************************************************************************
+#define EPI_HB16CFG_CLKGATE     0x80000000  // Clock Gated
+#define EPI_HB16CFG_CLKGATEI    0x40000000  // Clock Gated Idle
+#define EPI_HB16CFG_CLKINV      0x20000000  // Invert Output Clock Enable
+#define EPI_HB16CFG_RDYEN       0x10000000  // Input Ready Enable
+#define EPI_HB16CFG_IRDYINV     0x08000000  // Input Ready Invert
+#define EPI_HB16CFG_XFFEN       0x00800000  // External FIFO FULL Enable
+#define EPI_HB16CFG_XFEEN       0x00400000  // External FIFO EMPTY Enable
+#define EPI_HB16CFG_WRHIGH      0x00200000  // WRITE Strobe Polarity
+#define EPI_HB16CFG_RDHIGH      0x00100000  // READ Strobe Polarity
+#define EPI_HB16CFG_ALEHIGH     0x00080000  // ALE Strobe Polarity
+#define EPI_HB16CFG_WRCRE       0x00040000  // PSRAM Configuration Register
+                                            // Write
+#define EPI_HB16CFG_RDCRE       0x00020000  // PSRAM Configuration Register
+                                            // Read
+#define EPI_HB16CFG_BURST       0x00010000  // Burst Mode
+#define EPI_HB16CFG_MAXWAIT_M   0x0000FF00  // Maximum Wait
+#define EPI_HB16CFG_WRWS_M      0x000000C0  // Write Wait States
+#define EPI_HB16CFG_WRWS_2      0x00000000  // Active WRn is 2 EPI clocks
+#define EPI_HB16CFG_WRWS_4      0x00000040  // Active WRn is 4 EPI clocks
+#define EPI_HB16CFG_WRWS_6      0x00000080  // Active WRn is 6 EPI clocks
+#define EPI_HB16CFG_WRWS_8      0x000000C0  // Active WRn is 8 EPI clocks
+#define EPI_HB16CFG_RDWS_M      0x00000030  // Read Wait States
+#define EPI_HB16CFG_RDWS_2      0x00000000  // Active RDn is 2 EPI clocks
+#define EPI_HB16CFG_RDWS_4      0x00000010  // Active RDn is 4 EPI clocks
+#define EPI_HB16CFG_RDWS_6      0x00000020  // Active RDn is 6 EPI clocks
+#define EPI_HB16CFG_RDWS_8      0x00000030  // Active RDn is 8 EPI clocks
+#define EPI_HB16CFG_BSEL        0x00000004  // Byte Select Configuration
+#define EPI_HB16CFG_MODE_M      0x00000003  // Host Bus Sub-Mode
+#define EPI_HB16CFG_MODE_ADMUX  0x00000000  // ADMUX - AD[15:0]
+#define EPI_HB16CFG_MODE_ADNMUX 0x00000001  // ADNONMUX - D[15:0]
+#define EPI_HB16CFG_MODE_SRAM   0x00000002  // Continuous Read - D[15:0]
+#define EPI_HB16CFG_MODE_XFIFO  0x00000003  // XFIFO - D[15:0]
+#define EPI_HB16CFG_MAXWAIT_S   8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_GPCFG register.
+//
+//*****************************************************************************
+#define EPI_GPCFG_CLKPIN        0x80000000  // Clock Pin
+#define EPI_GPCFG_CLKGATE       0x40000000  // Clock Gated
+#define EPI_GPCFG_FRM50         0x04000000  // 50/50 Frame
+#define EPI_GPCFG_FRMCNT_M      0x03C00000  // Frame Count
+#define EPI_GPCFG_WR2CYC        0x00080000  // 2-Cycle Writes
+#define EPI_GPCFG_ASIZE_M       0x00000030  // Address Bus Size
+#define EPI_GPCFG_ASIZE_NONE    0x00000000  // No address
+#define EPI_GPCFG_ASIZE_4BIT    0x00000010  // Up to 4 bits wide
+#define EPI_GPCFG_ASIZE_12BIT   0x00000020  // Up to 12 bits wide. This size
+                                            // cannot be used with 24-bit data
+#define EPI_GPCFG_ASIZE_20BIT   0x00000030  // Up to 20 bits wide. This size
+                                            // cannot be used with data sizes
+                                            // other than 8
+#define EPI_GPCFG_DSIZE_M       0x00000003  // Size of Data Bus
+#define EPI_GPCFG_DSIZE_4BIT    0x00000000  // 8 Bits Wide (EPI0S0 to EPI0S7)
+#define EPI_GPCFG_DSIZE_16BIT   0x00000001  // 16 Bits Wide (EPI0S0 to EPI0S15)
+#define EPI_GPCFG_DSIZE_24BIT   0x00000002  // 24 Bits Wide (EPI0S0 to EPI0S23)
+#define EPI_GPCFG_DSIZE_32BIT   0x00000003  // 32 Bits Wide (EPI0S0 to EPI0S31)
+#define EPI_GPCFG_FRMCNT_S      22
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_SDRAMCFG register.
+//
+//*****************************************************************************
+#define EPI_SDRAMCFG_FREQ_M     0xC0000000  // EPI Frequency Range
+#define EPI_SDRAMCFG_FREQ_NONE  0x00000000  // 0 - 15 MHz
+#define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000  // 15 - 30 MHz
+#define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000  // 30 - 50 MHz
+#define EPI_SDRAMCFG_RFSH_M     0x07FF0000  // Refresh Counter
+#define EPI_SDRAMCFG_SLEEP      0x00000200  // Sleep Mode
+#define EPI_SDRAMCFG_SIZE_M     0x00000003  // Size of SDRAM
+#define EPI_SDRAMCFG_SIZE_8MB   0x00000000  // 64 megabits (8MB)
+#define EPI_SDRAMCFG_SIZE_16MB  0x00000001  // 128 megabits (16MB)
+#define EPI_SDRAMCFG_SIZE_32MB  0x00000002  // 256 megabits (32MB)
+#define EPI_SDRAMCFG_SIZE_64MB  0x00000003  // 512 megabits (64MB)
+#define EPI_SDRAMCFG_RFSH_S     16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8CFG register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG_CLKGATE      0x80000000  // Clock Gated
+#define EPI_HB8CFG_CLKGATEI     0x40000000  // Clock Gated when Idle
+#define EPI_HB8CFG_CLKINV       0x20000000  // Invert Output Clock Enable
+#define EPI_HB8CFG_RDYEN        0x10000000  // Input Ready Enable
+#define EPI_HB8CFG_IRDYINV      0x08000000  // Input Ready Invert
+#define EPI_HB8CFG_XFFEN        0x00800000  // External FIFO FULL Enable
+#define EPI_HB8CFG_XFEEN        0x00400000  // External FIFO EMPTY Enable
+#define EPI_HB8CFG_WRHIGH       0x00200000  // WRITE Strobe Polarity
+#define EPI_HB8CFG_RDHIGH       0x00100000  // READ Strobe Polarity
+#define EPI_HB8CFG_ALEHIGH      0x00080000  // ALE Strobe Polarity
+#define EPI_HB8CFG_MAXWAIT_M    0x0000FF00  // Maximum Wait
+#define EPI_HB8CFG_WRWS_M       0x000000C0  // Write Wait States
+#define EPI_HB8CFG_WRWS_2       0x00000000  // Active WRn is 2 EPI clocks
+#define EPI_HB8CFG_WRWS_4       0x00000040  // Active WRn is 4 EPI clocks
+#define EPI_HB8CFG_WRWS_6       0x00000080  // Active WRn is 6 EPI clocks
+#define EPI_HB8CFG_WRWS_8       0x000000C0  // Active WRn is 8 EPI clocks
+#define EPI_HB8CFG_RDWS_M       0x00000030  // Read Wait States
+#define EPI_HB8CFG_RDWS_2       0x00000000  // Active RDn is 2 EPI clocks
+#define EPI_HB8CFG_RDWS_4       0x00000010  // Active RDn is 4 EPI clocks
+#define EPI_HB8CFG_RDWS_6       0x00000020  // Active RDn is 6 EPI clocks
+#define EPI_HB8CFG_RDWS_8       0x00000030  // Active RDn is 8 EPI clocks
+#define EPI_HB8CFG_MODE_M       0x00000003  // Host Bus Sub-Mode
+#define EPI_HB8CFG_MODE_MUX     0x00000000  // ADMUX - AD[7:0]
+#define EPI_HB8CFG_MODE_NMUX    0x00000001  // ADNONMUX - D[7:0]
+#define EPI_HB8CFG_MODE_SRAM    0x00000002  // Continuous Read - D[7:0]
+#define EPI_HB8CFG_MODE_FIFO    0x00000003  // XFIFO - D[7:0]
+#define EPI_HB8CFG_MAXWAIT_S    8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8CFG2 register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG2_CSCFGEXT    0x08000000  // Chip Select Extended
+                                            // Configuration
+#define EPI_HB8CFG2_CSBAUD      0x04000000  // Chip Select Baud Rate and
+                                            // Multiple Sub-Mode Configuration
+                                            // enable
+#define EPI_HB8CFG2_CSCFG_M     0x03000000  // Chip Select Configuration
+#define EPI_HB8CFG2_CSCFG_ALE   0x00000000  // ALE Configuration
+#define EPI_HB8CFG2_CSCFG_CS    0x01000000  // CSn Configuration
+#define EPI_HB8CFG2_CSCFG_DCS   0x02000000  // Dual CSn Configuration
+#define EPI_HB8CFG2_CSCFG_ADCS  0x03000000  // ALE with Dual CSn Configuration
+#define EPI_HB8CFG2_WRHIGH      0x00200000  // CS1n WRITE Strobe Polarity
+#define EPI_HB8CFG2_RDHIGH      0x00100000  // CS1n READ Strobe Polarity
+#define EPI_HB8CFG2_ALEHIGH     0x00080000  // CS1n ALE Strobe Polarity
+#define EPI_HB8CFG2_WRWS_M      0x000000C0  // CS1n Write Wait States
+#define EPI_HB8CFG2_WRWS_2      0x00000000  // Active WRn is 2 EPI clocks
+#define EPI_HB8CFG2_WRWS_4      0x00000040  // Active WRn is 4 EPI clocks
+#define EPI_HB8CFG2_WRWS_6      0x00000080  // Active WRn is 6 EPI clocks
+#define EPI_HB8CFG2_WRWS_8      0x000000C0  // Active WRn is 8 EPI clocks
+#define EPI_HB8CFG2_RDWS_M      0x00000030  // CS1n Read Wait States
+#define EPI_HB8CFG2_RDWS_2      0x00000000  // Active RDn is 2 EPI clocks
+#define EPI_HB8CFG2_RDWS_4      0x00000010  // Active RDn is 4 EPI clocks
+#define EPI_HB8CFG2_RDWS_6      0x00000020  // Active RDn is 6 EPI clocks
+#define EPI_HB8CFG2_RDWS_8      0x00000030  // Active RDn is 8 EPI clocks
+#define EPI_HB8CFG2_MODE_M      0x00000003  // CS1n Host Bus Sub-Mode
+#define EPI_HB8CFG2_MODE_ADMUX  0x00000000  // ADMUX - AD[7:0]
+#define EPI_HB8CFG2_MODE_AD     0x00000001  // ADNONMUX - D[7:0]
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16CFG2 register.
+//
+//*****************************************************************************
+#define EPI_HB16CFG2_CSCFGEXT   0x08000000  // Chip Select Extended
+                                            // Configuration
+#define EPI_HB16CFG2_CSBAUD     0x04000000  // Chip Select Baud Rate and
+                                            // Multiple Sub-Mode Configuration
+                                            // enable
+#define EPI_HB16CFG2_CSCFG_M    0x03000000  // Chip Select Configuration
+#define EPI_HB16CFG2_CSCFG_ALE  0x00000000  // ALE Configuration
+#define EPI_HB16CFG2_CSCFG_CS   0x01000000  // CSn Configuration
+#define EPI_HB16CFG2_CSCFG_DCS  0x02000000  // Dual CSn Configuration
+#define EPI_HB16CFG2_CSCFG_ADCS 0x03000000  // ALE with Dual CSn Configuration
+#define EPI_HB16CFG2_WRHIGH     0x00200000  // CS1n WRITE Strobe Polarity
+#define EPI_HB16CFG2_RDHIGH     0x00100000  // CS1n READ Strobe Polarity
+#define EPI_HB16CFG2_ALEHIGH    0x00080000  // CS1n ALE Strobe Polarity
+#define EPI_HB16CFG2_WRCRE      0x00040000  // CS1n PSRAM Configuration
+                                            // Register Write
+#define EPI_HB16CFG2_RDCRE      0x00020000  // CS1n PSRAM Configuration
+                                            // Register Read
+#define EPI_HB16CFG2_BURST      0x00010000  // CS1n Burst Mode
+#define EPI_HB16CFG2_WRWS_M     0x000000C0  // CS1n Write Wait States
+#define EPI_HB16CFG2_WRWS_2     0x00000000  // Active WRn is 2 EPI clocks
+#define EPI_HB16CFG2_WRWS_4     0x00000040  // Active WRn is 4 EPI clocks
+#define EPI_HB16CFG2_WRWS_6     0x00000080  // Active WRn is 6 EPI clocks
+#define EPI_HB16CFG2_WRWS_8     0x000000C0  // Active WRn is 8 EPI clocks
+#define EPI_HB16CFG2_RDWS_M     0x00000030  // CS1n Read Wait States
+#define EPI_HB16CFG2_RDWS_2     0x00000000  // Active RDn is 2 EPI clocks
+#define EPI_HB16CFG2_RDWS_4     0x00000010  // Active RDn is 4 EPI clocks
+#define EPI_HB16CFG2_RDWS_6     0x00000020  // Active RDn is 6 EPI clocks
+#define EPI_HB16CFG2_RDWS_8     0x00000030  // Active RDn is 8 EPI clocks
+#define EPI_HB16CFG2_MODE_M     0x00000003  // CS1n Host Bus Sub-Mode
+#define EPI_HB16CFG2_MODE_ADMUX 0x00000000  // ADMUX - AD[15:0]
+#define EPI_HB16CFG2_MODE_AD    0x00000001  // ADNONMUX - D[15:0]
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_ADDRMAP register.
+//
+//*****************************************************************************
+#define EPI_ADDRMAP_ECSZ_M      0x00000C00  // External Code Size
+#define EPI_ADDRMAP_ECSZ_256B   0x00000000  // 256 bytes; lower address range:
+                                            // 0x00 to 0xFF
+#define EPI_ADDRMAP_ECSZ_64KB   0x00000400  // 64 KB; lower address range:
+                                            // 0x0000 to 0xFFFF
+#define EPI_ADDRMAP_ECSZ_16MB   0x00000800  // 16 MB; lower address range:
+                                            // 0x00.0000 to 0xFF.FFFF
+#define EPI_ADDRMAP_ECSZ_256MB  0x00000C00  // 256MB; lower address range:
+                                            // 0x000.0000 to 0x0FFF.FFFF
+#define EPI_ADDRMAP_ECADR_M     0x00000300  // External Code Address
+#define EPI_ADDRMAP_ECADR_NONE  0x00000000  // Not mapped
+#define EPI_ADDRMAP_ECADR_1000  0x00000100  // At 0x1000.0000
+#define EPI_ADDRMAP_EPSZ_M      0x000000C0  // External Peripheral Size
+#define EPI_ADDRMAP_EPSZ_256B   0x00000000  // 256 bytes; lower address range:
+                                            // 0x00 to 0xFF
+#define EPI_ADDRMAP_EPSZ_64KB   0x00000040  // 64 KB; lower address range:
+                                            // 0x0000 to 0xFFFF
+#define EPI_ADDRMAP_EPSZ_16MB   0x00000080  // 16 MB; lower address range:
+                                            // 0x00.0000 to 0xFF.FFFF
+#define EPI_ADDRMAP_EPSZ_256MB  0x000000C0  // 256 MB; lower address range:
+                                            // 0x000.0000 to 0xFFF.FFFF
+#define EPI_ADDRMAP_EPADR_M     0x00000030  // External Peripheral Address
+#define EPI_ADDRMAP_EPADR_NONE  0x00000000  // Not mapped
+#define EPI_ADDRMAP_EPADR_A000  0x00000010  // At 0xA000.0000
+#define EPI_ADDRMAP_EPADR_C000  0x00000020  // At 0xC000.0000
+#define EPI_ADDRMAP_EPADR_HBQS  0x00000030  // Only to be used with Host Bus
+                                            // quad chip select. In quad chip
+                                            // select mode, CS2n maps to
+                                            // 0xA000.0000 and CS3n maps to
+                                            // 0xC000.0000
+#define EPI_ADDRMAP_ERSZ_M      0x0000000C  // External RAM Size
+#define EPI_ADDRMAP_ERSZ_256B   0x00000000  // 256 bytes; lower address range:
+                                            // 0x00 to 0xFF
+#define EPI_ADDRMAP_ERSZ_64KB   0x00000004  // 64 KB; lower address range:
+                                            // 0x0000 to 0xFFFF
+#define EPI_ADDRMAP_ERSZ_16MB   0x00000008  // 16 MB; lower address range:
+                                            // 0x00.0000 to 0xFF.FFFF
+#define EPI_ADDRMAP_ERSZ_256MB  0x0000000C  // 256 MB; lower address range:
+                                            // 0x000.0000 to 0xFFF.FFFF
+#define EPI_ADDRMAP_ERADR_M     0x00000003  // External RAM Address
+#define EPI_ADDRMAP_ERADR_NONE  0x00000000  // Not mapped
+#define EPI_ADDRMAP_ERADR_6000  0x00000001  // At 0x6000.0000
+#define EPI_ADDRMAP_ERADR_8000  0x00000002  // At 0x8000.0000
+#define EPI_ADDRMAP_ERADR_HBQS  0x00000003  // Only to be used with Host Bus
+                                            // quad chip select. In quad chip
+                                            // select mode, CS0n maps to
+                                            // 0x6000.0000 and CS1n maps to
+                                            // 0x8000.0000
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RSIZE0 register.
+//
+//*****************************************************************************
+#define EPI_RSIZE0_SIZE_M       0x00000003  // Current Size
+#define EPI_RSIZE0_SIZE_8BIT    0x00000001  // Byte (8 bits)
+#define EPI_RSIZE0_SIZE_16BIT   0x00000002  // Half-word (16 bits)
+#define EPI_RSIZE0_SIZE_32BIT   0x00000003  // Word (32 bits)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RADDR0 register.
+//
+//*****************************************************************************
+#define EPI_RADDR0_ADDR_M       0xFFFFFFFF  // Current Address
+#define EPI_RADDR0_ADDR_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RPSTD0 register.
+//
+//*****************************************************************************
+#define EPI_RPSTD0_POSTCNT_M    0x00001FFF  // Post Count
+#define EPI_RPSTD0_POSTCNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RSIZE1 register.
+//
+//*****************************************************************************
+#define EPI_RSIZE1_SIZE_M       0x00000003  // Current Size
+#define EPI_RSIZE1_SIZE_8BIT    0x00000001  // Byte (8 bits)
+#define EPI_RSIZE1_SIZE_16BIT   0x00000002  // Half-word (16 bits)
+#define EPI_RSIZE1_SIZE_32BIT   0x00000003  // Word (32 bits)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RADDR1 register.
+//
+//*****************************************************************************
+#define EPI_RADDR1_ADDR_M       0xFFFFFFFF  // Current Address
+#define EPI_RADDR1_ADDR_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RPSTD1 register.
+//
+//*****************************************************************************
+#define EPI_RPSTD1_POSTCNT_M    0x00001FFF  // Post Count
+#define EPI_RPSTD1_POSTCNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_STAT register.
+//
+//*****************************************************************************
+#define EPI_STAT_XFFULL         0x00000100  // External FIFO Full
+#define EPI_STAT_XFEMPTY        0x00000080  // External FIFO Empty
+#define EPI_STAT_INITSEQ        0x00000040  // Initialization Sequence
+#define EPI_STAT_WBUSY          0x00000020  // Write Busy
+#define EPI_STAT_NBRBUSY        0x00000010  // Non-Blocking Read Busy
+#define EPI_STAT_ACTIVE         0x00000001  // Register Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RFIFOCNT register.
+//
+//*****************************************************************************
+#define EPI_RFIFOCNT_COUNT_M    0x0000000F  // FIFO Count
+#define EPI_RFIFOCNT_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO0
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO0_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO0_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO1
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO1_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO1_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO2
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO2_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO2_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO3
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO3_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO3_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO4
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO4_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO4_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO5
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO5_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO5_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO6
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO6_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO6_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO7
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO7_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO7_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_FIFOLVL register.
+//
+//*****************************************************************************
+#define EPI_FIFOLVL_WFERR       0x00020000  // Write Full Error
+#define EPI_FIFOLVL_RSERR       0x00010000  // Read Stall Error
+#define EPI_FIFOLVL_WRFIFO_M    0x00000070  // Write FIFO
+#define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000  // Interrupt is triggered while
+                                            // WRFIFO is empty.
+#define EPI_FIFOLVL_WRFIFO_2    0x00000020  // Interrupt is triggered until
+                                            // there are only two slots
+                                            // available. Thus, trigger is
+                                            // deasserted when there are two
+                                            // WRFIFO entries present. This
+                                            // configuration is optimized for
+                                            // bursts of 2
+#define EPI_FIFOLVL_WRFIFO_1    0x00000030  // Interrupt is triggered until
+                                            // there is one WRFIFO entry
+                                            // available. This configuration
+                                            // expects only single writes
+#define EPI_FIFOLVL_WRFIFO_NFULL                                              \
+                                0x00000040  // Trigger interrupt when WRFIFO is
+                                            // not full, meaning trigger will
+                                            // continue to assert until there
+                                            // are four entries in the WRFIFO
+#define EPI_FIFOLVL_RDFIFO_M    0x00000007  // Read FIFO
+#define EPI_FIFOLVL_RDFIFO_EMPT 0x00000000  // Empty
+#define EPI_FIFOLVL_RDFIFO_1    0x00000001  // Trigger when there are 1 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_2    0x00000002  // Trigger when there are 2 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_4    0x00000003  // Trigger when there are 4 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_6    0x00000004  // Trigger when there are 6 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_7    0x00000005  // Trigger when there are 7 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_8    0x00000006  // Trigger when there are 8 entries
+                                            // in the NBRFIFO
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_WFIFOCNT register.
+//
+//*****************************************************************************
+#define EPI_WFIFOCNT_WTAV_M     0x00000007  // Available Write Transactions
+#define EPI_WFIFOCNT_WTAV_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_DMATXCNT register.
+//
+//*****************************************************************************
+#define EPI_DMATXCNT_TXCNT_M    0x0000FFFF  // DMA Count
+#define EPI_DMATXCNT_TXCNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_IM register.
+//
+//*****************************************************************************
+#define EPI_IM_DMAWRIM          0x00000010  // Write uDMA Interrupt Mask
+#define EPI_IM_DMARDIM          0x00000008  // Read uDMA Interrupt Mask
+#define EPI_IM_WRIM             0x00000004  // Write FIFO Empty Interrupt Mask
+#define EPI_IM_RDIM             0x00000002  // Read FIFO Full Interrupt Mask
+#define EPI_IM_ERRIM            0x00000001  // Error Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RIS register.
+//
+//*****************************************************************************
+#define EPI_RIS_DMAWRRIS        0x00000010  // Write uDMA Raw Interrupt Status
+#define EPI_RIS_DMARDRIS        0x00000008  // Read uDMA Raw Interrupt Status
+#define EPI_RIS_WRRIS           0x00000004  // Write Raw Interrupt Status
+#define EPI_RIS_RDRIS           0x00000002  // Read Raw Interrupt Status
+#define EPI_RIS_ERRRIS          0x00000001  // Error Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_MIS register.
+//
+//*****************************************************************************
+#define EPI_MIS_DMAWRMIS        0x00000010  // Write uDMA Masked Interrupt
+                                            // Status
+#define EPI_MIS_DMARDMIS        0x00000008  // Read uDMA Masked Interrupt
+                                            // Status
+#define EPI_MIS_WRMIS           0x00000004  // Write Masked Interrupt Status
+#define EPI_MIS_RDMIS           0x00000002  // Read Masked Interrupt Status
+#define EPI_MIS_ERRMIS          0x00000001  // Error Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_EISC register.
+//
+//*****************************************************************************
+#define EPI_EISC_DMAWRIC        0x00000010  // Write uDMA Interrupt Clear
+#define EPI_EISC_DMARDIC        0x00000008  // Read uDMA Interrupt Clear
+#define EPI_EISC_WTFULL         0x00000004  // Write FIFO Full Error
+#define EPI_EISC_RSTALL         0x00000002  // Read Stalled Error
+#define EPI_EISC_TOUT           0x00000001  // Timeout Error
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8CFG3 register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG3_WRHIGH      0x00200000  // CS2n WRITE Strobe Polarity
+#define EPI_HB8CFG3_RDHIGH      0x00100000  // CS2n READ Strobe Polarity
+#define EPI_HB8CFG3_ALEHIGH     0x00080000  // CS2n ALE Strobe Polarity
+#define EPI_HB8CFG3_WRWS_M      0x000000C0  // CS2n Write Wait States
+#define EPI_HB8CFG3_WRWS_2      0x00000000  // Active WRn is 2 EPI clocks
+#define EPI_HB8CFG3_WRWS_4      0x00000040  // Active WRn is 4 EPI clocks
+#define EPI_HB8CFG3_WRWS_6      0x00000080  // Active WRn is 6 EPI clocks
+#define EPI_HB8CFG3_WRWS_8      0x000000C0  // Active WRn is 8 EPI clocks
+#define EPI_HB8CFG3_RDWS_M      0x00000030  // CS2n Read Wait States
+#define EPI_HB8CFG3_RDWS_2      0x00000000  // Active RDn is 2 EPI clocks
+#define EPI_HB8CFG3_RDWS_4      0x00000010  // Active RDn is 4 EPI clocks
+#define EPI_HB8CFG3_RDWS_6      0x00000020  // Active RDn is 6 EPI clocks
+#define EPI_HB8CFG3_RDWS_8      0x00000030  // Active RDn is 8 EPI clocks
+#define EPI_HB8CFG3_MODE_M      0x00000003  // CS2n Host Bus Sub-Mode
+#define EPI_HB8CFG3_MODE_ADMUX  0x00000000  // ADMUX - AD[7:0]
+#define EPI_HB8CFG3_MODE_AD     0x00000001  // ADNONMUX - D[7:0]
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16CFG3 register.
+//
+//*****************************************************************************
+#define EPI_HB16CFG3_WRHIGH     0x00200000  // CS2n WRITE Strobe Polarity
+#define EPI_HB16CFG3_RDHIGH     0x00100000  // CS2n READ Strobe Polarity
+#define EPI_HB16CFG3_ALEHIGH    0x00080000  // CS2n ALE Strobe Polarity
+#define EPI_HB16CFG3_WRCRE      0x00040000  // CS2n PSRAM Configuration
+                                            // Register Write
+#define EPI_HB16CFG3_RDCRE      0x00020000  // CS2n PSRAM Configuration
+                                            // Register Read
+#define EPI_HB16CFG3_BURST      0x00010000  // CS2n Burst Mode
+#define EPI_HB16CFG3_WRWS_M     0x000000C0  // CS2n Write Wait States
+#define EPI_HB16CFG3_WRWS_2     0x00000000  // Active WRn is 2 EPI clocks
+#define EPI_HB16CFG3_WRWS_4     0x00000040  // Active WRn is 4 EPI clocks
+#define EPI_HB16CFG3_WRWS_6     0x00000080  // Active WRn is 6 EPI clocks
+#define EPI_HB16CFG3_WRWS_8     0x000000C0  // Active WRn is 8 EPI clocks
+#define EPI_HB16CFG3_RDWS_M     0x00000030  // CS2n Read Wait States
+#define EPI_HB16CFG3_RDWS_2     0x00000000  // Active RDn is 2 EPI clocks
+#define EPI_HB16CFG3_RDWS_4     0x00000010  // Active RDn is 4 EPI clocks
+#define EPI_HB16CFG3_RDWS_6     0x00000020  // Active RDn is 6 EPI clocks
+#define EPI_HB16CFG3_RDWS_8     0x00000030  // Active RDn is 8 EPI clocks
+#define EPI_HB16CFG3_MODE_M     0x00000003  // CS2n Host Bus Sub-Mode
+#define EPI_HB16CFG3_MODE_ADMUX 0x00000000  // ADMUX - AD[15:0]
+#define EPI_HB16CFG3_MODE_AD    0x00000001  // ADNONMUX - D[15:0]
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16CFG4 register.
+//
+//*****************************************************************************
+#define EPI_HB16CFG4_WRHIGH     0x00200000  // CS3n WRITE Strobe Polarity
+#define EPI_HB16CFG4_RDHIGH     0x00100000  // CS3n READ Strobe Polarity
+#define EPI_HB16CFG4_ALEHIGH    0x00080000  // CS3n ALE Strobe Polarity
+#define EPI_HB16CFG4_WRCRE      0x00040000  // CS3n PSRAM Configuration
+                                            // Register Write
+#define EPI_HB16CFG4_RDCRE      0x00020000  // CS3n PSRAM Configuration
+                                            // Register Read
+#define EPI_HB16CFG4_BURST      0x00010000  // CS3n Burst Mode
+#define EPI_HB16CFG4_WRWS_M     0x000000C0  // CS3n Write Wait States
+#define EPI_HB16CFG4_WRWS_2     0x00000000  // Active WRn is 2 EPI clocks
+#define EPI_HB16CFG4_WRWS_4     0x00000040  // Active WRn is 4 EPI clocks
+#define EPI_HB16CFG4_WRWS_6     0x00000080  // Active WRn is 6 EPI clocks
+#define EPI_HB16CFG4_WRWS_8     0x000000C0  // Active WRn is 8 EPI clocks
+#define EPI_HB16CFG4_RDWS_M     0x00000030  // CS3n Read Wait States
+#define EPI_HB16CFG4_RDWS_2     0x00000000  // Active RDn is 2 EPI clocks
+#define EPI_HB16CFG4_RDWS_4     0x00000010  // Active RDn is 4 EPI clocks
+#define EPI_HB16CFG4_RDWS_6     0x00000020  // Active RDn is 6 EPI clocks
+#define EPI_HB16CFG4_RDWS_8     0x00000030  // Active RDn is 8 EPI clocks
+#define EPI_HB16CFG4_MODE_M     0x00000003  // CS3n Host Bus Sub-Mode
+#define EPI_HB16CFG4_MODE_ADMUX 0x00000000  // ADMUX - AD[15:0]
+#define EPI_HB16CFG4_MODE_AD    0x00000001  // ADNONMUX - D[15:0]
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8CFG4 register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG4_WRHIGH      0x00200000  // CS3n WRITE Strobe Polarity
+#define EPI_HB8CFG4_RDHIGH      0x00100000  // CS2n READ Strobe Polarity
+#define EPI_HB8CFG4_ALEHIGH     0x00080000  // CS3n ALE Strobe Polarity
+#define EPI_HB8CFG4_WRWS_M      0x000000C0  // CS3n Write Wait States
+#define EPI_HB8CFG4_WRWS_2      0x00000000  // Active WRn is 2 EPI clocks
+#define EPI_HB8CFG4_WRWS_4      0x00000040  // Active WRn is 4 EPI clocks
+#define EPI_HB8CFG4_WRWS_6      0x00000080  // Active WRn is 6 EPI clocks
+#define EPI_HB8CFG4_WRWS_8      0x000000C0  // Active WRn is 8 EPI clocks
+#define EPI_HB8CFG4_RDWS_M      0x00000030  // CS3n Read Wait States
+#define EPI_HB8CFG4_RDWS_2      0x00000000  // Active RDn is 2 EPI clocks
+#define EPI_HB8CFG4_RDWS_4      0x00000010  // Active RDn is 4 EPI clocks
+#define EPI_HB8CFG4_RDWS_6      0x00000020  // Active RDn is 6 EPI clocks
+#define EPI_HB8CFG4_RDWS_8      0x00000030  // Active RDn is 8 EPI clocks
+#define EPI_HB8CFG4_MODE_M      0x00000003  // CS3n Host Bus Sub-Mode
+#define EPI_HB8CFG4_MODE_ADMUX  0x00000000  // ADMUX - AD[7:0]
+#define EPI_HB8CFG4_MODE_AD     0x00000001  // ADNONMUX - D[7:0]
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8TIME register.
+//
+//*****************************************************************************
+#define EPI_HB8TIME_IRDYDLY_M   0x03000000  // CS0n Input Ready Delay
+#define EPI_HB8TIME_CAPWIDTH_M  0x00003000  // CS0n Inter-transfer Capture
+                                            // Width
+#define EPI_HB8TIME_WRWSM       0x00000010  // Write Wait State Minus One
+#define EPI_HB8TIME_RDWSM       0x00000001  // Read Wait State Minus One
+#define EPI_HB8TIME_IRDYDLY_S   24
+#define EPI_HB8TIME_CAPWIDTH_S  12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16TIME register.
+//
+//*****************************************************************************
+#define EPI_HB16TIME_IRDYDLY_M  0x03000000  // CS0n Input Ready Delay
+#define EPI_HB16TIME_PSRAMSZ_M  0x00070000  // PSRAM Row Size
+#define EPI_HB16TIME_PSRAMSZ_0  0x00000000  // No row size limitation
+#define EPI_HB16TIME_PSRAMSZ_128B                                             \
+                                0x00010000  // 128 B
+#define EPI_HB16TIME_PSRAMSZ_256B                                             \
+                                0x00020000  // 256 B
+#define EPI_HB16TIME_PSRAMSZ_512B                                             \
+                                0x00030000  // 512 B
+#define EPI_HB16TIME_PSRAMSZ_1KB                                              \
+                                0x00040000  // 1024 B
+#define EPI_HB16TIME_PSRAMSZ_2KB                                              \
+                                0x00050000  // 2048 B
+#define EPI_HB16TIME_PSRAMSZ_4KB                                              \
+                                0x00060000  // 4096 B
+#define EPI_HB16TIME_PSRAMSZ_8KB                                              \
+                                0x00070000  // 8192 B
+#define EPI_HB16TIME_CAPWIDTH_M 0x00003000  // CS0n Inter-transfer Capture
+                                            // Width
+#define EPI_HB16TIME_WRWSM      0x00000010  // Write Wait State Minus One
+#define EPI_HB16TIME_RDWSM      0x00000001  // Read Wait State Minus One
+#define EPI_HB16TIME_IRDYDLY_S  24
+#define EPI_HB16TIME_CAPWIDTH_S 12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8TIME2 register.
+//
+//*****************************************************************************
+#define EPI_HB8TIME2_IRDYDLY_M  0x03000000  // CS1n Input Ready Delay
+#define EPI_HB8TIME2_CAPWIDTH_M 0x00003000  // CS1n Inter-transfer Capture
+                                            // Width
+#define EPI_HB8TIME2_WRWSM      0x00000010  // CS1n Write Wait State Minus One
+#define EPI_HB8TIME2_RDWSM      0x00000001  // CS1n Read Wait State Minus One
+#define EPI_HB8TIME2_IRDYDLY_S  24
+#define EPI_HB8TIME2_CAPWIDTH_S 12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16TIME2
+// register.
+//
+//*****************************************************************************
+#define EPI_HB16TIME2_IRDYDLY_M 0x03000000  // CS1n Input Ready Delay
+#define EPI_HB16TIME2_PSRAMSZ_M 0x00070000  // PSRAM Row Size
+#define EPI_HB16TIME2_PSRAMSZ_0 0x00000000  // No row size limitation
+#define EPI_HB16TIME2_PSRAMSZ_128B                                            \
+                                0x00010000  // 128 B
+#define EPI_HB16TIME2_PSRAMSZ_256B                                            \
+                                0x00020000  // 256 B
+#define EPI_HB16TIME2_PSRAMSZ_512B                                            \
+                                0x00030000  // 512 B
+#define EPI_HB16TIME2_PSRAMSZ_1KB                                             \
+                                0x00040000  // 1024 B
+#define EPI_HB16TIME2_PSRAMSZ_2KB                                             \
+                                0x00050000  // 2048 B
+#define EPI_HB16TIME2_PSRAMSZ_4KB                                             \
+                                0x00060000  // 4096 B
+#define EPI_HB16TIME2_PSRAMSZ_8KB                                             \
+                                0x00070000  // 8192 B
+#define EPI_HB16TIME2_CAPWIDTH_M                                              \
+                                0x00003000  // CS1n Inter-transfer Capture
+                                            // Width
+#define EPI_HB16TIME2_WRWSM     0x00000010  // CS1n Write Wait State Minus One
+#define EPI_HB16TIME2_RDWSM     0x00000001  // CS1n Read Wait State Minus One
+#define EPI_HB16TIME2_IRDYDLY_S 24
+#define EPI_HB16TIME2_CAPWIDTH_S                                              \
+                                12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16TIME3
+// register.
+//
+//*****************************************************************************
+#define EPI_HB16TIME3_IRDYDLY_M 0x03000000  // CS2n Input Ready Delay
+#define EPI_HB16TIME3_PSRAMSZ_M 0x00070000  // PSRAM Row Size
+#define EPI_HB16TIME3_PSRAMSZ_0 0x00000000  // No row size limitation
+#define EPI_HB16TIME3_PSRAMSZ_128B                                            \
+                                0x00010000  // 128 B
+#define EPI_HB16TIME3_PSRAMSZ_256B                                            \
+                                0x00020000  // 256 B
+#define EPI_HB16TIME3_PSRAMSZ_512B                                            \
+                                0x00030000  // 512 B
+#define EPI_HB16TIME3_PSRAMSZ_1KB                                             \
+                                0x00040000  // 1024 B
+#define EPI_HB16TIME3_PSRAMSZ_2KB                                             \
+                                0x00050000  // 2048 B
+#define EPI_HB16TIME3_PSRAMSZ_4KB                                             \
+                                0x00060000  // 4096 B
+#define EPI_HB16TIME3_PSRAMSZ_8KB                                             \
+                                0x00070000  // 8192 B
+#define EPI_HB16TIME3_CAPWIDTH_M                                              \
+                                0x00003000  // CS2n Inter-transfer Capture
+                                            // Width
+#define EPI_HB16TIME3_WRWSM     0x00000010  // CS2n Write Wait State Minus One
+#define EPI_HB16TIME3_RDWSM     0x00000001  // CS2n Read Wait State Minus One
+#define EPI_HB16TIME3_IRDYDLY_S 24
+#define EPI_HB16TIME3_CAPWIDTH_S                                              \
+                                12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8TIME3 register.
+//
+//*****************************************************************************
+#define EPI_HB8TIME3_IRDYDLY_M  0x03000000  // CS2n Input Ready Delay
+#define EPI_HB8TIME3_CAPWIDTH_M 0x00003000  // CS2n Inter-transfer Capture
+                                            // Width
+#define EPI_HB8TIME3_WRWSM      0x00000010  // CS2n Write Wait State Minus One
+#define EPI_HB8TIME3_RDWSM      0x00000001  // CS2n Read Wait State Minus One
+#define EPI_HB8TIME3_IRDYDLY_S  24
+#define EPI_HB8TIME3_CAPWIDTH_S 12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8TIME4 register.
+//
+//*****************************************************************************
+#define EPI_HB8TIME4_IRDYDLY_M  0x03000000  // CS3n Input Ready Delay
+#define EPI_HB8TIME4_CAPWIDTH_M 0x00003000  // CS3n Inter-transfer Capture
+                                            // Width
+#define EPI_HB8TIME4_WRWSM      0x00000010  // CS3n Write Wait State Minus One
+#define EPI_HB8TIME4_RDWSM      0x00000001  // CS3n Read Wait State Minus One
+#define EPI_HB8TIME4_IRDYDLY_S  24
+#define EPI_HB8TIME4_CAPWIDTH_S 12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16TIME4
+// register.
+//
+//*****************************************************************************
+#define EPI_HB16TIME4_IRDYDLY_M 0x03000000  // CS3n Input Ready Delay
+#define EPI_HB16TIME4_PSRAMSZ_M 0x00070000  // PSRAM Row Size
+#define EPI_HB16TIME4_PSRAMSZ_0 0x00000000  // No row size limitation
+#define EPI_HB16TIME4_PSRAMSZ_128B                                            \
+                                0x00010000  // 128 B
+#define EPI_HB16TIME4_PSRAMSZ_256B                                            \
+                                0x00020000  // 256 B
+#define EPI_HB16TIME4_PSRAMSZ_512B                                            \
+                                0x00030000  // 512 B
+#define EPI_HB16TIME4_PSRAMSZ_1KB                                             \
+                                0x00040000  // 1024 B
+#define EPI_HB16TIME4_PSRAMSZ_2KB                                             \
+                                0x00050000  // 2048 B
+#define EPI_HB16TIME4_PSRAMSZ_4KB                                             \
+                                0x00060000  // 4096 B
+#define EPI_HB16TIME4_PSRAMSZ_8KB                                             \
+                                0x00070000  // 8192 B
+#define EPI_HB16TIME4_CAPWIDTH_M                                              \
+                                0x00003000  // CS3n Inter-transfer Capture
+                                            // Width
+#define EPI_HB16TIME4_WRWSM     0x00000010  // CS3n Write Wait State Minus One
+#define EPI_HB16TIME4_RDWSM     0x00000001  // CS3n Read Wait State Minus One
+#define EPI_HB16TIME4_IRDYDLY_S 24
+#define EPI_HB16TIME4_CAPWIDTH_S                                              \
+                                12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HBPSRAM register.
+//
+//*****************************************************************************
+#define EPI_HBPSRAM_CR_M        0x001FFFFF  // PSRAM Config Register
+#define EPI_HBPSRAM_CR_S        0
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the EPI_O_FIFOLVL
+// register.
+//
+//*****************************************************************************
+#define EPI_FIFOLVL_WRFIFO_1_4  0x00000020  // Trigger when there are up to 3
+                                            // spaces available in the WFIFO
+#define EPI_FIFOLVL_WRFIFO_1_2  0x00000030  // Trigger when there are up to 2
+                                            // spaces available in the WFIFO
+#define EPI_FIFOLVL_WRFIFO_3_4  0x00000040  // Trigger when there is 1 space
+                                            // available in the WFIFO
+#define EPI_FIFOLVL_RDFIFO_1_8  0x00000001  // Trigger when there are 1 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_1_4  0x00000002  // Trigger when there are 2 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_1_2  0x00000003  // Trigger when there are 4 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_3_4  0x00000004  // Trigger when there are 6 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_7_8  0x00000005  // Trigger when there are 7 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_FULL 0x00000006  // Trigger when there are 8 entries
+                                            // in the NBRFIFO
+
+#endif
+
+#endif // __HW_EPI_H__
diff --git a/os/common/ext/TivaWare/inc/hw_fan.h b/os/common/ext/TivaWare/inc/hw_fan.h
new file mode 100644
index 0000000..089a8ea
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_fan.h
@@ -0,0 +1,49 @@
+//*****************************************************************************
+//
+// hw_fan.h - Macros used when accessing the fan control hardware.
+//
+// Copyright (c) 2010-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_FAN_H__
+#define __HW_FAN_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Fan Control register offsets.
+//
+//*****************************************************************************
+
+#endif // __HW_FAN_H__
diff --git a/os/common/ext/TivaWare/inc/hw_flash.h b/os/common/ext/TivaWare/inc/hw_flash.h
new file mode 100644
index 0000000..0133b35
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_flash.h
@@ -0,0 +1,625 @@
+//*****************************************************************************
+//
+// hw_flash.h - Macros used when accessing the flash controller.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_FLASH_H__
+#define __HW_FLASH_H__
+
+//*****************************************************************************
+//
+// The following are defines for the FLASH register offsets.
+//
+//*****************************************************************************
+#define FLASH_FMA               0x400FD000  // Flash Memory Address
+#define FLASH_FMD               0x400FD004  // Flash Memory Data
+#define FLASH_FMC               0x400FD008  // Flash Memory Control
+#define FLASH_FCRIS             0x400FD00C  // Flash Controller Raw Interrupt
+                                            // Status
+#define FLASH_FCIM              0x400FD010  // Flash Controller Interrupt Mask
+#define FLASH_FCMISC            0x400FD014  // Flash Controller Masked
+                                            // Interrupt Status and Clear
+#define FLASH_FMC2              0x400FD020  // Flash Memory Control 2
+#define FLASH_FWBVAL            0x400FD030  // Flash Write Buffer Valid
+#define FLASH_FLPEKEY           0x400FD03C  // Flash Program/Erase Key
+#define FLASH_FWBN              0x400FD100  // Flash Write Buffer n
+#define FLASH_PP                0x400FDFC0  // Flash Peripheral Properties
+#define FLASH_FSIZE             0x400FDFC0  // Flash Size
+#define FLASH_SSIZE             0x400FDFC4  // SRAM Size
+#define FLASH_CONF              0x400FDFC8  // Flash Configuration Register
+#define FLASH_ROMSWMAP          0x400FDFCC  // ROM Software Map
+#define FLASH_DMASZ             0x400FDFD0  // Flash DMA Address Size
+#define FLASH_DMAST             0x400FDFD4  // Flash DMA Starting Address
+#define FLASH_RVP               0x400FE0D4  // Reset Vector Pointer
+#define FLASH_RMCTL             0x400FE0F0  // ROM Control
+#define FLASH_BOOTCFG           0x400FE1D0  // Boot Configuration
+#define FLASH_USERREG0          0x400FE1E0  // User Register 0
+#define FLASH_USERREG1          0x400FE1E4  // User Register 1
+#define FLASH_USERREG2          0x400FE1E8  // User Register 2
+#define FLASH_USERREG3          0x400FE1EC  // User Register 3
+#define FLASH_FMPRE0            0x400FE200  // Flash Memory Protection Read
+                                            // Enable 0
+#define FLASH_FMPRE1            0x400FE204  // Flash Memory Protection Read
+                                            // Enable 1
+#define FLASH_FMPRE2            0x400FE208  // Flash Memory Protection Read
+                                            // Enable 2
+#define FLASH_FMPRE3            0x400FE20C  // Flash Memory Protection Read
+                                            // Enable 3
+#define FLASH_FMPRE4            0x400FE210  // Flash Memory Protection Read
+                                            // Enable 4
+#define FLASH_FMPRE5            0x400FE214  // Flash Memory Protection Read
+                                            // Enable 5
+#define FLASH_FMPRE6            0x400FE218  // Flash Memory Protection Read
+                                            // Enable 6
+#define FLASH_FMPRE7            0x400FE21C  // Flash Memory Protection Read
+                                            // Enable 7
+#define FLASH_FMPRE8            0x400FE220  // Flash Memory Protection Read
+                                            // Enable 8
+#define FLASH_FMPRE9            0x400FE224  // Flash Memory Protection Read
+                                            // Enable 9
+#define FLASH_FMPRE10           0x400FE228  // Flash Memory Protection Read
+                                            // Enable 10
+#define FLASH_FMPRE11           0x400FE22C  // Flash Memory Protection Read
+                                            // Enable 11
+#define FLASH_FMPRE12           0x400FE230  // Flash Memory Protection Read
+                                            // Enable 12
+#define FLASH_FMPRE13           0x400FE234  // Flash Memory Protection Read
+                                            // Enable 13
+#define FLASH_FMPRE14           0x400FE238  // Flash Memory Protection Read
+                                            // Enable 14
+#define FLASH_FMPRE15           0x400FE23C  // Flash Memory Protection Read
+                                            // Enable 15
+#define FLASH_FMPPE0            0x400FE400  // Flash Memory Protection Program
+                                            // Enable 0
+#define FLASH_FMPPE1            0x400FE404  // Flash Memory Protection Program
+                                            // Enable 1
+#define FLASH_FMPPE2            0x400FE408  // Flash Memory Protection Program
+                                            // Enable 2
+#define FLASH_FMPPE3            0x400FE40C  // Flash Memory Protection Program
+                                            // Enable 3
+#define FLASH_FMPPE4            0x400FE410  // Flash Memory Protection Program
+                                            // Enable 4
+#define FLASH_FMPPE5            0x400FE414  // Flash Memory Protection Program
+                                            // Enable 5
+#define FLASH_FMPPE6            0x400FE418  // Flash Memory Protection Program
+                                            // Enable 6
+#define FLASH_FMPPE7            0x400FE41C  // Flash Memory Protection Program
+                                            // Enable 7
+#define FLASH_FMPPE8            0x400FE420  // Flash Memory Protection Program
+                                            // Enable 8
+#define FLASH_FMPPE9            0x400FE424  // Flash Memory Protection Program
+                                            // Enable 9
+#define FLASH_FMPPE10           0x400FE428  // Flash Memory Protection Program
+                                            // Enable 10
+#define FLASH_FMPPE11           0x400FE42C  // Flash Memory Protection Program
+                                            // Enable 11
+#define FLASH_FMPPE12           0x400FE430  // Flash Memory Protection Program
+                                            // Enable 12
+#define FLASH_FMPPE13           0x400FE434  // Flash Memory Protection Program
+                                            // Enable 13
+#define FLASH_FMPPE14           0x400FE438  // Flash Memory Protection Program
+                                            // Enable 14
+#define FLASH_FMPPE15           0x400FE43C  // Flash Memory Protection Program
+                                            // Enable 15
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMA register.
+//
+//*****************************************************************************
+#define FLASH_FMA_OFFSET_M      0x000FFFFF  // Address Offset
+#define FLASH_FMA_OFFSET_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMD register.
+//
+//*****************************************************************************
+#define FLASH_FMD_DATA_M        0xFFFFFFFF  // Data Value
+#define FLASH_FMD_DATA_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY         0xA4420000  // FLASH write key
+#define FLASH_FMC_COMT          0x00000008  // Commit Register Value
+#define FLASH_FMC_MERASE        0x00000004  // Mass Erase Flash Memory
+#define FLASH_FMC_ERASE         0x00000002  // Erase a Page of Flash Memory
+#define FLASH_FMC_WRITE         0x00000001  // Write a Word into Flash Memory
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCRIS register.
+//
+//*****************************************************************************
+#define FLASH_FCRIS_PROGRIS     0x00002000  // Program Verify Error Raw
+                                            // Interrupt Status
+#define FLASH_FCRIS_ERRIS       0x00000800  // Erase Verify Error Raw Interrupt
+                                            // Status
+#define FLASH_FCRIS_INVDRIS     0x00000400  // Invalid Data Raw Interrupt
+                                            // Status
+#define FLASH_FCRIS_VOLTRIS     0x00000200  // Pump Voltage Raw Interrupt
+                                            // Status
+#define FLASH_FCRIS_ERIS        0x00000004  // EEPROM Raw Interrupt Status
+#define FLASH_FCRIS_PRIS        0x00000002  // Programming Raw Interrupt Status
+#define FLASH_FCRIS_ARIS        0x00000001  // Access Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCIM register.
+//
+//*****************************************************************************
+#define FLASH_FCIM_PROGMASK     0x00002000  // PROGVER Interrupt Mask
+#define FLASH_FCIM_ERMASK       0x00000800  // ERVER Interrupt Mask
+#define FLASH_FCIM_INVDMASK     0x00000400  // Invalid Data Interrupt Mask
+#define FLASH_FCIM_VOLTMASK     0x00000200  // VOLT Interrupt Mask
+#define FLASH_FCIM_EMASK        0x00000004  // EEPROM Interrupt Mask
+#define FLASH_FCIM_PMASK        0x00000002  // Programming Interrupt Mask
+#define FLASH_FCIM_AMASK        0x00000001  // Access Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCMISC register.
+//
+//*****************************************************************************
+#define FLASH_FCMISC_PROGMISC   0x00002000  // PROGVER Masked Interrupt Status
+                                            // and Clear
+#define FLASH_FCMISC_ERMISC     0x00000800  // ERVER Masked Interrupt Status
+                                            // and Clear
+#define FLASH_FCMISC_INVDMISC   0x00000400  // Invalid Data Masked Interrupt
+                                            // Status and Clear
+#define FLASH_FCMISC_VOLTMISC   0x00000200  // VOLT Masked Interrupt Status and
+                                            // Clear
+#define FLASH_FCMISC_EMISC      0x00000004  // EEPROM Masked Interrupt Status
+                                            // and Clear
+#define FLASH_FCMISC_PMISC      0x00000002  // Programming Masked Interrupt
+                                            // Status and Clear
+#define FLASH_FCMISC_AMISC      0x00000001  // Access Masked Interrupt Status
+                                            // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC2 register.
+//
+//*****************************************************************************
+#define FLASH_FMC2_WRKEY        0xA4420000  // FLASH write key
+#define FLASH_FMC2_WRBUF        0x00000001  // Buffered Flash Memory Write
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FWBVAL register.
+//
+//*****************************************************************************
+#define FLASH_FWBVAL_FWB_M      0xFFFFFFFF  // Flash Memory Write Buffer
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FLPEKEY register.
+//
+//*****************************************************************************
+#define FLASH_FLPEKEY_PEKEY_M   0x0000FFFF  // Key Value
+#define FLASH_FLPEKEY_PEKEY_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FWBN register.
+//
+//*****************************************************************************
+#define FLASH_FWBN_DATA_M       0xFFFFFFFF  // Data
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_PP register.
+//
+//*****************************************************************************
+#define FLASH_PP_PFC            0x40000000  // Prefetch Buffer Mode
+#define FLASH_PP_FMM            0x20000000  // Flash Mirror Mode
+#define FLASH_PP_DFA            0x10000000  // DMA Flash Access
+#define FLASH_PP_EESS_M         0x00780000  // EEPROM Sector Size of the
+                                            // physical bank
+#define FLASH_PP_EESS_1KB       0x00000000  // 1 KB
+#define FLASH_PP_EESS_2KB       0x00080000  // 2 KB
+#define FLASH_PP_EESS_4KB       0x00100000  // 4 KB
+#define FLASH_PP_EESS_8KB       0x00180000  // 8 KB
+#define FLASH_PP_MAINSS_M       0x00070000  // Flash Sector Size of the
+                                            // physical bank
+#define FLASH_PP_MAINSS_1KB     0x00000000  // 1 KB
+#define FLASH_PP_MAINSS_2KB     0x00010000  // 2 KB
+#define FLASH_PP_MAINSS_4KB     0x00020000  // 4 KB
+#define FLASH_PP_MAINSS_8KB     0x00030000  // 8 KB
+#define FLASH_PP_MAINSS_16KB    0x00040000  // 16 KB
+#define FLASH_PP_SIZE_M         0x0000FFFF  // Flash Size
+#define FLASH_PP_SIZE_512KB     0x000000FF  // 512 KB of Flash
+#define FLASH_PP_SIZE_1MB       0x000001FF  // 1024 KB of Flash
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FSIZE register.
+//
+//*****************************************************************************
+#define FLASH_FSIZE_SIZE_M      0x0000FFFF  // Flash Size
+#define FLASH_FSIZE_SIZE_32KB   0x0000000F  // 32 KB of Flash
+#define FLASH_FSIZE_SIZE_64KB   0x0000001F  // 64 KB of Flash
+#define FLASH_FSIZE_SIZE_128KB  0x0000003F  // 128 KB of Flash
+#define FLASH_FSIZE_SIZE_256KB  0x0000007F  // 256 KB of Flash
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_SSIZE register.
+//
+//*****************************************************************************
+#define FLASH_SSIZE_SIZE_M      0x0000FFFF  // SRAM Size
+#define FLASH_SSIZE_SIZE_12KB   0x0000002F  // 12 KB of SRAM
+#define FLASH_SSIZE_SIZE_24KB   0x0000005F  // 24 KB of SRAM
+#define FLASH_SSIZE_SIZE_32KB   0x0000007F  // 32 KB of SRAM
+#define FLASH_SSIZE_SIZE_256KB  0x000003FF  // 256 KB of SRAM
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_CONF register.
+//
+//*****************************************************************************
+#define FLASH_CONF_FMME         0x40000000  // Flash Mirror Mode Enable
+#define FLASH_CONF_SPFE         0x20000000  // Single Prefetch Mode Enable
+#define FLASH_CONF_CLRTV        0x00100000  // Clear Valid Tags
+#define FLASH_CONF_FPFON        0x00020000  // Force Prefetch On
+#define FLASH_CONF_FPFOFF       0x00010000  // Force Prefetch Off
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_ROMSWMAP register.
+//
+//*****************************************************************************
+#define FLASH_ROMSWMAP_SAFERTOS 0x00000001  // SafeRTOS Present
+#define FLASH_ROMSWMAP_SW0EN_M  0x00000003  // ROM SW Region 0 Availability
+#define FLASH_ROMSWMAP_SW0EN_NOTVIS                                           \
+                                0x00000000  // Software region not available to
+                                            // the core
+#define FLASH_ROMSWMAP_SW0EN_CORE                                             \
+                                0x00000001  // Region available to core
+#define FLASH_ROMSWMAP_SW1EN_M  0x0000000C  // ROM SW Region 1 Availability
+#define FLASH_ROMSWMAP_SW1EN_NOTVIS                                           \
+                                0x00000000  // Software region not available to
+                                            // the core
+#define FLASH_ROMSWMAP_SW1EN_CORE                                             \
+                                0x00000004  // Region available to core
+#define FLASH_ROMSWMAP_SW2EN_M  0x00000030  // ROM SW Region 2 Availability
+#define FLASH_ROMSWMAP_SW2EN_NOTVIS                                           \
+                                0x00000000  // Software region not available to
+                                            // the core
+#define FLASH_ROMSWMAP_SW2EN_CORE                                             \
+                                0x00000010  // Region available to core
+#define FLASH_ROMSWMAP_SW3EN_M  0x000000C0  // ROM SW Region 3 Availability
+#define FLASH_ROMSWMAP_SW3EN_NOTVIS                                           \
+                                0x00000000  // Software region not available to
+                                            // the core
+#define FLASH_ROMSWMAP_SW3EN_CORE                                             \
+                                0x00000040  // Region available to core
+#define FLASH_ROMSWMAP_SW4EN_M  0x00000300  // ROM SW Region 4 Availability
+#define FLASH_ROMSWMAP_SW4EN_NOTVIS                                           \
+                                0x00000000  // Software region not available to
+                                            // the core
+#define FLASH_ROMSWMAP_SW4EN_CORE                                             \
+                                0x00000100  // Region available to core
+#define FLASH_ROMSWMAP_SW5EN_M  0x00000C00  // ROM SW Region 5 Availability
+#define FLASH_ROMSWMAP_SW5EN_NOTVIS                                           \
+                                0x00000000  // Software region not available to
+                                            // the core
+#define FLASH_ROMSWMAP_SW5EN_CORE                                             \
+                                0x00000400  // Region available to core
+#define FLASH_ROMSWMAP_SW6EN_M  0x00003000  // ROM SW Region 6 Availability
+#define FLASH_ROMSWMAP_SW6EN_NOTVIS                                           \
+                                0x00000000  // Software region not available to
+                                            // the core
+#define FLASH_ROMSWMAP_SW6EN_CORE                                             \
+                                0x00001000  // Region available to core
+#define FLASH_ROMSWMAP_SW7EN_M  0x0000C000  // ROM SW Region 7 Availability
+#define FLASH_ROMSWMAP_SW7EN_NOTVIS                                           \
+                                0x00000000  // Software region not available to
+                                            // the core
+#define FLASH_ROMSWMAP_SW7EN_CORE                                             \
+                                0x00004000  // Region available to core
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_DMASZ register.
+//
+//*****************************************************************************
+#define FLASH_DMASZ_SIZE_M      0x0003FFFF  // uDMA-accessible Memory Size
+#define FLASH_DMASZ_SIZE_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_DMAST register.
+//
+//*****************************************************************************
+#define FLASH_DMAST_ADDR_M      0x1FFFF800  // Contains the starting address of
+                                            // the flash region accessible by
+                                            // uDMA if the FLASHPP register DFA
+                                            // bit is set
+#define FLASH_DMAST_ADDR_S      11
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_RVP register.
+//
+//*****************************************************************************
+#define FLASH_RVP_RV_M          0xFFFFFFFF  // Reset Vector Pointer Address
+#define FLASH_RVP_RV_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_RMCTL register.
+//
+//*****************************************************************************
+#define FLASH_RMCTL_BA          0x00000001  // Boot Alias
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_BOOTCFG register.
+//
+//*****************************************************************************
+#define FLASH_BOOTCFG_NW        0x80000000  // Not Written
+#define FLASH_BOOTCFG_PORT_M    0x0000E000  // Boot GPIO Port
+#define FLASH_BOOTCFG_PORT_A    0x00000000  // Port A
+#define FLASH_BOOTCFG_PORT_B    0x00002000  // Port B
+#define FLASH_BOOTCFG_PORT_C    0x00004000  // Port C
+#define FLASH_BOOTCFG_PORT_D    0x00006000  // Port D
+#define FLASH_BOOTCFG_PORT_E    0x00008000  // Port E
+#define FLASH_BOOTCFG_PORT_F    0x0000A000  // Port F
+#define FLASH_BOOTCFG_PORT_G    0x0000C000  // Port G
+#define FLASH_BOOTCFG_PORT_H    0x0000E000  // Port H
+#define FLASH_BOOTCFG_PIN_M     0x00001C00  // Boot GPIO Pin
+#define FLASH_BOOTCFG_PIN_0     0x00000000  // Pin 0
+#define FLASH_BOOTCFG_PIN_1     0x00000400  // Pin 1
+#define FLASH_BOOTCFG_PIN_2     0x00000800  // Pin 2
+#define FLASH_BOOTCFG_PIN_3     0x00000C00  // Pin 3
+#define FLASH_BOOTCFG_PIN_4     0x00001000  // Pin 4
+#define FLASH_BOOTCFG_PIN_5     0x00001400  // Pin 5
+#define FLASH_BOOTCFG_PIN_6     0x00001800  // Pin 6
+#define FLASH_BOOTCFG_PIN_7     0x00001C00  // Pin 7
+#define FLASH_BOOTCFG_POL       0x00000200  // Boot GPIO Polarity
+#define FLASH_BOOTCFG_EN        0x00000100  // Boot GPIO Enable
+#define FLASH_BOOTCFG_KEY       0x00000010  // KEY Select
+#define FLASH_BOOTCFG_DBG1      0x00000002  // Debug Control 1
+#define FLASH_BOOTCFG_DBG0      0x00000001  // Debug Control 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG0 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG0_DATA_M   0xFFFFFFFF  // User Data
+#define FLASH_USERREG0_DATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG1 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG1_DATA_M   0xFFFFFFFF  // User Data
+#define FLASH_USERREG1_DATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG2 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG2_DATA_M   0xFFFFFFFF  // User Data
+#define FLASH_USERREG2_DATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG3 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG3_DATA_M   0xFFFFFFFF  // User Data
+#define FLASH_USERREG3_DATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE8 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE8_READ_ENABLE_M                                            \
+                                0xFFFFFFFF  // Flash Read Enable
+#define FLASH_FMPRE8_READ_ENABLE_S                                            \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE9 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE9_READ_ENABLE_M                                            \
+                                0xFFFFFFFF  // Flash Read Enable
+#define FLASH_FMPRE9_READ_ENABLE_S                                            \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE10 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE10_READ_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Read Enable
+#define FLASH_FMPRE10_READ_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE11 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE11_READ_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Read Enable
+#define FLASH_FMPRE11_READ_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE12 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE12_READ_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Read Enable
+#define FLASH_FMPRE12_READ_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE13 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE13_READ_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Read Enable
+#define FLASH_FMPRE13_READ_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE14 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE14_READ_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Read Enable
+#define FLASH_FMPRE14_READ_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE15 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE15_READ_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Read Enable
+#define FLASH_FMPRE15_READ_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE8 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE8_PROG_ENABLE_M                                            \
+                                0xFFFFFFFF  // Flash Programming Enable
+#define FLASH_FMPPE8_PROG_ENABLE_S                                            \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE9 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE9_PROG_ENABLE_M                                            \
+                                0xFFFFFFFF  // Flash Programming Enable
+#define FLASH_FMPPE9_PROG_ENABLE_S                                            \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE10 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE10_PROG_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Programming Enable
+#define FLASH_FMPPE10_PROG_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE11 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE11_PROG_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Programming Enable
+#define FLASH_FMPPE11_PROG_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE12 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE12_PROG_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Programming Enable
+#define FLASH_FMPPE12_PROG_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE13 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE13_PROG_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Programming Enable
+#define FLASH_FMPPE13_PROG_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE14 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE14_PROG_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Programming Enable
+#define FLASH_FMPPE14_PROG_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE15 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE15_PROG_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Programming Enable
+#define FLASH_FMPPE15_PROG_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the erase size of the FLASH block that is
+// erased by an erase operation, and the protect size is the size of the FLASH
+// block that is protected by each protection register.
+//
+//*****************************************************************************
+#define FLASH_PROTECT_SIZE      0x00000800
+#define FLASH_ERASE_SIZE        0x00000400
+
+#endif // __HW_FLASH_H__
diff --git a/os/common/ext/TivaWare/inc/hw_gpio.h b/os/common/ext/TivaWare/inc/hw_gpio.h
new file mode 100644
index 0000000..a2ef2e7
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_gpio.h
@@ -0,0 +1,213 @@
+//*****************************************************************************
+//
+// hw_gpio.h - Defines and Macros for GPIO hardware.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_GPIO_H__
+#define __HW_GPIO_H__
+
+//*****************************************************************************
+//
+// The following are defines for the GPIO register offsets.
+//
+//*****************************************************************************
+#define GPIO_O_DATA             0x00000000  // GPIO Data
+#define GPIO_O_DIR              0x00000400  // GPIO Direction
+#define GPIO_O_IS               0x00000404  // GPIO Interrupt Sense
+#define GPIO_O_IBE              0x00000408  // GPIO Interrupt Both Edges
+#define GPIO_O_IEV              0x0000040C  // GPIO Interrupt Event
+#define GPIO_O_IM               0x00000410  // GPIO Interrupt Mask
+#define GPIO_O_RIS              0x00000414  // GPIO Raw Interrupt Status
+#define GPIO_O_MIS              0x00000418  // GPIO Masked Interrupt Status
+#define GPIO_O_ICR              0x0000041C  // GPIO Interrupt Clear
+#define GPIO_O_AFSEL            0x00000420  // GPIO Alternate Function Select
+#define GPIO_O_DR2R             0x00000500  // GPIO 2-mA Drive Select
+#define GPIO_O_DR4R             0x00000504  // GPIO 4-mA Drive Select
+#define GPIO_O_DR8R             0x00000508  // GPIO 8-mA Drive Select
+#define GPIO_O_ODR              0x0000050C  // GPIO Open Drain Select
+#define GPIO_O_PUR              0x00000510  // GPIO Pull-Up Select
+#define GPIO_O_PDR              0x00000514  // GPIO Pull-Down Select
+#define GPIO_O_SLR              0x00000518  // GPIO Slew Rate Control Select
+#define GPIO_O_DEN              0x0000051C  // GPIO Digital Enable
+#define GPIO_O_LOCK             0x00000520  // GPIO Lock
+#define GPIO_O_CR               0x00000524  // GPIO Commit
+#define GPIO_O_AMSEL            0x00000528  // GPIO Analog Mode Select
+#define GPIO_O_PCTL             0x0000052C  // GPIO Port Control
+#define GPIO_O_ADCCTL           0x00000530  // GPIO ADC Control
+#define GPIO_O_DMACTL           0x00000534  // GPIO DMA Control
+#define GPIO_O_SI               0x00000538  // GPIO Select Interrupt
+#define GPIO_O_DR12R            0x0000053C  // GPIO 12-mA Drive Select
+#define GPIO_O_WAKEPEN          0x00000540  // GPIO Wake Pin Enable
+#define GPIO_O_WAKELVL          0x00000544  // GPIO Wake Level
+#define GPIO_O_WAKESTAT         0x00000548  // GPIO Wake Status
+#define GPIO_O_PP               0x00000FC0  // GPIO Peripheral Property
+#define GPIO_O_PC               0x00000FC4  // GPIO Peripheral Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_IM register.
+//
+//*****************************************************************************
+#define GPIO_IM_DMAIME          0x00000100  // GPIO uDMA Done Interrupt Mask
+                                            // Enable
+#define GPIO_IM_GPIO_M          0x000000FF  // GPIO Interrupt Mask Enable
+#define GPIO_IM_GPIO_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_RIS register.
+//
+//*****************************************************************************
+#define GPIO_RIS_DMARIS         0x00000100  // GPIO uDMA Done Interrupt Raw
+                                            // Status
+#define GPIO_RIS_GPIO_M         0x000000FF  // GPIO Interrupt Raw Status
+#define GPIO_RIS_GPIO_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_MIS register.
+//
+//*****************************************************************************
+#define GPIO_MIS_DMAMIS         0x00000100  // GPIO uDMA Done Masked Interrupt
+                                            // Status
+#define GPIO_MIS_GPIO_M         0x000000FF  // GPIO Masked Interrupt Status
+#define GPIO_MIS_GPIO_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_ICR register.
+//
+//*****************************************************************************
+#define GPIO_ICR_DMAIC          0x00000100  // GPIO uDMA Interrupt Clear
+#define GPIO_ICR_GPIO_M         0x000000FF  // GPIO Interrupt Clear
+#define GPIO_ICR_GPIO_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_LOCK register.
+//
+//*****************************************************************************
+#define GPIO_LOCK_M             0xFFFFFFFF  // GPIO Lock
+#define GPIO_LOCK_UNLOCKED      0x00000000  // The GPIOCR register is unlocked
+                                            // and may be modified
+#define GPIO_LOCK_LOCKED        0x00000001  // The GPIOCR register is locked
+                                            // and may not be modified
+#define GPIO_LOCK_KEY           0x4C4F434B  // Unlocks the GPIO_CR register
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_SI register.
+//
+//*****************************************************************************
+#define GPIO_SI_SUM             0x00000001  // Summary Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_DR12R register.
+//
+//*****************************************************************************
+#define GPIO_DR12R_DRV12_M      0x000000FF  // Output Pad 12-mA Drive Enable
+#define GPIO_DR12R_DRV12_12MA   0x00000001  // The corresponding GPIO pin has
+                                            // 12-mA drive. This encoding is
+                                            // only valid if the GPIOPP EDE bit
+                                            // is set and the appropriate
+                                            // GPIOPC EDM bit field is
+                                            // programmed to 0x3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_WAKEPEN register.
+//
+//*****************************************************************************
+#define GPIO_WAKEPEN_WAKEP4     0x00000010  // P[4] Wake Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_WAKELVL register.
+//
+//*****************************************************************************
+#define GPIO_WAKELVL_WAKELVL4   0x00000010  // P[4] Wake Level
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_WAKESTAT
+// register.
+//
+//*****************************************************************************
+#define GPIO_WAKESTAT_STAT4     0x00000010  // P[4] Wake Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_PP register.
+//
+//*****************************************************************************
+#define GPIO_PP_EDE             0x00000001  // Extended Drive Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_PC register.
+//
+//*****************************************************************************
+#define GPIO_PC_EDM7_M          0x0000C000  // Extended Drive Mode Bit 7
+#define GPIO_PC_EDM6_M          0x00003000  // Extended Drive Mode Bit 6
+#define GPIO_PC_EDM5_M          0x00000C00  // Extended Drive Mode Bit 5
+#define GPIO_PC_EDM4_M          0x00000300  // Extended Drive Mode Bit 4
+#define GPIO_PC_EDM3_M          0x000000C0  // Extended Drive Mode Bit 3
+#define GPIO_PC_EDM2_M          0x00000030  // Extended Drive Mode Bit 2
+#define GPIO_PC_EDM1_M          0x0000000C  // Extended Drive Mode Bit 1
+#define GPIO_PC_EDM0_M          0x00000003  // Extended Drive Mode Bit 0
+#define GPIO_PC_EDM0_DISABLE    0x00000000  // Drive values of 2, 4 and 8 mA
+                                            // are maintained. GPIO n Drive
+                                            // Select (GPIODRnR) registers
+                                            // function as normal
+#define GPIO_PC_EDM0_6MA        0x00000001  // An additional 6 mA option is
+                                            // provided
+#define GPIO_PC_EDM0_PLUS2MA    0x00000003  // A 2 mA driver is always enabled;
+                                            // setting the corresponding
+                                            // GPIODR4R register bit adds 2 mA
+                                            // and setting the corresponding
+                                            // GPIODR8R of GPIODR12R register
+                                            // bit adds an additional 4 mA
+#define GPIO_PC_EDM7_S          14
+#define GPIO_PC_EDM6_S          12
+#define GPIO_PC_EDM5_S          10
+#define GPIO_PC_EDM4_S          8
+#define GPIO_PC_EDM3_S          6
+#define GPIO_PC_EDM2_S          4
+#define GPIO_PC_EDM1_S          2
+
+#endif // __HW_GPIO_H__
diff --git a/os/common/ext/TivaWare/inc/hw_hibernate.h b/os/common/ext/TivaWare/inc/hw_hibernate.h
new file mode 100644
index 0000000..6c9b4be
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_hibernate.h
@@ -0,0 +1,483 @@
+//*****************************************************************************
+//
+// hw_hibernate.h - Defines and Macros for the Hibernation module.
+//
+// Copyright (c) 2007-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_HIBERNATE_H__
+#define __HW_HIBERNATE_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Hibernation module register addresses.
+//
+//*****************************************************************************
+#define HIB_RTCC                0x400FC000  // Hibernation RTC Counter
+#define HIB_RTCM0               0x400FC004  // Hibernation RTC Match 0
+#define HIB_RTCLD               0x400FC00C  // Hibernation RTC Load
+#define HIB_CTL                 0x400FC010  // Hibernation Control
+#define HIB_IM                  0x400FC014  // Hibernation Interrupt Mask
+#define HIB_RIS                 0x400FC018  // Hibernation Raw Interrupt Status
+#define HIB_MIS                 0x400FC01C  // Hibernation Masked Interrupt
+                                            // Status
+#define HIB_IC                  0x400FC020  // Hibernation Interrupt Clear
+#define HIB_RTCT                0x400FC024  // Hibernation RTC Trim
+#define HIB_RTCSS               0x400FC028  // Hibernation RTC Sub Seconds
+#define HIB_IO                  0x400FC02C  // Hibernation IO Configuration
+#define HIB_DATA                0x400FC030  // Hibernation Data
+#define HIB_CALCTL              0x400FC300  // Hibernation Calendar Control
+#define HIB_CAL0                0x400FC310  // Hibernation Calendar 0
+#define HIB_CAL1                0x400FC314  // Hibernation Calendar 1
+#define HIB_CALLD0              0x400FC320  // Hibernation Calendar Load 0
+#define HIB_CALLD1              0x400FC324  // Hibernation Calendar Load
+#define HIB_CALM0               0x400FC330  // Hibernation Calendar Match 0
+#define HIB_CALM1               0x400FC334  // Hibernation Calendar Match 1
+#define HIB_LOCK                0x400FC360  // Hibernation Lock
+#define HIB_TPCTL               0x400FC400  // HIB Tamper Control
+#define HIB_TPSTAT              0x400FC404  // HIB Tamper Status
+#define HIB_TPIO                0x400FC410  // HIB Tamper I/O Control
+#define HIB_TPLOG0              0x400FC4E0  // HIB Tamper Log 0
+#define HIB_TPLOG1              0x400FC4E4  // HIB Tamper Log 1
+#define HIB_TPLOG2              0x400FC4E8  // HIB Tamper Log 2
+#define HIB_TPLOG3              0x400FC4EC  // HIB Tamper Log 3
+#define HIB_TPLOG4              0x400FC4F0  // HIB Tamper Log 4
+#define HIB_TPLOG5              0x400FC4F4  // HIB Tamper Log 5
+#define HIB_TPLOG6              0x400FC4F8  // HIB Tamper Log 6
+#define HIB_TPLOG7              0x400FC4FC  // HIB Tamper Log 7
+#define HIB_PP                  0x400FCFC0  // Hibernation Peripheral
+                                            // Properties
+#define HIB_CC                  0x400FCFC8  // Hibernation Clock Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCC register.
+//
+//*****************************************************************************
+#define HIB_RTCC_M              0xFFFFFFFF  // RTC Counter
+#define HIB_RTCC_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCM0 register.
+//
+//*****************************************************************************
+#define HIB_RTCM0_M             0xFFFFFFFF  // RTC Match 0
+#define HIB_RTCM0_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCLD register.
+//
+//*****************************************************************************
+#define HIB_RTCLD_M             0xFFFFFFFF  // RTC Load
+#define HIB_RTCLD_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CTL register.
+//
+//*****************************************************************************
+#define HIB_CTL_WRC             0x80000000  // Write Complete/Capable
+#define HIB_CTL_RETCLR          0x40000000  // GPIO Retention/Clear
+#define HIB_CTL_OSCSEL          0x00080000  // Oscillator Select
+#define HIB_CTL_OSCDRV          0x00020000  // Oscillator Drive Capability
+#define HIB_CTL_OSCBYP          0x00010000  // Oscillator Bypass
+#define HIB_CTL_VBATSEL_M       0x00006000  // Select for Low-Battery
+                                            // Comparator
+#define HIB_CTL_VBATSEL_1_9V    0x00000000  // 1.9 Volts
+#define HIB_CTL_VBATSEL_2_1V    0x00002000  // 2.1 Volts (default)
+#define HIB_CTL_VBATSEL_2_3V    0x00004000  // 2.3 Volts
+#define HIB_CTL_VBATSEL_2_5V    0x00006000  // 2.5 Volts
+#define HIB_CTL_BATCHK          0x00000400  // Check Battery Status
+#define HIB_CTL_BATWKEN         0x00000200  // Wake on Low Battery
+#define HIB_CTL_VDD3ON          0x00000100  // VDD Powered
+#define HIB_CTL_VABORT          0x00000080  // Power Cut Abort Enable
+#define HIB_CTL_CLK32EN         0x00000040  // Clocking Enable
+#define HIB_CTL_PINWEN          0x00000010  // External Wake Pin Enable
+#define HIB_CTL_RTCWEN          0x00000008  // RTC Wake-up Enable
+#define HIB_CTL_HIBREQ          0x00000002  // Hibernation Request
+#define HIB_CTL_RTCEN           0x00000001  // RTC Timer Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IM register.
+//
+//*****************************************************************************
+#define HIB_IM_VDDFAIL          0x00000080  // VDD Fail Interrupt Mask
+#define HIB_IM_RSTWK            0x00000040  // Reset Pad I/O Wake-Up Interrupt
+                                            // Mask
+#define HIB_IM_PADIOWK          0x00000020  // Pad I/O Wake-Up Interrupt Mask
+#define HIB_IM_WC               0x00000010  // External Write Complete/Capable
+                                            // Interrupt Mask
+#define HIB_IM_EXTW             0x00000008  // External Wake-Up Interrupt Mask
+#define HIB_IM_LOWBAT           0x00000004  // Low Battery Voltage Interrupt
+                                            // Mask
+#define HIB_IM_RTCALT0          0x00000001  // RTC Alert 0 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RIS register.
+//
+//*****************************************************************************
+#define HIB_RIS_VDDFAIL         0x00000080  // VDD Fail Raw Interrupt Status
+#define HIB_RIS_RSTWK           0x00000040  // Reset Pad I/O Wake-Up Raw
+                                            // Interrupt Status
+#define HIB_RIS_PADIOWK         0x00000020  // Pad I/O Wake-Up Raw Interrupt
+                                            // Status
+#define HIB_RIS_WC              0x00000010  // Write Complete/Capable Raw
+                                            // Interrupt Status
+#define HIB_RIS_EXTW            0x00000008  // External Wake-Up Raw Interrupt
+                                            // Status
+#define HIB_RIS_LOWBAT          0x00000004  // Low Battery Voltage Raw
+                                            // Interrupt Status
+#define HIB_RIS_RTCALT0         0x00000001  // RTC Alert 0 Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_MIS register.
+//
+//*****************************************************************************
+#define HIB_MIS_VDDFAIL         0x00000080  // VDD Fail Interrupt Mask
+#define HIB_MIS_RSTWK           0x00000040  // Reset Pad I/O Wake-Up Interrupt
+                                            // Mask
+#define HIB_MIS_PADIOWK         0x00000020  // Pad I/O Wake-Up Interrupt Mask
+#define HIB_MIS_WC              0x00000010  // Write Complete/Capable Masked
+                                            // Interrupt Status
+#define HIB_MIS_EXTW            0x00000008  // External Wake-Up Masked
+                                            // Interrupt Status
+#define HIB_MIS_LOWBAT          0x00000004  // Low Battery Voltage Masked
+                                            // Interrupt Status
+#define HIB_MIS_RTCALT0         0x00000001  // RTC Alert 0 Masked Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IC register.
+//
+//*****************************************************************************
+#define HIB_IC_VDDFAIL          0x00000080  // VDD Fail Interrupt Clear
+#define HIB_IC_RSTWK            0x00000040  // Reset Pad I/O Wake-Up Interrupt
+                                            // Clear
+#define HIB_IC_PADIOWK          0x00000020  // Pad I/O Wake-Up Interrupt Clear
+#define HIB_IC_WC               0x00000010  // Write Complete/Capable Interrupt
+                                            // Clear
+#define HIB_IC_EXTW             0x00000008  // External Wake-Up Interrupt Clear
+#define HIB_IC_LOWBAT           0x00000004  // Low Battery Voltage Interrupt
+                                            // Clear
+#define HIB_IC_RTCALT0          0x00000001  // RTC Alert0 Masked Interrupt
+                                            // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCT register.
+//
+//*****************************************************************************
+#define HIB_RTCT_TRIM_M         0x0000FFFF  // RTC Trim Value
+#define HIB_RTCT_TRIM_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCSS register.
+//
+//*****************************************************************************
+#define HIB_RTCSS_RTCSSM_M      0x7FFF0000  // RTC Sub Seconds Match
+#define HIB_RTCSS_RTCSSC_M      0x00007FFF  // RTC Sub Seconds Count
+#define HIB_RTCSS_RTCSSM_S      16
+#define HIB_RTCSS_RTCSSC_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IO register.
+//
+//*****************************************************************************
+#define HIB_IO_IOWRC            0x80000000  // I/O Write Complete
+#define HIB_IO_WURSTEN          0x00000010  // Reset Wake Source Enable
+#define HIB_IO_WUUNLK           0x00000001  // I/O Wake Pad Configuration
+                                            // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_DATA register.
+//
+//*****************************************************************************
+#define HIB_DATA_RTD_M          0xFFFFFFFF  // Hibernation Module NV Data
+#define HIB_DATA_RTD_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CALCTL register.
+//
+//*****************************************************************************
+#define HIB_CALCTL_CAL24        0x00000004  // Calendar Mode
+#define HIB_CALCTL_CALEN        0x00000001  // RTC Calendar/Counter Mode Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CAL0 register.
+//
+//*****************************************************************************
+#define HIB_CAL0_VALID          0x80000000  // Valid Calendar Load
+#define HIB_CAL0_AMPM           0x00400000  // AM/PM Designation
+#define HIB_CAL0_HR_M           0x001F0000  // Hours
+#define HIB_CAL0_MIN_M          0x00003F00  // Minutes
+#define HIB_CAL0_SEC_M          0x0000003F  // Seconds
+#define HIB_CAL0_HR_S           16
+#define HIB_CAL0_MIN_S          8
+#define HIB_CAL0_SEC_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CAL1 register.
+//
+//*****************************************************************************
+#define HIB_CAL1_VALID          0x80000000  // Valid Calendar Load
+#define HIB_CAL1_DOW_M          0x07000000  // Day of Week
+#define HIB_CAL1_YEAR_M         0x007F0000  // Year Value
+#define HIB_CAL1_MON_M          0x00000F00  // Month
+#define HIB_CAL1_DOM_M          0x0000001F  // Day of Month
+#define HIB_CAL1_DOW_S          24
+#define HIB_CAL1_YEAR_S         16
+#define HIB_CAL1_MON_S          8
+#define HIB_CAL1_DOM_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CALLD0 register.
+//
+//*****************************************************************************
+#define HIB_CALLD0_AMPM         0x00400000  // AM/PM Designation
+#define HIB_CALLD0_HR_M         0x001F0000  // Hours
+#define HIB_CALLD0_MIN_M        0x00003F00  // Minutes
+#define HIB_CALLD0_SEC_M        0x0000003F  // Seconds
+#define HIB_CALLD0_HR_S         16
+#define HIB_CALLD0_MIN_S        8
+#define HIB_CALLD0_SEC_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CALLD1 register.
+//
+//*****************************************************************************
+#define HIB_CALLD1_DOW_M        0x07000000  // Day of Week
+#define HIB_CALLD1_YEAR_M       0x007F0000  // Year Value
+#define HIB_CALLD1_MON_M        0x00000F00  // Month
+#define HIB_CALLD1_DOM_M        0x0000001F  // Day of Month
+#define HIB_CALLD1_DOW_S        24
+#define HIB_CALLD1_YEAR_S       16
+#define HIB_CALLD1_MON_S        8
+#define HIB_CALLD1_DOM_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CALM0 register.
+//
+//*****************************************************************************
+#define HIB_CALM0_AMPM          0x00400000  // AM/PM Designation
+#define HIB_CALM0_HR_M          0x001F0000  // Hours
+#define HIB_CALM0_MIN_M         0x00003F00  // Minutes
+#define HIB_CALM0_SEC_M         0x0000003F  // Seconds
+#define HIB_CALM0_HR_S          16
+#define HIB_CALM0_MIN_S         8
+#define HIB_CALM0_SEC_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CALM1 register.
+//
+//*****************************************************************************
+#define HIB_CALM1_DOM_M         0x0000001F  // Day of Month
+#define HIB_CALM1_DOM_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_LOCK register.
+//
+//*****************************************************************************
+#define HIB_LOCK_HIBLOCK_M      0xFFFFFFFF  // HIbernate Lock
+#define HIB_LOCK_HIBLOCK_KEY    0xA3359554  // Hibernate Lock Key
+#define HIB_LOCK_HIBLOCK_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPCTL register.
+//
+//*****************************************************************************
+#define HIB_TPCTL_WAKE          0x00000800  // Wake from Hibernate on a Tamper
+                                            // Event
+#define HIB_TPCTL_MEMCLR_M      0x00000300  // HIB Memory Clear on Tamper Event
+#define HIB_TPCTL_MEMCLR_NONE   0x00000000  // Do not Clear HIB memory on
+                                            // tamper event
+#define HIB_TPCTL_MEMCLR_LOW32  0x00000100  // Clear Lower 32 Bytes of HIB
+                                            // memory on tamper event
+#define HIB_TPCTL_MEMCLR_HIGH32 0x00000200  // Clear upper 32 Bytes of HIB
+                                            // memory on tamper event
+#define HIB_TPCTL_MEMCLR_ALL    0x00000300  // Clear all HIB memory on tamper
+                                            // event
+#define HIB_TPCTL_TPCLR         0x00000010  // Tamper Event Clear
+#define HIB_TPCTL_TPEN          0x00000001  // Tamper Module Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPSTAT register.
+//
+//*****************************************************************************
+#define HIB_TPSTAT_STATE_M      0x0000000C  // Tamper Module Status
+#define HIB_TPSTAT_STATE_DISABLED                                             \
+                                0x00000000  // Tamper disabled
+#define HIB_TPSTAT_STATE_CONFIGED                                             \
+                                0x00000004  // Tamper configured
+#define HIB_TPSTAT_STATE_ERROR  0x00000008  // Tamper pin event occurred
+#define HIB_TPSTAT_XOSCST       0x00000002  // External Oscillator Status
+#define HIB_TPSTAT_XOSCFAIL     0x00000001  // External Oscillator Failure
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPIO register.
+//
+//*****************************************************************************
+#define HIB_TPIO_GFLTR3         0x08000000  // TMPR3 Glitch Filtering
+#define HIB_TPIO_PUEN3          0x04000000  // TMPR3 Internal Weak Pull-up
+                                            // Enable
+#define HIB_TPIO_LEV3           0x02000000  // TMPR3 Trigger Level
+#define HIB_TPIO_EN3            0x01000000  // TMPR3 Enable
+#define HIB_TPIO_GFLTR2         0x00080000  // TMPR2 Glitch Filtering
+#define HIB_TPIO_PUEN2          0x00040000  // TMPR2 Internal Weak Pull-up
+                                            // Enable
+#define HIB_TPIO_LEV2           0x00020000  // TMPR2 Trigger Level
+#define HIB_TPIO_EN2            0x00010000  // TMPR2 Enable
+#define HIB_TPIO_GFLTR1         0x00000800  // TMPR1 Glitch Filtering
+#define HIB_TPIO_PUEN1          0x00000400  // TMPR1 Internal Weak Pull-up
+                                            // Enable
+#define HIB_TPIO_LEV1           0x00000200  // TMPR1 Trigger Level
+#define HIB_TPIO_EN1            0x00000100  // TMPR1Enable
+#define HIB_TPIO_GFLTR0         0x00000008  // TMPR0 Glitch Filtering
+#define HIB_TPIO_PUEN0          0x00000004  // TMPR0 Internal Weak Pull-up
+                                            // Enable
+#define HIB_TPIO_LEV0           0x00000002  // TMPR0 Trigger Level
+#define HIB_TPIO_EN0            0x00000001  // TMPR0 Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG0 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG0_TIME_M       0xFFFFFFFF  // Tamper Log Calendar Information
+#define HIB_TPLOG0_TIME_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG1 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG1_XOSC         0x00010000  // Status of external 32
+#define HIB_TPLOG1_TRIG3        0x00000008  // Status of TMPR[3] Trigger
+#define HIB_TPLOG1_TRIG2        0x00000004  // Status of TMPR[2] Trigger
+#define HIB_TPLOG1_TRIG1        0x00000002  // Status of TMPR[1] Trigger
+#define HIB_TPLOG1_TRIG0        0x00000001  // Status of TMPR[0] Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG2 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG2_TIME_M       0xFFFFFFFF  // Tamper Log Calendar Information
+#define HIB_TPLOG2_TIME_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG3 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG3_XOSC         0x00010000  // Status of external 32
+#define HIB_TPLOG3_TRIG3        0x00000008  // Status of TMPR[3] Trigger
+#define HIB_TPLOG3_TRIG2        0x00000004  // Status of TMPR[2] Trigger
+#define HIB_TPLOG3_TRIG1        0x00000002  // Status of TMPR[1] Trigger
+#define HIB_TPLOG3_TRIG0        0x00000001  // Status of TMPR[0] Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG4 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG4_TIME_M       0xFFFFFFFF  // Tamper Log Calendar Information
+#define HIB_TPLOG4_TIME_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG5 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG5_XOSC         0x00010000  // Status of external 32
+#define HIB_TPLOG5_TRIG3        0x00000008  // Status of TMPR[3] Trigger
+#define HIB_TPLOG5_TRIG2        0x00000004  // Status of TMPR[2] Trigger
+#define HIB_TPLOG5_TRIG1        0x00000002  // Status of TMPR[1] Trigger
+#define HIB_TPLOG5_TRIG0        0x00000001  // Status of TMPR[0] Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG6 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG6_TIME_M       0xFFFFFFFF  // Tamper Log Calendar Information
+#define HIB_TPLOG6_TIME_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG7 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG7_XOSC         0x00010000  // Status of external 32
+#define HIB_TPLOG7_TRIG3        0x00000008  // Status of TMPR[3] Trigger
+#define HIB_TPLOG7_TRIG2        0x00000004  // Status of TMPR[2] Trigger
+#define HIB_TPLOG7_TRIG1        0x00000002  // Status of TMPR[1] Trigger
+#define HIB_TPLOG7_TRIG0        0x00000001  // Status of TMPR[0] Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_PP register.
+//
+//*****************************************************************************
+#define HIB_PP_TAMPER           0x00000002  // Tamper Pin Presence
+#define HIB_PP_WAKENC           0x00000001  // Wake Pin Presence
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CC register.
+//
+//*****************************************************************************
+#define HIB_CC_SYSCLKEN         0x00000001  // RTCOSC to System Clock Enable
+
+#endif // __HW_HIBERNATE_H__
diff --git a/os/common/ext/TivaWare/inc/hw_i2c.h b/os/common/ext/TivaWare/inc/hw_i2c.h
new file mode 100644
index 0000000..2cc2032
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_i2c.h
@@ -0,0 +1,470 @@
+//*****************************************************************************
+//
+// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_I2C_H__
+#define __HW_I2C_H__
+
+//*****************************************************************************
+//
+// The following are defines for the I2C register offsets.
+//
+//*****************************************************************************
+#define I2C_O_MSA               0x00000000  // I2C Master Slave Address
+#define I2C_O_MCS               0x00000004  // I2C Master Control/Status
+#define I2C_O_MDR               0x00000008  // I2C Master Data
+#define I2C_O_MTPR              0x0000000C  // I2C Master Timer Period
+#define I2C_O_MIMR              0x00000010  // I2C Master Interrupt Mask
+#define I2C_O_MRIS              0x00000014  // I2C Master Raw Interrupt Status
+#define I2C_O_MMIS              0x00000018  // I2C Master Masked Interrupt
+                                            // Status
+#define I2C_O_MICR              0x0000001C  // I2C Master Interrupt Clear
+#define I2C_O_MCR               0x00000020  // I2C Master Configuration
+#define I2C_O_MCLKOCNT          0x00000024  // I2C Master Clock Low Timeout
+                                            // Count
+#define I2C_O_MBMON             0x0000002C  // I2C Master Bus Monitor
+#define I2C_O_MBLEN             0x00000030  // I2C Master Burst Length
+#define I2C_O_MBCNT             0x00000034  // I2C Master Burst Count
+#define I2C_O_MCR2              0x00000038  // I2C Master Configuration 2
+#define I2C_O_SOAR              0x00000800  // I2C Slave Own Address
+#define I2C_O_SCSR              0x00000804  // I2C Slave Control/Status
+#define I2C_O_SDR               0x00000808  // I2C Slave Data
+#define I2C_O_SIMR              0x0000080C  // I2C Slave Interrupt Mask
+#define I2C_O_SRIS              0x00000810  // I2C Slave Raw Interrupt Status
+#define I2C_O_SMIS              0x00000814  // I2C Slave Masked Interrupt
+                                            // Status
+#define I2C_O_SICR              0x00000818  // I2C Slave Interrupt Clear
+#define I2C_O_SOAR2             0x0000081C  // I2C Slave Own Address 2
+#define I2C_O_SACKCTL           0x00000820  // I2C Slave ACK Control
+#define I2C_O_FIFODATA          0x00000F00  // I2C FIFO Data
+#define I2C_O_FIFOCTL           0x00000F04  // I2C FIFO Control
+#define I2C_O_FIFOSTATUS        0x00000F08  // I2C FIFO Status
+#define I2C_O_PP                0x00000FC0  // I2C Peripheral Properties
+#define I2C_O_PC                0x00000FC4  // I2C Peripheral Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MSA register.
+//
+//*****************************************************************************
+#define I2C_MSA_SA_M            0x000000FE  // I2C Slave Address
+#define I2C_MSA_RS              0x00000001  // Receive not send
+#define I2C_MSA_SA_S            1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCS register.
+//
+//*****************************************************************************
+#define I2C_MCS_ACTDMARX        0x80000000  // DMA RX Active Status
+#define I2C_MCS_ACTDMATX        0x40000000  // DMA TX Active Status
+#define I2C_MCS_CLKTO           0x00000080  // Clock Timeout Error
+#define I2C_MCS_BURST           0x00000040  // Burst Enable
+#define I2C_MCS_BUSBSY          0x00000040  // Bus Busy
+#define I2C_MCS_IDLE            0x00000020  // I2C Idle
+#define I2C_MCS_QCMD            0x00000020  // Quick Command
+#define I2C_MCS_ARBLST          0x00000010  // Arbitration Lost
+#define I2C_MCS_HS              0x00000010  // High-Speed Enable
+#define I2C_MCS_ACK             0x00000008  // Data Acknowledge Enable
+#define I2C_MCS_DATACK          0x00000008  // Acknowledge Data
+#define I2C_MCS_ADRACK          0x00000004  // Acknowledge Address
+#define I2C_MCS_STOP            0x00000004  // Generate STOP
+#define I2C_MCS_ERROR           0x00000002  // Error
+#define I2C_MCS_START           0x00000002  // Generate START
+#define I2C_MCS_RUN             0x00000001  // I2C Master Enable
+#define I2C_MCS_BUSY            0x00000001  // I2C Busy
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MDR register.
+//
+//*****************************************************************************
+#define I2C_MDR_DATA_M          0x000000FF  // This byte contains the data
+                                            // transferred during a transaction
+#define I2C_MDR_DATA_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MTPR register.
+//
+//*****************************************************************************
+#define I2C_MTPR_PULSEL_M       0x00070000  // Glitch Suppression Pulse Width
+#define I2C_MTPR_PULSEL_BYPASS  0x00000000  // Bypass
+#define I2C_MTPR_PULSEL_1       0x00010000  // 1 clock
+#define I2C_MTPR_PULSEL_2       0x00020000  // 2 clocks
+#define I2C_MTPR_PULSEL_3       0x00030000  // 3 clocks
+#define I2C_MTPR_PULSEL_4       0x00040000  // 4 clocks
+#define I2C_MTPR_PULSEL_8       0x00050000  // 8 clocks
+#define I2C_MTPR_PULSEL_16      0x00060000  // 16 clocks
+#define I2C_MTPR_PULSEL_31      0x00070000  // 31 clocks
+#define I2C_MTPR_HS             0x00000080  // High-Speed Enable
+#define I2C_MTPR_TPR_M          0x0000007F  // Timer Period
+#define I2C_MTPR_TPR_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MIMR register.
+//
+//*****************************************************************************
+#define I2C_MIMR_RXFFIM         0x00000800  // Receive FIFO Full Interrupt Mask
+#define I2C_MIMR_TXFEIM         0x00000400  // Transmit FIFO Empty Interrupt
+                                            // Mask
+#define I2C_MIMR_RXIM           0x00000200  // Receive FIFO Request Interrupt
+                                            // Mask
+#define I2C_MIMR_TXIM           0x00000100  // Transmit FIFO Request Interrupt
+                                            // Mask
+#define I2C_MIMR_ARBLOSTIM      0x00000080  // Arbitration Lost Interrupt Mask
+#define I2C_MIMR_STOPIM         0x00000040  // STOP Detection Interrupt Mask
+#define I2C_MIMR_STARTIM        0x00000020  // START Detection Interrupt Mask
+#define I2C_MIMR_NACKIM         0x00000010  // Address/Data NACK Interrupt Mask
+#define I2C_MIMR_DMATXIM        0x00000008  // Transmit DMA Interrupt Mask
+#define I2C_MIMR_DMARXIM        0x00000004  // Receive DMA Interrupt Mask
+#define I2C_MIMR_CLKIM          0x00000002  // Clock Timeout Interrupt Mask
+#define I2C_MIMR_IM             0x00000001  // Master Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MRIS register.
+//
+//*****************************************************************************
+#define I2C_MRIS_RXFFRIS        0x00000800  // Receive FIFO Full Raw Interrupt
+                                            // Status
+#define I2C_MRIS_TXFERIS        0x00000400  // Transmit FIFO Empty Raw
+                                            // Interrupt Status
+#define I2C_MRIS_RXRIS          0x00000200  // Receive FIFO Request Raw
+                                            // Interrupt Status
+#define I2C_MRIS_TXRIS          0x00000100  // Transmit Request Raw Interrupt
+                                            // Status
+#define I2C_MRIS_ARBLOSTRIS     0x00000080  // Arbitration Lost Raw Interrupt
+                                            // Status
+#define I2C_MRIS_STOPRIS        0x00000040  // STOP Detection Raw Interrupt
+                                            // Status
+#define I2C_MRIS_STARTRIS       0x00000020  // START Detection Raw Interrupt
+                                            // Status
+#define I2C_MRIS_NACKRIS        0x00000010  // Address/Data NACK Raw Interrupt
+                                            // Status
+#define I2C_MRIS_DMATXRIS       0x00000008  // Transmit DMA Raw Interrupt
+                                            // Status
+#define I2C_MRIS_DMARXRIS       0x00000004  // Receive DMA Raw Interrupt Status
+#define I2C_MRIS_CLKRIS         0x00000002  // Clock Timeout Raw Interrupt
+                                            // Status
+#define I2C_MRIS_RIS            0x00000001  // Master Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MMIS register.
+//
+//*****************************************************************************
+#define I2C_MMIS_RXFFMIS        0x00000800  // Receive FIFO Full Interrupt Mask
+#define I2C_MMIS_TXFEMIS        0x00000400  // Transmit FIFO Empty Interrupt
+                                            // Mask
+#define I2C_MMIS_RXMIS          0x00000200  // Receive FIFO Request Interrupt
+                                            // Mask
+#define I2C_MMIS_TXMIS          0x00000100  // Transmit Request Interrupt Mask
+#define I2C_MMIS_ARBLOSTMIS     0x00000080  // Arbitration Lost Interrupt Mask
+#define I2C_MMIS_STOPMIS        0x00000040  // STOP Detection Interrupt Mask
+#define I2C_MMIS_STARTMIS       0x00000020  // START Detection Interrupt Mask
+#define I2C_MMIS_NACKMIS        0x00000010  // Address/Data NACK Interrupt Mask
+#define I2C_MMIS_DMATXMIS       0x00000008  // Transmit DMA Interrupt Status
+#define I2C_MMIS_DMARXMIS       0x00000004  // Receive DMA Interrupt Status
+#define I2C_MMIS_CLKMIS         0x00000002  // Clock Timeout Masked Interrupt
+                                            // Status
+#define I2C_MMIS_MIS            0x00000001  // Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MICR register.
+//
+//*****************************************************************************
+#define I2C_MICR_RXFFIC         0x00000800  // Receive FIFO Full Interrupt
+                                            // Clear
+#define I2C_MICR_TXFEIC         0x00000400  // Transmit FIFO Empty Interrupt
+                                            // Clear
+#define I2C_MICR_RXIC           0x00000200  // Receive FIFO Request Interrupt
+                                            // Clear
+#define I2C_MICR_TXIC           0x00000100  // Transmit FIFO Request Interrupt
+                                            // Clear
+#define I2C_MICR_ARBLOSTIC      0x00000080  // Arbitration Lost Interrupt Clear
+#define I2C_MICR_STOPIC         0x00000040  // STOP Detection Interrupt Clear
+#define I2C_MICR_STARTIC        0x00000020  // START Detection Interrupt Clear
+#define I2C_MICR_NACKIC         0x00000010  // Address/Data NACK Interrupt
+                                            // Clear
+#define I2C_MICR_DMATXIC        0x00000008  // Transmit DMA Interrupt Clear
+#define I2C_MICR_DMARXIC        0x00000004  // Receive DMA Interrupt Clear
+#define I2C_MICR_CLKIC          0x00000002  // Clock Timeout Interrupt Clear
+#define I2C_MICR_IC             0x00000001  // Master Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCR register.
+//
+//*****************************************************************************
+#define I2C_MCR_GFE             0x00000040  // I2C Glitch Filter Enable
+#define I2C_MCR_SFE             0x00000020  // I2C Slave Function Enable
+#define I2C_MCR_MFE             0x00000010  // I2C Master Function Enable
+#define I2C_MCR_LPBK            0x00000001  // I2C Loopback
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCLKOCNT register.
+//
+//*****************************************************************************
+#define I2C_MCLKOCNT_CNTL_M     0x000000FF  // I2C Master Count
+#define I2C_MCLKOCNT_CNTL_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MBMON register.
+//
+//*****************************************************************************
+#define I2C_MBMON_SDA           0x00000002  // I2C SDA Status
+#define I2C_MBMON_SCL           0x00000001  // I2C SCL Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MBLEN register.
+//
+//*****************************************************************************
+#define I2C_MBLEN_CNTL_M        0x000000FF  // I2C Burst Length
+#define I2C_MBLEN_CNTL_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MBCNT register.
+//
+//*****************************************************************************
+#define I2C_MBCNT_CNTL_M        0x000000FF  // I2C Master Burst Count
+#define I2C_MBCNT_CNTL_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCR2 register.
+//
+//*****************************************************************************
+#define I2C_MCR2_GFPW_M         0x00000070  // I2C Glitch Filter Pulse Width
+#define I2C_MCR2_GFPW_BYPASS    0x00000000  // Bypass
+#define I2C_MCR2_GFPW_1         0x00000010  // 1 clock
+#define I2C_MCR2_GFPW_2         0x00000020  // 2 clocks
+#define I2C_MCR2_GFPW_3         0x00000030  // 3 clocks
+#define I2C_MCR2_GFPW_4         0x00000040  // 4 clocks
+#define I2C_MCR2_GFPW_8         0x00000050  // 8 clocks
+#define I2C_MCR2_GFPW_16        0x00000060  // 16 clocks
+#define I2C_MCR2_GFPW_31        0x00000070  // 31 clocks
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR register.
+//
+//*****************************************************************************
+#define I2C_SOAR_OAR_M          0x0000007F  // I2C Slave Own Address
+#define I2C_SOAR_OAR_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SCSR register.
+//
+//*****************************************************************************
+#define I2C_SCSR_ACTDMARX       0x80000000  // DMA RX Active Status
+#define I2C_SCSR_ACTDMATX       0x40000000  // DMA TX Active Status
+#define I2C_SCSR_QCMDRW         0x00000020  // Quick Command Read / Write
+#define I2C_SCSR_QCMDST         0x00000010  // Quick Command Status
+#define I2C_SCSR_OAR2SEL        0x00000008  // OAR2 Address Matched
+#define I2C_SCSR_FBR            0x00000004  // First Byte Received
+#define I2C_SCSR_RXFIFO         0x00000004  // RX FIFO Enable
+#define I2C_SCSR_TXFIFO         0x00000002  // TX FIFO Enable
+#define I2C_SCSR_TREQ           0x00000002  // Transmit Request
+#define I2C_SCSR_DA             0x00000001  // Device Active
+#define I2C_SCSR_RREQ           0x00000001  // Receive Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SDR register.
+//
+//*****************************************************************************
+#define I2C_SDR_DATA_M          0x000000FF  // Data for Transfer
+#define I2C_SDR_DATA_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SIMR register.
+//
+//*****************************************************************************
+#define I2C_SIMR_RXFFIM         0x00000100  // Receive FIFO Full Interrupt Mask
+#define I2C_SIMR_TXFEIM         0x00000080  // Transmit FIFO Empty Interrupt
+                                            // Mask
+#define I2C_SIMR_RXIM           0x00000040  // Receive FIFO Request Interrupt
+                                            // Mask
+#define I2C_SIMR_TXIM           0x00000020  // Transmit FIFO Request Interrupt
+                                            // Mask
+#define I2C_SIMR_DMATXIM        0x00000010  // Transmit DMA Interrupt Mask
+#define I2C_SIMR_DMARXIM        0x00000008  // Receive DMA Interrupt Mask
+#define I2C_SIMR_STOPIM         0x00000004  // Stop Condition Interrupt Mask
+#define I2C_SIMR_STARTIM        0x00000002  // Start Condition Interrupt Mask
+#define I2C_SIMR_DATAIM         0x00000001  // Data Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SRIS register.
+//
+//*****************************************************************************
+#define I2C_SRIS_RXFFRIS        0x00000100  // Receive FIFO Full Raw Interrupt
+                                            // Status
+#define I2C_SRIS_TXFERIS        0x00000080  // Transmit FIFO Empty Raw
+                                            // Interrupt Status
+#define I2C_SRIS_RXRIS          0x00000040  // Receive FIFO Request Raw
+                                            // Interrupt Status
+#define I2C_SRIS_TXRIS          0x00000020  // Transmit Request Raw Interrupt
+                                            // Status
+#define I2C_SRIS_DMATXRIS       0x00000010  // Transmit DMA Raw Interrupt
+                                            // Status
+#define I2C_SRIS_DMARXRIS       0x00000008  // Receive DMA Raw Interrupt Status
+#define I2C_SRIS_STOPRIS        0x00000004  // Stop Condition Raw Interrupt
+                                            // Status
+#define I2C_SRIS_STARTRIS       0x00000002  // Start Condition Raw Interrupt
+                                            // Status
+#define I2C_SRIS_DATARIS        0x00000001  // Data Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SMIS register.
+//
+//*****************************************************************************
+#define I2C_SMIS_RXFFMIS        0x00000100  // Receive FIFO Full Interrupt Mask
+#define I2C_SMIS_TXFEMIS        0x00000080  // Transmit FIFO Empty Interrupt
+                                            // Mask
+#define I2C_SMIS_RXMIS          0x00000040  // Receive FIFO Request Interrupt
+                                            // Mask
+#define I2C_SMIS_TXMIS          0x00000020  // Transmit FIFO Request Interrupt
+                                            // Mask
+#define I2C_SMIS_DMATXMIS       0x00000010  // Transmit DMA Masked Interrupt
+                                            // Status
+#define I2C_SMIS_DMARXMIS       0x00000008  // Receive DMA Masked Interrupt
+                                            // Status
+#define I2C_SMIS_STOPMIS        0x00000004  // Stop Condition Masked Interrupt
+                                            // Status
+#define I2C_SMIS_STARTMIS       0x00000002  // Start Condition Masked Interrupt
+                                            // Status
+#define I2C_SMIS_DATAMIS        0x00000001  // Data Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SICR register.
+//
+//*****************************************************************************
+#define I2C_SICR_RXFFIC         0x00000100  // Receive FIFO Full Interrupt Mask
+#define I2C_SICR_TXFEIC         0x00000080  // Transmit FIFO Empty Interrupt
+                                            // Mask
+#define I2C_SICR_RXIC           0x00000040  // Receive Request Interrupt Mask
+#define I2C_SICR_TXIC           0x00000020  // Transmit Request Interrupt Mask
+#define I2C_SICR_DMATXIC        0x00000010  // Transmit DMA Interrupt Clear
+#define I2C_SICR_DMARXIC        0x00000008  // Receive DMA Interrupt Clear
+#define I2C_SICR_STOPIC         0x00000004  // Stop Condition Interrupt Clear
+#define I2C_SICR_STARTIC        0x00000002  // Start Condition Interrupt Clear
+#define I2C_SICR_DATAIC         0x00000001  // Data Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR2 register.
+//
+//*****************************************************************************
+#define I2C_SOAR2_OAR2EN        0x00000080  // I2C Slave Own Address 2 Enable
+#define I2C_SOAR2_OAR2_M        0x0000007F  // I2C Slave Own Address 2
+#define I2C_SOAR2_OAR2_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SACKCTL register.
+//
+//*****************************************************************************
+#define I2C_SACKCTL_ACKOVAL     0x00000002  // I2C Slave ACK Override Value
+#define I2C_SACKCTL_ACKOEN      0x00000001  // I2C Slave ACK Override Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_FIFODATA register.
+//
+//*****************************************************************************
+#define I2C_FIFODATA_DATA_M     0x000000FF  // I2C TX FIFO Write Data Byte
+#define I2C_FIFODATA_DATA_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_FIFOCTL register.
+//
+//*****************************************************************************
+#define I2C_FIFOCTL_RXASGNMT    0x80000000  // RX Control Assignment
+#define I2C_FIFOCTL_RXFLUSH     0x40000000  // RX FIFO Flush
+#define I2C_FIFOCTL_DMARXENA    0x20000000  // DMA RX Channel Enable
+#define I2C_FIFOCTL_RXTRIG_M    0x00070000  // RX FIFO Trigger
+#define I2C_FIFOCTL_TXASGNMT    0x00008000  // TX Control Assignment
+#define I2C_FIFOCTL_TXFLUSH     0x00004000  // TX FIFO Flush
+#define I2C_FIFOCTL_DMATXENA    0x00002000  // DMA TX Channel Enable
+#define I2C_FIFOCTL_TXTRIG_M    0x00000007  // TX FIFO Trigger
+#define I2C_FIFOCTL_RXTRIG_S    16
+#define I2C_FIFOCTL_TXTRIG_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_FIFOSTATUS
+// register.
+//
+//*****************************************************************************
+#define I2C_FIFOSTATUS_RXABVTRIG                                              \
+                                0x00040000  // RX FIFO Above Trigger Level
+#define I2C_FIFOSTATUS_RXFF     0x00020000  // RX FIFO Full
+#define I2C_FIFOSTATUS_RXFE     0x00010000  // RX FIFO Empty
+#define I2C_FIFOSTATUS_TXBLWTRIG                                              \
+                                0x00000004  // TX FIFO Below Trigger Level
+#define I2C_FIFOSTATUS_TXFF     0x00000002  // TX FIFO Full
+#define I2C_FIFOSTATUS_TXFE     0x00000001  // TX FIFO Empty
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_PP register.
+//
+//*****************************************************************************
+#define I2C_PP_HS               0x00000001  // High-Speed Capable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_PC register.
+//
+//*****************************************************************************
+#define I2C_PC_HS               0x00000001  // High-Speed Capable
+
+#endif // __HW_I2C_H__
diff --git a/os/common/ext/TivaWare/inc/hw_ints.h b/os/common/ext/TivaWare/inc/hw_ints.h
new file mode 100644
index 0000000..d8efb43
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_ints.h
@@ -0,0 +1,491 @@
+//*****************************************************************************
+//
+// hw_ints.h - Macros that define the interrupt assignment on Tiva C Series
+// MCUs.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_INTS_H__
+#define __HW_INTS_H__
+
+//*****************************************************************************
+//
+// The following are defines for the fault assignments.
+//
+//*****************************************************************************
+#define FAULT_NMI               2           // NMI fault
+#define FAULT_HARD              3           // Hard fault
+#define FAULT_MPU               4           // MPU fault
+#define FAULT_BUS               5           // Bus fault
+#define FAULT_USAGE             6           // Usage fault
+#define FAULT_SVCALL            11          // SVCall
+#define FAULT_DEBUG             12          // Debug monitor
+#define FAULT_PENDSV            14          // PendSV
+#define FAULT_SYSTICK           15          // System Tick
+
+//*****************************************************************************
+//
+// TM4C123 Class Interrupts
+//
+//*****************************************************************************
+#define INT_GPIOA_TM4C123       16          // GPIO Port A
+#define INT_GPIOB_TM4C123       17          // GPIO Port B
+#define INT_GPIOC_TM4C123       18          // GPIO Port C
+#define INT_GPIOD_TM4C123       19          // GPIO Port D
+#define INT_GPIOE_TM4C123       20          // GPIO Port E
+#define INT_UART0_TM4C123       21          // UART0
+#define INT_UART1_TM4C123       22          // UART1
+#define INT_SSI0_TM4C123        23          // SSI0
+#define INT_I2C0_TM4C123        24          // I2C0
+#define INT_PWM0_FAULT_TM4C123  25          // PWM0 Fault
+#define INT_PWM0_0_TM4C123      26          // PWM0 Generator 0
+#define INT_PWM0_1_TM4C123      27          // PWM0 Generator 1
+#define INT_PWM0_2_TM4C123      28          // PWM0 Generator 2
+#define INT_QEI0_TM4C123        29          // QEI0
+#define INT_ADC0SS0_TM4C123     30          // ADC0 Sequence 0
+#define INT_ADC0SS1_TM4C123     31          // ADC0 Sequence 1
+#define INT_ADC0SS2_TM4C123     32          // ADC0 Sequence 2
+#define INT_ADC0SS3_TM4C123     33          // ADC0 Sequence 3
+#define INT_WATCHDOG_TM4C123    34          // Watchdog Timers 0 and 1
+#define INT_TIMER0A_TM4C123     35          // 16/32-Bit Timer 0A
+#define INT_TIMER0B_TM4C123     36          // 16/32-Bit Timer 0B
+#define INT_TIMER1A_TM4C123     37          // 16/32-Bit Timer 1A
+#define INT_TIMER1B_TM4C123     38          // 16/32-Bit Timer 1B
+#define INT_TIMER2A_TM4C123     39          // 16/32-Bit Timer 2A
+#define INT_TIMER2B_TM4C123     40          // 16/32-Bit Timer 2B
+#define INT_COMP0_TM4C123       41          // Analog Comparator 0
+#define INT_COMP1_TM4C123       42          // Analog Comparator 1
+#define INT_COMP2_TM4C123       43          // Analog Comparator 2
+#define INT_SYSCTL_TM4C123      44          // System Control
+#define INT_FLASH_TM4C123       45          // Flash Memory Control and EEPROM
+                                            // Control
+#define INT_GPIOF_TM4C123       46          // GPIO Port F
+#define INT_GPIOG_TM4C123       47          // GPIO Port G
+#define INT_GPIOH_TM4C123       48          // GPIO Port H
+#define INT_UART2_TM4C123       49          // UART2
+#define INT_SSI1_TM4C123        50          // SSI1
+#define INT_TIMER3A_TM4C123     51          // 16/32-Bit Timer 3A
+#define INT_TIMER3B_TM4C123     52          // Timer 3B
+#define INT_I2C1_TM4C123        53          // I2C1
+#define INT_QEI1_TM4C123        54          // QEI1
+#define INT_CAN0_TM4C123        55          // CAN0
+#define INT_CAN1_TM4C123        56          // CAN1
+#define INT_HIBERNATE_TM4C123   59          // Hibernation Module
+#define INT_USB0_TM4C123        60          // USB
+#define INT_PWM0_3_TM4C123      61          // PWM Generator 3
+#define INT_UDMA_TM4C123        62          // uDMA Software
+#define INT_UDMAERR_TM4C123     63          // uDMA Error
+#define INT_ADC1SS0_TM4C123     64          // ADC1 Sequence 0
+#define INT_ADC1SS1_TM4C123     65          // ADC1 Sequence 1
+#define INT_ADC1SS2_TM4C123     66          // ADC1 Sequence 2
+#define INT_ADC1SS3_TM4C123     67          // ADC1 Sequence 3
+#define INT_GPIOJ_TM4C123       70          // GPIO Port J
+#define INT_GPIOK_TM4C123       71          // GPIO Port K
+#define INT_GPIOL_TM4C123       72          // GPIO Port L
+#define INT_SSI2_TM4C123        73          // SSI2
+#define INT_SSI3_TM4C123        74          // SSI3
+#define INT_UART3_TM4C123       75          // UART3
+#define INT_UART4_TM4C123       76          // UART4
+#define INT_UART5_TM4C123       77          // UART5
+#define INT_UART6_TM4C123       78          // UART6
+#define INT_UART7_TM4C123       79          // UART7
+#define INT_I2C2_TM4C123        84          // I2C2
+#define INT_I2C3_TM4C123        85          // I2C3
+#define INT_TIMER4A_TM4C123     86          // 16/32-Bit Timer 4A
+#define INT_TIMER4B_TM4C123     87          // 16/32-Bit Timer 4B
+#define INT_TIMER5A_TM4C123     108         // 16/32-Bit Timer 5A
+#define INT_TIMER5B_TM4C123     109         // 16/32-Bit Timer 5B
+#define INT_WTIMER0A_TM4C123    110         // 32/64-Bit Timer 0A
+#define INT_WTIMER0B_TM4C123    111         // 32/64-Bit Timer 0B
+#define INT_WTIMER1A_TM4C123    112         // 32/64-Bit Timer 1A
+#define INT_WTIMER1B_TM4C123    113         // 32/64-Bit Timer 1B
+#define INT_WTIMER2A_TM4C123    114         // 32/64-Bit Timer 2A
+#define INT_WTIMER2B_TM4C123    115         // 32/64-Bit Timer 2B
+#define INT_WTIMER3A_TM4C123    116         // 32/64-Bit Timer 3A
+#define INT_WTIMER3B_TM4C123    117         // 32/64-Bit Timer 3B
+#define INT_WTIMER4A_TM4C123    118         // 32/64-Bit Timer 4A
+#define INT_WTIMER4B_TM4C123    119         // 32/64-Bit Timer 4B
+#define INT_WTIMER5A_TM4C123    120         // 32/64-Bit Timer 5A
+#define INT_WTIMER5B_TM4C123    121         // 32/64-Bit Timer 5B
+#define INT_SYSEXC_TM4C123      122         // System Exception (imprecise)
+#define INT_I2C4_TM4C123        125         // I2C4
+#define INT_I2C5_TM4C123        126         // I2C5
+#define INT_GPIOM_TM4C123       127         // GPIO Port M
+#define INT_GPION_TM4C123       128         // GPIO Port N
+#define INT_GPIOP0_TM4C123      132         // GPIO Port P (Summary or P0)
+#define INT_GPIOP1_TM4C123      133         // GPIO Port P1
+#define INT_GPIOP2_TM4C123      134         // GPIO Port P2
+#define INT_GPIOP3_TM4C123      135         // GPIO Port P3
+#define INT_GPIOP4_TM4C123      136         // GPIO Port P4
+#define INT_GPIOP5_TM4C123      137         // GPIO Port P5
+#define INT_GPIOP6_TM4C123      138         // GPIO Port P6
+#define INT_GPIOP7_TM4C123      139         // GPIO Port P7
+#define INT_GPIOQ0_TM4C123      140         // GPIO Port Q (Summary or Q0)
+#define INT_GPIOQ1_TM4C123      141         // GPIO Port Q1
+#define INT_GPIOQ2_TM4C123      142         // GPIO Port Q2
+#define INT_GPIOQ3_TM4C123      143         // GPIO Port Q3
+#define INT_GPIOQ4_TM4C123      144         // GPIO Port Q4
+#define INT_GPIOQ5_TM4C123      145         // GPIO Port Q5
+#define INT_GPIOQ6_TM4C123      146         // GPIO Port Q6
+#define INT_GPIOQ7_TM4C123      147         // GPIO Port Q7
+#define INT_PWM1_0_TM4C123      150         // PWM1 Generator 0
+#define INT_PWM1_1_TM4C123      151         // PWM1 Generator 1
+#define INT_PWM1_2_TM4C123      152         // PWM1 Generator 2
+#define INT_PWM1_3_TM4C123      153         // PWM1 Generator 3
+#define INT_PWM1_FAULT_TM4C123  154         // PWM1 Fault
+#define NUM_INTERRUPTS_TM4C123  155
+
+//*****************************************************************************
+//
+// TM4C129 Class Interrupts
+//
+//*****************************************************************************
+#define INT_GPIOA_TM4C129       16          // GPIO Port A
+#define INT_GPIOB_TM4C129       17          // GPIO Port B
+#define INT_GPIOC_TM4C129       18          // GPIO Port C
+#define INT_GPIOD_TM4C129       19          // GPIO Port D
+#define INT_GPIOE_TM4C129       20          // GPIO Port E
+#define INT_UART0_TM4C129       21          // UART0
+#define INT_UART1_TM4C129       22          // UART1
+#define INT_SSI0_TM4C129        23          // SSI0
+#define INT_I2C0_TM4C129        24          // I2C0
+#define INT_PWM0_FAULT_TM4C129  25          // PWM Fault
+#define INT_PWM0_0_TM4C129      26          // PWM Generator 0
+#define INT_PWM0_1_TM4C129      27          // PWM Generator 1
+#define INT_PWM0_2_TM4C129      28          // PWM Generator 2
+#define INT_QEI0_TM4C129        29          // QEI0
+#define INT_ADC0SS0_TM4C129     30          // ADC0 Sequence 0
+#define INT_ADC0SS1_TM4C129     31          // ADC0 Sequence 1
+#define INT_ADC0SS2_TM4C129     32          // ADC0 Sequence 2
+#define INT_ADC0SS3_TM4C129     33          // ADC0 Sequence 3
+#define INT_WATCHDOG_TM4C129    34          // Watchdog Timers 0 and 1
+#define INT_TIMER0A_TM4C129     35          // 16/32-Bit Timer 0A
+#define INT_TIMER0B_TM4C129     36          // 16/32-Bit Timer 0B
+#define INT_TIMER1A_TM4C129     37          // 16/32-Bit Timer 1A
+#define INT_TIMER1B_TM4C129     38          // 16/32-Bit Timer 1B
+#define INT_TIMER2A_TM4C129     39          // 16/32-Bit Timer 2A
+#define INT_TIMER2B_TM4C129     40          // 16/32-Bit Timer 2B
+#define INT_COMP0_TM4C129       41          // Analog Comparator 0
+#define INT_COMP1_TM4C129       42          // Analog Comparator 1
+#define INT_COMP2_TM4C129       43          // Analog Comparator 2
+#define INT_SYSCTL_TM4C129      44          // System Control
+#define INT_FLASH_TM4C129       45          // Flash Memory Control
+#define INT_GPIOF_TM4C129       46          // GPIO Port F
+#define INT_GPIOG_TM4C129       47          // GPIO Port G
+#define INT_GPIOH_TM4C129       48          // GPIO Port H
+#define INT_UART2_TM4C129       49          // UART2
+#define INT_SSI1_TM4C129        50          // SSI1
+#define INT_TIMER3A_TM4C129     51          // 16/32-Bit Timer 3A
+#define INT_TIMER3B_TM4C129     52          // 16/32-Bit Timer 3B
+#define INT_I2C1_TM4C129        53          // I2C1
+#define INT_CAN0_TM4C129        54          // CAN 0
+#define INT_CAN1_TM4C129        55          // CAN1
+#define INT_EMAC0_TM4C129       56          // Ethernet MAC
+#define INT_HIBERNATE_TM4C129   57          // HIB
+#define INT_USB0_TM4C129        58          // USB MAC
+#define INT_PWM0_3_TM4C129      59          // PWM Generator 3
+#define INT_UDMA_TM4C129        60          // uDMA 0 Software
+#define INT_UDMAERR_TM4C129     61          // uDMA 0 Error
+#define INT_ADC1SS0_TM4C129     62          // ADC1 Sequence 0
+#define INT_ADC1SS1_TM4C129     63          // ADC1 Sequence 1
+#define INT_ADC1SS2_TM4C129     64          // ADC1 Sequence 2
+#define INT_ADC1SS3_TM4C129     65          // ADC1 Sequence 3
+#define INT_EPI0_TM4C129        66          // EPI 0
+#define INT_GPIOJ_TM4C129       67          // GPIO Port J
+#define INT_GPIOK_TM4C129       68          // GPIO Port K
+#define INT_GPIOL_TM4C129       69          // GPIO Port L
+#define INT_SSI2_TM4C129        70          // SSI 2
+#define INT_SSI3_TM4C129        71          // SSI 3
+#define INT_UART3_TM4C129       72          // UART 3
+#define INT_UART4_TM4C129       73          // UART 4
+#define INT_UART5_TM4C129       74          // UART 5
+#define INT_UART6_TM4C129       75          // UART 6
+#define INT_UART7_TM4C129       76          // UART 7
+#define INT_I2C2_TM4C129        77          // I2C 2
+#define INT_I2C3_TM4C129        78          // I2C 3
+#define INT_TIMER4A_TM4C129     79          // Timer 4A
+#define INT_TIMER4B_TM4C129     80          // Timer 4B
+#define INT_TIMER5A_TM4C129     81          // Timer 5A
+#define INT_TIMER5B_TM4C129     82          // Timer 5B
+#define INT_SYSEXC_TM4C129      83          // Floating-Point Exception
+                                            // (imprecise)
+#define INT_I2C4_TM4C129        86          // I2C 4
+#define INT_I2C5_TM4C129        87          // I2C 5
+#define INT_GPIOM_TM4C129       88          // GPIO Port M
+#define INT_GPION_TM4C129       89          // GPIO Port N
+#define INT_TAMPER0_TM4C129     91          // Tamper
+#define INT_GPIOP0_TM4C129      92          // GPIO Port P (Summary or P0)
+#define INT_GPIOP1_TM4C129      93          // GPIO Port P1
+#define INT_GPIOP2_TM4C129      94          // GPIO Port P2
+#define INT_GPIOP3_TM4C129      95          // GPIO Port P3
+#define INT_GPIOP4_TM4C129      96          // GPIO Port P4
+#define INT_GPIOP5_TM4C129      97          // GPIO Port P5
+#define INT_GPIOP6_TM4C129      98          // GPIO Port P6
+#define INT_GPIOP7_TM4C129      99          // GPIO Port P7
+#define INT_GPIOQ0_TM4C129      100         // GPIO Port Q (Summary or Q0)
+#define INT_GPIOQ1_TM4C129      101         // GPIO Port Q1
+#define INT_GPIOQ2_TM4C129      102         // GPIO Port Q2
+#define INT_GPIOQ3_TM4C129      103         // GPIO Port Q3
+#define INT_GPIOQ4_TM4C129      104         // GPIO Port Q4
+#define INT_GPIOQ5_TM4C129      105         // GPIO Port Q5
+#define INT_GPIOQ6_TM4C129      106         // GPIO Port Q6
+#define INT_GPIOQ7_TM4C129      107         // GPIO Port Q7
+#define INT_GPIOR_TM4C129       108         // GPIO Port R
+#define INT_GPIOS_TM4C129       109         // GPIO Port S
+#define INT_SHA0_TM4C129        110         // SHA/MD5
+#define INT_AES0_TM4C129        111         // AES
+#define INT_DES0_TM4C129        112         // DES
+#define INT_LCD0_TM4C129        113         // LCD
+#define INT_TIMER6A_TM4C129     114         // 16/32-Bit Timer 6A
+#define INT_TIMER6B_TM4C129     115         // 16/32-Bit Timer 6B
+#define INT_TIMER7A_TM4C129     116         // 16/32-Bit Timer 7A
+#define INT_TIMER7B_TM4C129     117         // 16/32-Bit Timer 7B
+#define INT_I2C6_TM4C129        118         // I2C 6
+#define INT_I2C7_TM4C129        119         // I2C 7
+#define INT_ONEWIRE0_TM4C129    121         // 1-Wire
+#define INT_I2C8_TM4C129        125         // I2C 8
+#define INT_I2C9_TM4C129        126         // I2C 9
+#define INT_GPIOT_TM4C129       127         // GPIO T
+#define NUM_INTERRUPTS_TM4C129  129
+
+//*****************************************************************************
+//
+// TM4C123 Interrupt Class Definition
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C123_RA1) || defined(TARGET_IS_TM4C123_RA2) || \
+    defined(TARGET_IS_TM4C123_RA3) || defined(TARGET_IS_TM4C123_RB0) || \
+    defined(TARGET_IS_TM4C123_RB1) || defined(PART_TM4C1230C3PM) || \
+    defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) || \
+    defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || \
+    defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231D5PZ) || \
+    defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) || \
+    defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) || \
+    defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || \
+    defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) || \
+    defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) || \
+    defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || \
+    defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PM) || \
+    defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1236D5PM) || \
+    defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) || \
+    defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || \
+    defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237E6PZ) || \
+    defined(PART_TM4C1237H6PM) || defined(PART_TM4C1237H6PZ) || \
+    defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || \
+    defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || \
+    defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || \
+    defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || \
+    defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) || \
+    defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) || \
+    defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1233H6PGE) || \
+    defined(PART_TM4C1237H6PGE) || defined(PART_TM4C123BH6PGE) || \
+    defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GH6PGE) || \
+    defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH6ZXR)
+#define INT_RESOLVE(intname, class) intname##TM4C123
+
+//*****************************************************************************
+//
+// TM4C129 Interrupt Class Definition
+//
+//*****************************************************************************
+#elif defined(TARGET_IS_TM4C129_RA0) || defined(PART_TM4C1290NCPDT) || \
+    defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT) || \
+    defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || \
+    defined(PART_TM4C1294NCPDT) || defined(PART_TM4C1294NCZAD) || \
+    defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || \
+    defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || \
+    defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) || \
+    defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || \
+    defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || \
+    defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || \
+    defined(PART_TM4C129XNCZAD)
+#define INT_RESOLVE(intname, class) intname##TM4C129
+#else
+#define INT_DEVICE_CLASS        "UNKNOWN"
+#endif
+
+//*****************************************************************************
+//
+// Macros to resolve the INT_PERIPH_CLASS name to a common INT_PERIPH name.
+//
+//*****************************************************************************
+#define INT_CONCAT(intname, class)  INT_RESOLVE(intname, class)
+
+//*****************************************************************************
+//
+// The following are defines for the interrupt assignments.
+//
+//*****************************************************************************
+#define INT_ADC0SS0             INT_CONCAT(INT_ADC0SS0_, INT_DEVICE_CLASS)
+#define INT_ADC0SS1             INT_CONCAT(INT_ADC0SS1_, INT_DEVICE_CLASS)
+#define INT_ADC0SS2             INT_CONCAT(INT_ADC0SS2_, INT_DEVICE_CLASS)
+#define INT_ADC0SS3             INT_CONCAT(INT_ADC0SS3_, INT_DEVICE_CLASS)
+#define INT_ADC1SS0             INT_CONCAT(INT_ADC1SS0_, INT_DEVICE_CLASS)
+#define INT_ADC1SS1             INT_CONCAT(INT_ADC1SS1_, INT_DEVICE_CLASS)
+#define INT_ADC1SS2             INT_CONCAT(INT_ADC1SS2_, INT_DEVICE_CLASS)
+#define INT_ADC1SS3             INT_CONCAT(INT_ADC1SS3_, INT_DEVICE_CLASS)
+#define INT_AES0                INT_CONCAT(INT_AES0_, INT_DEVICE_CLASS)
+#define INT_CAN0                INT_CONCAT(INT_CAN0_, INT_DEVICE_CLASS)
+#define INT_CAN1                INT_CONCAT(INT_CAN1_, INT_DEVICE_CLASS)
+#define INT_COMP0               INT_CONCAT(INT_COMP0_, INT_DEVICE_CLASS)
+#define INT_COMP1               INT_CONCAT(INT_COMP1_, INT_DEVICE_CLASS)
+#define INT_COMP2               INT_CONCAT(INT_COMP2_, INT_DEVICE_CLASS)
+#define INT_DES0                INT_CONCAT(INT_DES0_, INT_DEVICE_CLASS)
+#define INT_EMAC0               INT_CONCAT(INT_EMAC0_, INT_DEVICE_CLASS)
+#define INT_EPI0                INT_CONCAT(INT_EPI0_, INT_DEVICE_CLASS)
+#define INT_FLASH               INT_CONCAT(INT_FLASH_, INT_DEVICE_CLASS)
+#define INT_GPIOA               INT_CONCAT(INT_GPIOA_, INT_DEVICE_CLASS)
+#define INT_GPIOB               INT_CONCAT(INT_GPIOB_, INT_DEVICE_CLASS)
+#define INT_GPIOC               INT_CONCAT(INT_GPIOC_, INT_DEVICE_CLASS)
+#define INT_GPIOD               INT_CONCAT(INT_GPIOD_, INT_DEVICE_CLASS)
+#define INT_GPIOE               INT_CONCAT(INT_GPIOE_, INT_DEVICE_CLASS)
+#define INT_GPIOF               INT_CONCAT(INT_GPIOF_, INT_DEVICE_CLASS)
+#define INT_GPIOG               INT_CONCAT(INT_GPIOG_, INT_DEVICE_CLASS)
+#define INT_GPIOH               INT_CONCAT(INT_GPIOH_, INT_DEVICE_CLASS)
+#define INT_GPIOJ               INT_CONCAT(INT_GPIOJ_, INT_DEVICE_CLASS)
+#define INT_GPIOK               INT_CONCAT(INT_GPIOK_, INT_DEVICE_CLASS)
+#define INT_GPIOL               INT_CONCAT(INT_GPIOL_, INT_DEVICE_CLASS)
+#define INT_GPIOM               INT_CONCAT(INT_GPIOM_, INT_DEVICE_CLASS)
+#define INT_GPION               INT_CONCAT(INT_GPION_, INT_DEVICE_CLASS)
+#define INT_GPIOP0              INT_CONCAT(INT_GPIOP0_, INT_DEVICE_CLASS)
+#define INT_GPIOP1              INT_CONCAT(INT_GPIOP1_, INT_DEVICE_CLASS)
+#define INT_GPIOP2              INT_CONCAT(INT_GPIOP2_, INT_DEVICE_CLASS)
+#define INT_GPIOP3              INT_CONCAT(INT_GPIOP3_, INT_DEVICE_CLASS)
+#define INT_GPIOP4              INT_CONCAT(INT_GPIOP4_, INT_DEVICE_CLASS)
+#define INT_GPIOP5              INT_CONCAT(INT_GPIOP5_, INT_DEVICE_CLASS)
+#define INT_GPIOP6              INT_CONCAT(INT_GPIOP6_, INT_DEVICE_CLASS)
+#define INT_GPIOP7              INT_CONCAT(INT_GPIOP7_, INT_DEVICE_CLASS)
+#define INT_GPIOQ0              INT_CONCAT(INT_GPIOQ0_, INT_DEVICE_CLASS)
+#define INT_GPIOQ1              INT_CONCAT(INT_GPIOQ1_, INT_DEVICE_CLASS)
+#define INT_GPIOQ2              INT_CONCAT(INT_GPIOQ2_, INT_DEVICE_CLASS)
+#define INT_GPIOQ3              INT_CONCAT(INT_GPIOQ3_, INT_DEVICE_CLASS)
+#define INT_GPIOQ4              INT_CONCAT(INT_GPIOQ4_, INT_DEVICE_CLASS)
+#define INT_GPIOQ5              INT_CONCAT(INT_GPIOQ5_, INT_DEVICE_CLASS)
+#define INT_GPIOQ6              INT_CONCAT(INT_GPIOQ6_, INT_DEVICE_CLASS)
+#define INT_GPIOQ7              INT_CONCAT(INT_GPIOQ7_, INT_DEVICE_CLASS)
+#define INT_GPIOR               INT_CONCAT(INT_GPIOR_, INT_DEVICE_CLASS)
+#define INT_GPIOS               INT_CONCAT(INT_GPIOS_, INT_DEVICE_CLASS)
+#define INT_GPIOT               INT_CONCAT(INT_GPIOT_, INT_DEVICE_CLASS)
+#define INT_HIBERNATE           INT_CONCAT(INT_HIBERNATE_, INT_DEVICE_CLASS)
+#define INT_I2C0                INT_CONCAT(INT_I2C0_, INT_DEVICE_CLASS)
+#define INT_I2C1                INT_CONCAT(INT_I2C1_, INT_DEVICE_CLASS)
+#define INT_I2C2                INT_CONCAT(INT_I2C2_, INT_DEVICE_CLASS)
+#define INT_I2C3                INT_CONCAT(INT_I2C3_, INT_DEVICE_CLASS)
+#define INT_I2C4                INT_CONCAT(INT_I2C4_, INT_DEVICE_CLASS)
+#define INT_I2C5                INT_CONCAT(INT_I2C5_, INT_DEVICE_CLASS)
+#define INT_I2C6                INT_CONCAT(INT_I2C6_, INT_DEVICE_CLASS)
+#define INT_I2C7                INT_CONCAT(INT_I2C7_, INT_DEVICE_CLASS)
+#define INT_I2C8                INT_CONCAT(INT_I2C8_, INT_DEVICE_CLASS)
+#define INT_I2C9                INT_CONCAT(INT_I2C9_, INT_DEVICE_CLASS)
+#define INT_LCD0                INT_CONCAT(INT_LCD0_, INT_DEVICE_CLASS)
+#define INT_ONEWIRE0            INT_CONCAT(INT_ONEWIRE0_, INT_DEVICE_CLASS)
+#define INT_PWM0_0              INT_CONCAT(INT_PWM0_0_, INT_DEVICE_CLASS)
+#define INT_PWM0_1              INT_CONCAT(INT_PWM0_1_, INT_DEVICE_CLASS)
+#define INT_PWM0_2              INT_CONCAT(INT_PWM0_2_, INT_DEVICE_CLASS)
+#define INT_PWM0_3              INT_CONCAT(INT_PWM0_3_, INT_DEVICE_CLASS)
+#define INT_PWM0_FAULT          INT_CONCAT(INT_PWM0_FAULT_, INT_DEVICE_CLASS)
+#define INT_PWM1_0              INT_CONCAT(INT_PWM1_0_, INT_DEVICE_CLASS)
+#define INT_PWM1_1              INT_CONCAT(INT_PWM1_1_, INT_DEVICE_CLASS)
+#define INT_PWM1_2              INT_CONCAT(INT_PWM1_2_, INT_DEVICE_CLASS)
+#define INT_PWM1_3              INT_CONCAT(INT_PWM1_3_, INT_DEVICE_CLASS)
+#define INT_PWM1_FAULT          INT_CONCAT(INT_PWM1_FAULT_, INT_DEVICE_CLASS)
+#define INT_QEI0                INT_CONCAT(INT_QEI0_, INT_DEVICE_CLASS)
+#define INT_QEI1                INT_CONCAT(INT_QEI1_, INT_DEVICE_CLASS)
+#define INT_SHA0                INT_CONCAT(INT_SHA0_, INT_DEVICE_CLASS)
+#define INT_SSI0                INT_CONCAT(INT_SSI0_, INT_DEVICE_CLASS)
+#define INT_SSI1                INT_CONCAT(INT_SSI1_, INT_DEVICE_CLASS)
+#define INT_SSI2                INT_CONCAT(INT_SSI2_, INT_DEVICE_CLASS)
+#define INT_SSI3                INT_CONCAT(INT_SSI3_, INT_DEVICE_CLASS)
+#define INT_SYSCTL              INT_CONCAT(INT_SYSCTL_, INT_DEVICE_CLASS)
+#define INT_SYSEXC              INT_CONCAT(INT_SYSEXC_, INT_DEVICE_CLASS)
+#define INT_TAMPER0             INT_CONCAT(INT_TAMPER0_, INT_DEVICE_CLASS)
+#define INT_TIMER0A             INT_CONCAT(INT_TIMER0A_, INT_DEVICE_CLASS)
+#define INT_TIMER0B             INT_CONCAT(INT_TIMER0B_, INT_DEVICE_CLASS)
+#define INT_TIMER1A             INT_CONCAT(INT_TIMER1A_, INT_DEVICE_CLASS)
+#define INT_TIMER1B             INT_CONCAT(INT_TIMER1B_, INT_DEVICE_CLASS)
+#define INT_TIMER2A             INT_CONCAT(INT_TIMER2A_, INT_DEVICE_CLASS)
+#define INT_TIMER2B             INT_CONCAT(INT_TIMER2B_, INT_DEVICE_CLASS)
+#define INT_TIMER3A             INT_CONCAT(INT_TIMER3A_, INT_DEVICE_CLASS)
+#define INT_TIMER3B             INT_CONCAT(INT_TIMER3B_, INT_DEVICE_CLASS)
+#define INT_TIMER4A             INT_CONCAT(INT_TIMER4A_, INT_DEVICE_CLASS)
+#define INT_TIMER4B             INT_CONCAT(INT_TIMER4B_, INT_DEVICE_CLASS)
+#define INT_TIMER5A             INT_CONCAT(INT_TIMER5A_, INT_DEVICE_CLASS)
+#define INT_TIMER5B             INT_CONCAT(INT_TIMER5B_, INT_DEVICE_CLASS)
+#define INT_TIMER6A             INT_CONCAT(INT_TIMER6A_, INT_DEVICE_CLASS)
+#define INT_TIMER6B             INT_CONCAT(INT_TIMER6B_, INT_DEVICE_CLASS)
+#define INT_TIMER7A             INT_CONCAT(INT_TIMER7A_, INT_DEVICE_CLASS)
+#define INT_TIMER7B             INT_CONCAT(INT_TIMER7B_, INT_DEVICE_CLASS)
+#define INT_UART0               INT_CONCAT(INT_UART0_, INT_DEVICE_CLASS)
+#define INT_UART1               INT_CONCAT(INT_UART1_, INT_DEVICE_CLASS)
+#define INT_UART2               INT_CONCAT(INT_UART2_, INT_DEVICE_CLASS)
+#define INT_UART3               INT_CONCAT(INT_UART3_, INT_DEVICE_CLASS)
+#define INT_UART4               INT_CONCAT(INT_UART4_, INT_DEVICE_CLASS)
+#define INT_UART5               INT_CONCAT(INT_UART5_, INT_DEVICE_CLASS)
+#define INT_UART6               INT_CONCAT(INT_UART6_, INT_DEVICE_CLASS)
+#define INT_UART7               INT_CONCAT(INT_UART7_, INT_DEVICE_CLASS)
+#define INT_UDMA                INT_CONCAT(INT_UDMA_, INT_DEVICE_CLASS)
+#define INT_UDMAERR             INT_CONCAT(INT_UDMAERR_, INT_DEVICE_CLASS)
+#define INT_USB0                INT_CONCAT(INT_USB0_, INT_DEVICE_CLASS)
+#define INT_WATCHDOG            INT_CONCAT(INT_WATCHDOG_, INT_DEVICE_CLASS)
+#define INT_WTIMER0A            INT_CONCAT(INT_WTIMER0A_, INT_DEVICE_CLASS)
+#define INT_WTIMER0B            INT_CONCAT(INT_WTIMER0B_, INT_DEVICE_CLASS)
+#define INT_WTIMER1A            INT_CONCAT(INT_WTIMER1A_, INT_DEVICE_CLASS)
+#define INT_WTIMER1B            INT_CONCAT(INT_WTIMER1B_, INT_DEVICE_CLASS)
+#define INT_WTIMER2A            INT_CONCAT(INT_WTIMER2A_, INT_DEVICE_CLASS)
+#define INT_WTIMER2B            INT_CONCAT(INT_WTIMER2B_, INT_DEVICE_CLASS)
+#define INT_WTIMER3A            INT_CONCAT(INT_WTIMER3A_, INT_DEVICE_CLASS)
+#define INT_WTIMER3B            INT_CONCAT(INT_WTIMER3B_, INT_DEVICE_CLASS)
+#define INT_WTIMER4A            INT_CONCAT(INT_WTIMER4A_, INT_DEVICE_CLASS)
+#define INT_WTIMER4B            INT_CONCAT(INT_WTIMER4B_, INT_DEVICE_CLASS)
+#define INT_WTIMER5A            INT_CONCAT(INT_WTIMER5A_, INT_DEVICE_CLASS)
+#define INT_WTIMER5B            INT_CONCAT(INT_WTIMER5B_, INT_DEVICE_CLASS)
+
+//*****************************************************************************
+//
+// The following are defines for the total number of interrupts.
+//
+//*****************************************************************************
+#define NUM_INTERRUPTS          INT_CONCAT(NUM_INTERRUPTS_, INT_DEVICE_CLASS)
+
+//*****************************************************************************
+//
+// The following are defines for the total number of priority levels.
+//
+//*****************************************************************************
+#define NUM_PRIORITY            8
+#define NUM_PRIORITY_BITS       3
+
+#endif // __HW_INTS_H__
diff --git a/os/common/ext/TivaWare/inc/hw_lcd.h b/os/common/ext/TivaWare/inc/hw_lcd.h
new file mode 100644
index 0000000..f8711be
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_lcd.h
@@ -0,0 +1,575 @@
+//*****************************************************************************
+//
+// hw_lcd.h - Defines and macros used when accessing the LCD controller.
+//
+// Copyright (c) 2011-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_LCD_H__
+#define __HW_LCD_H__
+
+//*****************************************************************************
+//
+// The following are defines for the LCD register offsets.
+//
+//*****************************************************************************
+#define LCD_O_PID               0x00000000  // LCD PID Register Format
+#define LCD_O_CTL               0x00000004  // LCD Control
+#define LCD_O_LIDDCTL           0x0000000C  // LCD LIDD Control
+#define LCD_O_LIDDCS0CFG        0x00000010  // LCD LIDD CS0 Configuration
+#define LCD_O_LIDDCS0ADDR       0x00000014  // LIDD CS0 Read/Write Address
+#define LCD_O_LIDDCS0DATA       0x00000018  // LIDD CS0 Data Read/Write
+                                            // Initiation
+#define LCD_O_LIDDCS1CFG        0x0000001C  // LIDD CS1 Configuration
+#define LCD_O_LIDDCS1ADDR       0x00000020  // LIDD CS1 Address Read/Write
+                                            // Initiation
+#define LCD_O_LIDDCS1DATA       0x00000024  // LIDD CS1 Data Read/Write
+                                            // Initiation
+#define LCD_O_RASTRCTL          0x00000028  // LCD Raster Control
+#define LCD_O_RASTRTIM0         0x0000002C  // LCD Raster Timing 0
+#define LCD_O_RASTRTIM1         0x00000030  // LCD Raster Timing 1
+#define LCD_O_RASTRTIM2         0x00000034  // LCD Raster Timing 2
+#define LCD_O_RASTRSUBP1        0x00000038  // LCD Raster Subpanel Display 1
+#define LCD_O_RASTRSUBP2        0x0000003C  // LCD Raster Subpanel Display 2
+#define LCD_O_DMACTL            0x00000040  // LCD DMA Control
+#define LCD_O_DMABAFB0          0x00000044  // LCD DMA Frame Buffer 0 Base
+                                            // Address
+#define LCD_O_DMACAFB0          0x00000048  // LCD DMA Frame Buffer 0 Ceiling
+                                            // Address
+#define LCD_O_DMABAFB1          0x0000004C  // LCD DMA Frame Buffer 1 Base
+                                            // Address
+#define LCD_O_DMACAFB1          0x00000050  // LCD DMA Frame Buffer 1 Ceiling
+                                            // Address
+#define LCD_O_SYSCFG            0x00000054  // LCD System Configuration
+                                            // Register
+#define LCD_O_RISSET            0x00000058  // LCD Interrupt Raw Status and Set
+                                            // Register
+#define LCD_O_MISCLR            0x0000005C  // LCD Interrupt Status and Clear
+#define LCD_O_IM                0x00000060  // LCD Interrupt Mask
+#define LCD_O_IENC              0x00000064  // LCD Interrupt Enable Clear
+#define LCD_O_CLKEN             0x0000006C  // LCD Clock Enable
+#define LCD_O_CLKRESET          0x00000070  // LCD Clock Resets
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_PID register.
+//
+//*****************************************************************************
+#define LCD_PID_MAJOR_M         0x00000700  // Major Release Number
+#define LCD_PID_MINOR_M         0x0000003F  // Minor Release Number
+#define LCD_PID_MAJOR_S         8
+#define LCD_PID_MINOR_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_CTL register.
+//
+//*****************************************************************************
+#define LCD_CTL_CLKDIV_M        0x0000FF00  // Clock Divisor
+#define LCD_CTL_UFLOWRST        0x00000002  // Underflow Restart
+#define LCD_CTL_LCDMODE         0x00000001  // LCD Mode Select
+#define LCD_CTL_CLKDIV_S        8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_LIDDCTL register.
+//
+//*****************************************************************************
+#define LCD_LIDDCTL_DMACS       0x00000200  // CS0/CS1 Select for LIDD DMA
+                                            // Writes
+#define LCD_LIDDCTL_DMAEN       0x00000100  // LIDD DMA Enable
+#define LCD_LIDDCTL_CS1E1       0x00000080  // Chip Select 1 (CS1)/Enable 1(E1)
+                                            // Polarity Control
+#define LCD_LIDDCTL_CS0E0       0x00000040  // Chip Select 0 (CS0)/Enable 0
+                                            // (E0) Polarity Control
+#define LCD_LIDDCTL_WRDIRINV    0x00000020  // Write Strobe (WR) /Direction
+                                            // (DIR) Polarity Control
+#define LCD_LIDDCTL_RDEN        0x00000010  // Read Strobe (RD) /Direct Enable
+                                            // (EN) Polarity Control
+#define LCD_LIDDCTL_ALE         0x00000008  // Address Latch Enable (ALE)
+                                            // Polarity Control
+#define LCD_LIDDCTL_MODE_M      0x00000007  // LIDD Mode Select
+#define LCD_LIDDCTL_MODE_SYNCM68                                              \
+                                0x00000000  // Synchronous Motorola 6800 Mode
+#define LCD_LIDDCTL_MODE_ASYNCM68                                             \
+                                0x00000001  // Asynchronous Motorola 6800 Mode
+#define LCD_LIDDCTL_MODE_SYNCM80                                              \
+                                0x00000002  // Synchronous Intel 8080 mode
+#define LCD_LIDDCTL_MODE_ASYNCM80                                             \
+                                0x00000003  // Asynchronous Intel 8080 mode
+#define LCD_LIDDCTL_MODE_ASYNCHIT                                             \
+                                0x00000004  // Asynchronous Hitachi mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_LIDDCS0CFG
+// register.
+//
+//*****************************************************************************
+#define LCD_LIDDCS0CFG_WRSU_M   0xF8000000  // Write Strobe (WR) Set-Up Cycles
+#define LCD_LIDDCS0CFG_WRDUR_M  0x07E00000  // Write Strobe (WR) Duration
+                                            // Cycles
+#define LCD_LIDDCS0CFG_WRHOLD_M 0x001E0000  // Write Strobe (WR) Hold cycles
+#define LCD_LIDDCS0CFG_RDSU_M   0x0001F000  // Read Strobe (RD) Set-Up cycles
+#define LCD_LIDDCS0CFG_RDDUR_M  0x00000FC0  // Read Strobe (RD) Duration cycles
+#define LCD_LIDDCS0CFG_RDHOLD_M 0x0000003C  // Read Strobe (RD) Hold cycles
+#define LCD_LIDDCS0CFG_GAP_M    0x00000003  // Field value defines the number
+                                            // of LCDMCLK cycles (GAP +1)
+                                            // between the end of one CS0
+                                            // (LCDAC) device access and the
+                                            // start of another CS0 (LCDAC)
+                                            // device access unless the two
+                                            // accesses are both reads
+#define LCD_LIDDCS0CFG_WRSU_S   27
+#define LCD_LIDDCS0CFG_WRDUR_S  21
+#define LCD_LIDDCS0CFG_WRHOLD_S 17
+#define LCD_LIDDCS0CFG_RDSU_S   12
+#define LCD_LIDDCS0CFG_RDDUR_S  6
+#define LCD_LIDDCS0CFG_RDHOLD_S 2
+#define LCD_LIDDCS0CFG_GAP_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_LIDDCS0ADDR
+// register.
+//
+//*****************************************************************************
+#define LCD_LIDDCS0ADDR_CS0ADDR_M                                             \
+                                0x0000FFFF  // LCD Address
+#define LCD_LIDDCS0ADDR_CS0ADDR_S                                             \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_LIDDCS0DATA
+// register.
+//
+//*****************************************************************************
+#define LCD_LIDDCS0DATA_CS0DATA_M                                             \
+                                0x0000FFFF  // LCD Data Read/Write
+#define LCD_LIDDCS0DATA_CS0DATA_S                                             \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_LIDDCS1CFG
+// register.
+//
+//*****************************************************************************
+#define LCD_LIDDCS1CFG_WRSU_M   0xF8000000  // Write Strobe (WR) Set-Up Cycles
+#define LCD_LIDDCS1CFG_WRDUR_M  0x07E00000  // Write Strobe (WR) Duration
+                                            // Cycles
+#define LCD_LIDDCS1CFG_WRHOLD_M 0x001E0000  // Write Strobe (WR) Hold cycles
+#define LCD_LIDDCS1CFG_RDSU_M   0x0001F000  // Read Strobe (RD) Set-Up cycles
+#define LCD_LIDDCS1CFG_RDDUR_M  0x00000FC0  // Read Strobe (RD) Duration cycles
+#define LCD_LIDDCS1CFG_RDHOLD_M 0x0000003C  // Read Strobe (RD) Hold cycles
+#define LCD_LIDDCS1CFG_GAP_M    0x00000003  // Field value defines the number
+                                            // of LCDMCLK cycles (GAP + 1)
+                                            // between the end of one CS1
+                                            // (LCDAC) device access and the
+                                            // start of another CS0 (LCDAC)
+                                            // device access unless the two
+                                            // accesses are both reads
+#define LCD_LIDDCS1CFG_WRSU_S   27
+#define LCD_LIDDCS1CFG_WRDUR_S  21
+#define LCD_LIDDCS1CFG_WRHOLD_S 17
+#define LCD_LIDDCS1CFG_RDSU_S   12
+#define LCD_LIDDCS1CFG_RDDUR_S  6
+#define LCD_LIDDCS1CFG_RDHOLD_S 2
+#define LCD_LIDDCS1CFG_GAP_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_LIDDCS1ADDR
+// register.
+//
+//*****************************************************************************
+#define LCD_LIDDCS1ADDR_CS1ADDR_M                                             \
+                                0x0000FFFF  // LCD Address Bus
+#define LCD_LIDDCS1ADDR_CS1ADDR_S                                             \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_LIDDCS1DATA
+// register.
+//
+//*****************************************************************************
+#define LCD_LIDDCS1DATA_CS0DATA_M                                             \
+                                0x0000FFFF  // LCD Data Read/Write Initiation
+#define LCD_LIDDCS1DATA_CS0DATA_S                                             \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_RASTRCTL register.
+//
+//*****************************************************************************
+#define LCD_RASTRCTL_TFT24UPCK  0x04000000  // 24-bit TFT Mode Packing
+#define LCD_RASTRCTL_TFT24      0x02000000  // 24-Bit TFT Mode
+#define LCD_RASTRCTL_FRMBUFSZ   0x01000000  // Frame Buffer Select
+#define LCD_RASTRCTL_TFTMAP     0x00800000  // TFT Mode Alternate Signal
+                                            // Mapping for Palettized
+                                            // Framebuffer
+#define LCD_RASTRCTL_NIBMODE    0x00400000  // Nibble Mode
+#define LCD_RASTRCTL_PALMODE_M  0x00300000  // Pallette Loading Mode
+#define LCD_RASTRCTL_PALMODE_PALDAT                                           \
+                                0x00000000  // Palette and data loading, reset
+                                            // value
+#define LCD_RASTRCTL_PALMODE_PAL                                              \
+                                0x00100000  // Palette loading only
+#define LCD_RASTRCTL_PALMODE_DAT                                              \
+                                0x00200000  // Data loading only
+#define LCD_RASTRCTL_REQDLY_M   0x000FF000  // Palette Loading Delay
+#define LCD_RASTRCTL_MONO8B     0x00000200  // Mono 8-Bit
+#define LCD_RASTRCTL_RDORDER    0x00000100  // Raster Data Order Select
+#define LCD_RASTRCTL_LCDTFT     0x00000080  // LCD TFT
+#define LCD_RASTRCTL_LCDBW      0x00000002  // LCD Monochrome
+#define LCD_RASTRCTL_LCDEN      0x00000001  // LCD Controller Enable for Raster
+                                            // Operations
+#define LCD_RASTRCTL_REQDLY_S   12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_RASTRTIM0
+// register.
+//
+//*****************************************************************************
+#define LCD_RASTRTIM0_HBP_M     0xFF000000  // Horizontal Back Porch Lowbits
+#define LCD_RASTRTIM0_HFP_M     0x00FF0000  // Horizontal Front Porch Lowbits
+#define LCD_RASTRTIM0_HSW_M     0x0000FC00  // Horizontal Sync Pulse Width
+                                            // Lowbits
+#define LCD_RASTRTIM0_PPL_M     0x000003F0  // Pixels-per-line LSB[9:4]
+#define LCD_RASTRTIM0_MSBPPL    0x00000008  // Pixels-per-line MSB[10]
+#define LCD_RASTRTIM0_HBP_S     24
+#define LCD_RASTRTIM0_HFP_S     16
+#define LCD_RASTRTIM0_HSW_S     10
+#define LCD_RASTRTIM0_PPL_S     4
+#define LCD_RASTRTIM0_MSBPPL_S  3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_RASTRTIM1
+// register.
+//
+//*****************************************************************************
+#define LCD_RASTRTIM1_VBP_M     0xFF000000  // Vertical Back Porch
+#define LCD_RASTRTIM1_VFP_M     0x00FF0000  // Vertical Front Porch
+#define LCD_RASTRTIM1_VSW_M     0x0000FC00  // Vertical Sync Width Pulse
+#define LCD_RASTRTIM1_LPP_M     0x000003FF  // Lines Per Panel
+#define LCD_RASTRTIM1_VBP_S     24
+#define LCD_RASTRTIM1_VFP_S     16
+#define LCD_RASTRTIM1_VSW_S     10
+#define LCD_RASTRTIM1_LPP_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_RASTRTIM2
+// register.
+//
+//*****************************************************************************
+#define LCD_RASTRTIM2_HSW_M     0x78000000  // Bits 9:6 of the horizontal sync
+                                            // width field
+#define LCD_RASTRTIM2_MSBLPP    0x04000000  // MSB of Lines Per Panel
+#define LCD_RASTRTIM2_PXLCLKCTL 0x02000000  // Hsync/Vsync Pixel Clock Control
+                                            // On/Off
+#define LCD_RASTRTIM2_PSYNCRF   0x01000000  // Program HSYNC/VSYNC Rise or Fall
+#define LCD_RASTRTIM2_INVOE     0x00800000  // Invert Output Enable
+#define LCD_RASTRTIM2_INVPXLCLK 0x00400000  // Invert Pixel Clock
+#define LCD_RASTRTIM2_IHS       0x00200000  // Invert Hysync
+#define LCD_RASTRTIM2_IVS       0x00100000  // Invert Vsync
+#define LCD_RASTRTIM2_ACBI_M    0x000F0000  // AC Bias Pins Transitions per
+                                            // Interrupt
+#define LCD_RASTRTIM2_ACBF_M    0x0000FF00  // AC Bias Pin Frequency
+#define LCD_RASTRTIM2_MSBHBP_M  0x00000030  // Bits 9:8 of the horizontal back
+                                            // porch field
+#define LCD_RASTRTIM2_MSBHFP_M  0x00000003  // Bits 9:8 of the horizontal front
+                                            // porch field
+#define LCD_RASTRTIM2_HSW_S     27
+#define LCD_RASTRTIM2_MSBLPP_S  26
+#define LCD_RASTRTIM2_ACBI_S    16
+#define LCD_RASTRTIM2_ACBF_S    8
+#define LCD_RASTRTIM2_MSBHBP_S  4
+#define LCD_RASTRTIM2_MSBHFP_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_RASTRSUBP1
+// register.
+//
+//*****************************************************************************
+#define LCD_RASTRSUBP1_SPEN     0x80000000  // Sub Panel Enable
+#define LCD_RASTRSUBP1_HOLS     0x20000000  // High or Low Signal
+#define LCD_RASTRSUBP1_LPPT_M   0x03FF0000  // Line Per Panel Threshold
+#define LCD_RASTRSUBP1_DPDLSB_M 0x0000FFFF  // Default Pixel Data LSB[15:0]
+#define LCD_RASTRSUBP1_LPPT_S   16
+#define LCD_RASTRSUBP1_DPDLSB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_RASTRSUBP2
+// register.
+//
+//*****************************************************************************
+#define LCD_RASTRSUBP2_LPPTMSB  0x00000100  // Lines Per Panel Threshold Bit 10
+#define LCD_RASTRSUBP2_DPDMSB_M 0x000000FF  // Default Pixel Data MSB [23:16]
+#define LCD_RASTRSUBP2_DPDMSB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_DMACTL register.
+//
+//*****************************************************************************
+#define LCD_DMACTL_FIFORDY_M    0x00000700  // DMA FIFO threshold
+#define LCD_DMACTL_FIFORDY_8    0x00000000  // 8 words
+#define LCD_DMACTL_FIFORDY_16   0x00000100  // 16 words
+#define LCD_DMACTL_FIFORDY_32   0x00000200  // 32 words
+#define LCD_DMACTL_FIFORDY_64   0x00000300  // 64 words
+#define LCD_DMACTL_FIFORDY_128  0x00000400  // 128 words
+#define LCD_DMACTL_FIFORDY_256  0x00000500  // 256 words
+#define LCD_DMACTL_FIFORDY_512  0x00000600  // 512 words
+#define LCD_DMACTL_BURSTSZ_M    0x00000070  // Burst Size setting for DMA
+                                            // transfers (all DMA transfers are
+                                            // 32 bits wide):
+#define LCD_DMACTL_BURSTSZ_4    0x00000020  // burst size of 4
+#define LCD_DMACTL_BURSTSZ_8    0x00000030  // burst size of 8
+#define LCD_DMACTL_BURSTSZ_16   0x00000040  // burst size of 16
+#define LCD_DMACTL_BYTESWAP     0x00000008  // This bit controls the bytelane
+                                            // ordering of the data on the
+                                            // output of the DMA module
+#define LCD_DMACTL_BIGDEND      0x00000002  // Big Endian Enable
+#define LCD_DMACTL_FMODE        0x00000001  // Frame Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_DMABAFB0 register.
+//
+//*****************************************************************************
+#define LCD_DMABAFB0_FB0BA_M    0xFFFFFFFC  // Frame Buffer 0 Base Address
+                                            // pointer
+#define LCD_DMABAFB0_FB0BA_S    2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_DMACAFB0 register.
+//
+//*****************************************************************************
+#define LCD_DMACAFB0_FB0CA_M    0xFFFFFFFC  // Frame Buffer 0 Ceiling Address
+                                            // pointer
+#define LCD_DMACAFB0_FB0CA_S    2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_DMABAFB1 register.
+//
+//*****************************************************************************
+#define LCD_DMABAFB1_FB1BA_M    0xFFFFFFFC  // Frame Buffer 1 Base Address
+                                            // pointer
+#define LCD_DMABAFB1_FB1BA_S    2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_DMACAFB1 register.
+//
+//*****************************************************************************
+#define LCD_DMACAFB1_FB1CA_M    0xFFFFFFFC  // Frame Buffer 1 Ceiling Address
+                                            // pointer
+#define LCD_DMACAFB1_FB1CA_S    2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_SYSCFG register.
+//
+//*****************************************************************************
+#define LCD_SYSCFG_STDBY_M      0x00000030  // Standby Mode
+#define LCD_SYSCFG_STDBY_FORCE  0x00000000  // Force-standby mode: local
+                                            // initiator is unconditionally
+                                            // placed in standby state. Backup
+                                            // mode, for debug only
+#define LCD_SYSCFG_STDBY_NONE   0x00000010  // No-standby mode: local initiator
+                                            // is unconditionally placed out of
+                                            // standby state. Backup mode, for
+                                            // debug only
+#define LCD_SYSCFG_STDBY_SMART  0x00000020  // Smart-standby mode: local
+                                            // initiator standby status depends
+                                            // on local conditions, that is,
+                                            // the module's functional
+                                            // requirement from the initiator.
+                                            // IP module shall not generate
+                                            // (initiator-related) wakeup
+                                            // events
+#define LCD_SYSCFG_IDLEMODE_M   0x0000000C  // Idle Mode
+#define LCD_SYSCFG_IDLEMODE_FORCE                                             \
+                                0x00000000  // Force-idle mode: local target's
+                                            // idle state follows
+                                            // (acknowledges) the system's idle
+                                            // requests unconditionally, that
+                                            // is, regardless of the IP
+                                            // module's internal requirements.
+                                            // Backup mode, for debug only
+#define LCD_SYSCFG_IDLEMODE_NONE                                              \
+                                0x00000004  // No-idle mode: local target never
+                                            // enters idle state. Backup mode,
+                                            // for debug only
+#define LCD_SYSCFG_IDLEMODE_SMART                                             \
+                                0x00000008  // Smart-idle mode: local target's
+                                            // idle state eventually follows
+                                            // (acknowledges) the system's idle
+                                            // requests, depending on the IP
+                                            // module's internal requirements.
+                                            // IP module shall not generate
+                                            // (IRQ- or DMA-requestrelated)
+                                            // wakeup events
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_RISSET register.
+//
+//*****************************************************************************
+#define LCD_RISSET_EOF1         0x00000200  // DMA End-of-Frame 1 Raw Interrupt
+                                            // Status and Set
+#define LCD_RISSET_EOF0         0x00000100  // DMA End-of-Frame 0 Raw Interrupt
+                                            // Status and Set
+#define LCD_RISSET_PALLOAD      0x00000040  // DMA Palette Loaded Raw Interrupt
+                                            // Status and Set
+#define LCD_RISSET_FIFOU        0x00000020  // DMA FIFO Underflow Raw Interrupt
+                                            // Status and Set
+#define LCD_RISSET_ACBS         0x00000008  // AC Bias Count Raw Interrupt
+                                            // Status and Set
+#define LCD_RISSET_SYNCS        0x00000004  // Frame Synchronization Lost Raw
+                                            // Interrupt Status and Set
+#define LCD_RISSET_RRASTRDONE   0x00000002  // Raster Mode Frame Done interrupt
+#define LCD_RISSET_DONE         0x00000001  // Raster or LIDD Frame Done
+                                            // (shared, depends on whether
+                                            // Raster or LIDD mode enabled) Raw
+                                            // Interrupt Status and Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_MISCLR register.
+//
+//*****************************************************************************
+#define LCD_MISCLR_EOF1         0x00000200  // DMA End-of-Frame 1 Enabled
+                                            // Interrupt and Clear
+#define LCD_MISCLR_EOF0         0x00000100  // DMA End-of-Frame 0 Raw Interrupt
+                                            // and Clear
+#define LCD_MISCLR_PALLOAD      0x00000040  // DMA Palette Loaded Enabled
+                                            // Interrupt and Clear
+#define LCD_MISCLR_FIFOU        0x00000020  // DMA FIFO Underflow Enabled
+                                            // Interrupt and Clear
+#define LCD_MISCLR_ACBS         0x00000008  // AC Bias Count Enabled Interrupt
+                                            // and Clear
+#define LCD_MISCLR_SYNCS        0x00000004  // Frame Synchronization Lost
+                                            // Enabled Interrupt and Clear
+#define LCD_MISCLR_RRASTRDONE   0x00000002  // Raster Mode Frame Done interrupt
+#define LCD_MISCLR_DONE         0x00000001  // Raster or LIDD Frame Done
+                                            // (shared, depends on whether
+                                            // Raster or LIDD mode enabled)
+                                            // Enabled Interrupt and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_IM register.
+//
+//*****************************************************************************
+#define LCD_IM_EOF1             0x00000200  // DMA End-of-Frame 1 Interrupt
+                                            // Enable Set
+#define LCD_IM_EOF0             0x00000100  // DMA End-of-Frame 0 Interrupt
+                                            // Enable Set
+#define LCD_IM_PALLOAD          0x00000040  // DMA Palette Loaded Interrupt
+                                            // Enable Set
+#define LCD_IM_FIFOU            0x00000020  // DMA FIFO Underflow Interrupt
+                                            // Enable Set
+#define LCD_IM_ACBS             0x00000008  // AC Bias Count Interrupt Enable
+                                            // Set
+#define LCD_IM_SYNCS            0x00000004  // Frame Synchronization Lost
+                                            // Interrupt Enable Set
+#define LCD_IM_RRASTRDONE       0x00000002  // Raster Mode Frame Done Interrupt
+                                            // Enable Set
+#define LCD_IM_DONE             0x00000001  // Raster or LIDD Frame Done
+                                            // (shared, depends on whether
+                                            // Raster or LIDD mode enabled)
+                                            // Interrupt Enable Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_IENC register.
+//
+//*****************************************************************************
+#define LCD_IENC_EOF1           0x00000200  // DMA End-of-Frame 1 Interrupt
+                                            // Enable Clear
+#define LCD_IENC_EOF0           0x00000100  // DMA End-of-Frame 0 Interrupt
+                                            // Enable Clear
+#define LCD_IENC_PALLOAD        0x00000040  // DMA Palette Loaded Interrupt
+                                            // Enable Clear
+#define LCD_IENC_FIFOU          0x00000020  // DMA FIFO Underflow Interrupt
+                                            // Enable Clear
+#define LCD_IENC_ACBS           0x00000008  // AC Bias Count Interrupt Enable
+                                            // Clear
+#define LCD_IENC_SYNCS          0x00000004  // Frame Synchronization Lost
+                                            // Interrupt Enable Clear
+#define LCD_IENC_RRASTRDONE     0x00000002  // Raster Mode Frame Done Interrupt
+                                            // Enable Clear
+#define LCD_IENC_DONE           0x00000001  // Raster or LIDD Frame Done
+                                            // (shared, depends on whether
+                                            // Raster or LIDD mode enabled)
+                                            // Interrupt Enable Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_CLKEN register.
+//
+//*****************************************************************************
+#define LCD_CLKEN_DMA           0x00000004  // DMA Clock Enable
+#define LCD_CLKEN_LIDD          0x00000002  // LIDD Submodule Clock Enable
+#define LCD_CLKEN_CORE          0x00000001  // LCD Core Clock Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_CLKRESET register.
+//
+//*****************************************************************************
+#define LCD_CLKRESET_MAIN       0x00000008  // Software Reset for the entire
+                                            // LCD module
+#define LCD_CLKRESET_DMA        0x00000004  // Software Reset for the DMA
+                                            // submodule
+#define LCD_CLKRESET_LIDD       0x00000002  // Software Reset for the LIDD
+                                            // submodule (character displays)
+#define LCD_CLKRESET_CORE       0x00000001  // Software Reset for the Core,
+                                            // which encompasses the Raster
+                                            // Active Matrix and Passive Matrix
+                                            // logic
+
+#endif // __HW_LCD_H__
diff --git a/os/common/ext/TivaWare/inc/hw_memmap.h b/os/common/ext/TivaWare/inc/hw_memmap.h
new file mode 100644
index 0000000..dafd4f7
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_memmap.h
@@ -0,0 +1,151 @@
+//*****************************************************************************
+//
+// hw_memmap.h - Macros defining the memory map of the device.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_MEMMAP_H__
+#define __HW_MEMMAP_H__
+
+//*****************************************************************************
+//
+// The following are defines for the base address of the memories and
+// peripherals.
+//
+//*****************************************************************************
+#define FLASH_BASE              0x00000000  // FLASH memory
+#define SRAM_BASE               0x20000000  // SRAM memory
+#define WATCHDOG0_BASE          0x40000000  // Watchdog0
+#define WATCHDOG1_BASE          0x40001000  // Watchdog1
+#define GPIO_PORTA_BASE         0x40004000  // GPIO Port A
+#define GPIO_PORTB_BASE         0x40005000  // GPIO Port B
+#define GPIO_PORTC_BASE         0x40006000  // GPIO Port C
+#define GPIO_PORTD_BASE         0x40007000  // GPIO Port D
+#define SSI0_BASE               0x40008000  // SSI0
+#define SSI1_BASE               0x40009000  // SSI1
+#define SSI2_BASE               0x4000A000  // SSI2
+#define SSI3_BASE               0x4000B000  // SSI3
+#define UART0_BASE              0x4000C000  // UART0
+#define UART1_BASE              0x4000D000  // UART1
+#define UART2_BASE              0x4000E000  // UART2
+#define UART3_BASE              0x4000F000  // UART3
+#define UART4_BASE              0x40010000  // UART4
+#define UART5_BASE              0x40011000  // UART5
+#define UART6_BASE              0x40012000  // UART6
+#define UART7_BASE              0x40013000  // UART7
+#define I2C0_BASE               0x40020000  // I2C0
+#define I2C1_BASE               0x40021000  // I2C1
+#define I2C2_BASE               0x40022000  // I2C2
+#define I2C3_BASE               0x40023000  // I2C3
+#define GPIO_PORTE_BASE         0x40024000  // GPIO Port E
+#define GPIO_PORTF_BASE         0x40025000  // GPIO Port F
+#define GPIO_PORTG_BASE         0x40026000  // GPIO Port G
+#define GPIO_PORTH_BASE         0x40027000  // GPIO Port H
+#define PWM0_BASE               0x40028000  // Pulse Width Modulator (PWM)
+#define PWM1_BASE               0x40029000  // Pulse Width Modulator (PWM)
+#define QEI0_BASE               0x4002C000  // QEI0
+#define QEI1_BASE               0x4002D000  // QEI1
+#define TIMER0_BASE             0x40030000  // Timer0
+#define TIMER1_BASE             0x40031000  // Timer1
+#define TIMER2_BASE             0x40032000  // Timer2
+#define TIMER3_BASE             0x40033000  // Timer3
+#define TIMER4_BASE             0x40034000  // Timer4
+#define TIMER5_BASE             0x40035000  // Timer5
+#define WTIMER0_BASE            0x40036000  // Wide Timer0
+#define WTIMER1_BASE            0x40037000  // Wide Timer1
+#define ADC0_BASE               0x40038000  // ADC0
+#define ADC1_BASE               0x40039000  // ADC1
+#define COMP_BASE               0x4003C000  // Analog comparators
+#define GPIO_PORTJ_BASE         0x4003D000  // GPIO Port J
+#define CAN0_BASE               0x40040000  // CAN0
+#define CAN1_BASE               0x40041000  // CAN1
+#define WTIMER2_BASE            0x4004C000  // Wide Timer2
+#define WTIMER3_BASE            0x4004D000  // Wide Timer3
+#define WTIMER4_BASE            0x4004E000  // Wide Timer4
+#define WTIMER5_BASE            0x4004F000  // Wide Timer5
+#define USB0_BASE               0x40050000  // USB 0 Controller
+#define GPIO_PORTA_AHB_BASE     0x40058000  // GPIO Port A (high speed)
+#define GPIO_PORTB_AHB_BASE     0x40059000  // GPIO Port B (high speed)
+#define GPIO_PORTC_AHB_BASE     0x4005A000  // GPIO Port C (high speed)
+#define GPIO_PORTD_AHB_BASE     0x4005B000  // GPIO Port D (high speed)
+#define GPIO_PORTE_AHB_BASE     0x4005C000  // GPIO Port E (high speed)
+#define GPIO_PORTF_AHB_BASE     0x4005D000  // GPIO Port F (high speed)
+#define GPIO_PORTG_AHB_BASE     0x4005E000  // GPIO Port G (high speed)
+#define GPIO_PORTH_AHB_BASE     0x4005F000  // GPIO Port H (high speed)
+#define GPIO_PORTJ_AHB_BASE     0x40060000  // GPIO Port J (high speed)
+#define GPIO_PORTK_BASE         0x40061000  // GPIO Port K
+#define GPIO_PORTL_BASE         0x40062000  // GPIO Port L
+#define GPIO_PORTM_BASE         0x40063000  // GPIO Port M
+#define GPIO_PORTN_BASE         0x40064000  // GPIO Port N
+#define GPIO_PORTP_BASE         0x40065000  // GPIO Port P
+#define GPIO_PORTQ_BASE         0x40066000  // GPIO Port Q
+#define GPIO_PORTR_BASE         0x40067000  // General-Purpose Input/Outputs
+                                            // (GPIOs)
+#define GPIO_PORTS_BASE         0x40068000  // General-Purpose Input/Outputs
+                                            // (GPIOs)
+#define GPIO_PORTT_BASE         0x40069000  // General-Purpose Input/Outputs
+                                            // (GPIOs)
+#define EEPROM_BASE             0x400AF000  // EEPROM memory
+#define ONEWIRE0_BASE           0x400B6000  // 1-Wire Master Module
+#define I2C8_BASE               0x400B8000  // I2C8
+#define I2C9_BASE               0x400B9000  // I2C9
+#define I2C4_BASE               0x400C0000  // I2C4
+#define I2C5_BASE               0x400C1000  // I2C5
+#define I2C6_BASE               0x400C2000  // I2C6
+#define I2C7_BASE               0x400C3000  // I2C7
+#define EPI0_BASE               0x400D0000  // EPI0
+#define TIMER6_BASE             0x400E0000  // General-Purpose Timers
+#define TIMER7_BASE             0x400E1000  // General-Purpose Timers
+#define EMAC0_BASE              0x400EC000  // Ethernet Controller
+#define SYSEXC_BASE             0x400F9000  // System Exception Module
+#define HIB_BASE                0x400FC000  // Hibernation Module
+#define FLASH_CTRL_BASE         0x400FD000  // FLASH Controller
+#define SYSCTL_BASE             0x400FE000  // System Control
+#define UDMA_BASE               0x400FF000  // uDMA Controller
+#define CCM0_BASE               0x44030000  // Cyclical Redundancy Check (CRC)
+#define SHAMD5_BASE             0x44034000  // SHA/MD5 Accelerator
+#define AES_BASE                0x44036000  // Advance Encryption
+                                            // Hardware-Accelerated Module
+#define DES_BASE                0x44038000  // Data Encryption Standard
+                                            // Accelerator (DES)
+#define LCD0_BASE               0x44050000  // LCD Controller
+// #define ITM_BASE                0xE0000000  // Instrumentation Trace Macrocell
+// #define DWT_BASE                0xE0001000  // Data Watchpoint and Trace
+// #define FPB_BASE                0xE0002000  // FLASH Patch and Breakpoint
+// #define NVIC_BASE               0xE000E000  // Nested Vectored Interrupt Ctrl
+// #define TPIU_BASE               0xE0040000  // Trace Port Interface Unit
+
+#endif // __HW_MEMMAP_H__
diff --git a/os/common/ext/TivaWare/inc/hw_nvic.h b/os/common/ext/TivaWare/inc/hw_nvic.h
new file mode 100644
index 0000000..c7b3568
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_nvic.h
@@ -0,0 +1,1414 @@
+//*****************************************************************************
+//
+// hw_nvic.h - Macros used when accessing the NVIC hardware.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_NVIC_H__
+#define __HW_NVIC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the NVIC register addresses.
+//
+//*****************************************************************************
+#define NVIC_ACTLR              0xE000E008  // Auxiliary Control
+#define NVIC_ST_CTRL            0xE000E010  // SysTick Control and Status
+                                            // Register
+#define NVIC_ST_RELOAD          0xE000E014  // SysTick Reload Value Register
+#define NVIC_ST_CURRENT         0xE000E018  // SysTick Current Value Register
+#define NVIC_EN0                0xE000E100  // Interrupt 0-31 Set Enable
+#define NVIC_EN1                0xE000E104  // Interrupt 32-63 Set Enable
+#define NVIC_EN2                0xE000E108  // Interrupt 64-95 Set Enable
+#define NVIC_EN3                0xE000E10C  // Interrupt 96-127 Set Enable
+#define NVIC_EN4                0xE000E110  // Interrupt 128-159 Set Enable
+#define NVIC_DIS0               0xE000E180  // Interrupt 0-31 Clear Enable
+#define NVIC_DIS1               0xE000E184  // Interrupt 32-63 Clear Enable
+#define NVIC_DIS2               0xE000E188  // Interrupt 64-95 Clear Enable
+#define NVIC_DIS3               0xE000E18C  // Interrupt 96-127 Clear Enable
+#define NVIC_DIS4               0xE000E190  // Interrupt 128-159 Clear Enable
+#define NVIC_PEND0              0xE000E200  // Interrupt 0-31 Set Pending
+#define NVIC_PEND1              0xE000E204  // Interrupt 32-63 Set Pending
+#define NVIC_PEND2              0xE000E208  // Interrupt 64-95 Set Pending
+#define NVIC_PEND3              0xE000E20C  // Interrupt 96-127 Set Pending
+#define NVIC_PEND4              0xE000E210  // Interrupt 128-159 Set Pending
+#define NVIC_UNPEND0            0xE000E280  // Interrupt 0-31 Clear Pending
+#define NVIC_UNPEND1            0xE000E284  // Interrupt 32-63 Clear Pending
+#define NVIC_UNPEND2            0xE000E288  // Interrupt 64-95 Clear Pending
+#define NVIC_UNPEND3            0xE000E28C  // Interrupt 96-127 Clear Pending
+#define NVIC_UNPEND4            0xE000E290  // Interrupt 128-159 Clear Pending
+#define NVIC_ACTIVE0            0xE000E300  // Interrupt 0-31 Active Bit
+#define NVIC_ACTIVE1            0xE000E304  // Interrupt 32-63 Active Bit
+#define NVIC_ACTIVE2            0xE000E308  // Interrupt 64-95 Active Bit
+#define NVIC_ACTIVE3            0xE000E30C  // Interrupt 96-127 Active Bit
+#define NVIC_ACTIVE4            0xE000E310  // Interrupt 128-159 Active Bit
+#define NVIC_PRI0               0xE000E400  // Interrupt 0-3 Priority
+#define NVIC_PRI1               0xE000E404  // Interrupt 4-7 Priority
+#define NVIC_PRI2               0xE000E408  // Interrupt 8-11 Priority
+#define NVIC_PRI3               0xE000E40C  // Interrupt 12-15 Priority
+#define NVIC_PRI4               0xE000E410  // Interrupt 16-19 Priority
+#define NVIC_PRI5               0xE000E414  // Interrupt 20-23 Priority
+#define NVIC_PRI6               0xE000E418  // Interrupt 24-27 Priority
+#define NVIC_PRI7               0xE000E41C  // Interrupt 28-31 Priority
+#define NVIC_PRI8               0xE000E420  // Interrupt 32-35 Priority
+#define NVIC_PRI9               0xE000E424  // Interrupt 36-39 Priority
+#define NVIC_PRI10              0xE000E428  // Interrupt 40-43 Priority
+#define NVIC_PRI11              0xE000E42C  // Interrupt 44-47 Priority
+#define NVIC_PRI12              0xE000E430  // Interrupt 48-51 Priority
+#define NVIC_PRI13              0xE000E434  // Interrupt 52-55 Priority
+#define NVIC_PRI14              0xE000E438  // Interrupt 56-59 Priority
+#define NVIC_PRI15              0xE000E43C  // Interrupt 60-63 Priority
+#define NVIC_PRI16              0xE000E440  // Interrupt 64-67 Priority
+#define NVIC_PRI17              0xE000E444  // Interrupt 68-71 Priority
+#define NVIC_PRI18              0xE000E448  // Interrupt 72-75 Priority
+#define NVIC_PRI19              0xE000E44C  // Interrupt 76-79 Priority
+#define NVIC_PRI20              0xE000E450  // Interrupt 80-83 Priority
+#define NVIC_PRI21              0xE000E454  // Interrupt 84-87 Priority
+#define NVIC_PRI22              0xE000E458  // Interrupt 88-91 Priority
+#define NVIC_PRI23              0xE000E45C  // Interrupt 92-95 Priority
+#define NVIC_PRI24              0xE000E460  // Interrupt 96-99 Priority
+#define NVIC_PRI25              0xE000E464  // Interrupt 100-103 Priority
+#define NVIC_PRI26              0xE000E468  // Interrupt 104-107 Priority
+#define NVIC_PRI27              0xE000E46C  // Interrupt 108-111 Priority
+#define NVIC_PRI28              0xE000E470  // Interrupt 112-115 Priority
+#define NVIC_PRI29              0xE000E474  // Interrupt 116-119 Priority
+#define NVIC_PRI30              0xE000E478  // Interrupt 120-123 Priority
+#define NVIC_PRI31              0xE000E47C  // Interrupt 124-127 Priority
+#define NVIC_PRI32              0xE000E480  // Interrupt 128-131 Priority
+#define NVIC_PRI33              0xE000E484  // Interrupt 132-135 Priority
+#define NVIC_PRI34              0xE000E488  // Interrupt 136-139 Priority
+#define NVIC_CPUID              0xE000ED00  // CPU ID Base
+#define NVIC_INT_CTRL           0xE000ED04  // Interrupt Control and State
+#define NVIC_VTABLE             0xE000ED08  // Vector Table Offset
+#define NVIC_APINT              0xE000ED0C  // Application Interrupt and Reset
+                                            // Control
+#define NVIC_SYS_CTRL           0xE000ED10  // System Control
+#define NVIC_CFG_CTRL           0xE000ED14  // Configuration and Control
+#define NVIC_SYS_PRI1           0xE000ED18  // System Handler Priority 1
+#define NVIC_SYS_PRI2           0xE000ED1C  // System Handler Priority 2
+#define NVIC_SYS_PRI3           0xE000ED20  // System Handler Priority 3
+#define NVIC_SYS_HND_CTRL       0xE000ED24  // System Handler Control and State
+#define NVIC_FAULT_STAT         0xE000ED28  // Configurable Fault Status
+#define NVIC_HFAULT_STAT        0xE000ED2C  // Hard Fault Status
+#define NVIC_DEBUG_STAT         0xE000ED30  // Debug Status Register
+#define NVIC_MM_ADDR            0xE000ED34  // Memory Management Fault Address
+#define NVIC_FAULT_ADDR         0xE000ED38  // Bus Fault Address
+#define NVIC_CPAC               0xE000ED88  // Coprocessor Access Control
+#define NVIC_MPU_TYPE           0xE000ED90  // MPU Type
+#define NVIC_MPU_CTRL           0xE000ED94  // MPU Control
+#define NVIC_MPU_NUMBER         0xE000ED98  // MPU Region Number
+#define NVIC_MPU_BASE           0xE000ED9C  // MPU Region Base Address
+#define NVIC_MPU_ATTR           0xE000EDA0  // MPU Region Attribute and Size
+#define NVIC_MPU_BASE1          0xE000EDA4  // MPU Region Base Address Alias 1
+#define NVIC_MPU_ATTR1          0xE000EDA8  // MPU Region Attribute and Size
+                                            // Alias 1
+#define NVIC_MPU_BASE2          0xE000EDAC  // MPU Region Base Address Alias 2
+#define NVIC_MPU_ATTR2          0xE000EDB0  // MPU Region Attribute and Size
+                                            // Alias 2
+#define NVIC_MPU_BASE3          0xE000EDB4  // MPU Region Base Address Alias 3
+#define NVIC_MPU_ATTR3          0xE000EDB8  // MPU Region Attribute and Size
+                                            // Alias 3
+#define NVIC_DBG_CTRL           0xE000EDF0  // Debug Control and Status Reg
+#define NVIC_DBG_XFER           0xE000EDF4  // Debug Core Reg. Transfer Select
+#define NVIC_DBG_DATA           0xE000EDF8  // Debug Core Register Data
+#define NVIC_DBG_INT            0xE000EDFC  // Debug Reset Interrupt Control
+#define NVIC_SW_TRIG            0xE000EF00  // Software Trigger Interrupt
+#define NVIC_FPCC               0xE000EF34  // Floating-Point Context Control
+#define NVIC_FPCA               0xE000EF38  // Floating-Point Context Address
+#define NVIC_FPDSC              0xE000EF3C  // Floating-Point Default Status
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTLR register.
+//
+//*****************************************************************************
+#define NVIC_ACTLR_DISOOFP      0x00000200  // Disable Out-Of-Order Floating
+                                            // Point
+#define NVIC_ACTLR_DISFPCA      0x00000100  // Disable CONTROL
+#define NVIC_ACTLR_DISFOLD      0x00000004  // Disable IT Folding
+#define NVIC_ACTLR_DISWBUF      0x00000002  // Disable Write Buffer
+#define NVIC_ACTLR_DISMCYC      0x00000001  // Disable Interrupts of Multiple
+                                            // Cycle Instructions
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CTRL_COUNT      0x00010000  // Count Flag
+#define NVIC_ST_CTRL_CLK_SRC    0x00000004  // Clock Source
+#define NVIC_ST_CTRL_INTEN      0x00000002  // Interrupt Enable
+#define NVIC_ST_CTRL_ENABLE     0x00000001  // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_RELOAD register.
+//
+//*****************************************************************************
+#define NVIC_ST_RELOAD_M        0x00FFFFFF  // Reload Value
+#define NVIC_ST_RELOAD_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CURRENT
+// register.
+//
+//*****************************************************************************
+#define NVIC_ST_CURRENT_M       0x00FFFFFF  // Current Value
+#define NVIC_ST_CURRENT_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN0 register.
+//
+//*****************************************************************************
+#define NVIC_EN0_INT_M          0xFFFFFFFF  // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN1 register.
+//
+//*****************************************************************************
+#define NVIC_EN1_INT_M          0xFFFFFFFF  // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN2 register.
+//
+//*****************************************************************************
+#define NVIC_EN2_INT_M          0xFFFFFFFF  // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN3 register.
+//
+//*****************************************************************************
+#define NVIC_EN3_INT_M          0xFFFFFFFF  // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN4 register.
+//
+//*****************************************************************************
+#define NVIC_EN4_INT_M          0x000007FF  // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS0 register.
+//
+//*****************************************************************************
+#define NVIC_DIS0_INT_M         0xFFFFFFFF  // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS1 register.
+//
+//*****************************************************************************
+#define NVIC_DIS1_INT_M         0xFFFFFFFF  // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS2 register.
+//
+//*****************************************************************************
+#define NVIC_DIS2_INT_M         0xFFFFFFFF  // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS3 register.
+//
+//*****************************************************************************
+#define NVIC_DIS3_INT_M         0xFFFFFFFF  // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS4 register.
+//
+//*****************************************************************************
+#define NVIC_DIS4_INT_M         0x000007FF  // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND0 register.
+//
+//*****************************************************************************
+#define NVIC_PEND0_INT_M        0xFFFFFFFF  // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND1 register.
+//
+//*****************************************************************************
+#define NVIC_PEND1_INT_M        0xFFFFFFFF  // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND2 register.
+//
+//*****************************************************************************
+#define NVIC_PEND2_INT_M        0xFFFFFFFF  // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND3 register.
+//
+//*****************************************************************************
+#define NVIC_PEND3_INT_M        0xFFFFFFFF  // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND4 register.
+//
+//*****************************************************************************
+#define NVIC_PEND4_INT_M        0x000007FF  // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND0 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND0_INT_M      0xFFFFFFFF  // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND1 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND1_INT_M      0xFFFFFFFF  // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND2 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND2_INT_M      0xFFFFFFFF  // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND3 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND3_INT_M      0xFFFFFFFF  // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND4 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND4_INT_M      0x000007FF  // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE0 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE0_INT_M      0xFFFFFFFF  // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE1 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE1_INT_M      0xFFFFFFFF  // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE2 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE2_INT_M      0xFFFFFFFF  // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE3 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE3_INT_M      0xFFFFFFFF  // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE4 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE4_INT_M      0x000007FF  // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI0 register.
+//
+//*****************************************************************************
+#define NVIC_PRI0_INT3_M        0xE0000000  // Interrupt 3 Priority Mask
+#define NVIC_PRI0_INT2_M        0x00E00000  // Interrupt 2 Priority Mask
+#define NVIC_PRI0_INT1_M        0x0000E000  // Interrupt 1 Priority Mask
+#define NVIC_PRI0_INT0_M        0x000000E0  // Interrupt 0 Priority Mask
+#define NVIC_PRI0_INT3_S        29
+#define NVIC_PRI0_INT2_S        21
+#define NVIC_PRI0_INT1_S        13
+#define NVIC_PRI0_INT0_S        5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_PRI1_INT7_M        0xE0000000  // Interrupt 7 Priority Mask
+#define NVIC_PRI1_INT6_M        0x00E00000  // Interrupt 6 Priority Mask
+#define NVIC_PRI1_INT5_M        0x0000E000  // Interrupt 5 Priority Mask
+#define NVIC_PRI1_INT4_M        0x000000E0  // Interrupt 4 Priority Mask
+#define NVIC_PRI1_INT7_S        29
+#define NVIC_PRI1_INT6_S        21
+#define NVIC_PRI1_INT5_S        13
+#define NVIC_PRI1_INT4_S        5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_PRI2_INT11_M       0xE0000000  // Interrupt 11 Priority Mask
+#define NVIC_PRI2_INT10_M       0x00E00000  // Interrupt 10 Priority Mask
+#define NVIC_PRI2_INT9_M        0x0000E000  // Interrupt 9 Priority Mask
+#define NVIC_PRI2_INT8_M        0x000000E0  // Interrupt 8 Priority Mask
+#define NVIC_PRI2_INT11_S       29
+#define NVIC_PRI2_INT10_S       21
+#define NVIC_PRI2_INT9_S        13
+#define NVIC_PRI2_INT8_S        5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_PRI3_INT15_M       0xE0000000  // Interrupt 15 Priority Mask
+#define NVIC_PRI3_INT14_M       0x00E00000  // Interrupt 14 Priority Mask
+#define NVIC_PRI3_INT13_M       0x0000E000  // Interrupt 13 Priority Mask
+#define NVIC_PRI3_INT12_M       0x000000E0  // Interrupt 12 Priority Mask
+#define NVIC_PRI3_INT15_S       29
+#define NVIC_PRI3_INT14_S       21
+#define NVIC_PRI3_INT13_S       13
+#define NVIC_PRI3_INT12_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI4 register.
+//
+//*****************************************************************************
+#define NVIC_PRI4_INT19_M       0xE0000000  // Interrupt 19 Priority Mask
+#define NVIC_PRI4_INT18_M       0x00E00000  // Interrupt 18 Priority Mask
+#define NVIC_PRI4_INT17_M       0x0000E000  // Interrupt 17 Priority Mask
+#define NVIC_PRI4_INT16_M       0x000000E0  // Interrupt 16 Priority Mask
+#define NVIC_PRI4_INT19_S       29
+#define NVIC_PRI4_INT18_S       21
+#define NVIC_PRI4_INT17_S       13
+#define NVIC_PRI4_INT16_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI5 register.
+//
+//*****************************************************************************
+#define NVIC_PRI5_INT23_M       0xE0000000  // Interrupt 23 Priority Mask
+#define NVIC_PRI5_INT22_M       0x00E00000  // Interrupt 22 Priority Mask
+#define NVIC_PRI5_INT21_M       0x0000E000  // Interrupt 21 Priority Mask
+#define NVIC_PRI5_INT20_M       0x000000E0  // Interrupt 20 Priority Mask
+#define NVIC_PRI5_INT23_S       29
+#define NVIC_PRI5_INT22_S       21
+#define NVIC_PRI5_INT21_S       13
+#define NVIC_PRI5_INT20_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI6 register.
+//
+//*****************************************************************************
+#define NVIC_PRI6_INT27_M       0xE0000000  // Interrupt 27 Priority Mask
+#define NVIC_PRI6_INT26_M       0x00E00000  // Interrupt 26 Priority Mask
+#define NVIC_PRI6_INT25_M       0x0000E000  // Interrupt 25 Priority Mask
+#define NVIC_PRI6_INT24_M       0x000000E0  // Interrupt 24 Priority Mask
+#define NVIC_PRI6_INT27_S       29
+#define NVIC_PRI6_INT26_S       21
+#define NVIC_PRI6_INT25_S       13
+#define NVIC_PRI6_INT24_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI7 register.
+//
+//*****************************************************************************
+#define NVIC_PRI7_INT31_M       0xE0000000  // Interrupt 31 Priority Mask
+#define NVIC_PRI7_INT30_M       0x00E00000  // Interrupt 30 Priority Mask
+#define NVIC_PRI7_INT29_M       0x0000E000  // Interrupt 29 Priority Mask
+#define NVIC_PRI7_INT28_M       0x000000E0  // Interrupt 28 Priority Mask
+#define NVIC_PRI7_INT31_S       29
+#define NVIC_PRI7_INT30_S       21
+#define NVIC_PRI7_INT29_S       13
+#define NVIC_PRI7_INT28_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI8 register.
+//
+//*****************************************************************************
+#define NVIC_PRI8_INT35_M       0xE0000000  // Interrupt 35 Priority Mask
+#define NVIC_PRI8_INT34_M       0x00E00000  // Interrupt 34 Priority Mask
+#define NVIC_PRI8_INT33_M       0x0000E000  // Interrupt 33 Priority Mask
+#define NVIC_PRI8_INT32_M       0x000000E0  // Interrupt 32 Priority Mask
+#define NVIC_PRI8_INT35_S       29
+#define NVIC_PRI8_INT34_S       21
+#define NVIC_PRI8_INT33_S       13
+#define NVIC_PRI8_INT32_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI9 register.
+//
+//*****************************************************************************
+#define NVIC_PRI9_INT39_M       0xE0000000  // Interrupt 39 Priority Mask
+#define NVIC_PRI9_INT38_M       0x00E00000  // Interrupt 38 Priority Mask
+#define NVIC_PRI9_INT37_M       0x0000E000  // Interrupt 37 Priority Mask
+#define NVIC_PRI9_INT36_M       0x000000E0  // Interrupt 36 Priority Mask
+#define NVIC_PRI9_INT39_S       29
+#define NVIC_PRI9_INT38_S       21
+#define NVIC_PRI9_INT37_S       13
+#define NVIC_PRI9_INT36_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI10 register.
+//
+//*****************************************************************************
+#define NVIC_PRI10_INT43_M      0xE0000000  // Interrupt 43 Priority Mask
+#define NVIC_PRI10_INT42_M      0x00E00000  // Interrupt 42 Priority Mask
+#define NVIC_PRI10_INT41_M      0x0000E000  // Interrupt 41 Priority Mask
+#define NVIC_PRI10_INT40_M      0x000000E0  // Interrupt 40 Priority Mask
+#define NVIC_PRI10_INT43_S      29
+#define NVIC_PRI10_INT42_S      21
+#define NVIC_PRI10_INT41_S      13
+#define NVIC_PRI10_INT40_S      5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI11 register.
+//
+//*****************************************************************************
+#define NVIC_PRI11_INT47_M      0xE0000000  // Interrupt 47 Priority Mask
+#define NVIC_PRI11_INT46_M      0x00E00000  // Interrupt 46 Priority Mask
+#define NVIC_PRI11_INT45_M      0x0000E000  // Interrupt 45 Priority Mask
+#define NVIC_PRI11_INT44_M      0x000000E0  // Interrupt 44 Priority Mask
+#define NVIC_PRI11_INT47_S      29
+#define NVIC_PRI11_INT46_S      21
+#define NVIC_PRI11_INT45_S      13
+#define NVIC_PRI11_INT44_S      5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI12 register.
+//
+//*****************************************************************************
+#define NVIC_PRI12_INT51_M      0xE0000000  // Interrupt 51 Priority Mask
+#define NVIC_PRI12_INT50_M      0x00E00000  // Interrupt 50 Priority Mask
+#define NVIC_PRI12_INT49_M      0x0000E000  // Interrupt 49 Priority Mask
+#define NVIC_PRI12_INT48_M      0x000000E0  // Interrupt 48 Priority Mask
+#define NVIC_PRI12_INT51_S      29
+#define NVIC_PRI12_INT50_S      21
+#define NVIC_PRI12_INT49_S      13
+#define NVIC_PRI12_INT48_S      5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI13 register.
+//
+//*****************************************************************************
+#define NVIC_PRI13_INT55_M      0xE0000000  // Interrupt 55 Priority Mask
+#define NVIC_PRI13_INT54_M      0x00E00000  // Interrupt 54 Priority Mask
+#define NVIC_PRI13_INT53_M      0x0000E000  // Interrupt 53 Priority Mask
+#define NVIC_PRI13_INT52_M      0x000000E0  // Interrupt 52 Priority Mask
+#define NVIC_PRI13_INT55_S      29
+#define NVIC_PRI13_INT54_S      21
+#define NVIC_PRI13_INT53_S      13
+#define NVIC_PRI13_INT52_S      5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI14 register.
+//
+//*****************************************************************************
+#define NVIC_PRI14_INTD_M       0xE0000000  // Interrupt 59 Priority Mask
+#define NVIC_PRI14_INTC_M       0x00E00000  // Interrupt 58 Priority Mask
+#define NVIC_PRI14_INTB_M       0x0000E000  // Interrupt 57 Priority Mask
+#define NVIC_PRI14_INTA_M       0x000000E0  // Interrupt 56 Priority Mask
+#define NVIC_PRI14_INTD_S       29
+#define NVIC_PRI14_INTC_S       21
+#define NVIC_PRI14_INTB_S       13
+#define NVIC_PRI14_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI15 register.
+//
+//*****************************************************************************
+#define NVIC_PRI15_INTD_M       0xE0000000  // Interrupt 63 Priority Mask
+#define NVIC_PRI15_INTC_M       0x00E00000  // Interrupt 62 Priority Mask
+#define NVIC_PRI15_INTB_M       0x0000E000  // Interrupt 61 Priority Mask
+#define NVIC_PRI15_INTA_M       0x000000E0  // Interrupt 60 Priority Mask
+#define NVIC_PRI15_INTD_S       29
+#define NVIC_PRI15_INTC_S       21
+#define NVIC_PRI15_INTB_S       13
+#define NVIC_PRI15_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI16 register.
+//
+//*****************************************************************************
+#define NVIC_PRI16_INTD_M       0xE0000000  // Interrupt 67 Priority Mask
+#define NVIC_PRI16_INTC_M       0x00E00000  // Interrupt 66 Priority Mask
+#define NVIC_PRI16_INTB_M       0x0000E000  // Interrupt 65 Priority Mask
+#define NVIC_PRI16_INTA_M       0x000000E0  // Interrupt 64 Priority Mask
+#define NVIC_PRI16_INTD_S       29
+#define NVIC_PRI16_INTC_S       21
+#define NVIC_PRI16_INTB_S       13
+#define NVIC_PRI16_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI17 register.
+//
+//*****************************************************************************
+#define NVIC_PRI17_INTD_M       0xE0000000  // Interrupt 71 Priority Mask
+#define NVIC_PRI17_INTC_M       0x00E00000  // Interrupt 70 Priority Mask
+#define NVIC_PRI17_INTB_M       0x0000E000  // Interrupt 69 Priority Mask
+#define NVIC_PRI17_INTA_M       0x000000E0  // Interrupt 68 Priority Mask
+#define NVIC_PRI17_INTD_S       29
+#define NVIC_PRI17_INTC_S       21
+#define NVIC_PRI17_INTB_S       13
+#define NVIC_PRI17_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI18 register.
+//
+//*****************************************************************************
+#define NVIC_PRI18_INTD_M       0xE0000000  // Interrupt 75 Priority Mask
+#define NVIC_PRI18_INTC_M       0x00E00000  // Interrupt 74 Priority Mask
+#define NVIC_PRI18_INTB_M       0x0000E000  // Interrupt 73 Priority Mask
+#define NVIC_PRI18_INTA_M       0x000000E0  // Interrupt 72 Priority Mask
+#define NVIC_PRI18_INTD_S       29
+#define NVIC_PRI18_INTC_S       21
+#define NVIC_PRI18_INTB_S       13
+#define NVIC_PRI18_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI19 register.
+//
+//*****************************************************************************
+#define NVIC_PRI19_INTD_M       0xE0000000  // Interrupt 79 Priority Mask
+#define NVIC_PRI19_INTC_M       0x00E00000  // Interrupt 78 Priority Mask
+#define NVIC_PRI19_INTB_M       0x0000E000  // Interrupt 77 Priority Mask
+#define NVIC_PRI19_INTA_M       0x000000E0  // Interrupt 76 Priority Mask
+#define NVIC_PRI19_INTD_S       29
+#define NVIC_PRI19_INTC_S       21
+#define NVIC_PRI19_INTB_S       13
+#define NVIC_PRI19_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI20 register.
+//
+//*****************************************************************************
+#define NVIC_PRI20_INTD_M       0xE0000000  // Interrupt 83 Priority Mask
+#define NVIC_PRI20_INTC_M       0x00E00000  // Interrupt 82 Priority Mask
+#define NVIC_PRI20_INTB_M       0x0000E000  // Interrupt 81 Priority Mask
+#define NVIC_PRI20_INTA_M       0x000000E0  // Interrupt 80 Priority Mask
+#define NVIC_PRI20_INTD_S       29
+#define NVIC_PRI20_INTC_S       21
+#define NVIC_PRI20_INTB_S       13
+#define NVIC_PRI20_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI21 register.
+//
+//*****************************************************************************
+#define NVIC_PRI21_INTD_M       0xE0000000  // Interrupt 87 Priority Mask
+#define NVIC_PRI21_INTC_M       0x00E00000  // Interrupt 86 Priority Mask
+#define NVIC_PRI21_INTB_M       0x0000E000  // Interrupt 85 Priority Mask
+#define NVIC_PRI21_INTA_M       0x000000E0  // Interrupt 84 Priority Mask
+#define NVIC_PRI21_INTD_S       29
+#define NVIC_PRI21_INTC_S       21
+#define NVIC_PRI21_INTB_S       13
+#define NVIC_PRI21_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI22 register.
+//
+//*****************************************************************************
+#define NVIC_PRI22_INTD_M       0xE0000000  // Interrupt 91 Priority Mask
+#define NVIC_PRI22_INTC_M       0x00E00000  // Interrupt 90 Priority Mask
+#define NVIC_PRI22_INTB_M       0x0000E000  // Interrupt 89 Priority Mask
+#define NVIC_PRI22_INTA_M       0x000000E0  // Interrupt 88 Priority Mask
+#define NVIC_PRI22_INTD_S       29
+#define NVIC_PRI22_INTC_S       21
+#define NVIC_PRI22_INTB_S       13
+#define NVIC_PRI22_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI23 register.
+//
+//*****************************************************************************
+#define NVIC_PRI23_INTD_M       0xE0000000  // Interrupt 95 Priority Mask
+#define NVIC_PRI23_INTC_M       0x00E00000  // Interrupt 94 Priority Mask
+#define NVIC_PRI23_INTB_M       0x0000E000  // Interrupt 93 Priority Mask
+#define NVIC_PRI23_INTA_M       0x000000E0  // Interrupt 92 Priority Mask
+#define NVIC_PRI23_INTD_S       29
+#define NVIC_PRI23_INTC_S       21
+#define NVIC_PRI23_INTB_S       13
+#define NVIC_PRI23_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI24 register.
+//
+//*****************************************************************************
+#define NVIC_PRI24_INTD_M       0xE0000000  // Interrupt 99 Priority Mask
+#define NVIC_PRI24_INTC_M       0x00E00000  // Interrupt 98 Priority Mask
+#define NVIC_PRI24_INTB_M       0x0000E000  // Interrupt 97 Priority Mask
+#define NVIC_PRI24_INTA_M       0x000000E0  // Interrupt 96 Priority Mask
+#define NVIC_PRI24_INTD_S       29
+#define NVIC_PRI24_INTC_S       21
+#define NVIC_PRI24_INTB_S       13
+#define NVIC_PRI24_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI25 register.
+//
+//*****************************************************************************
+#define NVIC_PRI25_INTD_M       0xE0000000  // Interrupt 103 Priority Mask
+#define NVIC_PRI25_INTC_M       0x00E00000  // Interrupt 102 Priority Mask
+#define NVIC_PRI25_INTB_M       0x0000E000  // Interrupt 101 Priority Mask
+#define NVIC_PRI25_INTA_M       0x000000E0  // Interrupt 100 Priority Mask
+#define NVIC_PRI25_INTD_S       29
+#define NVIC_PRI25_INTC_S       21
+#define NVIC_PRI25_INTB_S       13
+#define NVIC_PRI25_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI26 register.
+//
+//*****************************************************************************
+#define NVIC_PRI26_INTD_M       0xE0000000  // Interrupt 107 Priority Mask
+#define NVIC_PRI26_INTC_M       0x00E00000  // Interrupt 106 Priority Mask
+#define NVIC_PRI26_INTB_M       0x0000E000  // Interrupt 105 Priority Mask
+#define NVIC_PRI26_INTA_M       0x000000E0  // Interrupt 104 Priority Mask
+#define NVIC_PRI26_INTD_S       29
+#define NVIC_PRI26_INTC_S       21
+#define NVIC_PRI26_INTB_S       13
+#define NVIC_PRI26_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI27 register.
+//
+//*****************************************************************************
+#define NVIC_PRI27_INTD_M       0xE0000000  // Interrupt 111 Priority Mask
+#define NVIC_PRI27_INTC_M       0x00E00000  // Interrupt 110 Priority Mask
+#define NVIC_PRI27_INTB_M       0x0000E000  // Interrupt 109 Priority Mask
+#define NVIC_PRI27_INTA_M       0x000000E0  // Interrupt 108 Priority Mask
+#define NVIC_PRI27_INTD_S       29
+#define NVIC_PRI27_INTC_S       21
+#define NVIC_PRI27_INTB_S       13
+#define NVIC_PRI27_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI28 register.
+//
+//*****************************************************************************
+#define NVIC_PRI28_INTD_M       0xE0000000  // Interrupt 115 Priority Mask
+#define NVIC_PRI28_INTC_M       0x00E00000  // Interrupt 114 Priority Mask
+#define NVIC_PRI28_INTB_M       0x0000E000  // Interrupt 113 Priority Mask
+#define NVIC_PRI28_INTA_M       0x000000E0  // Interrupt 112 Priority Mask
+#define NVIC_PRI28_INTD_S       29
+#define NVIC_PRI28_INTC_S       21
+#define NVIC_PRI28_INTB_S       13
+#define NVIC_PRI28_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI29 register.
+//
+//*****************************************************************************
+#define NVIC_PRI29_INTD_M       0xE0000000  // Interrupt 119 Priority Mask
+#define NVIC_PRI29_INTC_M       0x00E00000  // Interrupt 118 Priority Mask
+#define NVIC_PRI29_INTB_M       0x0000E000  // Interrupt 117 Priority Mask
+#define NVIC_PRI29_INTA_M       0x000000E0  // Interrupt 116 Priority Mask
+#define NVIC_PRI29_INTD_S       29
+#define NVIC_PRI29_INTC_S       21
+#define NVIC_PRI29_INTB_S       13
+#define NVIC_PRI29_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI30 register.
+//
+//*****************************************************************************
+#define NVIC_PRI30_INTD_M       0xE0000000  // Interrupt 123 Priority Mask
+#define NVIC_PRI30_INTC_M       0x00E00000  // Interrupt 122 Priority Mask
+#define NVIC_PRI30_INTB_M       0x0000E000  // Interrupt 121 Priority Mask
+#define NVIC_PRI30_INTA_M       0x000000E0  // Interrupt 120 Priority Mask
+#define NVIC_PRI30_INTD_S       29
+#define NVIC_PRI30_INTC_S       21
+#define NVIC_PRI30_INTB_S       13
+#define NVIC_PRI30_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI31 register.
+//
+//*****************************************************************************
+#define NVIC_PRI31_INTD_M       0xE0000000  // Interrupt 127 Priority Mask
+#define NVIC_PRI31_INTC_M       0x00E00000  // Interrupt 126 Priority Mask
+#define NVIC_PRI31_INTB_M       0x0000E000  // Interrupt 125 Priority Mask
+#define NVIC_PRI31_INTA_M       0x000000E0  // Interrupt 124 Priority Mask
+#define NVIC_PRI31_INTD_S       29
+#define NVIC_PRI31_INTC_S       21
+#define NVIC_PRI31_INTB_S       13
+#define NVIC_PRI31_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI32 register.
+//
+//*****************************************************************************
+#define NVIC_PRI32_INTD_M       0xE0000000  // Interrupt 131 Priority Mask
+#define NVIC_PRI32_INTC_M       0x00E00000  // Interrupt 130 Priority Mask
+#define NVIC_PRI32_INTB_M       0x0000E000  // Interrupt 129 Priority Mask
+#define NVIC_PRI32_INTA_M       0x000000E0  // Interrupt 128 Priority Mask
+#define NVIC_PRI32_INTD_S       29
+#define NVIC_PRI32_INTC_S       21
+#define NVIC_PRI32_INTB_S       13
+#define NVIC_PRI32_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI33 register.
+//
+//*****************************************************************************
+#define NVIC_PRI33_INTD_M       0xE0000000  // Interrupt Priority for Interrupt
+                                            // [4n+3]
+#define NVIC_PRI33_INTC_M       0x00E00000  // Interrupt Priority for Interrupt
+                                            // [4n+2]
+#define NVIC_PRI33_INTB_M       0x0000E000  // Interrupt Priority for Interrupt
+                                            // [4n+1]
+#define NVIC_PRI33_INTA_M       0x000000E0  // Interrupt Priority for Interrupt
+                                            // [4n]
+#define NVIC_PRI33_INTD_S       29
+#define NVIC_PRI33_INTC_S       21
+#define NVIC_PRI33_INTB_S       13
+#define NVIC_PRI33_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI34 register.
+//
+//*****************************************************************************
+#define NVIC_PRI34_INTD_M       0xE0000000  // Interrupt Priority for Interrupt
+                                            // [4n+3]
+#define NVIC_PRI34_INTC_M       0x00E00000  // Interrupt Priority for Interrupt
+                                            // [4n+2]
+#define NVIC_PRI34_INTB_M       0x0000E000  // Interrupt Priority for Interrupt
+                                            // [4n+1]
+#define NVIC_PRI34_INTA_M       0x000000E0  // Interrupt Priority for Interrupt
+                                            // [4n]
+#define NVIC_PRI34_INTD_S       29
+#define NVIC_PRI34_INTC_S       21
+#define NVIC_PRI34_INTB_S       13
+#define NVIC_PRI34_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPUID register.
+//
+//*****************************************************************************
+#define NVIC_CPUID_IMP_M        0xFF000000  // Implementer Code
+#define NVIC_CPUID_IMP_ARM      0x41000000  // ARM
+#define NVIC_CPUID_VAR_M        0x00F00000  // Variant Number
+#define NVIC_CPUID_CON_M        0x000F0000  // Constant
+#define NVIC_CPUID_PARTNO_M     0x0000FFF0  // Part Number
+#define NVIC_CPUID_PARTNO_CM4   0x0000C240  // Cortex-M4 processor
+#define NVIC_CPUID_REV_M        0x0000000F  // Revision Number
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_INT_CTRL_NMI_SET   0x80000000  // NMI Set Pending
+#define NVIC_INT_CTRL_PEND_SV   0x10000000  // PendSV Set Pending
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000  // PendSV Clear Pending
+#define NVIC_INT_CTRL_PENDSTSET 0x04000000  // SysTick Set Pending
+#define NVIC_INT_CTRL_PENDSTCLR 0x02000000  // SysTick Clear Pending
+#define NVIC_INT_CTRL_ISR_PRE   0x00800000  // Debug Interrupt Handling
+#define NVIC_INT_CTRL_ISR_PEND  0x00400000  // Interrupt Pending
+#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000  // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_PEN_NMI                                             \
+                                0x00002000  // NMI
+#define NVIC_INT_CTRL_VEC_PEN_HARD                                            \
+                                0x00003000  // Hard fault
+#define NVIC_INT_CTRL_VEC_PEN_MEM                                             \
+                                0x00004000  // Memory management fault
+#define NVIC_INT_CTRL_VEC_PEN_BUS                                             \
+                                0x00005000  // Bus fault
+#define NVIC_INT_CTRL_VEC_PEN_USG                                             \
+                                0x00006000  // Usage fault
+#define NVIC_INT_CTRL_VEC_PEN_SVC                                             \
+                                0x0000B000  // SVCall
+#define NVIC_INT_CTRL_VEC_PEN_PNDSV                                           \
+                                0x0000E000  // PendSV
+#define NVIC_INT_CTRL_VEC_PEN_TICK                                            \
+                                0x0000F000  // SysTick
+#define NVIC_INT_CTRL_RET_BASE  0x00000800  // Return to Base
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF  // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_ACT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_VTABLE register.
+//
+//*****************************************************************************
+#define NVIC_VTABLE_OFFSET_M    0xFFFFFC00  // Vector Table Offset
+#define NVIC_VTABLE_OFFSET_S    10
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_APINT register.
+//
+//*****************************************************************************
+#define NVIC_APINT_VECTKEY_M    0xFFFF0000  // Register Key
+#define NVIC_APINT_VECTKEY      0x05FA0000  // Vector key
+#define NVIC_APINT_ENDIANESS    0x00008000  // Data Endianess
+#define NVIC_APINT_PRIGROUP_M   0x00000700  // Interrupt Priority Grouping
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000  // Priority group 7.1 split
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100  // Priority group 6.2 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200  // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300  // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400  // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500  // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600  // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700  // Priority group 0.8 split
+#define NVIC_APINT_SYSRESETREQ  0x00000004  // System Reset Request
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002  // Clear Active NMI / Fault
+#define NVIC_APINT_VECT_RESET   0x00000001  // System Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010  // Wake Up on Pending
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004  // Deep Sleep Enable
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002  // Sleep on ISR Exit
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CFG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_CFG_CTRL_STKALIGN  0x00000200  // Stack Alignment on Exception
+                                            // Entry
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100  // Ignore Bus Fault in NMI and
+                                            // Fault
+#define NVIC_CFG_CTRL_DIV0      0x00000010  // Trap on Divide by 0
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008  // Trap on Unaligned Access
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002  // Allow Main Interrupt Trigger
+#define NVIC_CFG_CTRL_BASE_THR  0x00000001  // Thread State Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI1_USAGE_M   0x00E00000  // Usage Fault Priority
+#define NVIC_SYS_PRI1_BUS_M     0x0000E000  // Bus Fault Priority
+#define NVIC_SYS_PRI1_MEM_M     0x000000E0  // Memory Management Fault Priority
+#define NVIC_SYS_PRI1_USAGE_S   21
+#define NVIC_SYS_PRI1_BUS_S     13
+#define NVIC_SYS_PRI1_MEM_S     5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI2_SVC_M     0xE0000000  // SVCall Priority
+#define NVIC_SYS_PRI2_SVC_S     29
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI3_TICK_M    0xE0000000  // SysTick Exception Priority
+#define NVIC_SYS_PRI3_PENDSV_M  0x00E00000  // PendSV Priority
+#define NVIC_SYS_PRI3_DEBUG_M   0x000000E0  // Debug Priority
+#define NVIC_SYS_PRI3_TICK_S    29
+#define NVIC_SYS_PRI3_PENDSV_S  21
+#define NVIC_SYS_PRI3_DEBUG_S   5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
+// register.
+//
+//*****************************************************************************
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000  // Usage Fault Enable
+#define NVIC_SYS_HND_CTRL_BUS   0x00020000  // Bus Fault Enable
+#define NVIC_SYS_HND_CTRL_MEM   0x00010000  // Memory Management Fault Enable
+#define NVIC_SYS_HND_CTRL_SVC   0x00008000  // SVC Call Pending
+#define NVIC_SYS_HND_CTRL_BUSP  0x00004000  // Bus Fault Pending
+#define NVIC_SYS_HND_CTRL_MEMP  0x00002000  // Memory Management Fault Pending
+#define NVIC_SYS_HND_CTRL_USAGEP                                              \
+                                0x00001000  // Usage Fault Pending
+#define NVIC_SYS_HND_CTRL_TICK  0x00000800  // SysTick Exception Active
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400  // PendSV Exception Active
+#define NVIC_SYS_HND_CTRL_MON   0x00000100  // Debug Monitor Active
+#define NVIC_SYS_HND_CTRL_SVCA  0x00000080  // SVC Call Active
+#define NVIC_SYS_HND_CTRL_USGA  0x00000008  // Usage Fault Active
+#define NVIC_SYS_HND_CTRL_BUSA  0x00000002  // Bus Fault Active
+#define NVIC_SYS_HND_CTRL_MEMA  0x00000001  // Memory Management Fault Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_STAT_DIV0    0x02000000  // Divide-by-Zero Usage Fault
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000  // Unaligned Access Usage Fault
+#define NVIC_FAULT_STAT_NOCP    0x00080000  // No Coprocessor Usage Fault
+#define NVIC_FAULT_STAT_INVPC   0x00040000  // Invalid PC Load Usage Fault
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000  // Invalid State Usage Fault
+#define NVIC_FAULT_STAT_UNDEF   0x00010000  // Undefined Instruction Usage
+                                            // Fault
+#define NVIC_FAULT_STAT_BFARV   0x00008000  // Bus Fault Address Register Valid
+#define NVIC_FAULT_STAT_BLSPERR 0x00002000  // Bus Fault on Floating-Point Lazy
+                                            // State Preservation
+#define NVIC_FAULT_STAT_BSTKE   0x00001000  // Stack Bus Fault
+#define NVIC_FAULT_STAT_BUSTKE  0x00000800  // Unstack Bus Fault
+#define NVIC_FAULT_STAT_IMPRE   0x00000400  // Imprecise Data Bus Error
+#define NVIC_FAULT_STAT_PRECISE 0x00000200  // Precise Data Bus Error
+#define NVIC_FAULT_STAT_IBUS    0x00000100  // Instruction Bus Error
+#define NVIC_FAULT_STAT_MMARV   0x00000080  // Memory Management Fault Address
+                                            // Register Valid
+#define NVIC_FAULT_STAT_MLSPERR 0x00000020  // Memory Management Fault on
+                                            // Floating-Point Lazy State
+                                            // Preservation
+#define NVIC_FAULT_STAT_MSTKE   0x00000010  // Stack Access Violation
+#define NVIC_FAULT_STAT_MUSTKE  0x00000008  // Unstack Access Violation
+#define NVIC_FAULT_STAT_DERR    0x00000002  // Data Access Violation
+#define NVIC_FAULT_STAT_IERR    0x00000001  // Instruction Access Violation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_HFAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_HFAULT_STAT_DBG    0x80000000  // Debug Event
+#define NVIC_HFAULT_STAT_FORCED 0x40000000  // Forced Hard Fault
+#define NVIC_HFAULT_STAT_VECT   0x00000002  // Vector Table Read Fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DEBUG_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_DEBUG_STAT_EXTRNL  0x00000010  // EDBGRQ asserted
+#define NVIC_DEBUG_STAT_VCATCH  0x00000008  // Vector catch
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004  // DWT match
+#define NVIC_DEBUG_STAT_BKPT    0x00000002  // Breakpoint instruction
+#define NVIC_DEBUG_STAT_HALTED  0x00000001  // Halt request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MM_ADDR register.
+//
+//*****************************************************************************
+#define NVIC_MM_ADDR_M          0xFFFFFFFF  // Fault Address
+#define NVIC_MM_ADDR_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_ADDR
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_ADDR_M       0xFFFFFFFF  // Fault Address
+#define NVIC_FAULT_ADDR_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPAC register.
+//
+//*****************************************************************************
+#define NVIC_CPAC_CP11_M        0x00C00000  // CP11 Coprocessor Access
+                                            // Privilege
+#define NVIC_CPAC_CP11_DIS      0x00000000  // Access Denied
+#define NVIC_CPAC_CP11_PRIV     0x00400000  // Privileged Access Only
+#define NVIC_CPAC_CP11_FULL     0x00C00000  // Full Access
+#define NVIC_CPAC_CP10_M        0x00300000  // CP10 Coprocessor Access
+                                            // Privilege
+#define NVIC_CPAC_CP10_DIS      0x00000000  // Access Denied
+#define NVIC_CPAC_CP10_PRIV     0x00100000  // Privileged Access Only
+#define NVIC_CPAC_CP10_FULL     0x00300000  // Full Access
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000  // Number of I Regions
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00  // Number of D Regions
+#define NVIC_MPU_TYPE_SEPARATE  0x00000001  // Separate or Unified MPU
+#define NVIC_MPU_TYPE_IREGION_S 16
+#define NVIC_MPU_TYPE_DREGION_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004  // MPU Default Region
+#define NVIC_MPU_CTRL_HFNMIENA  0x00000002  // MPU Enabled During Faults
+#define NVIC_MPU_CTRL_ENABLE    0x00000001  // MPU Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_NUMBER
+// register.
+//
+//*****************************************************************************
+#define NVIC_MPU_NUMBER_M       0x00000007  // MPU Region to Access
+#define NVIC_MPU_NUMBER_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE_ADDR_M    0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE_VALID     0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE_REGION_M  0x00000007  // Region Number
+#define NVIC_MPU_BASE_ADDR_S    5
+#define NVIC_MPU_BASE_REGION_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR_XN        0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR_AP_M      0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR_AP_NO_NO  0x00000000  // prv: no access, usr: no access
+#define NVIC_MPU_ATTR_AP_RW_NO  0x01000000  // prv: rw, usr: none
+#define NVIC_MPU_ATTR_AP_RW_RO  0x02000000  // prv: rw, usr: read-only
+#define NVIC_MPU_ATTR_AP_RW_RW  0x03000000  // prv: rw, usr: rw
+#define NVIC_MPU_ATTR_AP_RO_NO  0x05000000  // prv: ro, usr: none
+#define NVIC_MPU_ATTR_AP_RO_RO  0x06000000  // prv: ro, usr: ro
+#define NVIC_MPU_ATTR_TEX_M     0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR_SHAREABLE 0x00040000  // Shareable
+#define NVIC_MPU_ATTR_CACHEABLE 0x00020000  // Cacheable
+#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000  // Bufferable
+#define NVIC_MPU_ATTR_SRD_M     0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR_SRD_0     0x00000100  // Sub-region 0 disable
+#define NVIC_MPU_ATTR_SRD_1     0x00000200  // Sub-region 1 disable
+#define NVIC_MPU_ATTR_SRD_2     0x00000400  // Sub-region 2 disable
+#define NVIC_MPU_ATTR_SRD_3     0x00000800  // Sub-region 3 disable
+#define NVIC_MPU_ATTR_SRD_4     0x00001000  // Sub-region 4 disable
+#define NVIC_MPU_ATTR_SRD_5     0x00002000  // Sub-region 5 disable
+#define NVIC_MPU_ATTR_SRD_6     0x00004000  // Sub-region 6 disable
+#define NVIC_MPU_ATTR_SRD_7     0x00008000  // Sub-region 7 disable
+#define NVIC_MPU_ATTR_SIZE_M    0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR_SIZE_32B  0x00000008  // Region size 32 bytes
+#define NVIC_MPU_ATTR_SIZE_64B  0x0000000A  // Region size 64 bytes
+#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C  // Region size 128 bytes
+#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E  // Region size 256 bytes
+#define NVIC_MPU_ATTR_SIZE_512B 0x00000010  // Region size 512 bytes
+#define NVIC_MPU_ATTR_SIZE_1K   0x00000012  // Region size 1 Kbytes
+#define NVIC_MPU_ATTR_SIZE_2K   0x00000014  // Region size 2 Kbytes
+#define NVIC_MPU_ATTR_SIZE_4K   0x00000016  // Region size 4 Kbytes
+#define NVIC_MPU_ATTR_SIZE_8K   0x00000018  // Region size 8 Kbytes
+#define NVIC_MPU_ATTR_SIZE_16K  0x0000001A  // Region size 16 Kbytes
+#define NVIC_MPU_ATTR_SIZE_32K  0x0000001C  // Region size 32 Kbytes
+#define NVIC_MPU_ATTR_SIZE_64K  0x0000001E  // Region size 64 Kbytes
+#define NVIC_MPU_ATTR_SIZE_128K 0x00000020  // Region size 128 Kbytes
+#define NVIC_MPU_ATTR_SIZE_256K 0x00000022  // Region size 256 Kbytes
+#define NVIC_MPU_ATTR_SIZE_512K 0x00000024  // Region size 512 Kbytes
+#define NVIC_MPU_ATTR_SIZE_1M   0x00000026  // Region size 1 Mbytes
+#define NVIC_MPU_ATTR_SIZE_2M   0x00000028  // Region size 2 Mbytes
+#define NVIC_MPU_ATTR_SIZE_4M   0x0000002A  // Region size 4 Mbytes
+#define NVIC_MPU_ATTR_SIZE_8M   0x0000002C  // Region size 8 Mbytes
+#define NVIC_MPU_ATTR_SIZE_16M  0x0000002E  // Region size 16 Mbytes
+#define NVIC_MPU_ATTR_SIZE_32M  0x00000030  // Region size 32 Mbytes
+#define NVIC_MPU_ATTR_SIZE_64M  0x00000032  // Region size 64 Mbytes
+#define NVIC_MPU_ATTR_SIZE_128M 0x00000034  // Region size 128 Mbytes
+#define NVIC_MPU_ATTR_SIZE_256M 0x00000036  // Region size 256 Mbytes
+#define NVIC_MPU_ATTR_SIZE_512M 0x00000038  // Region size 512 Mbytes
+#define NVIC_MPU_ATTR_SIZE_1G   0x0000003A  // Region size 1 Gbytes
+#define NVIC_MPU_ATTR_SIZE_2G   0x0000003C  // Region size 2 Gbytes
+#define NVIC_MPU_ATTR_SIZE_4G   0x0000003E  // Region size 4 Gbytes
+#define NVIC_MPU_ATTR_ENABLE    0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE1_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE1_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE1_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE1_ADDR_S   5
+#define NVIC_MPU_BASE1_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR1_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR1_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR1_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR1_SHAREABLE                                              \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR1_CACHEABLE                                              \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR1_BUFFRABLE                                              \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR1_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR1_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR1_ENABLE   0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE2_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE2_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE2_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE2_ADDR_S   5
+#define NVIC_MPU_BASE2_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR2_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR2_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR2_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR2_SHAREABLE                                              \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR2_CACHEABLE                                              \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR2_BUFFRABLE                                              \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR2_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR2_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR2_ENABLE   0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE3_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE3_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE3_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE3_ADDR_S   5
+#define NVIC_MPU_BASE3_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR3_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR3_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR3_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR3_SHAREABLE                                              \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR3_CACHEABLE                                              \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR3_BUFFRABLE                                              \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR3_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR3_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR3_ENABLE   0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_DBG_CTRL_DBGKEY_M  0xFFFF0000  // Debug key mask
+#define NVIC_DBG_CTRL_DBGKEY    0xA05F0000  // Debug key
+#define NVIC_DBG_CTRL_S_RESET_ST                                              \
+                                0x02000000  // Core has reset since last read
+#define NVIC_DBG_CTRL_S_RETIRE_ST                                             \
+                                0x01000000  // Core has executed insruction
+                                            // since last read
+#define NVIC_DBG_CTRL_S_LOCKUP  0x00080000  // Core is locked up
+#define NVIC_DBG_CTRL_S_SLEEP   0x00040000  // Core is sleeping
+#define NVIC_DBG_CTRL_S_HALT    0x00020000  // Core status on halt
+#define NVIC_DBG_CTRL_S_REGRDY  0x00010000  // Register read/write available
+#define NVIC_DBG_CTRL_C_SNAPSTALL                                             \
+                                0x00000020  // Breaks a stalled load/store
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008  // Mask interrupts when stepping
+#define NVIC_DBG_CTRL_C_STEP    0x00000004  // Step the core
+#define NVIC_DBG_CTRL_C_HALT    0x00000002  // Halt the core
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001  // Enable debug
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_XFER register.
+//
+//*****************************************************************************
+#define NVIC_DBG_XFER_REG_WNR   0x00010000  // Write or not read
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F  // Register
+#define NVIC_DBG_XFER_REG_R0    0x00000000  // Register R0
+#define NVIC_DBG_XFER_REG_R1    0x00000001  // Register R1
+#define NVIC_DBG_XFER_REG_R2    0x00000002  // Register R2
+#define NVIC_DBG_XFER_REG_R3    0x00000003  // Register R3
+#define NVIC_DBG_XFER_REG_R4    0x00000004  // Register R4
+#define NVIC_DBG_XFER_REG_R5    0x00000005  // Register R5
+#define NVIC_DBG_XFER_REG_R6    0x00000006  // Register R6
+#define NVIC_DBG_XFER_REG_R7    0x00000007  // Register R7
+#define NVIC_DBG_XFER_REG_R8    0x00000008  // Register R8
+#define NVIC_DBG_XFER_REG_R9    0x00000009  // Register R9
+#define NVIC_DBG_XFER_REG_R10   0x0000000A  // Register R10
+#define NVIC_DBG_XFER_REG_R11   0x0000000B  // Register R11
+#define NVIC_DBG_XFER_REG_R12   0x0000000C  // Register R12
+#define NVIC_DBG_XFER_REG_R13   0x0000000D  // Register R13
+#define NVIC_DBG_XFER_REG_R14   0x0000000E  // Register R14
+#define NVIC_DBG_XFER_REG_R15   0x0000000F  // Register R15
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010  // xPSR/Flags register
+#define NVIC_DBG_XFER_REG_MSP   0x00000011  // Main SP
+#define NVIC_DBG_XFER_REG_PSP   0x00000012  // Process SP
+#define NVIC_DBG_XFER_REG_DSP   0x00000013  // Deep SP
+#define NVIC_DBG_XFER_REG_CFBP  0x00000014  // Control/Fault/BasePri/PriMask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_DATA register.
+//
+//*****************************************************************************
+#define NVIC_DBG_DATA_M         0xFFFFFFFF  // Data temporary cache
+#define NVIC_DBG_DATA_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_INT register.
+//
+//*****************************************************************************
+#define NVIC_DBG_INT_HARDERR    0x00000400  // Debug trap on hard fault
+#define NVIC_DBG_INT_INTERR     0x00000200  // Debug trap on interrupt errors
+#define NVIC_DBG_INT_BUSERR     0x00000100  // Debug trap on bus error
+#define NVIC_DBG_INT_STATERR    0x00000080  // Debug trap on usage fault state
+#define NVIC_DBG_INT_CHKERR     0x00000040  // Debug trap on usage fault check
+#define NVIC_DBG_INT_NOCPERR    0x00000020  // Debug trap on coprocessor error
+#define NVIC_DBG_INT_MMERR      0x00000010  // Debug trap on mem manage fault
+#define NVIC_DBG_INT_RESET      0x00000008  // Core reset status
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004  // Clear pending core reset
+#define NVIC_DBG_INT_RSTPENDING 0x00000002  // Core reset is pending
+#define NVIC_DBG_INT_RSTVCATCH  0x00000001  // Reset vector catch
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SW_TRIG register.
+//
+//*****************************************************************************
+#define NVIC_SW_TRIG_INTID_M    0x000000FF  // Interrupt ID
+#define NVIC_SW_TRIG_INTID_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FPCC register.
+//
+//*****************************************************************************
+#define NVIC_FPCC_ASPEN         0x80000000  // Automatic State Preservation
+                                            // Enable
+#define NVIC_FPCC_LSPEN         0x40000000  // Lazy State Preservation Enable
+#define NVIC_FPCC_MONRDY        0x00000100  // Monitor Ready
+#define NVIC_FPCC_BFRDY         0x00000040  // Bus Fault Ready
+#define NVIC_FPCC_MMRDY         0x00000020  // Memory Management Fault Ready
+#define NVIC_FPCC_HFRDY         0x00000010  // Hard Fault Ready
+#define NVIC_FPCC_THREAD        0x00000008  // Thread Mode
+#define NVIC_FPCC_USER          0x00000002  // User Privilege Level
+#define NVIC_FPCC_LSPACT        0x00000001  // Lazy State Preservation Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FPCA register.
+//
+//*****************************************************************************
+#define NVIC_FPCA_ADDRESS_M     0xFFFFFFF8  // Address
+#define NVIC_FPCA_ADDRESS_S     3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FPDSC register.
+//
+//*****************************************************************************
+#define NVIC_FPDSC_AHP          0x04000000  // AHP Bit Default
+#define NVIC_FPDSC_DN           0x02000000  // DN Bit Default
+#define NVIC_FPDSC_FZ           0x01000000  // FZ Bit Default
+#define NVIC_FPDSC_RMODE_M      0x00C00000  // RMODE Bit Default
+#define NVIC_FPDSC_RMODE_RN     0x00000000  // Round to Nearest (RN) mode
+#define NVIC_FPDSC_RMODE_RP     0x00400000  // Round towards Plus Infinity (RP)
+                                            // mode
+#define NVIC_FPDSC_RMODE_RM     0x00800000  // Round towards Minus Infinity
+                                            // (RM) mode
+#define NVIC_FPDSC_RMODE_RZ     0x00C00000  // Round towards Zero (RZ) mode
+
+#endif // __HW_NVIC_H__
diff --git a/os/common/ext/TivaWare/inc/hw_onewire.h b/os/common/ext/TivaWare/inc/hw_onewire.h
new file mode 100644
index 0000000..8910a7d
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_onewire.h
@@ -0,0 +1,223 @@
+//*****************************************************************************
+//
+// hw_onewire.h - Macros used when accessing the One wire hardware.
+//
+// Copyright (c) 2012-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_ONEWIRE_H__
+#define __HW_ONEWIRE_H__
+
+//*****************************************************************************
+//
+// The following are defines for the One wire register offsets.
+//
+//*****************************************************************************
+#define ONEWIRE_O_CS            0x00000000  // 1-Wire Control and Status
+#define ONEWIRE_O_TIM           0x00000004  // 1-Wire Timing Override
+#define ONEWIRE_O_DATW          0x00000008  // 1-Wire Data Write
+#define ONEWIRE_O_DATR          0x0000000C  // 1-Wire Data Read
+#define ONEWIRE_O_IM            0x00000100  // 1-Wire Interrupt Mask
+#define ONEWIRE_O_RIS           0x00000104  // 1-Wire Raw Interrupt Status
+#define ONEWIRE_O_MIS           0x00000108  // 1-Wire Masked Interrupt Status
+#define ONEWIRE_O_ICR           0x0000010C  // 1-Wire Interrupt Clear
+#define ONEWIRE_O_DMA           0x00000120  // 1-Wire uDMA Control
+#define ONEWIRE_O_PP            0x00000FC0  // 1-Wire Peripheral Properties
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_CS register.
+//
+//*****************************************************************************
+#define ONEWIRE_CS_USEALT       0x80000000  // Two Wire Enable
+#define ONEWIRE_CS_ALTP         0x40000000  // Alternate Polarity Enable
+#define ONEWIRE_CS_BSIZE_M      0x00070000  // Last Byte Size
+#define ONEWIRE_CS_BSIZE_8      0x00000000  // 8 bits (1 byte)
+#define ONEWIRE_CS_BSIZE_1      0x00010000  // 1 bit
+#define ONEWIRE_CS_BSIZE_2      0x00020000  // 2 bits
+#define ONEWIRE_CS_BSIZE_3      0x00030000  // 3 bits
+#define ONEWIRE_CS_BSIZE_4      0x00040000  // 4 bits
+#define ONEWIRE_CS_BSIZE_5      0x00050000  // 5 bits
+#define ONEWIRE_CS_BSIZE_6      0x00060000  // 6 bits
+#define ONEWIRE_CS_BSIZE_7      0x00070000  // 7 bits
+#define ONEWIRE_CS_STUCK        0x00000400  // STUCK Status
+#define ONEWIRE_CS_NOATR        0x00000200  // Answer-to-Reset Status
+#define ONEWIRE_CS_BUSY         0x00000100  // Busy Status
+#define ONEWIRE_CS_SKATR        0x00000080  // Skip Answer-to-Reset Enable
+#define ONEWIRE_CS_LSAM         0x00000040  // Late Sample Enable
+#define ONEWIRE_CS_ODRV         0x00000020  // Overdrive Enable
+#define ONEWIRE_CS_SZ_M         0x00000018  // Data Operation Size
+#define ONEWIRE_CS_OP_M         0x00000006  // Operation Request
+#define ONEWIRE_CS_OP_NONE      0x00000000  // No operation
+#define ONEWIRE_CS_OP_RD        0x00000002  // Read
+#define ONEWIRE_CS_OP_WR        0x00000004  // Write
+#define ONEWIRE_CS_OP_WRRD      0x00000006  // Write/Read
+#define ONEWIRE_CS_RST          0x00000001  // Reset Request
+#define ONEWIRE_CS_SZ_S         3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_TIM register.
+//
+//*****************************************************************************
+#define ONEWIRE_TIM_W1TIM_M     0xF0000000  // Value '1' Timing
+#define ONEWIRE_TIM_W0TIM_M     0x0F800000  // Value '0' Timing
+#define ONEWIRE_TIM_W0REST_M    0x00780000  // Rest Time
+#define ONEWIRE_TIM_W1SAM_M     0x00078000  // Sample Time
+#define ONEWIRE_TIM_ATRSAM_M    0x00007800  // Answer-to-Reset Sample
+#define ONEWIRE_TIM_ATRTIM_M    0x000007C0  // Answer-to-Reset/Rest Period
+#define ONEWIRE_TIM_RSTTIM_M    0x0000003F  // Reset Low Time
+#define ONEWIRE_TIM_W1TIM_S     28
+#define ONEWIRE_TIM_W0TIM_S     23
+#define ONEWIRE_TIM_W0REST_S    19
+#define ONEWIRE_TIM_W1SAM_S     15
+#define ONEWIRE_TIM_ATRSAM_S    11
+#define ONEWIRE_TIM_ATRTIM_S    6
+#define ONEWIRE_TIM_RSTTIM_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_DATW register.
+//
+//*****************************************************************************
+#define ONEWIRE_DATW_B3_M       0xFF000000  // Upper Data Byte
+#define ONEWIRE_DATW_B2_M       0x00FF0000  // Upper Middle Data Byte
+#define ONEWIRE_DATW_B1_M       0x0000FF00  // Lower Middle Data Byte
+#define ONEWIRE_DATW_B0_M       0x000000FF  // Lowest Data Byte
+#define ONEWIRE_DATW_B3_S       24
+#define ONEWIRE_DATW_B2_S       16
+#define ONEWIRE_DATW_B1_S       8
+#define ONEWIRE_DATW_B0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_DATR register.
+//
+//*****************************************************************************
+#define ONEWIRE_DATR_B3_M       0xFF000000  // Upper Data Byte
+#define ONEWIRE_DATR_B2_M       0x00FF0000  // Upper Middle Data Byte
+#define ONEWIRE_DATR_B1_M       0x0000FF00  // Lower Middle Data Byte
+#define ONEWIRE_DATR_B0_M       0x000000FF  // Lowest Data Byte
+#define ONEWIRE_DATR_B3_S       24
+#define ONEWIRE_DATR_B2_S       16
+#define ONEWIRE_DATR_B1_S       8
+#define ONEWIRE_DATR_B0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_IM register.
+//
+//*****************************************************************************
+#define ONEWIRE_IM_DMA          0x00000010  // DMA Done Interrupt Mask
+#define ONEWIRE_IM_STUCK        0x00000008  // Stuck Status Interrupt Mask
+#define ONEWIRE_IM_NOATR        0x00000004  // No Answer-to-Reset Interrupt
+                                            // Mask
+#define ONEWIRE_IM_OPC          0x00000002  // Operation Complete Interrupt
+                                            // Mask
+#define ONEWIRE_IM_RST          0x00000001  // Reset Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_RIS register.
+//
+//*****************************************************************************
+#define ONEWIRE_RIS_DMA         0x00000010  // DMA Done Raw Interrupt Status
+#define ONEWIRE_RIS_STUCK       0x00000008  // Stuck Status Raw Interrupt
+                                            // Status
+#define ONEWIRE_RIS_NOATR       0x00000004  // No Answer-to-Reset Raw Interrupt
+                                            // Status
+#define ONEWIRE_RIS_OPC         0x00000002  // Operation Complete Raw Interrupt
+                                            // Status
+#define ONEWIRE_RIS_RST         0x00000001  // Reset Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_MIS register.
+//
+//*****************************************************************************
+#define ONEWIRE_MIS_DMA         0x00000010  // DMA Done Masked Interrupt Status
+#define ONEWIRE_MIS_STUCK       0x00000008  // Stuck Status Masked Interrupt
+                                            // Status
+#define ONEWIRE_MIS_NOATR       0x00000004  // No Answer-to-Reset Masked
+                                            // Interrupt Status
+#define ONEWIRE_MIS_OPC         0x00000002  // Operation Complete Masked
+                                            // Interrupt Status
+#define ONEWIRE_MIS_RST         0x00000001  // Reset Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_ICR register.
+//
+//*****************************************************************************
+#define ONEWIRE_ICR_DMA         0x00000010  // DMA Done Interrupt Clear
+#define ONEWIRE_ICR_STUCK       0x00000008  // Stuck Status Interrupt Clear
+#define ONEWIRE_ICR_NOATR       0x00000004  // No Answer-to-Reset Interrupt
+                                            // Clear
+#define ONEWIRE_ICR_OPC         0x00000002  // Operation Complete Interrupt
+                                            // Clear
+#define ONEWIRE_ICR_RST         0x00000001  // Reset Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_DMA register.
+//
+//*****************************************************************************
+#define ONEWIRE_DMA_SG          0x00000008  // Scatter-Gather Enable
+#define ONEWIRE_DMA_DMAOP_M     0x00000006  // uDMA Operation
+#define ONEWIRE_DMA_DMAOP_DIS   0x00000000  // uDMA disabled
+#define ONEWIRE_DMA_DMAOP_RDSNG 0x00000002  // uDMA single read: 1-Wire
+                                            // requests uDMA to read
+                                            // ONEWIREDATR register after each
+                                            // read transaction
+#define ONEWIRE_DMA_DMAOP_WRMUL 0x00000004  // uDMA multiple write: 1-Wire
+                                            // requests uDMA to load whenever
+                                            // the ONEWIREDATW register is
+                                            // empty
+#define ONEWIRE_DMA_DMAOP_RDMUL 0x00000006  // uDMA multiple read: An initial
+                                            // read occurs and subsequent reads
+                                            // start after uDMA has read the
+                                            // ONEWIREDATR register
+#define ONEWIRE_DMA_RST         0x00000001  // uDMA Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_PP register.
+//
+//*****************************************************************************
+#define ONEWIRE_PP_DMAP         0x00000010  // uDMA Present
+#define ONEWIRE_PP_CNT_M        0x00000003  // 1-Wire Bus Count
+#define ONEWIRE_PP_CNT_S        0
+
+#endif // __HW_ONEWIRE_H__
diff --git a/os/common/ext/TivaWare/inc/hw_pwm.h b/os/common/ext/TivaWare/inc/hw_pwm.h
new file mode 100644
index 0000000..00d42bf
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_pwm.h
@@ -0,0 +1,1885 @@
+//*****************************************************************************
+//
+// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_PWM_H__
+#define __HW_PWM_H__
+
+//*****************************************************************************
+//
+// The following are defines for the PWM register offsets.
+//
+//*****************************************************************************
+#define PWM_O_CTL               0x00000000  // PWM Master Control
+#define PWM_O_SYNC              0x00000004  // PWM Time Base Sync
+#define PWM_O_ENABLE            0x00000008  // PWM Output Enable
+#define PWM_O_INVERT            0x0000000C  // PWM Output Inversion
+#define PWM_O_FAULT             0x00000010  // PWM Output Fault
+#define PWM_O_INTEN             0x00000014  // PWM Interrupt Enable
+#define PWM_O_RIS               0x00000018  // PWM Raw Interrupt Status
+#define PWM_O_ISC               0x0000001C  // PWM Interrupt Status and Clear
+#define PWM_O_STATUS            0x00000020  // PWM Status
+#define PWM_O_FAULTVAL          0x00000024  // PWM Fault Condition Value
+#define PWM_O_ENUPD             0x00000028  // PWM Enable Update
+#define PWM_O_0_CTL             0x00000040  // PWM0 Control
+#define PWM_O_0_INTEN           0x00000044  // PWM0 Interrupt and Trigger
+                                            // Enable
+#define PWM_O_0_RIS             0x00000048  // PWM0 Raw Interrupt Status
+#define PWM_O_0_ISC             0x0000004C  // PWM0 Interrupt Status and Clear
+#define PWM_O_0_LOAD            0x00000050  // PWM0 Load
+#define PWM_O_0_COUNT           0x00000054  // PWM0 Counter
+#define PWM_O_0_CMPA            0x00000058  // PWM0 Compare A
+#define PWM_O_0_CMPB            0x0000005C  // PWM0 Compare B
+#define PWM_O_0_GENA            0x00000060  // PWM0 Generator A Control
+#define PWM_O_0_GENB            0x00000064  // PWM0 Generator B Control
+#define PWM_O_0_DBCTL           0x00000068  // PWM0 Dead-Band Control
+#define PWM_O_0_DBRISE          0x0000006C  // PWM0 Dead-Band Rising-Edge Delay
+#define PWM_O_0_DBFALL          0x00000070  // PWM0 Dead-Band
+                                            // Falling-Edge-Delay
+#define PWM_O_0_FLTSRC0         0x00000074  // PWM0 Fault Source 0
+#define PWM_O_0_FLTSRC1         0x00000078  // PWM0 Fault Source 1
+#define PWM_O_0_MINFLTPER       0x0000007C  // PWM0 Minimum Fault Period
+#define PWM_O_1_CTL             0x00000080  // PWM1 Control
+#define PWM_O_1_INTEN           0x00000084  // PWM1 Interrupt and Trigger
+                                            // Enable
+#define PWM_O_1_RIS             0x00000088  // PWM1 Raw Interrupt Status
+#define PWM_O_1_ISC             0x0000008C  // PWM1 Interrupt Status and Clear
+#define PWM_O_1_LOAD            0x00000090  // PWM1 Load
+#define PWM_O_1_COUNT           0x00000094  // PWM1 Counter
+#define PWM_O_1_CMPA            0x00000098  // PWM1 Compare A
+#define PWM_O_1_CMPB            0x0000009C  // PWM1 Compare B
+#define PWM_O_1_GENA            0x000000A0  // PWM1 Generator A Control
+#define PWM_O_1_GENB            0x000000A4  // PWM1 Generator B Control
+#define PWM_O_1_DBCTL           0x000000A8  // PWM1 Dead-Band Control
+#define PWM_O_1_DBRISE          0x000000AC  // PWM1 Dead-Band Rising-Edge Delay
+#define PWM_O_1_DBFALL          0x000000B0  // PWM1 Dead-Band
+                                            // Falling-Edge-Delay
+#define PWM_O_1_FLTSRC0         0x000000B4  // PWM1 Fault Source 0
+#define PWM_O_1_FLTSRC1         0x000000B8  // PWM1 Fault Source 1
+#define PWM_O_1_MINFLTPER       0x000000BC  // PWM1 Minimum Fault Period
+#define PWM_O_2_CTL             0x000000C0  // PWM2 Control
+#define PWM_O_2_INTEN           0x000000C4  // PWM2 Interrupt and Trigger
+                                            // Enable
+#define PWM_O_2_RIS             0x000000C8  // PWM2 Raw Interrupt Status
+#define PWM_O_2_ISC             0x000000CC  // PWM2 Interrupt Status and Clear
+#define PWM_O_2_LOAD            0x000000D0  // PWM2 Load
+#define PWM_O_2_COUNT           0x000000D4  // PWM2 Counter
+#define PWM_O_2_CMPA            0x000000D8  // PWM2 Compare A
+#define PWM_O_2_CMPB            0x000000DC  // PWM2 Compare B
+#define PWM_O_2_GENA            0x000000E0  // PWM2 Generator A Control
+#define PWM_O_2_GENB            0x000000E4  // PWM2 Generator B Control
+#define PWM_O_2_DBCTL           0x000000E8  // PWM2 Dead-Band Control
+#define PWM_O_2_DBRISE          0x000000EC  // PWM2 Dead-Band Rising-Edge Delay
+#define PWM_O_2_DBFALL          0x000000F0  // PWM2 Dead-Band
+                                            // Falling-Edge-Delay
+#define PWM_O_2_FLTSRC0         0x000000F4  // PWM2 Fault Source 0
+#define PWM_O_2_FLTSRC1         0x000000F8  // PWM2 Fault Source 1
+#define PWM_O_2_MINFLTPER       0x000000FC  // PWM2 Minimum Fault Period
+#define PWM_O_3_CTL             0x00000100  // PWM3 Control
+#define PWM_O_3_INTEN           0x00000104  // PWM3 Interrupt and Trigger
+                                            // Enable
+#define PWM_O_3_RIS             0x00000108  // PWM3 Raw Interrupt Status
+#define PWM_O_3_ISC             0x0000010C  // PWM3 Interrupt Status and Clear
+#define PWM_O_3_LOAD            0x00000110  // PWM3 Load
+#define PWM_O_3_COUNT           0x00000114  // PWM3 Counter
+#define PWM_O_3_CMPA            0x00000118  // PWM3 Compare A
+#define PWM_O_3_CMPB            0x0000011C  // PWM3 Compare B
+#define PWM_O_3_GENA            0x00000120  // PWM3 Generator A Control
+#define PWM_O_3_GENB            0x00000124  // PWM3 Generator B Control
+#define PWM_O_3_DBCTL           0x00000128  // PWM3 Dead-Band Control
+#define PWM_O_3_DBRISE          0x0000012C  // PWM3 Dead-Band Rising-Edge Delay
+#define PWM_O_3_DBFALL          0x00000130  // PWM3 Dead-Band
+                                            // Falling-Edge-Delay
+#define PWM_O_3_FLTSRC0         0x00000134  // PWM3 Fault Source 0
+#define PWM_O_3_FLTSRC1         0x00000138  // PWM3 Fault Source 1
+#define PWM_O_3_MINFLTPER       0x0000013C  // PWM3 Minimum Fault Period
+#define PWM_O_0_FLTSEN          0x00000800  // PWM0 Fault Pin Logic Sense
+#define PWM_O_0_FLTSTAT0        0x00000804  // PWM0 Fault Status 0
+#define PWM_O_0_FLTSTAT1        0x00000808  // PWM0 Fault Status 1
+#define PWM_O_1_FLTSEN          0x00000880  // PWM1 Fault Pin Logic Sense
+#define PWM_O_1_FLTSTAT0        0x00000884  // PWM1 Fault Status 0
+#define PWM_O_1_FLTSTAT1        0x00000888  // PWM1 Fault Status 1
+#define PWM_O_2_FLTSEN          0x00000900  // PWM2 Fault Pin Logic Sense
+#define PWM_O_2_FLTSTAT0        0x00000904  // PWM2 Fault Status 0
+#define PWM_O_2_FLTSTAT1        0x00000908  // PWM2 Fault Status 1
+#define PWM_O_3_FLTSEN          0x00000980  // PWM3 Fault Pin Logic Sense
+#define PWM_O_3_FLTSTAT0        0x00000984  // PWM3 Fault Status 0
+#define PWM_O_3_FLTSTAT1        0x00000988  // PWM3 Fault Status 1
+#define PWM_O_PP                0x00000FC0  // PWM Peripheral Properties
+#define PWM_O_CC                0x00000FC8  // PWM Clock Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_CTL register.
+//
+//*****************************************************************************
+#define PWM_CTL_GLOBALSYNC3     0x00000008  // Update PWM Generator 3
+#define PWM_CTL_GLOBALSYNC2     0x00000004  // Update PWM Generator 2
+#define PWM_CTL_GLOBALSYNC1     0x00000002  // Update PWM Generator 1
+#define PWM_CTL_GLOBALSYNC0     0x00000001  // Update PWM Generator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_SYNC register.
+//
+//*****************************************************************************
+#define PWM_SYNC_SYNC3          0x00000008  // Reset Generator 3 Counter
+#define PWM_SYNC_SYNC2          0x00000004  // Reset Generator 2 Counter
+#define PWM_SYNC_SYNC1          0x00000002  // Reset Generator 1 Counter
+#define PWM_SYNC_SYNC0          0x00000001  // Reset Generator 0 Counter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ENABLE register.
+//
+//*****************************************************************************
+#define PWM_ENABLE_PWM7EN       0x00000080  // MnPWM7 Output Enable
+#define PWM_ENABLE_PWM6EN       0x00000040  // MnPWM6 Output Enable
+#define PWM_ENABLE_PWM5EN       0x00000020  // MnPWM5 Output Enable
+#define PWM_ENABLE_PWM4EN       0x00000010  // MnPWM4 Output Enable
+#define PWM_ENABLE_PWM3EN       0x00000008  // MnPWM3 Output Enable
+#define PWM_ENABLE_PWM2EN       0x00000004  // MnPWM2 Output Enable
+#define PWM_ENABLE_PWM1EN       0x00000002  // MnPWM1 Output Enable
+#define PWM_ENABLE_PWM0EN       0x00000001  // MnPWM0 Output Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INVERT register.
+//
+//*****************************************************************************
+#define PWM_INVERT_PWM7INV      0x00000080  // Invert MnPWM7 Signal
+#define PWM_INVERT_PWM6INV      0x00000040  // Invert MnPWM6 Signal
+#define PWM_INVERT_PWM5INV      0x00000020  // Invert MnPWM5 Signal
+#define PWM_INVERT_PWM4INV      0x00000010  // Invert MnPWM4 Signal
+#define PWM_INVERT_PWM3INV      0x00000008  // Invert MnPWM3 Signal
+#define PWM_INVERT_PWM2INV      0x00000004  // Invert MnPWM2 Signal
+#define PWM_INVERT_PWM1INV      0x00000002  // Invert MnPWM1 Signal
+#define PWM_INVERT_PWM0INV      0x00000001  // Invert MnPWM0 Signal
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULT register.
+//
+//*****************************************************************************
+#define PWM_FAULT_FAULT7        0x00000080  // MnPWM7 Fault
+#define PWM_FAULT_FAULT6        0x00000040  // MnPWM6 Fault
+#define PWM_FAULT_FAULT5        0x00000020  // MnPWM5 Fault
+#define PWM_FAULT_FAULT4        0x00000010  // MnPWM4 Fault
+#define PWM_FAULT_FAULT3        0x00000008  // MnPWM3 Fault
+#define PWM_FAULT_FAULT2        0x00000004  // MnPWM2 Fault
+#define PWM_FAULT_FAULT1        0x00000002  // MnPWM1 Fault
+#define PWM_FAULT_FAULT0        0x00000001  // MnPWM0 Fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INTEN register.
+//
+//*****************************************************************************
+#define PWM_INTEN_INTFAULT3     0x00080000  // Interrupt Fault 3
+#define PWM_INTEN_INTFAULT2     0x00040000  // Interrupt Fault 2
+#define PWM_INTEN_INTFAULT1     0x00020000  // Interrupt Fault 1
+#define PWM_INTEN_INTFAULT0     0x00010000  // Interrupt Fault 0
+#define PWM_INTEN_INTPWM3       0x00000008  // PWM3 Interrupt Enable
+#define PWM_INTEN_INTPWM2       0x00000004  // PWM2 Interrupt Enable
+#define PWM_INTEN_INTPWM1       0x00000002  // PWM1 Interrupt Enable
+#define PWM_INTEN_INTPWM0       0x00000001  // PWM0 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_RIS register.
+//
+//*****************************************************************************
+#define PWM_RIS_INTFAULT3       0x00080000  // Interrupt Fault PWM 3
+#define PWM_RIS_INTFAULT2       0x00040000  // Interrupt Fault PWM 2
+#define PWM_RIS_INTFAULT1       0x00020000  // Interrupt Fault PWM 1
+#define PWM_RIS_INTFAULT0       0x00010000  // Interrupt Fault PWM 0
+#define PWM_RIS_INTPWM3         0x00000008  // PWM3 Interrupt Asserted
+#define PWM_RIS_INTPWM2         0x00000004  // PWM2 Interrupt Asserted
+#define PWM_RIS_INTPWM1         0x00000002  // PWM1 Interrupt Asserted
+#define PWM_RIS_INTPWM0         0x00000001  // PWM0 Interrupt Asserted
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ISC register.
+//
+//*****************************************************************************
+#define PWM_ISC_INTFAULT3       0x00080000  // FAULT3 Interrupt Asserted
+#define PWM_ISC_INTFAULT2       0x00040000  // FAULT2 Interrupt Asserted
+#define PWM_ISC_INTFAULT1       0x00020000  // FAULT1 Interrupt Asserted
+#define PWM_ISC_INTFAULT0       0x00010000  // FAULT0 Interrupt Asserted
+#define PWM_ISC_INTPWM3         0x00000008  // PWM3 Interrupt Status
+#define PWM_ISC_INTPWM2         0x00000004  // PWM2 Interrupt Status
+#define PWM_ISC_INTPWM1         0x00000002  // PWM1 Interrupt Status
+#define PWM_ISC_INTPWM0         0x00000001  // PWM0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_STATUS register.
+//
+//*****************************************************************************
+#define PWM_STATUS_FAULT3       0x00000008  // Generator 3 Fault Status
+#define PWM_STATUS_FAULT2       0x00000004  // Generator 2 Fault Status
+#define PWM_STATUS_FAULT1       0x00000002  // Generator 1 Fault Status
+#define PWM_STATUS_FAULT0       0x00000001  // Generator 0 Fault Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULTVAL register.
+//
+//*****************************************************************************
+#define PWM_FAULTVAL_PWM7       0x00000080  // MnPWM7 Fault Value
+#define PWM_FAULTVAL_PWM6       0x00000040  // MnPWM6 Fault Value
+#define PWM_FAULTVAL_PWM5       0x00000020  // MnPWM5 Fault Value
+#define PWM_FAULTVAL_PWM4       0x00000010  // MnPWM4 Fault Value
+#define PWM_FAULTVAL_PWM3       0x00000008  // MnPWM3 Fault Value
+#define PWM_FAULTVAL_PWM2       0x00000004  // MnPWM2 Fault Value
+#define PWM_FAULTVAL_PWM1       0x00000002  // MnPWM1 Fault Value
+#define PWM_FAULTVAL_PWM0       0x00000001  // MnPWM0 Fault Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ENUPD register.
+//
+//*****************************************************************************
+#define PWM_ENUPD_ENUPD7_M      0x0000C000  // MnPWM7 Enable Update Mode
+#define PWM_ENUPD_ENUPD7_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD7_LSYNC  0x00008000  // Locally Synchronized
+#define PWM_ENUPD_ENUPD7_GSYNC  0x0000C000  // Globally Synchronized
+#define PWM_ENUPD_ENUPD6_M      0x00003000  // MnPWM6 Enable Update Mode
+#define PWM_ENUPD_ENUPD6_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD6_LSYNC  0x00002000  // Locally Synchronized
+#define PWM_ENUPD_ENUPD6_GSYNC  0x00003000  // Globally Synchronized
+#define PWM_ENUPD_ENUPD5_M      0x00000C00  // MnPWM5 Enable Update Mode
+#define PWM_ENUPD_ENUPD5_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD5_LSYNC  0x00000800  // Locally Synchronized
+#define PWM_ENUPD_ENUPD5_GSYNC  0x00000C00  // Globally Synchronized
+#define PWM_ENUPD_ENUPD4_M      0x00000300  // MnPWM4 Enable Update Mode
+#define PWM_ENUPD_ENUPD4_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD4_LSYNC  0x00000200  // Locally Synchronized
+#define PWM_ENUPD_ENUPD4_GSYNC  0x00000300  // Globally Synchronized
+#define PWM_ENUPD_ENUPD3_M      0x000000C0  // MnPWM3 Enable Update Mode
+#define PWM_ENUPD_ENUPD3_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD3_LSYNC  0x00000080  // Locally Synchronized
+#define PWM_ENUPD_ENUPD3_GSYNC  0x000000C0  // Globally Synchronized
+#define PWM_ENUPD_ENUPD2_M      0x00000030  // MnPWM2 Enable Update Mode
+#define PWM_ENUPD_ENUPD2_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD2_LSYNC  0x00000020  // Locally Synchronized
+#define PWM_ENUPD_ENUPD2_GSYNC  0x00000030  // Globally Synchronized
+#define PWM_ENUPD_ENUPD1_M      0x0000000C  // MnPWM1 Enable Update Mode
+#define PWM_ENUPD_ENUPD1_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD1_LSYNC  0x00000008  // Locally Synchronized
+#define PWM_ENUPD_ENUPD1_GSYNC  0x0000000C  // Globally Synchronized
+#define PWM_ENUPD_ENUPD0_M      0x00000003  // MnPWM0 Enable Update Mode
+#define PWM_ENUPD_ENUPD0_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD0_LSYNC  0x00000002  // Locally Synchronized
+#define PWM_ENUPD_ENUPD0_GSYNC  0x00000003  // Globally Synchronized
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CTL register.
+//
+//*****************************************************************************
+#define PWM_0_CTL_LATCH         0x00040000  // Latch Fault Input
+#define PWM_0_CTL_MINFLTPER     0x00020000  // Minimum Fault Period
+#define PWM_0_CTL_FLTSRC        0x00010000  // Fault Condition Source
+#define PWM_0_CTL_DBFALLUPD_M   0x0000C000  // PWMnDBFALL Update Mode
+#define PWM_0_CTL_DBFALLUPD_I   0x00000000  // Immediate
+#define PWM_0_CTL_DBFALLUPD_LS  0x00008000  // Locally Synchronized
+#define PWM_0_CTL_DBFALLUPD_GS  0x0000C000  // Globally Synchronized
+#define PWM_0_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode
+#define PWM_0_CTL_DBRISEUPD_I   0x00000000  // Immediate
+#define PWM_0_CTL_DBRISEUPD_LS  0x00002000  // Locally Synchronized
+#define PWM_0_CTL_DBRISEUPD_GS  0x00003000  // Globally Synchronized
+#define PWM_0_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode
+#define PWM_0_CTL_DBCTLUPD_I    0x00000000  // Immediate
+#define PWM_0_CTL_DBCTLUPD_LS   0x00000800  // Locally Synchronized
+#define PWM_0_CTL_DBCTLUPD_GS   0x00000C00  // Globally Synchronized
+#define PWM_0_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode
+#define PWM_0_CTL_GENBUPD_I     0x00000000  // Immediate
+#define PWM_0_CTL_GENBUPD_LS    0x00000200  // Locally Synchronized
+#define PWM_0_CTL_GENBUPD_GS    0x00000300  // Globally Synchronized
+#define PWM_0_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode
+#define PWM_0_CTL_GENAUPD_I     0x00000000  // Immediate
+#define PWM_0_CTL_GENAUPD_LS    0x00000080  // Locally Synchronized
+#define PWM_0_CTL_GENAUPD_GS    0x000000C0  // Globally Synchronized
+#define PWM_0_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode
+#define PWM_0_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode
+#define PWM_0_CTL_LOADUPD       0x00000008  // Load Register Update Mode
+#define PWM_0_CTL_DEBUG         0x00000004  // Debug Mode
+#define PWM_0_CTL_MODE          0x00000002  // Counter Mode
+#define PWM_0_CTL_ENABLE        0x00000001  // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_INTEN register.
+//
+//*****************************************************************************
+#define PWM_0_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB
+                                            // Down
+#define PWM_0_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up
+#define PWM_0_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA
+                                            // Down
+#define PWM_0_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up
+#define PWM_0_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD
+#define PWM_0_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0
+#define PWM_0_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB
+                                            // Down
+#define PWM_0_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB
+                                            // Up
+#define PWM_0_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA
+                                            // Down
+#define PWM_0_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA
+                                            // Up
+#define PWM_0_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD
+#define PWM_0_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_RIS register.
+//
+//*****************************************************************************
+#define PWM_0_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+                                            // Status
+#define PWM_0_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status
+#define PWM_0_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+                                            // Status
+#define PWM_0_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status
+#define PWM_0_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status
+#define PWM_0_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_ISC register.
+//
+//*****************************************************************************
+#define PWM_0_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+#define PWM_0_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt
+#define PWM_0_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+#define PWM_0_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt
+#define PWM_0_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt
+#define PWM_0_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_LOAD register.
+//
+//*****************************************************************************
+#define PWM_0_LOAD_M            0x0000FFFF  // Counter Load Value
+#define PWM_0_LOAD_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_COUNT register.
+//
+//*****************************************************************************
+#define PWM_0_COUNT_M           0x0000FFFF  // Counter Value
+#define PWM_0_COUNT_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CMPA register.
+//
+//*****************************************************************************
+#define PWM_0_CMPA_M            0x0000FFFF  // Comparator A Value
+#define PWM_0_CMPA_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CMPB register.
+//
+//*****************************************************************************
+#define PWM_0_CMPB_M            0x0000FFFF  // Comparator B Value
+#define PWM_0_CMPB_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_GENA register.
+//
+//*****************************************************************************
+#define PWM_0_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_0_GENA_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA
+#define PWM_0_GENA_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmA Low
+#define PWM_0_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High
+#define PWM_0_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_0_GENA_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA
+#define PWM_0_GENA_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmA Low
+#define PWM_0_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High
+#define PWM_0_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_0_GENA_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA
+#define PWM_0_GENA_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmA Low
+#define PWM_0_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High
+#define PWM_0_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_0_GENA_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA
+#define PWM_0_GENA_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmA Low
+#define PWM_0_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High
+#define PWM_0_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_0_GENA_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_0_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA
+#define PWM_0_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low
+#define PWM_0_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High
+#define PWM_0_GENA_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_0_GENA_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_0_GENA_ACTZERO_INV  0x00000001  // Invert pwmA
+#define PWM_0_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low
+#define PWM_0_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_GENB register.
+//
+//*****************************************************************************
+#define PWM_0_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_0_GENB_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB
+#define PWM_0_GENB_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmB Low
+#define PWM_0_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High
+#define PWM_0_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_0_GENB_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB
+#define PWM_0_GENB_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmB Low
+#define PWM_0_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High
+#define PWM_0_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_0_GENB_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB
+#define PWM_0_GENB_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmB Low
+#define PWM_0_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High
+#define PWM_0_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_0_GENB_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB
+#define PWM_0_GENB_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmB Low
+#define PWM_0_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High
+#define PWM_0_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_0_GENB_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_0_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB
+#define PWM_0_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low
+#define PWM_0_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High
+#define PWM_0_GENB_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_0_GENB_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_0_GENB_ACTZERO_INV  0x00000001  // Invert pwmB
+#define PWM_0_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low
+#define PWM_0_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_0_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_0_DBRISE_DELAY_M    0x00000FFF  // Dead-Band Rise Delay
+#define PWM_0_DBRISE_DELAY_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_0_DBFALL_DELAY_M    0x00000FFF  // Dead-Band Fall Delay
+#define PWM_0_DBFALL_DELAY_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSRC0_FAULT3    0x00000008  // Fault3 Input
+#define PWM_0_FLTSRC0_FAULT2    0x00000004  // Fault2 Input
+#define PWM_0_FLTSRC0_FAULT1    0x00000002  // Fault1 Input
+#define PWM_0_FLTSRC0_FAULT0    0x00000001  // Fault0 Input
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7
+#define PWM_0_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6
+#define PWM_0_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5
+#define PWM_0_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4
+#define PWM_0_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3
+#define PWM_0_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2
+#define PWM_0_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1
+#define PWM_0_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_0_MINFLTPER_M       0x0000FFFF  // Minimum Fault Period
+#define PWM_0_MINFLTPER_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_CTL register.
+//
+//*****************************************************************************
+#define PWM_1_CTL_LATCH         0x00040000  // Latch Fault Input
+#define PWM_1_CTL_MINFLTPER     0x00020000  // Minimum Fault Period
+#define PWM_1_CTL_FLTSRC        0x00010000  // Fault Condition Source
+#define PWM_1_CTL_DBFALLUPD_M   0x0000C000  // PWMnDBFALL Update Mode
+#define PWM_1_CTL_DBFALLUPD_I   0x00000000  // Immediate
+#define PWM_1_CTL_DBFALLUPD_LS  0x00008000  // Locally Synchronized
+#define PWM_1_CTL_DBFALLUPD_GS  0x0000C000  // Globally Synchronized
+#define PWM_1_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode
+#define PWM_1_CTL_DBRISEUPD_I   0x00000000  // Immediate
+#define PWM_1_CTL_DBRISEUPD_LS  0x00002000  // Locally Synchronized
+#define PWM_1_CTL_DBRISEUPD_GS  0x00003000  // Globally Synchronized
+#define PWM_1_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode
+#define PWM_1_CTL_DBCTLUPD_I    0x00000000  // Immediate
+#define PWM_1_CTL_DBCTLUPD_LS   0x00000800  // Locally Synchronized
+#define PWM_1_CTL_DBCTLUPD_GS   0x00000C00  // Globally Synchronized
+#define PWM_1_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode
+#define PWM_1_CTL_GENBUPD_I     0x00000000  // Immediate
+#define PWM_1_CTL_GENBUPD_LS    0x00000200  // Locally Synchronized
+#define PWM_1_CTL_GENBUPD_GS    0x00000300  // Globally Synchronized
+#define PWM_1_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode
+#define PWM_1_CTL_GENAUPD_I     0x00000000  // Immediate
+#define PWM_1_CTL_GENAUPD_LS    0x00000080  // Locally Synchronized
+#define PWM_1_CTL_GENAUPD_GS    0x000000C0  // Globally Synchronized
+#define PWM_1_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode
+#define PWM_1_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode
+#define PWM_1_CTL_LOADUPD       0x00000008  // Load Register Update Mode
+#define PWM_1_CTL_DEBUG         0x00000004  // Debug Mode
+#define PWM_1_CTL_MODE          0x00000002  // Counter Mode
+#define PWM_1_CTL_ENABLE        0x00000001  // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_INTEN register.
+//
+//*****************************************************************************
+#define PWM_1_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB
+                                            // Down
+#define PWM_1_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up
+#define PWM_1_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA
+                                            // Down
+#define PWM_1_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up
+#define PWM_1_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD
+#define PWM_1_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0
+#define PWM_1_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB
+                                            // Down
+#define PWM_1_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB
+                                            // Up
+#define PWM_1_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA
+                                            // Down
+#define PWM_1_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA
+                                            // Up
+#define PWM_1_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD
+#define PWM_1_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_RIS register.
+//
+//*****************************************************************************
+#define PWM_1_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+                                            // Status
+#define PWM_1_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status
+#define PWM_1_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+                                            // Status
+#define PWM_1_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status
+#define PWM_1_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status
+#define PWM_1_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_ISC register.
+//
+//*****************************************************************************
+#define PWM_1_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+#define PWM_1_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt
+#define PWM_1_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+#define PWM_1_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt
+#define PWM_1_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt
+#define PWM_1_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_LOAD register.
+//
+//*****************************************************************************
+#define PWM_1_LOAD_LOAD_M       0x0000FFFF  // Counter Load Value
+#define PWM_1_LOAD_LOAD_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_COUNT register.
+//
+//*****************************************************************************
+#define PWM_1_COUNT_COUNT_M     0x0000FFFF  // Counter Value
+#define PWM_1_COUNT_COUNT_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_CMPA register.
+//
+//*****************************************************************************
+#define PWM_1_CMPA_COMPA_M      0x0000FFFF  // Comparator A Value
+#define PWM_1_CMPA_COMPA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_CMPB register.
+//
+//*****************************************************************************
+#define PWM_1_CMPB_COMPB_M      0x0000FFFF  // Comparator B Value
+#define PWM_1_CMPB_COMPB_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_GENA register.
+//
+//*****************************************************************************
+#define PWM_1_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_1_GENA_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA
+#define PWM_1_GENA_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmA Low
+#define PWM_1_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High
+#define PWM_1_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_1_GENA_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA
+#define PWM_1_GENA_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmA Low
+#define PWM_1_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High
+#define PWM_1_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_1_GENA_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA
+#define PWM_1_GENA_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmA Low
+#define PWM_1_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High
+#define PWM_1_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_1_GENA_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA
+#define PWM_1_GENA_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmA Low
+#define PWM_1_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High
+#define PWM_1_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_1_GENA_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_1_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA
+#define PWM_1_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low
+#define PWM_1_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High
+#define PWM_1_GENA_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_1_GENA_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_1_GENA_ACTZERO_INV  0x00000001  // Invert pwmA
+#define PWM_1_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low
+#define PWM_1_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_GENB register.
+//
+//*****************************************************************************
+#define PWM_1_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_1_GENB_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB
+#define PWM_1_GENB_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmB Low
+#define PWM_1_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High
+#define PWM_1_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_1_GENB_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB
+#define PWM_1_GENB_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmB Low
+#define PWM_1_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High
+#define PWM_1_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_1_GENB_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB
+#define PWM_1_GENB_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmB Low
+#define PWM_1_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High
+#define PWM_1_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_1_GENB_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB
+#define PWM_1_GENB_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmB Low
+#define PWM_1_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High
+#define PWM_1_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_1_GENB_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_1_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB
+#define PWM_1_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low
+#define PWM_1_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High
+#define PWM_1_GENB_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_1_GENB_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_1_GENB_ACTZERO_INV  0x00000001  // Invert pwmB
+#define PWM_1_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low
+#define PWM_1_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_1_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_1_DBRISE_RISEDELAY_M                                              \
+                                0x00000FFF  // Dead-Band Rise Delay
+#define PWM_1_DBRISE_RISEDELAY_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_1_DBFALL_FALLDELAY_M                                              \
+                                0x00000FFF  // Dead-Band Fall Delay
+#define PWM_1_DBFALL_FALLDELAY_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSRC0_FAULT3    0x00000008  // Fault3 Input
+#define PWM_1_FLTSRC0_FAULT2    0x00000004  // Fault2 Input
+#define PWM_1_FLTSRC0_FAULT1    0x00000002  // Fault1 Input
+#define PWM_1_FLTSRC0_FAULT0    0x00000001  // Fault0 Input
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7
+#define PWM_1_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6
+#define PWM_1_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5
+#define PWM_1_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4
+#define PWM_1_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3
+#define PWM_1_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2
+#define PWM_1_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1
+#define PWM_1_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_1_MINFLTPER_MFP_M   0x0000FFFF  // Minimum Fault Period
+#define PWM_1_MINFLTPER_MFP_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_CTL register.
+//
+//*****************************************************************************
+#define PWM_2_CTL_LATCH         0x00040000  // Latch Fault Input
+#define PWM_2_CTL_MINFLTPER     0x00020000  // Minimum Fault Period
+#define PWM_2_CTL_FLTSRC        0x00010000  // Fault Condition Source
+#define PWM_2_CTL_DBFALLUPD_M   0x0000C000  // PWMnDBFALL Update Mode
+#define PWM_2_CTL_DBFALLUPD_I   0x00000000  // Immediate
+#define PWM_2_CTL_DBFALLUPD_LS  0x00008000  // Locally Synchronized
+#define PWM_2_CTL_DBFALLUPD_GS  0x0000C000  // Globally Synchronized
+#define PWM_2_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode
+#define PWM_2_CTL_DBRISEUPD_I   0x00000000  // Immediate
+#define PWM_2_CTL_DBRISEUPD_LS  0x00002000  // Locally Synchronized
+#define PWM_2_CTL_DBRISEUPD_GS  0x00003000  // Globally Synchronized
+#define PWM_2_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode
+#define PWM_2_CTL_DBCTLUPD_I    0x00000000  // Immediate
+#define PWM_2_CTL_DBCTLUPD_LS   0x00000800  // Locally Synchronized
+#define PWM_2_CTL_DBCTLUPD_GS   0x00000C00  // Globally Synchronized
+#define PWM_2_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode
+#define PWM_2_CTL_GENBUPD_I     0x00000000  // Immediate
+#define PWM_2_CTL_GENBUPD_LS    0x00000200  // Locally Synchronized
+#define PWM_2_CTL_GENBUPD_GS    0x00000300  // Globally Synchronized
+#define PWM_2_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode
+#define PWM_2_CTL_GENAUPD_I     0x00000000  // Immediate
+#define PWM_2_CTL_GENAUPD_LS    0x00000080  // Locally Synchronized
+#define PWM_2_CTL_GENAUPD_GS    0x000000C0  // Globally Synchronized
+#define PWM_2_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode
+#define PWM_2_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode
+#define PWM_2_CTL_LOADUPD       0x00000008  // Load Register Update Mode
+#define PWM_2_CTL_DEBUG         0x00000004  // Debug Mode
+#define PWM_2_CTL_MODE          0x00000002  // Counter Mode
+#define PWM_2_CTL_ENABLE        0x00000001  // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_INTEN register.
+//
+//*****************************************************************************
+#define PWM_2_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB
+                                            // Down
+#define PWM_2_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up
+#define PWM_2_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA
+                                            // Down
+#define PWM_2_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up
+#define PWM_2_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD
+#define PWM_2_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0
+#define PWM_2_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB
+                                            // Down
+#define PWM_2_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB
+                                            // Up
+#define PWM_2_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA
+                                            // Down
+#define PWM_2_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA
+                                            // Up
+#define PWM_2_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD
+#define PWM_2_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_RIS register.
+//
+//*****************************************************************************
+#define PWM_2_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+                                            // Status
+#define PWM_2_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status
+#define PWM_2_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+                                            // Status
+#define PWM_2_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status
+#define PWM_2_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status
+#define PWM_2_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_ISC register.
+//
+//*****************************************************************************
+#define PWM_2_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+#define PWM_2_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt
+#define PWM_2_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+#define PWM_2_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt
+#define PWM_2_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt
+#define PWM_2_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_LOAD register.
+//
+//*****************************************************************************
+#define PWM_2_LOAD_LOAD_M       0x0000FFFF  // Counter Load Value
+#define PWM_2_LOAD_LOAD_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_COUNT register.
+//
+//*****************************************************************************
+#define PWM_2_COUNT_COUNT_M     0x0000FFFF  // Counter Value
+#define PWM_2_COUNT_COUNT_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_CMPA register.
+//
+//*****************************************************************************
+#define PWM_2_CMPA_COMPA_M      0x0000FFFF  // Comparator A Value
+#define PWM_2_CMPA_COMPA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_CMPB register.
+//
+//*****************************************************************************
+#define PWM_2_CMPB_COMPB_M      0x0000FFFF  // Comparator B Value
+#define PWM_2_CMPB_COMPB_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_GENA register.
+//
+//*****************************************************************************
+#define PWM_2_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_2_GENA_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA
+#define PWM_2_GENA_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmA Low
+#define PWM_2_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High
+#define PWM_2_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_2_GENA_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA
+#define PWM_2_GENA_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmA Low
+#define PWM_2_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High
+#define PWM_2_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_2_GENA_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA
+#define PWM_2_GENA_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmA Low
+#define PWM_2_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High
+#define PWM_2_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_2_GENA_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA
+#define PWM_2_GENA_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmA Low
+#define PWM_2_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High
+#define PWM_2_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_2_GENA_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_2_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA
+#define PWM_2_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low
+#define PWM_2_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High
+#define PWM_2_GENA_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_2_GENA_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_2_GENA_ACTZERO_INV  0x00000001  // Invert pwmA
+#define PWM_2_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low
+#define PWM_2_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_GENB register.
+//
+//*****************************************************************************
+#define PWM_2_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_2_GENB_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB
+#define PWM_2_GENB_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmB Low
+#define PWM_2_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High
+#define PWM_2_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_2_GENB_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB
+#define PWM_2_GENB_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmB Low
+#define PWM_2_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High
+#define PWM_2_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_2_GENB_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB
+#define PWM_2_GENB_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmB Low
+#define PWM_2_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High
+#define PWM_2_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_2_GENB_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB
+#define PWM_2_GENB_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmB Low
+#define PWM_2_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High
+#define PWM_2_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_2_GENB_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_2_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB
+#define PWM_2_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low
+#define PWM_2_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High
+#define PWM_2_GENB_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_2_GENB_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_2_GENB_ACTZERO_INV  0x00000001  // Invert pwmB
+#define PWM_2_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low
+#define PWM_2_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_2_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_2_DBRISE_RISEDELAY_M                                              \
+                                0x00000FFF  // Dead-Band Rise Delay
+#define PWM_2_DBRISE_RISEDELAY_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_2_DBFALL_FALLDELAY_M                                              \
+                                0x00000FFF  // Dead-Band Fall Delay
+#define PWM_2_DBFALL_FALLDELAY_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSRC0_FAULT3    0x00000008  // Fault3 Input
+#define PWM_2_FLTSRC0_FAULT2    0x00000004  // Fault2 Input
+#define PWM_2_FLTSRC0_FAULT1    0x00000002  // Fault1 Input
+#define PWM_2_FLTSRC0_FAULT0    0x00000001  // Fault0 Input
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7
+#define PWM_2_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6
+#define PWM_2_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5
+#define PWM_2_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4
+#define PWM_2_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3
+#define PWM_2_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2
+#define PWM_2_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1
+#define PWM_2_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_2_MINFLTPER_MFP_M   0x0000FFFF  // Minimum Fault Period
+#define PWM_2_MINFLTPER_MFP_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_CTL register.
+//
+//*****************************************************************************
+#define PWM_3_CTL_LATCH         0x00040000  // Latch Fault Input
+#define PWM_3_CTL_MINFLTPER     0x00020000  // Minimum Fault Period
+#define PWM_3_CTL_FLTSRC        0x00010000  // Fault Condition Source
+#define PWM_3_CTL_DBFALLUPD_M   0x0000C000  // PWMnDBFALL Update Mode
+#define PWM_3_CTL_DBFALLUPD_I   0x00000000  // Immediate
+#define PWM_3_CTL_DBFALLUPD_LS  0x00008000  // Locally Synchronized
+#define PWM_3_CTL_DBFALLUPD_GS  0x0000C000  // Globally Synchronized
+#define PWM_3_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode
+#define PWM_3_CTL_DBRISEUPD_I   0x00000000  // Immediate
+#define PWM_3_CTL_DBRISEUPD_LS  0x00002000  // Locally Synchronized
+#define PWM_3_CTL_DBRISEUPD_GS  0x00003000  // Globally Synchronized
+#define PWM_3_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode
+#define PWM_3_CTL_DBCTLUPD_I    0x00000000  // Immediate
+#define PWM_3_CTL_DBCTLUPD_LS   0x00000800  // Locally Synchronized
+#define PWM_3_CTL_DBCTLUPD_GS   0x00000C00  // Globally Synchronized
+#define PWM_3_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode
+#define PWM_3_CTL_GENBUPD_I     0x00000000  // Immediate
+#define PWM_3_CTL_GENBUPD_LS    0x00000200  // Locally Synchronized
+#define PWM_3_CTL_GENBUPD_GS    0x00000300  // Globally Synchronized
+#define PWM_3_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode
+#define PWM_3_CTL_GENAUPD_I     0x00000000  // Immediate
+#define PWM_3_CTL_GENAUPD_LS    0x00000080  // Locally Synchronized
+#define PWM_3_CTL_GENAUPD_GS    0x000000C0  // Globally Synchronized
+#define PWM_3_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode
+#define PWM_3_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode
+#define PWM_3_CTL_LOADUPD       0x00000008  // Load Register Update Mode
+#define PWM_3_CTL_DEBUG         0x00000004  // Debug Mode
+#define PWM_3_CTL_MODE          0x00000002  // Counter Mode
+#define PWM_3_CTL_ENABLE        0x00000001  // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_INTEN register.
+//
+//*****************************************************************************
+#define PWM_3_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB
+                                            // Down
+#define PWM_3_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up
+#define PWM_3_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA
+                                            // Down
+#define PWM_3_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up
+#define PWM_3_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD
+#define PWM_3_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0
+#define PWM_3_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB
+                                            // Down
+#define PWM_3_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB
+                                            // Up
+#define PWM_3_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA
+                                            // Down
+#define PWM_3_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA
+                                            // Up
+#define PWM_3_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD
+#define PWM_3_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_RIS register.
+//
+//*****************************************************************************
+#define PWM_3_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+                                            // Status
+#define PWM_3_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status
+#define PWM_3_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+                                            // Status
+#define PWM_3_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status
+#define PWM_3_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status
+#define PWM_3_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_ISC register.
+//
+//*****************************************************************************
+#define PWM_3_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+#define PWM_3_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt
+#define PWM_3_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+#define PWM_3_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt
+#define PWM_3_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt
+#define PWM_3_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_LOAD register.
+//
+//*****************************************************************************
+#define PWM_3_LOAD_LOAD_M       0x0000FFFF  // Counter Load Value
+#define PWM_3_LOAD_LOAD_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_COUNT register.
+//
+//*****************************************************************************
+#define PWM_3_COUNT_COUNT_M     0x0000FFFF  // Counter Value
+#define PWM_3_COUNT_COUNT_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_CMPA register.
+//
+//*****************************************************************************
+#define PWM_3_CMPA_COMPA_M      0x0000FFFF  // Comparator A Value
+#define PWM_3_CMPA_COMPA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_CMPB register.
+//
+//*****************************************************************************
+#define PWM_3_CMPB_COMPB_M      0x0000FFFF  // Comparator B Value
+#define PWM_3_CMPB_COMPB_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_GENA register.
+//
+//*****************************************************************************
+#define PWM_3_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_3_GENA_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA
+#define PWM_3_GENA_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmA Low
+#define PWM_3_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High
+#define PWM_3_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_3_GENA_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA
+#define PWM_3_GENA_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmA Low
+#define PWM_3_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High
+#define PWM_3_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_3_GENA_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA
+#define PWM_3_GENA_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmA Low
+#define PWM_3_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High
+#define PWM_3_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_3_GENA_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA
+#define PWM_3_GENA_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmA Low
+#define PWM_3_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High
+#define PWM_3_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_3_GENA_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_3_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA
+#define PWM_3_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low
+#define PWM_3_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High
+#define PWM_3_GENA_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_3_GENA_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_3_GENA_ACTZERO_INV  0x00000001  // Invert pwmA
+#define PWM_3_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low
+#define PWM_3_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_GENB register.
+//
+//*****************************************************************************
+#define PWM_3_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_3_GENB_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB
+#define PWM_3_GENB_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmB Low
+#define PWM_3_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High
+#define PWM_3_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_3_GENB_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB
+#define PWM_3_GENB_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmB Low
+#define PWM_3_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High
+#define PWM_3_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_3_GENB_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB
+#define PWM_3_GENB_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmB Low
+#define PWM_3_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High
+#define PWM_3_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_3_GENB_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB
+#define PWM_3_GENB_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmB Low
+#define PWM_3_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High
+#define PWM_3_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_3_GENB_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_3_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB
+#define PWM_3_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low
+#define PWM_3_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High
+#define PWM_3_GENB_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_3_GENB_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_3_GENB_ACTZERO_INV  0x00000001  // Invert pwmB
+#define PWM_3_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low
+#define PWM_3_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_3_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_3_DBRISE_RISEDELAY_M                                              \
+                                0x00000FFF  // Dead-Band Rise Delay
+#define PWM_3_DBRISE_RISEDELAY_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_3_DBFALL_FALLDELAY_M                                              \
+                                0x00000FFF  // Dead-Band Fall Delay
+#define PWM_3_DBFALL_FALLDELAY_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSRC0_FAULT3    0x00000008  // Fault3 Input
+#define PWM_3_FLTSRC0_FAULT2    0x00000004  // Fault2 Input
+#define PWM_3_FLTSRC0_FAULT1    0x00000002  // Fault1 Input
+#define PWM_3_FLTSRC0_FAULT0    0x00000001  // Fault0 Input
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7
+#define PWM_3_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6
+#define PWM_3_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5
+#define PWM_3_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4
+#define PWM_3_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3
+#define PWM_3_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2
+#define PWM_3_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1
+#define PWM_3_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_3_MINFLTPER_MFP_M   0x0000FFFF  // Minimum Fault Period
+#define PWM_3_MINFLTPER_MFP_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSEN_FAULT3     0x00000008  // Fault3 Sense
+#define PWM_0_FLTSEN_FAULT2     0x00000004  // Fault2 Sense
+#define PWM_0_FLTSEN_FAULT1     0x00000002  // Fault1 Sense
+#define PWM_0_FLTSEN_FAULT0     0x00000001  // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSTAT0_FAULT3   0x00000008  // Fault Input 3
+#define PWM_0_FLTSTAT0_FAULT2   0x00000004  // Fault Input 2
+#define PWM_0_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1
+#define PWM_0_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger
+#define PWM_0_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger
+#define PWM_0_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger
+#define PWM_0_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger
+#define PWM_0_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger
+#define PWM_0_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger
+#define PWM_0_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger
+#define PWM_0_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSEN_FAULT3     0x00000008  // Fault3 Sense
+#define PWM_1_FLTSEN_FAULT2     0x00000004  // Fault2 Sense
+#define PWM_1_FLTSEN_FAULT1     0x00000002  // Fault1 Sense
+#define PWM_1_FLTSEN_FAULT0     0x00000001  // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSTAT0_FAULT3   0x00000008  // Fault Input 3
+#define PWM_1_FLTSTAT0_FAULT2   0x00000004  // Fault Input 2
+#define PWM_1_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1
+#define PWM_1_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger
+#define PWM_1_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger
+#define PWM_1_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger
+#define PWM_1_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger
+#define PWM_1_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger
+#define PWM_1_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger
+#define PWM_1_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger
+#define PWM_1_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSEN_FAULT3     0x00000008  // Fault3 Sense
+#define PWM_2_FLTSEN_FAULT2     0x00000004  // Fault2 Sense
+#define PWM_2_FLTSEN_FAULT1     0x00000002  // Fault1 Sense
+#define PWM_2_FLTSEN_FAULT0     0x00000001  // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSTAT0_FAULT3   0x00000008  // Fault Input 3
+#define PWM_2_FLTSTAT0_FAULT2   0x00000004  // Fault Input 2
+#define PWM_2_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1
+#define PWM_2_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger
+#define PWM_2_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger
+#define PWM_2_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger
+#define PWM_2_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger
+#define PWM_2_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger
+#define PWM_2_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger
+#define PWM_2_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger
+#define PWM_2_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSEN_FAULT3     0x00000008  // Fault3 Sense
+#define PWM_3_FLTSEN_FAULT2     0x00000004  // Fault2 Sense
+#define PWM_3_FLTSEN_FAULT1     0x00000002  // Fault1 Sense
+#define PWM_3_FLTSEN_FAULT0     0x00000001  // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSTAT0_FAULT3   0x00000008  // Fault Input 3
+#define PWM_3_FLTSTAT0_FAULT2   0x00000004  // Fault Input 2
+#define PWM_3_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1
+#define PWM_3_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger
+#define PWM_3_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger
+#define PWM_3_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger
+#define PWM_3_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger
+#define PWM_3_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger
+#define PWM_3_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger
+#define PWM_3_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger
+#define PWM_3_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_PP register.
+//
+//*****************************************************************************
+#define PWM_PP_GCNT_M           0x0000000F  // Generators
+#define PWM_PP_FCNT_M           0x000000F0  // Fault Inputs (per PWM unit)
+#define PWM_PP_ESYNC            0x00000100  // Extended Synchronization
+#define PWM_PP_EFAULT           0x00000200  // Extended Fault
+#define PWM_PP_ONE              0x00000400  // One-Shot Mode
+#define PWM_PP_GCNT_S           0
+#define PWM_PP_FCNT_S           4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_CC register.
+//
+//*****************************************************************************
+#define PWM_CC_USEPWM           0x00000100  // Use PWM Clock Divisor
+#define PWM_CC_PWMDIV_M         0x00000007  // PWM Clock Divider
+#define PWM_CC_PWMDIV_2         0x00000000  // /2
+#define PWM_CC_PWMDIV_4         0x00000001  // /4
+#define PWM_CC_PWMDIV_8         0x00000002  // /8
+#define PWM_CC_PWMDIV_16        0x00000003  // /16
+#define PWM_CC_PWMDIV_32        0x00000004  // /32
+#define PWM_CC_PWMDIV_64        0x00000005  // /64
+
+//*****************************************************************************
+//
+// The following are defines for the PWM Generator standard offsets.
+//
+//*****************************************************************************
+#define PWM_O_X_CTL             0x00000000  // Gen Control Reg
+#define PWM_O_X_INTEN           0x00000004  // Gen Int/Trig Enable Reg
+#define PWM_O_X_RIS             0x00000008  // Gen Raw Int Status Reg
+#define PWM_O_X_ISC             0x0000000C  // Gen Int Status Reg
+#define PWM_O_X_LOAD            0x00000010  // Gen Load Reg
+#define PWM_O_X_COUNT           0x00000014  // Gen Counter Reg
+#define PWM_O_X_CMPA            0x00000018  // Gen Compare A Reg
+#define PWM_O_X_CMPB            0x0000001C  // Gen Compare B Reg
+#define PWM_O_X_GENA            0x00000020  // Gen Generator A Ctrl Reg
+#define PWM_O_X_GENB            0x00000024  // Gen Generator B Ctrl Reg
+#define PWM_O_X_DBCTL           0x00000028  // Gen Dead Band Ctrl Reg
+#define PWM_O_X_DBRISE          0x0000002C  // Gen DB Rising Edge Delay Reg
+#define PWM_O_X_DBFALL          0x00000030  // Gen DB Falling Edge Delay Reg
+#define PWM_O_X_FLTSRC0         0x00000034  // Fault pin, comparator condition
+#define PWM_O_X_FLTSRC1         0x00000038  // Digital comparator condition
+#define PWM_O_X_MINFLTPER       0x0000003C  // Fault minimum period extension
+#define PWM_GEN_0_OFFSET        0x00000040  // PWM0 base
+#define PWM_GEN_1_OFFSET        0x00000080  // PWM1 base
+#define PWM_GEN_2_OFFSET        0x000000C0  // PWM2 base
+#define PWM_GEN_3_OFFSET        0x00000100  // PWM3 base
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CTL register.
+//
+//*****************************************************************************
+#define PWM_X_CTL_LATCH         0x00040000  // Latch Fault Input
+#define PWM_X_CTL_MINFLTPER     0x00020000  // Minimum Fault Period
+#define PWM_X_CTL_FLTSRC        0x00010000  // Fault Condition Source
+#define PWM_X_CTL_DBFALLUPD_M   0x0000C000  // PWMnDBFALL Update Mode
+#define PWM_X_CTL_DBFALLUPD_I   0x00000000  // Immediate
+#define PWM_X_CTL_DBFALLUPD_LS  0x00008000  // Locally Synchronized
+#define PWM_X_CTL_DBFALLUPD_GS  0x0000C000  // Globally Synchronized
+#define PWM_X_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode
+#define PWM_X_CTL_DBRISEUPD_I   0x00000000  // Immediate
+#define PWM_X_CTL_DBRISEUPD_LS  0x00002000  // Locally Synchronized
+#define PWM_X_CTL_DBRISEUPD_GS  0x00003000  // Globally Synchronized
+#define PWM_X_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode
+#define PWM_X_CTL_DBCTLUPD_I    0x00000000  // Immediate
+#define PWM_X_CTL_DBCTLUPD_LS   0x00000800  // Locally Synchronized
+#define PWM_X_CTL_DBCTLUPD_GS   0x00000C00  // Globally Synchronized
+#define PWM_X_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode
+#define PWM_X_CTL_GENBUPD_I     0x00000000  // Immediate
+#define PWM_X_CTL_GENBUPD_LS    0x00000200  // Locally Synchronized
+#define PWM_X_CTL_GENBUPD_GS    0x00000300  // Globally Synchronized
+#define PWM_X_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode
+#define PWM_X_CTL_GENAUPD_I     0x00000000  // Immediate
+#define PWM_X_CTL_GENAUPD_LS    0x00000080  // Locally Synchronized
+#define PWM_X_CTL_GENAUPD_GS    0x000000C0  // Globally Synchronized
+#define PWM_X_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode
+#define PWM_X_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode
+#define PWM_X_CTL_LOADUPD       0x00000008  // Load Register Update Mode
+#define PWM_X_CTL_DEBUG         0x00000004  // Debug Mode
+#define PWM_X_CTL_MODE          0x00000002  // Counter Mode
+#define PWM_X_CTL_ENABLE        0x00000001  // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_INTEN register.
+//
+//*****************************************************************************
+#define PWM_X_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB
+                                            // Down
+#define PWM_X_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up
+#define PWM_X_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA
+                                            // Down
+#define PWM_X_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up
+#define PWM_X_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD
+#define PWM_X_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0
+#define PWM_X_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB
+                                            // Down
+#define PWM_X_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB
+                                            // Up
+#define PWM_X_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA
+                                            // Down
+#define PWM_X_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA
+                                            // Up
+#define PWM_X_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD
+#define PWM_X_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_RIS register.
+//
+//*****************************************************************************
+#define PWM_X_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+                                            // Status
+#define PWM_X_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status
+#define PWM_X_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+                                            // Status
+#define PWM_X_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status
+#define PWM_X_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status
+#define PWM_X_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_ISC register.
+//
+//*****************************************************************************
+#define PWM_X_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+#define PWM_X_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt
+#define PWM_X_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+#define PWM_X_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt
+#define PWM_X_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt
+#define PWM_X_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_LOAD register.
+//
+//*****************************************************************************
+#define PWM_X_LOAD_M            0x0000FFFF  // Counter Load Value
+#define PWM_X_LOAD_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_COUNT register.
+//
+//*****************************************************************************
+#define PWM_X_COUNT_M           0x0000FFFF  // Counter Value
+#define PWM_X_COUNT_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CMPA register.
+//
+//*****************************************************************************
+#define PWM_X_CMPA_M            0x0000FFFF  // Comparator A Value
+#define PWM_X_CMPA_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CMPB register.
+//
+//*****************************************************************************
+#define PWM_X_CMPB_M            0x0000FFFF  // Comparator B Value
+#define PWM_X_CMPB_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_GENA register.
+//
+//*****************************************************************************
+#define PWM_X_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_X_GENA_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA
+#define PWM_X_GENA_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High
+#define PWM_X_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_X_GENA_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA
+#define PWM_X_GENA_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High
+#define PWM_X_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_X_GENA_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA
+#define PWM_X_GENA_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High
+#define PWM_X_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_X_GENA_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA
+#define PWM_X_GENA_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High
+#define PWM_X_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_X_GENA_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_X_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA
+#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low
+#define PWM_X_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High
+#define PWM_X_GENA_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_X_GENA_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_X_GENA_ACTZERO_INV  0x00000001  // Invert pwmA
+#define PWM_X_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low
+#define PWM_X_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_GENB register.
+//
+//*****************************************************************************
+#define PWM_X_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_X_GENB_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB
+#define PWM_X_GENB_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High
+#define PWM_X_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_X_GENB_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB
+#define PWM_X_GENB_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High
+#define PWM_X_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_X_GENB_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB
+#define PWM_X_GENB_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High
+#define PWM_X_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_X_GENB_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB
+#define PWM_X_GENB_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High
+#define PWM_X_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_X_GENB_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_X_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB
+#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low
+#define PWM_X_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High
+#define PWM_X_GENB_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_X_GENB_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_X_GENB_ACTZERO_INV  0x00000001  // Invert pwmB
+#define PWM_X_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low
+#define PWM_X_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_X_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_X_DBRISE_DELAY_M    0x00000FFF  // Dead-Band Rise Delay
+#define PWM_X_DBRISE_DELAY_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_X_DBFALL_DELAY_M    0x00000FFF  // Dead-Band Fall Delay
+#define PWM_X_DBFALL_DELAY_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSRC0_FAULT3    0x00000008  // Fault3 Input
+#define PWM_X_FLTSRC0_FAULT2    0x00000004  // Fault2 Input
+#define PWM_X_FLTSRC0_FAULT1    0x00000002  // Fault1 Input
+#define PWM_X_FLTSRC0_FAULT0    0x00000001  // Fault0 Input
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7
+#define PWM_X_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6
+#define PWM_X_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5
+#define PWM_X_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4
+#define PWM_X_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3
+#define PWM_X_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2
+#define PWM_X_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1
+#define PWM_X_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_X_MINFLTPER_M       0x0000FFFF  // Minimum Fault Period
+#define PWM_X_MINFLTPER_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the PWM Generator extended offsets.
+//
+//*****************************************************************************
+#define PWM_O_X_FLTSEN          0x00000000  // Fault logic sense
+#define PWM_O_X_FLTSTAT0        0x00000004  // Pin and comparator status
+#define PWM_O_X_FLTSTAT1        0x00000008  // Digital comparator status
+#define PWM_EXT_0_OFFSET        0x00000800  // PWM0 extended base
+#define PWM_EXT_1_OFFSET        0x00000880  // PWM1 extended base
+#define PWM_EXT_2_OFFSET        0x00000900  // PWM2 extended base
+#define PWM_EXT_3_OFFSET        0x00000980  // PWM3 extended base
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSEN_FAULT3     0x00000008  // Fault3 Sense
+#define PWM_X_FLTSEN_FAULT2     0x00000004  // Fault2 Sense
+#define PWM_X_FLTSEN_FAULT1     0x00000002  // Fault1 Sense
+#define PWM_X_FLTSEN_FAULT0     0x00000001  // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSTAT0_FAULT3   0x00000008  // Fault Input 3
+#define PWM_X_FLTSTAT0_FAULT2   0x00000004  // Fault Input 2
+#define PWM_X_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1
+#define PWM_X_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger
+#define PWM_X_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger
+#define PWM_X_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger
+#define PWM_X_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger
+#define PWM_X_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger
+#define PWM_X_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger
+#define PWM_X_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger
+#define PWM_X_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger
+
+#endif // __HW_PWM_H__
diff --git a/os/common/ext/TivaWare/inc/hw_qei.h b/os/common/ext/TivaWare/inc/hw_qei.h
new file mode 100644
index 0000000..93c4a07
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_qei.h
@@ -0,0 +1,178 @@
+//*****************************************************************************
+//
+// hw_qei.h - Macros used when accessing the QEI hardware.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_QEI_H__
+#define __HW_QEI_H__
+
+//*****************************************************************************
+//
+// The following are defines for the QEI register offsets.
+//
+//*****************************************************************************
+#define QEI_O_CTL               0x00000000  // QEI Control
+#define QEI_O_STAT              0x00000004  // QEI Status
+#define QEI_O_POS               0x00000008  // QEI Position
+#define QEI_O_MAXPOS            0x0000000C  // QEI Maximum Position
+#define QEI_O_LOAD              0x00000010  // QEI Timer Load
+#define QEI_O_TIME              0x00000014  // QEI Timer
+#define QEI_O_COUNT             0x00000018  // QEI Velocity Counter
+#define QEI_O_SPEED             0x0000001C  // QEI Velocity
+#define QEI_O_INTEN             0x00000020  // QEI Interrupt Enable
+#define QEI_O_RIS               0x00000024  // QEI Raw Interrupt Status
+#define QEI_O_ISC               0x00000028  // QEI Interrupt Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_CTL register.
+//
+//*****************************************************************************
+#define QEI_CTL_FILTCNT_M       0x000F0000  // Input Filter Prescale Count
+#define QEI_CTL_FILTEN          0x00002000  // Enable Input Filter
+#define QEI_CTL_STALLEN         0x00001000  // Stall QEI
+#define QEI_CTL_INVI            0x00000800  // Invert Index Pulse
+#define QEI_CTL_INVB            0x00000400  // Invert PhB
+#define QEI_CTL_INVA            0x00000200  // Invert PhA
+#define QEI_CTL_VELDIV_M        0x000001C0  // Predivide Velocity
+#define QEI_CTL_VELDIV_1        0x00000000  // QEI clock /1
+#define QEI_CTL_VELDIV_2        0x00000040  // QEI clock /2
+#define QEI_CTL_VELDIV_4        0x00000080  // QEI clock /4
+#define QEI_CTL_VELDIV_8        0x000000C0  // QEI clock /8
+#define QEI_CTL_VELDIV_16       0x00000100  // QEI clock /16
+#define QEI_CTL_VELDIV_32       0x00000140  // QEI clock /32
+#define QEI_CTL_VELDIV_64       0x00000180  // QEI clock /64
+#define QEI_CTL_VELDIV_128      0x000001C0  // QEI clock /128
+#define QEI_CTL_VELEN           0x00000020  // Capture Velocity
+#define QEI_CTL_RESMODE         0x00000010  // Reset Mode
+#define QEI_CTL_CAPMODE         0x00000008  // Capture Mode
+#define QEI_CTL_SIGMODE         0x00000004  // Signal Mode
+#define QEI_CTL_SWAP            0x00000002  // Swap Signals
+#define QEI_CTL_ENABLE          0x00000001  // Enable QEI
+#define QEI_CTL_FILTCNT_S       16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_STAT register.
+//
+//*****************************************************************************
+#define QEI_STAT_DIRECTION      0x00000002  // Direction of Rotation
+#define QEI_STAT_ERROR          0x00000001  // Error Detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_POS register.
+//
+//*****************************************************************************
+#define QEI_POS_M               0xFFFFFFFF  // Current Position Integrator
+                                            // Value
+#define QEI_POS_S               0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_MAXPOS register.
+//
+//*****************************************************************************
+#define QEI_MAXPOS_M            0xFFFFFFFF  // Maximum Position Integrator
+                                            // Value
+#define QEI_MAXPOS_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_LOAD register.
+//
+//*****************************************************************************
+#define QEI_LOAD_M              0xFFFFFFFF  // Velocity Timer Load Value
+#define QEI_LOAD_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_TIME register.
+//
+//*****************************************************************************
+#define QEI_TIME_M              0xFFFFFFFF  // Velocity Timer Current Value
+#define QEI_TIME_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_COUNT register.
+//
+//*****************************************************************************
+#define QEI_COUNT_M             0xFFFFFFFF  // Velocity Pulse Count
+#define QEI_COUNT_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_SPEED register.
+//
+//*****************************************************************************
+#define QEI_SPEED_M             0xFFFFFFFF  // Velocity
+#define QEI_SPEED_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_INTEN register.
+//
+//*****************************************************************************
+#define QEI_INTEN_ERROR         0x00000008  // Phase Error Interrupt Enable
+#define QEI_INTEN_DIR           0x00000004  // Direction Change Interrupt
+                                            // Enable
+#define QEI_INTEN_TIMER         0x00000002  // Timer Expires Interrupt Enable
+#define QEI_INTEN_INDEX         0x00000001  // Index Pulse Detected Interrupt
+                                            // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_RIS register.
+//
+//*****************************************************************************
+#define QEI_RIS_ERROR           0x00000008  // Phase Error Detected
+#define QEI_RIS_DIR             0x00000004  // Direction Change Detected
+#define QEI_RIS_TIMER           0x00000002  // Velocity Timer Expired
+#define QEI_RIS_INDEX           0x00000001  // Index Pulse Asserted
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_ISC register.
+//
+//*****************************************************************************
+#define QEI_ISC_ERROR           0x00000008  // Phase Error Interrupt
+#define QEI_ISC_DIR             0x00000004  // Direction Change Interrupt
+#define QEI_ISC_TIMER           0x00000002  // Velocity Timer Expired Interrupt
+#define QEI_ISC_INDEX           0x00000001  // Index Pulse Interrupt
+
+#endif // __HW_QEI_H__
diff --git a/os/common/ext/TivaWare/inc/hw_shamd5.h b/os/common/ext/TivaWare/inc/hw_shamd5.h
new file mode 100644
index 0000000..1f697fe
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_shamd5.h
@@ -0,0 +1,548 @@
+//*****************************************************************************
+//
+// hw_shamd5.h - Macros used when accessing the SHA/MD5 hardware.
+//
+// Copyright (c) 2012-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_SHAMD5_H__
+#define __HW_SHAMD5_H__
+
+//*****************************************************************************
+//
+// The following are defines for the SHA/MD5 register offsets.
+//
+//*****************************************************************************
+#define SHAMD5_O_ODIGEST_A      0x00000000  // SHA Outer Digest A
+#define SHAMD5_O_ODIGEST_B      0x00000004  // SHA Outer Digest B
+#define SHAMD5_O_ODIGEST_C      0x00000008  // SHA Outer Digest C
+#define SHAMD5_O_ODIGEST_D      0x0000000C  // SHA Outer Digest D
+#define SHAMD5_O_ODIGEST_E      0x00000010  // SHA Outer Digest E
+#define SHAMD5_O_ODIGEST_F      0x00000014  // SHA Outer Digest F
+#define SHAMD5_O_ODIGEST_G      0x00000018  // SHA Outer Digest G
+#define SHAMD5_O_ODIGEST_H      0x0000001C  // SHA Outer Digest H
+#define SHAMD5_O_IDIGEST_A      0x00000020  // SHA Inner Digest A
+#define SHAMD5_O_IDIGEST_B      0x00000024  // SHA Inner Digest B
+#define SHAMD5_O_IDIGEST_C      0x00000028  // SHA Inner Digest C
+#define SHAMD5_O_IDIGEST_D      0x0000002C  // SHA Inner Digest D
+#define SHAMD5_O_IDIGEST_E      0x00000030  // SHA Inner Digest E
+#define SHAMD5_O_IDIGEST_F      0x00000034  // SHA Inner Digest F
+#define SHAMD5_O_IDIGEST_G      0x00000038  // SHA Inner Digest G
+#define SHAMD5_O_IDIGEST_H      0x0000003C  // SHA Inner Digest H
+#define SHAMD5_O_DIGEST_COUNT   0x00000040  // SHA Digest Count
+#define SHAMD5_O_MODE           0x00000044  // SHA Mode
+#define SHAMD5_O_LENGTH         0x00000048  // SHA Length
+#define SHAMD5_O_DATA_0_IN      0x00000080  // SHA Data 0 Input
+#define SHAMD5_O_DATA_1_IN      0x00000084  // SHA Data 1 Input
+#define SHAMD5_O_DATA_2_IN      0x00000088  // SHA Data 2 Input
+#define SHAMD5_O_DATA_3_IN      0x0000008C  // SHA Data 3 Input
+#define SHAMD5_O_DATA_4_IN      0x00000090  // SHA Data 4 Input
+#define SHAMD5_O_DATA_5_IN      0x00000094  // SHA Data 5 Input
+#define SHAMD5_O_DATA_6_IN      0x00000098  // SHA Data 6 Input
+#define SHAMD5_O_DATA_7_IN      0x0000009C  // SHA Data 7 Input
+#define SHAMD5_O_DATA_8_IN      0x000000A0  // SHA Data 8 Input
+#define SHAMD5_O_DATA_9_IN      0x000000A4  // SHA Data 9 Input
+#define SHAMD5_O_DATA_10_IN     0x000000A8  // SHA Data 10 Input
+#define SHAMD5_O_DATA_11_IN     0x000000AC  // SHA Data 11 Input
+#define SHAMD5_O_DATA_12_IN     0x000000B0  // SHA Data 12 Input
+#define SHAMD5_O_DATA_13_IN     0x000000B4  // SHA Data 13 Input
+#define SHAMD5_O_DATA_14_IN     0x000000B8  // SHA Data 14 Input
+#define SHAMD5_O_DATA_15_IN     0x000000BC  // SHA Data 15 Input
+#define SHAMD5_O_REVISION       0x00000100  // SHA Revision
+#define SHAMD5_O_SYSCONFIG      0x00000110  // SHA System Configuration
+#define SHAMD5_O_SYSSTATUS      0x00000114  // SHA System Status
+#define SHAMD5_O_IRQSTATUS      0x00000118  // SHA Interrupt Status
+#define SHAMD5_O_IRQENABLE      0x0000011C  // SHA Interrupt Enable
+#define SHAMD5_O_DMAIM          0xFFFFC010  // SHA DMA Interrupt Mask
+#define SHAMD5_O_DMARIS         0xFFFFC014  // SHA DMA Raw Interrupt Status
+#define SHAMD5_O_DMAMIS         0xFFFFC018  // SHA DMA Masked Interrupt Status
+#define SHAMD5_O_DMAIC          0xFFFFC01C  // SHA DMA Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_A
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_A_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_ODIGEST_A_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_B
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_B_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_ODIGEST_B_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_C
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_C_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_ODIGEST_C_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_D
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_D_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_ODIGEST_D_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_E
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_E_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_ODIGEST_E_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_F
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_F_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_ODIGEST_F_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_G
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_G_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_ODIGEST_G_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_H
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_H_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_ODIGEST_H_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_A
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_A_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_IDIGEST_A_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_B
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_B_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_IDIGEST_B_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_C
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_C_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_IDIGEST_C_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_D
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_D_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_IDIGEST_D_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_E
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_E_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_IDIGEST_E_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_F
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_F_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_IDIGEST_F_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_G
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_G_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_IDIGEST_G_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_H
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_H_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_IDIGEST_H_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DIGEST_COUNT
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DIGEST_COUNT_M   0xFFFFFFFF  // Digest Count
+#define SHAMD5_DIGEST_COUNT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_MODE register.
+//
+//*****************************************************************************
+#define SHAMD5_MODE_HMAC_OUTER_HASH                                           \
+                                0x00000080  // HMAC Outer Hash Processing
+                                            // Enable
+#define SHAMD5_MODE_HMAC_KEY_PROC                                             \
+                                0x00000020  // HMAC Key Processing Enable
+#define SHAMD5_MODE_CLOSE_HASH  0x00000010  // Performs the padding, the
+                                            // Hash/HMAC will be 'closed' at
+                                            // the end of the block, as per
+                                            // MD5/SHA-1/SHA-2 specification
+#define SHAMD5_MODE_ALGO_CONSTANT                                             \
+                                0x00000008  // The initial digest register will
+                                            // be overwritten with the
+                                            // algorithm constants for the
+                                            // selected algorithm when hashing
+                                            // and the initial digest count
+                                            // register will be reset to 0
+#define SHAMD5_MODE_ALGO_M      0x00000007  // Hash Algorithm
+#define SHAMD5_MODE_ALGO_MD5    0x00000000  // MD5
+#define SHAMD5_MODE_ALGO_SHA1   0x00000002  // SHA-1
+#define SHAMD5_MODE_ALGO_SHA224 0x00000004  // SHA-224
+#define SHAMD5_MODE_ALGO_SHA256 0x00000006  // SHA-256
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_LENGTH
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_LENGTH_M         0xFFFFFFFF  // Block Length/Remaining Byte
+                                            // Count
+#define SHAMD5_LENGTH_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_0_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_0_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_0_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_1_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_1_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_1_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_2_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_2_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_2_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_3_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_3_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_3_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_4_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_4_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_4_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_5_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_5_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_5_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_6_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_6_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_6_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_7_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_7_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_7_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_8_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_8_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_8_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_9_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_9_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_9_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_10_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_10_IN_DATA_M                                              \
+                                0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_10_IN_DATA_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_11_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_11_IN_DATA_M                                              \
+                                0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_11_IN_DATA_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_12_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_12_IN_DATA_M                                              \
+                                0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_12_IN_DATA_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_13_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_13_IN_DATA_M                                              \
+                                0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_13_IN_DATA_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_14_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_14_IN_DATA_M                                              \
+                                0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_14_IN_DATA_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_15_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_15_IN_DATA_M                                              \
+                                0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_15_IN_DATA_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_REVISION
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_REVISION_M       0xFFFFFFFF  // Revision Number
+#define SHAMD5_REVISION_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_SYSCONFIG
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_SYSCONFIG_SADVANCED                                            \
+                                0x00000080  // Advanced Mode Enable
+#define SHAMD5_SYSCONFIG_SIDLE_M                                              \
+                                0x00000030  // Sidle mode
+#define SHAMD5_SYSCONFIG_SIDLE_FORCE                                          \
+                                0x00000000  // Force-idle mode
+#define SHAMD5_SYSCONFIG_DMA_EN 0x00000008  // uDMA Request Enable
+#define SHAMD5_SYSCONFIG_IT_EN  0x00000004  // Interrupt Enable
+#define SHAMD5_SYSCONFIG_SOFTRESET                                            \
+                                0x00000002  // Soft reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_SYSSTATUS
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_SYSSTATUS_RESETDONE                                            \
+                                0x00000001  // Reset done status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IRQSTATUS
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IRQSTATUS_CONTEXT_READY                                        \
+                                0x00000008  // Context Ready Status
+#define SHAMD5_IRQSTATUS_INPUT_READY                                          \
+                                0x00000002  // Input Ready Status
+#define SHAMD5_IRQSTATUS_OUTPUT_READY                                         \
+                                0x00000001  // Output Ready Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IRQENABLE
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IRQENABLE_CONTEXT_READY                                        \
+                                0x00000008  // Mask for context ready interrupt
+#define SHAMD5_IRQENABLE_INPUT_READY                                          \
+                                0x00000002  // Mask for input ready interrupt
+#define SHAMD5_IRQENABLE_OUTPUT_READY                                         \
+                                0x00000001  // Mask for output ready interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DMAIM register.
+//
+//*****************************************************************************
+#define SHAMD5_DMAIM_COUT       0x00000004  // Context Out DMA Done Interrupt
+                                            // Mask
+#define SHAMD5_DMAIM_DIN        0x00000002  // Data In DMA Done Interrupt Mask
+#define SHAMD5_DMAIM_CIN        0x00000001  // Context In DMA Done Interrupt
+                                            // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DMARIS
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DMARIS_COUT      0x00000004  // Context Out DMA Done Raw
+                                            // Interrupt Status
+#define SHAMD5_DMARIS_DIN       0x00000002  // Data In DMA Done Raw Interrupt
+                                            // Status
+#define SHAMD5_DMARIS_CIN       0x00000001  // Context In DMA Done Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DMAMIS
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DMAMIS_COUT      0x00000004  // Context Out DMA Done Masked
+                                            // Interrupt Status
+#define SHAMD5_DMAMIS_DIN       0x00000002  // Data In DMA Done Masked
+                                            // Interrupt Status
+#define SHAMD5_DMAMIS_CIN       0x00000001  // Context In DMA Done Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DMAIC register.
+//
+//*****************************************************************************
+#define SHAMD5_DMAIC_COUT       0x00000004  // Context Out DMA Done Masked
+                                            // Interrupt Status
+#define SHAMD5_DMAIC_DIN        0x00000002  // Data In DMA Done Interrupt Clear
+#define SHAMD5_DMAIC_CIN        0x00000001  // Context In DMA Done Raw
+                                            // Interrupt Status
+
+#endif // __HW_SHAMD5_H__
diff --git a/os/common/ext/TivaWare/inc/hw_ssi.h b/os/common/ext/TivaWare/inc/hw_ssi.h
new file mode 100644
index 0000000..3a1503d
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_ssi.h
@@ -0,0 +1,237 @@
+//*****************************************************************************
+//
+// hw_ssi.h - Macros used when accessing the SSI hardware.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_SSI_H__
+#define __HW_SSI_H__
+
+//*****************************************************************************
+//
+// The following are defines for the SSI register offsets.
+//
+//*****************************************************************************
+#define SSI_O_CR0               0x00000000  // SSI Control 0
+#define SSI_O_CR1               0x00000004  // SSI Control 1
+#define SSI_O_DR                0x00000008  // SSI Data
+#define SSI_O_SR                0x0000000C  // SSI Status
+#define SSI_O_CPSR              0x00000010  // SSI Clock Prescale
+#define SSI_O_IM                0x00000014  // SSI Interrupt Mask
+#define SSI_O_RIS               0x00000018  // SSI Raw Interrupt Status
+#define SSI_O_MIS               0x0000001C  // SSI Masked Interrupt Status
+#define SSI_O_ICR               0x00000020  // SSI Interrupt Clear
+#define SSI_O_DMACTL            0x00000024  // SSI DMA Control
+#define SSI_O_PP                0x00000FC0  // SSI Peripheral Properties
+#define SSI_O_CC                0x00000FC8  // SSI Clock Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR0 register.
+//
+//*****************************************************************************
+#define SSI_CR0_SCR_M           0x0000FF00  // SSI Serial Clock Rate
+#define SSI_CR0_SPH             0x00000080  // SSI Serial Clock Phase
+#define SSI_CR0_SPO             0x00000040  // SSI Serial Clock Polarity
+#define SSI_CR0_FRF_M           0x00000030  // SSI Frame Format Select
+#define SSI_CR0_FRF_MOTO        0x00000000  // Freescale SPI Frame Format
+#define SSI_CR0_FRF_TI          0x00000010  // Synchronous Serial Frame Format
+#define SSI_CR0_FRF_NMW         0x00000020  // MICROWIRE Frame Format
+#define SSI_CR0_DSS_M           0x0000000F  // SSI Data Size Select
+#define SSI_CR0_DSS_4           0x00000003  // 4-bit data
+#define SSI_CR0_DSS_5           0x00000004  // 5-bit data
+#define SSI_CR0_DSS_6           0x00000005  // 6-bit data
+#define SSI_CR0_DSS_7           0x00000006  // 7-bit data
+#define SSI_CR0_DSS_8           0x00000007  // 8-bit data
+#define SSI_CR0_DSS_9           0x00000008  // 9-bit data
+#define SSI_CR0_DSS_10          0x00000009  // 10-bit data
+#define SSI_CR0_DSS_11          0x0000000A  // 11-bit data
+#define SSI_CR0_DSS_12          0x0000000B  // 12-bit data
+#define SSI_CR0_DSS_13          0x0000000C  // 13-bit data
+#define SSI_CR0_DSS_14          0x0000000D  // 14-bit data
+#define SSI_CR0_DSS_15          0x0000000E  // 15-bit data
+#define SSI_CR0_DSS_16          0x0000000F  // 16-bit data
+#define SSI_CR0_SCR_S           8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR1 register.
+//
+//*****************************************************************************
+#define SSI_CR1_EOM             0x00000800  // Stop Frame (End of Message)
+#define SSI_CR1_FSSHLDFRM       0x00000400  // FSS Hold Frame
+#define SSI_CR1_HSCLKEN         0x00000200  // High Speed Clock Enable
+#define SSI_CR1_DIR             0x00000100  // SSI Direction of Operation
+#define SSI_CR1_MODE_M          0x000000C0  // SSI Mode
+#define SSI_CR1_MODE_LEGACY     0x00000000  // Legacy SSI mode
+#define SSI_CR1_MODE_BI         0x00000040  // Bi-SSI mode
+#define SSI_CR1_MODE_QUAD       0x00000080  // Quad-SSI Mode
+#define SSI_CR1_MODE_ADVANCED   0x000000C0  // Advanced SSI Mode with 8-bit
+                                            // packet size
+#define SSI_CR1_EOT             0x00000010  // End of Transmission
+#define SSI_CR1_MS              0x00000004  // SSI Master/Slave Select
+#define SSI_CR1_SSE             0x00000002  // SSI Synchronous Serial Port
+                                            // Enable
+#define SSI_CR1_LBM             0x00000001  // SSI Loopback Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DR register.
+//
+//*****************************************************************************
+#define SSI_DR_DATA_M           0x0000FFFF  // SSI Receive/Transmit Data
+#define SSI_DR_DATA_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_SR register.
+//
+//*****************************************************************************
+#define SSI_SR_BSY              0x00000010  // SSI Busy Bit
+#define SSI_SR_RFF              0x00000008  // SSI Receive FIFO Full
+#define SSI_SR_RNE              0x00000004  // SSI Receive FIFO Not Empty
+#define SSI_SR_TNF              0x00000002  // SSI Transmit FIFO Not Full
+#define SSI_SR_TFE              0x00000001  // SSI Transmit FIFO Empty
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CPSR register.
+//
+//*****************************************************************************
+#define SSI_CPSR_CPSDVSR_M      0x000000FF  // SSI Clock Prescale Divisor
+#define SSI_CPSR_CPSDVSR_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_IM register.
+//
+//*****************************************************************************
+#define SSI_IM_EOTIM            0x00000040  // End of Transmit Interrupt Mask
+#define SSI_IM_DMATXIM          0x00000020  // SSI Transmit DMA Interrupt Mask
+#define SSI_IM_DMARXIM          0x00000010  // SSI Receive DMA Interrupt Mask
+#define SSI_IM_TXIM             0x00000008  // SSI Transmit FIFO Interrupt Mask
+#define SSI_IM_RXIM             0x00000004  // SSI Receive FIFO Interrupt Mask
+#define SSI_IM_RTIM             0x00000002  // SSI Receive Time-Out Interrupt
+                                            // Mask
+#define SSI_IM_RORIM            0x00000001  // SSI Receive Overrun Interrupt
+                                            // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_RIS register.
+//
+//*****************************************************************************
+#define SSI_RIS_EOTRIS          0x00000040  // End of Transmit Raw Interrupt
+                                            // Status
+#define SSI_RIS_DMATXRIS        0x00000020  // SSI Transmit DMA Raw Interrupt
+                                            // Status
+#define SSI_RIS_DMARXRIS        0x00000010  // SSI Receive DMA Raw Interrupt
+                                            // Status
+#define SSI_RIS_TXRIS           0x00000008  // SSI Transmit FIFO Raw Interrupt
+                                            // Status
+#define SSI_RIS_RXRIS           0x00000004  // SSI Receive FIFO Raw Interrupt
+                                            // Status
+#define SSI_RIS_RTRIS           0x00000002  // SSI Receive Time-Out Raw
+                                            // Interrupt Status
+#define SSI_RIS_RORRIS          0x00000001  // SSI Receive Overrun Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_MIS register.
+//
+//*****************************************************************************
+#define SSI_MIS_EOTMIS          0x00000040  // End of Transmit Masked Interrupt
+                                            // Status
+#define SSI_MIS_DMATXMIS        0x00000020  // SSI Transmit DMA Masked
+                                            // Interrupt Status
+#define SSI_MIS_DMARXMIS        0x00000010  // SSI Receive DMA Masked Interrupt
+                                            // Status
+#define SSI_MIS_TXMIS           0x00000008  // SSI Transmit FIFO Masked
+                                            // Interrupt Status
+#define SSI_MIS_RXMIS           0x00000004  // SSI Receive FIFO Masked
+                                            // Interrupt Status
+#define SSI_MIS_RTMIS           0x00000002  // SSI Receive Time-Out Masked
+                                            // Interrupt Status
+#define SSI_MIS_RORMIS          0x00000001  // SSI Receive Overrun Masked
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_ICR register.
+//
+//*****************************************************************************
+#define SSI_ICR_EOTIC           0x00000040  // End of Transmit Interrupt Clear
+#define SSI_ICR_DMATXIC         0x00000020  // SSI Transmit DMA Interrupt Clear
+#define SSI_ICR_DMARXIC         0x00000010  // SSI Receive DMA Interrupt Clear
+#define SSI_ICR_RTIC            0x00000002  // SSI Receive Time-Out Interrupt
+                                            // Clear
+#define SSI_ICR_RORIC           0x00000001  // SSI Receive Overrun Interrupt
+                                            // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DMACTL register.
+//
+//*****************************************************************************
+#define SSI_DMACTL_TXDMAE       0x00000002  // Transmit DMA Enable
+#define SSI_DMACTL_RXDMAE       0x00000001  // Receive DMA Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_PP register.
+//
+//*****************************************************************************
+#define SSI_PP_FSSHLDFRM        0x00000008  // FSS Hold Frame Capability
+#define SSI_PP_MODE_M           0x00000006  // Mode of Operation
+#define SSI_PP_MODE_LEGACY      0x00000000  // Legacy SSI mode
+#define SSI_PP_MODE_ADVBI       0x00000002  // Legacy mode, Advanced SSI mode
+                                            // and Bi-SSI mode enabled
+#define SSI_PP_MODE_ADVBIQUAD   0x00000004  // Legacy mode, Advanced mode,
+                                            // Bi-SSI and Quad-SSI mode enabled
+#define SSI_PP_HSCLK            0x00000001  // High Speed Capability
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CC register.
+//
+//*****************************************************************************
+#define SSI_CC_CS_M             0x0000000F  // SSI Baud Clock Source
+#define SSI_CC_CS_SYSPLL        0x00000000  // System clock (based on clock
+                                            // source and divisor factor)
+#define SSI_CC_CS_PIOSC         0x00000005  // PIOSC
+
+#endif // __HW_SSI_H__
diff --git a/os/common/ext/TivaWare/inc/hw_sysctl.h b/os/common/ext/TivaWare/inc/hw_sysctl.h
new file mode 100644
index 0000000..6f78204
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_sysctl.h
@@ -0,0 +1,3749 @@
+//*****************************************************************************
+//
+// hw_sysctl.h - Macros used when accessing the system control hardware.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_SYSCTL_H__
+#define __HW_SYSCTL_H__
+
+//*****************************************************************************
+//
+// The following are defines for the System Control register addresses.
+//
+//*****************************************************************************
+#define SYSCTL_DID0             0x400FE000  // Device Identification 0
+#define SYSCTL_DID1             0x400FE004  // Device Identification 1
+#define SYSCTL_DC0              0x400FE008  // Device Capabilities 0
+#define SYSCTL_DC1              0x400FE010  // Device Capabilities 1
+#define SYSCTL_DC2              0x400FE014  // Device Capabilities 2
+#define SYSCTL_DC3              0x400FE018  // Device Capabilities 3
+#define SYSCTL_DC4              0x400FE01C  // Device Capabilities 4
+#define SYSCTL_DC5              0x400FE020  // Device Capabilities 5
+#define SYSCTL_DC6              0x400FE024  // Device Capabilities 6
+#define SYSCTL_DC7              0x400FE028  // Device Capabilities 7
+#define SYSCTL_DC8              0x400FE02C  // Device Capabilities 8
+#define SYSCTL_PBORCTL          0x400FE030  // Brown-Out Reset Control
+#define SYSCTL_PTBOCTL          0x400FE038  // Power-Temp Brown Out Control
+#define SYSCTL_SRCR0            0x400FE040  // Software Reset Control 0
+#define SYSCTL_SRCR1            0x400FE044  // Software Reset Control 1
+#define SYSCTL_SRCR2            0x400FE048  // Software Reset Control 2
+#define SYSCTL_RIS              0x400FE050  // Raw Interrupt Status
+#define SYSCTL_IMC              0x400FE054  // Interrupt Mask Control
+#define SYSCTL_MISC             0x400FE058  // Masked Interrupt Status and
+                                            // Clear
+#define SYSCTL_RESC             0x400FE05C  // Reset Cause
+#define SYSCTL_PWRTC            0x400FE060  // Power-Temperature Cause
+#define SYSCTL_RCC              0x400FE060  // Run-Mode Clock Configuration
+#define SYSCTL_NMIC             0x400FE064  // NMI Cause Register
+#define SYSCTL_GPIOHBCTL        0x400FE06C  // GPIO High-Performance Bus
+                                            // Control
+#define SYSCTL_RCC2             0x400FE070  // Run-Mode Clock Configuration 2
+#define SYSCTL_MOSCCTL          0x400FE07C  // Main Oscillator Control
+#define SYSCTL_RSCLKCFG         0x400FE0B0  // Run and Sleep Mode Configuration
+                                            // Register
+#define SYSCTL_MEMTIM0          0x400FE0C0  // Memory Timing Parameter Register
+                                            // 0 for Main Flash and EEPROM
+#define SYSCTL_RCGC0            0x400FE100  // Run Mode Clock Gating Control
+                                            // Register 0
+#define SYSCTL_RCGC1            0x400FE104  // Run Mode Clock Gating Control
+                                            // Register 1
+#define SYSCTL_RCGC2            0x400FE108  // Run Mode Clock Gating Control
+                                            // Register 2
+#define SYSCTL_SCGC0            0x400FE110  // Sleep Mode Clock Gating Control
+                                            // Register 0
+#define SYSCTL_SCGC1            0x400FE114  // Sleep Mode Clock Gating Control
+                                            // Register 1
+#define SYSCTL_SCGC2            0x400FE118  // Sleep Mode Clock Gating Control
+                                            // Register 2
+#define SYSCTL_DCGC0            0x400FE120  // Deep Sleep Mode Clock Gating
+                                            // Control Register 0
+#define SYSCTL_DCGC1            0x400FE124  // Deep-Sleep Mode Clock Gating
+                                            // Control Register 1
+#define SYSCTL_DCGC2            0x400FE128  // Deep Sleep Mode Clock Gating
+                                            // Control Register 2
+#define SYSCTL_ALTCLKCFG        0x400FE138  // Alternate Clock Configuration
+#define SYSCTL_DSLPCLKCFG       0x400FE144  // Deep Sleep Clock Configuration
+#define SYSCTL_DSCLKCFG         0x400FE144  // Deep Sleep Clock Configuration
+                                            // Register
+#define SYSCTL_DIVSCLK          0x400FE148  // Divisor and Source Clock
+                                            // Configuration
+#define SYSCTL_SYSPROP          0x400FE14C  // System Properties
+#define SYSCTL_PIOSCCAL         0x400FE150  // Precision Internal Oscillator
+                                            // Calibration
+#define SYSCTL_PIOSCSTAT        0x400FE154  // Precision Internal Oscillator
+                                            // Statistics
+#define SYSCTL_PLLFREQ0         0x400FE160  // PLL Frequency 0
+#define SYSCTL_PLLFREQ1         0x400FE164  // PLL Frequency 1
+#define SYSCTL_PLLSTAT          0x400FE168  // PLL Status
+#define SYSCTL_SLPPWRCFG        0x400FE188  // Sleep Power Configuration
+#define SYSCTL_DSLPPWRCFG       0x400FE18C  // Deep-Sleep Power Configuration
+#define SYSCTL_DC9              0x400FE190  // Device Capabilities 9
+#define SYSCTL_NVMSTAT          0x400FE1A0  // Non-Volatile Memory Information
+#define SYSCTL_LDOSPCTL         0x400FE1B4  // LDO Sleep Power Control
+#define SYSCTL_LDODPCTL         0x400FE1BC  // LDO Deep-Sleep Power Control
+#define SYSCTL_RESBEHAVCTL      0x400FE1D8  // Reset Behavior Control Register
+#define SYSCTL_HSSR             0x400FE1F4  // Hardware System Service Request
+#define SYSCTL_USBPDS           0x400FE280  // USB Power Domain Status
+#define SYSCTL_USBMPC           0x400FE284  // USB Memory Power Control
+#define SYSCTL_EMACPDS          0x400FE288  // Ethernet MAC Power Domain Status
+#define SYSCTL_EMACMPC          0x400FE28C  // Ethernet MAC Memory Power
+                                            // Control
+#define SYSCTL_LCDMPC           0x400FE294  // LCD Memory Power Control
+#define SYSCTL_PPWD             0x400FE300  // Watchdog Timer Peripheral
+                                            // Present
+#define SYSCTL_PPTIMER          0x400FE304  // 16/32-Bit General-Purpose Timer
+                                            // Peripheral Present
+#define SYSCTL_PPGPIO           0x400FE308  // General-Purpose Input/Output
+                                            // Peripheral Present
+#define SYSCTL_PPDMA            0x400FE30C  // Micro Direct Memory Access
+                                            // Peripheral Present
+#define SYSCTL_PPEPI            0x400FE310  // EPI Peripheral Present
+#define SYSCTL_PPHIB            0x400FE314  // Hibernation Peripheral Present
+#define SYSCTL_PPUART           0x400FE318  // Universal Asynchronous
+                                            // Receiver/Transmitter Peripheral
+                                            // Present
+#define SYSCTL_PPSSI            0x400FE31C  // Synchronous Serial Interface
+                                            // Peripheral Present
+#define SYSCTL_PPI2C            0x400FE320  // Inter-Integrated Circuit
+                                            // Peripheral Present
+#define SYSCTL_PPUSB            0x400FE328  // Universal Serial Bus Peripheral
+                                            // Present
+#define SYSCTL_PPEPHY           0x400FE330  // Ethernet PHY Peripheral Present
+#define SYSCTL_PPCAN            0x400FE334  // Controller Area Network
+                                            // Peripheral Present
+#define SYSCTL_PPADC            0x400FE338  // Analog-to-Digital Converter
+                                            // Peripheral Present
+#define SYSCTL_PPACMP           0x400FE33C  // Analog Comparator Peripheral
+                                            // Present
+#define SYSCTL_PPPWM            0x400FE340  // Pulse Width Modulator Peripheral
+                                            // Present
+#define SYSCTL_PPQEI            0x400FE344  // Quadrature Encoder Interface
+                                            // Peripheral Present
+#define SYSCTL_PPLPC            0x400FE348  // Low Pin Count Interface
+                                            // Peripheral Present
+#define SYSCTL_PPPECI           0x400FE350  // Platform Environment Control
+                                            // Interface Peripheral Present
+#define SYSCTL_PPFAN            0x400FE354  // Fan Control Peripheral Present
+#define SYSCTL_PPEEPROM         0x400FE358  // EEPROM Peripheral Present
+#define SYSCTL_PPWTIMER         0x400FE35C  // 32/64-Bit Wide General-Purpose
+                                            // Timer Peripheral Present
+#define SYSCTL_PPRTS            0x400FE370  // Remote Temperature Sensor
+                                            // Peripheral Present
+#define SYSCTL_PPCCM            0x400FE374  // CRC and Cryptographic Modules
+                                            // Peripheral Present
+#define SYSCTL_PPLCD            0x400FE390  // LCD Peripheral Present
+#define SYSCTL_PPOWIRE          0x400FE398  // 1-Wire Peripheral Present
+#define SYSCTL_PPEMAC           0x400FE39C  // Ethernet MAC Peripheral Present
+#define SYSCTL_PPHIM            0x400FE3A4  // Human Interface Master
+                                            // Peripheral Present
+#define SYSCTL_SRWD             0x400FE500  // Watchdog Timer Software Reset
+#define SYSCTL_SRTIMER          0x400FE504  // 16/32-Bit General-Purpose Timer
+                                            // Software Reset
+#define SYSCTL_SRGPIO           0x400FE508  // General-Purpose Input/Output
+                                            // Software Reset
+#define SYSCTL_SRDMA            0x400FE50C  // Micro Direct Memory Access
+                                            // Software Reset
+#define SYSCTL_SREPI            0x400FE510  // EPI Software Reset
+#define SYSCTL_SRHIB            0x400FE514  // Hibernation Software Reset
+#define SYSCTL_SRUART           0x400FE518  // Universal Asynchronous
+                                            // Receiver/Transmitter Software
+                                            // Reset
+#define SYSCTL_SRSSI            0x400FE51C  // Synchronous Serial Interface
+                                            // Software Reset
+#define SYSCTL_SRI2C            0x400FE520  // Inter-Integrated Circuit
+                                            // Software Reset
+#define SYSCTL_SRUSB            0x400FE528  // Universal Serial Bus Software
+                                            // Reset
+#define SYSCTL_SREPHY           0x400FE530  // Ethernet PHY Software Reset
+#define SYSCTL_SRCAN            0x400FE534  // Controller Area Network Software
+                                            // Reset
+#define SYSCTL_SRADC            0x400FE538  // Analog-to-Digital Converter
+                                            // Software Reset
+#define SYSCTL_SRACMP           0x400FE53C  // Analog Comparator Software Reset
+#define SYSCTL_SRPWM            0x400FE540  // Pulse Width Modulator Software
+                                            // Reset
+#define SYSCTL_SRQEI            0x400FE544  // Quadrature Encoder Interface
+                                            // Software Reset
+#define SYSCTL_SREEPROM         0x400FE558  // EEPROM Software Reset
+#define SYSCTL_SRWTIMER         0x400FE55C  // 32/64-Bit Wide General-Purpose
+                                            // Timer Software Reset
+#define SYSCTL_SRCCM            0x400FE574  // CRC and Cryptographic Modules
+                                            // Software Reset
+#define SYSCTL_SRLCD            0x400FE590  // LCD Controller Software Reset
+#define SYSCTL_SROWIRE          0x400FE598  // 1-Wire Software Reset
+#define SYSCTL_SREMAC           0x400FE59C  // Ethernet MAC Software Reset
+#define SYSCTL_RCGCWD           0x400FE600  // Watchdog Timer Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCTIMER        0x400FE604  // 16/32-Bit General-Purpose Timer
+                                            // Run Mode Clock Gating Control
+#define SYSCTL_RCGCGPIO         0x400FE608  // General-Purpose Input/Output Run
+                                            // Mode Clock Gating Control
+#define SYSCTL_RCGCDMA          0x400FE60C  // Micro Direct Memory Access Run
+                                            // Mode Clock Gating Control
+#define SYSCTL_RCGCEPI          0x400FE610  // EPI Run Mode Clock Gating
+                                            // Control
+#define SYSCTL_RCGCHIB          0x400FE614  // Hibernation Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART         0x400FE618  // Universal Asynchronous
+                                            // Receiver/Transmitter Run Mode
+                                            // Clock Gating Control
+#define SYSCTL_RCGCSSI          0x400FE61C  // Synchronous Serial Interface Run
+                                            // Mode Clock Gating Control
+#define SYSCTL_RCGCI2C          0x400FE620  // Inter-Integrated Circuit Run
+                                            // Mode Clock Gating Control
+#define SYSCTL_RCGCUSB          0x400FE628  // Universal Serial Bus Run Mode
+                                            // Clock Gating Control
+#define SYSCTL_RCGCEPHY         0x400FE630  // Ethernet PHY Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCCAN          0x400FE634  // Controller Area Network Run Mode
+                                            // Clock Gating Control
+#define SYSCTL_RCGCADC          0x400FE638  // Analog-to-Digital Converter Run
+                                            // Mode Clock Gating Control
+#define SYSCTL_RCGCACMP         0x400FE63C  // Analog Comparator Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCPWM          0x400FE640  // Pulse Width Modulator Run Mode
+                                            // Clock Gating Control
+#define SYSCTL_RCGCQEI          0x400FE644  // Quadrature Encoder Interface Run
+                                            // Mode Clock Gating Control
+#define SYSCTL_RCGCEEPROM       0x400FE658  // EEPROM Run Mode Clock Gating
+                                            // Control
+#define SYSCTL_RCGCWTIMER       0x400FE65C  // 32/64-Bit Wide General-Purpose
+                                            // Timer Run Mode Clock Gating
+                                            // Control
+#define SYSCTL_RCGCCCM          0x400FE674  // CRC and Cryptographic Modules
+                                            // Run Mode Clock Gating Control
+#define SYSCTL_RCGCLCD          0x400FE690  // LCD Controller Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCOWIRE        0x400FE698  // 1-Wire Run Mode Clock Gating
+                                            // Control
+#define SYSCTL_RCGCEMAC         0x400FE69C  // Ethernet MAC Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCWD           0x400FE700  // Watchdog Timer Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCTIMER        0x400FE704  // 16/32-Bit General-Purpose Timer
+                                            // Sleep Mode Clock Gating Control
+#define SYSCTL_SCGCGPIO         0x400FE708  // General-Purpose Input/Output
+                                            // Sleep Mode Clock Gating Control
+#define SYSCTL_SCGCDMA          0x400FE70C  // Micro Direct Memory Access Sleep
+                                            // Mode Clock Gating Control
+#define SYSCTL_SCGCEPI          0x400FE710  // EPI Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCHIB          0x400FE714  // Hibernation Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART         0x400FE718  // Universal Asynchronous
+                                            // Receiver/Transmitter Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_SCGCSSI          0x400FE71C  // Synchronous Serial Interface
+                                            // Sleep Mode Clock Gating Control
+#define SYSCTL_SCGCI2C          0x400FE720  // Inter-Integrated Circuit Sleep
+                                            // Mode Clock Gating Control
+#define SYSCTL_SCGCUSB          0x400FE728  // Universal Serial Bus Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_SCGCEPHY         0x400FE730  // Ethernet PHY Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCCAN          0x400FE734  // Controller Area Network Sleep
+                                            // Mode Clock Gating Control
+#define SYSCTL_SCGCADC          0x400FE738  // Analog-to-Digital Converter
+                                            // Sleep Mode Clock Gating Control
+#define SYSCTL_SCGCACMP         0x400FE73C  // Analog Comparator Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_SCGCPWM          0x400FE740  // Pulse Width Modulator Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_SCGCQEI          0x400FE744  // Quadrature Encoder Interface
+                                            // Sleep Mode Clock Gating Control
+#define SYSCTL_SCGCEEPROM       0x400FE758  // EEPROM Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCWTIMER       0x400FE75C  // 32/64-Bit Wide General-Purpose
+                                            // Timer Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCCCM          0x400FE774  // CRC and Cryptographic Modules
+                                            // Sleep Mode Clock Gating Control
+#define SYSCTL_SCGCLCD          0x400FE790  // LCD Controller Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCOWIRE        0x400FE798  // 1-Wire Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCEMAC         0x400FE79C  // Ethernet MAC Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_DCGCWD           0x400FE800  // Watchdog Timer Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCTIMER        0x400FE804  // 16/32-Bit General-Purpose Timer
+                                            // Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCGPIO         0x400FE808  // General-Purpose Input/Output
+                                            // Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCDMA          0x400FE80C  // Micro Direct Memory Access
+                                            // Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCEPI          0x400FE810  // EPI Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCHIB          0x400FE814  // Hibernation Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART         0x400FE818  // Universal Asynchronous
+                                            // Receiver/Transmitter Deep-Sleep
+                                            // Mode Clock Gating Control
+#define SYSCTL_DCGCSSI          0x400FE81C  // Synchronous Serial Interface
+                                            // Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCI2C          0x400FE820  // Inter-Integrated Circuit
+                                            // Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCUSB          0x400FE828  // Universal Serial Bus Deep-Sleep
+                                            // Mode Clock Gating Control
+#define SYSCTL_DCGCEPHY         0x400FE830  // Ethernet PHY Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCCAN          0x400FE834  // Controller Area Network
+                                            // Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCADC          0x400FE838  // Analog-to-Digital Converter
+                                            // Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCACMP         0x400FE83C  // Analog Comparator Deep-Sleep
+                                            // Mode Clock Gating Control
+#define SYSCTL_DCGCPWM          0x400FE840  // Pulse Width Modulator Deep-Sleep
+                                            // Mode Clock Gating Control
+#define SYSCTL_DCGCQEI          0x400FE844  // Quadrature Encoder Interface
+                                            // Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCEEPROM       0x400FE858  // EEPROM Deep-Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_DCGCWTIMER       0x400FE85C  // 32/64-Bit Wide General-Purpose
+                                            // Timer Deep-Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_DCGCCCM          0x400FE874  // CRC and Cryptographic Modules
+                                            // Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCLCD          0x400FE890  // LCD Controller Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCOWIRE        0x400FE898  // 1-Wire Deep-Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_DCGCEMAC         0x400FE89C  // Ethernet MAC Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_PCWD             0x400FE900  // Watchdog Timer Power Control
+#define SYSCTL_PCTIMER          0x400FE904  // 16/32-Bit General-Purpose Timer
+                                            // Power Control
+#define SYSCTL_PCGPIO           0x400FE908  // General-Purpose Input/Output
+                                            // Power Control
+#define SYSCTL_PCDMA            0x400FE90C  // Micro Direct Memory Access Power
+                                            // Control
+#define SYSCTL_PCEPI            0x400FE910  // External Peripheral Interface
+                                            // Power Control
+#define SYSCTL_PCHIB            0x400FE914  // Hibernation Power Control
+#define SYSCTL_PCUART           0x400FE918  // Universal Asynchronous
+                                            // Receiver/Transmitter Power
+                                            // Control
+#define SYSCTL_PCSSI            0x400FE91C  // Synchronous Serial Interface
+                                            // Power Control
+#define SYSCTL_PCI2C            0x400FE920  // Inter-Integrated Circuit Power
+                                            // Control
+#define SYSCTL_PCUSB            0x400FE928  // Universal Serial Bus Power
+                                            // Control
+#define SYSCTL_PCEPHY           0x400FE930  // Ethernet PHY Power Control
+#define SYSCTL_PCCAN            0x400FE934  // Controller Area Network Power
+                                            // Control
+#define SYSCTL_PCADC            0x400FE938  // Analog-to-Digital Converter
+                                            // Power Control
+#define SYSCTL_PCACMP           0x400FE93C  // Analog Comparator Power Control
+#define SYSCTL_PCPWM            0x400FE940  // Pulse Width Modulator Power
+                                            // Control
+#define SYSCTL_PCQEI            0x400FE944  // Quadrature Encoder Interface
+                                            // Power Control
+#define SYSCTL_PCEEPROM         0x400FE958  // EEPROM Power Control
+#define SYSCTL_PCCCM            0x400FE974  // CRC and Cryptographic Modules
+                                            // Power Control
+#define SYSCTL_PCLCD            0x400FE990  // LCD Controller Power Control
+#define SYSCTL_PCOWIRE          0x400FE998  // 1-Wire Power Control
+#define SYSCTL_PCEMAC           0x400FE99C  // Ethernet MAC Power Control
+#define SYSCTL_PRWD             0x400FEA00  // Watchdog Timer Peripheral Ready
+#define SYSCTL_PRTIMER          0x400FEA04  // 16/32-Bit General-Purpose Timer
+                                            // Peripheral Ready
+#define SYSCTL_PRGPIO           0x400FEA08  // General-Purpose Input/Output
+                                            // Peripheral Ready
+#define SYSCTL_PRDMA            0x400FEA0C  // Micro Direct Memory Access
+                                            // Peripheral Ready
+#define SYSCTL_PREPI            0x400FEA10  // EPI Peripheral Ready
+#define SYSCTL_PRHIB            0x400FEA14  // Hibernation Peripheral Ready
+#define SYSCTL_PRUART           0x400FEA18  // Universal Asynchronous
+                                            // Receiver/Transmitter Peripheral
+                                            // Ready
+#define SYSCTL_PRSSI            0x400FEA1C  // Synchronous Serial Interface
+                                            // Peripheral Ready
+#define SYSCTL_PRI2C            0x400FEA20  // Inter-Integrated Circuit
+                                            // Peripheral Ready
+#define SYSCTL_PRUSB            0x400FEA28  // Universal Serial Bus Peripheral
+                                            // Ready
+#define SYSCTL_PREPHY           0x400FEA30  // Ethernet PHY Peripheral Ready
+#define SYSCTL_PRCAN            0x400FEA34  // Controller Area Network
+                                            // Peripheral Ready
+#define SYSCTL_PRADC            0x400FEA38  // Analog-to-Digital Converter
+                                            // Peripheral Ready
+#define SYSCTL_PRACMP           0x400FEA3C  // Analog Comparator Peripheral
+                                            // Ready
+#define SYSCTL_PRPWM            0x400FEA40  // Pulse Width Modulator Peripheral
+                                            // Ready
+#define SYSCTL_PRQEI            0x400FEA44  // Quadrature Encoder Interface
+                                            // Peripheral Ready
+#define SYSCTL_PREEPROM         0x400FEA58  // EEPROM Peripheral Ready
+#define SYSCTL_PRWTIMER         0x400FEA5C  // 32/64-Bit Wide General-Purpose
+                                            // Timer Peripheral Ready
+#define SYSCTL_PRCCM            0x400FEA74  // CRC and Cryptographic Modules
+                                            // Peripheral Ready
+#define SYSCTL_PRLCD            0x400FEA90  // LCD Controller Peripheral Ready
+#define SYSCTL_PROWIRE          0x400FEA98  // 1-Wire Peripheral Ready
+#define SYSCTL_PREMAC           0x400FEA9C  // Ethernet MAC Peripheral Ready
+#define SYSCTL_UNIQUEID0        0x400FEF20  // Unique ID 0
+#define SYSCTL_UNIQUEID1        0x400FEF24  // Unique ID 1
+#define SYSCTL_UNIQUEID2        0x400FEF28  // Unique ID 2
+#define SYSCTL_UNIQUEID3        0x400FEF2C  // Unique ID 3
+#define SYSCTL_CCMCGREQ         0x44030204  // Cryptographic Modules Clock
+                                            // Gating Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID0_VER_M       0x70000000  // DID0 Version
+#define SYSCTL_DID0_VER_1       0x10000000  // Second version of the DID0
+                                            // register format.
+#define SYSCTL_DID0_CLASS_M     0x00FF0000  // Device Class
+#define SYSCTL_DID0_CLASS_TM4C123                                             \
+                                0x00050000  // Tiva TM4C123x and TM4E123x
+                                            // microcontrollers
+#define SYSCTL_DID0_CLASS_TM4C129                                             \
+                                0x000A0000  // Tiva(TM) TM4C129-class
+                                            // microcontrollers
+#define SYSCTL_DID0_MAJ_M       0x0000FF00  // Major Revision
+#define SYSCTL_DID0_MAJ_REVA    0x00000000  // Revision A (initial device)
+#define SYSCTL_DID0_MAJ_REVB    0x00000100  // Revision B (first base layer
+                                            // revision)
+#define SYSCTL_DID0_MAJ_REVC    0x00000200  // Revision C (second base layer
+                                            // revision)
+#define SYSCTL_DID0_MIN_M       0x000000FF  // Minor Revision
+#define SYSCTL_DID0_MIN_0       0x00000000  // Initial device, or a major
+                                            // revision update
+#define SYSCTL_DID0_MIN_1       0x00000001  // First metal layer change
+#define SYSCTL_DID0_MIN_2       0x00000002  // Second metal layer change
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_VER_M       0xF0000000  // DID1 Version
+#define SYSCTL_DID1_VER_1       0x10000000  // fury_ib
+#define SYSCTL_DID1_FAM_M       0x0F000000  // Family
+#define SYSCTL_DID1_FAM_TIVA    0x00000000  // Tiva family of microcontollers
+#define SYSCTL_DID1_PRTNO_M     0x00FF0000  // Part Number
+#define SYSCTL_DID1_PRTNO_TM4C1230C3PM                                        \
+                                0x00220000  // TM4C1230C3PM
+#define SYSCTL_DID1_PRTNO_TM4C1230D5PM                                        \
+                                0x00230000  // TM4C1230D5PM
+#define SYSCTL_DID1_PRTNO_TM4C1230E6PM                                        \
+                                0x00200000  // TM4C1230E6PM
+#define SYSCTL_DID1_PRTNO_TM4C1230H6PM                                        \
+                                0x00210000  // TM4C1230H6PM
+#define SYSCTL_DID1_PRTNO_TM4C1231C3PM                                        \
+                                0x00180000  // TM4C1231C3PM
+#define SYSCTL_DID1_PRTNO_TM4C1231D5PM                                        \
+                                0x00190000  // TM4C1231D5PM
+#define SYSCTL_DID1_PRTNO_TM4C1231D5PZ                                        \
+                                0x00360000  // TM4C1231D5PZ
+#define SYSCTL_DID1_PRTNO_TM4C1231E6PM                                        \
+                                0x00100000  // TM4C1231E6PM
+#define SYSCTL_DID1_PRTNO_TM4C1231E6PZ                                        \
+                                0x00300000  // TM4C1231E6PZ
+#define SYSCTL_DID1_PRTNO_TM4C1231H6PGE                                       \
+                                0x00350000  // TM4C1231H6PGE
+#define SYSCTL_DID1_PRTNO_TM4C1231H6PM                                        \
+                                0x00110000  // TM4C1231H6PM
+#define SYSCTL_DID1_PRTNO_TM4C1231H6PZ                                        \
+                                0x00310000  // TM4C1231H6PZ
+#define SYSCTL_DID1_PRTNO_TM4C1232C3PM                                        \
+                                0x00080000  // TM4C1232C3PM
+#define SYSCTL_DID1_PRTNO_TM4C1232D5PM                                        \
+                                0x00090000  // TM4C1232D5PM
+#define SYSCTL_DID1_PRTNO_TM4C1232E6PM                                        \
+                                0x000A0000  // TM4C1232E6PM
+#define SYSCTL_DID1_PRTNO_TM4C1232H6PM                                        \
+                                0x000B0000  // TM4C1232H6PM
+#define SYSCTL_DID1_PRTNO_TM4C1233C3PM                                        \
+                                0x00010000  // TM4C1233C3PM
+#define SYSCTL_DID1_PRTNO_TM4C1233D5PM                                        \
+                                0x00020000  // TM4C1233D5PM
+#define SYSCTL_DID1_PRTNO_TM4C1233D5PZ                                        \
+                                0x00D00000  // TM4C1233D5PZ
+#define SYSCTL_DID1_PRTNO_TM4C1233E6PM                                        \
+                                0x00030000  // TM4C1233E6PM
+#define SYSCTL_DID1_PRTNO_TM4C1233E6PZ                                        \
+                                0x00D10000  // TM4C1233E6PZ
+#define SYSCTL_DID1_PRTNO_TM4C1233H6PGE                                       \
+                                0x00D60000  // TM4C1233H6PGE
+#define SYSCTL_DID1_PRTNO_TM4C1233H6PM                                        \
+                                0x00040000  // TM4C1233H6PM
+#define SYSCTL_DID1_PRTNO_TM4C1233H6PZ                                        \
+                                0x00D20000  // TM4C1233H6PZ
+#define SYSCTL_DID1_PRTNO_TM4C1236D5PM                                        \
+                                0x00520000  // TM4C1236D5PM
+#define SYSCTL_DID1_PRTNO_TM4C1236E6PM                                        \
+                                0x00500000  // TM4C1236E6PM
+#define SYSCTL_DID1_PRTNO_TM4C1236H6PM                                        \
+                                0x00510000  // TM4C1236H6PM
+#define SYSCTL_DID1_PRTNO_TM4C1237D5PM                                        \
+                                0x00480000  // TM4C1237D5PM
+#define SYSCTL_DID1_PRTNO_TM4C1237D5PZ                                        \
+                                0x00660000  // TM4C1237D5PZ
+#define SYSCTL_DID1_PRTNO_TM4C1237E6PM                                        \
+                                0x00400000  // TM4C1237E6PM
+#define SYSCTL_DID1_PRTNO_TM4C1237E6PZ                                        \
+                                0x00600000  // TM4C1237E6PZ
+#define SYSCTL_DID1_PRTNO_TM4C1237H6PGE                                       \
+                                0x00650000  // TM4C1237H6PGE
+#define SYSCTL_DID1_PRTNO_TM4C1237H6PM                                        \
+                                0x00410000  // TM4C1237H6PM
+#define SYSCTL_DID1_PRTNO_TM4C1237H6PZ                                        \
+                                0x00610000  // TM4C1237H6PZ
+#define SYSCTL_DID1_PRTNO_TM4C123AE6PM                                        \
+                                0x00800000  // TM4C123AE6PM
+#define SYSCTL_DID1_PRTNO_TM4C123AH6PM                                        \
+                                0x00830000  // TM4C123AH6PM
+#define SYSCTL_DID1_PRTNO_TM4C123BE6PM                                        \
+                                0x00700000  // TM4C123BE6PM
+#define SYSCTL_DID1_PRTNO_TM4C123BE6PZ                                        \
+                                0x00C30000  // TM4C123BE6PZ
+#define SYSCTL_DID1_PRTNO_TM4C123BH6PGE                                       \
+                                0x00C60000  // TM4C123BH6PGE
+#define SYSCTL_DID1_PRTNO_TM4C123BH6PM                                        \
+                                0x00730000  // TM4C123BH6PM
+#define SYSCTL_DID1_PRTNO_TM4C123BH6PZ                                        \
+                                0x00C40000  // TM4C123BH6PZ
+#define SYSCTL_DID1_PRTNO_TM4C123BH6ZRB                                       \
+                                0x00E90000  // TM4C123BH6ZRB
+#define SYSCTL_DID1_PRTNO_TM4C123FE6PM                                        \
+                                0x00B00000  // TM4C123FE6PM
+#define SYSCTL_DID1_PRTNO_TM4C123FH6PM                                        \
+                                0x00B10000  // TM4C123FH6PM
+#define SYSCTL_DID1_PRTNO_TM4C123GE6PM                                        \
+                                0x00A00000  // TM4C123GE6PM
+#define SYSCTL_DID1_PRTNO_TM4C123GE6PZ                                        \
+                                0x00C00000  // TM4C123GE6PZ
+#define SYSCTL_DID1_PRTNO_TM4C123GH6PGE                                       \
+                                0x00C50000  // TM4C123GH6PGE
+#define SYSCTL_DID1_PRTNO_TM4C123GH6PM                                        \
+                                0x00A10000  // TM4C123GH6PM
+#define SYSCTL_DID1_PRTNO_TM4C123GH6PZ                                        \
+                                0x00C10000  // TM4C123GH6PZ
+#define SYSCTL_DID1_PRTNO_TM4C123GH6ZRB                                       \
+                                0x00E30000  // TM4C123GH6ZRB
+#define SYSCTL_DID1_PRTNO_TM4C1290NCPDT                                       \
+                                0x00190000  // TM4C1290NCPDT
+#define SYSCTL_DID1_PRTNO_TM4C1290NCZAD                                       \
+                                0x001B0000  // TM4C1290NCZAD
+#define SYSCTL_DID1_PRTNO_TM4C1292NCPDT                                       \
+                                0x001C0000  // TM4C1292NCPDT
+#define SYSCTL_DID1_PRTNO_TM4C1292NCZAD                                       \
+                                0x001E0000  // TM4C1292NCZAD
+#define SYSCTL_DID1_PRTNO_TM4C1294KCPDT                                       \
+                                0x00340000  // TM4C1294KCPDT
+#define SYSCTL_DID1_PRTNO_TM4C1294NCPDT                                       \
+                                0x001F0000  // TM4C1294NCPDT
+#define SYSCTL_DID1_PRTNO_TM4C1294NCZAD                                       \
+                                0x00210000  // TM4C1294NCZAD
+#define SYSCTL_DID1_PRTNO_TM4C1297NCZAD                                       \
+                                0x00220000  // TM4C1297NCZAD
+#define SYSCTL_DID1_PRTNO_TM4C1299KCZAD                                       \
+                                0x00360000  // TM4C1299KCZAD
+#define SYSCTL_DID1_PRTNO_TM4C1299NCZAD                                       \
+                                0x00230000  // TM4C1299NCZAD
+#define SYSCTL_DID1_PRTNO_TM4C129CNCPDT                                       \
+                                0x00240000  // TM4C129CNCPDT
+#define SYSCTL_DID1_PRTNO_TM4C129CNCZAD                                       \
+                                0x00260000  // TM4C129CNCZAD
+#define SYSCTL_DID1_PRTNO_TM4C129DNCPDT                                       \
+                                0x00270000  // TM4C129DNCPDT
+#define SYSCTL_DID1_PRTNO_TM4C129DNCZAD                                       \
+                                0x00290000  // TM4C129DNCZAD
+#define SYSCTL_DID1_PRTNO_TM4C129EKCPDT                                       \
+                                0x00350000  // TM4C129EKCPDT
+#define SYSCTL_DID1_PRTNO_TM4C129ENCPDT                                       \
+                                0x002D0000  // TM4C129ENCPDT
+#define SYSCTL_DID1_PRTNO_TM4C129ENCZAD                                       \
+                                0x002F0000  // TM4C129ENCZAD
+#define SYSCTL_DID1_PRTNO_TM4C129LNCZAD                                       \
+                                0x00300000  // TM4C129LNCZAD
+#define SYSCTL_DID1_PRTNO_TM4C129XKCZAD                                       \
+                                0x00370000  // TM4C129XKCZAD
+#define SYSCTL_DID1_PRTNO_TM4C129XNCZAD                                       \
+                                0x00320000  // TM4C129XNCZAD
+#define SYSCTL_DID1_PINCNT_M    0x0000E000  // Package Pin Count
+#define SYSCTL_DID1_PINCNT_100  0x00004000  // 100-pin LQFP package
+#define SYSCTL_DID1_PINCNT_64   0x00006000  // 64-pin LQFP package
+#define SYSCTL_DID1_PINCNT_144  0x00008000  // 144-pin LQFP package
+#define SYSCTL_DID1_PINCNT_157  0x0000A000  // 157-pin BGA package
+#define SYSCTL_DID1_PINCNT_128  0x0000C000  // 128-pin TQFP package
+#define SYSCTL_DID1_TEMP_M      0x000000E0  // Temperature Range
+#define SYSCTL_DID1_TEMP_C      0x00000000  // Commercial temperature range
+#define SYSCTL_DID1_TEMP_I      0x00000020  // Industrial temperature range
+#define SYSCTL_DID1_TEMP_E      0x00000040  // Extended temperature range
+#define SYSCTL_DID1_TEMP_IE     0x00000060  // Available in both industrial
+                                            // temperature range (-40C to 85C)
+                                            // and extended temperature range
+                                            // (-40C to 105C) devices. See
+#define SYSCTL_DID1_PKG_M       0x00000018  // Package Type
+#define SYSCTL_DID1_PKG_QFP     0x00000008  // QFP package
+#define SYSCTL_DID1_PKG_BGA     0x00000010  // BGA package
+#define SYSCTL_DID1_ROHS        0x00000004  // RoHS-Compliance
+#define SYSCTL_DID1_QUAL_M      0x00000003  // Qualification Status
+#define SYSCTL_DID1_QUAL_ES     0x00000000  // Engineering Sample (unqualified)
+#define SYSCTL_DID1_QUAL_PP     0x00000001  // Pilot Production (unqualified)
+#define SYSCTL_DID1_QUAL_FQ     0x00000002  // Fully Qualified
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC0_SRAMSZ_M     0xFFFF0000  // SRAM Size
+#define SYSCTL_DC0_SRAMSZ_2KB   0x00070000  // 2 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_4KB   0x000F0000  // 4 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_6KB   0x00170000  // 6 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_8KB   0x001F0000  // 8 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_12KB  0x002F0000  // 12 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_16KB  0x003F0000  // 16 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_20KB  0x004F0000  // 20 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_24KB  0x005F0000  // 24 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_32KB  0x007F0000  // 32 KB of SRAM
+#define SYSCTL_DC0_FLASHSZ_M    0x0000FFFF  // Flash Size
+#define SYSCTL_DC0_FLASHSZ_8KB  0x00000003  // 8 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007  // 16 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F  // 32 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F  // 64 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F  // 96 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F  // 128 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_192K 0x0000005F  // 192 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F  // 256 KB of Flash
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC1_WDT1         0x10000000  // Watchdog Timer1 Present
+#define SYSCTL_DC1_CAN1         0x02000000  // CAN Module 1 Present
+#define SYSCTL_DC1_CAN0         0x01000000  // CAN Module 0 Present
+#define SYSCTL_DC1_PWM1         0x00200000  // PWM Module 1 Present
+#define SYSCTL_DC1_PWM0         0x00100000  // PWM Module 0 Present
+#define SYSCTL_DC1_ADC1         0x00020000  // ADC Module 1 Present
+#define SYSCTL_DC1_ADC0         0x00010000  // ADC Module 0 Present
+#define SYSCTL_DC1_MINSYSDIV_M  0x0000F000  // System Clock Divider
+#define SYSCTL_DC1_MINSYSDIV_80 0x00002000  // Specifies an 80-MHz CPU clock
+                                            // with a PLL divider of 2.5
+#define SYSCTL_DC1_MINSYSDIV_50 0x00003000  // Specifies a 50-MHz CPU clock
+                                            // with a PLL divider of 4
+#define SYSCTL_DC1_MINSYSDIV_40 0x00004000  // Specifies a 40-MHz CPU clock
+                                            // with a PLL divider of 5
+#define SYSCTL_DC1_MINSYSDIV_25 0x00007000  // Specifies a 25-MHz clock with a
+                                            // PLL divider of 8
+#define SYSCTL_DC1_MINSYSDIV_20 0x00009000  // Specifies a 20-MHz clock with a
+                                            // PLL divider of 10
+#define SYSCTL_DC1_ADC1SPD_M    0x00000C00  // Max ADC1 Speed
+#define SYSCTL_DC1_ADC1SPD_125K 0x00000000  // 125K samples/second
+#define SYSCTL_DC1_ADC1SPD_250K 0x00000400  // 250K samples/second
+#define SYSCTL_DC1_ADC1SPD_500K 0x00000800  // 500K samples/second
+#define SYSCTL_DC1_ADC1SPD_1M   0x00000C00  // 1M samples/second
+#define SYSCTL_DC1_ADC0SPD_M    0x00000300  // Max ADC0 Speed
+#define SYSCTL_DC1_ADC0SPD_125K 0x00000000  // 125K samples/second
+#define SYSCTL_DC1_ADC0SPD_250K 0x00000100  // 250K samples/second
+#define SYSCTL_DC1_ADC0SPD_500K 0x00000200  // 500K samples/second
+#define SYSCTL_DC1_ADC0SPD_1M   0x00000300  // 1M samples/second
+#define SYSCTL_DC1_MPU          0x00000080  // MPU Present
+#define SYSCTL_DC1_HIB          0x00000040  // Hibernation Module Present
+#define SYSCTL_DC1_TEMP         0x00000020  // Temp Sensor Present
+#define SYSCTL_DC1_PLL          0x00000010  // PLL Present
+#define SYSCTL_DC1_WDT0         0x00000008  // Watchdog Timer 0 Present
+#define SYSCTL_DC1_SWO          0x00000004  // SWO Trace Port Present
+#define SYSCTL_DC1_SWD          0x00000002  // SWD Present
+#define SYSCTL_DC1_JTAG         0x00000001  // JTAG Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC2_EPI0         0x40000000  // EPI Module 0 Present
+#define SYSCTL_DC2_I2S0         0x10000000  // I2S Module 0 Present
+#define SYSCTL_DC2_COMP2        0x04000000  // Analog Comparator 2 Present
+#define SYSCTL_DC2_COMP1        0x02000000  // Analog Comparator 1 Present
+#define SYSCTL_DC2_COMP0        0x01000000  // Analog Comparator 0 Present
+#define SYSCTL_DC2_TIMER3       0x00080000  // Timer Module 3 Present
+#define SYSCTL_DC2_TIMER2       0x00040000  // Timer Module 2 Present
+#define SYSCTL_DC2_TIMER1       0x00020000  // Timer Module 1 Present
+#define SYSCTL_DC2_TIMER0       0x00010000  // Timer Module 0 Present
+#define SYSCTL_DC2_I2C1HS       0x00008000  // I2C Module 1 Speed
+#define SYSCTL_DC2_I2C1         0x00004000  // I2C Module 1 Present
+#define SYSCTL_DC2_I2C0HS       0x00002000  // I2C Module 0 Speed
+#define SYSCTL_DC2_I2C0         0x00001000  // I2C Module 0 Present
+#define SYSCTL_DC2_QEI1         0x00000200  // QEI Module 1 Present
+#define SYSCTL_DC2_QEI0         0x00000100  // QEI Module 0 Present
+#define SYSCTL_DC2_SSI1         0x00000020  // SSI Module 1 Present
+#define SYSCTL_DC2_SSI0         0x00000010  // SSI Module 0 Present
+#define SYSCTL_DC2_UART2        0x00000004  // UART Module 2 Present
+#define SYSCTL_DC2_UART1        0x00000002  // UART Module 1 Present
+#define SYSCTL_DC2_UART0        0x00000001  // UART Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC3 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC3_32KHZ        0x80000000  // 32KHz Input Clock Available
+#define SYSCTL_DC3_CCP5         0x20000000  // T2CCP1 Pin Present
+#define SYSCTL_DC3_CCP4         0x10000000  // T2CCP0 Pin Present
+#define SYSCTL_DC3_CCP3         0x08000000  // T1CCP1 Pin Present
+#define SYSCTL_DC3_CCP2         0x04000000  // T1CCP0 Pin Present
+#define SYSCTL_DC3_CCP1         0x02000000  // T0CCP1 Pin Present
+#define SYSCTL_DC3_CCP0         0x01000000  // T0CCP0 Pin Present
+#define SYSCTL_DC3_ADC0AIN7     0x00800000  // ADC Module 0 AIN7 Pin Present
+#define SYSCTL_DC3_ADC0AIN6     0x00400000  // ADC Module 0 AIN6 Pin Present
+#define SYSCTL_DC3_ADC0AIN5     0x00200000  // ADC Module 0 AIN5 Pin Present
+#define SYSCTL_DC3_ADC0AIN4     0x00100000  // ADC Module 0 AIN4 Pin Present
+#define SYSCTL_DC3_ADC0AIN3     0x00080000  // ADC Module 0 AIN3 Pin Present
+#define SYSCTL_DC3_ADC0AIN2     0x00040000  // ADC Module 0 AIN2 Pin Present
+#define SYSCTL_DC3_ADC0AIN1     0x00020000  // ADC Module 0 AIN1 Pin Present
+#define SYSCTL_DC3_ADC0AIN0     0x00010000  // ADC Module 0 AIN0 Pin Present
+#define SYSCTL_DC3_PWMFAULT     0x00008000  // PWM Fault Pin Present
+#define SYSCTL_DC3_C2O          0x00004000  // C2o Pin Present
+#define SYSCTL_DC3_C2PLUS       0x00002000  // C2+ Pin Present
+#define SYSCTL_DC3_C2MINUS      0x00001000  // C2- Pin Present
+#define SYSCTL_DC3_C1O          0x00000800  // C1o Pin Present
+#define SYSCTL_DC3_C1PLUS       0x00000400  // C1+ Pin Present
+#define SYSCTL_DC3_C1MINUS      0x00000200  // C1- Pin Present
+#define SYSCTL_DC3_C0O          0x00000100  // C0o Pin Present
+#define SYSCTL_DC3_C0PLUS       0x00000080  // C0+ Pin Present
+#define SYSCTL_DC3_C0MINUS      0x00000040  // C0- Pin Present
+#define SYSCTL_DC3_PWM5         0x00000020  // PWM5 Pin Present
+#define SYSCTL_DC3_PWM4         0x00000010  // PWM4 Pin Present
+#define SYSCTL_DC3_PWM3         0x00000008  // PWM3 Pin Present
+#define SYSCTL_DC3_PWM2         0x00000004  // PWM2 Pin Present
+#define SYSCTL_DC3_PWM1         0x00000002  // PWM1 Pin Present
+#define SYSCTL_DC3_PWM0         0x00000001  // PWM0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC4 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC4_EPHY0        0x40000000  // Ethernet PHY Layer 0 Present
+#define SYSCTL_DC4_EMAC0        0x10000000  // Ethernet MAC Layer 0 Present
+#define SYSCTL_DC4_E1588        0x01000000  // 1588 Capable
+#define SYSCTL_DC4_PICAL        0x00040000  // PIOSC Calibrate
+#define SYSCTL_DC4_CCP7         0x00008000  // T3CCP1 Pin Present
+#define SYSCTL_DC4_CCP6         0x00004000  // T3CCP0 Pin Present
+#define SYSCTL_DC4_UDMA         0x00002000  // Micro-DMA Module Present
+#define SYSCTL_DC4_ROM          0x00001000  // Internal Code ROM Present
+#define SYSCTL_DC4_GPIOJ        0x00000100  // GPIO Port J Present
+#define SYSCTL_DC4_GPIOH        0x00000080  // GPIO Port H Present
+#define SYSCTL_DC4_GPIOG        0x00000040  // GPIO Port G Present
+#define SYSCTL_DC4_GPIOF        0x00000020  // GPIO Port F Present
+#define SYSCTL_DC4_GPIOE        0x00000010  // GPIO Port E Present
+#define SYSCTL_DC4_GPIOD        0x00000008  // GPIO Port D Present
+#define SYSCTL_DC4_GPIOC        0x00000004  // GPIO Port C Present
+#define SYSCTL_DC4_GPIOB        0x00000002  // GPIO Port B Present
+#define SYSCTL_DC4_GPIOA        0x00000001  // GPIO Port A Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC5 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC5_PWMFAULT3    0x08000000  // PWM Fault 3 Pin Present
+#define SYSCTL_DC5_PWMFAULT2    0x04000000  // PWM Fault 2 Pin Present
+#define SYSCTL_DC5_PWMFAULT1    0x02000000  // PWM Fault 1 Pin Present
+#define SYSCTL_DC5_PWMFAULT0    0x01000000  // PWM Fault 0 Pin Present
+#define SYSCTL_DC5_PWMEFLT      0x00200000  // PWM Extended Fault Active
+#define SYSCTL_DC5_PWMESYNC     0x00100000  // PWM Extended SYNC Active
+#define SYSCTL_DC5_PWM7         0x00000080  // PWM7 Pin Present
+#define SYSCTL_DC5_PWM6         0x00000040  // PWM6 Pin Present
+#define SYSCTL_DC5_PWM5         0x00000020  // PWM5 Pin Present
+#define SYSCTL_DC5_PWM4         0x00000010  // PWM4 Pin Present
+#define SYSCTL_DC5_PWM3         0x00000008  // PWM3 Pin Present
+#define SYSCTL_DC5_PWM2         0x00000004  // PWM2 Pin Present
+#define SYSCTL_DC5_PWM1         0x00000002  // PWM1 Pin Present
+#define SYSCTL_DC5_PWM0         0x00000001  // PWM0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC6 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC6_USB0PHY      0x00000010  // USB Module 0 PHY Present
+#define SYSCTL_DC6_USB0_M       0x00000003  // USB Module 0 Present
+#define SYSCTL_DC6_USB0_DEV     0x00000001  // USB0 is Device Only
+#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002  // USB is Device or Host
+#define SYSCTL_DC6_USB0_OTG     0x00000003  // USB0 is OTG
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC7 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC7_DMACH30      0x40000000  // DMA Channel 30
+#define SYSCTL_DC7_DMACH29      0x20000000  // DMA Channel 29
+#define SYSCTL_DC7_DMACH28      0x10000000  // DMA Channel 28
+#define SYSCTL_DC7_DMACH27      0x08000000  // DMA Channel 27
+#define SYSCTL_DC7_DMACH26      0x04000000  // DMA Channel 26
+#define SYSCTL_DC7_DMACH25      0x02000000  // DMA Channel 25
+#define SYSCTL_DC7_DMACH24      0x01000000  // DMA Channel 24
+#define SYSCTL_DC7_DMACH23      0x00800000  // DMA Channel 23
+#define SYSCTL_DC7_DMACH22      0x00400000  // DMA Channel 22
+#define SYSCTL_DC7_DMACH21      0x00200000  // DMA Channel 21
+#define SYSCTL_DC7_DMACH20      0x00100000  // DMA Channel 20
+#define SYSCTL_DC7_DMACH19      0x00080000  // DMA Channel 19
+#define SYSCTL_DC7_DMACH18      0x00040000  // DMA Channel 18
+#define SYSCTL_DC7_DMACH17      0x00020000  // DMA Channel 17
+#define SYSCTL_DC7_DMACH16      0x00010000  // DMA Channel 16
+#define SYSCTL_DC7_DMACH15      0x00008000  // DMA Channel 15
+#define SYSCTL_DC7_DMACH14      0x00004000  // DMA Channel 14
+#define SYSCTL_DC7_DMACH13      0x00002000  // DMA Channel 13
+#define SYSCTL_DC7_DMACH12      0x00001000  // DMA Channel 12
+#define SYSCTL_DC7_DMACH11      0x00000800  // DMA Channel 11
+#define SYSCTL_DC7_DMACH10      0x00000400  // DMA Channel 10
+#define SYSCTL_DC7_DMACH9       0x00000200  // DMA Channel 9
+#define SYSCTL_DC7_DMACH8       0x00000100  // DMA Channel 8
+#define SYSCTL_DC7_DMACH7       0x00000080  // DMA Channel 7
+#define SYSCTL_DC7_DMACH6       0x00000040  // DMA Channel 6
+#define SYSCTL_DC7_DMACH5       0x00000020  // DMA Channel 5
+#define SYSCTL_DC7_DMACH4       0x00000010  // DMA Channel 4
+#define SYSCTL_DC7_DMACH3       0x00000008  // DMA Channel 3
+#define SYSCTL_DC7_DMACH2       0x00000004  // DMA Channel 2
+#define SYSCTL_DC7_DMACH1       0x00000002  // DMA Channel 1
+#define SYSCTL_DC7_DMACH0       0x00000001  // DMA Channel 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC8 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC8_ADC1AIN15    0x80000000  // ADC Module 1 AIN15 Pin Present
+#define SYSCTL_DC8_ADC1AIN14    0x40000000  // ADC Module 1 AIN14 Pin Present
+#define SYSCTL_DC8_ADC1AIN13    0x20000000  // ADC Module 1 AIN13 Pin Present
+#define SYSCTL_DC8_ADC1AIN12    0x10000000  // ADC Module 1 AIN12 Pin Present
+#define SYSCTL_DC8_ADC1AIN11    0x08000000  // ADC Module 1 AIN11 Pin Present
+#define SYSCTL_DC8_ADC1AIN10    0x04000000  // ADC Module 1 AIN10 Pin Present
+#define SYSCTL_DC8_ADC1AIN9     0x02000000  // ADC Module 1 AIN9 Pin Present
+#define SYSCTL_DC8_ADC1AIN8     0x01000000  // ADC Module 1 AIN8 Pin Present
+#define SYSCTL_DC8_ADC1AIN7     0x00800000  // ADC Module 1 AIN7 Pin Present
+#define SYSCTL_DC8_ADC1AIN6     0x00400000  // ADC Module 1 AIN6 Pin Present
+#define SYSCTL_DC8_ADC1AIN5     0x00200000  // ADC Module 1 AIN5 Pin Present
+#define SYSCTL_DC8_ADC1AIN4     0x00100000  // ADC Module 1 AIN4 Pin Present
+#define SYSCTL_DC8_ADC1AIN3     0x00080000  // ADC Module 1 AIN3 Pin Present
+#define SYSCTL_DC8_ADC1AIN2     0x00040000  // ADC Module 1 AIN2 Pin Present
+#define SYSCTL_DC8_ADC1AIN1     0x00020000  // ADC Module 1 AIN1 Pin Present
+#define SYSCTL_DC8_ADC1AIN0     0x00010000  // ADC Module 1 AIN0 Pin Present
+#define SYSCTL_DC8_ADC0AIN15    0x00008000  // ADC Module 0 AIN15 Pin Present
+#define SYSCTL_DC8_ADC0AIN14    0x00004000  // ADC Module 0 AIN14 Pin Present
+#define SYSCTL_DC8_ADC0AIN13    0x00002000  // ADC Module 0 AIN13 Pin Present
+#define SYSCTL_DC8_ADC0AIN12    0x00001000  // ADC Module 0 AIN12 Pin Present
+#define SYSCTL_DC8_ADC0AIN11    0x00000800  // ADC Module 0 AIN11 Pin Present
+#define SYSCTL_DC8_ADC0AIN10    0x00000400  // ADC Module 0 AIN10 Pin Present
+#define SYSCTL_DC8_ADC0AIN9     0x00000200  // ADC Module 0 AIN9 Pin Present
+#define SYSCTL_DC8_ADC0AIN8     0x00000100  // ADC Module 0 AIN8 Pin Present
+#define SYSCTL_DC8_ADC0AIN7     0x00000080  // ADC Module 0 AIN7 Pin Present
+#define SYSCTL_DC8_ADC0AIN6     0x00000040  // ADC Module 0 AIN6 Pin Present
+#define SYSCTL_DC8_ADC0AIN5     0x00000020  // ADC Module 0 AIN5 Pin Present
+#define SYSCTL_DC8_ADC0AIN4     0x00000010  // ADC Module 0 AIN4 Pin Present
+#define SYSCTL_DC8_ADC0AIN3     0x00000008  // ADC Module 0 AIN3 Pin Present
+#define SYSCTL_DC8_ADC0AIN2     0x00000004  // ADC Module 0 AIN2 Pin Present
+#define SYSCTL_DC8_ADC0AIN1     0x00000002  // ADC Module 0 AIN1 Pin Present
+#define SYSCTL_DC8_ADC0AIN0     0x00000001  // ADC Module 0 AIN0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PBORCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_PBORCTL_BOR0     0x00000004  // VDD under BOR0 Event Action
+#define SYSCTL_PBORCTL_BOR1     0x00000002  // VDD under BOR1 Event Action
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PTBOCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_PTBOCTL_VDDA_UBOR_M                                            \
+                                0x00000300  // VDDA under BOR Event Action
+#define SYSCTL_PTBOCTL_VDDA_UBOR_NONE                                         \
+                                0x00000000  // No Action
+#define SYSCTL_PTBOCTL_VDDA_UBOR_SYSINT                                       \
+                                0x00000100  // System control interrupt
+#define SYSCTL_PTBOCTL_VDDA_UBOR_NMI                                          \
+                                0x00000200  // NMI
+#define SYSCTL_PTBOCTL_VDDA_UBOR_RST                                          \
+                                0x00000300  // Reset
+#define SYSCTL_PTBOCTL_VDD_UBOR_M                                             \
+                                0x00000003  // VDD (VDDS) under BOR Event
+                                            // Action
+#define SYSCTL_PTBOCTL_VDD_UBOR_NONE                                          \
+                                0x00000000  // No Action
+#define SYSCTL_PTBOCTL_VDD_UBOR_SYSINT                                        \
+                                0x00000001  // System control interrupt
+#define SYSCTL_PTBOCTL_VDD_UBOR_NMI                                           \
+                                0x00000002  // NMI
+#define SYSCTL_PTBOCTL_VDD_UBOR_RST                                           \
+                                0x00000003  // Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR0_WDT1       0x10000000  // WDT1 Reset Control
+#define SYSCTL_SRCR0_CAN1       0x02000000  // CAN1 Reset Control
+#define SYSCTL_SRCR0_CAN0       0x01000000  // CAN0 Reset Control
+#define SYSCTL_SRCR0_PWM0       0x00100000  // PWM Reset Control
+#define SYSCTL_SRCR0_ADC1       0x00020000  // ADC1 Reset Control
+#define SYSCTL_SRCR0_ADC0       0x00010000  // ADC0 Reset Control
+#define SYSCTL_SRCR0_HIB        0x00000040  // HIB Reset Control
+#define SYSCTL_SRCR0_WDT0       0x00000008  // WDT0 Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR1_COMP2      0x04000000  // Analog Comp 2 Reset Control
+#define SYSCTL_SRCR1_COMP1      0x02000000  // Analog Comp 1 Reset Control
+#define SYSCTL_SRCR1_COMP0      0x01000000  // Analog Comp 0 Reset Control
+#define SYSCTL_SRCR1_TIMER3     0x00080000  // Timer 3 Reset Control
+#define SYSCTL_SRCR1_TIMER2     0x00040000  // Timer 2 Reset Control
+#define SYSCTL_SRCR1_TIMER1     0x00020000  // Timer 1 Reset Control
+#define SYSCTL_SRCR1_TIMER0     0x00010000  // Timer 0 Reset Control
+#define SYSCTL_SRCR1_I2C1       0x00004000  // I2C1 Reset Control
+#define SYSCTL_SRCR1_I2C0       0x00001000  // I2C0 Reset Control
+#define SYSCTL_SRCR1_QEI1       0x00000200  // QEI1 Reset Control
+#define SYSCTL_SRCR1_QEI0       0x00000100  // QEI0 Reset Control
+#define SYSCTL_SRCR1_SSI1       0x00000020  // SSI1 Reset Control
+#define SYSCTL_SRCR1_SSI0       0x00000010  // SSI0 Reset Control
+#define SYSCTL_SRCR1_UART2      0x00000004  // UART2 Reset Control
+#define SYSCTL_SRCR1_UART1      0x00000002  // UART1 Reset Control
+#define SYSCTL_SRCR1_UART0      0x00000001  // UART0 Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR2_USB0       0x00010000  // USB0 Reset Control
+#define SYSCTL_SRCR2_UDMA       0x00002000  // Micro-DMA Reset Control
+#define SYSCTL_SRCR2_GPIOJ      0x00000100  // Port J Reset Control
+#define SYSCTL_SRCR2_GPIOH      0x00000080  // Port H Reset Control
+#define SYSCTL_SRCR2_GPIOG      0x00000040  // Port G Reset Control
+#define SYSCTL_SRCR2_GPIOF      0x00000020  // Port F Reset Control
+#define SYSCTL_SRCR2_GPIOE      0x00000010  // Port E Reset Control
+#define SYSCTL_SRCR2_GPIOD      0x00000008  // Port D Reset Control
+#define SYSCTL_SRCR2_GPIOC      0x00000004  // Port C Reset Control
+#define SYSCTL_SRCR2_GPIOB      0x00000002  // Port B Reset Control
+#define SYSCTL_SRCR2_GPIOA      0x00000001  // Port A Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RIS register.
+//
+//*****************************************************************************
+#define SYSCTL_RIS_BOR0RIS      0x00000800  // VDD under BOR0 Raw Interrupt
+                                            // Status
+#define SYSCTL_RIS_VDDARIS      0x00000400  // VDDA Power OK Event Raw
+                                            // Interrupt Status
+#define SYSCTL_RIS_MOSCPUPRIS   0x00000100  // MOSC Power Up Raw Interrupt
+                                            // Status
+#define SYSCTL_RIS_USBPLLLRIS   0x00000080  // USB PLL Lock Raw Interrupt
+                                            // Status
+#define SYSCTL_RIS_PLLLRIS      0x00000040  // PLL Lock Raw Interrupt Status
+#define SYSCTL_RIS_MOFRIS       0x00000008  // Main Oscillator Failure Raw
+                                            // Interrupt Status
+#define SYSCTL_RIS_BOR1RIS      0x00000002  // VDD under BOR1 Raw Interrupt
+                                            // Status
+#define SYSCTL_RIS_BORRIS       0x00000002  // Brown-Out Reset Raw Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_IMC register.
+//
+//*****************************************************************************
+#define SYSCTL_IMC_BOR0IM       0x00000800  // VDD under BOR0 Interrupt Mask
+#define SYSCTL_IMC_VDDAIM       0x00000400  // VDDA Power OK Interrupt Mask
+#define SYSCTL_IMC_MOSCPUPIM    0x00000100  // MOSC Power Up Interrupt Mask
+#define SYSCTL_IMC_USBPLLLIM    0x00000080  // USB PLL Lock Interrupt Mask
+#define SYSCTL_IMC_PLLLIM       0x00000040  // PLL Lock Interrupt Mask
+#define SYSCTL_IMC_MOFIM        0x00000008  // Main Oscillator Failure
+                                            // Interrupt Mask
+#define SYSCTL_IMC_BORIM        0x00000002  // Brown-Out Reset Interrupt Mask
+#define SYSCTL_IMC_BOR1IM       0x00000002  // VDD under BOR1 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MISC register.
+//
+//*****************************************************************************
+#define SYSCTL_MISC_BOR0MIS     0x00000800  // VDD under BOR0 Masked Interrupt
+                                            // Status
+#define SYSCTL_MISC_VDDAMIS     0x00000400  // VDDA Power OK Masked Interrupt
+                                            // Status
+#define SYSCTL_MISC_MOSCPUPMIS  0x00000100  // MOSC Power Up Masked Interrupt
+                                            // Status
+#define SYSCTL_MISC_USBPLLLMIS  0x00000080  // USB PLL Lock Masked Interrupt
+                                            // Status
+#define SYSCTL_MISC_PLLLMIS     0x00000040  // PLL Lock Masked Interrupt Status
+#define SYSCTL_MISC_MOFMIS      0x00000008  // Main Oscillator Failure Masked
+                                            // Interrupt Status
+#define SYSCTL_MISC_BORMIS      0x00000002  // BOR Masked Interrupt Status
+#define SYSCTL_MISC_BOR1MIS     0x00000002  // VDD under BOR1 Masked Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RESC register.
+//
+//*****************************************************************************
+#define SYSCTL_RESC_MOSCFAIL    0x00010000  // MOSC Failure Reset
+#define SYSCTL_RESC_HSSR        0x00001000  // HSSR Reset
+#define SYSCTL_RESC_WDT1        0x00000020  // Watchdog Timer 1 Reset
+#define SYSCTL_RESC_SW          0x00000010  // Software Reset
+#define SYSCTL_RESC_WDT0        0x00000008  // Watchdog Timer 0 Reset
+#define SYSCTL_RESC_BOR         0x00000004  // Brown-Out Reset
+#define SYSCTL_RESC_POR         0x00000002  // Power-On Reset
+#define SYSCTL_RESC_EXT         0x00000001  // External Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PWRTC register.
+//
+//*****************************************************************************
+#define SYSCTL_PWRTC_VDDA_UBOR  0x00000010  // VDDA Under BOR Status
+#define SYSCTL_PWRTC_VDD_UBOR   0x00000001  // VDD Under BOR Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC_ACG          0x08000000  // Auto Clock Gating
+#define SYSCTL_RCC_SYSDIV_M     0x07800000  // System Clock Divisor
+#define SYSCTL_RCC_USESYSDIV    0x00400000  // Enable System Clock Divider
+#define SYSCTL_RCC_USEPWMDIV    0x00100000  // Enable PWM Clock Divisor
+#define SYSCTL_RCC_PWMDIV_M     0x000E0000  // PWM Unit Clock Divisor
+#define SYSCTL_RCC_PWMDIV_2     0x00000000  // PWM clock /2
+#define SYSCTL_RCC_PWMDIV_4     0x00020000  // PWM clock /4
+#define SYSCTL_RCC_PWMDIV_8     0x00040000  // PWM clock /8
+#define SYSCTL_RCC_PWMDIV_16    0x00060000  // PWM clock /16
+#define SYSCTL_RCC_PWMDIV_32    0x00080000  // PWM clock /32
+#define SYSCTL_RCC_PWMDIV_64    0x000A0000  // PWM clock /64
+#define SYSCTL_RCC_PWRDN        0x00002000  // PLL Power Down
+#define SYSCTL_RCC_BYPASS       0x00000800  // PLL Bypass
+#define SYSCTL_RCC_XTAL_M       0x000007C0  // Crystal Value
+#define SYSCTL_RCC_XTAL_4MHZ    0x00000180  // 4 MHz
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0  // 4.096 MHz
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200  // 4.9152 MHz
+#define SYSCTL_RCC_XTAL_5MHZ    0x00000240  // 5 MHz
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280  // 5.12 MHz
+#define SYSCTL_RCC_XTAL_6MHZ    0x000002C0  // 6 MHz
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300  // 6.144 MHz
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340  // 7.3728 MHz
+#define SYSCTL_RCC_XTAL_8MHZ    0x00000380  // 8 MHz
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0  // 8.192 MHz
+#define SYSCTL_RCC_XTAL_10MHZ   0x00000400  // 10 MHz
+#define SYSCTL_RCC_XTAL_12MHZ   0x00000440  // 12 MHz
+#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480  // 12.288 MHz
+#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0  // 13.56 MHz
+#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500  // 14.31818 MHz
+#define SYSCTL_RCC_XTAL_16MHZ   0x00000540  // 16 MHz
+#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580  // 16.384 MHz
+#define SYSCTL_RCC_XTAL_18MHZ   0x000005C0  // 18.0 MHz (USB)
+#define SYSCTL_RCC_XTAL_20MHZ   0x00000600  // 20.0 MHz (USB)
+#define SYSCTL_RCC_XTAL_24MHZ   0x00000640  // 24.0 MHz (USB)
+#define SYSCTL_RCC_XTAL_25MHZ   0x00000680  // 25.0 MHz (USB)
+#define SYSCTL_RCC_OSCSRC_M     0x00000030  // Oscillator Source
+#define SYSCTL_RCC_OSCSRC_MAIN  0x00000000  // MOSC
+#define SYSCTL_RCC_OSCSRC_INT   0x00000010  // IOSC
+#define SYSCTL_RCC_OSCSRC_INT4  0x00000020  // IOSC/4
+#define SYSCTL_RCC_OSCSRC_30    0x00000030  // LFIOSC
+#define SYSCTL_RCC_MOSCDIS      0x00000001  // Main Oscillator Disable
+#define SYSCTL_RCC_SYSDIV_S     23
+#define SYSCTL_RCC_XTAL_S       6           // Shift to the XTAL field
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_NMIC register.
+//
+//*****************************************************************************
+#define SYSCTL_NMIC_MOSCFAIL    0x00010000  // MOSC Failure NMI
+#define SYSCTL_NMIC_TAMPER      0x00000200  // Tamper Event NMI
+#define SYSCTL_NMIC_WDT1        0x00000020  // Watch Dog Timer (WDT) 1 NMI
+#define SYSCTL_NMIC_WDT0        0x00000008  // Watch Dog Timer (WDT) 0 NMI
+#define SYSCTL_NMIC_POWER       0x00000004  // Power/Brown Out Event NMI
+#define SYSCTL_NMIC_EXTERNAL    0x00000001  // External Pin NMI
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_GPIOHBCTL_PORTJ  0x00000100  // Port J Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTH  0x00000080  // Port H Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTG  0x00000040  // Port G Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTF  0x00000020  // Port F Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTE  0x00000010  // Port E Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTD  0x00000008  // Port D Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTC  0x00000004  // Port C Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTB  0x00000002  // Port B Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTA  0x00000001  // Port A Advanced High-Performance
+                                            // Bus
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC2_USERCC2     0x80000000  // Use RCC2
+#define SYSCTL_RCC2_DIV400      0x40000000  // Divide PLL as 400 MHz vs. 200
+                                            // MHz
+#define SYSCTL_RCC2_SYSDIV2_M   0x1F800000  // System Clock Divisor 2
+#define SYSCTL_RCC2_SYSDIV2LSB  0x00400000  // Additional LSB for SYSDIV2
+#define SYSCTL_RCC2_USBPWRDN    0x00004000  // Power-Down USB PLL
+#define SYSCTL_RCC2_PWRDN2      0x00002000  // Power-Down PLL 2
+#define SYSCTL_RCC2_BYPASS2     0x00000800  // PLL Bypass 2
+#define SYSCTL_RCC2_OSCSRC2_M   0x00000070  // Oscillator Source 2
+#define SYSCTL_RCC2_OSCSRC2_MO  0x00000000  // MOSC
+#define SYSCTL_RCC2_OSCSRC2_IO  0x00000010  // PIOSC
+#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020  // PIOSC/4
+#define SYSCTL_RCC2_OSCSRC2_30  0x00000030  // LFIOSC
+#define SYSCTL_RCC2_OSCSRC2_32  0x00000070  // 32.768 kHz
+#define SYSCTL_RCC2_SYSDIV2_S   23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MOSCCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_MOSCCTL_OSCRNG   0x00000010  // Oscillator Range
+#define SYSCTL_MOSCCTL_PWRDN    0x00000008  // Power Down
+#define SYSCTL_MOSCCTL_NOXTAL   0x00000004  // No Crystal Connected
+#define SYSCTL_MOSCCTL_MOSCIM   0x00000002  // MOSC Failure Action
+#define SYSCTL_MOSCCTL_CVAL     0x00000001  // Clock Validation for MOSC
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RSCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RSCLKCFG_MEMTIMU 0x80000000  // Memory Timing Register Update
+#define SYSCTL_RSCLKCFG_NEWFREQ 0x40000000  // New PLLFREQ Accept
+#define SYSCTL_RSCLKCFG_ACG     0x20000000  // Auto Clock Gating
+#define SYSCTL_RSCLKCFG_USEPLL  0x10000000  // Use PLL
+#define SYSCTL_RSCLKCFG_PLLSRC_M                                              \
+                                0x0F000000  // PLL Source
+#define SYSCTL_RSCLKCFG_PLLSRC_PIOSC                                          \
+                                0x00000000  // PIOSC is PLL input clock source
+#define SYSCTL_RSCLKCFG_PLLSRC_MOSC                                           \
+                                0x03000000  // MOSC is the PLL input clock
+                                            // source
+#define SYSCTL_RSCLKCFG_OSCSRC_M                                              \
+                                0x00F00000  // Oscillator Source
+#define SYSCTL_RSCLKCFG_OSCSRC_PIOSC                                          \
+                                0x00000000  // PIOSC is oscillator source
+#define SYSCTL_RSCLKCFG_OSCSRC_LFIOSC                                         \
+                                0x00200000  // LFIOSC is oscillator source
+#define SYSCTL_RSCLKCFG_OSCSRC_MOSC                                           \
+                                0x00300000  // MOSC is oscillator source
+#define SYSCTL_RSCLKCFG_OSCSRC_RTC                                            \
+                                0x00400000  // Hibernation Module RTC
+                                            // Oscillator (RTCOSC)
+#define SYSCTL_RSCLKCFG_OSYSDIV_M                                             \
+                                0x000FFC00  // Oscillator System Clock Divisor
+#define SYSCTL_RSCLKCFG_PSYSDIV_M                                             \
+                                0x000003FF  // PLL System Clock Divisor
+#define SYSCTL_RSCLKCFG_OSYSDIV_S                                             \
+                                10
+#define SYSCTL_RSCLKCFG_PSYSDIV_S                                             \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MEMTIM0 register.
+//
+//*****************************************************************************
+#define SYSCTL_MEMTIM0_EBCHT_M  0x03C00000  // EEPROM Clock High Time
+#define SYSCTL_MEMTIM0_EBCHT_0_5                                              \
+                                0x00000000  // 1/2 system clock period
+#define SYSCTL_MEMTIM0_EBCHT_1  0x00400000  // 1 system clock period
+#define SYSCTL_MEMTIM0_EBCHT_1_5                                              \
+                                0x00800000  // 1.5 system clock periods
+#define SYSCTL_MEMTIM0_EBCHT_2  0x00C00000  // 2 system clock periods
+#define SYSCTL_MEMTIM0_EBCHT_2_5                                              \
+                                0x01000000  // 2.5 system clock periods
+#define SYSCTL_MEMTIM0_EBCHT_3  0x01400000  // 3 system clock periods
+#define SYSCTL_MEMTIM0_EBCHT_3_5                                              \
+                                0x01800000  // 3.5 system clock periods
+#define SYSCTL_MEMTIM0_EBCHT_4  0x01C00000  // 4 system clock periods
+#define SYSCTL_MEMTIM0_EBCHT_4_5                                              \
+                                0x02000000  // 4.5 system clock periods
+#define SYSCTL_MEMTIM0_EBCE     0x00200000  // EEPROM Bank Clock Edge
+#define SYSCTL_MEMTIM0_MB1      0x00100010  // Must be one
+#define SYSCTL_MEMTIM0_EWS_M    0x000F0000  // EEPROM Wait States
+#define SYSCTL_MEMTIM0_FBCHT_M  0x000003C0  // Flash Bank Clock High Time
+#define SYSCTL_MEMTIM0_FBCHT_0_5                                              \
+                                0x00000000  // 1/2 system clock period
+#define SYSCTL_MEMTIM0_FBCHT_1  0x00000040  // 1 system clock period
+#define SYSCTL_MEMTIM0_FBCHT_1_5                                              \
+                                0x00000080  // 1.5 system clock periods
+#define SYSCTL_MEMTIM0_FBCHT_2  0x000000C0  // 2 system clock periods
+#define SYSCTL_MEMTIM0_FBCHT_2_5                                              \
+                                0x00000100  // 2.5 system clock periods
+#define SYSCTL_MEMTIM0_FBCHT_3  0x00000140  // 3 system clock periods
+#define SYSCTL_MEMTIM0_FBCHT_3_5                                              \
+                                0x00000180  // 3.5 system clock periods
+#define SYSCTL_MEMTIM0_FBCHT_4  0x000001C0  // 4 system clock periods
+#define SYSCTL_MEMTIM0_FBCHT_4_5                                              \
+                                0x00000200  // 4.5 system clock periods
+#define SYSCTL_MEMTIM0_FBCE     0x00000020  // Flash Bank Clock Edge
+#define SYSCTL_MEMTIM0_FWS_M    0x0000000F  // Flash Wait State
+#define SYSCTL_MEMTIM0_EWS_S    16
+#define SYSCTL_MEMTIM0_FWS_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control
+#define SYSCTL_RCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control
+#define SYSCTL_RCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control
+#define SYSCTL_RCGC0_PWM0       0x00100000  // PWM Clock Gating Control
+#define SYSCTL_RCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control
+#define SYSCTL_RCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_RCGC0_ADC1SPD_M  0x00000C00  // ADC1 Sample Speed
+#define SYSCTL_RCGC0_ADC1SPD_125K                                             \
+                                0x00000000  // 125K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_250K                                             \
+                                0x00000400  // 250K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_500K                                             \
+                                0x00000800  // 500K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00  // 1M samples/second
+#define SYSCTL_RCGC0_ADC0SPD_M  0x00000300  // ADC0 Sample Speed
+#define SYSCTL_RCGC0_ADC0SPD_125K                                             \
+                                0x00000000  // 125K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_250K                                             \
+                                0x00000100  // 250K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_500K                                             \
+                                0x00000200  // 500K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300  // 1M samples/second
+#define SYSCTL_RCGC0_HIB        0x00000040  // HIB Clock Gating Control
+#define SYSCTL_RCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC1_COMP2      0x04000000  // Analog Comparator 2 Clock Gating
+#define SYSCTL_RCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating
+#define SYSCTL_RCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_RCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_RCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control
+#define SYSCTL_RCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_RCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
+#define SYSCTL_RCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
+#define SYSCTL_RCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control
+#define SYSCTL_RCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_RCGC1_UART2      0x00000004  // UART2 Clock Gating Control
+#define SYSCTL_RCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_RCGC1_UART0      0x00000001  // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC2_USB0       0x00010000  // USB0 Clock Gating Control
+#define SYSCTL_RCGC2_UDMA       0x00002000  // Micro-DMA Clock Gating Control
+#define SYSCTL_RCGC2_GPIOJ      0x00000100  // Port J Clock Gating Control
+#define SYSCTL_RCGC2_GPIOH      0x00000080  // Port H Clock Gating Control
+#define SYSCTL_RCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
+#define SYSCTL_RCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_RCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_RCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_RCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_RCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_RCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control
+#define SYSCTL_SCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control
+#define SYSCTL_SCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control
+#define SYSCTL_SCGC0_PWM0       0x00100000  // PWM Clock Gating Control
+#define SYSCTL_SCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control
+#define SYSCTL_SCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_SCGC0_ADCSPD_M   0x00000F00  // ADC Sample Speed
+#define SYSCTL_SCGC0_HIB        0x00000040  // HIB Clock Gating Control
+#define SYSCTL_SCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC1_COMP2      0x04000000  // Analog Comparator 2 Clock Gating
+#define SYSCTL_SCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating
+#define SYSCTL_SCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_SCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_SCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control
+#define SYSCTL_SCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_SCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
+#define SYSCTL_SCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
+#define SYSCTL_SCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control
+#define SYSCTL_SCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_SCGC1_UART2      0x00000004  // UART2 Clock Gating Control
+#define SYSCTL_SCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_SCGC1_UART0      0x00000001  // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC2_USB0       0x00010000  // USB0 Clock Gating Control
+#define SYSCTL_SCGC2_UDMA       0x00002000  // Micro-DMA Clock Gating Control
+#define SYSCTL_SCGC2_GPIOJ      0x00000100  // Port J Clock Gating Control
+#define SYSCTL_SCGC2_GPIOH      0x00000080  // Port H Clock Gating Control
+#define SYSCTL_SCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
+#define SYSCTL_SCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_SCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_SCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_SCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_SCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_SCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control
+#define SYSCTL_DCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control
+#define SYSCTL_DCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control
+#define SYSCTL_DCGC0_PWM0       0x00100000  // PWM Clock Gating Control
+#define SYSCTL_DCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control
+#define SYSCTL_DCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_DCGC0_HIB        0x00000040  // HIB Clock Gating Control
+#define SYSCTL_DCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC1_COMP2      0x04000000  // Analog Comparator 2 Clock Gating
+#define SYSCTL_DCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating
+#define SYSCTL_DCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_DCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_DCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control
+#define SYSCTL_DCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_DCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
+#define SYSCTL_DCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
+#define SYSCTL_DCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control
+#define SYSCTL_DCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_DCGC1_UART2      0x00000004  // UART2 Clock Gating Control
+#define SYSCTL_DCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_DCGC1_UART0      0x00000001  // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC2_USB0       0x00010000  // USB0 Clock Gating Control
+#define SYSCTL_DCGC2_UDMA       0x00002000  // Micro-DMA Clock Gating Control
+#define SYSCTL_DCGC2_GPIOJ      0x00000100  // Port J Clock Gating Control
+#define SYSCTL_DCGC2_GPIOH      0x00000080  // Port H Clock Gating Control
+#define SYSCTL_DCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
+#define SYSCTL_DCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_DCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_DCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_DCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_DCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_DCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_ALTCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_ALTCLKCFG_ALTCLK_M                                             \
+                                0x0000000F  // Alternate Clock Source
+#define SYSCTL_ALTCLKCFG_ALTCLK_PIOSC                                         \
+                                0x00000000  // PIOSC
+#define SYSCTL_ALTCLKCFG_ALTCLK_RTCOSC                                        \
+                                0x00000003  // Hibernation Module Real-time
+                                            // clock output (RTCOSC)
+#define SYSCTL_ALTCLKCFG_ALTCLK_LFIOSC                                        \
+                                0x00000004  // Low-frequency internal
+                                            // oscillator (LFIOSC)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSLPCLKCFG_D_M   0x1F800000  // Divider Field Override
+#define SYSCTL_DSLPCLKCFG_O_M   0x00000070  // Clock Source
+#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000  // MOSC
+#define SYSCTL_DSLPCLKCFG_O_IO  0x00000010  // PIOSC
+#define SYSCTL_DSLPCLKCFG_O_30  0x00000030  // LFIOSC
+#define SYSCTL_DSLPCLKCFG_O_32  0x00000070  // 32.768 kHz
+#define SYSCTL_DSLPCLKCFG_PIOSCPD                                             \
+                                0x00000002  // PIOSC Power Down Request
+#define SYSCTL_DSLPCLKCFG_D_S   23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSCLKCFG_PIOSCPD 0x80000000  // PIOSC Power Down
+#define SYSCTL_DSCLKCFG_MOSCDPD 0x40000000  // MOSC Disable Power Down
+#define SYSCTL_DSCLKCFG_DSOSCSRC_M                                            \
+                                0x00F00000  // Deep Sleep Oscillator Source
+#define SYSCTL_DSCLKCFG_DSOSCSRC_PIOSC                                        \
+                                0x00000000  // PIOSC
+#define SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC                                       \
+                                0x00200000  // LFIOSC
+#define SYSCTL_DSCLKCFG_DSOSCSRC_MOSC                                         \
+                                0x00300000  // MOSC
+#define SYSCTL_DSCLKCFG_DSOSCSRC_RTC                                          \
+                                0x00400000  // Hibernation Module RTCOSC
+#define SYSCTL_DSCLKCFG_DSSYSDIV_M                                            \
+                                0x000003FF  // Deep Sleep Clock Divisor
+#define SYSCTL_DSCLKCFG_DSSYSDIV_S                                            \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DIVSCLK register.
+//
+//*****************************************************************************
+#define SYSCTL_DIVSCLK_EN       0x80000000  // DIVSCLK Enable
+#define SYSCTL_DIVSCLK_SRC_M    0x00030000  // Clock Source
+#define SYSCTL_DIVSCLK_SRC_SYSCLK                                             \
+                                0x00000000  // System Clock
+#define SYSCTL_DIVSCLK_SRC_PIOSC                                              \
+                                0x00010000  // PIOSC
+#define SYSCTL_DIVSCLK_SRC_MOSC 0x00020000  // MOSC
+#define SYSCTL_DIVSCLK_DIV_M    0x000000FF  // Divisor Value
+#define SYSCTL_DIVSCLK_DIV_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SYSPROP register.
+//
+//*****************************************************************************
+#define SYSCTL_SYSPROP_FPU      0x00000001  // FPU Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PIOSCCAL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PIOSCCAL_UTEN    0x80000000  // Use User Trim Value
+#define SYSCTL_PIOSCCAL_CAL     0x00000200  // Start Calibration
+#define SYSCTL_PIOSCCAL_UPDATE  0x00000100  // Update Trim
+#define SYSCTL_PIOSCCAL_UT_M    0x0000007F  // User Trim Value
+#define SYSCTL_PIOSCCAL_UT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PIOSCSTAT_DT_M   0x007F0000  // Default Trim Value
+#define SYSCTL_PIOSCSTAT_CR_M   0x00000300  // Calibration Result
+#define SYSCTL_PIOSCSTAT_CRNONE 0x00000000  // Calibration has not been
+                                            // attempted
+#define SYSCTL_PIOSCSTAT_CRPASS 0x00000100  // The last calibration operation
+                                            // completed to meet 1% accuracy
+#define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200  // The last calibration operation
+                                            // failed to meet 1% accuracy
+#define SYSCTL_PIOSCSTAT_CT_M   0x0000007F  // Calibration Trim Value
+#define SYSCTL_PIOSCSTAT_DT_S   16
+#define SYSCTL_PIOSCSTAT_CT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLFREQ0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLFREQ0_PLLPWR  0x00800000  // PLL Power
+#define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00  // PLL M Fractional Value
+#define SYSCTL_PLLFREQ0_MINT_M  0x000003FF  // PLL M Integer Value
+#define SYSCTL_PLLFREQ0_MFRAC_S 10
+#define SYSCTL_PLLFREQ0_MINT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLFREQ1
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLFREQ1_Q_M     0x00001F00  // PLL Q Value
+#define SYSCTL_PLLFREQ1_N_M     0x0000001F  // PLL N Value
+#define SYSCTL_PLLFREQ1_Q_S     8
+#define SYSCTL_PLLFREQ1_N_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLSTAT register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLSTAT_LOCK     0x00000001  // PLL Lock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SLPPWRCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SLPPWRCFG_FLASHPM_M                                            \
+                                0x00000030  // Flash Power Modes
+#define SYSCTL_SLPPWRCFG_FLASHPM_NRM                                          \
+                                0x00000000  // Active Mode
+#define SYSCTL_SLPPWRCFG_FLASHPM_SLP                                          \
+                                0x00000020  // Low Power Mode
+#define SYSCTL_SLPPWRCFG_SRAMPM_M                                             \
+                                0x00000003  // SRAM Power Modes
+#define SYSCTL_SLPPWRCFG_SRAMPM_NRM                                           \
+                                0x00000000  // Active Mode
+#define SYSCTL_SLPPWRCFG_SRAMPM_SBY                                           \
+                                0x00000001  // Standby Mode
+#define SYSCTL_SLPPWRCFG_SRAMPM_LP                                            \
+                                0x00000003  // Low Power Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSLPPWRCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSLPPWRCFG_LDOSM 0x00000200  // LDO Sleep Mode
+#define SYSCTL_DSLPPWRCFG_TSPD  0x00000100  // Temperature Sense Power Down
+#define SYSCTL_DSLPPWRCFG_FLASHPM_M                                           \
+                                0x00000030  // Flash Power Modes
+#define SYSCTL_DSLPPWRCFG_FLASHPM_NRM                                         \
+                                0x00000000  // Active Mode
+#define SYSCTL_DSLPPWRCFG_FLASHPM_SLP                                         \
+                                0x00000020  // Low Power Mode
+#define SYSCTL_DSLPPWRCFG_SRAMPM_M                                            \
+                                0x00000003  // SRAM Power Modes
+#define SYSCTL_DSLPPWRCFG_SRAMPM_NRM                                          \
+                                0x00000000  // Active Mode
+#define SYSCTL_DSLPPWRCFG_SRAMPM_SBY                                          \
+                                0x00000001  // Standby Mode
+#define SYSCTL_DSLPPWRCFG_SRAMPM_LP                                           \
+                                0x00000003  // Low Power Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC9 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC9_ADC1DC7      0x00800000  // ADC1 DC7 Present
+#define SYSCTL_DC9_ADC1DC6      0x00400000  // ADC1 DC6 Present
+#define SYSCTL_DC9_ADC1DC5      0x00200000  // ADC1 DC5 Present
+#define SYSCTL_DC9_ADC1DC4      0x00100000  // ADC1 DC4 Present
+#define SYSCTL_DC9_ADC1DC3      0x00080000  // ADC1 DC3 Present
+#define SYSCTL_DC9_ADC1DC2      0x00040000  // ADC1 DC2 Present
+#define SYSCTL_DC9_ADC1DC1      0x00020000  // ADC1 DC1 Present
+#define SYSCTL_DC9_ADC1DC0      0x00010000  // ADC1 DC0 Present
+#define SYSCTL_DC9_ADC0DC7      0x00000080  // ADC0 DC7 Present
+#define SYSCTL_DC9_ADC0DC6      0x00000040  // ADC0 DC6 Present
+#define SYSCTL_DC9_ADC0DC5      0x00000020  // ADC0 DC5 Present
+#define SYSCTL_DC9_ADC0DC4      0x00000010  // ADC0 DC4 Present
+#define SYSCTL_DC9_ADC0DC3      0x00000008  // ADC0 DC3 Present
+#define SYSCTL_DC9_ADC0DC2      0x00000004  // ADC0 DC2 Present
+#define SYSCTL_DC9_ADC0DC1      0x00000002  // ADC0 DC1 Present
+#define SYSCTL_DC9_ADC0DC0      0x00000001  // ADC0 DC0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_NVMSTAT register.
+//
+//*****************************************************************************
+#define SYSCTL_NVMSTAT_FWB      0x00000001  // 32 Word Flash Write Buffer
+                                            // Available
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_LDOSPCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_LDOSPCTL_VADJEN  0x80000000  // Voltage Adjust Enable
+#define SYSCTL_LDOSPCTL_VLDO_M  0x000000FF  // LDO Output Voltage
+#define SYSCTL_LDOSPCTL_VLDO_0_90V                                            \
+                                0x00000012  // 0.90 V
+#define SYSCTL_LDOSPCTL_VLDO_0_95V                                            \
+                                0x00000013  // 0.95 V
+#define SYSCTL_LDOSPCTL_VLDO_1_00V                                            \
+                                0x00000014  // 1.00 V
+#define SYSCTL_LDOSPCTL_VLDO_1_05V                                            \
+                                0x00000015  // 1.05 V
+#define SYSCTL_LDOSPCTL_VLDO_1_10V                                            \
+                                0x00000016  // 1.10 V
+#define SYSCTL_LDOSPCTL_VLDO_1_15V                                            \
+                                0x00000017  // 1.15 V
+#define SYSCTL_LDOSPCTL_VLDO_1_20V                                            \
+                                0x00000018  // 1.20 V
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_LDODPCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_LDODPCTL_VADJEN  0x80000000  // Voltage Adjust Enable
+#define SYSCTL_LDODPCTL_VLDO_M  0x000000FF  // LDO Output Voltage
+#define SYSCTL_LDODPCTL_VLDO_0_90V                                            \
+                                0x00000012  // 0.90 V
+#define SYSCTL_LDODPCTL_VLDO_0_95V                                            \
+                                0x00000013  // 0.95 V
+#define SYSCTL_LDODPCTL_VLDO_1_00V                                            \
+                                0x00000014  // 1.00 V
+#define SYSCTL_LDODPCTL_VLDO_1_05V                                            \
+                                0x00000015  // 1.05 V
+#define SYSCTL_LDODPCTL_VLDO_1_10V                                            \
+                                0x00000016  // 1.10 V
+#define SYSCTL_LDODPCTL_VLDO_1_15V                                            \
+                                0x00000017  // 1.15 V
+#define SYSCTL_LDODPCTL_VLDO_1_20V                                            \
+                                0x00000018  // 1.20 V
+#define SYSCTL_LDODPCTL_VLDO_1_25V                                            \
+                                0x00000019  // 1.25 V
+#define SYSCTL_LDODPCTL_VLDO_1_30V                                            \
+                                0x0000001A  // 1.30 V
+#define SYSCTL_LDODPCTL_VLDO_1_35V                                            \
+                                0x0000001B  // 1.35 V
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RESBEHAVCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RESBEHAVCTL_WDOG1_M                                            \
+                                0x000000C0  // Watchdog 1 Reset Operation
+#define SYSCTL_RESBEHAVCTL_WDOG1_SYSRST                                       \
+                                0x00000080  // Watchdog 1 issues a system
+                                            // reset. The application starts
+                                            // within 10 us
+#define SYSCTL_RESBEHAVCTL_WDOG1_POR                                          \
+                                0x000000C0  // Watchdog 1 issues a simulated
+                                            // POR sequence. Application starts
+                                            // less than 500 us after
+                                            // deassertion (Default)
+#define SYSCTL_RESBEHAVCTL_WDOG0_M                                            \
+                                0x00000030  // Watchdog 0 Reset Operation
+#define SYSCTL_RESBEHAVCTL_WDOG0_SYSRST                                       \
+                                0x00000020  // Watchdog 0 issues a system
+                                            // reset. The application starts
+                                            // within 10 us
+#define SYSCTL_RESBEHAVCTL_WDOG0_POR                                          \
+                                0x00000030  // Watchdog 0 issues a simulated
+                                            // POR sequence. Application starts
+                                            // less than 500 us after
+                                            // deassertion (Default)
+#define SYSCTL_RESBEHAVCTL_BOR_M                                              \
+                                0x0000000C  // BOR Reset operation
+#define SYSCTL_RESBEHAVCTL_BOR_SYSRST                                         \
+                                0x00000008  // Brown Out Reset issues system
+                                            // reset. The application starts
+                                            // within 10 us
+#define SYSCTL_RESBEHAVCTL_BOR_POR                                            \
+                                0x0000000C  // Brown Out Reset issues a
+                                            // simulated POR sequence. The
+                                            // application starts less than 500
+                                            // us after deassertion (Default)
+#define SYSCTL_RESBEHAVCTL_EXTRES_M                                           \
+                                0x00000003  // External RST Pin Operation
+#define SYSCTL_RESBEHAVCTL_EXTRES_SYSRST                                      \
+                                0x00000002  // External RST assertion issues a
+                                            // system reset. The application
+                                            // starts within 10 us
+#define SYSCTL_RESBEHAVCTL_EXTRES_POR                                         \
+                                0x00000003  // External RST assertion issues a
+                                            // simulated POR sequence.
+                                            // Application starts less than 500
+                                            // us after deassertion (Default)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_HSSR register.
+//
+//*****************************************************************************
+#define SYSCTL_HSSR_KEY_M       0xFF000000  // Write Key
+#define SYSCTL_HSSR_CDOFF_M     0x00FFFFFF  // Command Descriptor Pointer
+#define SYSCTL_HSSR_KEY_S       24
+#define SYSCTL_HSSR_CDOFF_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_USBPDS register.
+//
+//*****************************************************************************
+#define SYSCTL_USBPDS_MEMSTAT_M 0x0000000C  // Memory Array Power Status
+#define SYSCTL_USBPDS_MEMSTAT_OFF                                             \
+                                0x00000000  // Array OFF
+#define SYSCTL_USBPDS_MEMSTAT_RETAIN                                          \
+                                0x00000004  // SRAM Retention
+#define SYSCTL_USBPDS_MEMSTAT_ON                                              \
+                                0x0000000C  // Array On
+#define SYSCTL_USBPDS_PWRSTAT_M 0x00000003  // Power Domain Status
+#define SYSCTL_USBPDS_PWRSTAT_OFF                                             \
+                                0x00000000  // OFF
+#define SYSCTL_USBPDS_PWRSTAT_ON                                              \
+                                0x00000003  // ON
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_USBMPC register.
+//
+//*****************************************************************************
+#define SYSCTL_USBMPC_PWRCTL_M  0x00000003  // Memory Array Power Control
+#define SYSCTL_USBMPC_PWRCTL_OFF                                              \
+                                0x00000000  // Array OFF
+#define SYSCTL_USBMPC_PWRCTL_RETAIN                                           \
+                                0x00000001  // SRAM Retention
+#define SYSCTL_USBMPC_PWRCTL_ON 0x00000003  // Array On
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_EMACPDS register.
+//
+//*****************************************************************************
+#define SYSCTL_EMACPDS_MEMSTAT_M                                              \
+                                0x0000000C  // Memory Array Power Status
+#define SYSCTL_EMACPDS_MEMSTAT_OFF                                            \
+                                0x00000000  // Array OFF
+#define SYSCTL_EMACPDS_MEMSTAT_ON                                             \
+                                0x0000000C  // Array On
+#define SYSCTL_EMACPDS_PWRSTAT_M                                              \
+                                0x00000003  // Power Domain Status
+#define SYSCTL_EMACPDS_PWRSTAT_OFF                                            \
+                                0x00000000  // OFF
+#define SYSCTL_EMACPDS_PWRSTAT_ON                                             \
+                                0x00000003  // ON
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_EMACMPC register.
+//
+//*****************************************************************************
+#define SYSCTL_EMACMPC_PWRCTL_M 0x00000003  // Memory Array Power Control
+#define SYSCTL_EMACMPC_PWRCTL_OFF                                             \
+                                0x00000000  // Array OFF
+#define SYSCTL_EMACMPC_PWRCTL_ON                                              \
+                                0x00000003  // Array On
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_LCDMPC register.
+//
+//*****************************************************************************
+#define SYSCTL_LCDMPC_PWRCTL_M  0x00000003  // Memory Array Power Control
+#define SYSCTL_LCDMPC_PWRCTL_OFF                                              \
+                                0x00000000  // Array OFF
+#define SYSCTL_LCDMPC_PWRCTL_ON 0x00000003  // Array On
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPWD register.
+//
+//*****************************************************************************
+#define SYSCTL_PPWD_P1          0x00000002  // Watchdog Timer 1 Present
+#define SYSCTL_PPWD_P0          0x00000001  // Watchdog Timer 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_PPTIMER_P7       0x00000080  // 16/32-Bit General-Purpose Timer
+                                            // 7 Present
+#define SYSCTL_PPTIMER_P6       0x00000040  // 16/32-Bit General-Purpose Timer
+                                            // 6 Present
+#define SYSCTL_PPTIMER_P5       0x00000020  // 16/32-Bit General-Purpose Timer
+                                            // 5 Present
+#define SYSCTL_PPTIMER_P4       0x00000010  // 16/32-Bit General-Purpose Timer
+                                            // 4 Present
+#define SYSCTL_PPTIMER_P3       0x00000008  // 16/32-Bit General-Purpose Timer
+                                            // 3 Present
+#define SYSCTL_PPTIMER_P2       0x00000004  // 16/32-Bit General-Purpose Timer
+                                            // 2 Present
+#define SYSCTL_PPTIMER_P1       0x00000002  // 16/32-Bit General-Purpose Timer
+                                            // 1 Present
+#define SYSCTL_PPTIMER_P0       0x00000001  // 16/32-Bit General-Purpose Timer
+                                            // 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_PPGPIO_P17       0x00020000  // GPIO Port T Present
+#define SYSCTL_PPGPIO_P16       0x00010000  // GPIO Port S Present
+#define SYSCTL_PPGPIO_P15       0x00008000  // GPIO Port R Present
+#define SYSCTL_PPGPIO_P14       0x00004000  // GPIO Port Q Present
+#define SYSCTL_PPGPIO_P13       0x00002000  // GPIO Port P Present
+#define SYSCTL_PPGPIO_P12       0x00001000  // GPIO Port N Present
+#define SYSCTL_PPGPIO_P11       0x00000800  // GPIO Port M Present
+#define SYSCTL_PPGPIO_P10       0x00000400  // GPIO Port L Present
+#define SYSCTL_PPGPIO_P9        0x00000200  // GPIO Port K Present
+#define SYSCTL_PPGPIO_P8        0x00000100  // GPIO Port J Present
+#define SYSCTL_PPGPIO_P7        0x00000080  // GPIO Port H Present
+#define SYSCTL_PPGPIO_P6        0x00000040  // GPIO Port G Present
+#define SYSCTL_PPGPIO_P5        0x00000020  // GPIO Port F Present
+#define SYSCTL_PPGPIO_P4        0x00000010  // GPIO Port E Present
+#define SYSCTL_PPGPIO_P3        0x00000008  // GPIO Port D Present
+#define SYSCTL_PPGPIO_P2        0x00000004  // GPIO Port C Present
+#define SYSCTL_PPGPIO_P1        0x00000002  // GPIO Port B Present
+#define SYSCTL_PPGPIO_P0        0x00000001  // GPIO Port A Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_PPDMA_P0         0x00000001  // uDMA Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPEPI register.
+//
+//*****************************************************************************
+#define SYSCTL_PPEPI_P0         0x00000001  // EPI Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_PPHIB_P0         0x00000001  // Hibernation Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPUART register.
+//
+//*****************************************************************************
+#define SYSCTL_PPUART_P7        0x00000080  // UART Module 7 Present
+#define SYSCTL_PPUART_P6        0x00000040  // UART Module 6 Present
+#define SYSCTL_PPUART_P5        0x00000020  // UART Module 5 Present
+#define SYSCTL_PPUART_P4        0x00000010  // UART Module 4 Present
+#define SYSCTL_PPUART_P3        0x00000008  // UART Module 3 Present
+#define SYSCTL_PPUART_P2        0x00000004  // UART Module 2 Present
+#define SYSCTL_PPUART_P1        0x00000002  // UART Module 1 Present
+#define SYSCTL_PPUART_P0        0x00000001  // UART Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_PPSSI_P3         0x00000008  // SSI Module 3 Present
+#define SYSCTL_PPSSI_P2         0x00000004  // SSI Module 2 Present
+#define SYSCTL_PPSSI_P1         0x00000002  // SSI Module 1 Present
+#define SYSCTL_PPSSI_P0         0x00000001  // SSI Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_PPI2C_P9         0x00000200  // I2C Module 9 Present
+#define SYSCTL_PPI2C_P8         0x00000100  // I2C Module 8 Present
+#define SYSCTL_PPI2C_P7         0x00000080  // I2C Module 7 Present
+#define SYSCTL_PPI2C_P6         0x00000040  // I2C Module 6 Present
+#define SYSCTL_PPI2C_P5         0x00000020  // I2C Module 5 Present
+#define SYSCTL_PPI2C_P4         0x00000010  // I2C Module 4 Present
+#define SYSCTL_PPI2C_P3         0x00000008  // I2C Module 3 Present
+#define SYSCTL_PPI2C_P2         0x00000004  // I2C Module 2 Present
+#define SYSCTL_PPI2C_P1         0x00000002  // I2C Module 1 Present
+#define SYSCTL_PPI2C_P0         0x00000001  // I2C Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_PPUSB_P0         0x00000001  // USB Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPEPHY register.
+//
+//*****************************************************************************
+#define SYSCTL_PPEPHY_P0        0x00000001  // Ethernet PHY Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PPCAN_P1         0x00000002  // CAN Module 1 Present
+#define SYSCTL_PPCAN_P0         0x00000001  // CAN Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPADC register.
+//
+//*****************************************************************************
+#define SYSCTL_PPADC_P1         0x00000002  // ADC Module 1 Present
+#define SYSCTL_PPADC_P0         0x00000001  // ADC Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_PPACMP_P0        0x00000001  // Analog Comparator Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_PPPWM_P1         0x00000002  // PWM Module 1 Present
+#define SYSCTL_PPPWM_P0         0x00000001  // PWM Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_PPQEI_P1         0x00000002  // QEI Module 1 Present
+#define SYSCTL_PPQEI_P0         0x00000001  // QEI Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPLPC register.
+//
+//*****************************************************************************
+#define SYSCTL_PPLPC_P0         0x00000001  // LPC Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPPECI register.
+//
+//*****************************************************************************
+#define SYSCTL_PPPECI_P0        0x00000001  // PECI Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPFAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PPFAN_P0         0x00000001  // FAN Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PPEEPROM_P0      0x00000001  // EEPROM Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PPWTIMER_P5      0x00000020  // 32/64-Bit Wide General-Purpose
+                                            // Timer 5 Present
+#define SYSCTL_PPWTIMER_P4      0x00000010  // 32/64-Bit Wide General-Purpose
+                                            // Timer 4 Present
+#define SYSCTL_PPWTIMER_P3      0x00000008  // 32/64-Bit Wide General-Purpose
+                                            // Timer 3 Present
+#define SYSCTL_PPWTIMER_P2      0x00000004  // 32/64-Bit Wide General-Purpose
+                                            // Timer 2 Present
+#define SYSCTL_PPWTIMER_P1      0x00000002  // 32/64-Bit Wide General-Purpose
+                                            // Timer 1 Present
+#define SYSCTL_PPWTIMER_P0      0x00000001  // 32/64-Bit Wide General-Purpose
+                                            // Timer 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPRTS register.
+//
+//*****************************************************************************
+#define SYSCTL_PPRTS_P0         0x00000001  // RTS Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPCCM register.
+//
+//*****************************************************************************
+#define SYSCTL_PPCCM_P0         0x00000001  // CRC and Cryptographic Modules
+                                            // Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPLCD register.
+//
+//*****************************************************************************
+#define SYSCTL_PPLCD_P0         0x00000001  // LCD Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPOWIRE register.
+//
+//*****************************************************************************
+#define SYSCTL_PPOWIRE_P0       0x00000001  // 1-Wire Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPEMAC register.
+//
+//*****************************************************************************
+#define SYSCTL_PPEMAC_P0        0x00000001  // Ethernet Controller Module
+                                            // Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPHIM register.
+//
+//*****************************************************************************
+#define SYSCTL_PPHIM_P0         0x00000001  // HIM Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRWD register.
+//
+//*****************************************************************************
+#define SYSCTL_SRWD_R1          0x00000002  // Watchdog Timer 1 Software Reset
+#define SYSCTL_SRWD_R0          0x00000001  // Watchdog Timer 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_SRTIMER_R7       0x00000080  // 16/32-Bit General-Purpose Timer
+                                            // 7 Software Reset
+#define SYSCTL_SRTIMER_R6       0x00000040  // 16/32-Bit General-Purpose Timer
+                                            // 6 Software Reset
+#define SYSCTL_SRTIMER_R5       0x00000020  // 16/32-Bit General-Purpose Timer
+                                            // 5 Software Reset
+#define SYSCTL_SRTIMER_R4       0x00000010  // 16/32-Bit General-Purpose Timer
+                                            // 4 Software Reset
+#define SYSCTL_SRTIMER_R3       0x00000008  // 16/32-Bit General-Purpose Timer
+                                            // 3 Software Reset
+#define SYSCTL_SRTIMER_R2       0x00000004  // 16/32-Bit General-Purpose Timer
+                                            // 2 Software Reset
+#define SYSCTL_SRTIMER_R1       0x00000002  // 16/32-Bit General-Purpose Timer
+                                            // 1 Software Reset
+#define SYSCTL_SRTIMER_R0       0x00000001  // 16/32-Bit General-Purpose Timer
+                                            // 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_SRGPIO_R17       0x00020000  // GPIO Port T Software Reset
+#define SYSCTL_SRGPIO_R16       0x00010000  // GPIO Port S Software Reset
+#define SYSCTL_SRGPIO_R15       0x00008000  // GPIO Port R Software Reset
+#define SYSCTL_SRGPIO_R14       0x00004000  // GPIO Port Q Software Reset
+#define SYSCTL_SRGPIO_R13       0x00002000  // GPIO Port P Software Reset
+#define SYSCTL_SRGPIO_R12       0x00001000  // GPIO Port N Software Reset
+#define SYSCTL_SRGPIO_R11       0x00000800  // GPIO Port M Software Reset
+#define SYSCTL_SRGPIO_R10       0x00000400  // GPIO Port L Software Reset
+#define SYSCTL_SRGPIO_R9        0x00000200  // GPIO Port K Software Reset
+#define SYSCTL_SRGPIO_R8        0x00000100  // GPIO Port J Software Reset
+#define SYSCTL_SRGPIO_R7        0x00000080  // GPIO Port H Software Reset
+#define SYSCTL_SRGPIO_R6        0x00000040  // GPIO Port G Software Reset
+#define SYSCTL_SRGPIO_R5        0x00000020  // GPIO Port F Software Reset
+#define SYSCTL_SRGPIO_R4        0x00000010  // GPIO Port E Software Reset
+#define SYSCTL_SRGPIO_R3        0x00000008  // GPIO Port D Software Reset
+#define SYSCTL_SRGPIO_R2        0x00000004  // GPIO Port C Software Reset
+#define SYSCTL_SRGPIO_R1        0x00000002  // GPIO Port B Software Reset
+#define SYSCTL_SRGPIO_R0        0x00000001  // GPIO Port A Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_SRDMA_R0         0x00000001  // uDMA Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SREPI register.
+//
+//*****************************************************************************
+#define SYSCTL_SREPI_R0         0x00000001  // EPI Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_SRHIB_R0         0x00000001  // Hibernation Module Software
+                                            // Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRUART register.
+//
+//*****************************************************************************
+#define SYSCTL_SRUART_R7        0x00000080  // UART Module 7 Software Reset
+#define SYSCTL_SRUART_R6        0x00000040  // UART Module 6 Software Reset
+#define SYSCTL_SRUART_R5        0x00000020  // UART Module 5 Software Reset
+#define SYSCTL_SRUART_R4        0x00000010  // UART Module 4 Software Reset
+#define SYSCTL_SRUART_R3        0x00000008  // UART Module 3 Software Reset
+#define SYSCTL_SRUART_R2        0x00000004  // UART Module 2 Software Reset
+#define SYSCTL_SRUART_R1        0x00000002  // UART Module 1 Software Reset
+#define SYSCTL_SRUART_R0        0x00000001  // UART Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_SRSSI_R3         0x00000008  // SSI Module 3 Software Reset
+#define SYSCTL_SRSSI_R2         0x00000004  // SSI Module 2 Software Reset
+#define SYSCTL_SRSSI_R1         0x00000002  // SSI Module 1 Software Reset
+#define SYSCTL_SRSSI_R0         0x00000001  // SSI Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_SRI2C_R9         0x00000200  // I2C Module 9 Software Reset
+#define SYSCTL_SRI2C_R8         0x00000100  // I2C Module 8 Software Reset
+#define SYSCTL_SRI2C_R7         0x00000080  // I2C Module 7 Software Reset
+#define SYSCTL_SRI2C_R6         0x00000040  // I2C Module 6 Software Reset
+#define SYSCTL_SRI2C_R5         0x00000020  // I2C Module 5 Software Reset
+#define SYSCTL_SRI2C_R4         0x00000010  // I2C Module 4 Software Reset
+#define SYSCTL_SRI2C_R3         0x00000008  // I2C Module 3 Software Reset
+#define SYSCTL_SRI2C_R2         0x00000004  // I2C Module 2 Software Reset
+#define SYSCTL_SRI2C_R1         0x00000002  // I2C Module 1 Software Reset
+#define SYSCTL_SRI2C_R0         0x00000001  // I2C Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_SRUSB_R0         0x00000001  // USB Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SREPHY register.
+//
+//*****************************************************************************
+#define SYSCTL_SREPHY_R0        0x00000001  // Ethernet PHY Module Software
+                                            // Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCAN_R1         0x00000002  // CAN Module 1 Software Reset
+#define SYSCTL_SRCAN_R0         0x00000001  // CAN Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRADC register.
+//
+//*****************************************************************************
+#define SYSCTL_SRADC_R1         0x00000002  // ADC Module 1 Software Reset
+#define SYSCTL_SRADC_R0         0x00000001  // ADC Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_SRACMP_R0        0x00000001  // Analog Comparator Module 0
+                                            // Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_SRPWM_R1         0x00000002  // PWM Module 1 Software Reset
+#define SYSCTL_SRPWM_R0         0x00000001  // PWM Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_SRQEI_R1         0x00000002  // QEI Module 1 Software Reset
+#define SYSCTL_SRQEI_R0         0x00000001  // QEI Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SREEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SREEPROM_R0      0x00000001  // EEPROM Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SRWTIMER_R5      0x00000020  // 32/64-Bit Wide General-Purpose
+                                            // Timer 5 Software Reset
+#define SYSCTL_SRWTIMER_R4      0x00000010  // 32/64-Bit Wide General-Purpose
+                                            // Timer 4 Software Reset
+#define SYSCTL_SRWTIMER_R3      0x00000008  // 32/64-Bit Wide General-Purpose
+                                            // Timer 3 Software Reset
+#define SYSCTL_SRWTIMER_R2      0x00000004  // 32/64-Bit Wide General-Purpose
+                                            // Timer 2 Software Reset
+#define SYSCTL_SRWTIMER_R1      0x00000002  // 32/64-Bit Wide General-Purpose
+                                            // Timer 1 Software Reset
+#define SYSCTL_SRWTIMER_R0      0x00000001  // 32/64-Bit Wide General-Purpose
+                                            // Timer 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCCM register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCCM_R0         0x00000001  // CRC and Cryptographic Modules
+                                            // Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRLCD register.
+//
+//*****************************************************************************
+#define SYSCTL_SRLCD_R0         0x00000001  // LCD Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SROWIRE register.
+//
+//*****************************************************************************
+#define SYSCTL_SROWIRE_R0       0x00000001  // 1-Wire Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SREMAC register.
+//
+//*****************************************************************************
+#define SYSCTL_SREMAC_R0        0x00000001  // Ethernet Controller MAC Module 0
+                                            // Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCWD_R1        0x00000002  // Watchdog Timer 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCWD_R0        0x00000001  // Watchdog Timer 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCTIMER_R7     0x00000080  // 16/32-Bit General-Purpose Timer
+                                            // 7 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R6     0x00000040  // 16/32-Bit General-Purpose Timer
+                                            // 6 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R5     0x00000020  // 16/32-Bit General-Purpose Timer
+                                            // 5 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R4     0x00000010  // 16/32-Bit General-Purpose Timer
+                                            // 4 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R3     0x00000008  // 16/32-Bit General-Purpose Timer
+                                            // 3 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R2     0x00000004  // 16/32-Bit General-Purpose Timer
+                                            // 2 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R1     0x00000002  // 16/32-Bit General-Purpose Timer
+                                            // 1 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R0     0x00000001  // 16/32-Bit General-Purpose Timer
+                                            // 0 Run Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCGPIO
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCGPIO_R17     0x00020000  // GPIO Port T Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R16     0x00010000  // GPIO Port S Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R15     0x00008000  // GPIO Port R Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R14     0x00004000  // GPIO Port Q Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R13     0x00002000  // GPIO Port P Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R12     0x00001000  // GPIO Port N Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R11     0x00000800  // GPIO Port M Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R10     0x00000400  // GPIO Port L Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R9      0x00000200  // GPIO Port K Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R8      0x00000100  // GPIO Port J Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R7      0x00000080  // GPIO Port H Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R6      0x00000040  // GPIO Port G Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R5      0x00000020  // GPIO Port F Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R4      0x00000010  // GPIO Port E Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R3      0x00000008  // GPIO Port D Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R2      0x00000004  // GPIO Port C Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R1      0x00000002  // GPIO Port B Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R0      0x00000001  // GPIO Port A Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCDMA_R0       0x00000001  // uDMA Module Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCEPI register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCEPI_R0       0x00000001  // EPI Module Run Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCHIB_R0       0x00000001  // Hibernation Module Run Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCUART
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCUART_R7      0x00000080  // UART Module 7 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART_R6      0x00000040  // UART Module 6 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART_R5      0x00000020  // UART Module 5 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART_R4      0x00000010  // UART Module 4 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART_R3      0x00000008  // UART Module 3 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART_R2      0x00000004  // UART Module 2 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART_R1      0x00000002  // UART Module 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART_R0      0x00000001  // UART Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCSSI_R3       0x00000008  // SSI Module 3 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCSSI_R2       0x00000004  // SSI Module 2 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCSSI_R1       0x00000002  // SSI Module 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCSSI_R0       0x00000001  // SSI Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCI2C_R9       0x00000200  // I2C Module 9 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R8       0x00000100  // I2C Module 8 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R7       0x00000080  // I2C Module 7 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R6       0x00000040  // I2C Module 6 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R5       0x00000020  // I2C Module 5 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R4       0x00000010  // I2C Module 4 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R3       0x00000008  // I2C Module 3 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R2       0x00000004  // I2C Module 2 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R1       0x00000002  // I2C Module 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R0       0x00000001  // I2C Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCUSB_R0       0x00000001  // USB Module Run Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCEPHY
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCEPHY_R0      0x00000001  // Ethernet PHY Module Run Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCCAN_R1       0x00000002  // CAN Module 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCCAN_R0       0x00000001  // CAN Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCADC_R1       0x00000002  // ADC Module 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCADC_R0       0x00000001  // ADC Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCACMP
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCACMP_R0      0x00000001  // Analog Comparator Module 0 Run
+                                            // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCPWM_R1       0x00000002  // PWM Module 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCPWM_R0       0x00000001  // PWM Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCQEI_R1       0x00000002  // QEI Module 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCQEI_R0       0x00000001  // QEI Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCEEPROM_R0    0x00000001  // EEPROM Module Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCWTIMER_R5    0x00000020  // 32/64-Bit Wide General-Purpose
+                                            // Timer 5 Run Mode Clock Gating
+                                            // Control
+#define SYSCTL_RCGCWTIMER_R4    0x00000010  // 32/64-Bit Wide General-Purpose
+                                            // Timer 4 Run Mode Clock Gating
+                                            // Control
+#define SYSCTL_RCGCWTIMER_R3    0x00000008  // 32/64-Bit Wide General-Purpose
+                                            // Timer 3 Run Mode Clock Gating
+                                            // Control
+#define SYSCTL_RCGCWTIMER_R2    0x00000004  // 32/64-Bit Wide General-Purpose
+                                            // Timer 2 Run Mode Clock Gating
+                                            // Control
+#define SYSCTL_RCGCWTIMER_R1    0x00000002  // 32/64-Bit Wide General-Purpose
+                                            // Timer 1 Run Mode Clock Gating
+                                            // Control
+#define SYSCTL_RCGCWTIMER_R0    0x00000001  // 32/64-Bit Wide General-Purpose
+                                            // Timer 0 Run Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCCCM register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCCCM_R0       0x00000001  // CRC and Cryptographic Modules
+                                            // Run Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCLCD register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCLCD_R0       0x00000001  // LCD Controller Module 0 Run Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCOWIRE
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCOWIRE_R0     0x00000001  // 1-Wire Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCEMAC
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCEMAC_R0      0x00000001  // Ethernet MAC Module 0 Run Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCWD_S1        0x00000002  // Watchdog Timer 1 Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_SCGCWD_S0        0x00000001  // Watchdog Timer 0 Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCTIMER_S7     0x00000080  // 16/32-Bit General-Purpose Timer
+                                            // 7 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCTIMER_S6     0x00000040  // 16/32-Bit General-Purpose Timer
+                                            // 6 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCTIMER_S5     0x00000020  // 16/32-Bit General-Purpose Timer
+                                            // 5 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCTIMER_S4     0x00000010  // 16/32-Bit General-Purpose Timer
+                                            // 4 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCTIMER_S3     0x00000008  // 16/32-Bit General-Purpose Timer
+                                            // 3 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCTIMER_S2     0x00000004  // 16/32-Bit General-Purpose Timer
+                                            // 2 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCTIMER_S1     0x00000002  // 16/32-Bit General-Purpose Timer
+                                            // 1 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCTIMER_S0     0x00000001  // 16/32-Bit General-Purpose Timer
+                                            // 0 Sleep Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCGPIO
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCGPIO_S17     0x00020000  // GPIO Port T Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S16     0x00010000  // GPIO Port S Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S15     0x00008000  // GPIO Port R Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S14     0x00004000  // GPIO Port Q Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S13     0x00002000  // GPIO Port P Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S12     0x00001000  // GPIO Port N Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S11     0x00000800  // GPIO Port M Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S10     0x00000400  // GPIO Port L Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S9      0x00000200  // GPIO Port K Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S8      0x00000100  // GPIO Port J Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S7      0x00000080  // GPIO Port H Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S6      0x00000040  // GPIO Port G Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S5      0x00000020  // GPIO Port F Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S4      0x00000010  // GPIO Port E Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S3      0x00000008  // GPIO Port D Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S2      0x00000004  // GPIO Port C Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S1      0x00000002  // GPIO Port B Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S0      0x00000001  // GPIO Port A Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCDMA_S0       0x00000001  // uDMA Module Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCEPI register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCEPI_S0       0x00000001  // EPI Module Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCHIB_S0       0x00000001  // Hibernation Module Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCUART
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCUART_S7      0x00000080  // UART Module 7 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART_S6      0x00000040  // UART Module 6 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART_S5      0x00000020  // UART Module 5 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART_S4      0x00000010  // UART Module 4 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART_S3      0x00000008  // UART Module 3 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART_S2      0x00000004  // UART Module 2 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART_S1      0x00000002  // UART Module 1 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART_S0      0x00000001  // UART Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCSSI_S3       0x00000008  // SSI Module 3 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCSSI_S2       0x00000004  // SSI Module 2 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCSSI_S1       0x00000002  // SSI Module 1 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCSSI_S0       0x00000001  // SSI Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCI2C_S9       0x00000200  // I2C Module 9 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S8       0x00000100  // I2C Module 8 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S7       0x00000080  // I2C Module 7 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S6       0x00000040  // I2C Module 6 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S5       0x00000020  // I2C Module 5 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S4       0x00000010  // I2C Module 4 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S3       0x00000008  // I2C Module 3 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S2       0x00000004  // I2C Module 2 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S1       0x00000002  // I2C Module 1 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S0       0x00000001  // I2C Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCUSB_S0       0x00000001  // USB Module Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCEPHY
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCEPHY_S0      0x00000001  // PHY Module Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCCAN_S1       0x00000002  // CAN Module 1 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCCAN_S0       0x00000001  // CAN Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCADC_S1       0x00000002  // ADC Module 1 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCADC_S0       0x00000001  // ADC Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCACMP
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCACMP_S0      0x00000001  // Analog Comparator Module 0 Sleep
+                                            // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCPWM_S1       0x00000002  // PWM Module 1 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCPWM_S0       0x00000001  // PWM Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCQEI_S1       0x00000002  // QEI Module 1 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCQEI_S0       0x00000001  // QEI Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCEEPROM_S0    0x00000001  // EEPROM Module Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCWTIMER_S5    0x00000020  // 32/64-Bit Wide General-Purpose
+                                            // Timer 5 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCWTIMER_S4    0x00000010  // 32/64-Bit Wide General-Purpose
+                                            // Timer 4 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCWTIMER_S3    0x00000008  // 32/64-Bit Wide General-Purpose
+                                            // Timer 3 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCWTIMER_S2    0x00000004  // 32/64-Bit Wide General-Purpose
+                                            // Timer 2 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCWTIMER_S1    0x00000002  // 32/64-Bit Wide General-Purpose
+                                            // Timer 1 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCWTIMER_S0    0x00000001  // 32/64-Bit Wide General-Purpose
+                                            // Timer 0 Sleep Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCCCM register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCCCM_S0       0x00000001  // CRC and Cryptographic Modules
+                                            // Sleep Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCLCD register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCLCD_S0       0x00000001  // LCD Controller Module 0 Sleep
+                                            // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCOWIRE
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCOWIRE_S0     0x00000001  // 1-Wire Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCEMAC
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCEMAC_S0      0x00000001  // Ethernet MAC Module 0 Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCWD_D1        0x00000002  // Watchdog Timer 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCWD_D0        0x00000001  // Watchdog Timer 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCTIMER_D7     0x00000080  // 16/32-Bit General-Purpose Timer
+                                            // 7 Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCTIMER_D6     0x00000040  // 16/32-Bit General-Purpose Timer
+                                            // 6 Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCTIMER_D5     0x00000020  // 16/32-Bit General-Purpose Timer
+                                            // 5 Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCTIMER_D4     0x00000010  // 16/32-Bit General-Purpose Timer
+                                            // 4 Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCTIMER_D3     0x00000008  // 16/32-Bit General-Purpose Timer
+                                            // 3 Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCTIMER_D2     0x00000004  // 16/32-Bit General-Purpose Timer
+                                            // 2 Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCTIMER_D1     0x00000002  // 16/32-Bit General-Purpose Timer
+                                            // 1 Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCTIMER_D0     0x00000001  // 16/32-Bit General-Purpose Timer
+                                            // 0 Deep-Sleep Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCGPIO
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCGPIO_D17     0x00020000  // GPIO Port T Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D16     0x00010000  // GPIO Port S Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D15     0x00008000  // GPIO Port R Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D14     0x00004000  // GPIO Port Q Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D13     0x00002000  // GPIO Port P Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D12     0x00001000  // GPIO Port N Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D11     0x00000800  // GPIO Port M Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D10     0x00000400  // GPIO Port L Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D9      0x00000200  // GPIO Port K Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D8      0x00000100  // GPIO Port J Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D7      0x00000080  // GPIO Port H Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D6      0x00000040  // GPIO Port G Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D5      0x00000020  // GPIO Port F Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D4      0x00000010  // GPIO Port E Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D3      0x00000008  // GPIO Port D Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D2      0x00000004  // GPIO Port C Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D1      0x00000002  // GPIO Port B Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D0      0x00000001  // GPIO Port A Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCDMA_D0       0x00000001  // uDMA Module Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCEPI register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCEPI_D0       0x00000001  // EPI Module Deep-Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCHIB_D0       0x00000001  // Hibernation Module Deep-Sleep
+                                            // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCUART
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCUART_D7      0x00000080  // UART Module 7 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART_D6      0x00000040  // UART Module 6 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART_D5      0x00000020  // UART Module 5 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART_D4      0x00000010  // UART Module 4 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART_D3      0x00000008  // UART Module 3 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART_D2      0x00000004  // UART Module 2 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART_D1      0x00000002  // UART Module 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART_D0      0x00000001  // UART Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCSSI_D3       0x00000008  // SSI Module 3 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCSSI_D2       0x00000004  // SSI Module 2 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCSSI_D1       0x00000002  // SSI Module 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCSSI_D0       0x00000001  // SSI Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCI2C_D9       0x00000200  // I2C Module 9 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D8       0x00000100  // I2C Module 8 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D7       0x00000080  // I2C Module 7 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D6       0x00000040  // I2C Module 6 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D5       0x00000020  // I2C Module 5 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D4       0x00000010  // I2C Module 4 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D3       0x00000008  // I2C Module 3 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D2       0x00000004  // I2C Module 2 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D1       0x00000002  // I2C Module 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D0       0x00000001  // I2C Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCUSB_D0       0x00000001  // USB Module Deep-Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCEPHY
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCEPHY_D0      0x00000001  // PHY Module Deep-Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCCAN_D1       0x00000002  // CAN Module 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCCAN_D0       0x00000001  // CAN Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCADC_D1       0x00000002  // ADC Module 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCADC_D0       0x00000001  // ADC Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCACMP
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCACMP_D0      0x00000001  // Analog Comparator Module 0
+                                            // Deep-Sleep Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCPWM_D1       0x00000002  // PWM Module 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCPWM_D0       0x00000001  // PWM Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCQEI_D1       0x00000002  // QEI Module 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCQEI_D0       0x00000001  // QEI Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCEEPROM_D0    0x00000001  // EEPROM Module Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCWTIMER_D5    0x00000020  // 32/64-Bit Wide General-Purpose
+                                            // Timer 5 Deep-Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_DCGCWTIMER_D4    0x00000010  // 32/64-Bit Wide General-Purpose
+                                            // Timer 4 Deep-Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_DCGCWTIMER_D3    0x00000008  // 32/64-Bit Wide General-Purpose
+                                            // Timer 3 Deep-Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_DCGCWTIMER_D2    0x00000004  // 32/64-Bit Wide General-Purpose
+                                            // Timer 2 Deep-Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_DCGCWTIMER_D1    0x00000002  // 32/64-Bit Wide General-Purpose
+                                            // Timer 1 Deep-Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_DCGCWTIMER_D0    0x00000001  // 32/64-Bit Wide General-Purpose
+                                            // Timer 0 Deep-Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCCCM register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCCCM_D0       0x00000001  // CRC and Cryptographic Modules
+                                            // Deep-Sleep Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCLCD register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCLCD_D0       0x00000001  // LCD Controller Module 0
+                                            // Deep-Sleep Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCOWIRE
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCOWIRE_D0     0x00000001  // 1-Wire Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCEMAC
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCEMAC_D0      0x00000001  // Ethernet MAC Module 0 Deep-Sleep
+                                            // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_PCWD_P1          0x00000002  // Watchdog Timer 1 Power Control
+#define SYSCTL_PCWD_P0          0x00000001  // Watchdog Timer 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_PCTIMER_P7       0x00000080  // General-Purpose Timer 7 Power
+                                            // Control
+#define SYSCTL_PCTIMER_P6       0x00000040  // General-Purpose Timer 6 Power
+                                            // Control
+#define SYSCTL_PCTIMER_P5       0x00000020  // General-Purpose Timer 5 Power
+                                            // Control
+#define SYSCTL_PCTIMER_P4       0x00000010  // General-Purpose Timer 4 Power
+                                            // Control
+#define SYSCTL_PCTIMER_P3       0x00000008  // General-Purpose Timer 3 Power
+                                            // Control
+#define SYSCTL_PCTIMER_P2       0x00000004  // General-Purpose Timer 2 Power
+                                            // Control
+#define SYSCTL_PCTIMER_P1       0x00000002  // General-Purpose Timer 1 Power
+                                            // Control
+#define SYSCTL_PCTIMER_P0       0x00000001  // General-Purpose Timer 0 Power
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_PCGPIO_P17       0x00020000  // GPIO Port T Power Control
+#define SYSCTL_PCGPIO_P16       0x00010000  // GPIO Port S Power Control
+#define SYSCTL_PCGPIO_P15       0x00008000  // GPIO Port R Power Control
+#define SYSCTL_PCGPIO_P14       0x00004000  // GPIO Port Q Power Control
+#define SYSCTL_PCGPIO_P13       0x00002000  // GPIO Port P Power Control
+#define SYSCTL_PCGPIO_P12       0x00001000  // GPIO Port N Power Control
+#define SYSCTL_PCGPIO_P11       0x00000800  // GPIO Port M Power Control
+#define SYSCTL_PCGPIO_P10       0x00000400  // GPIO Port L Power Control
+#define SYSCTL_PCGPIO_P9        0x00000200  // GPIO Port K Power Control
+#define SYSCTL_PCGPIO_P8        0x00000100  // GPIO Port J Power Control
+#define SYSCTL_PCGPIO_P7        0x00000080  // GPIO Port H Power Control
+#define SYSCTL_PCGPIO_P6        0x00000040  // GPIO Port G Power Control
+#define SYSCTL_PCGPIO_P5        0x00000020  // GPIO Port F Power Control
+#define SYSCTL_PCGPIO_P4        0x00000010  // GPIO Port E Power Control
+#define SYSCTL_PCGPIO_P3        0x00000008  // GPIO Port D Power Control
+#define SYSCTL_PCGPIO_P2        0x00000004  // GPIO Port C Power Control
+#define SYSCTL_PCGPIO_P1        0x00000002  // GPIO Port B Power Control
+#define SYSCTL_PCGPIO_P0        0x00000001  // GPIO Port A Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_PCDMA_P0         0x00000001  // uDMA Module Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCEPI register.
+//
+//*****************************************************************************
+#define SYSCTL_PCEPI_P0         0x00000001  // EPI Module Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_PCHIB_P0         0x00000001  // Hibernation Module Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCUART register.
+//
+//*****************************************************************************
+#define SYSCTL_PCUART_P7        0x00000080  // UART Module 7 Power Control
+#define SYSCTL_PCUART_P6        0x00000040  // UART Module 6 Power Control
+#define SYSCTL_PCUART_P5        0x00000020  // UART Module 5 Power Control
+#define SYSCTL_PCUART_P4        0x00000010  // UART Module 4 Power Control
+#define SYSCTL_PCUART_P3        0x00000008  // UART Module 3 Power Control
+#define SYSCTL_PCUART_P2        0x00000004  // UART Module 2 Power Control
+#define SYSCTL_PCUART_P1        0x00000002  // UART Module 1 Power Control
+#define SYSCTL_PCUART_P0        0x00000001  // UART Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_PCSSI_P3         0x00000008  // SSI Module 3 Power Control
+#define SYSCTL_PCSSI_P2         0x00000004  // SSI Module 2 Power Control
+#define SYSCTL_PCSSI_P1         0x00000002  // SSI Module 1 Power Control
+#define SYSCTL_PCSSI_P0         0x00000001  // SSI Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_PCI2C_P9         0x00000200  // I2C Module 9 Power Control
+#define SYSCTL_PCI2C_P8         0x00000100  // I2C Module 8 Power Control
+#define SYSCTL_PCI2C_P7         0x00000080  // I2C Module 7 Power Control
+#define SYSCTL_PCI2C_P6         0x00000040  // I2C Module 6 Power Control
+#define SYSCTL_PCI2C_P5         0x00000020  // I2C Module 5 Power Control
+#define SYSCTL_PCI2C_P4         0x00000010  // I2C Module 4 Power Control
+#define SYSCTL_PCI2C_P3         0x00000008  // I2C Module 3 Power Control
+#define SYSCTL_PCI2C_P2         0x00000004  // I2C Module 2 Power Control
+#define SYSCTL_PCI2C_P1         0x00000002  // I2C Module 1 Power Control
+#define SYSCTL_PCI2C_P0         0x00000001  // I2C Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_PCUSB_P0         0x00000001  // USB Module Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCEPHY register.
+//
+//*****************************************************************************
+#define SYSCTL_PCEPHY_P0        0x00000001  // Ethernet PHY Module Power
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PCCAN_P1         0x00000002  // CAN Module 1 Power Control
+#define SYSCTL_PCCAN_P0         0x00000001  // CAN Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_PCADC_P1         0x00000002  // ADC Module 1 Power Control
+#define SYSCTL_PCADC_P0         0x00000001  // ADC Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_PCACMP_P0        0x00000001  // Analog Comparator Module 0 Power
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_PCPWM_P0         0x00000001  // PWM Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_PCQEI_P0         0x00000001  // QEI Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PCEEPROM_P0      0x00000001  // EEPROM Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCCCM register.
+//
+//*****************************************************************************
+#define SYSCTL_PCCCM_P0         0x00000001  // CRC and Cryptographic Modules
+                                            // Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCLCD register.
+//
+//*****************************************************************************
+#define SYSCTL_PCLCD_P0         0x00000001  // LCD Controller Module 0 Power
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCOWIRE register.
+//
+//*****************************************************************************
+#define SYSCTL_PCOWIRE_P0       0x00000001  // 1-Wire Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCEMAC register.
+//
+//*****************************************************************************
+#define SYSCTL_PCEMAC_P0        0x00000001  // Ethernet MAC Module 0 Power
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRWD register.
+//
+//*****************************************************************************
+#define SYSCTL_PRWD_R1          0x00000002  // Watchdog Timer 1 Peripheral
+                                            // Ready
+#define SYSCTL_PRWD_R0          0x00000001  // Watchdog Timer 0 Peripheral
+                                            // Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_PRTIMER_R7       0x00000080  // 16/32-Bit General-Purpose Timer
+                                            // 7 Peripheral Ready
+#define SYSCTL_PRTIMER_R6       0x00000040  // 16/32-Bit General-Purpose Timer
+                                            // 6 Peripheral Ready
+#define SYSCTL_PRTIMER_R5       0x00000020  // 16/32-Bit General-Purpose Timer
+                                            // 5 Peripheral Ready
+#define SYSCTL_PRTIMER_R4       0x00000010  // 16/32-Bit General-Purpose Timer
+                                            // 4 Peripheral Ready
+#define SYSCTL_PRTIMER_R3       0x00000008  // 16/32-Bit General-Purpose Timer
+                                            // 3 Peripheral Ready
+#define SYSCTL_PRTIMER_R2       0x00000004  // 16/32-Bit General-Purpose Timer
+                                            // 2 Peripheral Ready
+#define SYSCTL_PRTIMER_R1       0x00000002  // 16/32-Bit General-Purpose Timer
+                                            // 1 Peripheral Ready
+#define SYSCTL_PRTIMER_R0       0x00000001  // 16/32-Bit General-Purpose Timer
+                                            // 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_PRGPIO_R17       0x00020000  // GPIO Port T Peripheral Ready
+#define SYSCTL_PRGPIO_R16       0x00010000  // GPIO Port S Peripheral Ready
+#define SYSCTL_PRGPIO_R15       0x00008000  // GPIO Port R Peripheral Ready
+#define SYSCTL_PRGPIO_R14       0x00004000  // GPIO Port Q Peripheral Ready
+#define SYSCTL_PRGPIO_R13       0x00002000  // GPIO Port P Peripheral Ready
+#define SYSCTL_PRGPIO_R12       0x00001000  // GPIO Port N Peripheral Ready
+#define SYSCTL_PRGPIO_R11       0x00000800  // GPIO Port M Peripheral Ready
+#define SYSCTL_PRGPIO_R10       0x00000400  // GPIO Port L Peripheral Ready
+#define SYSCTL_PRGPIO_R9        0x00000200  // GPIO Port K Peripheral Ready
+#define SYSCTL_PRGPIO_R8        0x00000100  // GPIO Port J Peripheral Ready
+#define SYSCTL_PRGPIO_R7        0x00000080  // GPIO Port H Peripheral Ready
+#define SYSCTL_PRGPIO_R6        0x00000040  // GPIO Port G Peripheral Ready
+#define SYSCTL_PRGPIO_R5        0x00000020  // GPIO Port F Peripheral Ready
+#define SYSCTL_PRGPIO_R4        0x00000010  // GPIO Port E Peripheral Ready
+#define SYSCTL_PRGPIO_R3        0x00000008  // GPIO Port D Peripheral Ready
+#define SYSCTL_PRGPIO_R2        0x00000004  // GPIO Port C Peripheral Ready
+#define SYSCTL_PRGPIO_R1        0x00000002  // GPIO Port B Peripheral Ready
+#define SYSCTL_PRGPIO_R0        0x00000001  // GPIO Port A Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_PRDMA_R0         0x00000001  // uDMA Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PREPI register.
+//
+//*****************************************************************************
+#define SYSCTL_PREPI_R0         0x00000001  // EPI Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_PRHIB_R0         0x00000001  // Hibernation Module Peripheral
+                                            // Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRUART register.
+//
+//*****************************************************************************
+#define SYSCTL_PRUART_R7        0x00000080  // UART Module 7 Peripheral Ready
+#define SYSCTL_PRUART_R6        0x00000040  // UART Module 6 Peripheral Ready
+#define SYSCTL_PRUART_R5        0x00000020  // UART Module 5 Peripheral Ready
+#define SYSCTL_PRUART_R4        0x00000010  // UART Module 4 Peripheral Ready
+#define SYSCTL_PRUART_R3        0x00000008  // UART Module 3 Peripheral Ready
+#define SYSCTL_PRUART_R2        0x00000004  // UART Module 2 Peripheral Ready
+#define SYSCTL_PRUART_R1        0x00000002  // UART Module 1 Peripheral Ready
+#define SYSCTL_PRUART_R0        0x00000001  // UART Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_PRSSI_R3         0x00000008  // SSI Module 3 Peripheral Ready
+#define SYSCTL_PRSSI_R2         0x00000004  // SSI Module 2 Peripheral Ready
+#define SYSCTL_PRSSI_R1         0x00000002  // SSI Module 1 Peripheral Ready
+#define SYSCTL_PRSSI_R0         0x00000001  // SSI Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_PRI2C_R9         0x00000200  // I2C Module 9 Peripheral Ready
+#define SYSCTL_PRI2C_R8         0x00000100  // I2C Module 8 Peripheral Ready
+#define SYSCTL_PRI2C_R7         0x00000080  // I2C Module 7 Peripheral Ready
+#define SYSCTL_PRI2C_R6         0x00000040  // I2C Module 6 Peripheral Ready
+#define SYSCTL_PRI2C_R5         0x00000020  // I2C Module 5 Peripheral Ready
+#define SYSCTL_PRI2C_R4         0x00000010  // I2C Module 4 Peripheral Ready
+#define SYSCTL_PRI2C_R3         0x00000008  // I2C Module 3 Peripheral Ready
+#define SYSCTL_PRI2C_R2         0x00000004  // I2C Module 2 Peripheral Ready
+#define SYSCTL_PRI2C_R1         0x00000002  // I2C Module 1 Peripheral Ready
+#define SYSCTL_PRI2C_R0         0x00000001  // I2C Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_PRUSB_R0         0x00000001  // USB Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PREPHY register.
+//
+//*****************************************************************************
+#define SYSCTL_PREPHY_R0        0x00000001  // Ethernet PHY Module Peripheral
+                                            // Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PRCAN_R1         0x00000002  // CAN Module 1 Peripheral Ready
+#define SYSCTL_PRCAN_R0         0x00000001  // CAN Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRADC register.
+//
+//*****************************************************************************
+#define SYSCTL_PRADC_R1         0x00000002  // ADC Module 1 Peripheral Ready
+#define SYSCTL_PRADC_R0         0x00000001  // ADC Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_PRACMP_R0        0x00000001  // Analog Comparator Module 0
+                                            // Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_PRPWM_R1         0x00000002  // PWM Module 1 Peripheral Ready
+#define SYSCTL_PRPWM_R0         0x00000001  // PWM Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_PRQEI_R1         0x00000002  // QEI Module 1 Peripheral Ready
+#define SYSCTL_PRQEI_R0         0x00000001  // QEI Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PREEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PREEPROM_R0      0x00000001  // EEPROM Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PRWTIMER_R5      0x00000020  // 32/64-Bit Wide General-Purpose
+                                            // Timer 5 Peripheral Ready
+#define SYSCTL_PRWTIMER_R4      0x00000010  // 32/64-Bit Wide General-Purpose
+                                            // Timer 4 Peripheral Ready
+#define SYSCTL_PRWTIMER_R3      0x00000008  // 32/64-Bit Wide General-Purpose
+                                            // Timer 3 Peripheral Ready
+#define SYSCTL_PRWTIMER_R2      0x00000004  // 32/64-Bit Wide General-Purpose
+                                            // Timer 2 Peripheral Ready
+#define SYSCTL_PRWTIMER_R1      0x00000002  // 32/64-Bit Wide General-Purpose
+                                            // Timer 1 Peripheral Ready
+#define SYSCTL_PRWTIMER_R0      0x00000001  // 32/64-Bit Wide General-Purpose
+                                            // Timer 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRCCM register.
+//
+//*****************************************************************************
+#define SYSCTL_PRCCM_R0         0x00000001  // CRC and Cryptographic Modules
+                                            // Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRLCD register.
+//
+//*****************************************************************************
+#define SYSCTL_PRLCD_R0         0x00000001  // LCD Controller Module 0
+                                            // Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PROWIRE register.
+//
+//*****************************************************************************
+#define SYSCTL_PROWIRE_R0       0x00000001  // 1-Wire Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PREMAC register.
+//
+//*****************************************************************************
+#define SYSCTL_PREMAC_R0        0x00000001  // Ethernet MAC Module 0 Peripheral
+                                            // Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_UNIQUEID0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_UNIQUEID0_ID_M   0xFFFFFFFF  // Unique ID
+#define SYSCTL_UNIQUEID0_ID_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_UNIQUEID1
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_UNIQUEID1_ID_M   0xFFFFFFFF  // Unique ID
+#define SYSCTL_UNIQUEID1_ID_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_UNIQUEID2
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_UNIQUEID2_ID_M   0xFFFFFFFF  // Unique ID
+#define SYSCTL_UNIQUEID2_ID_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_UNIQUEID3
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_UNIQUEID3_ID_M   0xFFFFFFFF  // Unique ID
+#define SYSCTL_UNIQUEID3_ID_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_CCMCGREQ
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_CCMCGREQ_DESCFG  0x00000004  // DES Clock Gating Request
+#define SYSCTL_CCMCGREQ_AESCFG  0x00000002  // AES Clock Gating Request
+#define SYSCTL_CCMCGREQ_SHACFG  0x00000001  // SHA/MD5 Clock Gating Request
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DID0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DID0_CLASS_BLIZZARD                                            \
+                                0x00050000  // Tiva(TM) C Series TM4C123-class
+                                            // microcontrollers
+#define SYSCTL_DID0_CLASS_SNOWFLAKE                                           \
+                                0x000A0000  // Tiva(TM) C Series TM4C129-class
+                                            // microcontrollers
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_RESC
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RESC_HIB         0x00000040  // HIB Reset
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_PWRTC
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PWRTC_VDDA_UBOR0 0x00000010  // VDDA Under BOR0 Status
+#define SYSCTL_PWRTC_VDD_UBOR0  0x00000001  // VDD Under BOR0 Status
+
+#endif
+
+#endif // __HW_SYSCTL_H__
diff --git a/os/common/ext/TivaWare/inc/hw_sysexc.h b/os/common/ext/TivaWare/inc/hw_sysexc.h
new file mode 100644
index 0000000..a6eec99
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_sysexc.h
@@ -0,0 +1,132 @@
+//*****************************************************************************
+//
+// hw_sysexc.h - Macros used when accessing the system exception module.
+//
+// Copyright (c) 2011-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_SYSEXC_H__
+#define __HW_SYSEXC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the System Exception Module register
+// addresses.
+//
+//*****************************************************************************
+#define SYSEXC_RIS              0x400F9000  // System Exception Raw Interrupt
+                                            // Status
+#define SYSEXC_IM               0x400F9004  // System Exception Interrupt Mask
+#define SYSEXC_MIS              0x400F9008  // System Exception Masked
+                                            // Interrupt Status
+#define SYSEXC_IC               0x400F900C  // System Exception Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_RIS register.
+//
+//*****************************************************************************
+#define SYSEXC_RIS_FPIXCRIS     0x00000020  // Floating-Point Inexact Exception
+                                            // Raw Interrupt Status
+#define SYSEXC_RIS_FPOFCRIS     0x00000010  // Floating-Point Overflow
+                                            // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPUFCRIS     0x00000008  // Floating-Point Underflow
+                                            // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPIOCRIS     0x00000004  // Floating-Point Invalid Operation
+                                            // Raw Interrupt Status
+#define SYSEXC_RIS_FPDZCRIS     0x00000002  // Floating-Point Divide By 0
+                                            // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPIDCRIS     0x00000001  // Floating-Point Input Denormal
+                                            // Exception Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_IM register.
+//
+//*****************************************************************************
+#define SYSEXC_IM_FPIXCIM       0x00000020  // Floating-Point Inexact Exception
+                                            // Interrupt Mask
+#define SYSEXC_IM_FPOFCIM       0x00000010  // Floating-Point Overflow
+                                            // Exception Interrupt Mask
+#define SYSEXC_IM_FPUFCIM       0x00000008  // Floating-Point Underflow
+                                            // Exception Interrupt Mask
+#define SYSEXC_IM_FPIOCIM       0x00000004  // Floating-Point Invalid Operation
+                                            // Interrupt Mask
+#define SYSEXC_IM_FPDZCIM       0x00000002  // Floating-Point Divide By 0
+                                            // Exception Interrupt Mask
+#define SYSEXC_IM_FPIDCIM       0x00000001  // Floating-Point Input Denormal
+                                            // Exception Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_MIS register.
+//
+//*****************************************************************************
+#define SYSEXC_MIS_FPIXCMIS     0x00000020  // Floating-Point Inexact Exception
+                                            // Masked Interrupt Status
+#define SYSEXC_MIS_FPOFCMIS     0x00000010  // Floating-Point Overflow
+                                            // Exception Masked Interrupt
+                                            // Status
+#define SYSEXC_MIS_FPUFCMIS     0x00000008  // Floating-Point Underflow
+                                            // Exception Masked Interrupt
+                                            // Status
+#define SYSEXC_MIS_FPIOCMIS     0x00000004  // Floating-Point Invalid Operation
+                                            // Masked Interrupt Status
+#define SYSEXC_MIS_FPDZCMIS     0x00000002  // Floating-Point Divide By 0
+                                            // Exception Masked Interrupt
+                                            // Status
+#define SYSEXC_MIS_FPIDCMIS     0x00000001  // Floating-Point Input Denormal
+                                            // Exception Masked Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_IC register.
+//
+//*****************************************************************************
+#define SYSEXC_IC_FPIXCIC       0x00000020  // Floating-Point Inexact Exception
+                                            // Interrupt Clear
+#define SYSEXC_IC_FPOFCIC       0x00000010  // Floating-Point Overflow
+                                            // Exception Interrupt Clear
+#define SYSEXC_IC_FPUFCIC       0x00000008  // Floating-Point Underflow
+                                            // Exception Interrupt Clear
+#define SYSEXC_IC_FPIOCIC       0x00000004  // Floating-Point Invalid Operation
+                                            // Interrupt Clear
+#define SYSEXC_IC_FPDZCIC       0x00000002  // Floating-Point Divide By 0
+                                            // Exception Interrupt Clear
+#define SYSEXC_IC_FPIDCIC       0x00000001  // Floating-Point Input Denormal
+                                            // Exception Interrupt Clear
+
+#endif // __HW_SYSEXC_H__
diff --git a/os/common/ext/TivaWare/inc/hw_timer.h b/os/common/ext/TivaWare/inc/hw_timer.h
new file mode 100644
index 0000000..25a7ed9
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_timer.h
@@ -0,0 +1,700 @@
+//*****************************************************************************
+//
+// hw_timer.h - Defines and macros used when accessing the timer.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_TIMER_H__
+#define __HW_TIMER_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Timer register offsets.
+//
+//*****************************************************************************
+#define TIMER_O_CFG             0x00000000  // GPTM Configuration
+#define TIMER_O_TAMR            0x00000004  // GPTM Timer A Mode
+#define TIMER_O_TBMR            0x00000008  // GPTM Timer B Mode
+#define TIMER_O_CTL             0x0000000C  // GPTM Control
+#define TIMER_O_SYNC            0x00000010  // GPTM Synchronize
+#define TIMER_O_IMR             0x00000018  // GPTM Interrupt Mask
+#define TIMER_O_RIS             0x0000001C  // GPTM Raw Interrupt Status
+#define TIMER_O_MIS             0x00000020  // GPTM Masked Interrupt Status
+#define TIMER_O_ICR             0x00000024  // GPTM Interrupt Clear
+#define TIMER_O_TAILR           0x00000028  // GPTM Timer A Interval Load
+#define TIMER_O_TBILR           0x0000002C  // GPTM Timer B Interval Load
+#define TIMER_O_TAMATCHR        0x00000030  // GPTM Timer A Match
+#define TIMER_O_TBMATCHR        0x00000034  // GPTM Timer B Match
+#define TIMER_O_TAPR            0x00000038  // GPTM Timer A Prescale
+#define TIMER_O_TBPR            0x0000003C  // GPTM Timer B Prescale
+#define TIMER_O_TAPMR           0x00000040  // GPTM TimerA Prescale Match
+#define TIMER_O_TBPMR           0x00000044  // GPTM TimerB Prescale Match
+#define TIMER_O_TAR             0x00000048  // GPTM Timer A
+#define TIMER_O_TBR             0x0000004C  // GPTM Timer B
+#define TIMER_O_TAV             0x00000050  // GPTM Timer A Value
+#define TIMER_O_TBV             0x00000054  // GPTM Timer B Value
+#define TIMER_O_RTCPD           0x00000058  // GPTM RTC Predivide
+#define TIMER_O_TAPS            0x0000005C  // GPTM Timer A Prescale Snapshot
+#define TIMER_O_TBPS            0x00000060  // GPTM Timer B Prescale Snapshot
+#define TIMER_O_TAPV            0x00000064  // GPTM Timer A Prescale Value
+#define TIMER_O_TBPV            0x00000068  // GPTM Timer B Prescale Value
+#define TIMER_O_DMAEV           0x0000006C  // GPTM DMA Event
+#define TIMER_O_ADCEV           0x00000070  // GPTM ADC Event
+#define TIMER_O_PP              0x00000FC0  // GPTM Peripheral Properties
+#define TIMER_O_CC              0x00000FC8  // GPTM Clock Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CFG register.
+//
+//*****************************************************************************
+#define TIMER_CFG_M             0x00000007  // GPTM Configuration
+#define TIMER_CFG_32_BIT_TIMER  0x00000000  // For a 16/32-bit timer, this
+                                            // value selects the 32-bit timer
+                                            // configuration
+#define TIMER_CFG_32_BIT_RTC    0x00000001  // For a 16/32-bit timer, this
+                                            // value selects the 32-bit
+                                            // real-time clock (RTC) counter
+                                            // configuration
+#define TIMER_CFG_16_BIT        0x00000004  // For a 16/32-bit timer, this
+                                            // value selects the 16-bit timer
+                                            // configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMR register.
+//
+//*****************************************************************************
+#define TIMER_TAMR_TCACT_M      0x0000E000  // Timer Compare Action Select
+#define TIMER_TAMR_TCACT_NONE   0x00000000  // Disable compare operations
+#define TIMER_TAMR_TCACT_TOGGLE 0x00002000  // Toggle State on Time-Out
+#define TIMER_TAMR_TCACT_CLRTO  0x00004000  // Clear CCP on Time-Out
+#define TIMER_TAMR_TCACT_SETTO  0x00006000  // Set CCP on Time-Out
+#define TIMER_TAMR_TCACT_SETTOGTO                                             \
+                                0x00008000  // Set CCP immediately and toggle
+                                            // on Time-Out
+#define TIMER_TAMR_TCACT_CLRTOGTO                                             \
+                                0x0000A000  // Clear CCP immediately and toggle
+                                            // on Time-Out
+#define TIMER_TAMR_TCACT_SETCLRTO                                             \
+                                0x0000C000  // Set CCP immediately and clear on
+                                            // Time-Out
+#define TIMER_TAMR_TCACT_CLRSETTO                                             \
+                                0x0000E000  // Clear CCP immediately and set on
+                                            // Time-Out
+#define TIMER_TAMR_TACINTD      0x00001000  // One-shot/Periodic Interrupt
+                                            // Disable
+#define TIMER_TAMR_TAPLO        0x00000800  // GPTM Timer A PWM Legacy
+                                            // Operation
+#define TIMER_TAMR_TAMRSU       0x00000400  // GPTM Timer A Match Register
+                                            // Update
+#define TIMER_TAMR_TAPWMIE      0x00000200  // GPTM Timer A PWM Interrupt
+                                            // Enable
+#define TIMER_TAMR_TAILD        0x00000100  // GPTM Timer A Interval Load Write
+#define TIMER_TAMR_TASNAPS      0x00000080  // GPTM Timer A Snap-Shot Mode
+#define TIMER_TAMR_TAWOT        0x00000040  // GPTM Timer A Wait-on-Trigger
+#define TIMER_TAMR_TAMIE        0x00000020  // GPTM Timer A Match Interrupt
+                                            // Enable
+#define TIMER_TAMR_TACDIR       0x00000010  // GPTM Timer A Count Direction
+#define TIMER_TAMR_TAAMS        0x00000008  // GPTM Timer A Alternate Mode
+                                            // Select
+#define TIMER_TAMR_TACMR        0x00000004  // GPTM Timer A Capture Mode
+#define TIMER_TAMR_TAMR_M       0x00000003  // GPTM Timer A Mode
+#define TIMER_TAMR_TAMR_1_SHOT  0x00000001  // One-Shot Timer mode
+#define TIMER_TAMR_TAMR_PERIOD  0x00000002  // Periodic Timer mode
+#define TIMER_TAMR_TAMR_CAP     0x00000003  // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMR register.
+//
+//*****************************************************************************
+#define TIMER_TBMR_TCACT_M      0x0000E000  // Timer Compare Action Select
+#define TIMER_TBMR_TCACT_NONE   0x00000000  // Disable compare operations
+#define TIMER_TBMR_TCACT_TOGGLE 0x00002000  // Toggle State on Time-Out
+#define TIMER_TBMR_TCACT_CLRTO  0x00004000  // Clear CCP on Time-Out
+#define TIMER_TBMR_TCACT_SETTO  0x00006000  // Set CCP on Time-Out
+#define TIMER_TBMR_TCACT_SETTOGTO                                             \
+                                0x00008000  // Set CCP immediately and toggle
+                                            // on Time-Out
+#define TIMER_TBMR_TCACT_CLRTOGTO                                             \
+                                0x0000A000  // Clear CCP immediately and toggle
+                                            // on Time-Out
+#define TIMER_TBMR_TCACT_SETCLRTO                                             \
+                                0x0000C000  // Set CCP immediately and clear on
+                                            // Time-Out
+#define TIMER_TBMR_TCACT_CLRSETTO                                             \
+                                0x0000E000  // Clear CCP immediately and set on
+                                            // Time-Out
+#define TIMER_TBMR_TBCINTD      0x00001000  // One-Shot/Periodic Interrupt
+                                            // Disable
+#define TIMER_TBMR_TBPLO        0x00000800  // GPTM Timer B PWM Legacy
+                                            // Operation
+#define TIMER_TBMR_TBMRSU       0x00000400  // GPTM Timer B Match Register
+                                            // Update
+#define TIMER_TBMR_TBPWMIE      0x00000200  // GPTM Timer B PWM Interrupt
+                                            // Enable
+#define TIMER_TBMR_TBILD        0x00000100  // GPTM Timer B Interval Load Write
+#define TIMER_TBMR_TBSNAPS      0x00000080  // GPTM Timer B Snap-Shot Mode
+#define TIMER_TBMR_TBWOT        0x00000040  // GPTM Timer B Wait-on-Trigger
+#define TIMER_TBMR_TBMIE        0x00000020  // GPTM Timer B Match Interrupt
+                                            // Enable
+#define TIMER_TBMR_TBCDIR       0x00000010  // GPTM Timer B Count Direction
+#define TIMER_TBMR_TBAMS        0x00000008  // GPTM Timer B Alternate Mode
+                                            // Select
+#define TIMER_TBMR_TBCMR        0x00000004  // GPTM Timer B Capture Mode
+#define TIMER_TBMR_TBMR_M       0x00000003  // GPTM Timer B Mode
+#define TIMER_TBMR_TBMR_1_SHOT  0x00000001  // One-Shot Timer mode
+#define TIMER_TBMR_TBMR_PERIOD  0x00000002  // Periodic Timer mode
+#define TIMER_TBMR_TBMR_CAP     0x00000003  // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CTL register.
+//
+//*****************************************************************************
+#define TIMER_CTL_TBPWML        0x00004000  // GPTM Timer B PWM Output Level
+#define TIMER_CTL_TBOTE         0x00002000  // GPTM Timer B Output Trigger
+                                            // Enable
+#define TIMER_CTL_TBEVENT_M     0x00000C00  // GPTM Timer B Event Mode
+#define TIMER_CTL_TBEVENT_POS   0x00000000  // Positive edge
+#define TIMER_CTL_TBEVENT_NEG   0x00000400  // Negative edge
+#define TIMER_CTL_TBEVENT_BOTH  0x00000C00  // Both edges
+#define TIMER_CTL_TBSTALL       0x00000200  // GPTM Timer B Stall Enable
+#define TIMER_CTL_TBEN          0x00000100  // GPTM Timer B Enable
+#define TIMER_CTL_TAPWML        0x00000040  // GPTM Timer A PWM Output Level
+#define TIMER_CTL_TAOTE         0x00000020  // GPTM Timer A Output Trigger
+                                            // Enable
+#define TIMER_CTL_RTCEN         0x00000010  // GPTM RTC Stall Enable
+#define TIMER_CTL_TAEVENT_M     0x0000000C  // GPTM Timer A Event Mode
+#define TIMER_CTL_TAEVENT_POS   0x00000000  // Positive edge
+#define TIMER_CTL_TAEVENT_NEG   0x00000004  // Negative edge
+#define TIMER_CTL_TAEVENT_BOTH  0x0000000C  // Both edges
+#define TIMER_CTL_TASTALL       0x00000002  // GPTM Timer A Stall Enable
+#define TIMER_CTL_TAEN          0x00000001  // GPTM Timer A Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_SYNC register.
+//
+//*****************************************************************************
+#define TIMER_SYNC_SYNCWT5_M    0x00C00000  // Synchronize GPTM 32/64-Bit Timer
+                                            // 5
+#define TIMER_SYNC_SYNCWT5_NONE 0x00000000  // GPTM 32/64-Bit Timer 5 is not
+                                            // affected
+#define TIMER_SYNC_SYNCWT5_TA   0x00400000  // A timeout event for Timer A of
+                                            // GPTM 32/64-Bit Timer 5 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT5_TB   0x00800000  // A timeout event for Timer B of
+                                            // GPTM 32/64-Bit Timer 5 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT5_TATB 0x00C00000  // A timeout event for both Timer A
+                                            // and Timer B of GPTM 32/64-Bit
+                                            // Timer 5 is triggered
+#define TIMER_SYNC_SYNCWT4_M    0x00300000  // Synchronize GPTM 32/64-Bit Timer
+                                            // 4
+#define TIMER_SYNC_SYNCWT4_NONE 0x00000000  // GPTM 32/64-Bit Timer 4 is not
+                                            // affected
+#define TIMER_SYNC_SYNCWT4_TA   0x00100000  // A timeout event for Timer A of
+                                            // GPTM 32/64-Bit Timer 4 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT4_TB   0x00200000  // A timeout event for Timer B of
+                                            // GPTM 32/64-Bit Timer 4 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT4_TATB 0x00300000  // A timeout event for both Timer A
+                                            // and Timer B of GPTM 32/64-Bit
+                                            // Timer 4 is triggered
+#define TIMER_SYNC_SYNCWT3_M    0x000C0000  // Synchronize GPTM 32/64-Bit Timer
+                                            // 3
+#define TIMER_SYNC_SYNCWT3_NONE 0x00000000  // GPTM 32/64-Bit Timer 3 is not
+                                            // affected
+#define TIMER_SYNC_SYNCWT3_TA   0x00040000  // A timeout event for Timer A of
+                                            // GPTM 32/64-Bit Timer 3 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT3_TB   0x00080000  // A timeout event for Timer B of
+                                            // GPTM 32/64-Bit Timer 3 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT3_TATB 0x000C0000  // A timeout event for both Timer A
+                                            // and Timer B of GPTM 32/64-Bit
+                                            // Timer 3 is triggered
+#define TIMER_SYNC_SYNCWT2_M    0x00030000  // Synchronize GPTM 32/64-Bit Timer
+                                            // 2
+#define TIMER_SYNC_SYNCWT2_NONE 0x00000000  // GPTM 32/64-Bit Timer 2 is not
+                                            // affected
+#define TIMER_SYNC_SYNCWT2_TA   0x00010000  // A timeout event for Timer A of
+                                            // GPTM 32/64-Bit Timer 2 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT2_TB   0x00020000  // A timeout event for Timer B of
+                                            // GPTM 32/64-Bit Timer 2 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT2_TATB 0x00030000  // A timeout event for both Timer A
+                                            // and Timer B of GPTM 32/64-Bit
+                                            // Timer 2 is triggered
+#define TIMER_SYNC_SYNCT7_M     0x0000C000  // Synchronize GPTM Timer 7
+#define TIMER_SYNC_SYNCT7_NONE  0x00000000  // GPT7 is not affected
+#define TIMER_SYNC_SYNCT7_TA    0x00004000  // A timeout event for Timer A of
+                                            // GPTM7 is triggered
+#define TIMER_SYNC_SYNCT7_TB    0x00008000  // A timeout event for Timer B of
+                                            // GPTM7 is triggered
+#define TIMER_SYNC_SYNCT7_TATB  0x0000C000  // A timeout event for both Timer A
+                                            // and Timer B of GPTM7 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT1_M    0x0000C000  // Synchronize GPTM 32/64-Bit Timer
+                                            // 1
+#define TIMER_SYNC_SYNCWT1_NONE 0x00000000  // GPTM 32/64-Bit Timer 1 is not
+                                            // affected
+#define TIMER_SYNC_SYNCWT1_TA   0x00004000  // A timeout event for Timer A of
+                                            // GPTM 32/64-Bit Timer 1 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT1_TB   0x00008000  // A timeout event for Timer B of
+                                            // GPTM 32/64-Bit Timer 1 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT1_TATB 0x0000C000  // A timeout event for both Timer A
+                                            // and Timer B of GPTM 32/64-Bit
+                                            // Timer 1 is triggered
+#define TIMER_SYNC_SYNCWT0_M    0x00003000  // Synchronize GPTM 32/64-Bit Timer
+                                            // 0
+#define TIMER_SYNC_SYNCWT0_NONE 0x00000000  // GPTM 32/64-Bit Timer 0 is not
+                                            // affected
+#define TIMER_SYNC_SYNCWT0_TA   0x00001000  // A timeout event for Timer A of
+                                            // GPTM 32/64-Bit Timer 0 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT0_TB   0x00002000  // A timeout event for Timer B of
+                                            // GPTM 32/64-Bit Timer 0 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT0_TATB 0x00003000  // A timeout event for both Timer A
+                                            // and Timer B of GPTM 32/64-Bit
+                                            // Timer 0 is triggered
+#define TIMER_SYNC_SYNCT6_M     0x00003000  // Synchronize GPTM Timer 6
+#define TIMER_SYNC_SYNCT6_NONE  0x00000000  // GPTM6 is not affected
+#define TIMER_SYNC_SYNCT6_TA    0x00001000  // A timeout event for Timer A of
+                                            // GPTM6 is triggered
+#define TIMER_SYNC_SYNCT6_TB    0x00002000  // A timeout event for Timer B of
+                                            // GPTM6 is triggered
+#define TIMER_SYNC_SYNCT6_TATB  0x00003000  // A timeout event for both Timer A
+                                            // and Timer B of GPTM6 is
+                                            // triggered
+#define TIMER_SYNC_SYNCT5_M     0x00000C00  // Synchronize GPTM Timer 5
+#define TIMER_SYNC_SYNCT5_NONE  0x00000000  // GPTM5 is not affected
+#define TIMER_SYNC_SYNCT5_TA    0x00000400  // A timeout event for Timer A of
+                                            // GPTM5 is triggered
+#define TIMER_SYNC_SYNCT5_TB    0x00000800  // A timeout event for Timer B of
+                                            // GPTM5 is triggered
+#define TIMER_SYNC_SYNCT5_TATB  0x00000C00  // A timeout event for both Timer A
+                                            // and Timer B of GPTM5 is
+                                            // triggered
+#define TIMER_SYNC_SYNCT4_M     0x00000300  // Synchronize GPTM Timer 4
+#define TIMER_SYNC_SYNCT4_NONE  0x00000000  // GPTM4 is not affected
+#define TIMER_SYNC_SYNCT4_TA    0x00000100  // A timeout event for Timer A of
+                                            // GPTM4 is triggered
+#define TIMER_SYNC_SYNCT4_TB    0x00000200  // A timeout event for Timer B of
+                                            // GPTM4 is triggered
+#define TIMER_SYNC_SYNCT4_TATB  0x00000300  // A timeout event for both Timer A
+                                            // and Timer B of GPTM4 is
+                                            // triggered
+#define TIMER_SYNC_SYNCT3_M     0x000000C0  // Synchronize GPTM Timer 3
+#define TIMER_SYNC_SYNCT3_NONE  0x00000000  // GPTM3 is not affected
+#define TIMER_SYNC_SYNCT3_TA    0x00000040  // A timeout event for Timer A of
+                                            // GPTM3 is triggered
+#define TIMER_SYNC_SYNCT3_TB    0x00000080  // A timeout event for Timer B of
+                                            // GPTM3 is triggered
+#define TIMER_SYNC_SYNCT3_TATB  0x000000C0  // A timeout event for both Timer A
+                                            // and Timer B of GPTM3 is
+                                            // triggered
+#define TIMER_SYNC_SYNCT2_M     0x00000030  // Synchronize GPTM Timer 2
+#define TIMER_SYNC_SYNCT2_NONE  0x00000000  // GPTM2 is not affected
+#define TIMER_SYNC_SYNCT2_TA    0x00000010  // A timeout event for Timer A of
+                                            // GPTM2 is triggered
+#define TIMER_SYNC_SYNCT2_TB    0x00000020  // A timeout event for Timer B of
+                                            // GPTM2 is triggered
+#define TIMER_SYNC_SYNCT2_TATB  0x00000030  // A timeout event for both Timer A
+                                            // and Timer B of GPTM2 is
+                                            // triggered
+#define TIMER_SYNC_SYNCT1_M     0x0000000C  // Synchronize GPTM Timer 1
+#define TIMER_SYNC_SYNCT1_NONE  0x00000000  // GPTM1 is not affected
+#define TIMER_SYNC_SYNCT1_TA    0x00000004  // A timeout event for Timer A of
+                                            // GPTM1 is triggered
+#define TIMER_SYNC_SYNCT1_TB    0x00000008  // A timeout event for Timer B of
+                                            // GPTM1 is triggered
+#define TIMER_SYNC_SYNCT1_TATB  0x0000000C  // A timeout event for both Timer A
+                                            // and Timer B of GPTM1 is
+                                            // triggered
+#define TIMER_SYNC_SYNCT0_M     0x00000003  // Synchronize GPTM Timer 0
+#define TIMER_SYNC_SYNCT0_NONE  0x00000000  // GPTM0 is not affected
+#define TIMER_SYNC_SYNCT0_TA    0x00000001  // A timeout event for Timer A of
+                                            // GPTM0 is triggered
+#define TIMER_SYNC_SYNCT0_TB    0x00000002  // A timeout event for Timer B of
+                                            // GPTM0 is triggered
+#define TIMER_SYNC_SYNCT0_TATB  0x00000003  // A timeout event for both Timer A
+                                            // and Timer B of GPTM0 is
+                                            // triggered
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_IMR register.
+//
+//*****************************************************************************
+#define TIMER_IMR_WUEIM         0x00010000  // 32/64-Bit Wide GPTM Write Update
+                                            // Error Interrupt Mask
+#define TIMER_IMR_DMABIM        0x00002000  // GPTM Timer B DMA Done Interrupt
+                                            // Mask
+#define TIMER_IMR_TBMIM         0x00000800  // GPTM Timer B Match Interrupt
+                                            // Mask
+#define TIMER_IMR_CBEIM         0x00000400  // GPTM Timer B Capture Mode Event
+                                            // Interrupt Mask
+#define TIMER_IMR_CBMIM         0x00000200  // GPTM Timer B Capture Mode Match
+                                            // Interrupt Mask
+#define TIMER_IMR_TBTOIM        0x00000100  // GPTM Timer B Time-Out Interrupt
+                                            // Mask
+#define TIMER_IMR_DMAAIM        0x00000020  // GPTM Timer A DMA Done Interrupt
+                                            // Mask
+#define TIMER_IMR_TAMIM         0x00000010  // GPTM Timer A Match Interrupt
+                                            // Mask
+#define TIMER_IMR_RTCIM         0x00000008  // GPTM RTC Interrupt Mask
+#define TIMER_IMR_CAEIM         0x00000004  // GPTM Timer A Capture Mode Event
+                                            // Interrupt Mask
+#define TIMER_IMR_CAMIM         0x00000002  // GPTM Timer A Capture Mode Match
+                                            // Interrupt Mask
+#define TIMER_IMR_TATOIM        0x00000001  // GPTM Timer A Time-Out Interrupt
+                                            // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RIS register.
+//
+//*****************************************************************************
+#define TIMER_RIS_WUERIS        0x00010000  // 32/64-Bit Wide GPTM Write Update
+                                            // Error Raw Interrupt Status
+#define TIMER_RIS_DMABRIS       0x00002000  // GPTM Timer B DMA Done Raw
+                                            // Interrupt Status
+#define TIMER_RIS_TBMRIS        0x00000800  // GPTM Timer B Match Raw Interrupt
+#define TIMER_RIS_CBERIS        0x00000400  // GPTM Timer B Capture Mode Event
+                                            // Raw Interrupt
+#define TIMER_RIS_CBMRIS        0x00000200  // GPTM Timer B Capture Mode Match
+                                            // Raw Interrupt
+#define TIMER_RIS_TBTORIS       0x00000100  // GPTM Timer B Time-Out Raw
+                                            // Interrupt
+#define TIMER_RIS_DMAARIS       0x00000020  // GPTM Timer A DMA Done Raw
+                                            // Interrupt Status
+#define TIMER_RIS_TAMRIS        0x00000010  // GPTM Timer A Match Raw Interrupt
+#define TIMER_RIS_RTCRIS        0x00000008  // GPTM RTC Raw Interrupt
+#define TIMER_RIS_CAERIS        0x00000004  // GPTM Timer A Capture Mode Event
+                                            // Raw Interrupt
+#define TIMER_RIS_CAMRIS        0x00000002  // GPTM Timer A Capture Mode Match
+                                            // Raw Interrupt
+#define TIMER_RIS_TATORIS       0x00000001  // GPTM Timer A Time-Out Raw
+                                            // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_MIS register.
+//
+//*****************************************************************************
+#define TIMER_MIS_WUEMIS        0x00010000  // 32/64-Bit Wide GPTM Write Update
+                                            // Error Masked Interrupt Status
+#define TIMER_MIS_DMABMIS       0x00002000  // GPTM Timer B DMA Done Masked
+                                            // Interrupt
+#define TIMER_MIS_TBMMIS        0x00000800  // GPTM Timer B Match Masked
+                                            // Interrupt
+#define TIMER_MIS_CBEMIS        0x00000400  // GPTM Timer B Capture Mode Event
+                                            // Masked Interrupt
+#define TIMER_MIS_CBMMIS        0x00000200  // GPTM Timer B Capture Mode Match
+                                            // Masked Interrupt
+#define TIMER_MIS_TBTOMIS       0x00000100  // GPTM Timer B Time-Out Masked
+                                            // Interrupt
+#define TIMER_MIS_DMAAMIS       0x00000020  // GPTM Timer A DMA Done Masked
+                                            // Interrupt
+#define TIMER_MIS_TAMMIS        0x00000010  // GPTM Timer A Match Masked
+                                            // Interrupt
+#define TIMER_MIS_RTCMIS        0x00000008  // GPTM RTC Masked Interrupt
+#define TIMER_MIS_CAEMIS        0x00000004  // GPTM Timer A Capture Mode Event
+                                            // Masked Interrupt
+#define TIMER_MIS_CAMMIS        0x00000002  // GPTM Timer A Capture Mode Match
+                                            // Masked Interrupt
+#define TIMER_MIS_TATOMIS       0x00000001  // GPTM Timer A Time-Out Masked
+                                            // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_ICR register.
+//
+//*****************************************************************************
+#define TIMER_ICR_WUECINT       0x00010000  // 32/64-Bit Wide GPTM Write Update
+                                            // Error Interrupt Clear
+#define TIMER_ICR_DMABINT       0x00002000  // GPTM Timer B DMA Done Interrupt
+                                            // Clear
+#define TIMER_ICR_TBMCINT       0x00000800  // GPTM Timer B Match Interrupt
+                                            // Clear
+#define TIMER_ICR_CBECINT       0x00000400  // GPTM Timer B Capture Mode Event
+                                            // Interrupt Clear
+#define TIMER_ICR_CBMCINT       0x00000200  // GPTM Timer B Capture Mode Match
+                                            // Interrupt Clear
+#define TIMER_ICR_TBTOCINT      0x00000100  // GPTM Timer B Time-Out Interrupt
+                                            // Clear
+#define TIMER_ICR_DMAAINT       0x00000020  // GPTM Timer A DMA Done Interrupt
+                                            // Clear
+#define TIMER_ICR_TAMCINT       0x00000010  // GPTM Timer A Match Interrupt
+                                            // Clear
+#define TIMER_ICR_RTCCINT       0x00000008  // GPTM RTC Interrupt Clear
+#define TIMER_ICR_CAECINT       0x00000004  // GPTM Timer A Capture Mode Event
+                                            // Interrupt Clear
+#define TIMER_ICR_CAMCINT       0x00000002  // GPTM Timer A Capture Mode Match
+                                            // Interrupt Clear
+#define TIMER_ICR_TATOCINT      0x00000001  // GPTM Timer A Time-Out Raw
+                                            // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAILR register.
+//
+//*****************************************************************************
+#define TIMER_TAILR_M           0xFFFFFFFF  // GPTM Timer A Interval Load
+                                            // Register
+#define TIMER_TAILR_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBILR register.
+//
+//*****************************************************************************
+#define TIMER_TBILR_M           0xFFFFFFFF  // GPTM Timer B Interval Load
+                                            // Register
+#define TIMER_TBILR_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAMATCHR_TAMR_M   0xFFFFFFFF  // GPTM Timer A Match Register
+#define TIMER_TAMATCHR_TAMR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBMATCHR_TBMR_M   0xFFFFFFFF  // GPTM Timer B Match Register
+#define TIMER_TBMATCHR_TBMR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPR register.
+//
+//*****************************************************************************
+#define TIMER_TAPR_TAPSRH_M     0x0000FF00  // GPTM Timer A Prescale High Byte
+#define TIMER_TAPR_TAPSR_M      0x000000FF  // GPTM Timer A Prescale
+#define TIMER_TAPR_TAPSRH_S     8
+#define TIMER_TAPR_TAPSR_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPR register.
+//
+//*****************************************************************************
+#define TIMER_TBPR_TBPSRH_M     0x0000FF00  // GPTM Timer B Prescale High Byte
+#define TIMER_TBPR_TBPSR_M      0x000000FF  // GPTM Timer B Prescale
+#define TIMER_TBPR_TBPSRH_S     8
+#define TIMER_TBPR_TBPSR_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPMR register.
+//
+//*****************************************************************************
+#define TIMER_TAPMR_TAPSMRH_M   0x0000FF00  // GPTM Timer A Prescale Match High
+                                            // Byte
+#define TIMER_TAPMR_TAPSMR_M    0x000000FF  // GPTM TimerA Prescale Match
+#define TIMER_TAPMR_TAPSMRH_S   8
+#define TIMER_TAPMR_TAPSMR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPMR register.
+//
+//*****************************************************************************
+#define TIMER_TBPMR_TBPSMRH_M   0x0000FF00  // GPTM Timer B Prescale Match High
+                                            // Byte
+#define TIMER_TBPMR_TBPSMR_M    0x000000FF  // GPTM TimerB Prescale Match
+#define TIMER_TBPMR_TBPSMRH_S   8
+#define TIMER_TBPMR_TBPSMR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAR register.
+//
+//*****************************************************************************
+#define TIMER_TAR_M             0xFFFFFFFF  // GPTM Timer A Register
+#define TIMER_TAR_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBR register.
+//
+//*****************************************************************************
+#define TIMER_TBR_M             0xFFFFFFFF  // GPTM Timer B Register
+#define TIMER_TBR_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAV register.
+//
+//*****************************************************************************
+#define TIMER_TAV_M             0xFFFFFFFF  // GPTM Timer A Value
+#define TIMER_TAV_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBV register.
+//
+//*****************************************************************************
+#define TIMER_TBV_M             0xFFFFFFFF  // GPTM Timer B Value
+#define TIMER_TBV_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RTCPD register.
+//
+//*****************************************************************************
+#define TIMER_RTCPD_RTCPD_M     0x0000FFFF  // RTC Predivide Counter Value
+#define TIMER_RTCPD_RTCPD_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPS register.
+//
+//*****************************************************************************
+#define TIMER_TAPS_PSS_M        0x0000FFFF  // GPTM Timer A Prescaler Snapshot
+#define TIMER_TAPS_PSS_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPS register.
+//
+//*****************************************************************************
+#define TIMER_TBPS_PSS_M        0x0000FFFF  // GPTM Timer A Prescaler Value
+#define TIMER_TBPS_PSS_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPV register.
+//
+//*****************************************************************************
+#define TIMER_TAPV_PSV_M        0x0000FFFF  // GPTM Timer A Prescaler Value
+#define TIMER_TAPV_PSV_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPV register.
+//
+//*****************************************************************************
+#define TIMER_TBPV_PSV_M        0x0000FFFF  // GPTM Timer B Prescaler Value
+#define TIMER_TBPV_PSV_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_DMAEV register.
+//
+//*****************************************************************************
+#define TIMER_DMAEV_TBMDMAEN    0x00000800  // GPTM B Mode Match Event DMA
+                                            // Trigger Enable
+#define TIMER_DMAEV_CBEDMAEN    0x00000400  // GPTM B Capture Event DMA Trigger
+                                            // Enable
+#define TIMER_DMAEV_CBMDMAEN    0x00000200  // GPTM B Capture Match Event DMA
+                                            // Trigger Enable
+#define TIMER_DMAEV_TBTODMAEN   0x00000100  // GPTM B Time-Out Event DMA
+                                            // Trigger Enable
+#define TIMER_DMAEV_TAMDMAEN    0x00000010  // GPTM A Mode Match Event DMA
+                                            // Trigger Enable
+#define TIMER_DMAEV_RTCDMAEN    0x00000008  // GPTM A RTC Match Event DMA
+                                            // Trigger Enable
+#define TIMER_DMAEV_CAEDMAEN    0x00000004  // GPTM A Capture Event DMA Trigger
+                                            // Enable
+#define TIMER_DMAEV_CAMDMAEN    0x00000002  // GPTM A Capture Match Event DMA
+                                            // Trigger Enable
+#define TIMER_DMAEV_TATODMAEN   0x00000001  // GPTM A Time-Out Event DMA
+                                            // Trigger Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_ADCEV register.
+//
+//*****************************************************************************
+#define TIMER_ADCEV_TBMADCEN    0x00000800  // GPTM B Mode Match Event ADC
+                                            // Trigger Enable
+#define TIMER_ADCEV_CBEADCEN    0x00000400  // GPTM B Capture Event ADC Trigger
+                                            // Enable
+#define TIMER_ADCEV_CBMADCEN    0x00000200  // GPTM B Capture Match Event ADC
+                                            // Trigger Enable
+#define TIMER_ADCEV_TBTOADCEN   0x00000100  // GPTM B Time-Out Event ADC
+                                            // Trigger Enable
+#define TIMER_ADCEV_TAMADCEN    0x00000010  // GPTM A Mode Match Event ADC
+                                            // Trigger Enable
+#define TIMER_ADCEV_RTCADCEN    0x00000008  // GPTM RTC Match Event ADC Trigger
+                                            // Enable
+#define TIMER_ADCEV_CAEADCEN    0x00000004  // GPTM A Capture Event ADC Trigger
+                                            // Enable
+#define TIMER_ADCEV_CAMADCEN    0x00000002  // GPTM A Capture Match Event ADC
+                                            // Trigger Enable
+#define TIMER_ADCEV_TATOADCEN   0x00000001  // GPTM A Time-Out Event ADC
+                                            // Trigger Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_PP register.
+//
+//*****************************************************************************
+#define TIMER_PP_ALTCLK         0x00000040  // Alternate Clock Source
+#define TIMER_PP_SYNCCNT        0x00000020  // Synchronize Start
+#define TIMER_PP_CHAIN          0x00000010  // Chain with Other Timers
+#define TIMER_PP_SIZE_M         0x0000000F  // Count Size
+#define TIMER_PP_SIZE_16        0x00000000  // Timer A and Timer B counters are
+                                            // 16 bits each with an 8-bit
+                                            // prescale counter
+#define TIMER_PP_SIZE_32        0x00000001  // Timer A and Timer B counters are
+                                            // 32 bits each with a 16-bit
+                                            // prescale counter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CC register.
+//
+//*****************************************************************************
+#define TIMER_CC_ALTCLK         0x00000001  // Alternate Clock Source
+
+#endif // __HW_TIMER_H__
diff --git a/os/common/ext/TivaWare/inc/hw_types.h b/os/common/ext/TivaWare/inc/hw_types.h
new file mode 100644
index 0000000..6312a28
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_types.h
@@ -0,0 +1,147 @@
+//*****************************************************************************
+//
+// hw_types.h - Common types and macros.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_TYPES_H__
+#define __HW_TYPES_H__
+
+//*****************************************************************************
+//
+// Macros for hardware access, both direct and via the bit-band region.
+//
+//*****************************************************************************
+#define HWREG(x)                                                              \
+        (*((volatile uint32_t *)(x)))
+#define HWREGH(x)                                                             \
+        (*((volatile uint16_t *)(x)))
+#define HWREGB(x)                                                             \
+        (*((volatile uint8_t *)(x)))
+#define HWREGBITW(x, b)                                                       \
+        HWREG(((uint32_t)(x) & 0xF0000000) | 0x02000000 |                     \
+              (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+#define HWREGBITH(x, b)                                                       \
+        HWREGH(((uint32_t)(x) & 0xF0000000) | 0x02000000 |                    \
+               (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+#define HWREGBITB(x, b)                                                       \
+        HWREGB(((uint32_t)(x) & 0xF0000000) | 0x02000000 |                    \
+               (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+
+//*****************************************************************************
+//
+// Helper Macros for determining silicon revisions, etc.
+//
+// These macros will be used by Driverlib at "run-time" to create necessary
+// conditional code blocks that will allow a single version of the Driverlib
+// "binary" code to support multiple(all) Tiva silicon revisions.
+//
+// It is expected that these macros will be used inside of a standard 'C'
+// conditional block of code, e.g.
+//
+//     if(CLASS_IS_TM4C123)
+//     {
+//         do some TM4C123-class specific code here.
+//     }
+//
+// By default, these macros will be defined as run-time checks of the
+// appropriate register(s) to allow creation of run-time conditional code
+// blocks for a common DriverLib across the entire Tiva family.
+//
+// However, if code-space optimization is required, these macros can be "hard-
+// coded" for a specific version of Tiva silicon.  Many compilers will then
+// detect the "hard-coded" conditionals, and appropriately optimize the code
+// blocks, eliminating any "unreachable" code.  This would result in a smaller
+// Driverlib, thus producing a smaller final application size, but at the cost
+// of limiting the Driverlib binary to a specific Tiva silicon revision.
+//
+//*****************************************************************************
+#ifndef CLASS_IS_TM4C123
+#define CLASS_IS_TM4C123                                                     \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
+         (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TM4C123))
+#endif
+
+#ifndef CLASS_IS_TM4C129
+#define CLASS_IS_TM4C129                                                     \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
+         (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TM4C129))
+#endif
+
+#ifndef REVISION_IS_A0
+#define REVISION_IS_A0                                                     \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+         (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
+#endif
+
+#ifndef REVISION_IS_A1
+#define REVISION_IS_A1                                                     \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+         (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
+#endif
+
+#ifndef REVISION_IS_A2
+#define REVISION_IS_A2                                                     \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+         (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2))
+#endif
+
+#ifndef REVISION_IS_B0
+#define REVISION_IS_B0                                                     \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+         (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_0))
+#endif
+
+#ifndef REVISION_IS_B1
+#define REVISION_IS_B1                                                     \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+         (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_1))
+#endif
+
+//*****************************************************************************
+//
+// For TivaWare 2.1, we removed all references to Tiva IC codenames from the
+// source.  To ensure that existing customer code doesn't break as a result
+// of this change, make sure that the old definitions are still available at
+// least for the time being.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define CLASS_IS_BLIZZARD CLASS_IS_TM4C123
+#define CLASS_IS_SNOWFLAKE CLASS_IS_TM4C123
+#endif
+
+#endif // __HW_TYPES_H__
diff --git a/os/common/ext/TivaWare/inc/hw_uart.h b/os/common/ext/TivaWare/inc/hw_uart.h
new file mode 100644
index 0000000..cca4b93
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_uart.h
@@ -0,0 +1,367 @@
+//*****************************************************************************
+//
+// hw_uart.h - Macros and defines used when accessing the UART hardware.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_UART_H__
+#define __HW_UART_H__
+
+//*****************************************************************************
+//
+// The following are defines for the UART register offsets.
+//
+//*****************************************************************************
+#define UART_O_DR               0x00000000  // UART Data
+#define UART_O_RSR              0x00000004  // UART Receive Status/Error Clear
+#define UART_O_ECR              0x00000004  // UART Receive Status/Error Clear
+#define UART_O_FR               0x00000018  // UART Flag
+#define UART_O_ILPR             0x00000020  // UART IrDA Low-Power Register
+#define UART_O_IBRD             0x00000024  // UART Integer Baud-Rate Divisor
+#define UART_O_FBRD             0x00000028  // UART Fractional Baud-Rate
+                                            // Divisor
+#define UART_O_LCRH             0x0000002C  // UART Line Control
+#define UART_O_CTL              0x00000030  // UART Control
+#define UART_O_IFLS             0x00000034  // UART Interrupt FIFO Level Select
+#define UART_O_IM               0x00000038  // UART Interrupt Mask
+#define UART_O_RIS              0x0000003C  // UART Raw Interrupt Status
+#define UART_O_MIS              0x00000040  // UART Masked Interrupt Status
+#define UART_O_ICR              0x00000044  // UART Interrupt Clear
+#define UART_O_DMACTL           0x00000048  // UART DMA Control
+#define UART_O_9BITADDR         0x000000A4  // UART 9-Bit Self Address
+#define UART_O_9BITAMASK        0x000000A8  // UART 9-Bit Self Address Mask
+#define UART_O_PP               0x00000FC0  // UART Peripheral Properties
+#define UART_O_CC               0x00000FC8  // UART Clock Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DR register.
+//
+//*****************************************************************************
+#define UART_DR_OE              0x00000800  // UART Overrun Error
+#define UART_DR_BE              0x00000400  // UART Break Error
+#define UART_DR_PE              0x00000200  // UART Parity Error
+#define UART_DR_FE              0x00000100  // UART Framing Error
+#define UART_DR_DATA_M          0x000000FF  // Data Transmitted or Received
+#define UART_DR_DATA_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RSR register.
+//
+//*****************************************************************************
+#define UART_RSR_OE             0x00000008  // UART Overrun Error
+#define UART_RSR_BE             0x00000004  // UART Break Error
+#define UART_RSR_PE             0x00000002  // UART Parity Error
+#define UART_RSR_FE             0x00000001  // UART Framing Error
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ECR register.
+//
+//*****************************************************************************
+#define UART_ECR_DATA_M         0x000000FF  // Error Clear
+#define UART_ECR_DATA_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FR register.
+//
+//*****************************************************************************
+#define UART_FR_RI              0x00000100  // Ring Indicator
+#define UART_FR_TXFE            0x00000080  // UART Transmit FIFO Empty
+#define UART_FR_RXFF            0x00000040  // UART Receive FIFO Full
+#define UART_FR_TXFF            0x00000020  // UART Transmit FIFO Full
+#define UART_FR_RXFE            0x00000010  // UART Receive FIFO Empty
+#define UART_FR_BUSY            0x00000008  // UART Busy
+#define UART_FR_DCD             0x00000004  // Data Carrier Detect
+#define UART_FR_DSR             0x00000002  // Data Set Ready
+#define UART_FR_CTS             0x00000001  // Clear To Send
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ILPR register.
+//
+//*****************************************************************************
+#define UART_ILPR_ILPDVSR_M     0x000000FF  // IrDA Low-Power Divisor
+#define UART_ILPR_ILPDVSR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IBRD register.
+//
+//*****************************************************************************
+#define UART_IBRD_DIVINT_M      0x0000FFFF  // Integer Baud-Rate Divisor
+#define UART_IBRD_DIVINT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FBRD register.
+//
+//*****************************************************************************
+#define UART_FBRD_DIVFRAC_M     0x0000003F  // Fractional Baud-Rate Divisor
+#define UART_FBRD_DIVFRAC_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LCRH register.
+//
+//*****************************************************************************
+#define UART_LCRH_SPS           0x00000080  // UART Stick Parity Select
+#define UART_LCRH_WLEN_M        0x00000060  // UART Word Length
+#define UART_LCRH_WLEN_5        0x00000000  // 5 bits (default)
+#define UART_LCRH_WLEN_6        0x00000020  // 6 bits
+#define UART_LCRH_WLEN_7        0x00000040  // 7 bits
+#define UART_LCRH_WLEN_8        0x00000060  // 8 bits
+#define UART_LCRH_FEN           0x00000010  // UART Enable FIFOs
+#define UART_LCRH_STP2          0x00000008  // UART Two Stop Bits Select
+#define UART_LCRH_EPS           0x00000004  // UART Even Parity Select
+#define UART_LCRH_PEN           0x00000002  // UART Parity Enable
+#define UART_LCRH_BRK           0x00000001  // UART Send Break
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CTL register.
+//
+//*****************************************************************************
+#define UART_CTL_CTSEN          0x00008000  // Enable Clear To Send
+#define UART_CTL_RTSEN          0x00004000  // Enable Request to Send
+#define UART_CTL_RTS            0x00000800  // Request to Send
+#define UART_CTL_DTR            0x00000400  // Data Terminal Ready
+#define UART_CTL_RXE            0x00000200  // UART Receive Enable
+#define UART_CTL_TXE            0x00000100  // UART Transmit Enable
+#define UART_CTL_LBE            0x00000080  // UART Loop Back Enable
+#define UART_CTL_HSE            0x00000020  // High-Speed Enable
+#define UART_CTL_EOT            0x00000010  // End of Transmission
+#define UART_CTL_SMART          0x00000008  // ISO 7816 Smart Card Support
+#define UART_CTL_SIRLP          0x00000004  // UART SIR Low-Power Mode
+#define UART_CTL_SIREN          0x00000002  // UART SIR Enable
+#define UART_CTL_UARTEN         0x00000001  // UART Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IFLS register.
+//
+//*****************************************************************************
+#define UART_IFLS_RX_M          0x00000038  // UART Receive Interrupt FIFO
+                                            // Level Select
+#define UART_IFLS_RX1_8         0x00000000  // RX FIFO >= 1/8 full
+#define UART_IFLS_RX2_8         0x00000008  // RX FIFO >= 1/4 full
+#define UART_IFLS_RX4_8         0x00000010  // RX FIFO >= 1/2 full (default)
+#define UART_IFLS_RX6_8         0x00000018  // RX FIFO >= 3/4 full
+#define UART_IFLS_RX7_8         0x00000020  // RX FIFO >= 7/8 full
+#define UART_IFLS_TX_M          0x00000007  // UART Transmit Interrupt FIFO
+                                            // Level Select
+#define UART_IFLS_TX1_8         0x00000000  // TX FIFO <= 1/8 full
+#define UART_IFLS_TX2_8         0x00000001  // TX FIFO <= 1/4 full
+#define UART_IFLS_TX4_8         0x00000002  // TX FIFO <= 1/2 full (default)
+#define UART_IFLS_TX6_8         0x00000003  // TX FIFO <= 3/4 full
+#define UART_IFLS_TX7_8         0x00000004  // TX FIFO <= 7/8 full
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IM register.
+//
+//*****************************************************************************
+#define UART_IM_DMATXIM         0x00020000  // Transmit DMA Interrupt Mask
+#define UART_IM_DMARXIM         0x00010000  // Receive DMA Interrupt Mask
+#define UART_IM_9BITIM          0x00001000  // 9-Bit Mode Interrupt Mask
+#define UART_IM_EOTIM           0x00000800  // End of Transmission Interrupt
+                                            // Mask
+#define UART_IM_OEIM            0x00000400  // UART Overrun Error Interrupt
+                                            // Mask
+#define UART_IM_BEIM            0x00000200  // UART Break Error Interrupt Mask
+#define UART_IM_PEIM            0x00000100  // UART Parity Error Interrupt Mask
+#define UART_IM_FEIM            0x00000080  // UART Framing Error Interrupt
+                                            // Mask
+#define UART_IM_RTIM            0x00000040  // UART Receive Time-Out Interrupt
+                                            // Mask
+#define UART_IM_TXIM            0x00000020  // UART Transmit Interrupt Mask
+#define UART_IM_RXIM            0x00000010  // UART Receive Interrupt Mask
+#define UART_IM_DSRMIM          0x00000008  // UART Data Set Ready Modem
+                                            // Interrupt Mask
+#define UART_IM_DCDMIM          0x00000004  // UART Data Carrier Detect Modem
+                                            // Interrupt Mask
+#define UART_IM_CTSMIM          0x00000002  // UART Clear to Send Modem
+                                            // Interrupt Mask
+#define UART_IM_RIMIM           0x00000001  // UART Ring Indicator Modem
+                                            // Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RIS register.
+//
+//*****************************************************************************
+#define UART_RIS_DMATXRIS       0x00020000  // Transmit DMA Raw Interrupt
+                                            // Status
+#define UART_RIS_DMARXRIS       0x00010000  // Receive DMA Raw Interrupt Status
+#define UART_RIS_9BITRIS        0x00001000  // 9-Bit Mode Raw Interrupt Status
+#define UART_RIS_EOTRIS         0x00000800  // End of Transmission Raw
+                                            // Interrupt Status
+#define UART_RIS_OERIS          0x00000400  // UART Overrun Error Raw Interrupt
+                                            // Status
+#define UART_RIS_BERIS          0x00000200  // UART Break Error Raw Interrupt
+                                            // Status
+#define UART_RIS_PERIS          0x00000100  // UART Parity Error Raw Interrupt
+                                            // Status
+#define UART_RIS_FERIS          0x00000080  // UART Framing Error Raw Interrupt
+                                            // Status
+#define UART_RIS_RTRIS          0x00000040  // UART Receive Time-Out Raw
+                                            // Interrupt Status
+#define UART_RIS_TXRIS          0x00000020  // UART Transmit Raw Interrupt
+                                            // Status
+#define UART_RIS_RXRIS          0x00000010  // UART Receive Raw Interrupt
+                                            // Status
+#define UART_RIS_DSRRIS         0x00000008  // UART Data Set Ready Modem Raw
+                                            // Interrupt Status
+#define UART_RIS_DCDRIS         0x00000004  // UART Data Carrier Detect Modem
+                                            // Raw Interrupt Status
+#define UART_RIS_CTSRIS         0x00000002  // UART Clear to Send Modem Raw
+                                            // Interrupt Status
+#define UART_RIS_RIRIS          0x00000001  // UART Ring Indicator Modem Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_MIS register.
+//
+//*****************************************************************************
+#define UART_MIS_DMATXMIS       0x00020000  // Transmit DMA Masked Interrupt
+                                            // Status
+#define UART_MIS_DMARXMIS       0x00010000  // Receive DMA Masked Interrupt
+                                            // Status
+#define UART_MIS_9BITMIS        0x00001000  // 9-Bit Mode Masked Interrupt
+                                            // Status
+#define UART_MIS_EOTMIS         0x00000800  // End of Transmission Masked
+                                            // Interrupt Status
+#define UART_MIS_OEMIS          0x00000400  // UART Overrun Error Masked
+                                            // Interrupt Status
+#define UART_MIS_BEMIS          0x00000200  // UART Break Error Masked
+                                            // Interrupt Status
+#define UART_MIS_PEMIS          0x00000100  // UART Parity Error Masked
+                                            // Interrupt Status
+#define UART_MIS_FEMIS          0x00000080  // UART Framing Error Masked
+                                            // Interrupt Status
+#define UART_MIS_RTMIS          0x00000040  // UART Receive Time-Out Masked
+                                            // Interrupt Status
+#define UART_MIS_TXMIS          0x00000020  // UART Transmit Masked Interrupt
+                                            // Status
+#define UART_MIS_RXMIS          0x00000010  // UART Receive Masked Interrupt
+                                            // Status
+#define UART_MIS_DSRMIS         0x00000008  // UART Data Set Ready Modem Masked
+                                            // Interrupt Status
+#define UART_MIS_DCDMIS         0x00000004  // UART Data Carrier Detect Modem
+                                            // Masked Interrupt Status
+#define UART_MIS_CTSMIS         0x00000002  // UART Clear to Send Modem Masked
+                                            // Interrupt Status
+#define UART_MIS_RIMIS          0x00000001  // UART Ring Indicator Modem Masked
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ICR register.
+//
+//*****************************************************************************
+#define UART_ICR_DMATXIC        0x00020000  // Transmit DMA Interrupt Clear
+#define UART_ICR_DMARXIC        0x00010000  // Receive DMA Interrupt Clear
+#define UART_ICR_9BITIC         0x00001000  // 9-Bit Mode Interrupt Clear
+#define UART_ICR_EOTIC          0x00000800  // End of Transmission Interrupt
+                                            // Clear
+#define UART_ICR_OEIC           0x00000400  // Overrun Error Interrupt Clear
+#define UART_ICR_BEIC           0x00000200  // Break Error Interrupt Clear
+#define UART_ICR_PEIC           0x00000100  // Parity Error Interrupt Clear
+#define UART_ICR_FEIC           0x00000080  // Framing Error Interrupt Clear
+#define UART_ICR_RTIC           0x00000040  // Receive Time-Out Interrupt Clear
+#define UART_ICR_TXIC           0x00000020  // Transmit Interrupt Clear
+#define UART_ICR_RXIC           0x00000010  // Receive Interrupt Clear
+#define UART_ICR_DSRMIC         0x00000008  // UART Data Set Ready Modem
+                                            // Interrupt Clear
+#define UART_ICR_DCDMIC         0x00000004  // UART Data Carrier Detect Modem
+                                            // Interrupt Clear
+#define UART_ICR_CTSMIC         0x00000002  // UART Clear to Send Modem
+                                            // Interrupt Clear
+#define UART_ICR_RIMIC          0x00000001  // UART Ring Indicator Modem
+                                            // Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DMACTL register.
+//
+//*****************************************************************************
+#define UART_DMACTL_DMAERR      0x00000004  // DMA on Error
+#define UART_DMACTL_TXDMAE      0x00000002  // Transmit DMA Enable
+#define UART_DMACTL_RXDMAE      0x00000001  // Receive DMA Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_9BITADDR
+// register.
+//
+//*****************************************************************************
+#define UART_9BITADDR_9BITEN    0x00008000  // Enable 9-Bit Mode
+#define UART_9BITADDR_ADDR_M    0x000000FF  // Self Address for 9-Bit Mode
+#define UART_9BITADDR_ADDR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_9BITAMASK
+// register.
+//
+//*****************************************************************************
+#define UART_9BITAMASK_MASK_M   0x000000FF  // Self Address Mask for 9-Bit Mode
+#define UART_9BITAMASK_MASK_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_PP register.
+//
+//*****************************************************************************
+#define UART_PP_MSE             0x00000008  // Modem Support Extended
+#define UART_PP_MS              0x00000004  // Modem Support
+#define UART_PP_NB              0x00000002  // 9-Bit Support
+#define UART_PP_SC              0x00000001  // Smart Card Support
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CC register.
+//
+//*****************************************************************************
+#define UART_CC_CS_M            0x0000000F  // UART Baud Clock Source
+#define UART_CC_CS_SYSCLK       0x00000000  // System clock (based on clock
+                                            // source and divisor factor)
+#define UART_CC_CS_PIOSC        0x00000005  // PIOSC
+
+#endif // __HW_UART_H__
diff --git a/os/common/ext/TivaWare/inc/hw_udma.h b/os/common/ext/TivaWare/inc/hw_udma.h
new file mode 100644
index 0000000..85bc014
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_udma.h
@@ -0,0 +1,414 @@
+//*****************************************************************************
+//
+// hw_udma.h - Macros for use in accessing the UDMA registers.
+//
+// Copyright (c) 2007-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_UDMA_H__
+#define __HW_UDMA_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Micro Direct Memory Access register
+// addresses.
+//
+//*****************************************************************************
+#define UDMA_STAT               0x400FF000  // DMA Status
+#define UDMA_CFG                0x400FF004  // DMA Configuration
+#define UDMA_CTLBASE            0x400FF008  // DMA Channel Control Base Pointer
+#define UDMA_ALTBASE            0x400FF00C  // DMA Alternate Channel Control
+                                            // Base Pointer
+#define UDMA_WAITSTAT           0x400FF010  // DMA Channel Wait-on-Request
+                                            // Status
+#define UDMA_SWREQ              0x400FF014  // DMA Channel Software Request
+#define UDMA_USEBURSTSET        0x400FF018  // DMA Channel Useburst Set
+#define UDMA_USEBURSTCLR        0x400FF01C  // DMA Channel Useburst Clear
+#define UDMA_REQMASKSET         0x400FF020  // DMA Channel Request Mask Set
+#define UDMA_REQMASKCLR         0x400FF024  // DMA Channel Request Mask Clear
+#define UDMA_ENASET             0x400FF028  // DMA Channel Enable Set
+#define UDMA_ENACLR             0x400FF02C  // DMA Channel Enable Clear
+#define UDMA_ALTSET             0x400FF030  // DMA Channel Primary Alternate
+                                            // Set
+#define UDMA_ALTCLR             0x400FF034  // DMA Channel Primary Alternate
+                                            // Clear
+#define UDMA_PRIOSET            0x400FF038  // DMA Channel Priority Set
+#define UDMA_PRIOCLR            0x400FF03C  // DMA Channel Priority Clear
+#define UDMA_ERRCLR             0x400FF04C  // DMA Bus Error Clear
+#define UDMA_CHASGN             0x400FF500  // DMA Channel Assignment
+#define UDMA_CHIS               0x400FF504  // DMA Channel Interrupt Status
+#define UDMA_CHMAP0             0x400FF510  // DMA Channel Map Select 0
+#define UDMA_CHMAP1             0x400FF514  // DMA Channel Map Select 1
+#define UDMA_CHMAP2             0x400FF518  // DMA Channel Map Select 2
+#define UDMA_CHMAP3             0x400FF51C  // DMA Channel Map Select 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_STAT register.
+//
+//*****************************************************************************
+#define UDMA_STAT_DMACHANS_M    0x001F0000  // Available uDMA Channels Minus 1
+#define UDMA_STAT_STATE_M       0x000000F0  // Control State Machine Status
+#define UDMA_STAT_STATE_IDLE    0x00000000  // Idle
+#define UDMA_STAT_STATE_RD_CTRL 0x00000010  // Reading channel controller data
+#define UDMA_STAT_STATE_RD_SRCENDP                                            \
+                                0x00000020  // Reading source end pointer
+#define UDMA_STAT_STATE_RD_DSTENDP                                            \
+                                0x00000030  // Reading destination end pointer
+#define UDMA_STAT_STATE_RD_SRCDAT                                             \
+                                0x00000040  // Reading source data
+#define UDMA_STAT_STATE_WR_DSTDAT                                             \
+                                0x00000050  // Writing destination data
+#define UDMA_STAT_STATE_WAIT    0x00000060  // Waiting for uDMA request to
+                                            // clear
+#define UDMA_STAT_STATE_WR_CTRL 0x00000070  // Writing channel controller data
+#define UDMA_STAT_STATE_STALL   0x00000080  // Stalled
+#define UDMA_STAT_STATE_DONE    0x00000090  // Done
+#define UDMA_STAT_STATE_UNDEF   0x000000A0  // Undefined
+#define UDMA_STAT_MASTEN        0x00000001  // Master Enable Status
+#define UDMA_STAT_DMACHANS_S    16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CFG register.
+//
+//*****************************************************************************
+#define UDMA_CFG_MASTEN         0x00000001  // Controller Master Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CTLBASE register.
+//
+//*****************************************************************************
+#define UDMA_CTLBASE_ADDR_M     0xFFFFFC00  // Channel Control Base Address
+#define UDMA_CTLBASE_ADDR_S     10
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTBASE register.
+//
+//*****************************************************************************
+#define UDMA_ALTBASE_ADDR_M     0xFFFFFFFF  // Alternate Channel Address
+                                            // Pointer
+#define UDMA_ALTBASE_ADDR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_WAITSTAT register.
+//
+//*****************************************************************************
+#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF  // Channel [n] Wait Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_SWREQ register.
+//
+//*****************************************************************************
+#define UDMA_SWREQ_M            0xFFFFFFFF  // Channel [n] Software Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTSET_SET_M  0xFFFFFFFF  // Channel [n] Useburst Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTCLR_CLR_M  0xFFFFFFFF  // Channel [n] Useburst Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKSET_SET_M   0xFFFFFFFF  // Channel [n] Request Mask Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKCLR_CLR_M   0xFFFFFFFF  // Channel [n] Request Mask Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENASET register.
+//
+//*****************************************************************************
+#define UDMA_ENASET_SET_M       0xFFFFFFFF  // Channel [n] Enable Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENACLR register.
+//
+//*****************************************************************************
+#define UDMA_ENACLR_CLR_M       0xFFFFFFFF  // Clear Channel [n] Enable Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTSET register.
+//
+//*****************************************************************************
+#define UDMA_ALTSET_SET_M       0xFFFFFFFF  // Channel [n] Alternate Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTCLR register.
+//
+//*****************************************************************************
+#define UDMA_ALTCLR_CLR_M       0xFFFFFFFF  // Channel [n] Alternate Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOSET register.
+//
+//*****************************************************************************
+#define UDMA_PRIOSET_SET_M      0xFFFFFFFF  // Channel [n] Priority Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOCLR register.
+//
+//*****************************************************************************
+#define UDMA_PRIOCLR_CLR_M      0xFFFFFFFF  // Channel [n] Priority Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ERRCLR register.
+//
+//*****************************************************************************
+#define UDMA_ERRCLR_ERRCLR      0x00000001  // uDMA Bus Error Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHASGN register.
+//
+//*****************************************************************************
+#define UDMA_CHASGN_M           0xFFFFFFFF  // Channel [n] Assignment Select
+#define UDMA_CHASGN_PRIMARY     0x00000000  // Use the primary channel
+                                            // assignment
+#define UDMA_CHASGN_SECONDARY   0x00000001  // Use the secondary channel
+                                            // assignment
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHIS register.
+//
+//*****************************************************************************
+#define UDMA_CHIS_M             0xFFFFFFFF  // Channel [n] Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP0 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP0_CH7SEL_M    0xF0000000  // uDMA Channel 7 Source Select
+#define UDMA_CHMAP0_CH6SEL_M    0x0F000000  // uDMA Channel 6 Source Select
+#define UDMA_CHMAP0_CH5SEL_M    0x00F00000  // uDMA Channel 5 Source Select
+#define UDMA_CHMAP0_CH4SEL_M    0x000F0000  // uDMA Channel 4 Source Select
+#define UDMA_CHMAP0_CH3SEL_M    0x0000F000  // uDMA Channel 3 Source Select
+#define UDMA_CHMAP0_CH2SEL_M    0x00000F00  // uDMA Channel 2 Source Select
+#define UDMA_CHMAP0_CH1SEL_M    0x000000F0  // uDMA Channel 1 Source Select
+#define UDMA_CHMAP0_CH0SEL_M    0x0000000F  // uDMA Channel 0 Source Select
+#define UDMA_CHMAP0_CH7SEL_S    28
+#define UDMA_CHMAP0_CH6SEL_S    24
+#define UDMA_CHMAP0_CH5SEL_S    20
+#define UDMA_CHMAP0_CH4SEL_S    16
+#define UDMA_CHMAP0_CH3SEL_S    12
+#define UDMA_CHMAP0_CH2SEL_S    8
+#define UDMA_CHMAP0_CH1SEL_S    4
+#define UDMA_CHMAP0_CH0SEL_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP1 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP1_CH15SEL_M   0xF0000000  // uDMA Channel 15 Source Select
+#define UDMA_CHMAP1_CH14SEL_M   0x0F000000  // uDMA Channel 14 Source Select
+#define UDMA_CHMAP1_CH13SEL_M   0x00F00000  // uDMA Channel 13 Source Select
+#define UDMA_CHMAP1_CH12SEL_M   0x000F0000  // uDMA Channel 12 Source Select
+#define UDMA_CHMAP1_CH11SEL_M   0x0000F000  // uDMA Channel 11 Source Select
+#define UDMA_CHMAP1_CH10SEL_M   0x00000F00  // uDMA Channel 10 Source Select
+#define UDMA_CHMAP1_CH9SEL_M    0x000000F0  // uDMA Channel 9 Source Select
+#define UDMA_CHMAP1_CH8SEL_M    0x0000000F  // uDMA Channel 8 Source Select
+#define UDMA_CHMAP1_CH15SEL_S   28
+#define UDMA_CHMAP1_CH14SEL_S   24
+#define UDMA_CHMAP1_CH13SEL_S   20
+#define UDMA_CHMAP1_CH12SEL_S   16
+#define UDMA_CHMAP1_CH11SEL_S   12
+#define UDMA_CHMAP1_CH10SEL_S   8
+#define UDMA_CHMAP1_CH9SEL_S    4
+#define UDMA_CHMAP1_CH8SEL_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP2 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP2_CH23SEL_M   0xF0000000  // uDMA Channel 23 Source Select
+#define UDMA_CHMAP2_CH22SEL_M   0x0F000000  // uDMA Channel 22 Source Select
+#define UDMA_CHMAP2_CH21SEL_M   0x00F00000  // uDMA Channel 21 Source Select
+#define UDMA_CHMAP2_CH20SEL_M   0x000F0000  // uDMA Channel 20 Source Select
+#define UDMA_CHMAP2_CH19SEL_M   0x0000F000  // uDMA Channel 19 Source Select
+#define UDMA_CHMAP2_CH18SEL_M   0x00000F00  // uDMA Channel 18 Source Select
+#define UDMA_CHMAP2_CH17SEL_M   0x000000F0  // uDMA Channel 17 Source Select
+#define UDMA_CHMAP2_CH16SEL_M   0x0000000F  // uDMA Channel 16 Source Select
+#define UDMA_CHMAP2_CH23SEL_S   28
+#define UDMA_CHMAP2_CH22SEL_S   24
+#define UDMA_CHMAP2_CH21SEL_S   20
+#define UDMA_CHMAP2_CH20SEL_S   16
+#define UDMA_CHMAP2_CH19SEL_S   12
+#define UDMA_CHMAP2_CH18SEL_S   8
+#define UDMA_CHMAP2_CH17SEL_S   4
+#define UDMA_CHMAP2_CH16SEL_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP3 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP3_CH31SEL_M   0xF0000000  // uDMA Channel 31 Source Select
+#define UDMA_CHMAP3_CH30SEL_M   0x0F000000  // uDMA Channel 30 Source Select
+#define UDMA_CHMAP3_CH29SEL_M   0x00F00000  // uDMA Channel 29 Source Select
+#define UDMA_CHMAP3_CH28SEL_M   0x000F0000  // uDMA Channel 28 Source Select
+#define UDMA_CHMAP3_CH27SEL_M   0x0000F000  // uDMA Channel 27 Source Select
+#define UDMA_CHMAP3_CH26SEL_M   0x00000F00  // uDMA Channel 26 Source Select
+#define UDMA_CHMAP3_CH25SEL_M   0x000000F0  // uDMA Channel 25 Source Select
+#define UDMA_CHMAP3_CH24SEL_M   0x0000000F  // uDMA Channel 24 Source Select
+#define UDMA_CHMAP3_CH31SEL_S   28
+#define UDMA_CHMAP3_CH30SEL_S   24
+#define UDMA_CHMAP3_CH29SEL_S   20
+#define UDMA_CHMAP3_CH28SEL_S   16
+#define UDMA_CHMAP3_CH27SEL_S   12
+#define UDMA_CHMAP3_CH26SEL_S   8
+#define UDMA_CHMAP3_CH25SEL_S   4
+#define UDMA_CHMAP3_CH24SEL_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the Micro Direct Memory Access (uDMA) offsets.
+//
+//*****************************************************************************
+#define UDMA_O_SRCENDP          0x00000000  // DMA Channel Source Address End
+                                            // Pointer
+#define UDMA_O_DSTENDP          0x00000004  // DMA Channel Destination Address
+                                            // End Pointer
+#define UDMA_O_CHCTL            0x00000008  // DMA Channel Control Word
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_SRCENDP register.
+//
+//*****************************************************************************
+#define UDMA_SRCENDP_ADDR_M     0xFFFFFFFF  // Source Address End Pointer
+#define UDMA_SRCENDP_ADDR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_DSTENDP register.
+//
+//*****************************************************************************
+#define UDMA_DSTENDP_ADDR_M     0xFFFFFFFF  // Destination Address End Pointer
+#define UDMA_DSTENDP_ADDR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_CHCTL register.
+//
+//*****************************************************************************
+#define UDMA_CHCTL_DSTINC_M     0xC0000000  // Destination Address Increment
+#define UDMA_CHCTL_DSTINC_8     0x00000000  // Byte
+#define UDMA_CHCTL_DSTINC_16    0x40000000  // Half-word
+#define UDMA_CHCTL_DSTINC_32    0x80000000  // Word
+#define UDMA_CHCTL_DSTINC_NONE  0xC0000000  // No increment
+#define UDMA_CHCTL_DSTSIZE_M    0x30000000  // Destination Data Size
+#define UDMA_CHCTL_DSTSIZE_8    0x00000000  // Byte
+#define UDMA_CHCTL_DSTSIZE_16   0x10000000  // Half-word
+#define UDMA_CHCTL_DSTSIZE_32   0x20000000  // Word
+#define UDMA_CHCTL_SRCINC_M     0x0C000000  // Source Address Increment
+#define UDMA_CHCTL_SRCINC_8     0x00000000  // Byte
+#define UDMA_CHCTL_SRCINC_16    0x04000000  // Half-word
+#define UDMA_CHCTL_SRCINC_32    0x08000000  // Word
+#define UDMA_CHCTL_SRCINC_NONE  0x0C000000  // No increment
+#define UDMA_CHCTL_SRCSIZE_M    0x03000000  // Source Data Size
+#define UDMA_CHCTL_SRCSIZE_8    0x00000000  // Byte
+#define UDMA_CHCTL_SRCSIZE_16   0x01000000  // Half-word
+#define UDMA_CHCTL_SRCSIZE_32   0x02000000  // Word
+#define UDMA_CHCTL_DSTPROT0     0x00200000  // Destination Privilege Access
+#define UDMA_CHCTL_SRCPROT0     0x00040000  // Source Privilege Access
+#define UDMA_CHCTL_ARBSIZE_M    0x0003C000  // Arbitration Size
+#define UDMA_CHCTL_ARBSIZE_1    0x00000000  // 1 Transfer
+#define UDMA_CHCTL_ARBSIZE_2    0x00004000  // 2 Transfers
+#define UDMA_CHCTL_ARBSIZE_4    0x00008000  // 4 Transfers
+#define UDMA_CHCTL_ARBSIZE_8    0x0000C000  // 8 Transfers
+#define UDMA_CHCTL_ARBSIZE_16   0x00010000  // 16 Transfers
+#define UDMA_CHCTL_ARBSIZE_32   0x00014000  // 32 Transfers
+#define UDMA_CHCTL_ARBSIZE_64   0x00018000  // 64 Transfers
+#define UDMA_CHCTL_ARBSIZE_128  0x0001C000  // 128 Transfers
+#define UDMA_CHCTL_ARBSIZE_256  0x00020000  // 256 Transfers
+#define UDMA_CHCTL_ARBSIZE_512  0x00024000  // 512 Transfers
+#define UDMA_CHCTL_ARBSIZE_1024 0x00028000  // 1024 Transfers
+#define UDMA_CHCTL_XFERSIZE_M   0x00003FF0  // Transfer Size (minus 1)
+#define UDMA_CHCTL_NXTUSEBURST  0x00000008  // Next Useburst
+#define UDMA_CHCTL_XFERMODE_M   0x00000007  // uDMA Transfer Mode
+#define UDMA_CHCTL_XFERMODE_STOP                                              \
+                                0x00000000  // Stop
+#define UDMA_CHCTL_XFERMODE_BASIC                                             \
+                                0x00000001  // Basic
+#define UDMA_CHCTL_XFERMODE_AUTO                                              \
+                                0x00000002  // Auto-Request
+#define UDMA_CHCTL_XFERMODE_PINGPONG                                          \
+                                0x00000003  // Ping-Pong
+#define UDMA_CHCTL_XFERMODE_MEM_SG                                            \
+                                0x00000004  // Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_MEM_SGA                                           \
+                                0x00000005  // Alternate Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SG                                            \
+                                0x00000006  // Peripheral Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SGA                                           \
+                                0x00000007  // Alternate Peripheral
+                                            // Scatter-Gather
+#define UDMA_CHCTL_XFERSIZE_S   4
+
+#endif // __HW_UDMA_H__
diff --git a/os/common/ext/TivaWare/inc/hw_usb.h b/os/common/ext/TivaWare/inc/hw_usb.h
new file mode 100644
index 0000000..5d4027a
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_usb.h
@@ -0,0 +1,3032 @@
+//*****************************************************************************
+//
+// hw_usb.h - Macros for use in accessing the USB registers.
+//
+// Copyright (c) 2007-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_USB_H__
+#define __HW_USB_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Univeral Serial Bus register offsets.
+//
+//*****************************************************************************
+#define USB_O_FADDR             0x00000000  // USB Device Functional Address
+#define USB_O_POWER             0x00000001  // USB Power
+#define USB_O_TXIS              0x00000002  // USB Transmit Interrupt Status
+#define USB_O_RXIS              0x00000004  // USB Receive Interrupt Status
+#define USB_O_TXIE              0x00000006  // USB Transmit Interrupt Enable
+#define USB_O_RXIE              0x00000008  // USB Receive Interrupt Enable
+#define USB_O_IS                0x0000000A  // USB General Interrupt Status
+#define USB_O_IE                0x0000000B  // USB Interrupt Enable
+#define USB_O_FRAME             0x0000000C  // USB Frame Value
+#define USB_O_EPIDX             0x0000000E  // USB Endpoint Index
+#define USB_O_TEST              0x0000000F  // USB Test Mode
+#define USB_O_FIFO0             0x00000020  // USB FIFO Endpoint 0
+#define USB_O_FIFO1             0x00000024  // USB FIFO Endpoint 1
+#define USB_O_FIFO2             0x00000028  // USB FIFO Endpoint 2
+#define USB_O_FIFO3             0x0000002C  // USB FIFO Endpoint 3
+#define USB_O_FIFO4             0x00000030  // USB FIFO Endpoint 4
+#define USB_O_FIFO5             0x00000034  // USB FIFO Endpoint 5
+#define USB_O_FIFO6             0x00000038  // USB FIFO Endpoint 6
+#define USB_O_FIFO7             0x0000003C  // USB FIFO Endpoint 7
+#define USB_O_DEVCTL            0x00000060  // USB Device Control
+#define USB_O_CCONF             0x00000061  // USB Common Configuration
+#define USB_O_TXFIFOSZ          0x00000062  // USB Transmit Dynamic FIFO Sizing
+#define USB_O_RXFIFOSZ          0x00000063  // USB Receive Dynamic FIFO Sizing
+#define USB_O_TXFIFOADD         0x00000064  // USB Transmit FIFO Start Address
+#define USB_O_RXFIFOADD         0x00000066  // USB Receive FIFO Start Address
+#define USB_O_ULPIVBUSCTL       0x00000070  // USB ULPI VBUS Control
+#define USB_O_ULPIREGDATA       0x00000074  // USB ULPI Register Data
+#define USB_O_ULPIREGADDR       0x00000075  // USB ULPI Register Address
+#define USB_O_ULPIREGCTL        0x00000076  // USB ULPI Register Control
+#define USB_O_EPINFO            0x00000078  // USB Endpoint Information
+#define USB_O_RAMINFO           0x00000079  // USB RAM Information
+#define USB_O_CONTIM            0x0000007A  // USB Connect Timing
+#define USB_O_VPLEN             0x0000007B  // USB OTG VBUS Pulse Timing
+#define USB_O_HSEOF             0x0000007C  // USB High-Speed Last Transaction
+                                            // to End of Frame Timing
+#define USB_O_FSEOF             0x0000007D  // USB Full-Speed Last Transaction
+                                            // to End of Frame Timing
+#define USB_O_LSEOF             0x0000007E  // USB Low-Speed Last Transaction
+                                            // to End of Frame Timing
+#define USB_O_TXFUNCADDR0       0x00000080  // USB Transmit Functional Address
+                                            // Endpoint 0
+#define USB_O_TXHUBADDR0        0x00000082  // USB Transmit Hub Address
+                                            // Endpoint 0
+#define USB_O_TXHUBPORT0        0x00000083  // USB Transmit Hub Port Endpoint 0
+#define USB_O_TXFUNCADDR1       0x00000088  // USB Transmit Functional Address
+                                            // Endpoint 1
+#define USB_O_TXHUBADDR1        0x0000008A  // USB Transmit Hub Address
+                                            // Endpoint 1
+#define USB_O_TXHUBPORT1        0x0000008B  // USB Transmit Hub Port Endpoint 1
+#define USB_O_RXFUNCADDR1       0x0000008C  // USB Receive Functional Address
+                                            // Endpoint 1
+#define USB_O_RXHUBADDR1        0x0000008E  // USB Receive Hub Address Endpoint
+                                            // 1
+#define USB_O_RXHUBPORT1        0x0000008F  // USB Receive Hub Port Endpoint 1
+#define USB_O_TXFUNCADDR2       0x00000090  // USB Transmit Functional Address
+                                            // Endpoint 2
+#define USB_O_TXHUBADDR2        0x00000092  // USB Transmit Hub Address
+                                            // Endpoint 2
+#define USB_O_TXHUBPORT2        0x00000093  // USB Transmit Hub Port Endpoint 2
+#define USB_O_RXFUNCADDR2       0x00000094  // USB Receive Functional Address
+                                            // Endpoint 2
+#define USB_O_RXHUBADDR2        0x00000096  // USB Receive Hub Address Endpoint
+                                            // 2
+#define USB_O_RXHUBPORT2        0x00000097  // USB Receive Hub Port Endpoint 2
+#define USB_O_TXFUNCADDR3       0x00000098  // USB Transmit Functional Address
+                                            // Endpoint 3
+#define USB_O_TXHUBADDR3        0x0000009A  // USB Transmit Hub Address
+                                            // Endpoint 3
+#define USB_O_TXHUBPORT3        0x0000009B  // USB Transmit Hub Port Endpoint 3
+#define USB_O_RXFUNCADDR3       0x0000009C  // USB Receive Functional Address
+                                            // Endpoint 3
+#define USB_O_RXHUBADDR3        0x0000009E  // USB Receive Hub Address Endpoint
+                                            // 3
+#define USB_O_RXHUBPORT3        0x0000009F  // USB Receive Hub Port Endpoint 3
+#define USB_O_TXFUNCADDR4       0x000000A0  // USB Transmit Functional Address
+                                            // Endpoint 4
+#define USB_O_TXHUBADDR4        0x000000A2  // USB Transmit Hub Address
+                                            // Endpoint 4
+#define USB_O_TXHUBPORT4        0x000000A3  // USB Transmit Hub Port Endpoint 4
+#define USB_O_RXFUNCADDR4       0x000000A4  // USB Receive Functional Address
+                                            // Endpoint 4
+#define USB_O_RXHUBADDR4        0x000000A6  // USB Receive Hub Address Endpoint
+                                            // 4
+#define USB_O_RXHUBPORT4        0x000000A7  // USB Receive Hub Port Endpoint 4
+#define USB_O_TXFUNCADDR5       0x000000A8  // USB Transmit Functional Address
+                                            // Endpoint 5
+#define USB_O_TXHUBADDR5        0x000000AA  // USB Transmit Hub Address
+                                            // Endpoint 5
+#define USB_O_TXHUBPORT5        0x000000AB  // USB Transmit Hub Port Endpoint 5
+#define USB_O_RXFUNCADDR5       0x000000AC  // USB Receive Functional Address
+                                            // Endpoint 5
+#define USB_O_RXHUBADDR5        0x000000AE  // USB Receive Hub Address Endpoint
+                                            // 5
+#define USB_O_RXHUBPORT5        0x000000AF  // USB Receive Hub Port Endpoint 5
+#define USB_O_TXFUNCADDR6       0x000000B0  // USB Transmit Functional Address
+                                            // Endpoint 6
+#define USB_O_TXHUBADDR6        0x000000B2  // USB Transmit Hub Address
+                                            // Endpoint 6
+#define USB_O_TXHUBPORT6        0x000000B3  // USB Transmit Hub Port Endpoint 6
+#define USB_O_RXFUNCADDR6       0x000000B4  // USB Receive Functional Address
+                                            // Endpoint 6
+#define USB_O_RXHUBADDR6        0x000000B6  // USB Receive Hub Address Endpoint
+                                            // 6
+#define USB_O_RXHUBPORT6        0x000000B7  // USB Receive Hub Port Endpoint 6
+#define USB_O_TXFUNCADDR7       0x000000B8  // USB Transmit Functional Address
+                                            // Endpoint 7
+#define USB_O_TXHUBADDR7        0x000000BA  // USB Transmit Hub Address
+                                            // Endpoint 7
+#define USB_O_TXHUBPORT7        0x000000BB  // USB Transmit Hub Port Endpoint 7
+#define USB_O_RXFUNCADDR7       0x000000BC  // USB Receive Functional Address
+                                            // Endpoint 7
+#define USB_O_RXHUBADDR7        0x000000BE  // USB Receive Hub Address Endpoint
+                                            // 7
+#define USB_O_RXHUBPORT7        0x000000BF  // USB Receive Hub Port Endpoint 7
+#define USB_O_CSRL0             0x00000102  // USB Control and Status Endpoint
+                                            // 0 Low
+#define USB_O_CSRH0             0x00000103  // USB Control and Status Endpoint
+                                            // 0 High
+#define USB_O_COUNT0            0x00000108  // USB Receive Byte Count Endpoint
+                                            // 0
+#define USB_O_TYPE0             0x0000010A  // USB Type Endpoint 0
+#define USB_O_NAKLMT            0x0000010B  // USB NAK Limit
+#define USB_O_TXMAXP1           0x00000110  // USB Maximum Transmit Data
+                                            // Endpoint 1
+#define USB_O_TXCSRL1           0x00000112  // USB Transmit Control and Status
+                                            // Endpoint 1 Low
+#define USB_O_TXCSRH1           0x00000113  // USB Transmit Control and Status
+                                            // Endpoint 1 High
+#define USB_O_RXMAXP1           0x00000114  // USB Maximum Receive Data
+                                            // Endpoint 1
+#define USB_O_RXCSRL1           0x00000116  // USB Receive Control and Status
+                                            // Endpoint 1 Low
+#define USB_O_RXCSRH1           0x00000117  // USB Receive Control and Status
+                                            // Endpoint 1 High
+#define USB_O_RXCOUNT1          0x00000118  // USB Receive Byte Count Endpoint
+                                            // 1
+#define USB_O_TXTYPE1           0x0000011A  // USB Host Transmit Configure Type
+                                            // Endpoint 1
+#define USB_O_TXINTERVAL1       0x0000011B  // USB Host Transmit Interval
+                                            // Endpoint 1
+#define USB_O_RXTYPE1           0x0000011C  // USB Host Configure Receive Type
+                                            // Endpoint 1
+#define USB_O_RXINTERVAL1       0x0000011D  // USB Host Receive Polling
+                                            // Interval Endpoint 1
+#define USB_O_TXMAXP2           0x00000120  // USB Maximum Transmit Data
+                                            // Endpoint 2
+#define USB_O_TXCSRL2           0x00000122  // USB Transmit Control and Status
+                                            // Endpoint 2 Low
+#define USB_O_TXCSRH2           0x00000123  // USB Transmit Control and Status
+                                            // Endpoint 2 High
+#define USB_O_RXMAXP2           0x00000124  // USB Maximum Receive Data
+                                            // Endpoint 2
+#define USB_O_RXCSRL2           0x00000126  // USB Receive Control and Status
+                                            // Endpoint 2 Low
+#define USB_O_RXCSRH2           0x00000127  // USB Receive Control and Status
+                                            // Endpoint 2 High
+#define USB_O_RXCOUNT2          0x00000128  // USB Receive Byte Count Endpoint
+                                            // 2
+#define USB_O_TXTYPE2           0x0000012A  // USB Host Transmit Configure Type
+                                            // Endpoint 2
+#define USB_O_TXINTERVAL2       0x0000012B  // USB Host Transmit Interval
+                                            // Endpoint 2
+#define USB_O_RXTYPE2           0x0000012C  // USB Host Configure Receive Type
+                                            // Endpoint 2
+#define USB_O_RXINTERVAL2       0x0000012D  // USB Host Receive Polling
+                                            // Interval Endpoint 2
+#define USB_O_TXMAXP3           0x00000130  // USB Maximum Transmit Data
+                                            // Endpoint 3
+#define USB_O_TXCSRL3           0x00000132  // USB Transmit Control and Status
+                                            // Endpoint 3 Low
+#define USB_O_TXCSRH3           0x00000133  // USB Transmit Control and Status
+                                            // Endpoint 3 High
+#define USB_O_RXMAXP3           0x00000134  // USB Maximum Receive Data
+                                            // Endpoint 3
+#define USB_O_RXCSRL3           0x00000136  // USB Receive Control and Status
+                                            // Endpoint 3 Low
+#define USB_O_RXCSRH3           0x00000137  // USB Receive Control and Status
+                                            // Endpoint 3 High
+#define USB_O_RXCOUNT3          0x00000138  // USB Receive Byte Count Endpoint
+                                            // 3
+#define USB_O_TXTYPE3           0x0000013A  // USB Host Transmit Configure Type
+                                            // Endpoint 3
+#define USB_O_TXINTERVAL3       0x0000013B  // USB Host Transmit Interval
+                                            // Endpoint 3
+#define USB_O_RXTYPE3           0x0000013C  // USB Host Configure Receive Type
+                                            // Endpoint 3
+#define USB_O_RXINTERVAL3       0x0000013D  // USB Host Receive Polling
+                                            // Interval Endpoint 3
+#define USB_O_TXMAXP4           0x00000140  // USB Maximum Transmit Data
+                                            // Endpoint 4
+#define USB_O_TXCSRL4           0x00000142  // USB Transmit Control and Status
+                                            // Endpoint 4 Low
+#define USB_O_TXCSRH4           0x00000143  // USB Transmit Control and Status
+                                            // Endpoint 4 High
+#define USB_O_RXMAXP4           0x00000144  // USB Maximum Receive Data
+                                            // Endpoint 4
+#define USB_O_RXCSRL4           0x00000146  // USB Receive Control and Status
+                                            // Endpoint 4 Low
+#define USB_O_RXCSRH4           0x00000147  // USB Receive Control and Status
+                                            // Endpoint 4 High
+#define USB_O_RXCOUNT4          0x00000148  // USB Receive Byte Count Endpoint
+                                            // 4
+#define USB_O_TXTYPE4           0x0000014A  // USB Host Transmit Configure Type
+                                            // Endpoint 4
+#define USB_O_TXINTERVAL4       0x0000014B  // USB Host Transmit Interval
+                                            // Endpoint 4
+#define USB_O_RXTYPE4           0x0000014C  // USB Host Configure Receive Type
+                                            // Endpoint 4
+#define USB_O_RXINTERVAL4       0x0000014D  // USB Host Receive Polling
+                                            // Interval Endpoint 4
+#define USB_O_TXMAXP5           0x00000150  // USB Maximum Transmit Data
+                                            // Endpoint 5
+#define USB_O_TXCSRL5           0x00000152  // USB Transmit Control and Status
+                                            // Endpoint 5 Low
+#define USB_O_TXCSRH5           0x00000153  // USB Transmit Control and Status
+                                            // Endpoint 5 High
+#define USB_O_RXMAXP5           0x00000154  // USB Maximum Receive Data
+                                            // Endpoint 5
+#define USB_O_RXCSRL5           0x00000156  // USB Receive Control and Status
+                                            // Endpoint 5 Low
+#define USB_O_RXCSRH5           0x00000157  // USB Receive Control and Status
+                                            // Endpoint 5 High
+#define USB_O_RXCOUNT5          0x00000158  // USB Receive Byte Count Endpoint
+                                            // 5
+#define USB_O_TXTYPE5           0x0000015A  // USB Host Transmit Configure Type
+                                            // Endpoint 5
+#define USB_O_TXINTERVAL5       0x0000015B  // USB Host Transmit Interval
+                                            // Endpoint 5
+#define USB_O_RXTYPE5           0x0000015C  // USB Host Configure Receive Type
+                                            // Endpoint 5
+#define USB_O_RXINTERVAL5       0x0000015D  // USB Host Receive Polling
+                                            // Interval Endpoint 5
+#define USB_O_TXMAXP6           0x00000160  // USB Maximum Transmit Data
+                                            // Endpoint 6
+#define USB_O_TXCSRL6           0x00000162  // USB Transmit Control and Status
+                                            // Endpoint 6 Low
+#define USB_O_TXCSRH6           0x00000163  // USB Transmit Control and Status
+                                            // Endpoint 6 High
+#define USB_O_RXMAXP6           0x00000164  // USB Maximum Receive Data
+                                            // Endpoint 6
+#define USB_O_RXCSRL6           0x00000166  // USB Receive Control and Status
+                                            // Endpoint 6 Low
+#define USB_O_RXCSRH6           0x00000167  // USB Receive Control and Status
+                                            // Endpoint 6 High
+#define USB_O_RXCOUNT6          0x00000168  // USB Receive Byte Count Endpoint
+                                            // 6
+#define USB_O_TXTYPE6           0x0000016A  // USB Host Transmit Configure Type
+                                            // Endpoint 6
+#define USB_O_TXINTERVAL6       0x0000016B  // USB Host Transmit Interval
+                                            // Endpoint 6
+#define USB_O_RXTYPE6           0x0000016C  // USB Host Configure Receive Type
+                                            // Endpoint 6
+#define USB_O_RXINTERVAL6       0x0000016D  // USB Host Receive Polling
+                                            // Interval Endpoint 6
+#define USB_O_TXMAXP7           0x00000170  // USB Maximum Transmit Data
+                                            // Endpoint 7
+#define USB_O_TXCSRL7           0x00000172  // USB Transmit Control and Status
+                                            // Endpoint 7 Low
+#define USB_O_TXCSRH7           0x00000173  // USB Transmit Control and Status
+                                            // Endpoint 7 High
+#define USB_O_RXMAXP7           0x00000174  // USB Maximum Receive Data
+                                            // Endpoint 7
+#define USB_O_RXCSRL7           0x00000176  // USB Receive Control and Status
+                                            // Endpoint 7 Low
+#define USB_O_RXCSRH7           0x00000177  // USB Receive Control and Status
+                                            // Endpoint 7 High
+#define USB_O_RXCOUNT7          0x00000178  // USB Receive Byte Count Endpoint
+                                            // 7
+#define USB_O_TXTYPE7           0x0000017A  // USB Host Transmit Configure Type
+                                            // Endpoint 7
+#define USB_O_TXINTERVAL7       0x0000017B  // USB Host Transmit Interval
+                                            // Endpoint 7
+#define USB_O_RXTYPE7           0x0000017C  // USB Host Configure Receive Type
+                                            // Endpoint 7
+#define USB_O_RXINTERVAL7       0x0000017D  // USB Host Receive Polling
+                                            // Interval Endpoint 7
+#define USB_O_DMAINTR           0x00000200  // USB DMA Interrupt
+#define USB_O_DMACTL0           0x00000204  // USB DMA Control 0
+#define USB_O_DMAADDR0          0x00000208  // USB DMA Address 0
+#define USB_O_DMACOUNT0         0x0000020C  // USB DMA Count 0
+#define USB_O_DMACTL1           0x00000214  // USB DMA Control 1
+#define USB_O_DMAADDR1          0x00000218  // USB DMA Address 1
+#define USB_O_DMACOUNT1         0x0000021C  // USB DMA Count 1
+#define USB_O_DMACTL2           0x00000224  // USB DMA Control 2
+#define USB_O_DMAADDR2          0x00000228  // USB DMA Address 2
+#define USB_O_DMACOUNT2         0x0000022C  // USB DMA Count 2
+#define USB_O_DMACTL3           0x00000234  // USB DMA Control 3
+#define USB_O_DMAADDR3          0x00000238  // USB DMA Address 3
+#define USB_O_DMACOUNT3         0x0000023C  // USB DMA Count 3
+#define USB_O_DMACTL4           0x00000244  // USB DMA Control 4
+#define USB_O_DMAADDR4          0x00000248  // USB DMA Address 4
+#define USB_O_DMACOUNT4         0x0000024C  // USB DMA Count 4
+#define USB_O_DMACTL5           0x00000254  // USB DMA Control 5
+#define USB_O_DMAADDR5          0x00000258  // USB DMA Address 5
+#define USB_O_DMACOUNT5         0x0000025C  // USB DMA Count 5
+#define USB_O_DMACTL6           0x00000264  // USB DMA Control 6
+#define USB_O_DMAADDR6          0x00000268  // USB DMA Address 6
+#define USB_O_DMACOUNT6         0x0000026C  // USB DMA Count 6
+#define USB_O_DMACTL7           0x00000274  // USB DMA Control 7
+#define USB_O_DMAADDR7          0x00000278  // USB DMA Address 7
+#define USB_O_DMACOUNT7         0x0000027C  // USB DMA Count 7
+#define USB_O_RQPKTCOUNT1       0x00000304  // USB Request Packet Count in
+                                            // Block Transfer Endpoint 1
+#define USB_O_RQPKTCOUNT2       0x00000308  // USB Request Packet Count in
+                                            // Block Transfer Endpoint 2
+#define USB_O_RQPKTCOUNT3       0x0000030C  // USB Request Packet Count in
+                                            // Block Transfer Endpoint 3
+#define USB_O_RQPKTCOUNT4       0x00000310  // USB Request Packet Count in
+                                            // Block Transfer Endpoint 4
+#define USB_O_RQPKTCOUNT5       0x00000314  // USB Request Packet Count in
+                                            // Block Transfer Endpoint 5
+#define USB_O_RQPKTCOUNT6       0x00000318  // USB Request Packet Count in
+                                            // Block Transfer Endpoint 6
+#define USB_O_RQPKTCOUNT7       0x0000031C  // USB Request Packet Count in
+                                            // Block Transfer Endpoint 7
+#define USB_O_RXDPKTBUFDIS      0x00000340  // USB Receive Double Packet Buffer
+                                            // Disable
+#define USB_O_TXDPKTBUFDIS      0x00000342  // USB Transmit Double Packet
+                                            // Buffer Disable
+#define USB_O_CTO               0x00000344  // USB Chirp Timeout
+#define USB_O_HHSRTN            0x00000346  // USB High Speed to UTM Operating
+                                            // Delay
+#define USB_O_HSBT              0x00000348  // USB High Speed Time-out Adder
+#define USB_O_LPMATTR           0x00000360  // USB LPM Attributes
+#define USB_O_LPMCNTRL          0x00000362  // USB LPM Control
+#define USB_O_LPMIM             0x00000363  // USB LPM Interrupt Mask
+#define USB_O_LPMRIS            0x00000364  // USB LPM Raw Interrupt Status
+#define USB_O_LPMFADDR          0x00000365  // USB LPM Function Address
+#define USB_O_EPC               0x00000400  // USB External Power Control
+#define USB_O_EPCRIS            0x00000404  // USB External Power Control Raw
+                                            // Interrupt Status
+#define USB_O_EPCIM             0x00000408  // USB External Power Control
+                                            // Interrupt Mask
+#define USB_O_EPCISC            0x0000040C  // USB External Power Control
+                                            // Interrupt Status and Clear
+#define USB_O_DRRIS             0x00000410  // USB Device RESUME Raw Interrupt
+                                            // Status
+#define USB_O_DRIM              0x00000414  // USB Device RESUME Interrupt Mask
+#define USB_O_DRISC             0x00000418  // USB Device RESUME Interrupt
+                                            // Status and Clear
+#define USB_O_GPCS              0x0000041C  // USB General-Purpose Control and
+                                            // Status
+#define USB_O_VDC               0x00000430  // USB VBUS Droop Control
+#define USB_O_VDCRIS            0x00000434  // USB VBUS Droop Control Raw
+                                            // Interrupt Status
+#define USB_O_VDCIM             0x00000438  // USB VBUS Droop Control Interrupt
+                                            // Mask
+#define USB_O_VDCISC            0x0000043C  // USB VBUS Droop Control Interrupt
+                                            // Status and Clear
+#define USB_O_IDVRIS            0x00000444  // USB ID Valid Detect Raw
+                                            // Interrupt Status
+#define USB_O_IDVIM             0x00000448  // USB ID Valid Detect Interrupt
+                                            // Mask
+#define USB_O_IDVISC            0x0000044C  // USB ID Valid Detect Interrupt
+                                            // Status and Clear
+#define USB_O_DMASEL            0x00000450  // USB DMA Select
+#define USB_O_PP                0x00000FC0  // USB Peripheral Properties
+#define USB_O_PC                0x00000FC4  // USB Peripheral Configuration
+#define USB_O_CC                0x00000FC8  // USB Clock Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FADDR register.
+//
+//*****************************************************************************
+#define USB_FADDR_M             0x0000007F  // Function Address
+#define USB_FADDR_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_POWER register.
+//
+//*****************************************************************************
+#define USB_POWER_ISOUP         0x00000080  // Isochronous Update
+#define USB_POWER_SOFTCONN      0x00000040  // Soft Connect/Disconnect
+#define USB_POWER_HSENAB        0x00000020  // High Speed Enable
+#define USB_POWER_HSMODE        0x00000010  // High Speed Enable
+#define USB_POWER_RESET         0x00000008  // RESET Signaling
+#define USB_POWER_RESUME        0x00000004  // RESUME Signaling
+#define USB_POWER_SUSPEND       0x00000002  // SUSPEND Mode
+#define USB_POWER_PWRDNPHY      0x00000001  // Power Down PHY
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIS register.
+//
+//*****************************************************************************
+#define USB_TXIS_EP7            0x00000080  // TX Endpoint 7 Interrupt
+#define USB_TXIS_EP6            0x00000040  // TX Endpoint 6 Interrupt
+#define USB_TXIS_EP5            0x00000020  // TX Endpoint 5 Interrupt
+#define USB_TXIS_EP4            0x00000010  // TX Endpoint 4 Interrupt
+#define USB_TXIS_EP3            0x00000008  // TX Endpoint 3 Interrupt
+#define USB_TXIS_EP2            0x00000004  // TX Endpoint 2 Interrupt
+#define USB_TXIS_EP1            0x00000002  // TX Endpoint 1 Interrupt
+#define USB_TXIS_EP0            0x00000001  // TX and RX Endpoint 0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIS register.
+//
+//*****************************************************************************
+#define USB_RXIS_EP7            0x00000080  // RX Endpoint 7 Interrupt
+#define USB_RXIS_EP6            0x00000040  // RX Endpoint 6 Interrupt
+#define USB_RXIS_EP5            0x00000020  // RX Endpoint 5 Interrupt
+#define USB_RXIS_EP4            0x00000010  // RX Endpoint 4 Interrupt
+#define USB_RXIS_EP3            0x00000008  // RX Endpoint 3 Interrupt
+#define USB_RXIS_EP2            0x00000004  // RX Endpoint 2 Interrupt
+#define USB_RXIS_EP1            0x00000002  // RX Endpoint 1 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIE register.
+//
+//*****************************************************************************
+#define USB_TXIE_EP7            0x00000080  // TX Endpoint 7 Interrupt Enable
+#define USB_TXIE_EP6            0x00000040  // TX Endpoint 6 Interrupt Enable
+#define USB_TXIE_EP5            0x00000020  // TX Endpoint 5 Interrupt Enable
+#define USB_TXIE_EP4            0x00000010  // TX Endpoint 4 Interrupt Enable
+#define USB_TXIE_EP3            0x00000008  // TX Endpoint 3 Interrupt Enable
+#define USB_TXIE_EP2            0x00000004  // TX Endpoint 2 Interrupt Enable
+#define USB_TXIE_EP1            0x00000002  // TX Endpoint 1 Interrupt Enable
+#define USB_TXIE_EP0            0x00000001  // TX and RX Endpoint 0 Interrupt
+                                            // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIE register.
+//
+//*****************************************************************************
+#define USB_RXIE_EP7            0x00000080  // RX Endpoint 7 Interrupt Enable
+#define USB_RXIE_EP6            0x00000040  // RX Endpoint 6 Interrupt Enable
+#define USB_RXIE_EP5            0x00000020  // RX Endpoint 5 Interrupt Enable
+#define USB_RXIE_EP4            0x00000010  // RX Endpoint 4 Interrupt Enable
+#define USB_RXIE_EP3            0x00000008  // RX Endpoint 3 Interrupt Enable
+#define USB_RXIE_EP2            0x00000004  // RX Endpoint 2 Interrupt Enable
+#define USB_RXIE_EP1            0x00000002  // RX Endpoint 1 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IS register.
+//
+//*****************************************************************************
+#define USB_IS_VBUSERR          0x00000080  // VBUS Error (OTG only)
+#define USB_IS_SESREQ           0x00000040  // SESSION REQUEST (OTG only)
+#define USB_IS_DISCON           0x00000020  // Session Disconnect (OTG only)
+#define USB_IS_CONN             0x00000010  // Session Connect
+#define USB_IS_SOF              0x00000008  // Start of Frame
+#define USB_IS_BABBLE           0x00000004  // Babble Detected
+#define USB_IS_RESET            0x00000004  // RESET Signaling Detected
+#define USB_IS_RESUME           0x00000002  // RESUME Signaling Detected
+#define USB_IS_SUSPEND          0x00000001  // SUSPEND Signaling Detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IE register.
+//
+//*****************************************************************************
+#define USB_IE_VBUSERR          0x00000080  // Enable VBUS Error Interrupt (OTG
+                                            // only)
+#define USB_IE_SESREQ           0x00000040  // Enable Session Request (OTG
+                                            // only)
+#define USB_IE_DISCON           0x00000020  // Enable Disconnect Interrupt
+#define USB_IE_CONN             0x00000010  // Enable Connect Interrupt
+#define USB_IE_SOF              0x00000008  // Enable Start-of-Frame Interrupt
+#define USB_IE_BABBLE           0x00000004  // Enable Babble Interrupt
+#define USB_IE_RESET            0x00000004  // Enable RESET Interrupt
+#define USB_IE_RESUME           0x00000002  // Enable RESUME Interrupt
+#define USB_IE_SUSPND           0x00000001  // Enable SUSPEND Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FRAME register.
+//
+//*****************************************************************************
+#define USB_FRAME_M             0x000007FF  // Frame Number
+#define USB_FRAME_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPIDX register.
+//
+//*****************************************************************************
+#define USB_EPIDX_EPIDX_M       0x0000000F  // Endpoint Index
+#define USB_EPIDX_EPIDX_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TEST register.
+//
+//*****************************************************************************
+#define USB_TEST_FORCEH         0x00000080  // Force Host Mode
+#define USB_TEST_FIFOACC        0x00000040  // FIFO Access
+#define USB_TEST_FORCEFS        0x00000020  // Force Full-Speed Mode
+#define USB_TEST_FORCEHS        0x00000010  // Force High-Speed Mode
+#define USB_TEST_TESTPKT        0x00000008  // Test Packet Mode Enable
+#define USB_TEST_TESTK          0x00000004  // Test_K Mode Enable
+#define USB_TEST_TESTJ          0x00000002  // Test_J Mode Enable
+#define USB_TEST_TESTSE0NAK     0x00000001  // Test_SE0_NAK Test Mode Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO0 register.
+//
+//*****************************************************************************
+#define USB_FIFO0_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO0_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO1 register.
+//
+//*****************************************************************************
+#define USB_FIFO1_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO1_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO2 register.
+//
+//*****************************************************************************
+#define USB_FIFO2_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO2_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO3 register.
+//
+//*****************************************************************************
+#define USB_FIFO3_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO3_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO4 register.
+//
+//*****************************************************************************
+#define USB_FIFO4_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO4_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO5 register.
+//
+//*****************************************************************************
+#define USB_FIFO5_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO5_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO6 register.
+//
+//*****************************************************************************
+#define USB_FIFO6_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO6_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO7 register.
+//
+//*****************************************************************************
+#define USB_FIFO7_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO7_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DEVCTL register.
+//
+//*****************************************************************************
+#define USB_DEVCTL_DEV          0x00000080  // Device Mode (OTG only)
+#define USB_DEVCTL_FSDEV        0x00000040  // Full-Speed Device Detected
+#define USB_DEVCTL_LSDEV        0x00000020  // Low-Speed Device Detected
+#define USB_DEVCTL_VBUS_M       0x00000018  // VBUS Level (OTG only)
+#define USB_DEVCTL_VBUS_NONE    0x00000000  // Below SessionEnd
+#define USB_DEVCTL_VBUS_SEND    0x00000008  // Above SessionEnd, below AValid
+#define USB_DEVCTL_VBUS_AVALID  0x00000010  // Above AValid, below VBUSValid
+#define USB_DEVCTL_VBUS_VALID   0x00000018  // Above VBUSValid
+#define USB_DEVCTL_HOST         0x00000004  // Host Mode
+#define USB_DEVCTL_HOSTREQ      0x00000002  // Host Request (OTG only)
+#define USB_DEVCTL_SESSION      0x00000001  // Session Start/End (OTG only)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CCONF register.
+//
+//*****************************************************************************
+#define USB_CCONF_TXEDMA        0x00000002  // TX Early DMA Enable
+#define USB_CCONF_RXEDMA        0x00000001  // TX Early DMA Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_TXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support
+#define USB_TXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size
+#define USB_TXFIFOSZ_SIZE_8     0x00000000  // 8
+#define USB_TXFIFOSZ_SIZE_16    0x00000001  // 16
+#define USB_TXFIFOSZ_SIZE_32    0x00000002  // 32
+#define USB_TXFIFOSZ_SIZE_64    0x00000003  // 64
+#define USB_TXFIFOSZ_SIZE_128   0x00000004  // 128
+#define USB_TXFIFOSZ_SIZE_256   0x00000005  // 256
+#define USB_TXFIFOSZ_SIZE_512   0x00000006  // 512
+#define USB_TXFIFOSZ_SIZE_1024  0x00000007  // 1024
+#define USB_TXFIFOSZ_SIZE_2048  0x00000008  // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_RXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support
+#define USB_RXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size
+#define USB_RXFIFOSZ_SIZE_8     0x00000000  // 8
+#define USB_RXFIFOSZ_SIZE_16    0x00000001  // 16
+#define USB_RXFIFOSZ_SIZE_32    0x00000002  // 32
+#define USB_RXFIFOSZ_SIZE_64    0x00000003  // 64
+#define USB_RXFIFOSZ_SIZE_128   0x00000004  // 128
+#define USB_RXFIFOSZ_SIZE_256   0x00000005  // 256
+#define USB_RXFIFOSZ_SIZE_512   0x00000006  // 512
+#define USB_RXFIFOSZ_SIZE_1024  0x00000007  // 1024
+#define USB_RXFIFOSZ_SIZE_2048  0x00000008  // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_TXFIFOADD_ADDR_M    0x000001FF  // Transmit/Receive Start Address
+#define USB_TXFIFOADD_ADDR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_RXFIFOADD_ADDR_M    0x000001FF  // Transmit/Receive Start Address
+#define USB_RXFIFOADD_ADDR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_ULPIVBUSCTL
+// register.
+//
+//*****************************************************************************
+#define USB_ULPIVBUSCTL_USEEXTVBUSIND                                         \
+                                0x00000002  // Use External VBUS Indicator
+#define USB_ULPIVBUSCTL_USEEXTVBUS                                            \
+                                0x00000001  // Use External VBUS
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_ULPIREGDATA
+// register.
+//
+//*****************************************************************************
+#define USB_ULPIREGDATA_REGDATA_M                                             \
+                                0x000000FF  // Register Data
+#define USB_ULPIREGDATA_REGDATA_S                                             \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_ULPIREGADDR
+// register.
+//
+//*****************************************************************************
+#define USB_ULPIREGADDR_ADDR_M  0x000000FF  // Register Address
+#define USB_ULPIREGADDR_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_ULPIREGCTL
+// register.
+//
+//*****************************************************************************
+#define USB_ULPIREGCTL_RDWR     0x00000004  // Read/Write Control
+#define USB_ULPIREGCTL_REGCMPLT 0x00000002  // Register Access Complete
+#define USB_ULPIREGCTL_REGACC   0x00000001  // Initiate Register Access
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPINFO register.
+//
+//*****************************************************************************
+#define USB_EPINFO_RXEP_M       0x000000F0  // RX Endpoints
+#define USB_EPINFO_TXEP_M       0x0000000F  // TX Endpoints
+#define USB_EPINFO_RXEP_S       4
+#define USB_EPINFO_TXEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RAMINFO register.
+//
+//*****************************************************************************
+#define USB_RAMINFO_DMACHAN_M   0x000000F0  // DMA Channels
+#define USB_RAMINFO_RAMBITS_M   0x0000000F  // RAM Address Bus Width
+#define USB_RAMINFO_DMACHAN_S   4
+#define USB_RAMINFO_RAMBITS_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CONTIM register.
+//
+//*****************************************************************************
+#define USB_CONTIM_WTCON_M      0x000000F0  // Connect Wait
+#define USB_CONTIM_WTID_M       0x0000000F  // Wait ID
+#define USB_CONTIM_WTCON_S      4
+#define USB_CONTIM_WTID_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VPLEN register.
+//
+//*****************************************************************************
+#define USB_VPLEN_VPLEN_M       0x000000FF  // VBUS Pulse Length
+#define USB_VPLEN_VPLEN_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_HSEOF register.
+//
+//*****************************************************************************
+#define USB_HSEOF_HSEOFG_M      0x000000FF  // HIgh-Speed End-of-Frame Gap
+#define USB_HSEOF_HSEOFG_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FSEOF register.
+//
+//*****************************************************************************
+#define USB_FSEOF_FSEOFG_M      0x000000FF  // Full-Speed End-of-Frame Gap
+#define USB_FSEOF_FSEOFG_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LSEOF register.
+//
+//*****************************************************************************
+#define USB_LSEOF_LSEOFG_M      0x000000FF  // Low-Speed End-of-Frame Gap
+#define USB_LSEOF_LSEOFG_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR0
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR0_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR0_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR0
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR0_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR0_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT0
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT0_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT0_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR1_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR1_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR1_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR1_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT1
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT1_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT1_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR1_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR1_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR1_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR1_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT1
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT1_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT1_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR2_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR2_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR2_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR2_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT2
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT2_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT2_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR2_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR2_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR2_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR2_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT2
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT2_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT2_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR3_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR3_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR3_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR3_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT3
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT3_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT3_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR3_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR3_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR3_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR3_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT3
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT3_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT3_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR4_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR4_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR4_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR4_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT4
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT4_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT4_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR4_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR4_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR4_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR4_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT4
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT4_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT4_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR5_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR5_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR5_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR5_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT5
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT5_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT5_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR5_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR5_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR5_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR5_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT5
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT5_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT5_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR6_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR6_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR6_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR6_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT6
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT6_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT6_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR6_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR6_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR6_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR6_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT6
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT6_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT6_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR7_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR7_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR7_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR7_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT7
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT7_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT7_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR7_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR7_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR7_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR7_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT7
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT7_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT7_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRL0 register.
+//
+//*****************************************************************************
+#define USB_CSRL0_NAKTO         0x00000080  // NAK Timeout
+#define USB_CSRL0_SETENDC       0x00000080  // Setup End Clear
+#define USB_CSRL0_STATUS        0x00000040  // STATUS Packet
+#define USB_CSRL0_RXRDYC        0x00000040  // RXRDY Clear
+#define USB_CSRL0_REQPKT        0x00000020  // Request Packet
+#define USB_CSRL0_STALL         0x00000020  // Send Stall
+#define USB_CSRL0_SETEND        0x00000010  // Setup End
+#define USB_CSRL0_ERROR         0x00000010  // Error
+#define USB_CSRL0_DATAEND       0x00000008  // Data End
+#define USB_CSRL0_SETUP         0x00000008  // Setup Packet
+#define USB_CSRL0_STALLED       0x00000004  // Endpoint Stalled
+#define USB_CSRL0_TXRDY         0x00000002  // Transmit Packet Ready
+#define USB_CSRL0_RXRDY         0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRH0 register.
+//
+//*****************************************************************************
+#define USB_CSRH0_DISPING       0x00000008  // PING Disable
+#define USB_CSRH0_DTWE          0x00000004  // Data Toggle Write Enable
+#define USB_CSRH0_DT            0x00000002  // Data Toggle
+#define USB_CSRH0_FLUSH         0x00000001  // Flush FIFO
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_COUNT0 register.
+//
+//*****************************************************************************
+#define USB_COUNT0_COUNT_M      0x0000007F  // FIFO Count
+#define USB_COUNT0_COUNT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TYPE0 register.
+//
+//*****************************************************************************
+#define USB_TYPE0_SPEED_M       0x000000C0  // Operating Speed
+#define USB_TYPE0_SPEED_HIGH    0x00000040  // High
+#define USB_TYPE0_SPEED_FULL    0x00000080  // Full
+#define USB_TYPE0_SPEED_LOW     0x000000C0  // Low
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_NAKLMT register.
+//
+//*****************************************************************************
+#define USB_NAKLMT_NAKLMT_M     0x0000001F  // EP0 NAK Limit
+#define USB_NAKLMT_NAKLMT_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP1_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP1_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL1_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL1_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL1_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL1_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL1_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL1_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL1_ERROR       0x00000004  // Error
+#define USB_TXCSRL1_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL1_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL1_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH1_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH1_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH1_MODE        0x00000020  // Mode
+#define USB_TXCSRH1_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH1_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH1_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH1_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH1_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP1_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP1_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL1_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL1_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL1_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL1_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL1_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL1_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL1_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL1_OVER        0x00000004  // Overrun
+#define USB_RXCSRL1_ERROR       0x00000004  // Error
+#define USB_RXCSRL1_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL1_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH1_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH1_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH1_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH1_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH1_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH1_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH1_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH1_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH1_DT          0x00000002  // Data Toggle
+#define USB_RXCSRH1_INCOMPRX    0x00000001  // Incomplete RX Transmission
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT1 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT1_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT1_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE1 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE1_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE1_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE1_SPEED_HIGH  0x00000040  // High
+#define USB_TXTYPE1_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE1_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE1_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE1_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE1_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE1_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE1_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE1_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE1_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL1
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL1_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL1_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL1_TXPOLL_S                                              \
+                                0
+#define USB_TXINTERVAL1_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE1 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE1_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE1_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE1_SPEED_HIGH  0x00000040  // High
+#define USB_RXTYPE1_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE1_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE1_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE1_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE1_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE1_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE1_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE1_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE1_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL1
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL1_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL1_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL1_TXPOLL_S                                              \
+                                0
+#define USB_RXINTERVAL1_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP2_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP2_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL2_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL2_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL2_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL2_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL2_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL2_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL2_ERROR       0x00000004  // Error
+#define USB_TXCSRL2_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL2_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL2_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH2_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH2_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH2_MODE        0x00000020  // Mode
+#define USB_TXCSRH2_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH2_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH2_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH2_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH2_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP2_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP2_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL2_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL2_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL2_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL2_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL2_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL2_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL2_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL2_ERROR       0x00000004  // Error
+#define USB_RXCSRL2_OVER        0x00000004  // Overrun
+#define USB_RXCSRL2_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL2_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH2_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH2_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH2_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH2_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH2_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH2_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH2_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH2_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH2_DT          0x00000002  // Data Toggle
+#define USB_RXCSRH2_INCOMPRX    0x00000001  // Incomplete RX Transmission
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT2 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT2_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT2_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE2 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE2_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE2_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE2_SPEED_HIGH  0x00000040  // High
+#define USB_TXTYPE2_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE2_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE2_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE2_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE2_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE2_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE2_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE2_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE2_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL2
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL2_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL2_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL2_NAKLMT_S                                              \
+                                0
+#define USB_TXINTERVAL2_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE2 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE2_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE2_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE2_SPEED_HIGH  0x00000040  // High
+#define USB_RXTYPE2_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE2_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE2_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE2_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE2_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE2_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE2_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE2_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE2_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL2
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL2_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL2_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL2_TXPOLL_S                                              \
+                                0
+#define USB_RXINTERVAL2_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP3_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP3_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL3_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL3_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL3_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL3_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL3_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL3_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL3_ERROR       0x00000004  // Error
+#define USB_TXCSRL3_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL3_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL3_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH3_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH3_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH3_MODE        0x00000020  // Mode
+#define USB_TXCSRH3_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH3_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH3_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH3_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH3_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP3_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP3_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL3_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL3_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL3_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL3_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL3_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL3_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL3_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL3_ERROR       0x00000004  // Error
+#define USB_RXCSRL3_OVER        0x00000004  // Overrun
+#define USB_RXCSRL3_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL3_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH3_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH3_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH3_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH3_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH3_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH3_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH3_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH3_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH3_DT          0x00000002  // Data Toggle
+#define USB_RXCSRH3_INCOMPRX    0x00000001  // Incomplete RX Transmission
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT3 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT3_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT3_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE3 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE3_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE3_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE3_SPEED_HIGH  0x00000040  // High
+#define USB_TXTYPE3_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE3_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE3_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE3_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE3_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE3_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE3_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE3_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE3_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL3
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL3_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL3_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL3_TXPOLL_S                                              \
+                                0
+#define USB_TXINTERVAL3_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE3 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE3_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE3_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE3_SPEED_HIGH  0x00000040  // High
+#define USB_RXTYPE3_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE3_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE3_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE3_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE3_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE3_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE3_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE3_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE3_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL3
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL3_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL3_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL3_TXPOLL_S                                              \
+                                0
+#define USB_RXINTERVAL3_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP4 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP4_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP4_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL4 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL4_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL4_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL4_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL4_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL4_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL4_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL4_ERROR       0x00000004  // Error
+#define USB_TXCSRL4_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL4_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL4_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH4 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH4_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH4_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH4_MODE        0x00000020  // Mode
+#define USB_TXCSRH4_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH4_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH4_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH4_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH4_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP4 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP4_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP4_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL4 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL4_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL4_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL4_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL4_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL4_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL4_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL4_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL4_OVER        0x00000004  // Overrun
+#define USB_RXCSRL4_ERROR       0x00000004  // Error
+#define USB_RXCSRL4_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL4_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH4 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH4_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH4_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH4_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH4_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH4_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH4_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH4_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH4_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH4_DT          0x00000002  // Data Toggle
+#define USB_RXCSRH4_INCOMPRX    0x00000001  // Incomplete RX Transmission
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT4 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT4_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT4_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE4 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE4_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE4_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE4_SPEED_HIGH  0x00000040  // High
+#define USB_TXTYPE4_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE4_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE4_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE4_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE4_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE4_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE4_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE4_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE4_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL4
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL4_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL4_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL4_NAKLMT_S                                              \
+                                0
+#define USB_TXINTERVAL4_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE4 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE4_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE4_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE4_SPEED_HIGH  0x00000040  // High
+#define USB_RXTYPE4_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE4_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE4_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE4_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE4_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE4_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE4_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE4_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE4_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL4
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL4_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL4_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL4_NAKLMT_S                                              \
+                                0
+#define USB_RXINTERVAL4_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP5 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP5_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP5_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL5 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL5_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL5_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL5_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL5_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL5_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL5_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL5_ERROR       0x00000004  // Error
+#define USB_TXCSRL5_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL5_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL5_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH5 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH5_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH5_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH5_MODE        0x00000020  // Mode
+#define USB_TXCSRH5_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH5_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH5_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH5_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH5_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP5 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP5_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP5_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL5 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL5_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL5_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL5_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL5_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL5_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL5_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL5_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL5_ERROR       0x00000004  // Error
+#define USB_RXCSRL5_OVER        0x00000004  // Overrun
+#define USB_RXCSRL5_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL5_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH5 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH5_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH5_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH5_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH5_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH5_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH5_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH5_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH5_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH5_DT          0x00000002  // Data Toggle
+#define USB_RXCSRH5_INCOMPRX    0x00000001  // Incomplete RX Transmission
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT5 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT5_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT5_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE5 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE5_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE5_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE5_SPEED_HIGH  0x00000040  // High
+#define USB_TXTYPE5_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE5_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE5_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE5_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE5_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE5_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE5_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE5_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE5_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL5
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL5_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL5_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL5_NAKLMT_S                                              \
+                                0
+#define USB_TXINTERVAL5_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE5 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE5_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE5_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE5_SPEED_HIGH  0x00000040  // High
+#define USB_RXTYPE5_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE5_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE5_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE5_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE5_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE5_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE5_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE5_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE5_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL5
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL5_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL5_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL5_TXPOLL_S                                              \
+                                0
+#define USB_RXINTERVAL5_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP6 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP6_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP6_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL6 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL6_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL6_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL6_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL6_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL6_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL6_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL6_ERROR       0x00000004  // Error
+#define USB_TXCSRL6_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL6_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL6_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH6 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH6_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH6_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH6_MODE        0x00000020  // Mode
+#define USB_TXCSRH6_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH6_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH6_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH6_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH6_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP6 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP6_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP6_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL6 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL6_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL6_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL6_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL6_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL6_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL6_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL6_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL6_ERROR       0x00000004  // Error
+#define USB_RXCSRL6_OVER        0x00000004  // Overrun
+#define USB_RXCSRL6_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL6_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH6 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH6_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH6_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH6_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH6_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH6_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH6_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH6_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH6_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH6_DT          0x00000002  // Data Toggle
+#define USB_RXCSRH6_INCOMPRX    0x00000001  // Incomplete RX Transmission
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT6 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT6_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT6_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE6 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE6_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE6_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE6_SPEED_HIGH  0x00000040  // High
+#define USB_TXTYPE6_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE6_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE6_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE6_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE6_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE6_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE6_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE6_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE6_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL6
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL6_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL6_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL6_TXPOLL_S                                              \
+                                0
+#define USB_TXINTERVAL6_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE6 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE6_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE6_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE6_SPEED_HIGH  0x00000040  // High
+#define USB_RXTYPE6_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE6_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE6_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE6_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE6_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE6_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE6_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE6_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE6_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL6
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL6_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL6_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL6_NAKLMT_S                                              \
+                                0
+#define USB_RXINTERVAL6_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP7 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP7_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP7_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL7 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL7_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL7_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL7_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL7_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL7_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL7_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL7_ERROR       0x00000004  // Error
+#define USB_TXCSRL7_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL7_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL7_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH7 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH7_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH7_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH7_MODE        0x00000020  // Mode
+#define USB_TXCSRH7_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH7_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH7_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH7_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH7_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP7 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP7_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP7_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL7 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL7_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL7_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL7_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL7_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL7_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL7_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL7_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL7_ERROR       0x00000004  // Error
+#define USB_RXCSRL7_OVER        0x00000004  // Overrun
+#define USB_RXCSRL7_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL7_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH7 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH7_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH7_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH7_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH7_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH7_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH7_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH7_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH7_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH7_DT          0x00000002  // Data Toggle
+#define USB_RXCSRH7_INCOMPRX    0x00000001  // Incomplete RX Transmission
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT7 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT7_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT7_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE7 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE7_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE7_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE7_SPEED_HIGH  0x00000040  // High
+#define USB_TXTYPE7_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE7_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE7_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE7_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE7_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE7_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE7_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE7_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE7_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL7
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL7_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL7_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL7_NAKLMT_S                                              \
+                                0
+#define USB_TXINTERVAL7_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE7 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE7_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE7_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE7_SPEED_HIGH  0x00000040  // High
+#define USB_RXTYPE7_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE7_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE7_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE7_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE7_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE7_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE7_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE7_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE7_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL7
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL7_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL7_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL7_NAKLMT_S                                              \
+                                0
+#define USB_RXINTERVAL7_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAINTR register.
+//
+//*****************************************************************************
+#define USB_DMAINTR_CH7         0x00000080  // Channel 7 DMA Interrupt
+#define USB_DMAINTR_CH6         0x00000040  // Channel 6 DMA Interrupt
+#define USB_DMAINTR_CH5         0x00000020  // Channel 5 DMA Interrupt
+#define USB_DMAINTR_CH4         0x00000010  // Channel 4 DMA Interrupt
+#define USB_DMAINTR_CH3         0x00000008  // Channel 3 DMA Interrupt
+#define USB_DMAINTR_CH2         0x00000004  // Channel 2 DMA Interrupt
+#define USB_DMAINTR_CH1         0x00000002  // Channel 1 DMA Interrupt
+#define USB_DMAINTR_CH0         0x00000001  // Channel 0 DMA Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL0 register.
+//
+//*****************************************************************************
+#define USB_DMACTL0_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL0_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL0_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL0_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL0_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL0_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL0_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL0_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL0_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL0_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL0_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL0_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR0 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR0_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR0_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT0
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT0_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT0_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL1 register.
+//
+//*****************************************************************************
+#define USB_DMACTL1_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL1_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL1_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL1_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL1_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL1_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL1_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL1_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL1_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL1_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL1_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL1_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR1 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR1_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR1_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT1
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT1_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT1_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL2 register.
+//
+//*****************************************************************************
+#define USB_DMACTL2_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL2_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL2_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL2_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL2_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL2_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL2_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL2_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL2_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL2_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL2_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL2_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR2 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR2_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR2_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT2
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT2_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT2_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL3 register.
+//
+//*****************************************************************************
+#define USB_DMACTL3_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL3_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL3_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL3_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL3_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL3_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL3_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL3_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL3_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL3_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL3_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL3_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR3 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR3_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR3_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT3
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT3_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT3_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL4 register.
+//
+//*****************************************************************************
+#define USB_DMACTL4_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL4_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL4_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL4_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL4_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL4_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL4_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL4_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL4_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL4_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL4_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL4_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR4 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR4_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR4_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT4
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT4_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT4_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL5 register.
+//
+//*****************************************************************************
+#define USB_DMACTL5_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL5_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL5_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL5_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL5_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL5_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL5_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL5_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL5_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL5_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL5_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL5_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR5 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR5_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR5_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT5
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT5_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT5_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL6 register.
+//
+//*****************************************************************************
+#define USB_DMACTL6_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL6_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL6_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL6_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL6_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL6_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL6_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL6_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL6_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL6_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL6_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL6_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR6 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR6_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR6_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT6
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT6_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT6_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL7 register.
+//
+//*****************************************************************************
+#define USB_DMACTL7_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL7_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL7_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL7_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL7_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL7_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL7_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL7_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL7_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL7_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL7_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL7_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR7 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR7_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR7_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT7
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT7_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT7_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT1_M       0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT1_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT2_M       0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT2_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT3_M       0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT3_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT4_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT5_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT6_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT7_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_RXDPKTBUFDIS_EP7    0x00000080  // EP7 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP6    0x00000040  // EP6 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP5    0x00000020  // EP5 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP4    0x00000010  // EP4 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP3    0x00000008  // EP3 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP2    0x00000004  // EP2 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP1    0x00000002  // EP1 RX Double-Packet Buffer
+                                            // Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_TXDPKTBUFDIS_EP7    0x00000080  // EP7 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP6    0x00000040  // EP6 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP5    0x00000020  // EP5 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP4    0x00000010  // EP4 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP3    0x00000008  // EP3 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP2    0x00000004  // EP2 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP1    0x00000002  // EP1 TX Double-Packet Buffer
+                                            // Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CTO register.
+//
+//*****************************************************************************
+#define USB_CTO_CCTV_M          0x0000FFFF  // Configurable Chirp Timeout Value
+#define USB_CTO_CCTV_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_HHSRTN register.
+//
+//*****************************************************************************
+#define USB_HHSRTN_HHSRTN_M     0x0000FFFF  // HIgh Speed to UTM Operating
+                                            // Delay
+#define USB_HHSRTN_HHSRTN_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_HSBT register.
+//
+//*****************************************************************************
+#define USB_HSBT_HSBT_M         0x0000000F  // High Speed Timeout Adder
+#define USB_HSBT_HSBT_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LPMATTR register.
+//
+//*****************************************************************************
+#define USB_LPMATTR_ENDPT_M     0x0000F000  // Endpoint
+#define USB_LPMATTR_RMTWAK      0x00000100  // Remote Wake
+#define USB_LPMATTR_HIRD_M      0x000000F0  // Host Initiated Resume Duration
+#define USB_LPMATTR_LS_M        0x0000000F  // Link State
+#define USB_LPMATTR_LS_L1       0x00000001  // Sleep State (L1)
+#define USB_LPMATTR_ENDPT_S     12
+#define USB_LPMATTR_HIRD_S      4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LPMCNTRL register.
+//
+//*****************************************************************************
+#define USB_LPMCNTRL_NAK        0x00000010  // LPM NAK
+#define USB_LPMCNTRL_EN_M       0x0000000C  // LPM Enable
+#define USB_LPMCNTRL_EN_NONE    0x00000000  // LPM and Extended transactions
+                                            // are not supported. In this case,
+                                            // the USB does not respond to LPM
+                                            // transactions and LPM
+                                            // transactions cause a timeout
+#define USB_LPMCNTRL_EN_EXT     0x00000004  // LPM is not supported but
+                                            // extended transactions are
+                                            // supported. In this case, the USB
+                                            // does respond to an LPM
+                                            // transaction with a STALL
+#define USB_LPMCNTRL_EN_LPMEXT  0x0000000C  // The USB supports LPM extended
+                                            // transactions. In this case, the
+                                            // USB responds with a NYET or an
+                                            // ACK as determined by the value
+                                            // of TXLPM and other conditions
+#define USB_LPMCNTRL_RES        0x00000002  // LPM Resume
+#define USB_LPMCNTRL_TXLPM      0x00000001  // Transmit LPM Transaction Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LPMIM register.
+//
+//*****************************************************************************
+#define USB_LPMIM_ERR           0x00000020  // LPM Error Interrupt Mask
+#define USB_LPMIM_RES           0x00000010  // LPM Resume Interrupt Mask
+#define USB_LPMIM_NC            0x00000008  // LPM NC Interrupt Mask
+#define USB_LPMIM_ACK           0x00000004  // LPM ACK Interrupt Mask
+#define USB_LPMIM_NY            0x00000002  // LPM NY Interrupt Mask
+#define USB_LPMIM_STALL         0x00000001  // LPM STALL Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LPMRIS register.
+//
+//*****************************************************************************
+#define USB_LPMRIS_ERR          0x00000020  // LPM Interrupt Status
+#define USB_LPMRIS_RES          0x00000010  // LPM Resume Interrupt Status
+#define USB_LPMRIS_NC           0x00000008  // LPM NC Interrupt Status
+#define USB_LPMRIS_ACK          0x00000004  // LPM ACK Interrupt Status
+#define USB_LPMRIS_NY           0x00000002  // LPM NY Interrupt Status
+#define USB_LPMRIS_LPMST        0x00000001  // LPM STALL Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LPMFADDR register.
+//
+//*****************************************************************************
+#define USB_LPMFADDR_ADDR_M     0x0000007F  // LPM Function Address
+#define USB_LPMFADDR_ADDR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPC register.
+//
+//*****************************************************************************
+#define USB_EPC_PFLTACT_M       0x00000300  // Power Fault Action
+#define USB_EPC_PFLTACT_UNCHG   0x00000000  // Unchanged
+#define USB_EPC_PFLTACT_TRIS    0x00000100  // Tristate
+#define USB_EPC_PFLTACT_LOW     0x00000200  // Low
+#define USB_EPC_PFLTACT_HIGH    0x00000300  // High
+#define USB_EPC_PFLTAEN         0x00000040  // Power Fault Action Enable
+#define USB_EPC_PFLTSEN_HIGH    0x00000020  // Power Fault Sense
+#define USB_EPC_PFLTEN          0x00000010  // Power Fault Input Enable
+#define USB_EPC_EPENDE          0x00000004  // EPEN Drive Enable
+#define USB_EPC_EPEN_M          0x00000003  // External Power Supply Enable
+                                            // Configuration
+#define USB_EPC_EPEN_LOW        0x00000000  // Power Enable Active Low
+#define USB_EPC_EPEN_HIGH       0x00000001  // Power Enable Active High
+#define USB_EPC_EPEN_VBLOW      0x00000002  // Power Enable High if VBUS Low
+                                            // (OTG only)
+#define USB_EPC_EPEN_VBHIGH     0x00000003  // Power Enable High if VBUS High
+                                            // (OTG only)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCRIS register.
+//
+//*****************************************************************************
+#define USB_EPCRIS_PF           0x00000001  // USB Power Fault Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCIM register.
+//
+//*****************************************************************************
+#define USB_EPCIM_PF            0x00000001  // USB Power Fault Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCISC register.
+//
+//*****************************************************************************
+#define USB_EPCISC_PF           0x00000001  // USB Power Fault Interrupt Status
+                                            // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRRIS register.
+//
+//*****************************************************************************
+#define USB_DRRIS_RESUME        0x00000001  // RESUME Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRIM register.
+//
+//*****************************************************************************
+#define USB_DRIM_RESUME         0x00000001  // RESUME Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRISC register.
+//
+//*****************************************************************************
+#define USB_DRISC_RESUME        0x00000001  // RESUME Interrupt Status and
+                                            // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_GPCS register.
+//
+//*****************************************************************************
+#define USB_GPCS_DEVMOD_M       0x00000007  // Device Mode
+#define USB_GPCS_DEVMOD_OTG     0x00000000  // Use USB0VBUS and USB0ID pin
+#define USB_GPCS_DEVMOD_HOST    0x00000002  // Force USB0VBUS and USB0ID low
+#define USB_GPCS_DEVMOD_DEV     0x00000003  // Force USB0VBUS and USB0ID high
+#define USB_GPCS_DEVMOD_HOSTVBUS                                              \
+                                0x00000004  // Use USB0VBUS and force USB0ID
+                                            // low
+#define USB_GPCS_DEVMOD_DEVVBUS 0x00000005  // Use USB0VBUS and force USB0ID
+                                            // high
+#define USB_GPCS_DEVMODOTG      0x00000002  // Enable Device Mode
+#define USB_GPCS_DEVMOD         0x00000001  // Device Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDC register.
+//
+//*****************************************************************************
+#define USB_VDC_VBDEN           0x00000001  // VBUS Droop Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCRIS register.
+//
+//*****************************************************************************
+#define USB_VDCRIS_VD           0x00000001  // VBUS Droop Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCIM register.
+//
+//*****************************************************************************
+#define USB_VDCIM_VD            0x00000001  // VBUS Droop Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCISC register.
+//
+//*****************************************************************************
+#define USB_VDCISC_VD           0x00000001  // VBUS Droop Interrupt Status and
+                                            // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVRIS register.
+//
+//*****************************************************************************
+#define USB_IDVRIS_ID           0x00000001  // ID Valid Detect Raw Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVIM register.
+//
+//*****************************************************************************
+#define USB_IDVIM_ID            0x00000001  // ID Valid Detect Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVISC register.
+//
+//*****************************************************************************
+#define USB_IDVISC_ID           0x00000001  // ID Valid Detect Interrupt Status
+                                            // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMASEL register.
+//
+//*****************************************************************************
+#define USB_DMASEL_DMACTX_M     0x00F00000  // DMA C TX Select
+#define USB_DMASEL_DMACRX_M     0x000F0000  // DMA C RX Select
+#define USB_DMASEL_DMABTX_M     0x0000F000  // DMA B TX Select
+#define USB_DMASEL_DMABRX_M     0x00000F00  // DMA B RX Select
+#define USB_DMASEL_DMAATX_M     0x000000F0  // DMA A TX Select
+#define USB_DMASEL_DMAARX_M     0x0000000F  // DMA A RX Select
+#define USB_DMASEL_DMACTX_S     20
+#define USB_DMASEL_DMACRX_S     16
+#define USB_DMASEL_DMABTX_S     12
+#define USB_DMASEL_DMABRX_S     8
+#define USB_DMASEL_DMAATX_S     4
+#define USB_DMASEL_DMAARX_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_PP register.
+//
+//*****************************************************************************
+#define USB_PP_ECNT_M           0x0000FF00  // Endpoint Count
+#define USB_PP_USB_M            0x000000C0  // USB Capability
+#define USB_PP_USB_DEVICE       0x00000040  // DEVICE
+#define USB_PP_USB_HOSTDEVICE   0x00000080  // HOST
+#define USB_PP_USB_OTG          0x000000C0  // OTG
+#define USB_PP_ULPI             0x00000020  // ULPI Present
+#define USB_PP_PHY              0x00000010  // PHY Present
+#define USB_PP_TYPE_M           0x0000000F  // Controller Type
+#define USB_PP_TYPE_0           0x00000000  // The first-generation USB
+                                            // controller
+#define USB_PP_TYPE_1           0x00000001  // Second-generation USB
+                                            // controller.The controller
+                                            // implemented in post Icestorm
+                                            // devices that use the 3.0 version
+                                            // of the Mentor controller
+#define USB_PP_ECNT_S           8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_PC register.
+//
+//*****************************************************************************
+#define USB_PC_ULPIEN           0x00010000  // ULPI Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CC register.
+//
+//*****************************************************************************
+#define USB_CC_CLKEN            0x00000200  // USB Clock Enable
+#define USB_CC_CSD              0x00000100  // Clock Source/Direction
+#define USB_CC_CLKDIV_M         0x0000000F  // PLL Clock Divisor
+#define USB_CC_CLKDIV_S         0
+
+#endif // __HW_USB_H__
diff --git a/os/common/ext/TivaWare/inc/hw_watchdog.h b/os/common/ext/TivaWare/inc/hw_watchdog.h
new file mode 100644
index 0000000..f15948b
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_watchdog.h
@@ -0,0 +1,122 @@
+//*****************************************************************************
+//
+// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_WATCHDOG_H__
+#define __HW_WATCHDOG_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Watchdog Timer register offsets.
+//
+//*****************************************************************************
+#define WDT_O_LOAD              0x00000000  // Watchdog Load
+#define WDT_O_VALUE             0x00000004  // Watchdog Value
+#define WDT_O_CTL               0x00000008  // Watchdog Control
+#define WDT_O_ICR               0x0000000C  // Watchdog Interrupt Clear
+#define WDT_O_RIS               0x00000010  // Watchdog Raw Interrupt Status
+#define WDT_O_MIS               0x00000014  // Watchdog Masked Interrupt Status
+#define WDT_O_TEST              0x00000418  // Watchdog Test
+#define WDT_O_LOCK              0x00000C00  // Watchdog Lock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOAD register.
+//
+//*****************************************************************************
+#define WDT_LOAD_M              0xFFFFFFFF  // Watchdog Load Value
+#define WDT_LOAD_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_VALUE register.
+//
+//*****************************************************************************
+#define WDT_VALUE_M             0xFFFFFFFF  // Watchdog Value
+#define WDT_VALUE_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_CTL register.
+//
+//*****************************************************************************
+#define WDT_CTL_WRC             0x80000000  // Write Complete
+#define WDT_CTL_INTTYPE         0x00000004  // Watchdog Interrupt Type
+#define WDT_CTL_RESEN           0x00000002  // Watchdog Reset Enable
+#define WDT_CTL_INTEN           0x00000001  // Watchdog Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_ICR register.
+//
+//*****************************************************************************
+#define WDT_ICR_M               0xFFFFFFFF  // Watchdog Interrupt Clear
+#define WDT_ICR_S               0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_RIS register.
+//
+//*****************************************************************************
+#define WDT_RIS_WDTRIS          0x00000001  // Watchdog Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_MIS register.
+//
+//*****************************************************************************
+#define WDT_MIS_WDTMIS          0x00000001  // Watchdog Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_TEST register.
+//
+//*****************************************************************************
+#define WDT_TEST_STALL          0x00000100  // Watchdog Stall Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOCK register.
+//
+//*****************************************************************************
+#define WDT_LOCK_M              0xFFFFFFFF  // Watchdog Lock
+#define WDT_LOCK_UNLOCKED       0x00000000  // Unlocked
+#define WDT_LOCK_LOCKED         0x00000001  // Locked
+#define WDT_LOCK_UNLOCK         0x1ACCE551  // Unlocks the watchdog timer
+
+#endif // __HW_WATCHDOG_H__
diff --git a/os/common/ports/MSP430X/chcore.c b/os/common/ports/MSP430X/chcore.c
index 7a8d7f2..b9001b0 100644
--- a/os/common/ports/MSP430X/chcore.c
+++ b/os/common/ports/MSP430X/chcore.c
@@ -32,6 +32,8 @@
 /* Module exported variables.                                                */

 /*===========================================================================*/

 

+bool __msp430x_in_isr;

+

 /*===========================================================================*/

 /* Module local types.                                                       */

 /*===========================================================================*/

@@ -98,6 +100,11 @@ void _port_thread_start(void) {
   asm volatile ("mov R5, R12");

   asm volatile ("call R4");

 #endif

+#if defined(_CHIBIOS_RT_CONF_)

+  chThdExit(MSG_OK);

+#endif

+#if defined(_CHIBIOS_NIL_CONF_)

   chSysHalt(0);

+#endif

 }

 /** @} */

diff --git a/os/common/ports/MSP430X/chcore.h b/os/common/ports/MSP430X/chcore.h
index 09f87c4..9e1efa8 100644
--- a/os/common/ports/MSP430X/chcore.h
+++ b/os/common/ports/MSP430X/chcore.h
@@ -28,6 +28,8 @@
 #include <msp430.h>

 #include <in430.h>

 

+extern bool __msp430x_in_isr;

+

 /*===========================================================================*/

 /* Module constants.                                                         */

 /*===========================================================================*/

@@ -225,21 +227,27 @@ struct port_context {
  * @details This macro must be inserted at the start of all IRQ handlers

  *          enabled to invoke system APIs.

  */

-#define PORT_IRQ_PROLOGUE() 

+#define PORT_IRQ_PROLOGUE() __msp430x_in_isr = true;

 

 /**

  * @brief   IRQ epilogue code.

  * @details This macro must be inserted at the end of all IRQ handlers

  *          enabled to invoke system APIs.

  */

-#define PORT_IRQ_EPILOGUE() chSchRescheduleS()

+#define PORT_IRQ_EPILOGUE() {                                               \

+  __msp430x_in_isr = false;                                                 \

+  _dbg_check_lock();                                                        \

+  if (chSchIsPreemptionRequired())                                          \

+    chSchDoReschedule();                                                    \

+  _dbg_check_unlock();                                                      \

+}

 

 /**

  * @brief   IRQ handler function declaration.

  * @note    @p id can be a function name or a vector number depending on the

  *          port implementation.

  */

-#define PORT_IRQ_HANDLER(id) __attribute__ ((interrupt(id)))                  \

+#define PORT_IRQ_HANDLER(id) __attribute__ ((interrupt(id)))                \

   void ISR_ ## id (void)

 

 /**

@@ -293,7 +301,7 @@ extern "C" {
  * @brief   Port-related initialization code.

  */

 static inline void port_init(void) {

-

+  __msp430x_in_isr = false;

 }

 

 /**

@@ -328,9 +336,7 @@ static inline bool port_irq_enabled(syssts_t sts) {
  * @retval true         running in ISR mode.

  */

 static inline bool port_is_isr_context(void) {

-  /* Efficiency would be enhanced by not doing this, 

-   * because of implementation details */

-  return __get_SR_register() & GIE;

+  return __msp430x_in_isr;

 }

 

 /**

diff --git a/os/common/ports/MSP430X/compilers/GCC/chtypes.h b/os/common/ports/MSP430X/compilers/GCC/chtypes.h
index 46a074c..b692cb7 100644
--- a/os/common/ports/MSP430X/compilers/GCC/chtypes.h
+++ b/os/common/ports/MSP430X/compilers/GCC/chtypes.h
@@ -62,6 +62,7 @@ typedef uint8_t             tprio_t;        /**< Thread priority.           */
 typedef int16_t             msg_t;          /**< Inter-thread message.      */

 typedef int32_t             eventid_t;      /**< Numeric event identifier.  */

 typedef uint8_t             eventmask_t;    /**< Mask of event identifiers. */

+typedef uint16_t            eventflags_t;   /**< Mask of event flags.       */

 typedef int16_t             cnt_t;          /**< Generic signed counter.    */

 typedef uint16_t            ucnt_t;         /**< Generic unsigned counter.  */

 

diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/NRF52832.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/NRF52832.ld
new file mode 100644
index 0000000..402995a
--- /dev/null
+++ b/os/common/startup/ARMCMx/compilers/GCC/ld/NRF52832.ld
@@ -0,0 +1,84 @@
+/*
+    Copyright (C) 2016 Stephane D'Alu
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * NRF52832 memory setup.
+ */
+MEMORY
+{
+  flash0  : org = 0x00000000, len = 512k
+  flash1  : org = 0x00000000, len = 0
+  flash2  : org = 0x00000000, len = 0
+  flash3  : org = 0x00000000, len = 0
+  flash4  : org = 0x00000000, len = 0
+  flash5  : org = 0x00000000, len = 0
+  flash6  : org = 0x00000000, len = 0
+  flash7  : org = 0x00000000, len = 0
+  ram0    : org = 0x20000000, len = 64k
+  ram1    : org = 0x00000000, len = 0
+  ram2    : org = 0x00000000, len = 0
+  ram3    : org = 0x00000000, len = 0
+  ram4    : org = 0x00000000, len = 0
+  ram5    : org = 0x00000000, len = 0
+  ram6    : org = 0x00000000, len = 0
+  ram7    : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+   and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+   of all exceptions and interrupts*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+   the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for HEAP segment.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+INCLUDE rules.ld
diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C123xC3.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C123xC3.ld
index da05e8a..9eeaf02 100644
--- a/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C123xC3.ld
+++ b/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C123xC3.ld
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C123xD5.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C123xD5.ld
index 1a1c89e..67d33ca 100644
--- a/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C123xD5.ld
+++ b/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C123xD5.ld
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C123xE6.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C123xE6.ld
index 254cb3a..83a3edd 100644
--- a/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C123xE6.ld
+++ b/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C123xE6.ld
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C123xH6.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C123xH6.ld
index f73f9ec..1affc86 100644
--- a/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C123xH6.ld
+++ b/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C123xH6.ld
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C129xKC.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C129xKC.ld
index 0463ba0..aef12ea 100644
--- a/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C129xKC.ld
+++ b/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C129xKC.ld
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C129xNC.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C129xNC.ld
index f1846ca..5e7bdb9 100644
--- a/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C129xNC.ld
+++ b/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C129xNC.ld
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf52.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf52.mk
new file mode 100644
index 0000000..693ae67
--- /dev/null
+++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf52.mk
@@ -0,0 +1,10 @@
+# List of the ChibiOS generic NRF51 startup and CMSIS files.

+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \

+             $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c

+

+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S

+

+STARTUPINC = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/NRF52832 \

+             $(CHIBIOS)/os/common/ext/CMSIS/include

+

+STARTUPLD  = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld

diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk
index 8457328..835faca 100644
--- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk
+++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk
@@ -1,12 +1,18 @@
 # List of the ChibiOS generic TM4C123x startup and CMSIS files.
-STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
-             $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
 
-STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \
+             $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
 
-STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+             $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
              $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/TM4C123x \
-             $(CHIBIOS)/os/common/ext/CMSIS/include \
-             $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include
+             $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
+             $(CHIBIOS_CONTRIB)/os/common/ext/TivaWare
 
 STARTUPLD  = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC    += $(STARTUPSRC)
+ALLINC     += $(STARTUPINC)
diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk
index e488537..ac4f76e 100644
--- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk
+++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk
@@ -1,12 +1,18 @@
 # List of the ChibiOS generic TM4C129x startup and CMSIS files.
-STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
-             $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
 
-STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \
+             $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
 
-STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+             $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
              $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/TM4C129x \
-             $(CHIBIOS)/os/common/ext/CMSIS/include \
-             $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include
+             $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
+             $(CHIBIOS_CONTRIB)/os/common/ext/TivaWare
 
 STARTUPLD  = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC    += $(STARTUPSRC)
+ALLINC     += $(STARTUPINC)
diff --git a/os/common/startup/ARMCMx/devices/NRF52832/cmparams.h b/os/common/startup/ARMCMx/devices/NRF52832/cmparams.h
new file mode 100644
index 0000000..b349291
--- /dev/null
+++ b/os/common/startup/ARMCMx/devices/NRF52832/cmparams.h
@@ -0,0 +1,82 @@
+/*

+    Copyright (C) 2016 Stephane D'Alu

+

+    This file is part of ChibiOS.

+

+    ChibiOS is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file    NRF51822/cmparams.h

+ * @brief   ARM Cortex-M4 parameters for the Nordic Semi NRF52832 family.

+ *

+ * @defgroup ARMCMx_NRF52x Nordic semiconductor NRF52x.

+ * @ingroup ARMCMx_SPECIFIC

+ * @details This file contains the Cortex-M4 specific parameters for the

+ *          NRF52x platform.

+ * @{

+ */

+

+#ifndef _CMPARAMS_H_

+#define _CMPARAMS_H_

+

+/**

+ * @brief   Cortex core model.

+ */

+#define CORTEX_MODEL            4

+

+/**

+ * @brief   Memory Protection unit presence.

+ */

+#define CORTEX_HAS_MPU          1

+

+/**

+ * @brief   Floating Point unit presence.

+ */

+#define CORTEX_HAS_FPU          1

+

+/**

+ * @brief   Number of bits in priority masks.

+ */

+#define CORTEX_PRIORITY_BITS    3

+

+/**

+ * @brief   Number of interrupt vectors.

+ * @note    This number does not include the 16 system vectors and must be

+ *          rounded to a multiple of 8.

+ */

+#define CORTEX_NUM_VECTORS      40

+

+/* The following code is not processed when the file is included from an

+   asm module.*/

+#if !defined(_FROM_ASM_)

+

+/* Including the device CMSIS header. Note, we are not using the definitions

+   from this header because we need this file to be usable also from

+   assembler source files. We verify that the info matches instead.*/

+#include "nrf52.h"

+

+#if CORTEX_MODEL != __CORTEX_M

+#error "CMSIS __CORTEX_M mismatch"

+#endif

+

+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS

+#error "CMSIS __NVIC_PRIO_BITS mismatch"

+#endif

+

+#endif /* !defined(_FROM_ASM_) */

+

+#endif /* _CMPARAMS_H_ */

+

+/** @} */

diff --git a/os/common/startup/ARMCMx/devices/TM4C123x/cmparams.h b/os/common/startup/ARMCMx/devices/TM4C123x/cmparams.h
index 933e111..7c40591 100644
--- a/os/common/startup/ARMCMx/devices/TM4C123x/cmparams.h
+++ b/os/common/startup/ARMCMx/devices/TM4C123x/cmparams.h
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -17,11 +17,26 @@
 /**
  * @file    TM4C123x/cmparams.h
  * @brief   ARM Cortex-M4 parameters for the TM4C123x.
+ *
+ * @defgroup ARMCMx_TM4C123x TM4C123x Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ *          TM4C123x platform.
  * @{
  */
 
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
+#ifndef CMPARAMS_H
+#define CMPARAMS_H
+
+/* Defines required for correct CMSIS header functioning */
+#define __MPU_PRESENT           1       /**< MPU present                     */
+#define __NVIC_PRIO_BITS        3       /**< Bits used for Priority Levels   */
+#define __Vendor_SysTickConfig  1       /**< Use different SysTick Config    */
+#define __FPU_PRESENT           1       /**< FPU present                     */
+
+/* The following two defines are needed by ChibiOS */
+#define SVCall_IRQn             -5
+#define PendSV_IRQn             -3
 
 /**
  * @brief   Cortex core model.
@@ -29,11 +44,6 @@
 #define CORTEX_MODEL            4
 
 /**
- * @brief   Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU          1
-
-/**
  * @brief   Floating Point unit presence.
  */
 #define CORTEX_HAS_FPU          1
@@ -57,56 +67,61 @@
 /* If the device type is not externally defined, for example from the Makefile,
    then a file named board.h is included. This file must contain a device
    definition compatible with the include file.*/
-#if !defined(TM4C1230C3PM) && !defined(TM4C1230D5PM) &&                       \
-  !defined(TM4C1230E6PM) && !defined(TM4C1230H6PM) &&                         \
-  !defined(TM4C1231C3PM) && !defined(TM4C1231D5PM) &&                         \
-  !defined(TM4C1231D5PZ) && !defined(TM4C1231E6PM) &&                         \
-  !defined(TM4C1231E6PZ) && !defined(TM4C1231H6PGE) &&                        \
-  !defined(TM4C1231H6PM) && !defined(TM4C1231H6PZ) &&                         \
-  !defined(TM4C1232C3PM) && !defined(TM4C1232D5PM) &&                         \
-  !defined(TM4C1232E6PM) && !defined(TM4C1232H6PM) &&                         \
-  !defined(TM4C1233C3PM) && !defined(TM4C1233D5PM) &&                         \
-  !defined(TM4C1233D5PZ) && !defined(TM4C1233E6PM) &&                         \
-  !defined(TM4C1233E6PZ) && !defined(TM4C1233H6PGE) &&                        \
-  !defined(TM4C1233H6PM) && !defined(TM4C1233H6PZ) &&                         \
-  !defined(TM4C1236D5PM) && !defined(TM4C1236E6PM) &&                         \
-  !defined(TM4C1236H6PM) && !defined(TM4C1237D5PM) &&                         \
-  !defined(TM4C1237D5PZ) && !defined(TM4C1237E6PM) &&                         \
-  !defined(TM4C1237E6PZ) && !defined(TM4C1237H6PGE) &&                        \
-  !defined(TM4C1237H6PM) && !defined(TM4C1237H6PZ) &&                         \
-  !defined(TM4C123AE6PM) && !defined(TM4C123AH6PM) &&                         \
-  !defined(TM4C123BE6PM) && !defined(TM4C123BE6PZ) &&                         \
-  !defined(TM4C123BH6PGE) && !defined(TM4C123BH6PM) &&                        \
-  !defined(TM4C123BH6PZ) && !defined(TM4C123BH6ZRB) &&                        \
-  !defined(TM4C123FE6PM) && !defined(TM4C123FH6PM) &&                         \
-  !defined(TM4C123GE6PM) && !defined(TM4C123GE6PZ) &&                         \
-  !defined(TM4C123GH6PGE) && !defined(TM4C123GH6PM) &&                        \
-  !defined(TM4C123GH6PZ) && !defined(TM4C123GH6ZRB) &&                        \
-  !defined(TM4C123GH5ZXR)
+#if !defined (PART_TM4C1230C3PM)  && !defined (PART_TM4C1230D5PM)  &&       \
+    !defined (PART_TM4C1230E6PM)  && !defined (PART_TM4C1230H6PM)  &&       \
+    !defined (PART_TM4C1231C3PM)  && !defined (PART_TM4C1231D5PM)  &&       \
+    !defined (PART_TM4C1231D5PZ)  && !defined (PART_TM4C1231E6PM)  &&       \
+    !defined (PART_TM4C1231E6PZ)  && !defined (PART_TM4C1231H6PGE) &&       \
+    !defined (PART_TM4C1231H6PM)  && !defined (PART_TM4C1231H6PZ)  &&       \
+    !defined (PART_TM4C1232C3PM)  && !defined (PART_TM4C1232D5PM)  &&       \
+    !defined (PART_TM4C1232E6PM)  && !defined (PART_TM4C1232H6PM)  &&       \
+    !defined (PART_TM4C1233C3PM)  && !defined (PART_TM4C1233D5PM)  &&       \
+    !defined (PART_TM4C1233D5PZ)  && !defined (PART_TM4C1233E6PM)  &&       \
+    !defined (PART_TM4C1233E6PZ)  && !defined (PART_TM4C1233H6PGE) &&       \
+    !defined (PART_TM4C1233H6PM)  && !defined (PART_TM4C1233H6PZ)  &&       \
+    !defined (PART_TM4C1236D5PM)  && !defined (PART_TM4C1236E6PM)  &&       \
+    !defined (PART_TM4C1236H6PM)  && !defined (PART_TM4C1237D5PM)  &&       \
+    !defined (PART_TM4C1237D5PZ)  && !defined (PART_TM4C1237E6PM)  &&       \
+    !defined (PART_TM4C1237E6PZ)  && !defined (PART_TM4C1237H6PGE) &&       \
+    !defined (PART_TM4C1237H6PM)  && !defined (PART_TM4C1237H6PZ)  &&       \
+    !defined (PART_TM4C123AE6PM)  && !defined (PART_TM4C123AH6PM)  &&       \
+    !defined (PART_TM4C123BE6PM)  && !defined (PART_TM4C123BE6PZ)  &&       \
+    !defined (PART_TM4C123BH6PGE) && !defined (PART_TM4C123BH6PM)  &&       \
+    !defined (PART_TM4C123BH6PZ)  && !defined (PART_TM4C123BH6ZRB) &&       \
+    !defined (PART_TM4C123FE6PM)  && !defined (PART_TM4C123FH6PM)  &&       \
+    !defined (PART_TM4C123GE6PM)  && !defined (PART_TM4C123GE6PZ)  &&       \
+    !defined (PART_TM4C123GH6PGE) && !defined (PART_TM4C123GH6PM)  &&       \
+    !defined (PART_TM4C123GH6PZ)  && !defined (PART_TM4C123GH6ZRB) &&       \
+    !defined (PART_TM4C123GH5ZXR)
 #include "board.h"
 #endif
 
-/* Including the device CMSIS header. Note, we are not using the definitions
-   from this header because we need this file to be usable also from
-   assembler source files. We verify that the info matches instead.*/
-#include "tm4c123x.h"
-
-#if !CORTEX_HAS_MPU != !__MPU_PRESENT
-#error "CMSIS __MPU_PRESENT mismatch"
-#endif
-
-#if !CORTEX_HAS_FPU != !__FPU_PRESENT
-#error "CMSIS __FPU_PRESENT mismatch"
-#endif
-
-#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
-#error "CMSIS __NVIC_PRIO_BITS mismatch"
+typedef int IRQn_Type;
+
+#include "core_cm4.h"
+
+/* Including the TivaWare peripheral headers.*/
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "inc/hw_timer.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_gpio.h"
+#include "inc/hw_uart.h"
+#include "inc/hw_timer.h"
+#include "inc/hw_i2c.h"
+#include "inc/hw_watchdog.h"
+#include "inc/hw_ssi.h"
+#include "inc/hw_udma.h"
+#include "inc/hw_pwm.h"
+#include "inc/hw_adc.h"
+
+#if CORTEX_NUM_VECTORS != ((((NUM_INTERRUPTS - 16) + 7) / 8) * 8)
+#error "TivaWare NUM_INTERRUPTS mismatch"
 #endif
 
 #endif /* !defined(_FROM_ASM_) */
 
-#endif /* _CMPARAMS_H_ */
+#endif /* CMPARAMS_H */
 
-/**
- * @}
- */
+/** @} */
diff --git a/os/common/startup/ARMCMx/devices/TM4C129x/cmparams.h b/os/common/startup/ARMCMx/devices/TM4C129x/cmparams.h
index 1d2661d..7bf68a0 100644
--- a/os/common/startup/ARMCMx/devices/TM4C129x/cmparams.h
+++ b/os/common/startup/ARMCMx/devices/TM4C129x/cmparams.h
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -17,11 +17,26 @@
 /**
  * @file    TM4C129x/cmparams.h
  * @brief   ARM Cortex-M4 parameters for the TM4C129x.
+ *
+ * @defgroup ARMCMx_TM4C129x TM4C129x Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ *          TM4C129x platform.
  * @{
  */
 
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
+#ifndef CMPARAMS_H
+#define CMPARAMS_H
+
+/* Defines required for correct CMSIS header functioning */
+#define __MPU_PRESENT           1       /**< MPU present                     */
+#define __NVIC_PRIO_BITS        3       /**< Bits used for Priority Levels   */
+#define __Vendor_SysTickConfig  1       /**< Use different SysTick Config    */
+#define __FPU_PRESENT           1       /**< FPU present                     */
+
+/* The following two defines are needed by ChibiOS */
+#define SVCall_IRQn             -5
+#define PendSV_IRQn             -3
 
 /**
  * @brief   Cortex core model.
@@ -29,11 +44,6 @@
 #define CORTEX_MODEL            4
 
 /**
- * @brief   Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU          1
-
-/**
  * @brief   Floating Point unit presence.
  */
 #define CORTEX_HAS_FPU          1
@@ -48,7 +58,7 @@
  * @note    This number does not include the 16 system vectors and must be
  *          rounded to a multiple of 8.
  */
-#define CORTEX_NUM_VECTORS      112
+#define CORTEX_NUM_VECTORS      120
 
 /* The following code is not processed when the file is included from an
    asm module.*/
@@ -57,40 +67,46 @@
 /* If the device type is not externally defined, for example from the Makefile,
    then a file named board.h is included. This file must contain a device
    definition compatible with the include file.*/
-#if !defined(TM4C1290NCPDT) && !defined(TM4C1290NCZAD)                        \
-  && !defined(TM4C1292NCPDT) && !defined(TM4C1292NCZAD)                       \
-  && !defined(TM4C1294KCPDT) && !defined(TM4C1294NCPDT)                       \
-  && !defined(TM4C1294NCZAD) && !defined(TM4C1297NCZAD)                       \
-  && !defined(TM4C1299KCZAD) && !defined(TM4C1299NCZAD)                       \
-  && !defined(TM4C129CNCPDT) && !defined(TM4C129CNCZAD)                       \
-  && !defined(TM4C129DNCPDT) && !defined(TM4C129DNCZAD)                       \
-  && !defined(TM4C129EKCPDT) && !defined(TM4C129ENCPDT)                       \
-  && !defined(TM4C129ENCZAD) && !defined(TM4C129LNCZAD)                       \
-  && !defined(TM4C129XKCZAD) && !defined(TM4C129XNCZAD)
+#if !defined (PART_TM4C1290NCPDT) && !defined (PART_TM4C1290NCZAD) &&       \
+    !defined (PART_TM4C1292NCPDT) && !defined (PART_TM4C1292NCZAD) &&       \
+    !defined (PART_TM4C1294KCPDT) && !defined (PART_TM4C1294NCPDT) &&       \
+    !defined (PART_TM4C1294NCZAD) && !defined (PART_TM4C1297NCZAD) &&       \
+    !defined (PART_TM4C1299KCZAD) && !defined (PART_TM4C1299NCZAD) &&       \
+    !defined (PART_TM4C129CNCPDT) && !defined (PART_TM4C129CNCZAD) &&       \
+    !defined (PART_TM4C129DNCPDT) && !defined (PART_TM4C129DNCZAD) &&       \
+    !defined (PART_TM4C129EKCPDT) && !defined (PART_TM4C129ENCPDT) &&       \
+    !defined (PART_TM4C129ENCZAD) && !defined (PART_TM4C129LNCZAD) &&       \
+    !defined (PART_TM4C129XKCZAD) && !defined (PART_TM4C129XNCZAD)
 #include "board.h"
 #endif
 
-/* Including the device CMSIS header. Note, we are not using the definitions
-   from this header because we need this file to be usable also from
-   assembler source files. We verify that the info matches instead.*/
-#include "tm4c129x.h"
-
-#if !CORTEX_HAS_MPU != !__MPU_PRESENT
-#error "CMSIS __MPU_PRESENT mismatch"
-#endif
-
-#if !CORTEX_HAS_FPU != !__FPU_PRESENT
-#error "CMSIS __FPU_PRESENT mismatch"
-#endif
-
-#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
-#error "CMSIS __NVIC_PRIO_BITS mismatch"
+typedef int IRQn_Type;
+
+#include "core_cm4.h"
+
+/* Including the TivaWare peripheral headers.*/
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "inc/hw_timer.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_gpio.h"
+#include "inc/hw_uart.h"
+#include "inc/hw_timer.h"
+#include "inc/hw_emac.h"
+#include "inc/hw_i2c.h"
+#include "inc/hw_watchdog.h"
+#include "inc/hw_ssi.h"
+#include "inc/hw_udma.h"
+#include "inc/hw_pwm.h"
+#include "inc/hw_adc.h"
+
+#if CORTEX_NUM_VECTORS != ((((NUM_INTERRUPTS - 16) + 7) / 8) * 8)
+#error "TivaWare NUM_INTERRUPTS mismatch"
 #endif
 
 #endif /* !defined(_FROM_ASM_) */
 
-#endif /* _CMPARAMS_H_ */
+#endif /* CMPARAMS_H */
 
-/**
- * @}
- */
+/** @} */
diff --git a/os/common/startup/MSP430X/compilers/GCC/ld/msp430fr5969_symbols.ld b/os/common/startup/MSP430X/compilers/GCC/ld/msp430fr5969_symbols.ld
new file mode 100644
index 0000000..b9ee725
--- /dev/null
+++ b/os/common/startup/MSP430X/compilers/GCC/ld/msp430fr5969_symbols.ld
@@ -0,0 +1,928 @@
+/* ============================================================================ */
+/* Copyright (c) 2016, Texas Instruments Incorporated                           */
+/*  All rights reserved.                                                        */
+/*                                                                              */
+/*  Redistribution and use in source and binary forms, with or without          */
+/*  modification, are permitted provided that the following conditions          */
+/*  are met:                                                                    */
+/*                                                                              */
+/*  *  Redistributions of source code must retain the above copyright           */
+/*     notice, this list of conditions and the following disclaimer.            */
+/*                                                                              */
+/*  *  Redistributions in binary form must reproduce the above copyright        */
+/*     notice, this list of conditions and the following disclaimer in the      */
+/*     documentation and/or other materials provided with the distribution.     */
+/*                                                                              */
+/*  *  Neither the name of Texas Instruments Incorporated nor the names of      */
+/*     its contributors may be used to endorse or promote products derived      */
+/*     from this software without specific prior written permission.            */
+/*                                                                              */
+/*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */
+/*  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,       */
+/*  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR      */
+/*  PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR            */
+/*  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,       */
+/*  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,         */
+/*  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */
+/*  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,    */
+/*  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR     */
+/*  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,              */
+/*  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                          */
+/* ============================================================================ */
+
+/* This file supports MSP430FR5969 devices. */
+/* Version: 1.198 */
+
+/************************************************************
+* STANDARD BITS
+************************************************************/
+/************************************************************
+* STATUS REGISTER BITS
+************************************************************/
+/************************************************************
+* PERIPHERAL FILE MAP
+************************************************************/
+/************************************************************
+* ADC12_B
+************************************************************/
+PROVIDE(ADC12CTL0          = 0x0800);
+PROVIDE(ADC12CTL0_L        = 0x0800);
+PROVIDE(ADC12CTL0_H        = 0x0801);
+PROVIDE(ADC12CTL1          = 0x0802);
+PROVIDE(ADC12CTL1_L        = 0x0802);
+PROVIDE(ADC12CTL1_H        = 0x0803);
+PROVIDE(ADC12CTL2          = 0x0804);
+PROVIDE(ADC12CTL2_L        = 0x0804);
+PROVIDE(ADC12CTL2_H        = 0x0805);
+PROVIDE(ADC12CTL3          = 0x0806);
+PROVIDE(ADC12CTL3_L        = 0x0806);
+PROVIDE(ADC12CTL3_H        = 0x0807);
+PROVIDE(ADC12LO            = 0x0808);
+PROVIDE(ADC12LO_L          = 0x0808);
+PROVIDE(ADC12LO_H          = 0x0809);
+PROVIDE(ADC12HI            = 0x080A);
+PROVIDE(ADC12HI_L          = 0x080A);
+PROVIDE(ADC12HI_H          = 0x080B);
+PROVIDE(ADC12IFGR0         = 0x080C);
+PROVIDE(ADC12IFGR0_L       = 0x080C);
+PROVIDE(ADC12IFGR0_H       = 0x080D);
+PROVIDE(ADC12IFGR1         = 0x080E);
+PROVIDE(ADC12IFGR1_L       = 0x080E);
+PROVIDE(ADC12IFGR1_H       = 0x080F);
+PROVIDE(ADC12IFGR2         = 0x0810);
+PROVIDE(ADC12IFGR2_L       = 0x0810);
+PROVIDE(ADC12IFGR2_H       = 0x0811);
+PROVIDE(ADC12IER0          = 0x0812);
+PROVIDE(ADC12IER0_L        = 0x0812);
+PROVIDE(ADC12IER0_H        = 0x0813);
+PROVIDE(ADC12IER1          = 0x0814);
+PROVIDE(ADC12IER1_L        = 0x0814);
+PROVIDE(ADC12IER1_H        = 0x0815);
+PROVIDE(ADC12IER2          = 0x0816);
+PROVIDE(ADC12IER2_L        = 0x0816);
+PROVIDE(ADC12IER2_H        = 0x0817);
+PROVIDE(ADC12IV            = 0x0818);
+PROVIDE(ADC12IV_L          = 0x0818);
+PROVIDE(ADC12IV_H          = 0x0819);
+PROVIDE(ADC12MCTL0         = 0x0820);
+PROVIDE(ADC12MCTL0_L       = 0x0820);
+PROVIDE(ADC12MCTL0_H       = 0x0821);
+PROVIDE(ADC12MCTL1         = 0x0822);
+PROVIDE(ADC12MCTL1_L       = 0x0822);
+PROVIDE(ADC12MCTL1_H       = 0x0823);
+PROVIDE(ADC12MCTL2         = 0x0824);
+PROVIDE(ADC12MCTL2_L       = 0x0824);
+PROVIDE(ADC12MCTL2_H       = 0x0825);
+PROVIDE(ADC12MCTL3         = 0x0826);
+PROVIDE(ADC12MCTL3_L       = 0x0826);
+PROVIDE(ADC12MCTL3_H       = 0x0827);
+PROVIDE(ADC12MCTL4         = 0x0828);
+PROVIDE(ADC12MCTL4_L       = 0x0828);
+PROVIDE(ADC12MCTL4_H       = 0x0829);
+PROVIDE(ADC12MCTL5         = 0x082A);
+PROVIDE(ADC12MCTL5_L       = 0x082A);
+PROVIDE(ADC12MCTL5_H       = 0x082B);
+PROVIDE(ADC12MCTL6         = 0x082C);
+PROVIDE(ADC12MCTL6_L       = 0x082C);
+PROVIDE(ADC12MCTL6_H       = 0x082D);
+PROVIDE(ADC12MCTL7         = 0x082E);
+PROVIDE(ADC12MCTL7_L       = 0x082E);
+PROVIDE(ADC12MCTL7_H       = 0x082F);
+PROVIDE(ADC12MCTL8         = 0x0830);
+PROVIDE(ADC12MCTL8_L       = 0x0830);
+PROVIDE(ADC12MCTL8_H       = 0x0831);
+PROVIDE(ADC12MCTL9         = 0x0832);
+PROVIDE(ADC12MCTL9_L       = 0x0832);
+PROVIDE(ADC12MCTL9_H       = 0x0833);
+PROVIDE(ADC12MCTL10        = 0x0834);
+PROVIDE(ADC12MCTL10_L      = 0x0834);
+PROVIDE(ADC12MCTL10_H      = 0x0835);
+PROVIDE(ADC12MCTL11        = 0x0836);
+PROVIDE(ADC12MCTL11_L      = 0x0836);
+PROVIDE(ADC12MCTL11_H      = 0x0837);
+PROVIDE(ADC12MCTL12        = 0x0838);
+PROVIDE(ADC12MCTL12_L      = 0x0838);
+PROVIDE(ADC12MCTL12_H      = 0x0839);
+PROVIDE(ADC12MCTL13        = 0x083A);
+PROVIDE(ADC12MCTL13_L      = 0x083A);
+PROVIDE(ADC12MCTL13_H      = 0x083B);
+PROVIDE(ADC12MCTL14        = 0x083C);
+PROVIDE(ADC12MCTL14_L      = 0x083C);
+PROVIDE(ADC12MCTL14_H      = 0x083D);
+PROVIDE(ADC12MCTL15        = 0x083E);
+PROVIDE(ADC12MCTL15_L      = 0x083E);
+PROVIDE(ADC12MCTL15_H      = 0x083F);
+PROVIDE(ADC12MCTL16        = 0x0840);
+PROVIDE(ADC12MCTL16_L      = 0x0840);
+PROVIDE(ADC12MCTL16_H      = 0x0841);
+PROVIDE(ADC12MCTL17        = 0x0842);
+PROVIDE(ADC12MCTL17_L      = 0x0842);
+PROVIDE(ADC12MCTL17_H      = 0x0843);
+PROVIDE(ADC12MCTL18        = 0x0844);
+PROVIDE(ADC12MCTL18_L      = 0x0844);
+PROVIDE(ADC12MCTL18_H      = 0x0845);
+PROVIDE(ADC12MCTL19        = 0x0846);
+PROVIDE(ADC12MCTL19_L      = 0x0846);
+PROVIDE(ADC12MCTL19_H      = 0x0847);
+PROVIDE(ADC12MCTL20        = 0x0848);
+PROVIDE(ADC12MCTL20_L      = 0x0848);
+PROVIDE(ADC12MCTL20_H      = 0x0849);
+PROVIDE(ADC12MCTL21        = 0x084A);
+PROVIDE(ADC12MCTL21_L      = 0x084A);
+PROVIDE(ADC12MCTL21_H      = 0x084B);
+PROVIDE(ADC12MCTL22        = 0x084C);
+PROVIDE(ADC12MCTL22_L      = 0x084C);
+PROVIDE(ADC12MCTL22_H      = 0x084D);
+PROVIDE(ADC12MCTL23        = 0x084E);
+PROVIDE(ADC12MCTL23_L      = 0x084E);
+PROVIDE(ADC12MCTL23_H      = 0x084F);
+PROVIDE(ADC12MCTL24        = 0x0850);
+PROVIDE(ADC12MCTL24_L      = 0x0850);
+PROVIDE(ADC12MCTL24_H      = 0x0851);
+PROVIDE(ADC12MCTL25        = 0x0852);
+PROVIDE(ADC12MCTL25_L      = 0x0852);
+PROVIDE(ADC12MCTL25_H      = 0x0853);
+PROVIDE(ADC12MCTL26        = 0x0854);
+PROVIDE(ADC12MCTL26_L      = 0x0854);
+PROVIDE(ADC12MCTL26_H      = 0x0855);
+PROVIDE(ADC12MCTL27        = 0x0856);
+PROVIDE(ADC12MCTL27_L      = 0x0856);
+PROVIDE(ADC12MCTL27_H      = 0x0857);
+PROVIDE(ADC12MCTL28        = 0x0858);
+PROVIDE(ADC12MCTL28_L      = 0x0858);
+PROVIDE(ADC12MCTL28_H      = 0x0859);
+PROVIDE(ADC12MCTL29        = 0x085A);
+PROVIDE(ADC12MCTL29_L      = 0x085A);
+PROVIDE(ADC12MCTL29_H      = 0x085B);
+PROVIDE(ADC12MCTL30        = 0x085C);
+PROVIDE(ADC12MCTL30_L      = 0x085C);
+PROVIDE(ADC12MCTL30_H      = 0x085D);
+PROVIDE(ADC12MCTL31        = 0x085E);
+PROVIDE(ADC12MCTL31_L      = 0x085E);
+PROVIDE(ADC12MCTL31_H      = 0x085F);
+PROVIDE(ADC12MEM0          = 0x0860);
+PROVIDE(ADC12MEM0_L        = 0x0860);
+PROVIDE(ADC12MEM0_H        = 0x0861);
+PROVIDE(ADC12MEM1          = 0x0862);
+PROVIDE(ADC12MEM1_L        = 0x0862);
+PROVIDE(ADC12MEM1_H        = 0x0863);
+PROVIDE(ADC12MEM2          = 0x0864);
+PROVIDE(ADC12MEM2_L        = 0x0864);
+PROVIDE(ADC12MEM2_H        = 0x0865);
+PROVIDE(ADC12MEM3          = 0x0866);
+PROVIDE(ADC12MEM3_L        = 0x0866);
+PROVIDE(ADC12MEM3_H        = 0x0867);
+PROVIDE(ADC12MEM4          = 0x0868);
+PROVIDE(ADC12MEM4_L        = 0x0868);
+PROVIDE(ADC12MEM4_H        = 0x0869);
+PROVIDE(ADC12MEM5          = 0x086A);
+PROVIDE(ADC12MEM5_L        = 0x086A);
+PROVIDE(ADC12MEM5_H        = 0x086B);
+PROVIDE(ADC12MEM6          = 0x086C);
+PROVIDE(ADC12MEM6_L        = 0x086C);
+PROVIDE(ADC12MEM6_H        = 0x086D);
+PROVIDE(ADC12MEM7          = 0x086E);
+PROVIDE(ADC12MEM7_L        = 0x086E);
+PROVIDE(ADC12MEM7_H        = 0x086F);
+PROVIDE(ADC12MEM8          = 0x0870);
+PROVIDE(ADC12MEM8_L        = 0x0870);
+PROVIDE(ADC12MEM8_H        = 0x0871);
+PROVIDE(ADC12MEM9          = 0x0872);
+PROVIDE(ADC12MEM9_L        = 0x0872);
+PROVIDE(ADC12MEM9_H        = 0x0873);
+PROVIDE(ADC12MEM10         = 0x0874);
+PROVIDE(ADC12MEM10_L       = 0x0874);
+PROVIDE(ADC12MEM10_H       = 0x0875);
+PROVIDE(ADC12MEM11         = 0x0876);
+PROVIDE(ADC12MEM11_L       = 0x0876);
+PROVIDE(ADC12MEM11_H       = 0x0877);
+PROVIDE(ADC12MEM12         = 0x0878);
+PROVIDE(ADC12MEM12_L       = 0x0878);
+PROVIDE(ADC12MEM12_H       = 0x0879);
+PROVIDE(ADC12MEM13         = 0x087A);
+PROVIDE(ADC12MEM13_L       = 0x087A);
+PROVIDE(ADC12MEM13_H       = 0x087B);
+PROVIDE(ADC12MEM14         = 0x087C);
+PROVIDE(ADC12MEM14_L       = 0x087C);
+PROVIDE(ADC12MEM14_H       = 0x087D);
+PROVIDE(ADC12MEM15         = 0x087E);
+PROVIDE(ADC12MEM15_L       = 0x087E);
+PROVIDE(ADC12MEM15_H       = 0x087F);
+PROVIDE(ADC12MEM16         = 0x0880);
+PROVIDE(ADC12MEM16_L       = 0x0880);
+PROVIDE(ADC12MEM16_H       = 0x0881);
+PROVIDE(ADC12MEM17         = 0x0882);
+PROVIDE(ADC12MEM17_L       = 0x0882);
+PROVIDE(ADC12MEM17_H       = 0x0883);
+PROVIDE(ADC12MEM18         = 0x0884);
+PROVIDE(ADC12MEM18_L       = 0x0884);
+PROVIDE(ADC12MEM18_H       = 0x0885);
+PROVIDE(ADC12MEM19         = 0x0886);
+PROVIDE(ADC12MEM19_L       = 0x0886);
+PROVIDE(ADC12MEM19_H       = 0x0887);
+PROVIDE(ADC12MEM20         = 0x0888);
+PROVIDE(ADC12MEM20_L       = 0x0888);
+PROVIDE(ADC12MEM20_H       = 0x0889);
+PROVIDE(ADC12MEM21         = 0x088A);
+PROVIDE(ADC12MEM21_L       = 0x088A);
+PROVIDE(ADC12MEM21_H       = 0x088B);
+PROVIDE(ADC12MEM22         = 0x088C);
+PROVIDE(ADC12MEM22_L       = 0x088C);
+PROVIDE(ADC12MEM22_H       = 0x088D);
+PROVIDE(ADC12MEM23         = 0x088E);
+PROVIDE(ADC12MEM23_L       = 0x088E);
+PROVIDE(ADC12MEM23_H       = 0x088F);
+PROVIDE(ADC12MEM24         = 0x0890);
+PROVIDE(ADC12MEM24_L       = 0x0890);
+PROVIDE(ADC12MEM24_H       = 0x0891);
+PROVIDE(ADC12MEM25         = 0x0892);
+PROVIDE(ADC12MEM25_L       = 0x0892);
+PROVIDE(ADC12MEM25_H       = 0x0893);
+PROVIDE(ADC12MEM26         = 0x0894);
+PROVIDE(ADC12MEM26_L       = 0x0894);
+PROVIDE(ADC12MEM26_H       = 0x0895);
+PROVIDE(ADC12MEM27         = 0x0896);
+PROVIDE(ADC12MEM27_L       = 0x0896);
+PROVIDE(ADC12MEM27_H       = 0x0897);
+PROVIDE(ADC12MEM28         = 0x0898);
+PROVIDE(ADC12MEM28_L       = 0x0898);
+PROVIDE(ADC12MEM28_H       = 0x0899);
+PROVIDE(ADC12MEM29         = 0x089A);
+PROVIDE(ADC12MEM29_L       = 0x089A);
+PROVIDE(ADC12MEM29_H       = 0x089B);
+PROVIDE(ADC12MEM30         = 0x089C);
+PROVIDE(ADC12MEM30_L       = 0x089C);
+PROVIDE(ADC12MEM30_H       = 0x089D);
+PROVIDE(ADC12MEM31         = 0x089E);
+PROVIDE(ADC12MEM31_L       = 0x089E);
+PROVIDE(ADC12MEM31_H       = 0x089F);
+/************************************************************
+* AES256 Accelerator
+************************************************************/
+PROVIDE(AESACTL0           = 0x09C0);
+PROVIDE(AESACTL0_L         = 0x09C0);
+PROVIDE(AESACTL0_H         = 0x09C1);
+PROVIDE(AESACTL1           = 0x09C2);
+PROVIDE(AESACTL1_L         = 0x09C2);
+PROVIDE(AESACTL1_H         = 0x09C3);
+PROVIDE(AESASTAT           = 0x09C4);
+PROVIDE(AESASTAT_L         = 0x09C4);
+PROVIDE(AESASTAT_H         = 0x09C5);
+PROVIDE(AESAKEY            = 0x09C6);
+PROVIDE(AESAKEY_L          = 0x09C6);
+PROVIDE(AESAKEY_H          = 0x09C7);
+PROVIDE(AESADIN            = 0x09C8);
+PROVIDE(AESADIN_L          = 0x09C8);
+PROVIDE(AESADIN_H          = 0x09C9);
+PROVIDE(AESADOUT           = 0x09CA);
+PROVIDE(AESADOUT_L         = 0x09CA);
+PROVIDE(AESADOUT_H         = 0x09CB);
+PROVIDE(AESAXDIN           = 0x09CC);
+PROVIDE(AESAXDIN_L         = 0x09CC);
+PROVIDE(AESAXDIN_H         = 0x09CD);
+PROVIDE(AESAXIN            = 0x09CE);
+PROVIDE(AESAXIN_L          = 0x09CE);
+PROVIDE(AESAXIN_H          = 0x09CF);
+/************************************************************
+* Capacitive_Touch_IO 0
+************************************************************/
+PROVIDE(CAPTIO0CTL         = 0x043E);
+PROVIDE(CAPTIO0CTL_L       = 0x043E);
+PROVIDE(CAPTIO0CTL_H       = 0x043F);
+/************************************************************
+* Capacitive_Touch_IO 1
+************************************************************/
+PROVIDE(CAPTIO1CTL         = 0x047E);
+PROVIDE(CAPTIO1CTL_L       = 0x047E);
+PROVIDE(CAPTIO1CTL_H       = 0x047F);
+/************************************************************
+* Comparator E
+************************************************************/
+PROVIDE(CECTL0             = 0x08C0);
+PROVIDE(CECTL0_L           = 0x08C0);
+PROVIDE(CECTL0_H           = 0x08C1);
+PROVIDE(CECTL1             = 0x08C2);
+PROVIDE(CECTL1_L           = 0x08C2);
+PROVIDE(CECTL1_H           = 0x08C3);
+PROVIDE(CECTL2             = 0x08C4);
+PROVIDE(CECTL2_L           = 0x08C4);
+PROVIDE(CECTL2_H           = 0x08C5);
+PROVIDE(CECTL3             = 0x08C6);
+PROVIDE(CECTL3_L           = 0x08C6);
+PROVIDE(CECTL3_H           = 0x08C7);
+PROVIDE(CEINT              = 0x08CC);
+PROVIDE(CEINT_L            = 0x08CC);
+PROVIDE(CEINT_H            = 0x08CD);
+PROVIDE(CEIV               = 0x08CE);
+PROVIDE(CEIV_L             = 0x08CE);
+PROVIDE(CEIV_H             = 0x08CF);
+/*************************************************************
+* CRC Module
+*************************************************************/
+PROVIDE(CRCDI              = 0x0150);
+PROVIDE(CRCDI_L            = 0x0150);
+PROVIDE(CRCDI_H            = 0x0151);
+PROVIDE(CRCDIRB            = 0x0152);
+PROVIDE(CRCDIRB_L          = 0x0152);
+PROVIDE(CRCDIRB_H          = 0x0153);
+PROVIDE(CRCINIRES          = 0x0154);
+PROVIDE(CRCINIRES_L        = 0x0154);
+PROVIDE(CRCINIRES_H        = 0x0155);
+PROVIDE(CRCRESR            = 0x0156);
+PROVIDE(CRCRESR_L          = 0x0156);
+PROVIDE(CRCRESR_H          = 0x0157);
+/************************************************************
+* CLOCK SYSTEM
+************************************************************/
+PROVIDE(CSCTL0             = 0x0160);
+PROVIDE(CSCTL0_L           = 0x0160);
+PROVIDE(CSCTL0_H           = 0x0161);
+PROVIDE(CSCTL1             = 0x0162);
+PROVIDE(CSCTL1_L           = 0x0162);
+PROVIDE(CSCTL1_H           = 0x0163);
+PROVIDE(CSCTL2             = 0x0164);
+PROVIDE(CSCTL2_L           = 0x0164);
+PROVIDE(CSCTL2_H           = 0x0165);
+PROVIDE(CSCTL3             = 0x0166);
+PROVIDE(CSCTL3_L           = 0x0166);
+PROVIDE(CSCTL3_H           = 0x0167);
+PROVIDE(CSCTL4             = 0x0168);
+PROVIDE(CSCTL4_L           = 0x0168);
+PROVIDE(CSCTL4_H           = 0x0169);
+PROVIDE(CSCTL5             = 0x016A);
+PROVIDE(CSCTL5_L           = 0x016A);
+PROVIDE(CSCTL5_H           = 0x016B);
+PROVIDE(CSCTL6             = 0x016C);
+PROVIDE(CSCTL6_L           = 0x016C);
+PROVIDE(CSCTL6_H           = 0x016D);
+/************************************************************
+* DMA_X
+************************************************************/
+PROVIDE(DMACTL0            = 0x0500);
+PROVIDE(DMACTL0_L          = 0x0500);
+PROVIDE(DMACTL0_H          = 0x0501);
+PROVIDE(DMACTL1            = 0x0502);
+PROVIDE(DMACTL1_L          = 0x0502);
+PROVIDE(DMACTL1_H          = 0x0503);
+PROVIDE(DMACTL2            = 0x0504);
+PROVIDE(DMACTL2_L          = 0x0504);
+PROVIDE(DMACTL2_H          = 0x0505);
+PROVIDE(DMACTL3            = 0x0506);
+PROVIDE(DMACTL3_L          = 0x0506);
+PROVIDE(DMACTL3_H          = 0x0507);
+PROVIDE(DMACTL4            = 0x0508);
+PROVIDE(DMACTL4_L          = 0x0508);
+PROVIDE(DMACTL4_H          = 0x0509);
+PROVIDE(DMAIV              = 0x050E);
+PROVIDE(DMAIV_L            = 0x050E);
+PROVIDE(DMAIV_H            = 0x050F);
+PROVIDE(DMA0CTL            = 0x0510);
+PROVIDE(DMA0CTL_L          = 0x0510);
+PROVIDE(DMA0CTL_H          = 0x0511);
+PROVIDE(DMA0SA             = 0x0512);
+PROVIDE(DMA0SAL            = 0x0512);
+PROVIDE(DMA0DA             = 0x0516);
+PROVIDE(DMA0DAL            = 0x0516);
+PROVIDE(DMA0SZ             = 0x051A);
+PROVIDE(DMA1CTL            = 0x0520);
+PROVIDE(DMA1CTL_L          = 0x0520);
+PROVIDE(DMA1CTL_H          = 0x0521);
+PROVIDE(DMA1SA             = 0x0522);
+PROVIDE(DMA1SAL            = 0x0522);
+PROVIDE(DMA1DA             = 0x0526);
+PROVIDE(DMA1DAL            = 0x0526);
+PROVIDE(DMA1SZ             = 0x052A);
+PROVIDE(DMA2CTL            = 0x0530);
+PROVIDE(DMA2CTL_L          = 0x0530);
+PROVIDE(DMA2CTL_H          = 0x0531);
+PROVIDE(DMA2SA             = 0x0532);
+PROVIDE(DMA2SAL            = 0x0532);
+PROVIDE(DMA2DA             = 0x0536);
+PROVIDE(DMA2DAL            = 0x0536);
+PROVIDE(DMA2SZ             = 0x053A);
+/*************************************************************
+* FRAM Memory
+*************************************************************/
+PROVIDE(FRCTL0             = 0x0140);
+PROVIDE(FRCTL0_L           = 0x0140);
+PROVIDE(FRCTL0_H           = 0x0141);
+PROVIDE(GCCTL0             = 0x0144);
+PROVIDE(GCCTL0_L           = 0x0144);
+PROVIDE(GCCTL0_H           = 0x0145);
+PROVIDE(GCCTL1             = 0x0146);
+PROVIDE(GCCTL1_L           = 0x0146);
+PROVIDE(GCCTL1_H           = 0x0147);
+/************************************************************
+* Memory Protection Unit
+************************************************************/
+PROVIDE(MPUCTL0            = 0x05A0);
+PROVIDE(MPUCTL0_L          = 0x05A0);
+PROVIDE(MPUCTL0_H          = 0x05A1);
+PROVIDE(MPUCTL1            = 0x05A2);
+PROVIDE(MPUCTL1_L          = 0x05A2);
+PROVIDE(MPUCTL1_H          = 0x05A3);
+PROVIDE(MPUSEGB2           = 0x05A4);
+PROVIDE(MPUSEGB2_L         = 0x05A4);
+PROVIDE(MPUSEGB2_H         = 0x05A5);
+PROVIDE(MPUSEGB1           = 0x05A6);
+PROVIDE(MPUSEGB1_L         = 0x05A6);
+PROVIDE(MPUSEGB1_H         = 0x05A7);
+PROVIDE(MPUSAM             = 0x05A8);
+PROVIDE(MPUSAM_L           = 0x05A8);
+PROVIDE(MPUSAM_H           = 0x05A9);
+PROVIDE(MPUIPC0            = 0x05AA);
+PROVIDE(MPUIPC0_L          = 0x05AA);
+PROVIDE(MPUIPC0_H          = 0x05AB);
+PROVIDE(MPUIPSEGB2         = 0x05AC);
+PROVIDE(MPUIPSEGB2_L       = 0x05AC);
+PROVIDE(MPUIPSEGB2_H       = 0x05AD);
+PROVIDE(MPUIPSEGB1         = 0x05AE);
+PROVIDE(MPUIPSEGB1_L       = 0x05AE);
+PROVIDE(MPUIPSEGB1_H       = 0x05AF);
+/************************************************************
+* HARDWARE MULTIPLIER 32Bit
+************************************************************/
+PROVIDE(MPY                = 0x04C0);
+PROVIDE(MPY_L              = 0x04C0);
+PROVIDE(MPY_H              = 0x04C1);
+PROVIDE(MPYS               = 0x04C2);
+PROVIDE(MPYS_L             = 0x04C2);
+PROVIDE(MPYS_H             = 0x04C3);
+PROVIDE(MAC                = 0x04C4);
+PROVIDE(MAC_L              = 0x04C4);
+PROVIDE(MAC_H              = 0x04C5);
+PROVIDE(MACS               = 0x04C6);
+PROVIDE(MACS_L             = 0x04C6);
+PROVIDE(MACS_H             = 0x04C7);
+PROVIDE(OP2                = 0x04C8);
+PROVIDE(OP2_L              = 0x04C8);
+PROVIDE(OP2_H              = 0x04C9);
+PROVIDE(RESLO              = 0x04CA);
+PROVIDE(RESLO_L            = 0x04CA);
+PROVIDE(RESLO_H            = 0x04CB);
+PROVIDE(RESHI              = 0x04CC);
+PROVIDE(RESHI_L            = 0x04CC);
+PROVIDE(RESHI_H            = 0x04CD);
+PROVIDE(SUMEXT             = 0x04CE);
+PROVIDE(SUMEXT_L           = 0x04CE);
+PROVIDE(SUMEXT_H           = 0x04CF);
+PROVIDE(MPY32L             = 0x04D0);
+PROVIDE(MPY32L_L           = 0x04D0);
+PROVIDE(MPY32L_H           = 0x04D1);
+PROVIDE(MPY32H             = 0x04D2);
+PROVIDE(MPY32H_L           = 0x04D2);
+PROVIDE(MPY32H_H           = 0x04D3);
+PROVIDE(MPYS32L            = 0x04D4);
+PROVIDE(MPYS32L_L          = 0x04D4);
+PROVIDE(MPYS32L_H          = 0x04D5);
+PROVIDE(MPYS32H            = 0x04D6);
+PROVIDE(MPYS32H_L          = 0x04D6);
+PROVIDE(MPYS32H_H          = 0x04D7);
+PROVIDE(MAC32L             = 0x04D8);
+PROVIDE(MAC32L_L           = 0x04D8);
+PROVIDE(MAC32L_H           = 0x04D9);
+PROVIDE(MAC32H             = 0x04DA);
+PROVIDE(MAC32H_L           = 0x04DA);
+PROVIDE(MAC32H_H           = 0x04DB);
+PROVIDE(MACS32L            = 0x04DC);
+PROVIDE(MACS32L_L          = 0x04DC);
+PROVIDE(MACS32L_H          = 0x04DD);
+PROVIDE(MACS32H            = 0x04DE);
+PROVIDE(MACS32H_L          = 0x04DE);
+PROVIDE(MACS32H_H          = 0x04DF);
+PROVIDE(OP2L               = 0x04E0);
+PROVIDE(OP2L_L             = 0x04E0);
+PROVIDE(OP2L_H             = 0x04E1);
+PROVIDE(OP2H               = 0x04E2);
+PROVIDE(OP2H_L             = 0x04E2);
+PROVIDE(OP2H_H             = 0x04E3);
+PROVIDE(RES0               = 0x04E4);
+PROVIDE(RES0_L             = 0x04E4);
+PROVIDE(RES0_H             = 0x04E5);
+PROVIDE(RES1               = 0x04E6);
+PROVIDE(RES1_L             = 0x04E6);
+PROVIDE(RES1_H             = 0x04E7);
+PROVIDE(RES2               = 0x04E8);
+PROVIDE(RES2_L             = 0x04E8);
+PROVIDE(RES2_H             = 0x04E9);
+PROVIDE(RES3               = 0x04EA);
+PROVIDE(RES3_L             = 0x04EA);
+PROVIDE(RES3_H             = 0x04EB);
+PROVIDE(MPY32CTL0          = 0x04EC);
+PROVIDE(MPY32CTL0_L        = 0x04EC);
+PROVIDE(MPY32CTL0_H        = 0x04ED);
+/************************************************************
+* PMM - Power Management System for FRAM
+************************************************************/
+PROVIDE(PMMCTL0            = 0x0120);
+PROVIDE(PMMCTL0_L          = 0x0120);
+PROVIDE(PMMCTL0_H          = 0x0121);
+PROVIDE(PMMIFG             = 0x012A);
+PROVIDE(PMMIFG_L           = 0x012A);
+PROVIDE(PMMIFG_H           = 0x012B);
+PROVIDE(PM5CTL0            = 0x0130);
+PROVIDE(PM5CTL0_L          = 0x0130);
+PROVIDE(PM5CTL0_H          = 0x0131);
+/************************************************************
+* DIGITAL I/O Port1/2 Pull up / Pull down Resistors
+************************************************************/
+PROVIDE(PAIN               = 0x0200);
+PROVIDE(PAIN_L             = 0x0200);
+PROVIDE(PAIN_H             = 0x0201);
+PROVIDE(PAOUT              = 0x0202);
+PROVIDE(PAOUT_L            = 0x0202);
+PROVIDE(PAOUT_H            = 0x0203);
+PROVIDE(PADIR              = 0x0204);
+PROVIDE(PADIR_L            = 0x0204);
+PROVIDE(PADIR_H            = 0x0205);
+PROVIDE(PAREN              = 0x0206);
+PROVIDE(PAREN_L            = 0x0206);
+PROVIDE(PAREN_H            = 0x0207);
+PROVIDE(PASEL0             = 0x020A);
+PROVIDE(PASEL0_L           = 0x020A);
+PROVIDE(PASEL0_H           = 0x020B);
+PROVIDE(PASEL1             = 0x020C);
+PROVIDE(PASEL1_L           = 0x020C);
+PROVIDE(PASEL1_H           = 0x020D);
+PROVIDE(PASELC             = 0x0216);
+PROVIDE(PASELC_L           = 0x0216);
+PROVIDE(PASELC_H           = 0x0217);
+PROVIDE(PAIES              = 0x0218);
+PROVIDE(PAIES_L            = 0x0218);
+PROVIDE(PAIES_H            = 0x0219);
+PROVIDE(PAIE               = 0x021A);
+PROVIDE(PAIE_L             = 0x021A);
+PROVIDE(PAIE_H             = 0x021B);
+PROVIDE(PAIFG              = 0x021C);
+PROVIDE(PAIFG_L            = 0x021C);
+PROVIDE(PAIFG_H            = 0x021D);
+PROVIDE(P1IV               = 0x020E);
+PROVIDE(P2IV               = 0x021E);
+/************************************************************
+* DIGITAL I/O Port3/4 Pull up / Pull down Resistors
+************************************************************/
+PROVIDE(PBIN               = 0x0220);
+PROVIDE(PBIN_L             = 0x0220);
+PROVIDE(PBIN_H             = 0x0221);
+PROVIDE(PBOUT              = 0x0222);
+PROVIDE(PBOUT_L            = 0x0222);
+PROVIDE(PBOUT_H            = 0x0223);
+PROVIDE(PBDIR              = 0x0224);
+PROVIDE(PBDIR_L            = 0x0224);
+PROVIDE(PBDIR_H            = 0x0225);
+PROVIDE(PBREN              = 0x0226);
+PROVIDE(PBREN_L            = 0x0226);
+PROVIDE(PBREN_H            = 0x0227);
+PROVIDE(PBSEL0             = 0x022A);
+PROVIDE(PBSEL0_L           = 0x022A);
+PROVIDE(PBSEL0_H           = 0x022B);
+PROVIDE(PBSEL1             = 0x022C);
+PROVIDE(PBSEL1_L           = 0x022C);
+PROVIDE(PBSEL1_H           = 0x022D);
+PROVIDE(PBSELC             = 0x0236);
+PROVIDE(PBSELC_L           = 0x0236);
+PROVIDE(PBSELC_H           = 0x0237);
+PROVIDE(PBIES              = 0x0238);
+PROVIDE(PBIES_L            = 0x0238);
+PROVIDE(PBIES_H            = 0x0239);
+PROVIDE(PBIE               = 0x023A);
+PROVIDE(PBIE_L             = 0x023A);
+PROVIDE(PBIE_H             = 0x023B);
+PROVIDE(PBIFG              = 0x023C);
+PROVIDE(PBIFG_L            = 0x023C);
+PROVIDE(PBIFG_H            = 0x023D);
+PROVIDE(P3IV               = 0x022E);
+PROVIDE(P4IV               = 0x023E);
+/************************************************************
+* DIGITAL I/O PortJ Pull up / Pull down Resistors
+************************************************************/
+PROVIDE(PJIN               = 0x0320);
+PROVIDE(PJIN_L             = 0x0320);
+PROVIDE(PJIN_H             = 0x0321);
+PROVIDE(PJOUT              = 0x0322);
+PROVIDE(PJOUT_L            = 0x0322);
+PROVIDE(PJOUT_H            = 0x0323);
+PROVIDE(PJDIR              = 0x0324);
+PROVIDE(PJDIR_L            = 0x0324);
+PROVIDE(PJDIR_H            = 0x0325);
+PROVIDE(PJREN              = 0x0326);
+PROVIDE(PJREN_L            = 0x0326);
+PROVIDE(PJREN_H            = 0x0327);
+PROVIDE(PJSEL0             = 0x032A);
+PROVIDE(PJSEL0_L           = 0x032A);
+PROVIDE(PJSEL0_H           = 0x032B);
+PROVIDE(PJSEL1             = 0x032C);
+PROVIDE(PJSEL1_L           = 0x032C);
+PROVIDE(PJSEL1_H           = 0x032D);
+PROVIDE(PJSELC             = 0x0336);
+PROVIDE(PJSELC_L           = 0x0336);
+PROVIDE(PJSELC_H           = 0x0337);
+/************************************************************
+* Shared Reference
+************************************************************/
+PROVIDE(REFCTL0            = 0x01B0);
+PROVIDE(REFCTL0_L          = 0x01B0);
+PROVIDE(REFCTL0_H          = 0x01B1);
+/************************************************************
+* Real Time Clock
+************************************************************/
+PROVIDE(RTCCTL01           = 0x04A0);
+PROVIDE(RTCCTL01_L         = 0x04A0);
+PROVIDE(RTCCTL01_H         = 0x04A1);
+PROVIDE(RTCCTL23           = 0x04A2);
+PROVIDE(RTCCTL23_L         = 0x04A2);
+PROVIDE(RTCCTL23_H         = 0x04A3);
+PROVIDE(RTCPS0CTL          = 0x04A8);
+PROVIDE(RTCPS0CTL_L        = 0x04A8);
+PROVIDE(RTCPS0CTL_H        = 0x04A9);
+PROVIDE(RTCPS1CTL          = 0x04AA);
+PROVIDE(RTCPS1CTL_L        = 0x04AA);
+PROVIDE(RTCPS1CTL_H        = 0x04AB);
+PROVIDE(RTCPS              = 0x04AC);
+PROVIDE(RTCPS_L            = 0x04AC);
+PROVIDE(RTCPS_H            = 0x04AD);
+PROVIDE(RTCIV              = 0x04AE);
+PROVIDE(RTCTIM0            = 0x04B0);
+PROVIDE(RTCTIM0_L          = 0x04B0);
+PROVIDE(RTCTIM0_H          = 0x04B1);
+PROVIDE(RTCTIM1            = 0x04B2);
+PROVIDE(RTCTIM1_L          = 0x04B2);
+PROVIDE(RTCTIM1_H          = 0x04B3);
+PROVIDE(RTCDATE            = 0x04B4);
+PROVIDE(RTCDATE_L          = 0x04B4);
+PROVIDE(RTCDATE_H          = 0x04B5);
+PROVIDE(RTCYEAR            = 0x04B6);
+PROVIDE(RTCYEAR_L          = 0x04B6);
+PROVIDE(RTCYEAR_H          = 0x04B7);
+PROVIDE(RTCAMINHR          = 0x04B8);
+PROVIDE(RTCAMINHR_L        = 0x04B8);
+PROVIDE(RTCAMINHR_H        = 0x04B9);
+PROVIDE(RTCADOWDAY         = 0x04BA);
+PROVIDE(RTCADOWDAY_L       = 0x04BA);
+PROVIDE(RTCADOWDAY_H       = 0x04BB);
+PROVIDE(BIN2BCD            = 0x04BC);
+PROVIDE(BCD2BIN            = 0x04BE);
+/************************************************************
+* SFR - Special Function Register Module
+************************************************************/
+PROVIDE(SFRIE1             = 0x0100);
+PROVIDE(SFRIE1_L           = 0x0100);
+PROVIDE(SFRIE1_H           = 0x0101);
+PROVIDE(SFRIFG1            = 0x0102);
+PROVIDE(SFRIFG1_L          = 0x0102);
+PROVIDE(SFRIFG1_H          = 0x0103);
+PROVIDE(SFRRPCR            = 0x0104);
+PROVIDE(SFRRPCR_L          = 0x0104);
+PROVIDE(SFRRPCR_H          = 0x0105);
+/************************************************************
+* SYS - System Module
+************************************************************/
+PROVIDE(SYSCTL             = 0x0180);
+PROVIDE(SYSCTL_L           = 0x0180);
+PROVIDE(SYSCTL_H           = 0x0181);
+PROVIDE(SYSJMBC            = 0x0186);
+PROVIDE(SYSJMBC_L          = 0x0186);
+PROVIDE(SYSJMBC_H          = 0x0187);
+PROVIDE(SYSJMBI0           = 0x0188);
+PROVIDE(SYSJMBI0_L         = 0x0188);
+PROVIDE(SYSJMBI0_H         = 0x0189);
+PROVIDE(SYSJMBI1           = 0x018A);
+PROVIDE(SYSJMBI1_L         = 0x018A);
+PROVIDE(SYSJMBI1_H         = 0x018B);
+PROVIDE(SYSJMBO0           = 0x018C);
+PROVIDE(SYSJMBO0_L         = 0x018C);
+PROVIDE(SYSJMBO0_H         = 0x018D);
+PROVIDE(SYSJMBO1           = 0x018E);
+PROVIDE(SYSJMBO1_L         = 0x018E);
+PROVIDE(SYSJMBO1_H         = 0x018F);
+PROVIDE(SYSUNIV            = 0x019A);
+PROVIDE(SYSUNIV_L          = 0x019A);
+PROVIDE(SYSUNIV_H          = 0x019B);
+PROVIDE(SYSSNIV            = 0x019C);
+PROVIDE(SYSSNIV_L          = 0x019C);
+PROVIDE(SYSSNIV_H          = 0x019D);
+PROVIDE(SYSRSTIV           = 0x019E);
+PROVIDE(SYSRSTIV_L         = 0x019E);
+PROVIDE(SYSRSTIV_H         = 0x019F);
+/************************************************************
+* Timer0_A3
+************************************************************/
+PROVIDE(TA0CTL             = 0x0340);
+PROVIDE(TA0CCTL0           = 0x0342);
+PROVIDE(TA0CCTL1           = 0x0344);
+PROVIDE(TA0CCTL2           = 0x0346);
+PROVIDE(TA0R               = 0x0350);
+PROVIDE(TA0CCR0            = 0x0352);
+PROVIDE(TA0CCR1            = 0x0354);
+PROVIDE(TA0CCR2            = 0x0356);
+PROVIDE(TA0IV              = 0x036E);
+PROVIDE(TA0EX0             = 0x0360);
+/************************************************************
+* Timer1_A3
+************************************************************/
+PROVIDE(TA1CTL             = 0x0380);
+PROVIDE(TA1CCTL0           = 0x0382);
+PROVIDE(TA1CCTL1           = 0x0384);
+PROVIDE(TA1CCTL2           = 0x0386);
+PROVIDE(TA1R               = 0x0390);
+PROVIDE(TA1CCR0            = 0x0392);
+PROVIDE(TA1CCR1            = 0x0394);
+PROVIDE(TA1CCR2            = 0x0396);
+PROVIDE(TA1IV              = 0x03AE);
+PROVIDE(TA1EX0             = 0x03A0);
+/************************************************************
+* Timer2_A2
+************************************************************/
+PROVIDE(TA2CTL             = 0x0400);
+PROVIDE(TA2CCTL0           = 0x0402);
+PROVIDE(TA2CCTL1           = 0x0404);
+PROVIDE(TA2R               = 0x0410);
+PROVIDE(TA2CCR0            = 0x0412);
+PROVIDE(TA2CCR1            = 0x0414);
+PROVIDE(TA2IV              = 0x042E);
+PROVIDE(TA2EX0             = 0x0420);
+/************************************************************
+* Timer3_A2
+************************************************************/
+PROVIDE(TA3CTL             = 0x0440);
+PROVIDE(TA3CCTL0           = 0x0442);
+PROVIDE(TA3CCTL1           = 0x0444);
+PROVIDE(TA3R               = 0x0450);
+PROVIDE(TA3CCR0            = 0x0452);
+PROVIDE(TA3CCR1            = 0x0454);
+PROVIDE(TA3IV              = 0x046E);
+PROVIDE(TA3EX0             = 0x0460);
+/************************************************************
+* Timer0_B7
+************************************************************/
+PROVIDE(TB0CTL             = 0x03C0);
+PROVIDE(TB0CCTL0           = 0x03C2);
+PROVIDE(TB0CCTL1           = 0x03C4);
+PROVIDE(TB0CCTL2           = 0x03C6);
+PROVIDE(TB0CCTL3           = 0x03C8);
+PROVIDE(TB0CCTL4           = 0x03CA);
+PROVIDE(TB0CCTL5           = 0x03CC);
+PROVIDE(TB0CCTL6           = 0x03CE);
+PROVIDE(TB0R               = 0x03D0);
+PROVIDE(TB0CCR0            = 0x03D2);
+PROVIDE(TB0CCR1            = 0x03D4);
+PROVIDE(TB0CCR2            = 0x03D6);
+PROVIDE(TB0CCR3            = 0x03D8);
+PROVIDE(TB0CCR4            = 0x03DA);
+PROVIDE(TB0CCR5            = 0x03DC);
+PROVIDE(TB0CCR6            = 0x03DE);
+PROVIDE(TB0EX0             = 0x03E0);
+PROVIDE(TB0IV              = 0x03EE);
+/************************************************************
+* USCI A0
+************************************************************/
+PROVIDE(UCA0CTLW0          = 0x05C0);
+PROVIDE(UCA0CTLW0_L        = 0x05C0);
+PROVIDE(UCA0CTLW0_H        = 0x05C1);
+PROVIDE(UCA0CTLW1          = 0x05C2);
+PROVIDE(UCA0CTLW1_L        = 0x05C2);
+PROVIDE(UCA0CTLW1_H        = 0x05C3);
+PROVIDE(UCA0BRW            = 0x05C6);
+PROVIDE(UCA0BRW_L          = 0x05C6);
+PROVIDE(UCA0BRW_H          = 0x05C7);
+PROVIDE(UCA0MCTLW          = 0x05C8);
+PROVIDE(UCA0MCTLW_L        = 0x05C8);
+PROVIDE(UCA0MCTLW_H        = 0x05C9);
+PROVIDE(UCA0STATW          = 0x05CA);
+PROVIDE(UCA0RXBUF          = 0x05CC);
+PROVIDE(UCA0RXBUF_L        = 0x05CC);
+PROVIDE(UCA0RXBUF_H        = 0x05CD);
+PROVIDE(UCA0TXBUF          = 0x05CE);
+PROVIDE(UCA0TXBUF_L        = 0x05CE);
+PROVIDE(UCA0TXBUF_H        = 0x05CF);
+PROVIDE(UCA0ABCTL          = 0x05D0);
+PROVIDE(UCA0IRCTL          = 0x05D2);
+PROVIDE(UCA0IRCTL_L        = 0x05D2);
+PROVIDE(UCA0IRCTL_H        = 0x05D3);
+PROVIDE(UCA0IE             = 0x05DA);
+PROVIDE(UCA0IE_L           = 0x05DA);
+PROVIDE(UCA0IE_H           = 0x05DB);
+PROVIDE(UCA0IFG            = 0x05DC);
+PROVIDE(UCA0IFG_L          = 0x05DC);
+PROVIDE(UCA0IFG_H          = 0x05DD);
+PROVIDE(UCA0IV             = 0x05DE);
+/************************************************************
+* USCI A1
+************************************************************/
+PROVIDE(UCA1CTLW0          = 0x05E0);
+PROVIDE(UCA1CTLW0_L        = 0x05E0);
+PROVIDE(UCA1CTLW0_H        = 0x05E1);
+PROVIDE(UCA1CTLW1          = 0x05E2);
+PROVIDE(UCA1CTLW1_L        = 0x05E2);
+PROVIDE(UCA1CTLW1_H        = 0x05E3);
+PROVIDE(UCA1BRW            = 0x05E6);
+PROVIDE(UCA1BRW_L          = 0x05E6);
+PROVIDE(UCA1BRW_H          = 0x05E7);
+PROVIDE(UCA1MCTLW          = 0x05E8);
+PROVIDE(UCA1MCTLW_L        = 0x05E8);
+PROVIDE(UCA1MCTLW_H        = 0x05E9);
+PROVIDE(UCA1STATW          = 0x05EA);
+PROVIDE(UCA1RXBUF          = 0x05EC);
+PROVIDE(UCA1RXBUF_L        = 0x05EC);
+PROVIDE(UCA1RXBUF_H        = 0x05ED);
+PROVIDE(UCA1TXBUF          = 0x05EE);
+PROVIDE(UCA1TXBUF_L        = 0x05EE);
+PROVIDE(UCA1TXBUF_H        = 0x05EF);
+PROVIDE(UCA1ABCTL          = 0x05F0);
+PROVIDE(UCA1IRCTL          = 0x05F2);
+PROVIDE(UCA1IRCTL_L        = 0x05F2);
+PROVIDE(UCA1IRCTL_H        = 0x05F3);
+PROVIDE(UCA1IE             = 0x05FA);
+PROVIDE(UCA1IE_L           = 0x05FA);
+PROVIDE(UCA1IE_H           = 0x05FB);
+PROVIDE(UCA1IFG            = 0x05FC);
+PROVIDE(UCA1IFG_L          = 0x05FC);
+PROVIDE(UCA1IFG_H          = 0x05FD);
+PROVIDE(UCA1IV             = 0x05FE);
+/************************************************************
+* USCI B0
+************************************************************/
+PROVIDE(UCB0CTLW0          = 0x0640);
+PROVIDE(UCB0CTLW0_L        = 0x0640);
+PROVIDE(UCB0CTLW0_H        = 0x0641);
+PROVIDE(UCB0CTLW1          = 0x0642);
+PROVIDE(UCB0CTLW1_L        = 0x0642);
+PROVIDE(UCB0CTLW1_H        = 0x0643);
+PROVIDE(UCB0BRW            = 0x0646);
+PROVIDE(UCB0BRW_L          = 0x0646);
+PROVIDE(UCB0BRW_H          = 0x0647);
+PROVIDE(UCB0STATW          = 0x0648);
+PROVIDE(UCB0STATW_L        = 0x0648);
+PROVIDE(UCB0STATW_H        = 0x0649);
+PROVIDE(UCB0TBCNT          = 0x064A);
+PROVIDE(UCB0TBCNT_L        = 0x064A);
+PROVIDE(UCB0TBCNT_H        = 0x064B);
+PROVIDE(UCB0RXBUF          = 0x064C);
+PROVIDE(UCB0RXBUF_L        = 0x064C);
+PROVIDE(UCB0RXBUF_H        = 0x064D);
+PROVIDE(UCB0TXBUF          = 0x064E);
+PROVIDE(UCB0TXBUF_L        = 0x064E);
+PROVIDE(UCB0TXBUF_H        = 0x064F);
+PROVIDE(UCB0I2COA0         = 0x0654);
+PROVIDE(UCB0I2COA0_L       = 0x0654);
+PROVIDE(UCB0I2COA0_H       = 0x0655);
+PROVIDE(UCB0I2COA1         = 0x0656);
+PROVIDE(UCB0I2COA1_L       = 0x0656);
+PROVIDE(UCB0I2COA1_H       = 0x0657);
+PROVIDE(UCB0I2COA2         = 0x0658);
+PROVIDE(UCB0I2COA2_L       = 0x0658);
+PROVIDE(UCB0I2COA2_H       = 0x0659);
+PROVIDE(UCB0I2COA3         = 0x065A);
+PROVIDE(UCB0I2COA3_L       = 0x065A);
+PROVIDE(UCB0I2COA3_H       = 0x065B);
+PROVIDE(UCB0ADDRX          = 0x065C);
+PROVIDE(UCB0ADDRX_L        = 0x065C);
+PROVIDE(UCB0ADDRX_H        = 0x065D);
+PROVIDE(UCB0ADDMASK        = 0x065E);
+PROVIDE(UCB0ADDMASK_L      = 0x065E);
+PROVIDE(UCB0ADDMASK_H      = 0x065F);
+PROVIDE(UCB0I2CSA          = 0x0660);
+PROVIDE(UCB0I2CSA_L        = 0x0660);
+PROVIDE(UCB0I2CSA_H        = 0x0661);
+PROVIDE(UCB0IE             = 0x066A);
+PROVIDE(UCB0IE_L           = 0x066A);
+PROVIDE(UCB0IE_H           = 0x066B);
+PROVIDE(UCB0IFG            = 0x066C);
+PROVIDE(UCB0IFG_L          = 0x066C);
+PROVIDE(UCB0IFG_H          = 0x066D);
+PROVIDE(UCB0IV             = 0x066E);
+/************************************************************
+* WATCHDOG TIMER A
+************************************************************/
+PROVIDE(WDTCTL             = 0x015C);
+PROVIDE(WDTCTL_L           = 0x015C);
+PROVIDE(WDTCTL_H           = 0x015D);
+/************************************************************
+* TLV Descriptors
+************************************************************/
+/************************************************************
+* Interrupt Vectors (offset from 0xFF80 + 0x10 for Password)
+************************************************************/
+/************************************************************
+* End of Modules
+************************************************************/
diff --git a/os/common/startup/MSP430X/compilers/GCC/ld/msp430fr6989_symbols.ld b/os/common/startup/MSP430X/compilers/GCC/ld/msp430fr6989_symbols.ld
new file mode 100644
index 0000000..05b7c84
--- /dev/null
+++ b/os/common/startup/MSP430X/compilers/GCC/ld/msp430fr6989_symbols.ld
@@ -0,0 +1,1552 @@
+/* ============================================================================ */
+/* Copyright (c) 2016, Texas Instruments Incorporated                           */
+/*  All rights reserved.                                                        */
+/*                                                                              */
+/*  Redistribution and use in source and binary forms, with or without          */
+/*  modification, are permitted provided that the following conditions          */
+/*  are met:                                                                    */
+/*                                                                              */
+/*  *  Redistributions of source code must retain the above copyright           */
+/*     notice, this list of conditions and the following disclaimer.            */
+/*                                                                              */
+/*  *  Redistributions in binary form must reproduce the above copyright        */
+/*     notice, this list of conditions and the following disclaimer in the      */
+/*     documentation and/or other materials provided with the distribution.     */
+/*                                                                              */
+/*  *  Neither the name of Texas Instruments Incorporated nor the names of      */
+/*     its contributors may be used to endorse or promote products derived      */
+/*     from this software without specific prior written permission.            */
+/*                                                                              */
+/*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */
+/*  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,       */
+/*  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR      */
+/*  PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR            */
+/*  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,       */
+/*  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,         */
+/*  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */
+/*  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,    */
+/*  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR     */
+/*  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,              */
+/*  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                          */
+/* ============================================================================ */
+
+/* This file supports MSP430FR6989 devices. */
+/* Version: 1.198 */
+
+/************************************************************
+* STANDARD BITS
+************************************************************/
+/************************************************************
+* STATUS REGISTER BITS
+************************************************************/
+/************************************************************
+* PERIPHERAL FILE MAP
+************************************************************/
+/************************************************************
+* ADC12_B
+************************************************************/
+PROVIDE(ADC12CTL0          = 0x0800);
+PROVIDE(ADC12CTL0_L        = 0x0800);
+PROVIDE(ADC12CTL0_H        = 0x0801);
+PROVIDE(ADC12CTL1          = 0x0802);
+PROVIDE(ADC12CTL1_L        = 0x0802);
+PROVIDE(ADC12CTL1_H        = 0x0803);
+PROVIDE(ADC12CTL2          = 0x0804);
+PROVIDE(ADC12CTL2_L        = 0x0804);
+PROVIDE(ADC12CTL2_H        = 0x0805);
+PROVIDE(ADC12CTL3          = 0x0806);
+PROVIDE(ADC12CTL3_L        = 0x0806);
+PROVIDE(ADC12CTL3_H        = 0x0807);
+PROVIDE(ADC12LO            = 0x0808);
+PROVIDE(ADC12LO_L          = 0x0808);
+PROVIDE(ADC12LO_H          = 0x0809);
+PROVIDE(ADC12HI            = 0x080A);
+PROVIDE(ADC12HI_L          = 0x080A);
+PROVIDE(ADC12HI_H          = 0x080B);
+PROVIDE(ADC12IFGR0         = 0x080C);
+PROVIDE(ADC12IFGR0_L       = 0x080C);
+PROVIDE(ADC12IFGR0_H       = 0x080D);
+PROVIDE(ADC12IFGR1         = 0x080E);
+PROVIDE(ADC12IFGR1_L       = 0x080E);
+PROVIDE(ADC12IFGR1_H       = 0x080F);
+PROVIDE(ADC12IFGR2         = 0x0810);
+PROVIDE(ADC12IFGR2_L       = 0x0810);
+PROVIDE(ADC12IFGR2_H       = 0x0811);
+PROVIDE(ADC12IER0          = 0x0812);
+PROVIDE(ADC12IER0_L        = 0x0812);
+PROVIDE(ADC12IER0_H        = 0x0813);
+PROVIDE(ADC12IER1          = 0x0814);
+PROVIDE(ADC12IER1_L        = 0x0814);
+PROVIDE(ADC12IER1_H        = 0x0815);
+PROVIDE(ADC12IER2          = 0x0816);
+PROVIDE(ADC12IER2_L        = 0x0816);
+PROVIDE(ADC12IER2_H        = 0x0817);
+PROVIDE(ADC12IV            = 0x0818);
+PROVIDE(ADC12IV_L          = 0x0818);
+PROVIDE(ADC12IV_H          = 0x0819);
+PROVIDE(ADC12MCTL0         = 0x0820);
+PROVIDE(ADC12MCTL0_L       = 0x0820);
+PROVIDE(ADC12MCTL0_H       = 0x0821);
+PROVIDE(ADC12MCTL1         = 0x0822);
+PROVIDE(ADC12MCTL1_L       = 0x0822);
+PROVIDE(ADC12MCTL1_H       = 0x0823);
+PROVIDE(ADC12MCTL2         = 0x0824);
+PROVIDE(ADC12MCTL2_L       = 0x0824);
+PROVIDE(ADC12MCTL2_H       = 0x0825);
+PROVIDE(ADC12MCTL3         = 0x0826);
+PROVIDE(ADC12MCTL3_L       = 0x0826);
+PROVIDE(ADC12MCTL3_H       = 0x0827);
+PROVIDE(ADC12MCTL4         = 0x0828);
+PROVIDE(ADC12MCTL4_L       = 0x0828);
+PROVIDE(ADC12MCTL4_H       = 0x0829);
+PROVIDE(ADC12MCTL5         = 0x082A);
+PROVIDE(ADC12MCTL5_L       = 0x082A);
+PROVIDE(ADC12MCTL5_H       = 0x082B);
+PROVIDE(ADC12MCTL6         = 0x082C);
+PROVIDE(ADC12MCTL6_L       = 0x082C);
+PROVIDE(ADC12MCTL6_H       = 0x082D);
+PROVIDE(ADC12MCTL7         = 0x082E);
+PROVIDE(ADC12MCTL7_L       = 0x082E);
+PROVIDE(ADC12MCTL7_H       = 0x082F);
+PROVIDE(ADC12MCTL8         = 0x0830);
+PROVIDE(ADC12MCTL8_L       = 0x0830);
+PROVIDE(ADC12MCTL8_H       = 0x0831);
+PROVIDE(ADC12MCTL9         = 0x0832);
+PROVIDE(ADC12MCTL9_L       = 0x0832);
+PROVIDE(ADC12MCTL9_H       = 0x0833);
+PROVIDE(ADC12MCTL10        = 0x0834);
+PROVIDE(ADC12MCTL10_L      = 0x0834);
+PROVIDE(ADC12MCTL10_H      = 0x0835);
+PROVIDE(ADC12MCTL11        = 0x0836);
+PROVIDE(ADC12MCTL11_L      = 0x0836);
+PROVIDE(ADC12MCTL11_H      = 0x0837);
+PROVIDE(ADC12MCTL12        = 0x0838);
+PROVIDE(ADC12MCTL12_L      = 0x0838);
+PROVIDE(ADC12MCTL12_H      = 0x0839);
+PROVIDE(ADC12MCTL13        = 0x083A);
+PROVIDE(ADC12MCTL13_L      = 0x083A);
+PROVIDE(ADC12MCTL13_H      = 0x083B);
+PROVIDE(ADC12MCTL14        = 0x083C);
+PROVIDE(ADC12MCTL14_L      = 0x083C);
+PROVIDE(ADC12MCTL14_H      = 0x083D);
+PROVIDE(ADC12MCTL15        = 0x083E);
+PROVIDE(ADC12MCTL15_L      = 0x083E);
+PROVIDE(ADC12MCTL15_H      = 0x083F);
+PROVIDE(ADC12MCTL16        = 0x0840);
+PROVIDE(ADC12MCTL16_L      = 0x0840);
+PROVIDE(ADC12MCTL16_H      = 0x0841);
+PROVIDE(ADC12MCTL17        = 0x0842);
+PROVIDE(ADC12MCTL17_L      = 0x0842);
+PROVIDE(ADC12MCTL17_H      = 0x0843);
+PROVIDE(ADC12MCTL18        = 0x0844);
+PROVIDE(ADC12MCTL18_L      = 0x0844);
+PROVIDE(ADC12MCTL18_H      = 0x0845);
+PROVIDE(ADC12MCTL19        = 0x0846);
+PROVIDE(ADC12MCTL19_L      = 0x0846);
+PROVIDE(ADC12MCTL19_H      = 0x0847);
+PROVIDE(ADC12MCTL20        = 0x0848);
+PROVIDE(ADC12MCTL20_L      = 0x0848);
+PROVIDE(ADC12MCTL20_H      = 0x0849);
+PROVIDE(ADC12MCTL21        = 0x084A);
+PROVIDE(ADC12MCTL21_L      = 0x084A);
+PROVIDE(ADC12MCTL21_H      = 0x084B);
+PROVIDE(ADC12MCTL22        = 0x084C);
+PROVIDE(ADC12MCTL22_L      = 0x084C);
+PROVIDE(ADC12MCTL22_H      = 0x084D);
+PROVIDE(ADC12MCTL23        = 0x084E);
+PROVIDE(ADC12MCTL23_L      = 0x084E);
+PROVIDE(ADC12MCTL23_H      = 0x084F);
+PROVIDE(ADC12MCTL24        = 0x0850);
+PROVIDE(ADC12MCTL24_L      = 0x0850);
+PROVIDE(ADC12MCTL24_H      = 0x0851);
+PROVIDE(ADC12MCTL25        = 0x0852);
+PROVIDE(ADC12MCTL25_L      = 0x0852);
+PROVIDE(ADC12MCTL25_H      = 0x0853);
+PROVIDE(ADC12MCTL26        = 0x0854);
+PROVIDE(ADC12MCTL26_L      = 0x0854);
+PROVIDE(ADC12MCTL26_H      = 0x0855);
+PROVIDE(ADC12MCTL27        = 0x0856);
+PROVIDE(ADC12MCTL27_L      = 0x0856);
+PROVIDE(ADC12MCTL27_H      = 0x0857);
+PROVIDE(ADC12MCTL28        = 0x0858);
+PROVIDE(ADC12MCTL28_L      = 0x0858);
+PROVIDE(ADC12MCTL28_H      = 0x0859);
+PROVIDE(ADC12MCTL29        = 0x085A);
+PROVIDE(ADC12MCTL29_L      = 0x085A);
+PROVIDE(ADC12MCTL29_H      = 0x085B);
+PROVIDE(ADC12MCTL30        = 0x085C);
+PROVIDE(ADC12MCTL30_L      = 0x085C);
+PROVIDE(ADC12MCTL30_H      = 0x085D);
+PROVIDE(ADC12MCTL31        = 0x085E);
+PROVIDE(ADC12MCTL31_L      = 0x085E);
+PROVIDE(ADC12MCTL31_H      = 0x085F);
+PROVIDE(ADC12MEM0          = 0x0860);
+PROVIDE(ADC12MEM0_L        = 0x0860);
+PROVIDE(ADC12MEM0_H        = 0x0861);
+PROVIDE(ADC12MEM1          = 0x0862);
+PROVIDE(ADC12MEM1_L        = 0x0862);
+PROVIDE(ADC12MEM1_H        = 0x0863);
+PROVIDE(ADC12MEM2          = 0x0864);
+PROVIDE(ADC12MEM2_L        = 0x0864);
+PROVIDE(ADC12MEM2_H        = 0x0865);
+PROVIDE(ADC12MEM3          = 0x0866);
+PROVIDE(ADC12MEM3_L        = 0x0866);
+PROVIDE(ADC12MEM3_H        = 0x0867);
+PROVIDE(ADC12MEM4          = 0x0868);
+PROVIDE(ADC12MEM4_L        = 0x0868);
+PROVIDE(ADC12MEM4_H        = 0x0869);
+PROVIDE(ADC12MEM5          = 0x086A);
+PROVIDE(ADC12MEM5_L        = 0x086A);
+PROVIDE(ADC12MEM5_H        = 0x086B);
+PROVIDE(ADC12MEM6          = 0x086C);
+PROVIDE(ADC12MEM6_L        = 0x086C);
+PROVIDE(ADC12MEM6_H        = 0x086D);
+PROVIDE(ADC12MEM7          = 0x086E);
+PROVIDE(ADC12MEM7_L        = 0x086E);
+PROVIDE(ADC12MEM7_H        = 0x086F);
+PROVIDE(ADC12MEM8          = 0x0870);
+PROVIDE(ADC12MEM8_L        = 0x0870);
+PROVIDE(ADC12MEM8_H        = 0x0871);
+PROVIDE(ADC12MEM9          = 0x0872);
+PROVIDE(ADC12MEM9_L        = 0x0872);
+PROVIDE(ADC12MEM9_H        = 0x0873);
+PROVIDE(ADC12MEM10         = 0x0874);
+PROVIDE(ADC12MEM10_L       = 0x0874);
+PROVIDE(ADC12MEM10_H       = 0x0875);
+PROVIDE(ADC12MEM11         = 0x0876);
+PROVIDE(ADC12MEM11_L       = 0x0876);
+PROVIDE(ADC12MEM11_H       = 0x0877);
+PROVIDE(ADC12MEM12         = 0x0878);
+PROVIDE(ADC12MEM12_L       = 0x0878);
+PROVIDE(ADC12MEM12_H       = 0x0879);
+PROVIDE(ADC12MEM13         = 0x087A);
+PROVIDE(ADC12MEM13_L       = 0x087A);
+PROVIDE(ADC12MEM13_H       = 0x087B);
+PROVIDE(ADC12MEM14         = 0x087C);
+PROVIDE(ADC12MEM14_L       = 0x087C);
+PROVIDE(ADC12MEM14_H       = 0x087D);
+PROVIDE(ADC12MEM15         = 0x087E);
+PROVIDE(ADC12MEM15_L       = 0x087E);
+PROVIDE(ADC12MEM15_H       = 0x087F);
+PROVIDE(ADC12MEM16         = 0x0880);
+PROVIDE(ADC12MEM16_L       = 0x0880);
+PROVIDE(ADC12MEM16_H       = 0x0881);
+PROVIDE(ADC12MEM17         = 0x0882);
+PROVIDE(ADC12MEM17_L       = 0x0882);
+PROVIDE(ADC12MEM17_H       = 0x0883);
+PROVIDE(ADC12MEM18         = 0x0884);
+PROVIDE(ADC12MEM18_L       = 0x0884);
+PROVIDE(ADC12MEM18_H       = 0x0885);
+PROVIDE(ADC12MEM19         = 0x0886);
+PROVIDE(ADC12MEM19_L       = 0x0886);
+PROVIDE(ADC12MEM19_H       = 0x0887);
+PROVIDE(ADC12MEM20         = 0x0888);
+PROVIDE(ADC12MEM20_L       = 0x0888);
+PROVIDE(ADC12MEM20_H       = 0x0889);
+PROVIDE(ADC12MEM21         = 0x088A);
+PROVIDE(ADC12MEM21_L       = 0x088A);
+PROVIDE(ADC12MEM21_H       = 0x088B);
+PROVIDE(ADC12MEM22         = 0x088C);
+PROVIDE(ADC12MEM22_L       = 0x088C);
+PROVIDE(ADC12MEM22_H       = 0x088D);
+PROVIDE(ADC12MEM23         = 0x088E);
+PROVIDE(ADC12MEM23_L       = 0x088E);
+PROVIDE(ADC12MEM23_H       = 0x088F);
+PROVIDE(ADC12MEM24         = 0x0890);
+PROVIDE(ADC12MEM24_L       = 0x0890);
+PROVIDE(ADC12MEM24_H       = 0x0891);
+PROVIDE(ADC12MEM25         = 0x0892);
+PROVIDE(ADC12MEM25_L       = 0x0892);
+PROVIDE(ADC12MEM25_H       = 0x0893);
+PROVIDE(ADC12MEM26         = 0x0894);
+PROVIDE(ADC12MEM26_L       = 0x0894);
+PROVIDE(ADC12MEM26_H       = 0x0895);
+PROVIDE(ADC12MEM27         = 0x0896);
+PROVIDE(ADC12MEM27_L       = 0x0896);
+PROVIDE(ADC12MEM27_H       = 0x0897);
+PROVIDE(ADC12MEM28         = 0x0898);
+PROVIDE(ADC12MEM28_L       = 0x0898);
+PROVIDE(ADC12MEM28_H       = 0x0899);
+PROVIDE(ADC12MEM29         = 0x089A);
+PROVIDE(ADC12MEM29_L       = 0x089A);
+PROVIDE(ADC12MEM29_H       = 0x089B);
+PROVIDE(ADC12MEM30         = 0x089C);
+PROVIDE(ADC12MEM30_L       = 0x089C);
+PROVIDE(ADC12MEM30_H       = 0x089D);
+PROVIDE(ADC12MEM31         = 0x089E);
+PROVIDE(ADC12MEM31_L       = 0x089E);
+PROVIDE(ADC12MEM31_H       = 0x089F);
+/************************************************************
+* AES256 Accelerator
+************************************************************/
+PROVIDE(AESACTL0           = 0x09C0);
+PROVIDE(AESACTL0_L         = 0x09C0);
+PROVIDE(AESACTL0_H         = 0x09C1);
+PROVIDE(AESACTL1           = 0x09C2);
+PROVIDE(AESACTL1_L         = 0x09C2);
+PROVIDE(AESACTL1_H         = 0x09C3);
+PROVIDE(AESASTAT           = 0x09C4);
+PROVIDE(AESASTAT_L         = 0x09C4);
+PROVIDE(AESASTAT_H         = 0x09C5);
+PROVIDE(AESAKEY            = 0x09C6);
+PROVIDE(AESAKEY_L          = 0x09C6);
+PROVIDE(AESAKEY_H          = 0x09C7);
+PROVIDE(AESADIN            = 0x09C8);
+PROVIDE(AESADIN_L          = 0x09C8);
+PROVIDE(AESADIN_H          = 0x09C9);
+PROVIDE(AESADOUT           = 0x09CA);
+PROVIDE(AESADOUT_L         = 0x09CA);
+PROVIDE(AESADOUT_H         = 0x09CB);
+PROVIDE(AESAXDIN           = 0x09CC);
+PROVIDE(AESAXDIN_L         = 0x09CC);
+PROVIDE(AESAXDIN_H         = 0x09CD);
+PROVIDE(AESAXIN            = 0x09CE);
+PROVIDE(AESAXIN_L          = 0x09CE);
+PROVIDE(AESAXIN_H          = 0x09CF);
+/************************************************************
+* Capacitive_Touch_IO 0
+************************************************************/
+PROVIDE(CAPTIO0CTL         = 0x043E);
+PROVIDE(CAPTIO0CTL_L       = 0x043E);
+PROVIDE(CAPTIO0CTL_H       = 0x043F);
+/************************************************************
+* Capacitive_Touch_IO 1
+************************************************************/
+PROVIDE(CAPTIO1CTL         = 0x047E);
+PROVIDE(CAPTIO1CTL_L       = 0x047E);
+PROVIDE(CAPTIO1CTL_H       = 0x047F);
+/************************************************************
+* Comparator E
+************************************************************/
+PROVIDE(CECTL0             = 0x08C0);
+PROVIDE(CECTL0_L           = 0x08C0);
+PROVIDE(CECTL0_H           = 0x08C1);
+PROVIDE(CECTL1             = 0x08C2);
+PROVIDE(CECTL1_L           = 0x08C2);
+PROVIDE(CECTL1_H           = 0x08C3);
+PROVIDE(CECTL2             = 0x08C4);
+PROVIDE(CECTL2_L           = 0x08C4);
+PROVIDE(CECTL2_H           = 0x08C5);
+PROVIDE(CECTL3             = 0x08C6);
+PROVIDE(CECTL3_L           = 0x08C6);
+PROVIDE(CECTL3_H           = 0x08C7);
+PROVIDE(CEINT              = 0x08CC);
+PROVIDE(CEINT_L            = 0x08CC);
+PROVIDE(CEINT_H            = 0x08CD);
+PROVIDE(CEIV               = 0x08CE);
+PROVIDE(CEIV_L             = 0x08CE);
+PROVIDE(CEIV_H             = 0x08CF);
+/*************************************************************
+* CRC Module
+*************************************************************/
+PROVIDE(CRCDI              = 0x0150);
+PROVIDE(CRCDI_L            = 0x0150);
+PROVIDE(CRCDI_H            = 0x0151);
+PROVIDE(CRCDIRB            = 0x0152);
+PROVIDE(CRCDIRB_L          = 0x0152);
+PROVIDE(CRCDIRB_H          = 0x0153);
+PROVIDE(CRCINIRES          = 0x0154);
+PROVIDE(CRCINIRES_L        = 0x0154);
+PROVIDE(CRCINIRES_H        = 0x0155);
+PROVIDE(CRCRESR            = 0x0156);
+PROVIDE(CRCRESR_L          = 0x0156);
+PROVIDE(CRCRESR_H          = 0x0157);
+/*************************************************************
+* CRC Module
+*************************************************************/
+PROVIDE(CRC32DIW0          = 0x0980);
+PROVIDE(CRC32DIW0_L        = 0x0980);
+PROVIDE(CRC32DIW0_H        = 0x0981);
+PROVIDE(CRC32DIW1          = 0x0982);
+PROVIDE(CRC32DIW1_L        = 0x0982);
+PROVIDE(CRC32DIW1_H        = 0x0983);
+PROVIDE(CRC32DIRBW1        = 0x0984);
+PROVIDE(CRC32DIRBW1_L      = 0x0984);
+PROVIDE(CRC32DIRBW1_H      = 0x0985);
+PROVIDE(CRC32DIRBW0        = 0x0986);
+PROVIDE(CRC32DIRBW0_L      = 0x0986);
+PROVIDE(CRC32DIRBW0_H      = 0x0987);
+PROVIDE(CRC32INIRESW0      = 0x0988);
+PROVIDE(CRC32INIRESW0_L    = 0x0988);
+PROVIDE(CRC32INIRESW0_H    = 0x0989);
+PROVIDE(CRC32INIRESW1      = 0x098A);
+PROVIDE(CRC32INIRESW1_L    = 0x098A);
+PROVIDE(CRC32INIRESW1_H    = 0x098B);
+PROVIDE(CRC32RESRW1        = 0x098C);
+PROVIDE(CRC32RESRW1_L      = 0x098C);
+PROVIDE(CRC32RESRW1_H      = 0x098D);
+PROVIDE(CRC32RESRW0        = 0x098E);
+PROVIDE(CRC32RESRW0_L      = 0x098E);
+PROVIDE(CRC32RESRW0_H      = 0x098F);
+PROVIDE(CRC16DIW0          = 0x0990);
+PROVIDE(CRC16DIW0_L        = 0x0990);
+PROVIDE(CRC16DIW0_H        = 0x0991);
+PROVIDE(CRC16DIW1          = 0x0992);
+PROVIDE(CRC16DIW1_L        = 0x0992);
+PROVIDE(CRC16DIW1_H        = 0x0993);
+PROVIDE(CRC16DIRBW1        = 0x0994);
+PROVIDE(CRC16DIRBW1_L      = 0x0994);
+PROVIDE(CRC16DIRBW1_H      = 0x0995);
+PROVIDE(CRC16DIRBW0        = 0x0996);
+PROVIDE(CRC16DIRBW0_L      = 0x0996);
+PROVIDE(CRC16DIRBW0_H      = 0x0997);
+PROVIDE(CRC16INIRESW0      = 0x0998);
+PROVIDE(CRC16INIRESW0_L    = 0x0998);
+PROVIDE(CRC16INIRESW0_H    = 0x0999);
+PROVIDE(CRC16RESRW0        = 0x099E);
+PROVIDE(CRC16RESRW0_L      = 0x099E);
+PROVIDE(CRC16RESRW0_H      = 0x099F);
+PROVIDE(CRC16RESRW1        = 0x099C);
+PROVIDE(CRC16RESRW1_L      = 0x099C);
+PROVIDE(CRC16RESRW1_H      = 0x099D);
+/************************************************************
+* CLOCK SYSTEM
+************************************************************/
+PROVIDE(CSCTL0             = 0x0160);
+PROVIDE(CSCTL0_L           = 0x0160);
+PROVIDE(CSCTL0_H           = 0x0161);
+PROVIDE(CSCTL1             = 0x0162);
+PROVIDE(CSCTL1_L           = 0x0162);
+PROVIDE(CSCTL1_H           = 0x0163);
+PROVIDE(CSCTL2             = 0x0164);
+PROVIDE(CSCTL2_L           = 0x0164);
+PROVIDE(CSCTL2_H           = 0x0165);
+PROVIDE(CSCTL3             = 0x0166);
+PROVIDE(CSCTL3_L           = 0x0166);
+PROVIDE(CSCTL3_H           = 0x0167);
+PROVIDE(CSCTL4             = 0x0168);
+PROVIDE(CSCTL4_L           = 0x0168);
+PROVIDE(CSCTL4_H           = 0x0169);
+PROVIDE(CSCTL5             = 0x016A);
+PROVIDE(CSCTL5_L           = 0x016A);
+PROVIDE(CSCTL5_H           = 0x016B);
+PROVIDE(CSCTL6             = 0x016C);
+PROVIDE(CSCTL6_L           = 0x016C);
+PROVIDE(CSCTL6_H           = 0x016D);
+/************************************************************
+* DMA_X
+************************************************************/
+PROVIDE(DMACTL0            = 0x0500);
+PROVIDE(DMACTL0_L          = 0x0500);
+PROVIDE(DMACTL0_H          = 0x0501);
+PROVIDE(DMACTL1            = 0x0502);
+PROVIDE(DMACTL1_L          = 0x0502);
+PROVIDE(DMACTL1_H          = 0x0503);
+PROVIDE(DMACTL2            = 0x0504);
+PROVIDE(DMACTL2_L          = 0x0504);
+PROVIDE(DMACTL2_H          = 0x0505);
+PROVIDE(DMACTL3            = 0x0506);
+PROVIDE(DMACTL3_L          = 0x0506);
+PROVIDE(DMACTL3_H          = 0x0507);
+PROVIDE(DMACTL4            = 0x0508);
+PROVIDE(DMACTL4_L          = 0x0508);
+PROVIDE(DMACTL4_H          = 0x0509);
+PROVIDE(DMAIV              = 0x050E);
+PROVIDE(DMAIV_L            = 0x050E);
+PROVIDE(DMAIV_H            = 0x050F);
+PROVIDE(DMA0CTL            = 0x0510);
+PROVIDE(DMA0CTL_L          = 0x0510);
+PROVIDE(DMA0CTL_H          = 0x0511);
+PROVIDE(DMA0SA             = 0x0512);
+PROVIDE(DMA0SAL            = 0x0512);
+PROVIDE(DMA0DA             = 0x0516);
+PROVIDE(DMA0DAL            = 0x0516);
+PROVIDE(DMA0SZ             = 0x051A);
+PROVIDE(DMA1CTL            = 0x0520);
+PROVIDE(DMA1CTL_L          = 0x0520);
+PROVIDE(DMA1CTL_H          = 0x0521);
+PROVIDE(DMA1SA             = 0x0522);
+PROVIDE(DMA1SAL            = 0x0522);
+PROVIDE(DMA1DA             = 0x0526);
+PROVIDE(DMA1DAL            = 0x0526);
+PROVIDE(DMA1SZ             = 0x052A);
+PROVIDE(DMA2CTL            = 0x0530);
+PROVIDE(DMA2CTL_L          = 0x0530);
+PROVIDE(DMA2CTL_H          = 0x0531);
+PROVIDE(DMA2SA             = 0x0532);
+PROVIDE(DMA2SAL            = 0x0532);
+PROVIDE(DMA2DA             = 0x0536);
+PROVIDE(DMA2DAL            = 0x0536);
+PROVIDE(DMA2SZ             = 0x053A);
+/************************************************************
+* EXTENDED SCAN INTERFACE
+************************************************************/
+PROVIDE(ESIDEBUG1          = 0x0D00);
+PROVIDE(ESIDEBUG1_L        = 0x0D00);
+PROVIDE(ESIDEBUG1_H        = 0x0D01);
+PROVIDE(ESIDEBUG2          = 0x0D02);
+PROVIDE(ESIDEBUG2_L        = 0x0D02);
+PROVIDE(ESIDEBUG2_H        = 0x0D03);
+PROVIDE(ESIDEBUG3          = 0x0D04);
+PROVIDE(ESIDEBUG3_L        = 0x0D04);
+PROVIDE(ESIDEBUG3_H        = 0x0D05);
+PROVIDE(ESIDEBUG4          = 0x0D06);
+PROVIDE(ESIDEBUG4_L        = 0x0D06);
+PROVIDE(ESIDEBUG4_H        = 0x0D07);
+PROVIDE(ESIDEBUG5          = 0x0D08);
+PROVIDE(ESIDEBUG5_L        = 0x0D08);
+PROVIDE(ESIDEBUG5_H        = 0x0D09);
+PROVIDE(ESICNT0            = 0x0D10);
+PROVIDE(ESICNT0_L          = 0x0D10);
+PROVIDE(ESICNT0_H          = 0x0D11);
+PROVIDE(ESICNT1            = 0x0D12);
+PROVIDE(ESICNT1_L          = 0x0D12);
+PROVIDE(ESICNT1_H          = 0x0D13);
+PROVIDE(ESICNT2            = 0x0D14);
+PROVIDE(ESICNT2_L          = 0x0D14);
+PROVIDE(ESICNT2_H          = 0x0D15);
+PROVIDE(ESICNT3            = 0x0D16);
+PROVIDE(ESICNT3_L          = 0x0D16);
+PROVIDE(ESICNT3_H          = 0x0D17);
+PROVIDE(ESIIV              = 0x0D1A);
+PROVIDE(ESIIV_L            = 0x0D1A);
+PROVIDE(ESIIV_H            = 0x0D1B);
+PROVIDE(ESIINT1            = 0x0D1C);
+PROVIDE(ESIINT1_L          = 0x0D1C);
+PROVIDE(ESIINT1_H          = 0x0D1D);
+PROVIDE(ESIINT2            = 0x0D1E);
+PROVIDE(ESIINT2_L          = 0x0D1E);
+PROVIDE(ESIINT2_H          = 0x0D1F);
+PROVIDE(ESIAFE             = 0x0D20);
+PROVIDE(ESIAFE_L           = 0x0D20);
+PROVIDE(ESIAFE_H           = 0x0D21);
+PROVIDE(ESIPPU             = 0x0D22);
+PROVIDE(ESIPPU_L           = 0x0D22);
+PROVIDE(ESIPPU_H           = 0x0D23);
+PROVIDE(ESITSM             = 0x0D24);
+PROVIDE(ESITSM_L           = 0x0D24);
+PROVIDE(ESITSM_H           = 0x0D25);
+PROVIDE(ESIPSM             = 0x0D26);
+PROVIDE(ESIPSM_L           = 0x0D26);
+PROVIDE(ESIPSM_H           = 0x0D27);
+PROVIDE(ESIOSC             = 0x0D28);
+PROVIDE(ESIOSC_L           = 0x0D28);
+PROVIDE(ESIOSC_H           = 0x0D29);
+PROVIDE(ESICTL             = 0x0D2A);
+PROVIDE(ESICTL_L           = 0x0D2A);
+PROVIDE(ESICTL_H           = 0x0D2B);
+PROVIDE(ESITHR1            = 0x0D2C);
+PROVIDE(ESITHR1_L          = 0x0D2C);
+PROVIDE(ESITHR1_H          = 0x0D2D);
+PROVIDE(ESITHR2            = 0x0D2E);
+PROVIDE(ESITHR2_L          = 0x0D2E);
+PROVIDE(ESITHR2_H          = 0x0D2F);
+PROVIDE(ESIDAC1R0          = 0x0D40);
+PROVIDE(ESIDAC1R0_L        = 0x0D40);
+PROVIDE(ESIDAC1R0_H        = 0x0D41);
+PROVIDE(ESIDAC1R1          = 0x0D42);
+PROVIDE(ESIDAC1R1_L        = 0x0D42);
+PROVIDE(ESIDAC1R1_H        = 0x0D43);
+PROVIDE(ESIDAC1R2          = 0x0D44);
+PROVIDE(ESIDAC1R2_L        = 0x0D44);
+PROVIDE(ESIDAC1R2_H        = 0x0D45);
+PROVIDE(ESIDAC1R3          = 0x0D46);
+PROVIDE(ESIDAC1R3_L        = 0x0D46);
+PROVIDE(ESIDAC1R3_H        = 0x0D47);
+PROVIDE(ESIDAC1R4          = 0x0D48);
+PROVIDE(ESIDAC1R4_L        = 0x0D48);
+PROVIDE(ESIDAC1R4_H        = 0x0D49);
+PROVIDE(ESIDAC1R5          = 0x0D4A);
+PROVIDE(ESIDAC1R5_L        = 0x0D4A);
+PROVIDE(ESIDAC1R5_H        = 0x0D4B);
+PROVIDE(ESIDAC1R6          = 0x0D4C);
+PROVIDE(ESIDAC1R6_L        = 0x0D4C);
+PROVIDE(ESIDAC1R6_H        = 0x0D4D);
+PROVIDE(ESIDAC1R7          = 0x0D4E);
+PROVIDE(ESIDAC1R7_L        = 0x0D4E);
+PROVIDE(ESIDAC1R7_H        = 0x0D4F);
+PROVIDE(ESIDAC2R0          = 0x0D50);
+PROVIDE(ESIDAC2R0_L        = 0x0D50);
+PROVIDE(ESIDAC2R0_H        = 0x0D51);
+PROVIDE(ESIDAC2R1          = 0x0D52);
+PROVIDE(ESIDAC2R1_L        = 0x0D52);
+PROVIDE(ESIDAC2R1_H        = 0x0D53);
+PROVIDE(ESIDAC2R2          = 0x0D54);
+PROVIDE(ESIDAC2R2_L        = 0x0D54);
+PROVIDE(ESIDAC2R2_H        = 0x0D55);
+PROVIDE(ESIDAC2R3          = 0x0D56);
+PROVIDE(ESIDAC2R3_L        = 0x0D56);
+PROVIDE(ESIDAC2R3_H        = 0x0D57);
+PROVIDE(ESIDAC2R4          = 0x0D58);
+PROVIDE(ESIDAC2R4_L        = 0x0D58);
+PROVIDE(ESIDAC2R4_H        = 0x0D59);
+PROVIDE(ESIDAC2R5          = 0x0D5A);
+PROVIDE(ESIDAC2R5_L        = 0x0D5A);
+PROVIDE(ESIDAC2R5_H        = 0x0D5B);
+PROVIDE(ESIDAC2R6          = 0x0D5C);
+PROVIDE(ESIDAC2R6_L        = 0x0D5C);
+PROVIDE(ESIDAC2R6_H        = 0x0D5D);
+PROVIDE(ESIDAC2R7          = 0x0D5E);
+PROVIDE(ESIDAC2R7_L        = 0x0D5E);
+PROVIDE(ESIDAC2R7_H        = 0x0D5F);
+PROVIDE(ESITSM0            = 0x0D60);
+PROVIDE(ESITSM0_L          = 0x0D60);
+PROVIDE(ESITSM0_H          = 0x0D61);
+PROVIDE(ESITSM1            = 0x0D62);
+PROVIDE(ESITSM1_L          = 0x0D62);
+PROVIDE(ESITSM1_H          = 0x0D63);
+PROVIDE(ESITSM2            = 0x0D64);
+PROVIDE(ESITSM2_L          = 0x0D64);
+PROVIDE(ESITSM2_H          = 0x0D65);
+PROVIDE(ESITSM3            = 0x0D66);
+PROVIDE(ESITSM3_L          = 0x0D66);
+PROVIDE(ESITSM3_H          = 0x0D67);
+PROVIDE(ESITSM4            = 0x0D68);
+PROVIDE(ESITSM4_L          = 0x0D68);
+PROVIDE(ESITSM4_H          = 0x0D69);
+PROVIDE(ESITSM5            = 0x0D6A);
+PROVIDE(ESITSM5_L          = 0x0D6A);
+PROVIDE(ESITSM5_H          = 0x0D6B);
+PROVIDE(ESITSM6            = 0x0D6C);
+PROVIDE(ESITSM6_L          = 0x0D6C);
+PROVIDE(ESITSM6_H          = 0x0D6D);
+PROVIDE(ESITSM7            = 0x0D6E);
+PROVIDE(ESITSM7_L          = 0x0D6E);
+PROVIDE(ESITSM7_H          = 0x0D6F);
+PROVIDE(ESITSM8            = 0x0D70);
+PROVIDE(ESITSM8_L          = 0x0D70);
+PROVIDE(ESITSM8_H          = 0x0D71);
+PROVIDE(ESITSM9            = 0x0D72);
+PROVIDE(ESITSM9_L          = 0x0D72);
+PROVIDE(ESITSM9_H          = 0x0D73);
+PROVIDE(ESITSM10           = 0x0D74);
+PROVIDE(ESITSM10_L         = 0x0D74);
+PROVIDE(ESITSM10_H         = 0x0D75);
+PROVIDE(ESITSM11           = 0x0D76);
+PROVIDE(ESITSM11_L         = 0x0D76);
+PROVIDE(ESITSM11_H         = 0x0D77);
+PROVIDE(ESITSM12           = 0x0D78);
+PROVIDE(ESITSM12_L         = 0x0D78);
+PROVIDE(ESITSM12_H         = 0x0D79);
+PROVIDE(ESITSM13           = 0x0D7A);
+PROVIDE(ESITSM13_L         = 0x0D7A);
+PROVIDE(ESITSM13_H         = 0x0D7B);
+PROVIDE(ESITSM14           = 0x0D7C);
+PROVIDE(ESITSM14_L         = 0x0D7C);
+PROVIDE(ESITSM14_H         = 0x0D7D);
+PROVIDE(ESITSM15           = 0x0D7E);
+PROVIDE(ESITSM15_L         = 0x0D7E);
+PROVIDE(ESITSM15_H         = 0x0D7F);
+PROVIDE(ESITSM16           = 0x0D80);
+PROVIDE(ESITSM16_L         = 0x0D80);
+PROVIDE(ESITSM16_H         = 0x0D81);
+PROVIDE(ESITSM17           = 0x0D82);
+PROVIDE(ESITSM17_L         = 0x0D82);
+PROVIDE(ESITSM17_H         = 0x0D83);
+PROVIDE(ESITSM18           = 0x0D84);
+PROVIDE(ESITSM18_L         = 0x0D84);
+PROVIDE(ESITSM18_H         = 0x0D85);
+PROVIDE(ESITSM19           = 0x0D86);
+PROVIDE(ESITSM19_L         = 0x0D86);
+PROVIDE(ESITSM19_H         = 0x0D87);
+PROVIDE(ESITSM20           = 0x0D88);
+PROVIDE(ESITSM20_L         = 0x0D88);
+PROVIDE(ESITSM20_H         = 0x0D89);
+PROVIDE(ESITSM21           = 0x0D8A);
+PROVIDE(ESITSM21_L         = 0x0D8A);
+PROVIDE(ESITSM21_H         = 0x0D8B);
+PROVIDE(ESITSM22           = 0x0D8C);
+PROVIDE(ESITSM22_L         = 0x0D8C);
+PROVIDE(ESITSM22_H         = 0x0D8D);
+PROVIDE(ESITSM23           = 0x0D8E);
+PROVIDE(ESITSM23_L         = 0x0D8E);
+PROVIDE(ESITSM23_H         = 0x0D8F);
+PROVIDE(ESITSM24           = 0x0D90);
+PROVIDE(ESITSM24_L         = 0x0D90);
+PROVIDE(ESITSM24_H         = 0x0D91);
+PROVIDE(ESITSM25           = 0x0D92);
+PROVIDE(ESITSM25_L         = 0x0D92);
+PROVIDE(ESITSM25_H         = 0x0D93);
+PROVIDE(ESITSM26           = 0x0D94);
+PROVIDE(ESITSM26_L         = 0x0D94);
+PROVIDE(ESITSM26_H         = 0x0D95);
+PROVIDE(ESITSM27           = 0x0D96);
+PROVIDE(ESITSM27_L         = 0x0D96);
+PROVIDE(ESITSM27_H         = 0x0D97);
+PROVIDE(ESITSM28           = 0x0D98);
+PROVIDE(ESITSM28_L         = 0x0D98);
+PROVIDE(ESITSM28_H         = 0x0D99);
+PROVIDE(ESITSM29           = 0x0D9A);
+PROVIDE(ESITSM29_L         = 0x0D9A);
+PROVIDE(ESITSM29_H         = 0x0D9B);
+PROVIDE(ESITSM30           = 0x0D9C);
+PROVIDE(ESITSM30_L         = 0x0D9C);
+PROVIDE(ESITSM30_H         = 0x0D9D);
+PROVIDE(ESITSM31           = 0x0D9E);
+PROVIDE(ESITSM31_L         = 0x0D9E);
+PROVIDE(ESITSM31_H         = 0x0D9F);
+/************************************************************
+* EXTENDED SCAN INTERFACE RAM
+************************************************************/
+PROVIDE(ESIRAM0            = 0x0E00);
+PROVIDE(ESIRAM1            = 0x0E01);
+PROVIDE(ESIRAM2            = 0x0E02);
+PROVIDE(ESIRAM3            = 0x0E03);
+PROVIDE(ESIRAM4            = 0x0E04);
+PROVIDE(ESIRAM5            = 0x0E05);
+PROVIDE(ESIRAM6            = 0x0E06);
+PROVIDE(ESIRAM7            = 0x0E07);
+PROVIDE(ESIRAM8            = 0x0E08);
+PROVIDE(ESIRAM9            = 0x0E09);
+PROVIDE(ESIRAM10           = 0x0E0A);
+PROVIDE(ESIRAM11           = 0x0E0B);
+PROVIDE(ESIRAM12           = 0x0E0C);
+PROVIDE(ESIRAM13           = 0x0E0D);
+PROVIDE(ESIRAM14           = 0x0E0E);
+PROVIDE(ESIRAM15           = 0x0E0F);
+PROVIDE(ESIRAM16           = 0x0E10);
+PROVIDE(ESIRAM17           = 0x0E11);
+PROVIDE(ESIRAM18           = 0x0E12);
+PROVIDE(ESIRAM19           = 0x0E13);
+PROVIDE(ESIRAM20           = 0x0E14);
+PROVIDE(ESIRAM21           = 0x0E15);
+PROVIDE(ESIRAM22           = 0x0E16);
+PROVIDE(ESIRAM23           = 0x0E17);
+PROVIDE(ESIRAM24           = 0x0E18);
+PROVIDE(ESIRAM25           = 0x0E19);
+PROVIDE(ESIRAM26           = 0x0E1A);
+PROVIDE(ESIRAM27           = 0x0E1B);
+PROVIDE(ESIRAM28           = 0x0E1C);
+PROVIDE(ESIRAM29           = 0x0E1D);
+PROVIDE(ESIRAM30           = 0x0E1E);
+PROVIDE(ESIRAM31           = 0x0E1F);
+PROVIDE(ESIRAM32           = 0x0E20);
+PROVIDE(ESIRAM33           = 0x0E21);
+PROVIDE(ESIRAM34           = 0x0E22);
+PROVIDE(ESIRAM35           = 0x0E23);
+PROVIDE(ESIRAM36           = 0x0E24);
+PROVIDE(ESIRAM37           = 0x0E25);
+PROVIDE(ESIRAM38           = 0x0E26);
+PROVIDE(ESIRAM39           = 0x0E27);
+PROVIDE(ESIRAM40           = 0x0E28);
+PROVIDE(ESIRAM41           = 0x0E29);
+PROVIDE(ESIRAM42           = 0x0E2A);
+PROVIDE(ESIRAM43           = 0x0E2B);
+PROVIDE(ESIRAM44           = 0x0E2C);
+PROVIDE(ESIRAM45           = 0x0E2D);
+PROVIDE(ESIRAM46           = 0x0E2E);
+PROVIDE(ESIRAM47           = 0x0E2F);
+PROVIDE(ESIRAM48           = 0x0E30);
+PROVIDE(ESIRAM49           = 0x0E31);
+PROVIDE(ESIRAM50           = 0x0E32);
+PROVIDE(ESIRAM51           = 0x0E33);
+PROVIDE(ESIRAM52           = 0x0E34);
+PROVIDE(ESIRAM53           = 0x0E35);
+PROVIDE(ESIRAM54           = 0x0E36);
+PROVIDE(ESIRAM55           = 0x0E37);
+PROVIDE(ESIRAM56           = 0x0E38);
+PROVIDE(ESIRAM57           = 0x0E39);
+PROVIDE(ESIRAM58           = 0x0E3A);
+PROVIDE(ESIRAM59           = 0x0E3B);
+PROVIDE(ESIRAM60           = 0x0E3C);
+PROVIDE(ESIRAM61           = 0x0E3D);
+PROVIDE(ESIRAM62           = 0x0E3E);
+PROVIDE(ESIRAM63           = 0x0E3F);
+PROVIDE(ESIRAM64           = 0x0E40);
+PROVIDE(ESIRAM65           = 0x0E41);
+PROVIDE(ESIRAM66           = 0x0E42);
+PROVIDE(ESIRAM67           = 0x0E43);
+PROVIDE(ESIRAM68           = 0x0E44);
+PROVIDE(ESIRAM69           = 0x0E45);
+PROVIDE(ESIRAM70           = 0x0E46);
+PROVIDE(ESIRAM71           = 0x0E47);
+PROVIDE(ESIRAM72           = 0x0E48);
+PROVIDE(ESIRAM73           = 0x0E49);
+PROVIDE(ESIRAM74           = 0x0E4A);
+PROVIDE(ESIRAM75           = 0x0E4B);
+PROVIDE(ESIRAM76           = 0x0E4C);
+PROVIDE(ESIRAM77           = 0x0E4D);
+PROVIDE(ESIRAM78           = 0x0E4E);
+PROVIDE(ESIRAM79           = 0x0E4F);
+PROVIDE(ESIRAM80           = 0x0E50);
+PROVIDE(ESIRAM81           = 0x0E51);
+PROVIDE(ESIRAM82           = 0x0E52);
+PROVIDE(ESIRAM83           = 0x0E53);
+PROVIDE(ESIRAM84           = 0x0E54);
+PROVIDE(ESIRAM85           = 0x0E55);
+PROVIDE(ESIRAM86           = 0x0E56);
+PROVIDE(ESIRAM87           = 0x0E57);
+PROVIDE(ESIRAM88           = 0x0E58);
+PROVIDE(ESIRAM89           = 0x0E59);
+PROVIDE(ESIRAM90           = 0x0E5A);
+PROVIDE(ESIRAM91           = 0x0E5B);
+PROVIDE(ESIRAM92           = 0x0E5C);
+PROVIDE(ESIRAM93           = 0x0E5D);
+PROVIDE(ESIRAM94           = 0x0E5E);
+PROVIDE(ESIRAM95           = 0x0E5F);
+PROVIDE(ESIRAM96           = 0x0E60);
+PROVIDE(ESIRAM97           = 0x0E61);
+PROVIDE(ESIRAM98           = 0x0E62);
+PROVIDE(ESIRAM99           = 0x0E63);
+PROVIDE(ESIRAM100          = 0x0E64);
+PROVIDE(ESIRAM101          = 0x0E65);
+PROVIDE(ESIRAM102          = 0x0E66);
+PROVIDE(ESIRAM103          = 0x0E67);
+PROVIDE(ESIRAM104          = 0x0E68);
+PROVIDE(ESIRAM105          = 0x0E69);
+PROVIDE(ESIRAM106          = 0x0E6A);
+PROVIDE(ESIRAM107          = 0x0E6B);
+PROVIDE(ESIRAM108          = 0x0E6C);
+PROVIDE(ESIRAM109          = 0x0E6D);
+PROVIDE(ESIRAM110          = 0x0E6E);
+PROVIDE(ESIRAM111          = 0x0E6F);
+PROVIDE(ESIRAM112          = 0x0E70);
+PROVIDE(ESIRAM113          = 0x0E71);
+PROVIDE(ESIRAM114          = 0x0E72);
+PROVIDE(ESIRAM115          = 0x0E73);
+PROVIDE(ESIRAM116          = 0x0E74);
+PROVIDE(ESIRAM117          = 0x0E75);
+PROVIDE(ESIRAM118          = 0x0E76);
+PROVIDE(ESIRAM119          = 0x0E77);
+PROVIDE(ESIRAM120          = 0x0E78);
+PROVIDE(ESIRAM121          = 0x0E79);
+PROVIDE(ESIRAM122          = 0x0E7A);
+PROVIDE(ESIRAM123          = 0x0E7B);
+PROVIDE(ESIRAM124          = 0x0E7C);
+PROVIDE(ESIRAM125          = 0x0E7D);
+PROVIDE(ESIRAM126          = 0x0E7E);
+PROVIDE(ESIRAM127          = 0x0E7F);
+/*************************************************************
+* FRAM Memory
+*************************************************************/
+PROVIDE(FRCTL0             = 0x0140);
+PROVIDE(FRCTL0_L           = 0x0140);
+PROVIDE(FRCTL0_H           = 0x0141);
+PROVIDE(GCCTL0             = 0x0144);
+PROVIDE(GCCTL0_L           = 0x0144);
+PROVIDE(GCCTL0_H           = 0x0145);
+PROVIDE(GCCTL1             = 0x0146);
+PROVIDE(GCCTL1_L           = 0x0146);
+PROVIDE(GCCTL1_H           = 0x0147);
+/************************************************************
+* LCD_C
+************************************************************/
+PROVIDE(LCDCCTL0           = 0x0A00);
+PROVIDE(LCDCCTL0_L         = 0x0A00);
+PROVIDE(LCDCCTL0_H         = 0x0A01);
+PROVIDE(LCDCCTL1           = 0x0A02);
+PROVIDE(LCDCCTL1_L         = 0x0A02);
+PROVIDE(LCDCCTL1_H         = 0x0A03);
+PROVIDE(LCDCBLKCTL         = 0x0A04);
+PROVIDE(LCDCBLKCTL_L       = 0x0A04);
+PROVIDE(LCDCBLKCTL_H       = 0x0A05);
+PROVIDE(LCDCMEMCTL         = 0x0A06);
+PROVIDE(LCDCMEMCTL_L       = 0x0A06);
+PROVIDE(LCDCMEMCTL_H       = 0x0A07);
+PROVIDE(LCDCVCTL           = 0x0A08);
+PROVIDE(LCDCVCTL_L         = 0x0A08);
+PROVIDE(LCDCVCTL_H         = 0x0A09);
+PROVIDE(LCDCPCTL0          = 0x0A0A);
+PROVIDE(LCDCPCTL0_L        = 0x0A0A);
+PROVIDE(LCDCPCTL0_H        = 0x0A0B);
+PROVIDE(LCDCPCTL1          = 0x0A0C);
+PROVIDE(LCDCPCTL1_L        = 0x0A0C);
+PROVIDE(LCDCPCTL1_H        = 0x0A0D);
+PROVIDE(LCDCPCTL2          = 0x0A0E);
+PROVIDE(LCDCPCTL2_L        = 0x0A0E);
+PROVIDE(LCDCPCTL2_H        = 0x0A0F);
+PROVIDE(LCDCCPCTL          = 0x0A12);
+PROVIDE(LCDCCPCTL_L        = 0x0A12);
+PROVIDE(LCDCCPCTL_H        = 0x0A13);
+PROVIDE(LCDCIV             = 0x0A1E);
+PROVIDE(LCDM1              = 0x0A20);
+PROVIDE(LCDM2              = 0x0A21);
+PROVIDE(LCDM3              = 0x0A22);
+PROVIDE(LCDM4              = 0x0A23);
+PROVIDE(LCDM5              = 0x0A24);
+PROVIDE(LCDM6              = 0x0A25);
+PROVIDE(LCDM7              = 0x0A26);
+PROVIDE(LCDM8              = 0x0A27);
+PROVIDE(LCDM9              = 0x0A28);
+PROVIDE(LCDM10             = 0x0A29);
+PROVIDE(LCDM11             = 0x0A2A);
+PROVIDE(LCDM12             = 0x0A2B);
+PROVIDE(LCDM13             = 0x0A2C);
+PROVIDE(LCDM14             = 0x0A2D);
+PROVIDE(LCDM15             = 0x0A2E);
+PROVIDE(LCDM16             = 0x0A2F);
+PROVIDE(LCDM17             = 0x0A30);
+PROVIDE(LCDM18             = 0x0A31);
+PROVIDE(LCDM19             = 0x0A32);
+PROVIDE(LCDM20             = 0x0A33);
+PROVIDE(LCDM21             = 0x0A34);
+PROVIDE(LCDM22             = 0x0A35);
+PROVIDE(LCDM23             = 0x0A36);
+PROVIDE(LCDM24             = 0x0A37);
+PROVIDE(LCDM25             = 0x0A38);
+PROVIDE(LCDM26             = 0x0A39);
+PROVIDE(LCDM27             = 0x0A3A);
+PROVIDE(LCDM28             = 0x0A3B);
+PROVIDE(LCDM29             = 0x0A3C);
+PROVIDE(LCDM30             = 0x0A3D);
+PROVIDE(LCDM31             = 0x0A3E);
+PROVIDE(LCDM32             = 0x0A3F);
+PROVIDE(LCDM33             = 0x0A40);
+PROVIDE(LCDM34             = 0x0A41);
+PROVIDE(LCDM35             = 0x0A42);
+PROVIDE(LCDM36             = 0x0A43);
+PROVIDE(LCDM37             = 0x0A44);
+PROVIDE(LCDM38             = 0x0A45);
+PROVIDE(LCDM39             = 0x0A46);
+PROVIDE(LCDM40             = 0x0A47);
+PROVIDE(LCDM41             = 0x0A48);
+PROVIDE(LCDM42             = 0x0A49);
+PROVIDE(LCDM43             = 0x0A4A);
+PROVIDE(LCDBM1             = 0x0A40);
+PROVIDE(LCDBM2             = 0x0A41);
+PROVIDE(LCDBM3             = 0x0A42);
+PROVIDE(LCDBM4             = 0x0A43);
+PROVIDE(LCDBM5             = 0x0A44);
+PROVIDE(LCDBM6             = 0x0A45);
+PROVIDE(LCDBM7             = 0x0A46);
+PROVIDE(LCDBM8             = 0x0A47);
+PROVIDE(LCDBM9             = 0x0A48);
+PROVIDE(LCDBM10            = 0x0A49);
+PROVIDE(LCDBM11            = 0x0A4A);
+PROVIDE(LCDBM12            = 0x0A4B);
+PROVIDE(LCDBM13            = 0x0A4C);
+PROVIDE(LCDBM14            = 0x0A4D);
+PROVIDE(LCDBM15            = 0x0A4E);
+PROVIDE(LCDBM16            = 0x0A4F);
+PROVIDE(LCDBM17            = 0x0A50);
+PROVIDE(LCDBM18            = 0x0A51);
+PROVIDE(LCDBM19            = 0x0A52);
+PROVIDE(LCDBM20            = 0x0A53);
+PROVIDE(LCDBM21            = 0x0A54);
+PROVIDE(LCDBM22            = 0x0A55);
+/************************************************************
+* Memory Protection Unit
+************************************************************/
+PROVIDE(MPUCTL0            = 0x05A0);
+PROVIDE(MPUCTL0_L          = 0x05A0);
+PROVIDE(MPUCTL0_H          = 0x05A1);
+PROVIDE(MPUCTL1            = 0x05A2);
+PROVIDE(MPUCTL1_L          = 0x05A2);
+PROVIDE(MPUCTL1_H          = 0x05A3);
+PROVIDE(MPUSEGB2           = 0x05A4);
+PROVIDE(MPUSEGB2_L         = 0x05A4);
+PROVIDE(MPUSEGB2_H         = 0x05A5);
+PROVIDE(MPUSEGB1           = 0x05A6);
+PROVIDE(MPUSEGB1_L         = 0x05A6);
+PROVIDE(MPUSEGB1_H         = 0x05A7);
+PROVIDE(MPUSAM             = 0x05A8);
+PROVIDE(MPUSAM_L           = 0x05A8);
+PROVIDE(MPUSAM_H           = 0x05A9);
+PROVIDE(MPUIPC0            = 0x05AA);
+PROVIDE(MPUIPC0_L          = 0x05AA);
+PROVIDE(MPUIPC0_H          = 0x05AB);
+PROVIDE(MPUIPSEGB2         = 0x05AC);
+PROVIDE(MPUIPSEGB2_L       = 0x05AC);
+PROVIDE(MPUIPSEGB2_H       = 0x05AD);
+PROVIDE(MPUIPSEGB1         = 0x05AE);
+PROVIDE(MPUIPSEGB1_L       = 0x05AE);
+PROVIDE(MPUIPSEGB1_H       = 0x05AF);
+/************************************************************
+* HARDWARE MULTIPLIER 32Bit
+************************************************************/
+PROVIDE(MPY                = 0x04C0);
+PROVIDE(MPY_L              = 0x04C0);
+PROVIDE(MPY_H              = 0x04C1);
+PROVIDE(MPYS               = 0x04C2);
+PROVIDE(MPYS_L             = 0x04C2);
+PROVIDE(MPYS_H             = 0x04C3);
+PROVIDE(MAC                = 0x04C4);
+PROVIDE(MAC_L              = 0x04C4);
+PROVIDE(MAC_H              = 0x04C5);
+PROVIDE(MACS               = 0x04C6);
+PROVIDE(MACS_L             = 0x04C6);
+PROVIDE(MACS_H             = 0x04C7);
+PROVIDE(OP2                = 0x04C8);
+PROVIDE(OP2_L              = 0x04C8);
+PROVIDE(OP2_H              = 0x04C9);
+PROVIDE(RESLO              = 0x04CA);
+PROVIDE(RESLO_L            = 0x04CA);
+PROVIDE(RESLO_H            = 0x04CB);
+PROVIDE(RESHI              = 0x04CC);
+PROVIDE(RESHI_L            = 0x04CC);
+PROVIDE(RESHI_H            = 0x04CD);
+PROVIDE(SUMEXT             = 0x04CE);
+PROVIDE(SUMEXT_L           = 0x04CE);
+PROVIDE(SUMEXT_H           = 0x04CF);
+PROVIDE(MPY32L             = 0x04D0);
+PROVIDE(MPY32L_L           = 0x04D0);
+PROVIDE(MPY32L_H           = 0x04D1);
+PROVIDE(MPY32H             = 0x04D2);
+PROVIDE(MPY32H_L           = 0x04D2);
+PROVIDE(MPY32H_H           = 0x04D3);
+PROVIDE(MPYS32L            = 0x04D4);
+PROVIDE(MPYS32L_L          = 0x04D4);
+PROVIDE(MPYS32L_H          = 0x04D5);
+PROVIDE(MPYS32H            = 0x04D6);
+PROVIDE(MPYS32H_L          = 0x04D6);
+PROVIDE(MPYS32H_H          = 0x04D7);
+PROVIDE(MAC32L             = 0x04D8);
+PROVIDE(MAC32L_L           = 0x04D8);
+PROVIDE(MAC32L_H           = 0x04D9);
+PROVIDE(MAC32H             = 0x04DA);
+PROVIDE(MAC32H_L           = 0x04DA);
+PROVIDE(MAC32H_H           = 0x04DB);
+PROVIDE(MACS32L            = 0x04DC);
+PROVIDE(MACS32L_L          = 0x04DC);
+PROVIDE(MACS32L_H          = 0x04DD);
+PROVIDE(MACS32H            = 0x04DE);
+PROVIDE(MACS32H_L          = 0x04DE);
+PROVIDE(MACS32H_H          = 0x04DF);
+PROVIDE(OP2L               = 0x04E0);
+PROVIDE(OP2L_L             = 0x04E0);
+PROVIDE(OP2L_H             = 0x04E1);
+PROVIDE(OP2H               = 0x04E2);
+PROVIDE(OP2H_L             = 0x04E2);
+PROVIDE(OP2H_H             = 0x04E3);
+PROVIDE(RES0               = 0x04E4);
+PROVIDE(RES0_L             = 0x04E4);
+PROVIDE(RES0_H             = 0x04E5);
+PROVIDE(RES1               = 0x04E6);
+PROVIDE(RES1_L             = 0x04E6);
+PROVIDE(RES1_H             = 0x04E7);
+PROVIDE(RES2               = 0x04E8);
+PROVIDE(RES2_L             = 0x04E8);
+PROVIDE(RES2_H             = 0x04E9);
+PROVIDE(RES3               = 0x04EA);
+PROVIDE(RES3_L             = 0x04EA);
+PROVIDE(RES3_H             = 0x04EB);
+PROVIDE(MPY32CTL0          = 0x04EC);
+PROVIDE(MPY32CTL0_L        = 0x04EC);
+PROVIDE(MPY32CTL0_H        = 0x04ED);
+/************************************************************
+* PMM - Power Management System for FRAM
+************************************************************/
+PROVIDE(PMMCTL0            = 0x0120);
+PROVIDE(PMMCTL0_L          = 0x0120);
+PROVIDE(PMMCTL0_H          = 0x0121);
+PROVIDE(PMMIFG             = 0x012A);
+PROVIDE(PMMIFG_L           = 0x012A);
+PROVIDE(PMMIFG_H           = 0x012B);
+PROVIDE(PM5CTL0            = 0x0130);
+PROVIDE(PM5CTL0_L          = 0x0130);
+PROVIDE(PM5CTL0_H          = 0x0131);
+/************************************************************
+* DIGITAL I/O Port1/2 Pull up / Pull down Resistors
+************************************************************/
+PROVIDE(PAIN               = 0x0200);
+PROVIDE(PAIN_L             = 0x0200);
+PROVIDE(PAIN_H             = 0x0201);
+PROVIDE(PAOUT              = 0x0202);
+PROVIDE(PAOUT_L            = 0x0202);
+PROVIDE(PAOUT_H            = 0x0203);
+PROVIDE(PADIR              = 0x0204);
+PROVIDE(PADIR_L            = 0x0204);
+PROVIDE(PADIR_H            = 0x0205);
+PROVIDE(PAREN              = 0x0206);
+PROVIDE(PAREN_L            = 0x0206);
+PROVIDE(PAREN_H            = 0x0207);
+PROVIDE(PASEL0             = 0x020A);
+PROVIDE(PASEL0_L           = 0x020A);
+PROVIDE(PASEL0_H           = 0x020B);
+PROVIDE(PASEL1             = 0x020C);
+PROVIDE(PASEL1_L           = 0x020C);
+PROVIDE(PASEL1_H           = 0x020D);
+PROVIDE(PASELC             = 0x0216);
+PROVIDE(PASELC_L           = 0x0216);
+PROVIDE(PASELC_H           = 0x0217);
+PROVIDE(PAIES              = 0x0218);
+PROVIDE(PAIES_L            = 0x0218);
+PROVIDE(PAIES_H            = 0x0219);
+PROVIDE(PAIE               = 0x021A);
+PROVIDE(PAIE_L             = 0x021A);
+PROVIDE(PAIE_H             = 0x021B);
+PROVIDE(PAIFG              = 0x021C);
+PROVIDE(PAIFG_L            = 0x021C);
+PROVIDE(PAIFG_H            = 0x021D);
+PROVIDE(P1IV               = 0x020E);
+PROVIDE(P2IV               = 0x021E);
+/************************************************************
+* DIGITAL I/O Port3/4 Pull up / Pull down Resistors
+************************************************************/
+PROVIDE(PBIN               = 0x0220);
+PROVIDE(PBIN_L             = 0x0220);
+PROVIDE(PBIN_H             = 0x0221);
+PROVIDE(PBOUT              = 0x0222);
+PROVIDE(PBOUT_L            = 0x0222);
+PROVIDE(PBOUT_H            = 0x0223);
+PROVIDE(PBDIR              = 0x0224);
+PROVIDE(PBDIR_L            = 0x0224);
+PROVIDE(PBDIR_H            = 0x0225);
+PROVIDE(PBREN              = 0x0226);
+PROVIDE(PBREN_L            = 0x0226);
+PROVIDE(PBREN_H            = 0x0227);
+PROVIDE(PBSEL0             = 0x022A);
+PROVIDE(PBSEL0_L           = 0x022A);
+PROVIDE(PBSEL0_H           = 0x022B);
+PROVIDE(PBSEL1             = 0x022C);
+PROVIDE(PBSEL1_L           = 0x022C);
+PROVIDE(PBSEL1_H           = 0x022D);
+PROVIDE(PBSELC             = 0x0236);
+PROVIDE(PBSELC_L           = 0x0236);
+PROVIDE(PBSELC_H           = 0x0237);
+PROVIDE(PBIES              = 0x0238);
+PROVIDE(PBIES_L            = 0x0238);
+PROVIDE(PBIES_H            = 0x0239);
+PROVIDE(PBIE               = 0x023A);
+PROVIDE(PBIE_L             = 0x023A);
+PROVIDE(PBIE_H             = 0x023B);
+PROVIDE(PBIFG              = 0x023C);
+PROVIDE(PBIFG_L            = 0x023C);
+PROVIDE(PBIFG_H            = 0x023D);
+PROVIDE(P3IV               = 0x022E);
+PROVIDE(P4IV               = 0x023E);
+/************************************************************
+* DIGITAL I/O Port5/6 Pull up / Pull down Resistors
+************************************************************/
+PROVIDE(PCIN               = 0x0240);
+PROVIDE(PCIN_L             = 0x0240);
+PROVIDE(PCIN_H             = 0x0241);
+PROVIDE(PCOUT              = 0x0242);
+PROVIDE(PCOUT_L            = 0x0242);
+PROVIDE(PCOUT_H            = 0x0243);
+PROVIDE(PCDIR              = 0x0244);
+PROVIDE(PCDIR_L            = 0x0244);
+PROVIDE(PCDIR_H            = 0x0245);
+PROVIDE(PCREN              = 0x0246);
+PROVIDE(PCREN_L            = 0x0246);
+PROVIDE(PCREN_H            = 0x0247);
+PROVIDE(PCSEL0             = 0x024A);
+PROVIDE(PCSEL0_L           = 0x024A);
+PROVIDE(PCSEL0_H           = 0x024B);
+PROVIDE(PCSEL1             = 0x024C);
+PROVIDE(PCSEL1_L           = 0x024C);
+PROVIDE(PCSEL1_H           = 0x024D);
+PROVIDE(PCSELC             = 0x0256);
+PROVIDE(PCSELC_L           = 0x0256);
+PROVIDE(PCSELC_H           = 0x0257);
+/************************************************************
+* DIGITAL I/O Port7/8 Pull up / Pull down Resistors
+************************************************************/
+PROVIDE(PDIN               = 0x0260);
+PROVIDE(PDIN_L             = 0x0260);
+PROVIDE(PDIN_H             = 0x0261);
+PROVIDE(PDOUT              = 0x0262);
+PROVIDE(PDOUT_L            = 0x0262);
+PROVIDE(PDOUT_H            = 0x0263);
+PROVIDE(PDDIR              = 0x0264);
+PROVIDE(PDDIR_L            = 0x0264);
+PROVIDE(PDDIR_H            = 0x0265);
+PROVIDE(PDREN              = 0x0266);
+PROVIDE(PDREN_L            = 0x0266);
+PROVIDE(PDREN_H            = 0x0267);
+PROVIDE(PDSEL0             = 0x026A);
+PROVIDE(PDSEL0_L           = 0x026A);
+PROVIDE(PDSEL0_H           = 0x026B);
+PROVIDE(PDSEL1             = 0x026C);
+PROVIDE(PDSEL1_L           = 0x026C);
+PROVIDE(PDSEL1_H           = 0x026D);
+PROVIDE(PDSELC             = 0x0276);
+PROVIDE(PDSELC_L           = 0x0276);
+PROVIDE(PDSELC_H           = 0x0277);
+/************************************************************
+* DIGITAL I/O Port9/10 Pull up / Pull down Resistors
+************************************************************/
+PROVIDE(PEIN               = 0x0280);
+PROVIDE(PEIN_L             = 0x0280);
+PROVIDE(PEIN_H             = 0x0281);
+PROVIDE(PEOUT              = 0x0282);
+PROVIDE(PEOUT_L            = 0x0282);
+PROVIDE(PEOUT_H            = 0x0283);
+PROVIDE(PEDIR              = 0x0284);
+PROVIDE(PEDIR_L            = 0x0284);
+PROVIDE(PEDIR_H            = 0x0285);
+PROVIDE(PEREN              = 0x0286);
+PROVIDE(PEREN_L            = 0x0286);
+PROVIDE(PEREN_H            = 0x0287);
+PROVIDE(PESEL0             = 0x028A);
+PROVIDE(PESEL0_L           = 0x028A);
+PROVIDE(PESEL0_H           = 0x028B);
+PROVIDE(PESEL1             = 0x028C);
+PROVIDE(PESEL1_L           = 0x028C);
+PROVIDE(PESEL1_H           = 0x028D);
+PROVIDE(PESELC             = 0x0296);
+PROVIDE(PESELC_L           = 0x0296);
+PROVIDE(PESELC_H           = 0x0297);
+/************************************************************
+* DIGITAL I/O PortJ Pull up / Pull down Resistors
+************************************************************/
+PROVIDE(PJIN               = 0x0320);
+PROVIDE(PJIN_L             = 0x0320);
+PROVIDE(PJIN_H             = 0x0321);
+PROVIDE(PJOUT              = 0x0322);
+PROVIDE(PJOUT_L            = 0x0322);
+PROVIDE(PJOUT_H            = 0x0323);
+PROVIDE(PJDIR              = 0x0324);
+PROVIDE(PJDIR_L            = 0x0324);
+PROVIDE(PJDIR_H            = 0x0325);
+PROVIDE(PJREN              = 0x0326);
+PROVIDE(PJREN_L            = 0x0326);
+PROVIDE(PJREN_H            = 0x0327);
+PROVIDE(PJSEL0             = 0x032A);
+PROVIDE(PJSEL0_L           = 0x032A);
+PROVIDE(PJSEL0_H           = 0x032B);
+PROVIDE(PJSEL1             = 0x032C);
+PROVIDE(PJSEL1_L           = 0x032C);
+PROVIDE(PJSEL1_H           = 0x032D);
+PROVIDE(PJSELC             = 0x0336);
+PROVIDE(PJSELC_L           = 0x0336);
+PROVIDE(PJSELC_H           = 0x0337);
+/*************************************************************
+* RAM Control Module for FRAM
+*************************************************************/
+PROVIDE(RCCTL0             = 0x0158);
+PROVIDE(RCCTL0_L           = 0x0158);
+PROVIDE(RCCTL0_H           = 0x0159);
+/************************************************************
+* Shared Reference
+************************************************************/
+PROVIDE(REFCTL0            = 0x01B0);
+PROVIDE(REFCTL0_L          = 0x01B0);
+PROVIDE(REFCTL0_H          = 0x01B1);
+/************************************************************
+* Real Time Clock
+************************************************************/
+PROVIDE(RTCCTL0            = 0x04A0);
+PROVIDE(RTCCTL0_L          = 0x04A0);
+PROVIDE(RTCCTL0_H          = 0x04A1);
+PROVIDE(RTCCTL13           = 0x04A2);
+PROVIDE(RTCCTL13_L         = 0x04A2);
+PROVIDE(RTCCTL13_H         = 0x04A3);
+PROVIDE(RTCOCAL            = 0x04A4);
+PROVIDE(RTCOCAL_L          = 0x04A4);
+PROVIDE(RTCOCAL_H          = 0x04A5);
+PROVIDE(RTCTCMP            = 0x04A6);
+PROVIDE(RTCTCMP_L          = 0x04A6);
+PROVIDE(RTCTCMP_H          = 0x04A7);
+PROVIDE(RTCPS0CTL          = 0x04A8);
+PROVIDE(RTCPS0CTL_L        = 0x04A8);
+PROVIDE(RTCPS0CTL_H        = 0x04A9);
+PROVIDE(RTCPS1CTL          = 0x04AA);
+PROVIDE(RTCPS1CTL_L        = 0x04AA);
+PROVIDE(RTCPS1CTL_H        = 0x04AB);
+PROVIDE(RTCPS              = 0x04AC);
+PROVIDE(RTCPS_L            = 0x04AC);
+PROVIDE(RTCPS_H            = 0x04AD);
+PROVIDE(RTCIV              = 0x04AE);
+PROVIDE(RTCTIM0            = 0x04B0);
+PROVIDE(RTCTIM0_L          = 0x04B0);
+PROVIDE(RTCTIM0_H          = 0x04B1);
+PROVIDE(RTCTIM1            = 0x04B2);
+PROVIDE(RTCTIM1_L          = 0x04B2);
+PROVIDE(RTCTIM1_H          = 0x04B3);
+PROVIDE(RTCDATE            = 0x04B4);
+PROVIDE(RTCDATE_L          = 0x04B4);
+PROVIDE(RTCDATE_H          = 0x04B5);
+PROVIDE(RTCYEAR            = 0x04B6);
+PROVIDE(RTCYEAR_L          = 0x04B6);
+PROVIDE(RTCYEAR_H          = 0x04B7);
+PROVIDE(RTCAMINHR          = 0x04B8);
+PROVIDE(RTCAMINHR_L        = 0x04B8);
+PROVIDE(RTCAMINHR_H        = 0x04B9);
+PROVIDE(RTCADOWDAY         = 0x04BA);
+PROVIDE(RTCADOWDAY_L       = 0x04BA);
+PROVIDE(RTCADOWDAY_H       = 0x04BB);
+PROVIDE(BIN2BCD            = 0x04BC);
+PROVIDE(BCD2BIN            = 0x04BE);
+/************************************************************
+* SFR - Special Function Register Module
+************************************************************/
+PROVIDE(SFRIE1             = 0x0100);
+PROVIDE(SFRIE1_L           = 0x0100);
+PROVIDE(SFRIE1_H           = 0x0101);
+PROVIDE(SFRIFG1            = 0x0102);
+PROVIDE(SFRIFG1_L          = 0x0102);
+PROVIDE(SFRIFG1_H          = 0x0103);
+PROVIDE(SFRRPCR            = 0x0104);
+PROVIDE(SFRRPCR_L          = 0x0104);
+PROVIDE(SFRRPCR_H          = 0x0105);
+/************************************************************
+* SYS - System Module
+************************************************************/
+PROVIDE(SYSCTL             = 0x0180);
+PROVIDE(SYSCTL_L           = 0x0180);
+PROVIDE(SYSCTL_H           = 0x0181);
+PROVIDE(SYSJMBC            = 0x0186);
+PROVIDE(SYSJMBC_L          = 0x0186);
+PROVIDE(SYSJMBC_H          = 0x0187);
+PROVIDE(SYSJMBI0           = 0x0188);
+PROVIDE(SYSJMBI0_L         = 0x0188);
+PROVIDE(SYSJMBI0_H         = 0x0189);
+PROVIDE(SYSJMBI1           = 0x018A);
+PROVIDE(SYSJMBI1_L         = 0x018A);
+PROVIDE(SYSJMBI1_H         = 0x018B);
+PROVIDE(SYSJMBO0           = 0x018C);
+PROVIDE(SYSJMBO0_L         = 0x018C);
+PROVIDE(SYSJMBO0_H         = 0x018D);
+PROVIDE(SYSJMBO1           = 0x018E);
+PROVIDE(SYSJMBO1_L         = 0x018E);
+PROVIDE(SYSJMBO1_H         = 0x018F);
+PROVIDE(SYSUNIV            = 0x019A);
+PROVIDE(SYSUNIV_L          = 0x019A);
+PROVIDE(SYSUNIV_H          = 0x019B);
+PROVIDE(SYSSNIV            = 0x019C);
+PROVIDE(SYSSNIV_L          = 0x019C);
+PROVIDE(SYSSNIV_H          = 0x019D);
+PROVIDE(SYSRSTIV           = 0x019E);
+PROVIDE(SYSRSTIV_L         = 0x019E);
+PROVIDE(SYSRSTIV_H         = 0x019F);
+/************************************************************
+* Timer0_A3
+************************************************************/
+PROVIDE(TA0CTL             = 0x0340);
+PROVIDE(TA0CCTL0           = 0x0342);
+PROVIDE(TA0CCTL1           = 0x0344);
+PROVIDE(TA0CCTL2           = 0x0346);
+PROVIDE(TA0R               = 0x0350);
+PROVIDE(TA0CCR0            = 0x0352);
+PROVIDE(TA0CCR1            = 0x0354);
+PROVIDE(TA0CCR2            = 0x0356);
+PROVIDE(TA0IV              = 0x036E);
+PROVIDE(TA0EX0             = 0x0360);
+/************************************************************
+* Timer1_A3
+************************************************************/
+PROVIDE(TA1CTL             = 0x0380);
+PROVIDE(TA1CCTL0           = 0x0382);
+PROVIDE(TA1CCTL1           = 0x0384);
+PROVIDE(TA1CCTL2           = 0x0386);
+PROVIDE(TA1R               = 0x0390);
+PROVIDE(TA1CCR0            = 0x0392);
+PROVIDE(TA1CCR1            = 0x0394);
+PROVIDE(TA1CCR2            = 0x0396);
+PROVIDE(TA1IV              = 0x03AE);
+PROVIDE(TA1EX0             = 0x03A0);
+/************************************************************
+* Timer2_A2
+************************************************************/
+PROVIDE(TA2CTL             = 0x0400);
+PROVIDE(TA2CCTL0           = 0x0402);
+PROVIDE(TA2CCTL1           = 0x0404);
+PROVIDE(TA2R               = 0x0410);
+PROVIDE(TA2CCR0            = 0x0412);
+PROVIDE(TA2CCR1            = 0x0414);
+PROVIDE(TA2IV              = 0x042E);
+PROVIDE(TA2EX0             = 0x0420);
+/************************************************************
+* Timer3_A5
+************************************************************/
+PROVIDE(TA3CTL             = 0x0440);
+PROVIDE(TA3CCTL0           = 0x0442);
+PROVIDE(TA3CCTL1           = 0x0444);
+PROVIDE(TA3CCTL2           = 0x0446);
+PROVIDE(TA3CCTL3           = 0x0448);
+PROVIDE(TA3CCTL4           = 0x044A);
+PROVIDE(TA3R               = 0x0450);
+PROVIDE(TA3CCR0            = 0x0452);
+PROVIDE(TA3CCR1            = 0x0454);
+PROVIDE(TA3CCR2            = 0x0456);
+PROVIDE(TA3CCR3            = 0x0458);
+PROVIDE(TA3CCR4            = 0x045A);
+PROVIDE(TA3IV              = 0x046E);
+PROVIDE(TA3EX0             = 0x0460);
+/************************************************************
+* Timer0_B7
+************************************************************/
+PROVIDE(TB0CTL             = 0x03C0);
+PROVIDE(TB0CCTL0           = 0x03C2);
+PROVIDE(TB0CCTL1           = 0x03C4);
+PROVIDE(TB0CCTL2           = 0x03C6);
+PROVIDE(TB0CCTL3           = 0x03C8);
+PROVIDE(TB0CCTL4           = 0x03CA);
+PROVIDE(TB0CCTL5           = 0x03CC);
+PROVIDE(TB0CCTL6           = 0x03CE);
+PROVIDE(TB0R               = 0x03D0);
+PROVIDE(TB0CCR0            = 0x03D2);
+PROVIDE(TB0CCR1            = 0x03D4);
+PROVIDE(TB0CCR2            = 0x03D6);
+PROVIDE(TB0CCR3            = 0x03D8);
+PROVIDE(TB0CCR4            = 0x03DA);
+PROVIDE(TB0CCR5            = 0x03DC);
+PROVIDE(TB0CCR6            = 0x03DE);
+PROVIDE(TB0EX0             = 0x03E0);
+PROVIDE(TB0IV              = 0x03EE);
+/************************************************************
+* USCI A0
+************************************************************/
+PROVIDE(UCA0CTLW0          = 0x05C0);
+PROVIDE(UCA0CTLW0_L        = 0x05C0);
+PROVIDE(UCA0CTLW0_H        = 0x05C1);
+PROVIDE(UCA0CTLW1          = 0x05C2);
+PROVIDE(UCA0CTLW1_L        = 0x05C2);
+PROVIDE(UCA0CTLW1_H        = 0x05C3);
+PROVIDE(UCA0BRW            = 0x05C6);
+PROVIDE(UCA0BRW_L          = 0x05C6);
+PROVIDE(UCA0BRW_H          = 0x05C7);
+PROVIDE(UCA0MCTLW          = 0x05C8);
+PROVIDE(UCA0MCTLW_L        = 0x05C8);
+PROVIDE(UCA0MCTLW_H        = 0x05C9);
+PROVIDE(UCA0STATW          = 0x05CA);
+PROVIDE(UCA0RXBUF          = 0x05CC);
+PROVIDE(UCA0RXBUF_L        = 0x05CC);
+PROVIDE(UCA0RXBUF_H        = 0x05CD);
+PROVIDE(UCA0TXBUF          = 0x05CE);
+PROVIDE(UCA0TXBUF_L        = 0x05CE);
+PROVIDE(UCA0TXBUF_H        = 0x05CF);
+PROVIDE(UCA0ABCTL          = 0x05D0);
+PROVIDE(UCA0IRCTL          = 0x05D2);
+PROVIDE(UCA0IRCTL_L        = 0x05D2);
+PROVIDE(UCA0IRCTL_H        = 0x05D3);
+PROVIDE(UCA0IE             = 0x05DA);
+PROVIDE(UCA0IE_L           = 0x05DA);
+PROVIDE(UCA0IE_H           = 0x05DB);
+PROVIDE(UCA0IFG            = 0x05DC);
+PROVIDE(UCA0IFG_L          = 0x05DC);
+PROVIDE(UCA0IFG_H          = 0x05DD);
+PROVIDE(UCA0IV             = 0x05DE);
+/************************************************************
+* USCI A1
+************************************************************/
+PROVIDE(UCA1CTLW0          = 0x05E0);
+PROVIDE(UCA1CTLW0_L        = 0x05E0);
+PROVIDE(UCA1CTLW0_H        = 0x05E1);
+PROVIDE(UCA1CTLW1          = 0x05E2);
+PROVIDE(UCA1CTLW1_L        = 0x05E2);
+PROVIDE(UCA1CTLW1_H        = 0x05E3);
+PROVIDE(UCA1BRW            = 0x05E6);
+PROVIDE(UCA1BRW_L          = 0x05E6);
+PROVIDE(UCA1BRW_H          = 0x05E7);
+PROVIDE(UCA1MCTLW          = 0x05E8);
+PROVIDE(UCA1MCTLW_L        = 0x05E8);
+PROVIDE(UCA1MCTLW_H        = 0x05E9);
+PROVIDE(UCA1STATW          = 0x05EA);
+PROVIDE(UCA1RXBUF          = 0x05EC);
+PROVIDE(UCA1RXBUF_L        = 0x05EC);
+PROVIDE(UCA1RXBUF_H        = 0x05ED);
+PROVIDE(UCA1TXBUF          = 0x05EE);
+PROVIDE(UCA1TXBUF_L        = 0x05EE);
+PROVIDE(UCA1TXBUF_H        = 0x05EF);
+PROVIDE(UCA1ABCTL          = 0x05F0);
+PROVIDE(UCA1IRCTL          = 0x05F2);
+PROVIDE(UCA1IRCTL_L        = 0x05F2);
+PROVIDE(UCA1IRCTL_H        = 0x05F3);
+PROVIDE(UCA1IE             = 0x05FA);
+PROVIDE(UCA1IE_L           = 0x05FA);
+PROVIDE(UCA1IE_H           = 0x05FB);
+PROVIDE(UCA1IFG            = 0x05FC);
+PROVIDE(UCA1IFG_L          = 0x05FC);
+PROVIDE(UCA1IFG_H          = 0x05FD);
+PROVIDE(UCA1IV             = 0x05FE);
+/************************************************************
+* USCI B0
+************************************************************/
+PROVIDE(UCB0CTLW0          = 0x0640);
+PROVIDE(UCB0CTLW0_L        = 0x0640);
+PROVIDE(UCB0CTLW0_H        = 0x0641);
+PROVIDE(UCB0CTLW1          = 0x0642);
+PROVIDE(UCB0CTLW1_L        = 0x0642);
+PROVIDE(UCB0CTLW1_H        = 0x0643);
+PROVIDE(UCB0BRW            = 0x0646);
+PROVIDE(UCB0BRW_L          = 0x0646);
+PROVIDE(UCB0BRW_H          = 0x0647);
+PROVIDE(UCB0STATW          = 0x0648);
+PROVIDE(UCB0STATW_L        = 0x0648);
+PROVIDE(UCB0STATW_H        = 0x0649);
+PROVIDE(UCB0TBCNT          = 0x064A);
+PROVIDE(UCB0TBCNT_L        = 0x064A);
+PROVIDE(UCB0TBCNT_H        = 0x064B);
+PROVIDE(UCB0RXBUF          = 0x064C);
+PROVIDE(UCB0RXBUF_L        = 0x064C);
+PROVIDE(UCB0RXBUF_H        = 0x064D);
+PROVIDE(UCB0TXBUF          = 0x064E);
+PROVIDE(UCB0TXBUF_L        = 0x064E);
+PROVIDE(UCB0TXBUF_H        = 0x064F);
+PROVIDE(UCB0I2COA0         = 0x0654);
+PROVIDE(UCB0I2COA0_L       = 0x0654);
+PROVIDE(UCB0I2COA0_H       = 0x0655);
+PROVIDE(UCB0I2COA1         = 0x0656);
+PROVIDE(UCB0I2COA1_L       = 0x0656);
+PROVIDE(UCB0I2COA1_H       = 0x0657);
+PROVIDE(UCB0I2COA2         = 0x0658);
+PROVIDE(UCB0I2COA2_L       = 0x0658);
+PROVIDE(UCB0I2COA2_H       = 0x0659);
+PROVIDE(UCB0I2COA3         = 0x065A);
+PROVIDE(UCB0I2COA3_L       = 0x065A);
+PROVIDE(UCB0I2COA3_H       = 0x065B);
+PROVIDE(UCB0ADDRX          = 0x065C);
+PROVIDE(UCB0ADDRX_L        = 0x065C);
+PROVIDE(UCB0ADDRX_H        = 0x065D);
+PROVIDE(UCB0ADDMASK        = 0x065E);
+PROVIDE(UCB0ADDMASK_L      = 0x065E);
+PROVIDE(UCB0ADDMASK_H      = 0x065F);
+PROVIDE(UCB0I2CSA          = 0x0660);
+PROVIDE(UCB0I2CSA_L        = 0x0660);
+PROVIDE(UCB0I2CSA_H        = 0x0661);
+PROVIDE(UCB0IE             = 0x066A);
+PROVIDE(UCB0IE_L           = 0x066A);
+PROVIDE(UCB0IE_H           = 0x066B);
+PROVIDE(UCB0IFG            = 0x066C);
+PROVIDE(UCB0IFG_L          = 0x066C);
+PROVIDE(UCB0IFG_H          = 0x066D);
+PROVIDE(UCB0IV             = 0x066E);
+/************************************************************
+* USCI B1
+************************************************************/
+PROVIDE(UCB1CTLW0          = 0x0680);
+PROVIDE(UCB1CTLW0_L        = 0x0680);
+PROVIDE(UCB1CTLW0_H        = 0x0681);
+PROVIDE(UCB1CTLW1          = 0x0682);
+PROVIDE(UCB1CTLW1_L        = 0x0682);
+PROVIDE(UCB1CTLW1_H        = 0x0683);
+PROVIDE(UCB1BRW            = 0x0686);
+PROVIDE(UCB1BRW_L          = 0x0686);
+PROVIDE(UCB1BRW_H          = 0x0687);
+PROVIDE(UCB1STATW          = 0x0688);
+PROVIDE(UCB1STATW_L        = 0x0688);
+PROVIDE(UCB1STATW_H        = 0x0689);
+PROVIDE(UCB1TBCNT          = 0x068A);
+PROVIDE(UCB1TBCNT_L        = 0x068A);
+PROVIDE(UCB1TBCNT_H        = 0x068B);
+PROVIDE(UCB1RXBUF          = 0x068C);
+PROVIDE(UCB1RXBUF_L        = 0x068C);
+PROVIDE(UCB1RXBUF_H        = 0x068D);
+PROVIDE(UCB1TXBUF          = 0x068E);
+PROVIDE(UCB1TXBUF_L        = 0x068E);
+PROVIDE(UCB1TXBUF_H        = 0x068F);
+PROVIDE(UCB1I2COA0         = 0x0694);
+PROVIDE(UCB1I2COA0_L       = 0x0694);
+PROVIDE(UCB1I2COA0_H       = 0x0695);
+PROVIDE(UCB1I2COA1         = 0x0696);
+PROVIDE(UCB1I2COA1_L       = 0x0696);
+PROVIDE(UCB1I2COA1_H       = 0x0697);
+PROVIDE(UCB1I2COA2         = 0x0698);
+PROVIDE(UCB1I2COA2_L       = 0x0698);
+PROVIDE(UCB1I2COA2_H       = 0x0699);
+PROVIDE(UCB1I2COA3         = 0x069A);
+PROVIDE(UCB1I2COA3_L       = 0x069A);
+PROVIDE(UCB1I2COA3_H       = 0x069B);
+PROVIDE(UCB1ADDRX          = 0x069C);
+PROVIDE(UCB1ADDRX_L        = 0x069C);
+PROVIDE(UCB1ADDRX_H        = 0x069D);
+PROVIDE(UCB1ADDMASK        = 0x069E);
+PROVIDE(UCB1ADDMASK_L      = 0x069E);
+PROVIDE(UCB1ADDMASK_H      = 0x069F);
+PROVIDE(UCB1I2CSA          = 0x06A0);
+PROVIDE(UCB1I2CSA_L        = 0x06A0);
+PROVIDE(UCB1I2CSA_H        = 0x06A1);
+PROVIDE(UCB1IE             = 0x06AA);
+PROVIDE(UCB1IE_L           = 0x06AA);
+PROVIDE(UCB1IE_H           = 0x06AB);
+PROVIDE(UCB1IFG            = 0x06AC);
+PROVIDE(UCB1IFG_L          = 0x06AC);
+PROVIDE(UCB1IFG_H          = 0x06AD);
+PROVIDE(UCB1IV             = 0x06AE);
+/************************************************************
+* WATCHDOG TIMER A
+************************************************************/
+PROVIDE(WDTCTL             = 0x015C);
+PROVIDE(WDTCTL_L           = 0x015C);
+PROVIDE(WDTCTL_H           = 0x015D);
+/************************************************************
+* TLV Descriptors
+************************************************************/
+/************************************************************
+* Interrupt Vectors (offset from 0xFF80 + 0x10 for Password)
+************************************************************/
+/************************************************************
+* End of Modules
+************************************************************/
diff --git a/os/common/startup/MSP430X/compilers/GCC/mk/startup_msp430fr5xxx.mk b/os/common/startup/MSP430X/compilers/GCC/mk/startup_msp430fr5xxx.mk
index 9c063cd..022bf9f 100644
--- a/os/common/startup/MSP430X/compilers/GCC/mk/startup_msp430fr5xxx.mk
+++ b/os/common/startup/MSP430X/compilers/GCC/mk/startup_msp430fr5xxx.mk
@@ -1,10 +1,11 @@
 # List of the ChibiOS generic MSP430X startup and linker files.

-STARTUPSRC = 

+STARTUPSRC =

 #$(CHIBIOS_CONTRIB)/os/common/startup/MSP430X/compilers/GCC/vectors.c

-             

-STARTUPASM = 

 

-STARTUPINC = $(CHIBIOS_CONTRIB)/os/common/startup/MSP430X/compilers/GCC

+STARTUPASM =

+

+STARTUPINC = $(CHIBIOS_CONTRIB)/os/common/startup/MSP430X/compilers/GCC \

+$(CHIBIOS_CONTRIB)/os/common/ext/MSP430/inc

 

 STARTUPLD  = $(CHIBIOS_CONTRIB)/os/common/startup/MSP430X/compilers/GCC/ld

 

diff --git a/os/hal/boards/EXP430FR5969/board.c b/os/hal/boards/EXP430FR5969/board.c
index ac48ba0..0643cce 100644
--- a/os/hal/boards/EXP430FR5969/board.c
+++ b/os/hal/boards/EXP430FR5969/board.c
@@ -25,11 +25,11 @@
 const PALConfig pal_default_config =

 {

   {VAL_IOPORT1_OUT, VAL_IOPORT1_DIR, VAL_IOPORT1_REN, VAL_IOPORT1_SEL0, 

-    VAL_IOPORT1_SEL1, VAL_IOPORT1_IES, VAL_IOPORT1_IE},

+    VAL_IOPORT1_SEL1},

   {VAL_IOPORT2_OUT, VAL_IOPORT2_DIR, VAL_IOPORT2_REN, VAL_IOPORT2_SEL0, 

-    VAL_IOPORT2_SEL1, VAL_IOPORT2_IES, VAL_IOPORT2_IE},

+    VAL_IOPORT2_SEL1},

   {VAL_IOPORT0_OUT, VAL_IOPORT0_DIR, VAL_IOPORT0_REN, VAL_IOPORT0_SEL0, 

-    VAL_IOPORT0_SEL1, VAL_IOPORT0_IES, VAL_IOPORT0_IE}

+    VAL_IOPORT0_SEL1}

 }; /* Set UART TX pin correctly */

 #endif /* HAL_USE_PAL */

 

diff --git a/os/hal/boards/EXP430FR5969/board.h b/os/hal/boards/EXP430FR5969/board.h
index 97103d3..3abe1cc 100644
--- a/os/hal/boards/EXP430FR5969/board.h
+++ b/os/hal/boards/EXP430FR5969/board.h
@@ -65,8 +65,6 @@
 #define VAL_IOPORT1_REN   0xFCFE

 #define VAL_IOPORT1_SEL0  0x0000

 #define VAL_IOPORT1_SEL1  0x0300

-#define VAL_IOPORT1_IES   0x0000

-#define VAL_IOPORT1_IE    0x0000

 

 /*

  * Port B setup:

@@ -93,8 +91,6 @@
 #define VAL_IOPORT2_REN   0xBDFF

 #define VAL_IOPORT2_SEL0  0x0000

 #define VAL_IOPORT2_SEL1  0x0000

-#define VAL_IOPORT2_IES   0x0000

-#define VAL_IOPORT2_IE    0x0000

 

 /*

  * Port J setup:

@@ -113,8 +109,6 @@
 #define VAL_IOPORT0_REN   0x00CF

 #define VAL_IOPORT0_SEL0  0x0030

 #define VAL_IOPORT0_SEL1  0x0000

-#define VAL_IOPORT0_IES   0x0000

-#define VAL_IOPORT0_IE    0x0000

 

 #if !defined(_FROM_ASM_)

 #ifdef __cplusplus

diff --git a/os/hal/boards/EXP430FR6989/board.c b/os/hal/boards/EXP430FR6989/board.c
index a6836cf..475a2ea 100644
--- a/os/hal/boards/EXP430FR6989/board.c
+++ b/os/hal/boards/EXP430FR6989/board.c
@@ -25,17 +25,17 @@
 const PALConfig pal_default_config =

 {

   {VAL_IOPORT1_OUT, VAL_IOPORT1_DIR, VAL_IOPORT1_REN, VAL_IOPORT1_SEL0, 

-    VAL_IOPORT1_SEL1, VAL_IOPORT1_IES, VAL_IOPORT1_IE},

+    VAL_IOPORT1_SEL1},

   {VAL_IOPORT2_OUT, VAL_IOPORT2_DIR, VAL_IOPORT2_REN, VAL_IOPORT2_SEL0, 

-    VAL_IOPORT2_SEL1, VAL_IOPORT2_IES, VAL_IOPORT2_IE},

+    VAL_IOPORT2_SEL1},

   {VAL_IOPORT3_OUT, VAL_IOPORT3_DIR, VAL_IOPORT3_REN, VAL_IOPORT3_SEL0, 

-    VAL_IOPORT3_SEL1, VAL_IOPORT3_IES, VAL_IOPORT3_IE},

+    VAL_IOPORT3_SEL1},

   {VAL_IOPORT4_OUT, VAL_IOPORT4_DIR, VAL_IOPORT4_REN, VAL_IOPORT4_SEL0, 

-    VAL_IOPORT4_SEL1, VAL_IOPORT4_IES, VAL_IOPORT4_IE},

+    VAL_IOPORT4_SEL1},

   {VAL_IOPORT5_OUT, VAL_IOPORT5_DIR, VAL_IOPORT5_REN, VAL_IOPORT5_SEL0, 

-    VAL_IOPORT5_SEL1, VAL_IOPORT5_IES, VAL_IOPORT5_IE},

+    VAL_IOPORT5_SEL1},

   {VAL_IOPORT0_OUT, VAL_IOPORT0_DIR, VAL_IOPORT0_REN, VAL_IOPORT0_SEL0, 

-    VAL_IOPORT0_SEL1, VAL_IOPORT0_IES, VAL_IOPORT0_IE}

+    VAL_IOPORT0_SEL1}

 }; /* Set UART TX pin correctly */

 #endif /* HAL_USE_PAL */

 

diff --git a/os/hal/boards/EXP430FR6989/board.h b/os/hal/boards/EXP430FR6989/board.h
index 83b8fbb..d5afe29 100644
--- a/os/hal/boards/EXP430FR6989/board.h
+++ b/os/hal/boards/EXP430FR6989/board.h
@@ -69,8 +69,6 @@
 #define VAL_IOPORT1_REN   0xFFFE

 #define VAL_IOPORT1_SEL0  0x0000

 #define VAL_IOPORT1_SEL1  0x0000

-#define VAL_IOPORT1_IES   0x0006

-#define VAL_IOPORT1_IE    0x0006

 

 /*

  * Port B setup:

@@ -97,8 +95,6 @@
 #define VAL_IOPORT2_REN   0xFFCF

 #define VAL_IOPORT2_SEL0  0x0030

 #define VAL_IOPORT2_SEL1  0x0000

-#define VAL_IOPORT2_IES   0x0000

-#define VAL_IOPORT2_IE    0x0000

 

 /*

  * Port C setup:

@@ -125,8 +121,6 @@
 #define VAL_IOPORT3_REN   0xFFFF

 #define VAL_IOPORT3_SEL0  0x0000

 #define VAL_IOPORT3_SEL1  0x0000

-#define VAL_IOPORT3_IES   0x0000

-#define VAL_IOPORT3_IE    0x0000

 

 /*

  * Port D setup:

@@ -153,11 +147,9 @@
 #define VAL_IOPORT4_REN   0xFFFF

 #define VAL_IOPORT4_SEL0  0x0000

 #define VAL_IOPORT4_SEL1  0x0000

-#define VAL_IOPORT4_IES   0x0000

-#define VAL_IOPORT4_IE    0x0000

 

 /*

- * Port D setup:

+ * Port E setup:

  * 

  * P9.0 - BoosterPack BP27        (input pullup)

  * P9.1 - BoosterPack BP28        (input pullup)

@@ -181,8 +173,6 @@
 #define VAL_IOPORT5_REN   0xFF7F

 #define VAL_IOPORT5_SEL0  0x0000

 #define VAL_IOPORT5_SEL1  0x0000

-#define VAL_IOPORT5_IES   0x0000

-#define VAL_IOPORT5_IE    0x0000

 

 /*

  * Port J setup:

@@ -201,8 +191,6 @@
 #define VAL_IOPORT0_REN   0x00CF

 #define VAL_IOPORT0_SEL0  0x0030

 #define VAL_IOPORT0_SEL1  0x0000

-#define VAL_IOPORT0_IES   0x0000

-#define VAL_IOPORT0_IE    0x0000

 

 #if !defined(_FROM_ASM_)

 #ifdef __cplusplus

diff --git a/os/hal/boards/MICROBIT/board.c b/os/hal/boards/MICROBIT/board.c
new file mode 100644
index 0000000..12f78e2
--- /dev/null
+++ b/os/hal/boards/MICROBIT/board.c
@@ -0,0 +1,91 @@
+/*
+    Copyright (C) 2017 Stéphane D'Alu
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+
+/* RAM Banks
+ *  (Values are defined in Nordic gcc_startup_nrf51.s)
+ */
+#define NRF_POWER_RAMON_ADDRESS 0x40000524
+#define NRF_POWER_RAMONB_ADDRESS 0x40000554
+#define NRF_POWER_RAMONx_RAMxON_ONMODE_Msk 0x3
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+    .pads = {
+        PAL_MODE_OUTPUT_OPENDRAIN,    /* P0.0 : SCL      P19   */
+        PAL_MODE_UNCONNECTED,         /* P0.1 : PAD1     P2    */
+        PAL_MODE_UNCONNECTED,         /* P0.2 : PAD2     P1    */
+        PAL_MODE_UNCONNECTED,         /* P0.3 : PAD3     P0    */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.4 : COL1     P3    */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.5 : COL2     P4    */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.6 : COL3     P10   */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.7 : COL4           */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.8 : COL5           */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.9 : COL6           */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.10: COL7     P9    */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.11: COL8     P7    */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.12: COL9     P6    */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.13: ROW1           */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.14: ROW2           */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.15: ROW3           */
+        PAL_MODE_UNCONNECTED,         /* P0.16           P16   */
+        PAL_MODE_INPUT,               /* P0.17: BTN_A    P5    */
+        PAL_MODE_UNCONNECTED,         /* P0.18           P8    */
+        PAL_MODE_INPUT,               /* P0.19: BTN_RST        */
+        PAL_MODE_UNCONNECTED,         /* P0.20           P12   */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.21: SPI_MOSI P15   */
+        PAL_MODE_INPUT_PULLUP,        /* P0.22: SPI_MISO P14   */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.23: SPI_SCK  P13   */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.24: UART_TX        */
+        PAL_MODE_INPUT_PULLUP,        /* P0.25: UART_RX        */
+        PAL_MODE_INPUT,               /* P0.26: BTN_B    P11   */
+        PAL_MODE_INPUT,               /* P0.27: ACC_INT2       */
+        PAL_MODE_INPUT,               /* P0.28: ACC_INT1       */
+        PAL_MODE_INPUT,               /* P0.29: MAG_INT1       */
+        PAL_MODE_OUTPUT_OPENDRAIN,    /* P0.30: SDA      P20   */
+        PAL_MODE_UNCONNECTED,         /* P0.31                 */
+  },
+};
+#endif
+
+/**
+ * @brief   Early initialization code.
+ * @details This initialization is performed just after reset before BSS and
+ *          DATA segments initialization.
+ */
+void __early_init(void)
+{
+  /* Make sure ALL RAM banks are powered on */
+  *(uint32_t *)NRF_POWER_RAMON_ADDRESS  |= NRF_POWER_RAMONx_RAMxON_ONMODE_Msk;
+  *(uint32_t *)NRF_POWER_RAMONB_ADDRESS |= NRF_POWER_RAMONx_RAMxON_ONMODE_Msk;
+}
+
+/**
+ * @brief   Late initialization code.
+ * @note    This initialization is performed after BSS and DATA segments
+ *          initialization and before invoking the main() function.
+ */
+void boardInit(void)
+{
+}
diff --git a/os/hal/boards/MICROBIT/board.h b/os/hal/boards/MICROBIT/board.h
new file mode 100644
index 0000000..157bd75
--- /dev/null
+++ b/os/hal/boards/MICROBIT/board.h
@@ -0,0 +1,147 @@
+/*
+    Copyright (C) 2016 Stephane D'Alu
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * See: https://www.microbit.co.uk/device/pins
+ *      https://lancaster-university.github.io/microbit-docs/ubit/display/
+ */
+
+/* Board identifier. */
+#define BOARD_MICROBIT
+#define BOARD_NAME              "micro:bit"
+
+/* Board oscillators-related settings. */
+#define NRF51_XTAL_VALUE        16000000
+#define NRF51_LFCLK_SOURCE      0  /* RC oscillator */
+
+/*
+ * IO pins assignments.
+ */
+#define IOPORT1_P0              3U
+#define IOPORT1_P1              2U
+#define IOPORT1_P2              1U
+#define IOPORT1_P3              4U
+#define IOPORT1_P4              5U
+#define IOPORT1_P5             17U
+#define IOPORT1_P6             12U
+#define IOPORT1_P7             11U
+#define IOPORT1_P8             18U
+#define IOPORT1_P9             10U
+#define IOPORT1_P10             6U
+#define IOPORT1_P11            26U
+#define IOPORT1_P12            20U
+#define IOPORT1_P13            23U
+#define IOPORT1_P14            22U
+#define IOPORT1_P15            21U
+#define IOPORT1_P16            16U
+#define IOPORT1_P19             0U
+#define IOPORT1_P20            30U
+#define IOPORT1_BTN_A          17U
+#define IOPORT1_BTN_B          26U
+#define IOPORT1_BTN_RST        19U  
+#define IOPORT1_LED_COL_1       4U
+#define IOPORT1_LED_COL_2       5U
+#define IOPORT1_LED_COL_3       6U
+#define IOPORT1_LED_COL_4       7U
+#define IOPORT1_LED_COL_5       8U
+#define IOPORT1_LED_COL_6       9U
+#define IOPORT1_LED_COL_7      10U
+#define IOPORT1_LED_COL_8      11U
+#define IOPORT1_LED_COL_9      12U
+#define IOPORT1_LED_ROW_1      13U
+#define IOPORT1_LED_ROW_2      14U
+#define IOPORT1_LED_ROW_3      15U
+#define IOPORT1_PAD_0             IOPORT1_P0
+#define IOPORT1_PAD_1             IOPORT1_P1
+#define IOPORT1_PAD_2             IOPORT1_P2
+#define IOPORT1_SPI_MOSI       21U
+#define IOPORT1_SPI_MISO       22U
+#define IOPORT1_SPI_SCK        23U
+#define IOPORT1_I2C_SCL         0U
+#define IOPORT1_I2C_SDA        30U
+#define IOPORT1_UART_TX        24U
+#define IOPORT1_UART_RX        25U
+#define IOPORT1_ACC_INT1       28U
+#define IOPORT1_ACC_INT2       27U
+#define IOPORT1_MAG_INT1       29U
+
+
+/*
+ * IO lines assignments.
+ */
+#define LINE_P0                PAL_LINE(IOPORT1, IOPORT1_P0)
+#define LINE_P1                PAL_LINE(IOPORT1, IOPORT1_P1)
+#define LINE_P2                PAL_LINE(IOPORT1, IOPORT1_P2)
+#define LINE_P3                PAL_LINE(IOPORT1, IOPORT1_P3)
+#define LINE_P4                PAL_LINE(IOPORT1, IOPORT1_P4)
+#define LINE_P5                PAL_LINE(IOPORT1, IOPORT1_P5)
+#define LINE_P6                PAL_LINE(IOPORT1, IOPORT1_P6)
+#define LINE_P7                PAL_LINE(IOPORT1, IOPORT1_P7)
+#define LINE_P8                PAL_LINE(IOPORT1, IOPORT1_P8)
+#define LINE_P9                PAL_LINE(IOPORT1, IOPORT1_P9)
+#define LINE_P10               PAL_LINE(IOPORT1, IOPORT1_P10)
+#define LINE_P11               PAL_LINE(IOPORT1, IOPORT1_P11)
+#define LINE_P12               PAL_LINE(IOPORT1, IOPORT1_P12)
+#define LINE_P13               PAL_LINE(IOPORT1, IOPORT1_P13)
+#define LINE_P14               PAL_LINE(IOPORT1, IOPORT1_P14)
+#define LINE_P15               PAL_LINE(IOPORT1, IOPORT1_P15)
+#define LINE_P16               PAL_LINE(IOPORT1, IOPORT1_P16)
+#define LINE_P19               PAL_LINE(IOPORT1, IOPORT1_P19)
+#define LINE_P20               PAL_LINE(IOPORT1, IOPORT1_P20)
+#define LINE_BTN_A             PAL_LINE(IOPORT1, IOPORT1_BTN_A)
+#define LINE_BTN_B             PAL_LINE(IOPORT1, IOPORT1_BTN_B)
+#define LINE_BTN_RST           PAL_LINE(IOPORT1, IOPORT1_BTN_RST)
+#define LINE_LED_COL_1         PAL_LINE(IOPORT1, IOPORT1_LED_COL_1)
+#define LINE_LED_COL_2         PAL_LINE(IOPORT1, IOPORT1_LED_COL_2)
+#define LINE_LED_COL_3         PAL_LINE(IOPORT1, IOPORT1_LED_COL_3)
+#define LINE_LED_COL_4         PAL_LINE(IOPORT1, IOPORT1_LED_COL_4)
+#define LINE_LED_COL_5         PAL_LINE(IOPORT1, IOPORT1_LED_COL_5)
+#define LINE_LED_COL_6         PAL_LINE(IOPORT1, IOPORT1_LED_COL_6)
+#define LINE_LED_COL_7         PAL_LINE(IOPORT1, IOPORT1_LED_COL_7)
+#define LINE_LED_COL_8         PAL_LINE(IOPORT1, IOPORT1_LED_COL_8)
+#define LINE_LED_COL_9         PAL_LINE(IOPORT1, IOPORT1_LED_COL_9)
+#define LINE_LED_ROW_1         PAL_LINE(IOPORT1, IOPORT1_LED_ROW_1)
+#define LINE_LED_ROW_2         PAL_LINE(IOPORT1, IOPORT1_LED_ROW_2)
+#define LINE_LED_ROW_3         PAL_LINE(IOPORT1, IOPORT1_LED_ROW_3)
+#define LINE_PAD_0             PAL_LINE(IOPORT1, IOPORT1_PAD_0)
+#define LINE_PAD_1             PAL_LINE(IOPORT1, IOPORT1_PAD_1)
+#define LINE_PAD_2             PAL_LINE(IOPORT1, IOPORT1_PAD_2)
+#define LINE_SPI_MOSI          PAL_LINE(IOPORT1, IOPORT1_SPI_MOSI)
+#define LINE_SPI_MISO          PAL_LINE(IOPORT1, IOPORT1_SPI_MISO)
+#define LINE_SPI_SCK           PAL_LINE(IOPORT1, IOPORT1_SPI_SCK)
+#define LINE_I2C_SCL           PAL_LINE(IOPORT1, IOPORT1_I2C_SCL)
+#define LINE_I2C_SDA           PAL_LINE(IOPORT1, IOPORT1_I2C_SDA)
+#define LINE_UART_TX           PAL_LINE(IOPORT1, IOPORT1_UART_TX)
+#define LINE_UART_RX           PAL_LINE(IOPORT1, IOPORT1_UART_RX)
+#define LINE_ACC_INT1          PAL_LINE(IOPORT1, IOPORT1_ACC_INT1)
+#define LINE_ACC_INT2          PAL_LINE(IOPORT1, IOPORT1_ACC_INT2)
+#define LINE_MAG_INT1          PAL_LINE(IOPORT1, IOPORT1_MAG_INT1)
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/MICROBIT/board.mk b/os/hal/boards/MICROBIT/board.mk
new file mode 100644
index 0000000..3595b1a
--- /dev/null
+++ b/os/hal/boards/MICROBIT/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/MICROBIT/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/MICROBIT
diff --git a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c
index e6c6080..09b44f7 100644
--- a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c
+++ b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c
@@ -14,45 +14,197 @@
     limitations under the License.
 */
 
-#include "ch.h"
 #include "hal.h"
+#include "stm32_gpio.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of STM32 GPIO port setup.
+ */
+typedef struct {
+  uint32_t              moder;
+  uint32_t              otyper;
+  uint32_t              ospeedr;
+  uint32_t              pupdr;
+  uint32_t              odr;
+  uint32_t              afrl;
+  uint32_t              afrh;
+} gpio_setup_t;
+
+/**
+ * @brief   Type of STM32 GPIO initialization data.
+ */
+typedef struct {
+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
+  gpio_setup_t          PAData;
+#endif
+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
+  gpio_setup_t          PBData;
+#endif
+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
+  gpio_setup_t          PCData;
+#endif
+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
+  gpio_setup_t          PDData;
+#endif
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
+  gpio_setup_t          PEData;
+#endif
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
+  gpio_setup_t          PFData;
+#endif
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
+  gpio_setup_t          PGData;
+#endif
+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
+  gpio_setup_t          PHData;
+#endif
+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
+  gpio_setup_t          PIData;
+#endif
+#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
+  gpio_setup_t          PJData;
+#endif
+#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
+  gpio_setup_t          PKData;
+#endif
+} gpio_config_t;
 
-#if HAL_USE_PAL || defined(__DOXYGEN__)
 /**
- * @brief   PAL setup.
- * @details Digital I/O ports static configuration as defined in @p board.h.
- *          This variable is used by the HAL when initializing the PAL driver.
+ * @brief   STM32 GPIO static initialization data.
  */
-const PALConfig pal_default_config =
-{
+static const gpio_config_t gpio_default_config = {
+#if STM32_HAS_GPIOA
   {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
    VAL_GPIOA_ODR,   VAL_GPIOA_AFRL,   VAL_GPIOA_AFRH},
+#endif
+#if STM32_HAS_GPIOB
   {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
    VAL_GPIOB_ODR,   VAL_GPIOB_AFRL,   VAL_GPIOB_AFRH},
+#endif
+#if STM32_HAS_GPIOC
   {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
    VAL_GPIOC_ODR,   VAL_GPIOC_AFRL,   VAL_GPIOC_AFRH},
+#endif
+#if STM32_HAS_GPIOD
   {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
    VAL_GPIOD_ODR,   VAL_GPIOD_AFRL,   VAL_GPIOD_AFRH},
+#endif
+#if STM32_HAS_GPIOE
   {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
    VAL_GPIOE_ODR,   VAL_GPIOE_AFRL,   VAL_GPIOE_AFRH},
+#endif
+#if STM32_HAS_GPIOF
   {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
    VAL_GPIOF_ODR,   VAL_GPIOF_AFRL,   VAL_GPIOF_AFRH},
+#endif
+#if STM32_HAS_GPIOG
   {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
    VAL_GPIOG_ODR,   VAL_GPIOG_AFRL,   VAL_GPIOG_AFRH},
+#endif
+#if STM32_HAS_GPIOH
   {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
    VAL_GPIOH_ODR,   VAL_GPIOH_AFRL,   VAL_GPIOH_AFRH},
+#endif
+#if STM32_HAS_GPIOI
   {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
-   VAL_GPIOI_ODR,   VAL_GPIOI_AFRL,   VAL_GPIOI_AFRH}
+   VAL_GPIOI_ODR,   VAL_GPIOI_AFRL,   VAL_GPIOI_AFRH},
+#endif
+#if STM32_HAS_GPIOJ
+  {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
+   VAL_GPIOJ_ODR,   VAL_GPIOJ_AFRL,   VAL_GPIOJ_AFRH},
+#endif
+#if STM32_HAS_GPIOK
+  {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
+   VAL_GPIOK_ODR,   VAL_GPIOK_AFRL,   VAL_GPIOK_AFRH}
+#endif
 };
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
+
+  gpiop->OTYPER  = config->otyper;
+  gpiop->OSPEEDR = config->ospeedr;
+  gpiop->PUPDR   = config->pupdr;
+  gpiop->ODR     = config->odr;
+  gpiop->AFRL    = config->afrl;
+  gpiop->AFRH    = config->afrh;
+  gpiop->MODER   = config->moder;
+}
+
+static void stm32_gpio_init(void) {
+
+  /* Enabling GPIO-related clocks, the mask comes from the
+     registry header file.*/
+  rccResetAHB1(STM32_GPIO_EN_MASK);
+  rccEnableAHB1(STM32_GPIO_EN_MASK, true);
+
+  /* Initializing all the defined GPIO ports.*/
+#if STM32_HAS_GPIOA
+  gpio_init(GPIOA, &gpio_default_config.PAData);
+#endif
+#if STM32_HAS_GPIOB
+  gpio_init(GPIOB, &gpio_default_config.PBData);
 #endif
+#if STM32_HAS_GPIOC
+  gpio_init(GPIOC, &gpio_default_config.PCData);
+#endif
+#if STM32_HAS_GPIOD
+  gpio_init(GPIOD, &gpio_default_config.PDData);
+#endif
+#if STM32_HAS_GPIOE
+  gpio_init(GPIOE, &gpio_default_config.PEData);
+#endif
+#if STM32_HAS_GPIOF
+  gpio_init(GPIOF, &gpio_default_config.PFData);
+#endif
+#if STM32_HAS_GPIOG
+  gpio_init(GPIOG, &gpio_default_config.PGData);
+#endif
+#if STM32_HAS_GPIOH
+  gpio_init(GPIOH, &gpio_default_config.PHData);
+#endif
+#if STM32_HAS_GPIOI
+  gpio_init(GPIOI, &gpio_default_config.PIData);
+#endif
+#if STM32_HAS_GPIOJ
+  gpio_init(GPIOJ, &gpio_default_config.PJData);
+#endif
+#if STM32_HAS_GPIOK
+  gpio_init(GPIOK, &gpio_default_config.PKData);
+#endif
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
 
 /**
  * @brief   Early initialization code.
- * @details This initialization must be performed just after stack setup
- *          and before any other initialization.
+ * @details GPIO ports and system clocks are initialized before everything
+ *          else.
  */
 void __early_init(void) {
 
+  stm32_gpio_init();
   stm32_clock_init();
 }
 
@@ -60,21 +212,21 @@ void __early_init(void) {
 /**
  * @brief   SDC card detection.
  */
-bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
 
   (void)sdcp;
   /* TODO: Fill the implementation.*/
-  return TRUE;
+  return true;
 }
 
 /**
  * @brief   SDC card write protection detection.
  */
-bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
 
   (void)sdcp;
   /* TODO: Fill the implementation.*/
-  return FALSE;
+  return false;
 }
 #endif /* HAL_USE_SDC */
 
@@ -82,21 +234,21 @@ bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
 /**
  * @brief   MMC_SPI card detection.
  */
-bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
 
   (void)mmcp;
   /* TODO: Fill the implementation.*/
-  return TRUE;
+  return true;
 }
 
 /**
  * @brief   MMC_SPI card write protection detection.
  */
-bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
 
   (void)mmcp;
   /* TODO: Fill the implementation.*/
-  return FALSE;
+  return false;
 }
 #endif
 
@@ -105,4 +257,5 @@ bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
  * @todo    Add your board-specific code, if any.
  */
 void boardInit(void) {
+
 }
diff --git a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h
index 05aeceb..0788eb7 100644
--- a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h
+++ b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h
@@ -587,19 +587,14 @@
                                      PIN_OSPEED_100M(GPIOD_MEM_D0) |        \
                                      PIN_OSPEED_100M(GPIOD_MEM_D1))
 
-#if STM32_NAND_USE_EXT_INT
-#define NAND_RB_NWAIT_PUPDR(pin) (PIN_PUPDR_PULLUP(pin))
-#else
-#define NAND_RB_NWAIT_PUPDR(pin) (PIN_PUPDR_FLOATING(pin))
-#endif
 #define VAL_GPIOD_PUPDR             (PIN_PUPDR_FLOATING(GPIOD_MEM_D2) |     \
                                      PIN_PUPDR_FLOATING(GPIOD_MEM_D3) |     \
                                      PIN_PUPDR_FLOATING(GPIOD_PIN2) |       \
                                      PIN_PUPDR_FLOATING(GPIOD_PIN3) |       \
                                      PIN_PUPDR_FLOATING(GPIOD_MEM_OE) |     \
                                      PIN_PUPDR_FLOATING(GPIOD_MEM_WE) |     \
-                                     NAND_RB_NWAIT_PUPDR(GPIOD_NAND_RB_NWAIT) |  \
-                                     PIN_PUPDR_PULLUP(GPIOD_NAND_CE1) |   \
+                                     PIN_PUPDR_FLOATING(GPIOD_NAND_RB_NWAIT) |\
+                                     PIN_PUPDR_PULLUP(GPIOD_NAND_CE1) |     \
                                      PIN_PUPDR_FLOATING(GPIOD_MEM_D13) |    \
                                      PIN_PUPDR_FLOATING(GPIOD_MEM_D14) |    \
                                      PIN_PUPDR_FLOATING(GPIOD_MEM_D15) |    \
@@ -893,21 +888,16 @@
                                      PIN_OSPEED_100M(GPIOG_PIN14) |         \
                                      PIN_OSPEED_100M(GPIOG_PIN15))
 
-#if STM32_NAND_USE_EXT_INT
-#define NAND_RB1_PUPDR(pin) (PIN_PUPDR_FLOATING(pin))
-#else
-#define NAND_RB1_PUPDR(pin) (PIN_PUPDR_PULLUP(pin))
-#endif
 #define VAL_GPIOG_PUPDR             (PIN_PUPDR_FLOATING(GPIOG_MEM_A10) |    \
                                      PIN_PUPDR_FLOATING(GPIOG_MEM_A11) |    \
                                      PIN_PUPDR_FLOATING(GPIOG_MEM_A12) |    \
                                      PIN_PUPDR_FLOATING(GPIOG_MEM_A13) |    \
                                      PIN_PUPDR_FLOATING(GPIOG_MEM_A14) |    \
                                      PIN_PUPDR_FLOATING(GPIOG_MEM_A15) |    \
-                                     NAND_RB1_PUPDR(GPIOG_NAND_RB1) |       \
+                                     PIN_PUPDR_PULLUP(GPIOG_NAND_RB1) |     \
                                      PIN_PUPDR_FLOATING(GPIOG_NAND_RB2) |   \
                                      PIN_PUPDR_FLOATING(GPIOG_PIN8) |       \
-                                     PIN_PUPDR_PULLUP(GPIOG_NAND_CE2) |   \
+                                     PIN_PUPDR_PULLUP(GPIOG_NAND_CE2) |     \
                                      PIN_PUPDR_FLOATING(GPIOG_PIN10) |      \
                                      PIN_PUPDR_FLOATING(GPIOG_PIN11) |      \
                                      PIN_PUPDR_FLOATING(GPIOG_SRAM_CS1) |   \
diff --git a/os/hal/boards/NRF51-DK/board.mk b/os/hal/boards/NRF51-DK/board.mk
index 9619bd4..631927b 100644
--- a/os/hal/boards/NRF51-DK/board.mk
+++ b/os/hal/boards/NRF51-DK/board.mk
@@ -8,4 +8,4 @@ BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/NRF51-DK
 JLINK_DEVICE    = nrf51422
 JLINK_PRE_FLASH = w4 4001e504 1
 JLINK_ERASE_ALL = w4 4001e504 2\nw4 4001e50c 1\nsleep 100
-
+JLINK_PIN_RESET = w4 40000544 1
diff --git a/os/hal/boards/NRF52-DK/board.c b/os/hal/boards/NRF52-DK/board.c
new file mode 100644
index 0000000..cfbf24d
--- /dev/null
+++ b/os/hal/boards/NRF52-DK/board.c
@@ -0,0 +1,81 @@
+/*
+    Copyright (C) 2016 Stéphane D'Alu
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+  .pads = {
+        PAL_MODE_UNCONNECTED,         /* P0.0 : XTAL (32MHz)   */
+        PAL_MODE_UNCONNECTED,         /* P0.1 : XTAL (32MHz)   */
+        PAL_MODE_UNCONNECTED,         /* P0.2                  */
+        PAL_MODE_UNCONNECTED,         /* P0.3                  */
+        PAL_MODE_UNCONNECTED,         /* P0.4                  */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.5 : UART_RTS       */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.6 : UART_TX        */
+        PAL_MODE_INPUT_PULLUP,        /* P0.7 : UART_CTS       */
+        PAL_MODE_INPUT_PULLUP,        /* P0.8 : UART_RX        */
+        PAL_MODE_UNCONNECTED,         /* P0.9                  */
+        PAL_MODE_UNCONNECTED,         /* P0.10                 */
+        PAL_MODE_UNCONNECTED,         /* P0.11                 */
+        PAL_MODE_UNCONNECTED,         /* P0.12                 */
+        PAL_MODE_INPUT_PULLUP,        /* P0.13: BTN1           */
+        PAL_MODE_INPUT_PULLUP,        /* P0.14: BTN2           */
+        PAL_MODE_INPUT_PULLUP,        /* P0.15: BTN3           */
+        PAL_MODE_INPUT_PULLUP,        /* P0.16: BTN4           */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.17: LED1           */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.18: LED2           */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.19: LED3           */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.20: LED4           */
+        PAL_MODE_UNCONNECTED,         /* P0.21                 */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.22: SPI_SS         */
+        PAL_MODE_INPUT_PULLUP,        /* P0.23: SPI_MISO       */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.24: SPI_MOSI       */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.25: SPI_SCK        */
+        PAL_MODE_OUTPUT_OPENDRAIN,    /* P0.26: SDA            */
+        PAL_MODE_OUTPUT_OPENDRAIN,    /* P0.27: SCL            */
+        PAL_MODE_UNCONNECTED,         /* P0.28                 */
+        PAL_MODE_UNCONNECTED,         /* P0.29                 */
+        PAL_MODE_UNCONNECTED,         /* P0.30                 */
+        PAL_MODE_UNCONNECTED,         /* P0.31                 */
+  },
+};
+#endif
+
+/**
+ * @brief   Early initialization code.
+ * @details This initialization is performed just after reset before BSS and
+ *          DATA segments initialization.
+ */
+void __early_init(void)
+{
+}
+
+/**
+ * @brief   Late initialization code.
+ * @note    This initialization is performed after BSS and DATA segments
+ *          initialization and before invoking the main() function.
+ */
+void boardInit(void)
+{
+}
diff --git a/os/hal/boards/NRF52-DK/board.h b/os/hal/boards/NRF52-DK/board.h
new file mode 100644
index 0000000..5c7566a
--- /dev/null
+++ b/os/hal/boards/NRF52-DK/board.h
@@ -0,0 +1,201 @@
+/*
+    Copyright (C) 2016 Stephane D'Alu
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/* Board identifier. */
+#define BOARD_NRF52_DK
+#define BOARD_NAME              "nRF52 DK"
+
+/* Board oscillators-related settings. */
+#define NRF5_XTAL_VALUE        32000000
+#define NRF5_LFCLK_SOURCE      1
+
+/*
+ * GPIO pins. 
+ */
+/* Defined by board */
+#define BTN1           13U
+#define BTN2           14U
+#define BTN3           15U
+#define BTN4           16U
+#define LED1           17U
+#define LED2           18U
+#define LED3           19U
+#define LED4           20U
+#define UART_RTS        5U
+#define UART_TX         6U
+#define UART_CTS        7U
+#define UART_RX         8U
+#define NFC1            9U
+#define NFC2           10U
+#define I2C_SCL        27U
+#define I2C_SDA        26U
+
+/* Our definitions */
+#define SPI_SCK        25U
+#define SPI_MOSI       24U
+#define SPI_MISO       23U
+#define SPI_SS         22U
+
+/* Analog input */
+#define AIN0            2U
+#define AIN1            3U
+#define AIN2            4U
+#define AIN3            5U
+#define AIN4           28U
+#define AIN5           29U
+#define AIN6           30U
+#define AIN7           31U
+#define AREF0         AIN0
+#define AREF1         AIN1
+
+/*
+ * IO pins assignments.
+ */
+/* Defined by board */
+#define IOPORT1_BTN1           13U
+#define IOPORT1_BTN2           14U
+#define IOPORT1_BTN3           15U
+#define IOPORT1_BTN4           16U
+#define IOPORT1_LED1           17U
+#define IOPORT1_LED2           18U
+#define IOPORT1_LED3           19U
+#define IOPORT1_LED4           20U
+#define IOPORT1_UART_RTS        5U
+#define IOPORT1_UART_TX         6U
+#define IOPORT1_UART_CTS        7U
+#define IOPORT1_UART_RX         8U
+#define IOPORT1_NFC1            9U
+#define IOPORT1_NFC2           10U
+#define IOPORT1_I2C_SCL        27U
+#define IOPORT1_I2C_SDA        26U
+#define IOPORT1_RESET          21U
+
+/* Our definitions */
+#define IOPORT1_SPI_SCK        25U
+#define IOPORT1_SPI_MOSI       24U
+#define IOPORT1_SPI_MISO       23U
+#define IOPORT1_SPI_SS         22U
+
+/* Analog inpupt */
+#define IOPORT1_AIN0            2U
+#define IOPORT1_AIN1            3U
+#define IOPORT1_AIN2            4U
+#define IOPORT1_AIN3            5U
+#define IOPORT1_AIN4           28U
+#define IOPORT1_AIN5           29U
+#define IOPORT1_AIN6           30U
+#define IOPORT1_AIN7           31U
+#define IOPORT1_AREF0           IOPORT1_AIN0
+#define IOPORT1_AREF1           IOPORT1_AIN1
+
+/* Arduino naming */
+#define IOPORT1_A0              3U
+#define IOPORT1_A1              4U
+#define IOPORT1_A2             28U
+#define IOPORT1_A3             39U
+#define IOPORT1_A4             30U
+#define IOPORT1_A5             31U
+#define IOPORT1_D0             11U
+#define IOPORT1_D1             12U
+#define IOPORT1_D2             13U
+#define IOPORT1_D3             14U
+#define IOPORT1_D4             15U
+#define IOPORT1_D5             16U
+#define IOPORT1_D6             17U
+#define IOPORT1_D7             18U
+#define IOPORT1_D8             19U
+#define IOPORT1_D9             20U
+#define IOPORT1_D10            22U
+#define IOPORT1_D11            23U
+#define IOPORT1_D12            24U
+#define IOPORT1_D13            25U
+
+
+/*
+ * IO lines assignments.
+ */
+/* Board defined */
+#define LINE_BTN1      PAL_LINE(IOPORT1, IOPORT1_BTN1)
+#define LINE_BTN2      PAL_LINE(IOPORT1, IOPORT1_BTN2)
+#define LINE_BTN3      PAL_LINE(IOPORT1, IOPORT1_BTN3)
+#define LINE_BTN4      PAL_LINE(IOPORT1, IOPORT1_BTN4)
+#define LINE_LED1      PAL_LINE(IOPORT1, IOPORT1_LED1)
+#define LINE_LED2      PAL_LINE(IOPORT1, IOPORT1_LED2)
+#define LINE_LED3      PAL_LINE(IOPORT1, IOPORT1_LED3)
+#define LINE_LED4      PAL_LINE(IOPORT1, IOPORT1_LED4)
+#define LINE_UART_RTS  PAL_LINE(IOPORT1, IOPORT1_UART_RTS)
+#define LINE_UART_TX   PAL_LINE(IOPORT1, IOPORT1_UART_TX)
+#define LINE_UART_CTS  PAL_LINE(IOPORT1, IOPORT1_UART_CTS)
+#define LINE_UART_RX   PAL_LINE(IOPORT1, IOPORT1_UART_RX)
+#define LINE_NFC1      PAL_LINE(IOPORT1, IOPORT1_NFC1)
+#define LINE_NFC2      PAL_LINE(IOPORT1, IOPORT1_NFC2)
+#define LINE_I2C_SCL   PAL_LINE(IOPORT1, IOPORT1_I2C_SCL)
+#define LINE_I2C_SDA   PAL_LINE(IOPORT1, IOPORT1_I2C_SDA)
+
+/* Our definitions */
+#define LINE_SPI_SCK   PAL_LINE(IOPORT1, IOPORT1_SPI_SCK)
+#define LINE_SPI_MOSI  PAL_LINE(IOPORT1, IOPORT1_SPI_MOSI)
+#define LINE_SPI_MISO  PAL_LINE(IOPORT1, IOPORT1_SPI_MISO)
+#define LINE_SPI_SS    PAL_LINE(IOPORT1, IOPORT1_SPI_SS)
+
+/* Analog line */
+#define LINE_AIN0      PAL_LINE(IOPORT1, IOPORT1_AIN0)
+#define LINE_AIN1      PAL_LINE(IOPORT1, IOPORT1_AIN1)
+#define LINE_AIN2      PAL_LINE(IOPORT1, IOPORT1_AIN2)
+#define LINE_AIN3      PAL_LINE(IOPORT1, IOPORT1_AIN3)
+#define LINE_AIN4      PAL_LINE(IOPORT1, IOPORT1_AIN4)
+#define LINE_AIN5      PAL_LINE(IOPORT1, IOPORT1_AIN5)
+#define LINE_AIN6      PAL_LINE(IOPORT1, IOPORT1_AIN6)
+#define LINE_AIN7      PAL_LINE(IOPORT1, IOPORT1_AIN7)
+#define LINE_AREF0     PAL_LINE(IOPORT1, IOPORT1_AREF0)
+#define LINE_AREF1     PAL_LINE(IOPORT1, IOPORT1_AREF1)
+
+/* Arduino naming */
+#define LINE_A0        PAL_LINE(IOPORT1, IOPORT1_A0)
+#define LINE_A1        PAL_LINE(IOPORT1, IOPORT1_A1)
+#define LINE_A2        PAL_LINE(IOPORT1, IOPORT1_A2)
+#define LINE_A3        PAL_LINE(IOPORT1, IOPORT1_A3)
+#define LINE_A4        PAL_LINE(IOPORT1, IOPORT1_A4)
+#define LINE_A5        PAL_LINE(IOPORT1, IOPORT1_A5)
+#define LINE_D0        PAL_LINE(IOPORT1, IOPORT1_D0)
+#define LINE_D1        PAL_LINE(IOPORT1, IOPORT1_D1)
+#define LINE_D2        PAL_LINE(IOPORT1, IOPORT1_D2)
+#define LINE_D3        PAL_LINE(IOPORT1, IOPORT1_D3)
+#define LINE_D4        PAL_LINE(IOPORT1, IOPORT1_D4)
+#define LINE_D5        PAL_LINE(IOPORT1, IOPORT1_D5)
+#define LINE_D6        PAL_LINE(IOPORT1, IOPORT1_D6)
+#define LINE_D7        PAL_LINE(IOPORT1, IOPORT1_D7)
+#define LINE_D8        PAL_LINE(IOPORT1, IOPORT1_D8)
+#define LINE_D9        PAL_LINE(IOPORT1, IOPORT1_D9)
+#define LINE_D10       PAL_LINE(IOPORT1, IOPORT1_D10)
+#define LINE_D11       PAL_LINE(IOPORT1, IOPORT1_D11)
+#define LINE_D12       PAL_LINE(IOPORT1, IOPORT1_D12)
+#define LINE_D13       PAL_LINE(IOPORT1, IOPORT1_D13)
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/NRF52-DK/board.mk b/os/hal/boards/NRF52-DK/board.mk
new file mode 100644
index 0000000..4310291
--- /dev/null
+++ b/os/hal/boards/NRF52-DK/board.mk
@@ -0,0 +1,12 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/NRF52-DK/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/NRF52-DK
+
+# Flash
+JLINK_DEVICE    = nrf52
+JLINK_PRE_FLASH = w4 4001e504 1
+#JLINK_ERASE_ALL = w4 4001e504 2\nw4 4001e50c 1\nsleep 100
+JLINK_PIN_RESET = w4 40000544 1
+
diff --git a/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c b/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c
index dc058f6..3412452 100644
--- a/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c
+++ b/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c
@@ -1,5 +1,5 @@
 /*

-    ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio

+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio

 

     Licensed under the Apache License, Version 2.0 (the "License");

     you may not use this file except in compliance with the License.

@@ -14,15 +14,76 @@
     limitations under the License.

 */

 

+/*

+ * This file has been automatically generated using ChibiStudio board

+ * generator plugin. Do not edit manually.

+ */

+

 #include "hal.h"

+#include "stm32_gpio.h"

+

+/*===========================================================================*/

+/* Driver local definitions.                                                 */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver exported variables.                                                */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver local variables and types.                                         */

+/*===========================================================================*/

+

+/**

+ * @brief   Type of STM32 GPIO port setup.

+ */

+typedef struct {

+  uint32_t              moder;

+  uint32_t              otyper;

+  uint32_t              ospeedr;

+  uint32_t              pupdr;

+  uint32_t              odr;

+  uint32_t              afrl;

+  uint32_t              afrh;

+} gpio_setup_t;

+

+/**

+ * @brief   Type of STM32 GPIO initialization data.

+ */

+typedef struct {

+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)

+  gpio_setup_t          PAData;

+#endif

+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)

+  gpio_setup_t          PBData;

+#endif

+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)

+  gpio_setup_t          PCData;

+#endif

+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)

+  gpio_setup_t          PDData;

+#endif

+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)

+  gpio_setup_t          PEData;

+#endif

+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)

+  gpio_setup_t          PFData;

+#endif

+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)

+  gpio_setup_t          PGData;

+#endif

+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)

+  gpio_setup_t          PHData;

+#endif

+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)

+  gpio_setup_t          PIData;

+#endif

+} gpio_config_t;

 

-#if HAL_USE_PAL || defined(__DOXYGEN__)

 /**

- * @brief   PAL setup.

- * @details Digital I/O ports static configuration as defined in @p board.h.

- *          This variable is used by the HAL when initializing the PAL driver.

+ * @brief   STM32 GPIO static initialization data.

  */

-const PALConfig pal_default_config = {

+static const gpio_config_t gpio_default_config = {

 #if STM32_HAS_GPIOA

   {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,

    VAL_GPIOA_ODR,   VAL_GPIOA_AFRL,   VAL_GPIOA_AFRH},

@@ -57,21 +118,103 @@ const PALConfig pal_default_config = {
 #endif

 #if STM32_HAS_GPIOI

   {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,

-   VAL_GPIOI_ODR,   VAL_GPIOI_AFRL,   VAL_GPIOI_AFRH}

+   VAL_GPIOI_ODR,   VAL_GPIOI_AFRL,   VAL_GPIOI_AFRH},

 #endif

 };

+

+/*===========================================================================*/

+/* Driver local functions.                                                   */

+/*===========================================================================*/

+

+static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {

+

+  gpiop->OTYPER  = config->otyper;

+  gpiop->OSPEEDR = config->ospeedr;

+  gpiop->PUPDR   = config->pupdr;

+  gpiop->ODR     = config->odr;

+  gpiop->AFRL    = config->afrl;

+  gpiop->AFRH    = config->afrh;

+  gpiop->MODER   = config->moder;

+}

+

+static void stm32_gpio_init(void) {

+

+  /* Enabling GPIO-related clocks, the mask comes from the

+     registry header file.*/

+  rccResetAHB(STM32_GPIO_EN_MASK);

+  rccEnableAHB(STM32_GPIO_EN_MASK, true);

+

+  /* Initializing all the defined GPIO ports.*/

+#if STM32_HAS_GPIOA

+  gpio_init(GPIOA, &gpio_default_config.PAData);

+#endif

+#if STM32_HAS_GPIOB

+  gpio_init(GPIOB, &gpio_default_config.PBData);

 #endif

+#if STM32_HAS_GPIOC

+  gpio_init(GPIOC, &gpio_default_config.PCData);

+#endif

+#if STM32_HAS_GPIOD

+  gpio_init(GPIOD, &gpio_default_config.PDData);

+#endif

+#if STM32_HAS_GPIOE

+  gpio_init(GPIOE, &gpio_default_config.PEData);

+#endif

+#if STM32_HAS_GPIOF

+  gpio_init(GPIOF, &gpio_default_config.PFData);

+#endif

+#if STM32_HAS_GPIOG

+  gpio_init(GPIOG, &gpio_default_config.PGData);

+#endif

+#if STM32_HAS_GPIOH

+  gpio_init(GPIOH, &gpio_default_config.PHData);

+#endif

+#if STM32_HAS_GPIOI

+  gpio_init(GPIOI, &gpio_default_config.PIData);

+#endif

+}

+

+/*===========================================================================*/

+/* Driver interrupt handlers.                                                */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver exported functions.                                                */

+/*===========================================================================*/

 

 /**

  * @brief   Early initialization code.

- * @details This initialization must be performed just after stack setup

- *          and before any other initialization.

+ * @details GPIO ports and system clocks are initialized before everything

+ *          else.

  */

 void __early_init(void) {

 

+  stm32_gpio_init();

   stm32_clock_init();

 }

 

+#if HAL_USE_SDC || defined(__DOXYGEN__)

+/**

+ * @brief   SDC card detection.

+ */

+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {

+

+  (void)sdcp;

+  /* TODO: Fill the implementation.*/

+  return true;

+}

+

+/**

+ * @brief   SDC card write protection detection.

+ */

+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {

+

+  (void)sdcp;

+  /* TODO: Fill the implementation.*/

+  return false;

+}

+#endif /* HAL_USE_SDC */

+

 #if HAL_USE_MMC_SPI || defined(__DOXYGEN__)

 /**

  * @brief   MMC_SPI card detection.

@@ -99,4 +242,5 @@ bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
  * @todo    Add your board-specific code, if any.

  */

 void boardInit(void) {

+

 }

diff --git a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.c b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.c
index 2bbbc4c..870b4cb 100644
--- a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.c
+++ b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.c
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
diff --git a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h
index 367dce1..8f2aacf 100644
--- a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h
+++ b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -14,8 +14,8 @@
     limitations under the License.
 */
 
-#ifndef _BOARD_H_
-#define _BOARD_H_
+#ifndef BOARD_H
+#define BOARD_H
 
 /*
  * Setup for Texas Instruments TM4C123G Launchpad Board.
@@ -28,59 +28,10 @@
 #define BOARD_NAME              "Texas Instruments TM4C123G Launchpad"
 
 /*
- * MCU type
+ * MCU type and revision as defined in the TI header.
  */
-//#define TM4C1230C3PM
-//#define TM4C1230D5PM
-//#define TM4C1230E6PM
-//#define TM4C1230H6PM
-//#define TM4C1231C3PM
-//#define TM4C1231D5PM
-//#define TM4C1231D5PZ
-//#define TM4C1231E6PM
-//#define TM4C1231E6PZ
-//#define TM4C1231H6PGE
-//#define TM4C1231H6PM
-//#define TM4C1231H6PZ
-//#define TM4C1232C3PM
-//#define TM4C1232D5PM
-//#define TM4C1232E6PM
-//#define TM4C1232H6PM
-//#define TM4C1233C3PM
-//#define TM4C1233D5PM
-//#define TM4C1233D5PZ
-//#define TM4C1233E6PM
-//#define TM4C1233E6PZ
-//#define TM4C1233H6PGE
-//#define TM4C1233H6PM
-//#define TM4C1233H6PZ
-//#define TM4C1236D5PM
-//#define TM4C1236E6PM
-//#define TM4C1236H6PM
-//#define TM4C1237D5PM
-//#define TM4C1237D5PZ
-//#define TM4C1237E6PM
-//#define TM4C1237E6PZ
-//#define TM4C1237H6PGE
-//#define TM4C1237H6PM
-//#define TM4C1237H6PZ
-//#define TM4C123AE6PM
-//#define TM4C123AH6PM
-//#define TM4C123BE6PM
-//#define TM4C123BE6PZ
-//#define TM4C123BH6PGE
-//#define TM4C123BH6PM
-//#define TM4C123BH6PZ
-//#define TM4C123BH6ZRB
-//#define TM4C123FE6PM
-//#define TM4C123FH6PM
-//#define TM4C123GE6PM
-//#define TM4C123GE6PZ
-//#define TM4C123GH6PGE
-#define TM4C123GH6PM
-//#define TM4C123GH6PZ
-//#define TM4C123GH6ZRB
-//#define TM4C123GH5ZXR
+#define PART_TM4C123GH6PM
+#define TARGET_IS_TM4C123_RB1
 
 /*
  * Board oscillators-related settings.
@@ -145,6 +96,24 @@
 #define GPIOF_PIN7              7
 
 /*
+ * IO lines assignments.
+ */
+#define LINE_UART0_RX           PAL_LINE(GPIOA, 0U)
+#define LINE_UART0_TX           PAL_LINE(GPIOA, 1U)
+#define LINE_SSI0_CLK           PAL_LINE(GPIOA, 2U)
+#define LINE_SSI0_RX            PAL_LINE(GPIOA, 4U)
+#define LINE_SSI0_TX            PAL_LINE(GPIOA, 5U)
+
+#define LINE_I2C0_SCL           PAL_LINE(GPIOB, 2U)
+#define LINE_I2C0_SDA           PAL_LINE(GPIOB, 3U)
+
+#define LINE_SW2                PAL_LINE(GPIOF, 0U)
+#define LINE_LED_RED            PAL_LINE(GPIOF, 1U)
+#define LINE_LED_BLUE           PAL_LINE(GPIOF, 2U)
+#define LINE_LED_GREEN          PAL_LINE(GPIOF, 3U)
+#define LINE_SW1                PAL_LINE(GPIOF, 4U)
+
+/*
  * I/O ports initial setup, this configuration is established soon after reset
  * in the initialization code.
  */
@@ -940,4 +909,4 @@ extern "C" {
 #endif
 #endif /* _FROM_ASM_ */
 
-#endif /* _BOARD_H_ */
+#endif /* BOARD_H */
diff --git a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk
index 8232a30..22b5467 100644
--- a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk
+++ b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk
@@ -3,3 +3,7 @@ BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.c
 
 # Required include directories
 BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/TI_TM4C123G_LAUNCHPAD
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.c b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.c
index 437dcf8..bbfdb88 100644
--- a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.c
+++ b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.c
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
diff --git a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h
index 08bb36f..611a580 100644
--- a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h
+++ b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -14,8 +14,8 @@
     limitations under the License.
 */
 
-#ifndef _BOARD_H_
-#define _BOARD_H_
+#ifndef BOARD_H
+#define BOARD_H
 
 /*
  * Setup for Texas Instruments TM4C1294 Launchpad Board.
@@ -36,28 +36,10 @@
 //#define BOARD_PHY_RMII
 
 /*
- * MCU type
+ * MCU type and revision as defined in the TI header.
  */
-//#define TM4C1290NCPDT
-//#define TM4C1290NCZAD
-//#define TM4C1292NCPDT
-//#define TM4C1292NCZAD
-//#define TM4C1294KCPDT
-#define TM4C1294NCPDT
-//#define TM4C1294NCZAD
-//#define TM4C1297NCZAD
-//#define TM4C1299KCZAD
-//#define TM4C1299NCZAD
-//#define TM4C129CNCPDT
-//#define TM4C129CNCZAD
-//#define TM4C129DNCPDT
-//#define TM4C129DNCZAD
-//#define TM4C129EKCPDT
-//#define TM4C129ENCPDT
-//#define TM4C129ENCZAD
-//#define TM4C129LNCZAD
-//#define TM4C129XKCZAD
-//#define TM4C129XNCZAD
+#define PART_TM4C1294NCPDT
+#define TARGET_IS_TM4C129_RA0
 
 /*
  * Board oscillators-related settings.
@@ -203,6 +185,20 @@
 #define GPIOQ_PIN7              7
 
 /*
+ * IO lines assignments.
+ */
+#define LINE_UART0_RX           PAL_LINE(GPIOA, 0U)
+#define LINE_UART0_TX           PAL_LINE(GPIOA, 1U)
+
+#define LINE_LED0               PAL_LINE(GPIOF, 0U)
+#define LINE_LED1               PAL_LINE(GPIOF, 4U)
+
+#define LINE_LED2               PAL_LINE(GPION, 0U)
+#define LINE_LED3               PAL_LINE(GPION, 1U)
+
+#define LINE_SW1                PAL_LINE(GPIOJ, 0U)
+
+/*
  * I/O ports initial setup, this configuration is established soon after reset
  * in the initialization code.
  */
@@ -426,4 +422,4 @@ extern "C" {
 #endif
 #endif /* _FROM_ASM_ */
 
-#endif /* _BOARD_H_ */
+#endif /* BOARD_H */
diff --git a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk
index 56298eb..e95de0b 100644
--- a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk
+++ b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk
@@ -3,3 +3,7 @@ BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.c
 
 # Required include directories
 BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/TI_TM4C1294_LAUNCHPAD
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/os/hal/hal.mk b/os/hal/hal.mk
index ce74620..119db8a 100644
--- a/os/hal/hal.mk
+++ b/os/hal/hal.mk
@@ -12,12 +12,16 @@ HALSRC += ${CHIBIOS_CONTRIB}/os/hal/src/hal_community.c \
           ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_hub.c \

           ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_msd.c \

           ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_ftdi.c \

+          ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_aoa.c \

+          ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_hid.c \

           ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_uvc.c \

           ${CHIBIOS_CONTRIB}/os/hal/src/hal_ee24xx.c \

           ${CHIBIOS_CONTRIB}/os/hal/src/hal_ee25xx.c \

           ${CHIBIOS_CONTRIB}/os/hal/src/hal_eeprom.c \

           ${CHIBIOS_CONTRIB}/os/hal/src/hal_timcap.c \

           ${CHIBIOS_CONTRIB}/os/hal/src/hal_qei.c \

-          ${CHIBIOS_CONTRIB}/os/hal/src/hal_usb_hid.c

+          ${CHIBIOS_CONTRIB}/os/hal/src/hal_usb_hid.c \

+          ${CHIBIOS_CONTRIB}/os/hal/src/hal_usb_msd.c \

+          ${CHIBIOS_CONTRIB}/os/hal/src/hal_comp.c

 

 HALINC += ${CHIBIOS_CONTRIB}/os/hal/include

diff --git a/os/hal/include/hal_community.h b/os/hal/include/hal_community.h
index 1518c7e..83b1f02 100644
--- a/os/hal/include/hal_community.h
+++ b/os/hal/include/hal_community.h
@@ -48,7 +48,7 @@
 #endif

 

 #if !defined(HAL_USE_QEI)

-#define HAL_USE_QEI                        FALSE

+#define HAL_USE_QEI                         FALSE

 #endif

 

 #if !defined(HAL_USE_RNG)

@@ -67,6 +67,14 @@
 #define HAL_USE_USB_HID                     FALSE

 #endif

 

+#if !defined(HAL_USE_USB_MSD)

+#define HAL_USE_USB_MSD                     FALSE

+#endif

+

+#if !defined(HAL_USE_COMP)

+#define HAL_USE_COMP                        FALSE

+#endif

+

 /* Abstract interfaces.*/

 

 /* Shared headers.*/

@@ -78,12 +86,14 @@
 #include "hal_usbh.h"

 #include "hal_timcap.h"

 #include "hal_qei.h"

+#include "hal_comp.h"

 

 /* Complex drivers.*/

 #include "hal_onewire.h"

 #include "hal_crc.h"

 #include "hal_eeprom.h"

 #include "hal_usb_hid.h"

+#include "hal_usb_msd.h"

 

 /*===========================================================================*/

 /* Driver constants.                                                         */

diff --git a/os/hal/include/hal_comp.h b/os/hal/include/hal_comp.h
new file mode 100644
index 0000000..835704d
--- /dev/null
+++ b/os/hal/include/hal_comp.h
@@ -0,0 +1,131 @@
+/*
+    ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio
+              Copyright (C) 2017 Fabien Poussin (fabien.poussin (at) google's mail)
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef HAL_COMP_H_
+#define HAL_COMP_H_
+
+#include "hal.h"
+
+
+#if (HAL_USE_COMP == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Driver state machine possible states.
+ */
+typedef enum {
+  COMP_UNINIT = 0,                   /**< Not initialized.                   */
+  COMP_STOP = 1,                     /**< Stopped.                           */
+  COMP_READY = 2,                    /**< Ready.                             */
+  COMP_ACTIVE = 3,                   /**< Active cycle phase.                */
+} compstate_t;
+
+/**
+ * @brief   Type of a structure representing an COMP driver.
+ */
+typedef struct COMPDriver COMPDriver;
+
+/**
+ * @brief   COMP notification callback type.
+ *
+ * @param[in] comp      pointer to a @p COMPDriver object
+ */
+typedef void (*compcallback_t)(COMPDriver *comp);
+
+#include "hal_comp_lld.h"
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @name    Macro Functions
+ * @{
+ */
+/**
+ * @brief   Enables the input capture.
+ *
+ * @param[in] comp      pointer to the @p COMPDriver object
+ *
+ * @iclass
+ */
+#define compEnableI(comp) comp_lld_enable(comp)
+
+/**
+ * @brief   Disables the input capture.
+ *
+ * @param[in] comp      pointer to the @p COMPDriver object
+ *
+ * @iclass
+ */
+#define compDisableI(comp) comp_lld_disable(comp)
+/** @} */
+
+
+/**
+ * @name    Low Level driver helper macros
+ * @{
+ */
+
+/**
+ * @brief   Common ISR code, main event.
+ *
+ * @param[in] comp      pointer to the @p COMPDriver object
+ *
+ * @notapi
+ */
+#define _comp_isr_invoke_cb(comp) {                                 \
+  (comp)->config->cb(comp);                                        \
+}
+/** @} */
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void compInit(void);
+  void compObjectInit(COMPDriver *comp);
+  void compStart(COMPDriver *comp, const COMPConfig *config);
+  void compStop(COMPDriver *comp);
+  void compEnable(COMPDriver *comp);
+  void compDisable(COMPDriver *comp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_COMP */
+
+
+#endif /* HAL_COMP_H_ */
diff --git a/os/hal/include/hal_crc.h b/os/hal/include/hal_crc.h
index 8c4c895..d7ef10f 100644
--- a/os/hal/include/hal_crc.h
+++ b/os/hal/include/hal_crc.h
@@ -14,8 +14,8 @@
     limitations under the License.
 */
 
-#ifndef _CRC_H_
-#define _CRC_H_
+#ifndef HAL_CRC_H_
+#define HAL_CRC_H_
 
 #if (HAL_USE_CRC == TRUE) || defined(__DOXYGEN__)
 
@@ -153,6 +153,6 @@ extern "C" {
 
 #endif /* HAL_USE_CRC */
 
-#endif /* _CRC_H_ */
+#endif /* HAL_CRC_H_ */
 
 /** @} */
diff --git a/os/hal/include/hal_ee24xx.h b/os/hal/include/hal_ee24xx.h
index ab12fd1..00cdc95 100644
--- a/os/hal/include/hal_ee24xx.h
+++ b/os/hal/include/hal_ee24xx.h
@@ -4,8 +4,8 @@
   The work is provided "as is" without warranty of any kind, neither express nor implied.
 */
 
-#ifndef EE24XX_H
-#define EE24XX_H
+#ifndef HAL_EE24XX_H
+#define HAL_EE24XX_H
 
 #include "hal.h"
 
@@ -61,4 +61,4 @@ typedef struct {
 
 #endif /* #if defined(EEPROM_USE_EE24XX) && EEPROM_USE_EE24XX */
 
-#endif // EE24XX_H
+#endif // HAL_EE24XX_H
diff --git a/os/hal/include/hal_ee25xx.h b/os/hal/include/hal_ee25xx.h
index fc2ad6f..e520bd6 100644
--- a/os/hal/include/hal_ee25xx.h
+++ b/os/hal/include/hal_ee25xx.h
@@ -4,8 +4,8 @@
   The work is provided "as is" without warranty of any kind, neither express nor implied.
 */
 
-#ifndef EE25XX_H
-#define EE25XX_H
+#ifndef HAL_EE25XX_H
+#define HAL_EE25XX_H
 
 #include "hal.h"
 
@@ -60,4 +60,4 @@ EepromFileStream *SPIEepromFileOpen(SPIEepromFileStream *efs,
 
 #endif /* #if defined(EEPROM_USE_EE25XX) && EEPROM_USE_EE25XX */
 
-#endif // EE25XX_H
+#endif // HAL_EE25XX_H
diff --git a/os/hal/include/hal_eeprom.h b/os/hal/include/hal_eeprom.h
index cd05e14..25e03bd 100644
--- a/os/hal/include/hal_eeprom.h
+++ b/os/hal/include/hal_eeprom.h
@@ -26,10 +26,9 @@
   The work is provided "as is" without warranty of any kind, neither express nor implied.
 */
 
-#ifndef __EEPROM_H__
-#define __EEPROM_H__
+#ifndef HAL_EEPROM_H_
+#define HAL_EEPROM_H_
 
-#include "ch.h"
 #include "hal.h"
 
 #ifndef EEPROM_USE_EE25XX
@@ -140,4 +139,4 @@ msg_t eepfs_get(void *ip);
 #include "hal_ee25xx.h"
 
 #endif /* #if defined(HAL_USE_EEPROM) && HAL_USE_EEPROM */
-#endif /* __EEPROM_H__ */
+#endif /* HAL_EEPROM_H_ */
diff --git a/os/hal/include/hal_eicu.h b/os/hal/include/hal_eicu.h
index d4b0ed2..8b4b07d 100644
--- a/os/hal/include/hal_eicu.h
+++ b/os/hal/include/hal_eicu.h
@@ -22,8 +22,8 @@
    32-bit timers and timers with single capture/compare channels.
 */
 
-#ifndef _EICU_H_
-#define _EICU_H_
+#ifndef HAL_EICU_H_
+#define HAL_EICU_H_
 
 #if (HAL_USE_EICU == TRUE) || defined(__DOXYGEN__)
 
@@ -186,6 +186,6 @@ extern "C" {
 
 #endif /* HAL_USE_EICU */
 
-#endif /* _EICU_H_ */
+#endif /* HAL_EICU_H_ */
 
 /** @} */
diff --git a/os/hal/include/hal_nand.h b/os/hal/include/hal_nand.h
index d5a1c04..f907152 100644
--- a/os/hal/include/hal_nand.h
+++ b/os/hal/include/hal_nand.h
@@ -15,15 +15,15 @@
 */
 
 /**
- * @file    nand.h
+ * @file    hal_nand.h
  * @brief   NAND Driver macros and structures.
  *
  * @addtogroup NAND
  * @{
  */
 
-#ifndef _NAND_H_
-#define _NAND_H_
+#ifndef HAL_NAND_H_
+#define HAL_NAND_H_
 
 #if (HAL_USE_NAND == TRUE) || defined(__DOXYGEN__)
 
@@ -82,6 +82,7 @@ typedef enum {
   NAND_READ = 6,                     /**< Reading from NAND.              */
   NAND_DMA_TX = 7,                   /**< DMA transmitting.               */
   NAND_DMA_RX = 8,                   /**< DMA receiving.                  */
+  NAND_RESET = 9,                    /**< Software reset in progress.     */
 } nandstate_t;
 
 /**
@@ -106,21 +107,21 @@ extern "C" {
   void nandObjectInit(NANDDriver *nandp);
   void nandStart(NANDDriver *nandp, const NANDConfig *config, bitmap_t *bb_map);
   void nandStop(NANDDriver *nandp);
+  uint8_t nandErase(NANDDriver *nandp, uint32_t block);
   void nandReadPageWhole(NANDDriver *nandp, uint32_t block, uint32_t page,
-                         uint8_t *data, size_t datalen);
-  void nandMarkBad(NANDDriver *nandp, uint32_t block);
+                         void *data, size_t datalen);
   void nandReadPageData(NANDDriver *nandp, uint32_t block, uint32_t page,
-                        uint8_t *data, size_t datalen, uint32_t *ecc);
+                        void *data, size_t datalen, uint32_t *ecc);
   void nandReadPageSpare(NANDDriver *nandp, uint32_t block, uint32_t page,
-                         uint8_t *spare, size_t sparelen);
+                         void *spare, size_t sparelen);
   uint8_t nandWritePageWhole(NANDDriver *nandp, uint32_t block, uint32_t page,
-                             const uint8_t *data, size_t datalen);
+                             const void *data, size_t datalen);
   uint8_t nandWritePageData(NANDDriver *nandp, uint32_t block, uint32_t page,
-                            const uint8_t *data, size_t datalen, uint32_t *ecc);
+                            const void *data, size_t datalen, uint32_t *ecc);
   uint8_t nandWritePageSpare(NANDDriver *nandp, uint32_t block, uint32_t page,
-                             const uint8_t *spare, size_t sparelen);
-  uint8_t nandReadBadMark(NANDDriver *nandp, uint32_t block, uint32_t page);
-  uint8_t nandErase(NANDDriver *nandp, uint32_t block);
+                             const void *spare, size_t sparelen);
+  uint16_t nandReadBadMark(NANDDriver *nandp, uint32_t block, uint32_t page);
+  void nandMarkBad(NANDDriver *nandp, uint32_t block);
   bool nandIsBad(NANDDriver *nandp, uint32_t block);
 #if NAND_USE_MUTUAL_EXCLUSION
   void nandAcquireBus(NANDDriver *nandp);
diff --git a/os/hal/include/hal_onewire.h b/os/hal/include/hal_onewire.h
index 9fb5be2..bbaf77b 100644
--- a/os/hal/include/hal_onewire.h
+++ b/os/hal/include/hal_onewire.h
@@ -15,15 +15,15 @@
 */
 
 /**
- * @file    onewire.h
+ * @file    hal_onewire.h
  * @brief   1-wire Driver macros and structures.
  *
  * @addtogroup onewire
  * @{
  */
 
-#ifndef _ONEWIRE_H_
-#define _ONEWIRE_H_
+#ifndef HAL_ONEWIRE_H_
+#define HAL_ONEWIRE_H_
 
 #if (HAL_USE_ONEWIRE == TRUE) || defined(__DOXYGEN__)
 
@@ -59,11 +59,13 @@
 /*===========================================================================*/
 /* Driver pre-compile time settings.                                         */
 /*===========================================================================*/
+#if ONEWIRE_SYNTH_SEARCH_TEST && !ONEWIRE_USE_SEARCH_ROM
+#error "Synthetic search rom test needs ONEWIRE_USE_SEARCH_ROM"
+#endif
 
 /*===========================================================================*/
 /* Derived constants and error checks.                                       */
 /*===========================================================================*/
-
 #if !HAL_USE_PWM
 #error "1-wire Driver requires HAL_USE_PWM"
 #endif
@@ -328,7 +330,6 @@ extern onewireDriver OWD1;
 #ifdef __cplusplus
 extern "C" {
 #endif
-  void onewireInit(void);
   void onewireObjectInit(onewireDriver *owp);
   void onewireStart(onewireDriver *owp, const onewireConfig *config);
   void onewireStop(onewireDriver *owp);
@@ -352,7 +353,7 @@ extern "C" {
 
 #endif /* HAL_USE_ONEWIRE */
 
-#endif /* _ONEWIRE_H_ */
+#endif /* HAL_ONEWIRE_H_ */
 
 /** @} */
 
diff --git a/os/hal/include/hal_qei.h b/os/hal/include/hal_qei.h
index 92f03fc..ce4a089 100644
--- a/os/hal/include/hal_qei.h
+++ b/os/hal/include/hal_qei.h
@@ -65,8 +65,36 @@ typedef struct QEIDriver QEIDriver;
  */

 typedef void (*qeicallback_t)(QEIDriver *qeip);

 

+/**

+ * @brief   Driver possible handling of counter overflow/underflow.

+ *

+ * @details When counter is going to overflow, the new value is

+ *          computed according to this mode in such a way that 

+ *          the counter will either wrap around, stay unchange 

+ *          or reach min/max

+ *

+ * @note    All driver implementation should support the

+ *          QEI_OVERFLOW_WRAP mode.

+ *

+ * @note    Mode QEI_OVERFLOW_DISCARD and QEI_OVERFLOW_MINMAX are included

+ *          if QEI_USE_OVERFLOW_DISCARD and QEI_USE_OVERFLOW_MINMAX are

+ *          set to TRUE in halconf_community.h and are not necessary supported

+ *          by all drivers

+ */

+typedef enum {

+  QEI_OVERFLOW_WRAP    = 0,     /**< Counter value will wrap around.        */

+#if QEI_USE_OVERFLOW_DISCARD == TRUE

+  QEI_OVERFLOW_DISCARD = 1,     /**< Counter doesn't change.                */

+#endif

+#if QEI_USE_OVERFLOW_MINMAX == TRUE

+  QEI_OVERFLOW_MINMAX  = 2,     /**< Counter will be updated upto min or max.*/

+#endif

+} qeioverflow_t;

+

+

 #include "hal_qei_lld.h"

 

+

 /*===========================================================================*/

 /* Driver macros.                                                            */

 /*===========================================================================*/

@@ -119,6 +147,7 @@ extern "C" {
   qeicnt_t qeiGetCount(QEIDriver *qeip);

   qeidelta_t qeiUpdate(QEIDriver *qeip);

   qeidelta_t qeiUpdateI(QEIDriver *qeip);

+  qeidelta_t qeiAdjustI(QEIDriver *qeip, qeidelta_t delta);

 #ifdef __cplusplus

 }

 #endif

diff --git a/os/hal/include/hal_rng.h b/os/hal/include/hal_rng.h
index 0e3c484..dc146c7 100644
--- a/os/hal/include/hal_rng.h
+++ b/os/hal/include/hal_rng.h
@@ -14,8 +14,8 @@
     limitations under the License.
 */
 
-#ifndef _RNG_H_
-#define _RNG_H_
+#ifndef HAL_RNG_H_
+#define HAL_RNG_H_
 
 #if (HAL_USE_RNG == TRUE) || defined(__DOXYGEN__)
 
@@ -131,6 +131,6 @@ extern "C" {
 
 #endif /* HAL_USE_RNG */
 
-#endif /* _RNG_H_ */
+#endif /* HAL_RNG_H_ */
 
 /** @} */
diff --git a/os/hal/include/hal_timcap.h b/os/hal/include/hal_timcap.h
index bd43dd1..a5db7d8 100644
--- a/os/hal/include/hal_timcap.h
+++ b/os/hal/include/hal_timcap.h
@@ -19,17 +19,16 @@
 */
 
 /**
- * @file    timcap.h
+ * @file    hal_timcap.h
  * @brief   TIMCAP Driver macros and structures.
  *
  * @addtogroup TIMCAP
  * @{
  */
 
-#ifndef _TIMCAP_H_
-#define _TIMCAP_H_
+#ifndef HAL_TIMCAP_H_
+#define HAL_TIMCAP_H_
 
-#include "ch.h"
 #include "hal.h"
 
 #if (HAL_USE_TIMCAP == TRUE) || defined(__DOXYGEN__)
@@ -201,6 +200,6 @@ extern "C" {
 
 #endif /* HAL_USE_TIMCAP */
 
-#endif /* _TIMCAP_H_ */
+#endif /* HAL_TIMCAP_H_ */
 
 /** @} */
diff --git a/os/hal/include/hal_usb_hid.h b/os/hal/include/hal_usb_hid.h
index 2a2d73a..d50c455 100644
--- a/os/hal/include/hal_usb_hid.h
+++ b/os/hal/include/hal_usb_hid.h
@@ -70,17 +70,35 @@
  * @name    HID Report items

  * @{

  */

+#define HID_REPORT_INPUT                    0x80

+#define HID_REPORT_OUTPUT                   0x90

+#define HID_REPORT_COLLECTION               0xA0

+#define HID_REPORT_FEATURE                  0xB0

+#define HID_REPORT_END_COLLECTION           0xC0

+

 #define HID_REPORT_USAGE_PAGE               0x04

-#define HID_REPORT_USAGE                    0x08

 #define HID_REPORT_LOGICAL_MINIMUM          0x14

-#define HID_REPORT_USAGE_MINIMUM            0x18

 #define HID_REPORT_LOGICAL_MAXIMUM          0x24

-#define HID_REPORT_USAGE_MAXIMUM            0x28

+#define HID_REPORT_PHYSICAL_MINIMUM         0x34

+#define HID_REPORT_PHYSICAL_MAXIMUM         0x44

+#define HID_REPORT_UNIT_EXPONENT            0x54

+#define HID_REPORT_UNIT                     0x64

 #define HID_REPORT_REPORT_SIZE              0x74

-#define HID_REPORT_INPUT                    0x80

+#define HID_REPORT_REPORT_ID                0x84

 #define HID_REPORT_REPORT_COUNT             0x94

-#define HID_REPORT_COLLECTION               0xA0

-#define HID_REPORT_END_COLLECTION           0xC0

+#define HID_REPORT_REPORT_PUSH              0xA4

+#define HID_REPORT_REPORT_POP               0xB4

+

+#define HID_REPORT_USAGE                    0x08

+#define HID_REPORT_USAGE_MINIMUM            0x18

+#define HID_REPORT_USAGE_MAXIMUM            0x28

+#define HID_REPORT_DESIGNATOR_INDEX         0x38

+#define HID_REPORT_DESIGNATOR_MINUMUM       0x48

+#define HID_REPORT_DESIGNATOR_MAXIMUM       0x58

+#define HID_REPORT_STRING_INDEX             0x78

+#define HID_REPORT_STRING_MINUMUM           0x88

+#define HID_REPORT_STRING_MAXIMUM           0x98

+#define HID_REPORT_DELIMITER                0xA8

 /** @} */

 

 /**

@@ -115,6 +133,7 @@
 #define HID_USAGE_PAGE_DIGITIZER            0x0D

 #define HID_USAGE_PAGE_PID                  0x0F

 #define HID_USAGE_PAGE_UNICODE              0x10

+#define HID_USAGE_PAGE_VENDOR               0xFF00

 /** @} */

 

 /**

@@ -170,12 +189,35 @@
 /** @} */

 

 /**

- * @name    HID Input item definitions.

+ * @name    HID item types definitions

  * @{

  */

-#define HID_INPUT_DATA_VAR_ABS              0x02

-#define HID_INPUT_CNST_VAR_ABS              0x03

-#define HID_INPUT_DATA_VAR_REL              0x06

+#define HID_ITEM_DATA                       0x00

+#define HID_ITEM_CNST                       0x01

+#define HID_ITEM_ARR                        0x00

+#define HID_ITEM_VAR                        0x02

+#define HID_ITEM_ABS                        0x00

+#define HID_ITEM_REL                        0x04

+#define HID_ITEM_NWRP                       0x00

+#define HID_ITEM_WRP                        0x08

+#define HID_ITEM_LIN                        0x00

+#define HID_ITEM_NLIN                       0x10

+#define HID_ITEM_PRF                        0x00

+#define HID_ITEM_NPRF                       0x20

+#define HID_ITEM_NNUL                       0x00

+#define HID_ITEM_NUL                        0x40

+#define HID_ITEM_NVOL                       0x00

+#define HID_ITEM_VOL                        0x80

+

+#define HID_ITEM_DATA_VAR_ABS               (HID_ITEM_DATA |                \

+                                             HID_ITEM_VAR |                 \

+                                             HID_ITEM_ABS)

+#define HID_ITEM_CNST_VAR_ABS               (HID_ITEM_CNST |                \

+                                             HID_ITEM_VAR |                 \

+                                             HID_ITEM_ABS)

+#define HID_ITEM_DATA_VAR_REL               (HID_ITEM_DATA |                \

+                                             HID_ITEM_VAR |                 \

+                                             HID_ITEM_REL)

 /** @} */

 

 /**

@@ -202,46 +244,54 @@
   USB_DESC_WORD(wDescriptorLength)

 

 /**

+ * @brief   HID Report item helper macro (Single byte).

+ */

+#define HID_ITEM_B(id, value)                                               \

+  USB_DESC_BYTE(id | 0x01),                                                 \

+  USB_DESC_BYTE(value)

+

+/**

+ * @brief   HID Report item helper macro (Double byte).

+ */

+#define HID_ITEM_W(id, value)                                               \

+  USB_DESC_BYTE(id | 0x02),                                                 \

+  USB_DESC_WORD(value)

+

+/**

  * @brief   HID Report Usage Page item helper macro (Single byte).

  */

 #define HID_USAGE_PAGE_B(up)                                                \

-  USB_DESC_BYTE(HID_REPORT_USAGE_PAGE | 0x01),                              \

-  USB_DESC_BYTE(up)

+  HID_ITEM_B(HID_REPORT_USAGE_PAGE, up)

 

 /**

  * @brief   HID Report Usage Page item helper macro (Double byte).

  */

 #define HID_USAGE_PAGE_W(up)                                                \

-  USB_DESC_BYTE(HID_REPORT_USAGE_PAGE | 0x02),                              \

-  USB_DESC_WORD(up)

+  HID_ITEM_W(HID_REPORT_USAGE_PAGE, up)

 

 /**

  * @brief   HID Report Usage item helper macro (Single byte).

  */

 #define HID_USAGE_B(u)                                                      \

-  USB_DESC_BYTE(HID_REPORT_USAGE | 0x01),                                   \

-  USB_DESC_BYTE(u)

+  HID_ITEM_B(HID_REPORT_USAGE, u)

 

 /**

  * @brief   HID Report Usage item helper macro (Double byte).

  */

 #define HID_USAGE_W(u)                                                      \

-  USB_DESC_BYTE(HID_REPORT_USAGE | 0x02),                                   \

-  USB_DESC_WORD(u)

+  HID_ITEM_W(HID_REPORT_USAGE, u)

 

 /**

  * @brief   HID Report Collection item helper macro (Single Byte).

  */

-#define HID_COLLECTION_B(c)                                                   \

-  USB_DESC_BYTE(HID_REPORT_COLLECTION | 0x01),                                \

-  USB_DESC_BYTE(c)

+#define HID_COLLECTION_B(c)                                                 \

+  HID_ITEM_B(HID_REPORT_COLLECTION, c)

 

 /**

  * @brief   HID Report Collection item helper macro (Double Byte).

  */

-#define HID_COLLECTION_W(c)                                                   \

-  USB_DESC_BYTE(HID_REPORT_COLLECTION | 0x02),                                \

-  USB_DESC_WORD(c)

+#define HID_COLLECTION_W(c)                                                 \

+  HID_ITEM_W(HID_REPORT_COLLECTION, c)

 

 /**

  * @brief   HID Report End Collection item helper macro.

@@ -253,99 +303,110 @@
  * @brief   HID Report Usage Minimum item helper macro (Single byte).

  */

 #define HID_USAGE_MINIMUM_B(x)                                              \

-  USB_DESC_BYTE(HID_REPORT_USAGE_MINIMUM | 0x01),                           \

-  USB_DESC_BYTE(x)

-

+  HID_ITEM_B(HID_REPORT_USAGE_MINIMUM, x)

+  

 /**

  * @brief   HID Report Usage Minimum item helper macro (Double byte).

  */

 #define HID_USAGE_MINIMUM_W(x)                                              \

-  USB_DESC_BYTE(HID_REPORT_USAGE_MINIMUM | 0x02),                           \

-  USB_DESC_WORD(x)

+  HID_ITEM_W(HID_REPORT_USAGE_MINIMUM, x)

 

 /**

  * @brief   HID Report Usage Maximum item helper macro (Single byte).

  */

 #define HID_USAGE_MAXIMUM_B(x)                                              \

-  USB_DESC_BYTE(HID_REPORT_USAGE_MAXIMUM | 0x01),                           \

-  USB_DESC_BYTE(x)

-

+  HID_ITEM_B(HID_REPORT_USAGE_MAXIMUM, x)

+  

 /**

  * @brief   HID Report Usage Maximum item helper macro (Double byte).

  */

 #define HID_USAGE_MAXIMUM_W(x)                                              \

-  USB_DESC_BYTE(HID_REPORT_USAGE_MAXIMUM | 0x02),                           \

-  USB_DESC_WORD(x)

+  HID_ITEM_W(HID_REPORT_USAGE_MAXIMUM, x)

 

 /**

  * @brief   HID Report Logical Minimum item helper macro (Single byte).

  */

 #define HID_LOGICAL_MINIMUM_B(x)                                            \

-  USB_DESC_BYTE(HID_REPORT_LOGICAL_MINIMUM | 0x01),                         \

-  USB_DESC_BYTE(x)

+  HID_ITEM_B(HID_REPORT_LOGICAL_MINIMUM, x)

 

 /**

  * @brief   HID Report Logical Minimum item helper macro (Double byte).

  */

 #define HID_LOGICAL_MINIMUM_W(x)                                            \

-  USB_DESC_BYTE(HID_REPORT_LOGICAL_MINIMUM | 0x02),                         \

-  USB_DESC_WORD(x)

+  HID_ITEM_W(HID_REPORT_LOGICAL_MINIMUM, x)

 

 /**

  * @brief   HID Report Logical Maximum item helper macro (Single byte).

  */

 #define HID_LOGICAL_MAXIMUM_B(x)                                            \

-  USB_DESC_BYTE(HID_REPORT_LOGICAL_MAXIMUM | 0x01),                         \

-  USB_DESC_BYTE(x)

+  HID_ITEM_B(HID_REPORT_LOGICAL_MAXIMUM, x)

 

 /**

  * @brief   HID Report Logical Maximum item helper macro (Double byte).

  */

 #define HID_LOGICAL_MAXIMUM_W(x)                                            \

-  USB_DESC_BYTE(HID_REPORT_LOGICAL_MAXIMUM | 0x02),                         \

-  USB_DESC_WORD(x)

+  HID_ITEM_W(HID_REPORT_LOGICAL_MAXIMUM, x)

 

 /**

+ * @brief   HID Report ID item helper macro (Single byte).

+ */

+#define HID_REPORT_ID_B(x)                                               \

+  HID_ITEM_B(HID_REPORT_REPORT_ID, x)

+

+/**

+ * @brief   HID Report ID item helper macro (Double byte).

+ */

+#define HID_REPORT_ID_W(x)                                               \

+  HID_ITEM_W(HID_REPORT_REPORT_ID, x)

+  

+/**

  * @brief   HID Report Count item helper macro (Single byte).

  */

 #define HID_REPORT_COUNT_B(x)                                               \

-  USB_DESC_BYTE(HID_REPORT_REPORT_COUNT | 0x01),                            \

-  USB_DESC_BYTE(x)

+  HID_ITEM_B(HID_REPORT_REPORT_COUNT, x)

 

 /**

  * @brief   HID Report Count item helper macro (Double byte).

  */

 #define HID_REPORT_COUNT_W(x)                                               \

-  USB_DESC_BYTE(HID_REPORT_REPORT_COUNT | 0x02),                            \

-  USB_DESC_WORD(x)

+  HID_ITEM_W(HID_REPORT_REPORT_COUNT, x)

 

 /**

  * @brief   HID Report Size item helper macro (Single byte).

  */

 #define HID_REPORT_SIZE_B(x)                                                \

-  USB_DESC_BYTE(HID_REPORT_REPORT_SIZE | 0x01),                             \

-  USB_DESC_BYTE(x)

+  HID_ITEM_B(HID_REPORT_REPORT_SIZE, x)

 

 /**

  * @brief   HID Report Size item helper macro (Double byte).

  */

 #define HID_REPORT_SIZE_W(x)                                                \

-  USB_DESC_BYTE(HID_REPORT_REPORT_SIZE | 0x02),                             \

-  USB_DESC_WORD(x)

+  HID_ITEM_W(HID_REPORT_REPORT_SIZE, x)

 

 /**

  * @brief   HID Report Input item helper macro (Single byte).

  */

 #define HID_INPUT_B(x)                                                      \

-  USB_DESC_BYTE(HID_REPORT_INPUT | 0x01),                                   \

-  USB_DESC_BYTE(x)

+  HID_ITEM_B(HID_REPORT_INPUT, x)

 

 /**

  * @brief   HID Report Input item helper macro (Double byte).

  */

 #define HID_INPUT_W(x)                                                      \

-  USB_DESC_BYTE(HID_REPORT_INPUT | 0x02),                                   \

-  USB_DESC_WORD(x)

+  HID_ITEM_W(HID_REPORT_INPUT, x)

+/** @} */

+

+/**

+ * @brief   HID Report Output item helper macro (Single byte).

+ */

+#define HID_OUTPUT_B(x)                                                     \

+  HID_ITEM_B(HID_REPORT_OUTPUT, x)

+

+/**

+ * @brief   HID Report Output item helper macro (Double byte).

+ */

+#define HID_OUTPUT_W(x)                                                     \

+  HID_ITEM_W(HID_REPORT_OUTPUT, x)

 /** @} */

 

 /*===========================================================================*/

diff --git a/os/hal/include/hal_usb_msd.h b/os/hal/include/hal_usb_msd.h
new file mode 100644
index 0000000..0fe03e4
--- /dev/null
+++ b/os/hal/include/hal_usb_msd.h
@@ -0,0 +1,196 @@
+/*
+    ChibiOS/HAL - Copyright (C) 2016 Uladzimir Pylinsky aka barthess
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    hal_usb_msd.h
+ * @brief   USM mass storage device driver macros and structures.
+ *
+ * @addtogroup usb_msd
+ * @{
+ */
+
+#ifndef HAL_USB_MSD_H
+#define HAL_USB_MSD_H
+
+#if (HAL_USE_USB_MSD == TRUE) || defined(__DOXYGEN__)
+
+#include "lib_scsi.h"
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+#define USB_MSD_DATA_EP                 0x01
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if !HAL_USE_USB
+#error "Mass storage Driver requires HAL_USE_USB"
+#endif
+
+#if !USB_USE_WAIT
+#error "Mass storage Driver requires USB_USE_WAIT"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of a structure representing an USB mass storage driver.
+ */
+typedef struct USBMassStorageDriver USBMassStorageDriver;
+
+/**
+ * @brief   Type of a driver state machine possible states.
+ */
+typedef enum {
+  USB_MSD_UNINIT = 0,
+  USB_MSD_STOP,
+  USB_MSD_READY,
+} usbmsdstate_t;
+
+/**
+ * @brief   Represents command block wrapper structure.
+ * @details See USB Mass Storage Class Specification.
+ */
+typedef struct PACKED_VAR {
+  uint32_t  signature;
+  uint32_t  tag;
+  uint32_t  data_len;
+  uint8_t   flags;
+  uint8_t   lun;
+  uint8_t   cmd_len;
+  uint8_t   cmd_data[16];
+} msd_cbw_t;
+
+/**
+ * @brief   Represents command status wrapper structure.
+ * @details See USB Mass Storage Class Specification.
+ */
+typedef struct PACKED_VAR {
+  uint32_t  signature;
+  uint32_t  tag;
+  uint32_t  data_residue;
+  uint8_t   status;
+} msd_csw_t;
+
+/**
+ * @brief   Transport handler passed to SCSI layer.
+ */
+typedef struct {
+  /**
+   * @brief   Pointer to the @p USBDriver object.
+   */
+  USBDriver *usbp;
+  /**
+   * @brief   USB endpoint number.
+   */
+  usbep_t   ep;
+} usb_scsi_transport_handler_t;
+
+
+/**
+ * @brief   Structure representing an USB mass storage driver.
+ */
+struct USBMassStorageDriver {
+  /**
+   * @brief   Pointer to the @p USBDriver object.
+   */
+  USBDriver                     *usbp;
+  /**
+   * @brief   Driver state.
+   */
+  usbmsdstate_t                 state;
+  /**
+   * @brief   CBW structure.
+   */
+  msd_cbw_t                     cbw;
+  /**
+   * @brief   CSW structure.
+   */
+  msd_csw_t                     csw;
+  /**
+   * @brief   Thread working area.
+   */
+  THD_WORKING_AREA(             waMSDWorker, 512);
+  /**
+   * @brief   Worker thread handler.
+   */
+  thread_reference_t            worker;
+  /**
+   * @brief   SCSI target driver structure.
+   */
+  SCSITarget                    scsi_target;
+  /**
+   * @brief   SCSI target configuration structure.
+   */
+  SCSITargetConfig              scsi_config;
+  /**
+   * @brief   SCSI transport structure.
+   */
+  SCSITransport                 scsi_transport;
+  /**
+   * @brief   SCSI over USB transport handler structure.
+   */
+  usb_scsi_transport_handler_t  usb_scsi_transport_handler;
+};
+
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+extern USBMassStorageDriver USBMSD1;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void msdObjectInit(USBMassStorageDriver *msdp);
+  void msdStart(USBMassStorageDriver *msdp, USBDriver *usbp,
+                BaseBlockDevice *blkdev, uint8_t *blkbuf,
+                const scsi_inquiry_response_t *scsi_inquiry_response,
+                const scsi_unit_serial_number_inquiry_response_t *serialInquiry);
+  void msdStop(USBMassStorageDriver *msdp);
+  bool msd_request_hook(USBDriver *usbp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_USB_MSD */
+
+#endif /* HAL_USB_MSD_H */
+
+/** @} */
+
+
+
+
+
+
+
+
+
diff --git a/os/hal/include/hal_usbh.h b/os/hal/include/hal_usbh.h
index 5fd0047..1ed6416 100644
--- a/os/hal/include/hal_usbh.h
+++ b/os/hal/include/hal_usbh.h
@@ -1,6 +1,6 @@
 /*
-    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
-              Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail)
+    ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio
+              Copyright (C) 2015..2017 Diego Ismirlian, (dismirlian (at) google's mail)
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -15,11 +15,14 @@
     limitations under the License.
 */
 
-#ifndef USBH_H_
-#define USBH_H_
+#ifndef HAL_USBH_H_
+#define HAL_USBH_H_
 
 #include "hal.h"
 
+#ifndef HAL_USE_USBH
+#define HAL_USE_USBH FALSE
+#endif
 
 #ifndef HAL_USBH_USE_FTDI
 #define HAL_USBH_USE_FTDI FALSE
@@ -37,19 +40,26 @@
 #define HAL_USBH_USE_UVC FALSE
 #endif
 
+#ifndef HAL_USBH_USE_AOA
+#define HAL_USBH_USE_AOA FALSE
+#endif
+
+#ifndef HAL_USBH_USE_HID
+#define HAL_USBH_USE_HID FALSE
+#endif
+
+#ifndef HAL_USBH_USE_ADDITIONAL_CLASS_DRIVERS
+#define HAL_USBH_USE_ADDITIONAL_CLASS_DRIVERS	FALSE
+#endif
+
+#define HAL_USBH_USE_IAD     HAL_USBH_USE_UVC
+
 #if (HAL_USE_USBH == TRUE) || defined(__DOXYGEN__)
 
 #include "osal.h"
 #include "usbh/list.h"
 #include "usbh/defs.h"
 
-/* TODO:
- *
- * - Integrate VBUS power switching functionality to the API.
- *
- */
-
-
 /*===========================================================================*/
 /* Derived constants and error checks.                                       */
 /*===========================================================================*/
@@ -66,6 +76,7 @@ enum usbh_status {
 	USBH_STATUS_SUSPENDED,
 };
 
+/* These correspond to the USB spec */
 enum usbh_devstatus {
 	USBH_DEVSTATUS_DISCONNECTED = 0,
 	USBH_DEVSTATUS_ATTACHED,
@@ -104,13 +115,11 @@ enum usbh_urbstatus {
 	USBH_URBSTATUS_UNINITIALIZED = 0,
 	USBH_URBSTATUS_INITIALIZED,
 	USBH_URBSTATUS_PENDING,
-//	USBH_URBSTATUS_QUEUED,
 	USBH_URBSTATUS_ERROR,
 	USBH_URBSTATUS_TIMEOUT,
 	USBH_URBSTATUS_CANCELLED,
 	USBH_URBSTATUS_STALL,
 	USBH_URBSTATUS_DISCONNECTED,
-//	USBH_URBSTATUS_EPCLOSED,
 	USBH_URBSTATUS_OK,
 };
 
@@ -145,7 +154,8 @@ typedef void (*usbh_completion_cb)(usbh_urb_t *);
 /* include the low level driver; the required definitions are above */
 #include "hal_usbh_lld.h"
 
-#define USBH_DEFINE_BUFFER(type, name)	USBH_LLD_DEFINE_BUFFER(type, name)
+#define USBH_DEFINE_BUFFER(var)	USBH_LLD_DEFINE_BUFFER(var)
+#define USBH_DECLARE_STRUCT_MEMBER(member) USBH_LLD_DECLARE_STRUCT_MEMBER(member)
 
 struct usbh_urb {
 	usbh_ep_t *ep;
@@ -198,9 +208,8 @@ struct usbh_device {
 	usbh_devstatus_t status;
 	usbh_devspeed_t speed;
 
-	USBH_DEFINE_BUFFER(usbh_device_descriptor_t, devDesc);
-	unsigned char align_bytes[2];
-	USBH_DEFINE_BUFFER(usbh_config_descriptor_t, basicConfigDesc);
+	USBH_DECLARE_STRUCT_MEMBER(usbh_device_descriptor_t devDesc);
+	USBH_DECLARE_STRUCT_MEMBER(usbh_config_descriptor_t basicConfigDesc);
 
 	uint8_t *fullConfigurationDescriptor;
 	uint8_t keepFullCfgDesc;
@@ -258,14 +267,6 @@ struct USBHDriver {
 /* External declarations.                                                    */
 /*===========================================================================*/
 
-#if STM32_USBH_USE_OTG1
-extern USBHDriver USBHD1;
-#endif
-
-#if STM32_USBH_USE_OTG2
-extern USBHDriver USBHD2;
-#endif
-
 
 /*===========================================================================*/
 /* Main driver API.		                                                     */
@@ -351,10 +352,8 @@ extern "C" {
 		osalDbgCheck(ep != 0);
 		osalDbgCheckClassS();
 		osalDbgAssert(ep->status != USBH_EPSTATUS_UNINITIALIZED, "invalid state");
-		if (ep->status == USBH_EPSTATUS_CLOSED) {
-			osalOsRescheduleS();
+		if (ep->status == USBH_EPSTATUS_CLOSED)
 			return;
-		}
 		usbh_lld_ep_close(ep);
 	}
 	static inline void usbhEPClose(usbh_ep_t *ep) {
@@ -362,11 +361,7 @@ extern "C" {
 		usbhEPCloseS(ep);
 		osalSysUnlock();
 	}
-	static inline void usbhEPResetI(usbh_ep_t *ep) {
-		osalDbgCheckClassI();
-		osalDbgCheck(ep != NULL);
-		usbh_lld_epreset(ep);
-	}
+	bool usbhEPReset(usbh_ep_t *ep);
 	static inline bool usbhEPIsPeriodic(usbh_ep_t *ep) {
 		osalDbgCheck(ep != NULL);
 		return (ep->type & 1) != 0;
@@ -389,6 +384,22 @@ extern "C" {
 	void usbhURBCancelAndWaitS(usbh_urb_t *urb);
 	msg_t usbhURBWaitTimeoutS(usbh_urb_t *urb, systime_t timeout);
 
+	static inline void usbhURBSubmit(usbh_urb_t *urb) {
+		osalSysLock();
+		usbhURBSubmitI(urb);
+		osalOsRescheduleS();
+		osalSysUnlock();
+	}
+
+	static inline bool usbhURBCancel(usbh_urb_t *urb) {
+		bool ret;
+		osalSysLock();
+		ret = usbhURBCancelI(urb);
+		osalOsRescheduleS();
+		osalSysUnlock();
+		return ret;
+	}
+
 	/* Main loop */
 	void usbhMainLoop(USBHDriver *usbh);
 
@@ -403,14 +414,13 @@ extern "C" {
 
 typedef struct usbh_classdriver_vmt usbh_classdriver_vmt_t;
 struct usbh_classdriver_vmt {
+	void (*init)(void);
 	usbh_baseclassdriver_t *(*load)(usbh_device_t *dev,	const uint8_t *descriptor, uint16_t rem);
 	void (*unload)(usbh_baseclassdriver_t *drv);
+	/* TODO: add power control, suspend, etc */
 };
 
 struct usbh_classdriverinfo {
-	int16_t class;
-	int16_t subclass;
-	int16_t protocol;
 	const char *name;
 	const usbh_classdriver_vmt_t *vmt;
 };
@@ -424,13 +434,6 @@ struct usbh_baseclassdriver {
 	_usbh_base_classdriver_data
 };
 
-
-/*===========================================================================*/
-/* Helper functions.				                                         */
-/*===========================================================================*/
-#include <usbh/desciter.h>	/* descriptor iterators */
-#include <usbh/debug.h>		/* debug */
-
 #endif
 
-#endif /* USBH_H_ */
+#endif /* HAL_USBH_H_ */
diff --git a/os/hal/include/usbh/debug.h b/os/hal/include/usbh/debug.h
index 5120121..d3bdee7 100644
--- a/os/hal/include/usbh/debug.h
+++ b/os/hal/include/usbh/debug.h
@@ -1,6 +1,6 @@
 /*

-    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio

-              Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail)

+    ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio

+              Copyright (C) 2015..2017 Diego Ismirlian, (dismirlian (at) google's mail)

 

     Licensed under the Apache License, Version 2.0 (the "License");

     you may not use this file except in compliance with the License.

@@ -23,8 +23,6 @@
 

 #if HAL_USE_USBH

 

-//TODO: Debug is only for USBHD1, make it generic.

-

 #if USBH_DEBUG_ENABLE

 	void usbDbgPrintf(const char *fmt, ...);

 	void usbDbgPuts(const char *s);

diff --git a/os/hal/include/usbh/defs.h b/os/hal/include/usbh/defs.h
index c3d8a9a..5e0c466 100644
--- a/os/hal/include/usbh/defs.h
+++ b/os/hal/include/usbh/defs.h
@@ -1,6 +1,6 @@
 /*

-    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio

-              Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail)

+    ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio

+              Copyright (C) 2015..2017 Diego Ismirlian, (dismirlian (at) google's mail)

 

     Licensed under the Apache License, Version 2.0 (the "License");

     you may not use this file except in compliance with the License.

@@ -25,12 +25,12 @@
 #include "osal.h"

 

 #ifdef __IAR_SYSTEMS_ICC__

-#define PACKED_STRUCT typedef PACKED_VAR struct

+#define PACKED_STRUCT PACKED_VAR struct

 #else

-#define PACKED_STRUCT typedef struct PACKED_VAR

+#define PACKED_STRUCT struct PACKED_VAR

 #endif

 

-PACKED_STRUCT {

+typedef PACKED_STRUCT {

 	uint8_t  bLength;

 	uint8_t  bDescriptorType;

 	uint16_t bcdUSB;

@@ -49,7 +49,7 @@ PACKED_STRUCT {
 #define USBH_DT_DEVICE                   0x01

 #define USBH_DT_DEVICE_SIZE              18

 

-PACKED_STRUCT {

+typedef PACKED_STRUCT {

 	uint8_t  bLength;

 	uint8_t  bDescriptorType;

 	uint16_t wTotalLength;

@@ -62,7 +62,7 @@ PACKED_STRUCT {
 #define USBH_DT_CONFIG                   0x02

 #define USBH_DT_CONFIG_SIZE              9

 

-PACKED_STRUCT {

+typedef PACKED_STRUCT {

 	uint8_t  bLength;

 	uint8_t  bDescriptorType;

 	uint16_t wData[1];

@@ -70,7 +70,7 @@ PACKED_STRUCT {
 #define USBH_DT_STRING                   0x03

 #define USBH_DT_STRING_SIZE              2

 

-PACKED_STRUCT {

+typedef PACKED_STRUCT {

 	uint8_t  bLength;

 	uint8_t  bDescriptorType;

 	uint8_t  bInterfaceNumber;

@@ -84,7 +84,7 @@ PACKED_STRUCT {
 #define USBH_DT_INTERFACE                0x04

 #define USBH_DT_INTERFACE_SIZE           9

 

-PACKED_STRUCT {

+typedef PACKED_STRUCT {

 	uint8_t	bLength;

 	uint8_t	bDescriptorType;

 	uint8_t	bEndpointAddress;

@@ -95,7 +95,7 @@ PACKED_STRUCT {
 #define USBH_DT_ENDPOINT                 0x05

 #define USBH_DT_ENDPOINT_SIZE            7

 

-PACKED_STRUCT {

+typedef PACKED_STRUCT {

 	uint8_t  bLength;

 	uint8_t  bDescriptorType;

 	uint8_t  bFirstInterface;

@@ -108,7 +108,7 @@ PACKED_STRUCT {
 #define USBH_DT_INTERFACE_ASSOCIATION    	0x0b

 #define USBH_DT_INTERFACE_ASSOCIATION_SIZE	8

 

-PACKED_STRUCT {

+typedef PACKED_STRUCT {

 	uint8_t  bDescLength;

 	uint8_t  bDescriptorType;

 	uint8_t  bNbrPorts;

@@ -120,7 +120,7 @@ PACKED_STRUCT {
 #define USBH_DT_HUB				    	0x29

 #define USBH_DT_HUB_SIZE		    	(7 + 4)

 

-PACKED_STRUCT {

+typedef PACKED_STRUCT {

 	uint8_t  bmRequestType;

 	uint8_t  bRequest;

 	uint16_t wValue;

@@ -141,18 +141,17 @@ PACKED_STRUCT {
 #define USBH_REQ_SET_INTERFACE           0x0B

 #define USBH_REQ_SYNCH_FRAME             0x0C

 

+#define USBH_REQTYPE_DIR_IN				0x80

+#define USBH_REQTYPE_DIR_OUT			0x00

 

-#define USBH_REQTYPE_IN					0x80

-#define USBH_REQTYPE_OUT				0x00

+#define USBH_REQTYPE_TYPE_STANDARD		0x00

+#define USBH_REQTYPE_TYPE_CLASS			0x20

+#define USBH_REQTYPE_TYPE_VENDOR		0x40

 

-#define USBH_REQTYPE_STANDARD			0x00

-#define USBH_REQTYPE_CLASS				0x20

-#define USBH_REQTYPE_VENDOR				0x40

-

-#define USBH_REQTYPE_DEVICE				0x00

-#define USBH_REQTYPE_INTERFACE			0x01

-#define USBH_REQTYPE_ENDPOINT			0x02

-#define USBH_REQTYPE_OTHER				0x03

+#define USBH_REQTYPE_RECIP_DEVICE		0x00

+#define USBH_REQTYPE_RECIP_INTERFACE	0x01

+#define USBH_REQTYPE_RECIP_ENDPOINT		0x02

+#define USBH_REQTYPE_RECIP_OTHER		0x03

 

 #endif

 

diff --git a/os/hal/include/usbh/desciter.h b/os/hal/include/usbh/desciter.h
index 52b0c98..142bd3c 100644
--- a/os/hal/include/usbh/desciter.h
+++ b/os/hal/include/usbh/desciter.h
@@ -1,6 +1,6 @@
 /*

-    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio

-              Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail)

+    ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio

+              Copyright (C) 2015..2017 Diego Ismirlian, (dismirlian (at) google's mail)

 

     Licensed under the Apache License, Version 2.0 (the "License");

     you may not use this file except in compliance with the License.

diff --git a/os/hal/include/usbh/dev/aoa.h b/os/hal/include/usbh/dev/aoa.h
new file mode 100644
index 0000000..a7f1c1b
--- /dev/null
+++ b/os/hal/include/usbh/dev/aoa.h
@@ -0,0 +1,152 @@
+/*
+    ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio
+              Copyright (C) 2015..2017 Diego Ismirlian, (dismirlian (at) google's mail)
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef USBH_AOA_H_
+#define USBH_AOA_H_
+
+#include "hal_usbh.h"
+
+#if HAL_USE_USBH && HAL_USBH_USE_AOA
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+typedef enum {
+	USBHAOA_CHANNEL_STATE_UNINIT = 0,
+	USBHAOA_CHANNEL_STATE_STOP = 1,
+	USBHAOA_CHANNEL_STATE_ACTIVE = 2,
+	USBHAOA_CHANNEL_STATE_READY = 3
+} usbhaoa_channel_state_t;
+
+typedef enum {
+	USBHAOA_STATE_UNINIT = 0,
+	USBHAOA_STATE_STOP = 1,
+	USBHAOA_STATE_ACTIVE = 2,
+	USBHAOA_STATE_READY = 3
+} usbhaoa_state_t;
+
+typedef enum {
+	USBHAOA_AUDIO_MODE_DISABLED = 0,
+	USBHAOA_AUDIO_MODE_2CH_16BIT_PCM_44100 = 1,
+} usbhaoa_audio_mode_t;
+
+typedef struct {
+	struct _aoa_channel_cfg {
+		const char *manufacturer;
+		const char *model;
+		const char *description;
+		const char *version;
+		const char *uri;
+		const char *serial;
+	} channel;
+
+	struct _aoa_audio_cfg {
+		usbhaoa_audio_mode_t mode;
+	} audio;
+
+} USBHAOAConfig;
+
+#define _aoa_driver_methods                                          \
+  _base_asynchronous_channel_methods
+
+struct AOADriverVMT {
+	_aoa_driver_methods
+};
+
+typedef struct USBHAOAChannel USBHAOAChannel;
+typedef struct USBHAOADriver USBHAOADriver;
+
+struct USBHAOAChannel {
+	/* inherited from abstract asyncrhonous channel driver */
+	const struct AOADriverVMT *vmt;
+	_base_asynchronous_channel_data
+
+	usbh_ep_t epin;
+	usbh_urb_t iq_urb;
+	threads_queue_t	iq_waiting;
+	uint32_t iq_counter;
+	USBH_DECLARE_STRUCT_MEMBER(uint8_t iq_buff[64]);
+	uint8_t *iq_ptr;
+
+	usbh_ep_t epout;
+	usbh_urb_t oq_urb;
+	threads_queue_t	oq_waiting;
+	uint32_t oq_counter;
+	USBH_DECLARE_STRUCT_MEMBER(uint8_t oq_buff[64]);
+	uint8_t *oq_ptr;
+
+	virtual_timer_t vt;
+
+	usbhaoa_channel_state_t state;
+};
+
+struct USBHAOADriver {
+	/* inherited from abstract class driver */
+	_usbh_base_classdriver_data
+
+	USBHAOAChannel channel;
+
+	usbhaoa_state_t state;
+
+};
+
+#define USBHAOA_ACCESSORY_STRING_MANUFACTURER   0
+#define USBHAOA_ACCESSORY_STRING_MODEL          1
+#define USBHAOA_ACCESSORY_STRING_DESCRIPTION    2
+#define USBHAOA_ACCESSORY_STRING_VERSION        3
+#define USBHAOA_ACCESSORY_STRING_URI            4
+#define USBHAOA_ACCESSORY_STRING_SERIAL         5
+
+typedef bool (*usbhaoa_filter_callback_t)(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem, USBHAOAConfig *config);
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+#define usbhaoaStop(aoap)
+
+#define usbhaoaGetState(aoap) ((aoap)->state)
+
+#define usbhaoaGetChannelState(aoap) ((aoap)->channel.state)
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+extern USBHAOADriver USBHAOAD[HAL_USBHAOA_MAX_INSTANCES];
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+	/* AOA device driver */
+	void usbhaoaChannelStart(USBHAOADriver *aoap);
+	void usbhaoaChannelStop(USBHAOADriver *aoap);
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
+
+#endif /* USBH_AOA_H_ */
diff --git a/os/hal/include/usbh/dev/ftdi.h b/os/hal/include/usbh/dev/ftdi.h
index ad6b4cd..eedb056 100644
--- a/os/hal/include/usbh/dev/ftdi.h
+++ b/os/hal/include/usbh/dev/ftdi.h
@@ -1,6 +1,6 @@
 /*

-    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio

-              Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail)

+    ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio

+              Copyright (C) 2015..2017 Diego Ismirlian, (dismirlian (at) google's mail)

 

     Licensed under the Apache License, Version 2.0 (the "License");

     you may not use this file except in compliance with the License.

@@ -96,7 +96,7 @@ struct USBHFTDIPortDriver {
 	usbh_urb_t iq_urb;

 	threads_queue_t	iq_waiting;

 	uint32_t iq_counter;

-	USBH_DEFINE_BUFFER(uint8_t, iq_buff[64]);

+	USBH_DECLARE_STRUCT_MEMBER(uint8_t iq_buff[64]);

 	uint8_t *iq_ptr;

 

 

@@ -104,7 +104,7 @@ struct USBHFTDIPortDriver {
 	usbh_urb_t oq_urb;

 	threads_queue_t	oq_waiting;

 	uint32_t oq_counter;

-	USBH_DEFINE_BUFFER(uint8_t, oq_buff[64]);

+	USBH_DECLARE_STRUCT_MEMBER(uint8_t oq_buff[64]);

 	uint8_t *oq_ptr;

 

 	virtual_timer_t vt;

@@ -113,7 +113,7 @@ struct USBHFTDIPortDriver {
 	USBHFTDIPortDriver *next;

 };

 

-typedef struct USBHFTDIDriver {

+struct USBHFTDIDriver {

 	/* inherited from abstract class driver */

 	_usbh_base_classdriver_data

 

@@ -121,11 +121,12 @@ typedef struct USBHFTDIDriver {
 	USBHFTDIPortDriver *ports;

 

 	mutex_t mtx;

-} USBHFTDIDriver;

+};

 

 /*===========================================================================*/

 /* Driver macros.                                                            */

 /*===========================================================================*/

+#define usbhftdipGetState(ftdipp) ((ftdipp)->state)

 

 

 /*===========================================================================*/

@@ -137,11 +138,7 @@ extern USBHFTDIPortDriver FTDIPD[HAL_USBHFTDI_MAX_PORTS];
 #ifdef __cplusplus

 extern "C" {

 #endif

-	/* FTDI device driver */

-	void usbhftdiObjectInit(USBHFTDIDriver *ftdip);

-

 	/* FTDI port driver */

-	void usbhftdipObjectInit(USBHFTDIPortDriver *ftdipp);

 	void usbhftdipStart(USBHFTDIPortDriver *ftdipp, const USBHFTDIPortConfig *config);

 	void usbhftdipStop(USBHFTDIPortDriver *ftdipp);

 #ifdef __cplusplus

diff --git a/os/hal/include/usbh/dev/hid.h b/os/hal/include/usbh/dev/hid.h
new file mode 100644
index 0000000..c7371ee
--- /dev/null
+++ b/os/hal/include/usbh/dev/hid.h
@@ -0,0 +1,144 @@
+/*
+    ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio
+              Copyright (C) 2015..2017 Diego Ismirlian, (dismirlian (at) google's mail)
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef USBH_HID_H_
+#define USBH_HID_H_
+
+#include "hal_usbh.h"
+
+#if HAL_USE_USBH && HAL_USBH_USE_HID
+
+/* TODO:
+ *
+ */
+
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+#if !defined(HAL_USBHHID_USE_INTERRUPT_OUT)
+#define HAL_USBHHID_USE_INTERRUPT_OUT 				FALSE
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+typedef enum {
+	USBHHID_STATE_UNINIT = 0,
+	USBHHID_STATE_STOP = 1,
+	USBHHID_STATE_ACTIVE = 2,
+	USBHHID_STATE_READY = 3
+} usbhhid_state_t;
+
+typedef enum {
+	USBHHID_DEVTYPE_GENERIC = 0,
+	USBHHID_DEVTYPE_BOOT_KEYBOARD = 1,
+	USBHHID_DEVTYPE_BOOT_MOUSE = 2,
+} usbhhid_devtype_t;
+
+typedef enum {
+	USBHHID_REPORTTYPE_INPUT = 1,
+	USBHHID_REPORTTYPE_OUTPUT = 2,
+	USBHHID_REPORTTYPE_FEATURE = 3,
+} usbhhid_reporttype_t;
+
+typedef enum {
+	USBHHID_PROTOCOL_BOOT = 0,
+	USBHHID_PROTOCOL_REPORT = 1,
+} usbhhid_protocol_t;
+
+typedef struct USBHHIDDriver USBHHIDDriver;
+typedef struct USBHHIDConfig USBHHIDConfig;
+
+typedef void (*usbhhid_report_callback)(USBHHIDDriver *hidp, uint16_t len);
+
+struct USBHHIDConfig {
+	usbhhid_report_callback cb_report;
+	void *report_buffer;
+	uint16_t report_len;
+	usbhhid_protocol_t protocol;
+};
+
+struct USBHHIDDriver {
+	/* inherited from abstract class driver */
+	_usbh_base_classdriver_data
+
+	usbh_ep_t epin;
+#if HAL_USBHHID_USE_INTERRUPT_OUT
+	usbh_ep_t epout;
+#endif
+	uint8_t ifnum;
+
+	usbhhid_devtype_t type;
+	usbhhid_state_t state;
+
+	usbh_urb_t in_urb;
+
+	const USBHHIDConfig *config;
+
+	semaphore_t sem;
+};
+
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+extern USBHHIDDriver USBHHIDD[HAL_USBHHID_MAX_INSTANCES];
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+	/* HID Common API */
+	usbh_urbstatus_t usbhhidGetReport(USBHHIDDriver *hidp,
+			uint8_t report_id, usbhhid_reporttype_t report_type,
+			void *data, uint16_t len);
+	usbh_urbstatus_t usbhhidSetReport(USBHHIDDriver *hidp,
+			uint8_t report_id, usbhhid_reporttype_t report_type,
+			const void *data, uint16_t len);
+	usbh_urbstatus_t usbhhidGetIdle(USBHHIDDriver *hidp, uint8_t report_id, uint8_t *duration);
+	usbh_urbstatus_t usbhhidSetIdle(USBHHIDDriver *hidp, uint8_t report_id, uint8_t duration);
+	usbh_urbstatus_t usbhhidGetProtocol(USBHHIDDriver *hidp, uint8_t *protocol);
+	usbh_urbstatus_t usbhhidSetProtocol(USBHHIDDriver *hidp, uint8_t protocol);
+
+	static inline uint8_t usbhhidGetType(USBHHIDDriver *hidp) {
+		return hidp->type;
+	}
+
+	static inline usbhhid_state_t usbhhidGetState(USBHHIDDriver *hidp) {
+		return hidp->state;
+	}
+
+	void usbhhidStart(USBHHIDDriver *hidp, const USBHHIDConfig *cfg);
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif /* USBH_HID_H_ */
diff --git a/os/hal/include/usbh/dev/hub.h b/os/hal/include/usbh/dev/hub.h
index 07e88e6..406fbaf 100644
--- a/os/hal/include/usbh/dev/hub.h
+++ b/os/hal/include/usbh/dev/hub.h
@@ -1,6 +1,6 @@
 /*

-    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio

-              Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail)

+    ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio

+              Copyright (C) 2015..2017 Diego Ismirlian, (dismirlian (at) google's mail)

 

     Licensed under the Apache License, Version 2.0 (the "License");

     you may not use this file except in compliance with the License.

@@ -23,7 +23,7 @@
 #if HAL_USE_USBH

 #if HAL_USBH_USE_HUB

 

-typedef struct USBHHubDriver {

+struct USBHHubDriver {

 	/* inherited from abstract class driver */

 	_usbh_base_classdriver_data

 

@@ -32,19 +32,19 @@ typedef struct USBHHubDriver {
 	usbh_ep_t epint;

 	usbh_urb_t urb;

 

-	USBH_DEFINE_BUFFER(uint8_t, scbuff[4]);

+	USBH_DECLARE_STRUCT_MEMBER(uint8_t scbuff[4]);

 	volatile uint32_t statuschange;

 	uint16_t status;

 	uint16_t c_status;

 

 	usbh_port_t *ports;

 

-	USBH_DEFINE_BUFFER(usbh_hub_descriptor_t, hubDesc);

+	USBH_DECLARE_STRUCT_MEMBER(usbh_hub_descriptor_t hubDesc);

 

 	/* Low level part */

 	_usbh_hub_ll_data

 

-} USBHHubDriver;

+};

 

 extern USBHHubDriver USBHHUBD[HAL_USBHHUB_MAX_INSTANCES];

 

@@ -60,7 +60,7 @@ usbh_urbstatus_t usbhhubControlRequest(USBHDriver *host, USBHHubDriver *hub,
 

 static inline usbh_urbstatus_t usbhhubClearFeaturePort(usbh_port_t *port, uint8_t feature) {

 	return usbhhubControlRequest(port->device.host, port->hub,

-				USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_OTHER,

+				USBH_REQTYPE_DIR_OUT | USBH_REQTYPE_TYPE_CLASS | USBH_REQTYPE_RECIP_OTHER,

 				USBH_REQ_CLEAR_FEATURE,

 				feature,

 				port->number,

@@ -70,7 +70,7 @@ static inline usbh_urbstatus_t usbhhubClearFeaturePort(usbh_port_t *port, uint8_
 

 static inline usbh_urbstatus_t usbhhubClearFeatureHub(USBHDriver *host, USBHHubDriver *hub, uint8_t feature) {

 	return usbhhubControlRequest(host, hub,

-				USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_DEVICE,

+				USBH_REQTYPE_DIR_OUT | USBH_REQTYPE_TYPE_CLASS | USBH_REQTYPE_RECIP_DEVICE,

 				USBH_REQ_CLEAR_FEATURE,

 				feature,

 				0,

@@ -80,7 +80,7 @@ static inline usbh_urbstatus_t usbhhubClearFeatureHub(USBHDriver *host, USBHHubD
 

 static inline usbh_urbstatus_t usbhhubSetFeaturePort(usbh_port_t *port, uint8_t feature) {

 	return usbhhubControlRequest(port->device.host, port->hub,

-				USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_OTHER,

+				USBH_REQTYPE_DIR_OUT | USBH_REQTYPE_TYPE_CLASS | USBH_REQTYPE_RECIP_OTHER,

 				USBH_REQ_SET_FEATURE,

 				feature,

 				port->number,

@@ -88,7 +88,6 @@ static inline usbh_urbstatus_t usbhhubSetFeaturePort(usbh_port_t *port, uint8_t
 				0);

 }

 

-void usbhhubObjectInit(USBHHubDriver *hubdp);

 #else

 

 static inline usbh_urbstatus_t usbhhubControlRequest(USBHDriver *host,

@@ -103,7 +102,7 @@ static inline usbh_urbstatus_t usbhhubControlRequest(USBHDriver *host,
 

 static inline usbh_urbstatus_t usbhhubClearFeaturePort(usbh_port_t *port, uint8_t feature) {

 	return usbhhubControlRequest(port->device.host,

-				USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_OTHER,

+				USBH_REQTYPE_DIR_OUT | USBH_REQTYPE_TYPE_CLASS | USBH_REQTYPE_RECIP_OTHER,

 				USBH_REQ_CLEAR_FEATURE,

 				feature,

 				port->number,

@@ -113,7 +112,7 @@ static inline usbh_urbstatus_t usbhhubClearFeaturePort(usbh_port_t *port, uint8_
 

 static inline usbh_urbstatus_t usbhhubClearFeatureHub(USBHDriver *host, uint8_t feature) {

 	return usbhhubControlRequest(host,

-				USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_DEVICE,

+				USBH_REQTYPE_DIR_OUT | USBH_REQTYPE_TYPE_CLASS | USBH_REQTYPE_RECIP_DEVICE,

 				USBH_REQ_CLEAR_FEATURE,

 				feature,

 				0,

@@ -123,7 +122,7 @@ static inline usbh_urbstatus_t usbhhubClearFeatureHub(USBHDriver *host, uint8_t
 

 static inline usbh_urbstatus_t usbhhubSetFeaturePort(usbh_port_t *port, uint8_t feature) {

 	return usbhhubControlRequest(port->device.host,

-				USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_OTHER,

+				USBH_REQTYPE_DIR_OUT | USBH_REQTYPE_TYPE_CLASS | USBH_REQTYPE_RECIP_OTHER,

 				USBH_REQ_SET_FEATURE,

 				feature,

 				port->number,

diff --git a/os/hal/include/usbh/dev/msd.h b/os/hal/include/usbh/dev/msd.h
index d164618..eedd474 100644
--- a/os/hal/include/usbh/dev/msd.h
+++ b/os/hal/include/usbh/dev/msd.h
@@ -1,6 +1,6 @@
 /*

-    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio

-              Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail)

+    ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio

+              Copyright (C) 2015..2017 Diego Ismirlian, (dismirlian (at) google's mail)

 

     Licensed under the Apache License, Version 2.0 (the "License");

     you may not use this file except in compliance with the License.

@@ -25,7 +25,6 @@
 /* TODO:

  *

  * - Implement of conditional compilation of multiple-luns per instance.

- * - Implement error checking and recovery when commands fail.

  *

  */

 

@@ -59,30 +58,15 @@ struct USBHMassStorageLUNDriver {
 	const struct USBHMassStorageDriverVMT *vmt;

 	_base_block_device_data

 

+	/* for serializing access to the LUN driver */

+	semaphore_t sem;

+

 	BlockDeviceInfo info;

 	USBHMassStorageDriver *msdp;

 

 	USBHMassStorageLUNDriver *next;

 };

 

-typedef struct USBHMassStorageDriver {

-	/* inherited from abstract class driver */

-	_usbh_base_classdriver_data

-

-	/* for LUN request serialization, can be removed

-	 * if the driver is configured to support only one LUN

-	 * per USBHMassStorageDriver instance */

-	mutex_t mtx;

-

-	usbh_ep_t epin;

-	usbh_ep_t epout;

-	uint8_t ifnum;

-	uint8_t max_lun;

-	uint32_t tag;

-

-	USBHMassStorageLUNDriver *luns;

-} USBHMassStorageDriver;

-

 

 /*===========================================================================*/

 /* Driver macros.                                                            */

@@ -94,18 +78,13 @@ typedef struct USBHMassStorageDriver {
 /*===========================================================================*/

 

 extern USBHMassStorageLUNDriver MSBLKD[HAL_USBHMSD_MAX_LUNS];

-extern USBHMassStorageDriver USBHMSD[HAL_USBHMSD_MAX_INSTANCES];

 

 #ifdef __cplusplus

 extern "C" {

 #endif

-	/* Mass Storage Driver */

-	void usbhmsdObjectInit(USBHMassStorageDriver *msdp);

-

 	/* Mass Storage LUN Driver (block driver) */

-	void usbhmsdLUNObjectInit(USBHMassStorageLUNDriver *lunp);

-	void usbhmsdLUNStart(USBHMassStorageLUNDriver *lunp);

-	void usbhmsdLUNStop(USBHMassStorageLUNDriver *lunp);

+//	void usbhmsdLUNStart(USBHMassStorageLUNDriver *lunp);

+//	void usbhmsdLUNStop(USBHMassStorageLUNDriver *lunp);

 	bool usbhmsdLUNConnect(USBHMassStorageLUNDriver *lunp);

 	bool usbhmsdLUNDisconnect(USBHMassStorageLUNDriver *lunp);

 	bool usbhmsdLUNRead(USBHMassStorageLUNDriver *lunp, uint32_t startblk,

diff --git a/os/hal/include/usbh/dev/uvc.h b/os/hal/include/usbh/dev/uvc.h
new file mode 100644
index 0000000..0477312
--- /dev/null
+++ b/os/hal/include/usbh/dev/uvc.h
@@ -0,0 +1,459 @@
+/*
+    ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio
+              Copyright (C) 2015..2017 Diego Ismirlian, (dismirlian (at) google's mail)
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+ */
+
+#ifndef USBH_INCLUDE_USBH_UVC_H_
+#define USBH_INCLUDE_USBH_UVC_H_
+
+#include "hal_usbh.h"
+
+#if HAL_USE_USBH && HAL_USBH_USE_UVC
+
+#include "usbh/desciter.h"
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+#define USBHUVC_MAX_STATUS_PACKET_SZ	16
+
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+
+typedef enum {
+	UVC_CS_INTERFACE 	= 0x24,
+	UVC_CS_ENDPOINT 	= 0x25
+} usbh_uvc_cstype_t;
+
+typedef enum {
+	UVC_CC_VIDEO 		= 0x0e
+} usbh_uvc_cctype_t;
+
+typedef enum {
+	UVC_SC_UNKNOWN = 0x00,
+	UVC_SC_VIDEOCONTROL,
+	UVC_SC_VIDEOSTREAMING,
+	UVC_SC_VIDEO_INTERFACE_COLLECTION
+} usbh_uvc_sctype_t;
+
+typedef enum {
+	UVC_VC_UNDEF = 0x00,
+	UVC_VC_HEADER,
+	UVC_VC_INPUT_TERMINAL,
+	UVC_VC_OUTPUT_TERMINAL,
+	UVC_VC_SELECTOR_UNIT,
+	UVC_VC_PROCESSING_UNIT,
+	UVC_VC_EXTENSION_UNIT
+} usbh_uvc_vctype_t;
+
+typedef enum {
+	UVC_VS_UNDEF = 0x00,
+	UVC_VS_INPUT_HEADER,
+	UVC_VS_OUTPUT_HEADER,
+	UVC_VS_STILL_IMAGE_FRAME,
+	UVC_VS_FORMAT_UNCOMPRESSED,
+	UVC_VS_FRAME_UNCOMPRESSED,
+	UVC_VS_FORMAT_MJPEG,
+	UVC_VS_FRAME_MJPEG,
+	UVC_VS_RESERVED_0,
+	UVC_VS_RESERVED_1,
+	UVC_VS_FORMAT_MPEG2TS,
+	UVC_VS_RESERVED_2,
+	UVC_VS_FORMAT_DV,
+	UVC_VS_COLOR_FORMAT,
+	UVC_VS_RESERVED_3,
+	UVC_VS_RESERVED_4,
+	UVC_VS_FORMAT_FRAME_BASED,
+	UVC_VS_FRAME_FRAME_BASED,
+	UVC_VS_FORMAT_STREAM_BASED
+} usbh_uvc_vstype_t;
+
+typedef enum {
+	UVC_TT_VENDOR_SPECIFIC 			= 0x0100,
+	UVC_TT_STREAMING 				= 0x0101,
+	UVC_ITT_VENDOR_SPECIFIC 		= 0x0200,
+	UVC_ITT_CAMERA 					= 0x0201,
+	UVC_ITT_MEDIA_TRANSPORT_INPUT 	= 0x0202,
+	UVC_OTT_VENDOR_SPECIFIC 		= 0x0300,
+	UVC_OTT_DISPLAY 				= 0x0301,
+	UVC_OTT_MEDIA_TRANSPORT 		= 0x0302
+} usbh_uvc_tttype_t;
+
+typedef enum {
+	UVC_SET_CUR	 =	0x01,
+	UVC_GET_CUR	 =	0x81,
+	UVC_GET_MIN	 =	0x82,
+	UVC_GET_MAX	 =	0x83,
+	UVC_GET_RES  =	0x84,
+	UVC_GET_LEN  = 	0x85,
+	UVC_GET_INFO =	0x86,
+	UVC_GET_DEF  =	0x87
+} usbh_uvc_ctrlops_t;
+
+typedef enum {
+	UVC_CTRL_VC_CONTROL_UNDEFINED  = 0x00,
+	UVC_CTRL_VC_VIDEO_POWER_MODE_CONTROL = 0x01,
+	UVC_CTRL_VC_REQUEST_ERROR_CODE_CONTROL = 0x02,
+} usbh_uvc_ctrl_vc_interface_controls_t;
+
+typedef enum {
+	UVC_CTRL_SU_CONTROL_UNDEFINED = 0x00,
+	UVC_CTRL_SU_INPUT_SELECT_CONTROL = 0x01,
+} usbh_uvc_ctrl_vc_selectorunit_controls_t;
+
+typedef enum {
+	UVC_CTRL_CT_CONTROL_UNDEFINED = 0x00,
+	UVC_CTRL_CT_SCANNING_MODE_CONTROL = 0x01,
+	UVC_CTRL_CT_AE_MODE_CONTROL = 0x02,
+	UVC_CTRL_CT_AE_PRIORITY_CONTROL = 0x03,
+	UVC_CTRL_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL = 0x04,
+	UVC_CTRL_CT_EXPOSURE_TIME_RELATIVE_CONTROL = 0x05,
+	UVC_CTRL_CT_FOCUS_ABSOLUTE_CONTROL = 0x06,
+	UVC_CTRL_CT_FOCUS_RELATIVE_CONTROL = 0x07,
+	UVC_CTRL_CT_FOCUS_AUTO_CONTROL = 0x08,
+	UVC_CTRL_CT_IRIS_ABSOLUTE_CONTROL = 0x09,
+	UVC_CTRL_CT_IRIS_RELATIVE_CONTROL = 0x0A,
+	UVC_CTRL_CT_ZOOM_ABSOLUTE_CONTROL = 0x0B,
+	UVC_CTRL_CT_ZOOM_RELATIVE_CONTROL = 0x0C,
+	UVC_CTRL_CT_PANTILT_ABSOLUTE_CONTROL = 0x0D,
+	UVC_CTRL_CT_PANTILT_RELATIVE_CONTROL = 0x0E,
+	UVC_CTRL_CT_ROLL_ABSOLUTE_CONTROL = 0x0F,
+	UVC_CTRL_CT_ROLL_RELATIVE_CONTROL = 0x10,
+	UVC_CTRL_CT_PRIVACY_CONTROL = 0x11
+} usbh_uvc_ctrl_vc_cameraterminal_controls_t;
+
+typedef enum {
+	UVC_CTRL_PU_CONTROL_UNDEFINED = 0x00,
+	UVC_CTRL_PU_BACKLIGHT_COMPENSATION_CONTROL = 0x01,
+	UVC_CTRL_PU_BRIGHTNESS_CONTROL = 0x02,
+	UVC_CTRL_PU_CONTRAST_CONTROL = 0x03,
+	UVC_CTRL_PU_GAIN_CONTROL = 0x04,
+	UVC_CTRL_PU_POWER_LINE_FREQUENCY_CONTROL = 0x05,
+	UVC_CTRL_PU_HUE_CONTROL = 0x06,
+	UVC_CTRL_PU_SATURATION_CONTROL = 0x07,
+	UVC_CTRL_PU_SHARPNESS_CONTROL = 0x08,
+	UVC_CTRL_PU_GAMMA_CONTROL = 0x09,
+	UVC_CTRL_PU_WHITE_BALANCE_TEMPERATURE_CONTROL = 0x0A,
+	UVC_CTRL_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL = 0x0B,
+	UVC_CTRL_PU_WHITE_BALANCE_COMPONENT_CONTROL = 0x0C,
+	UVC_CTRL_PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL = 0x0D,
+	UVC_CTRL_PU_DIGITAL_MULTIPLIER_CONTROL = 0x0E,
+	UVC_CTRL_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL = 0x0F,
+	UVC_CTRL_PU_HUE_AUTO_CONTROL = 0x10,
+	UVC_CTRL_PU_ANALOG_VIDEO_STANDARD_CONTROL = 0x11,
+	UVC_CTRL_PU_ANALOG_LOCK_STATUS_CONTROL = 0x12,
+} usbh_uvc_ctrl_vc_processingunit_controls_t;
+
+typedef enum {
+	UVC_CTRL_VS_CONTROL_UNDEFINED = 0x00,
+	UVC_CTRL_VS_PROBE_CONTROL = 0x01,
+	UVC_CTRL_VS_COMMIT_CONTROL = 0x02,
+	UVC_CTRL_VS_STILL_PROBE_CONTROL = 0x03,
+	UVC_CTRL_VS_STILL_COMMIT_CONTROL = 0x04,
+	UVC_CTRL_VS_STILL_IMAGE_TRIGGER_CONTROL = 0x05,
+	UVC_CTRL_VS_STREAM_ERROR_CODE_CONTROL = 0x06,
+	UVC_CTRL_VS_GENERATE_KEY_FRAME_CONTROL = 0x07,
+	UVC_CTRL_VS_UPDATE_FRAME_SEGMENT_CONTROL = 0x08,
+	UVC_CTRL_VS_SYNCH_DELAY_CONTROL = 0x09
+} usbh_uvc_ctrl_vs_interface_controls_t;
+
+
+typedef PACKED_STRUCT {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bDescriptorSubType;
+	uint8_t bFormatIndex;
+	uint8_t bNumFrameDescriptors;
+	uint8_t bmFlags;
+	uint8_t bDefaultFrameIndex;
+	uint8_t bAspectRatioX;
+	uint8_t bAspectRatioY;
+	uint8_t bmInterfaceFlags;
+	uint8_t bCopyProtect;
+} usbh_uvc_format_mjpeg_t;
+
+typedef PACKED_STRUCT {
+	uint8_t  bLength;
+	uint8_t  bDescriptorType;
+	uint8_t  bDescriptorSubType;
+	uint8_t  bFrameIndex;
+	uint8_t  bmCapabilities;
+	uint16_t wWidth;
+	uint16_t wHeight;
+	uint32_t dwMinBitRate;
+	uint32_t dwMaxBitRate;
+	uint32_t dwMaxVideoFrameBufferSize;
+	uint32_t dwDefaultFrameInterval;
+	uint8_t bFrameIntervalType;
+	uint32_t dwFrameInterval[0];
+} usbh_uvc_frame_mjpeg_t;
+
+
+typedef PACKED_STRUCT {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bDescriptorSubType;
+	uint8_t bFrameIndex;
+	uint8_t bmCapabilities;
+	uint16_t wWidth;
+	uint16_t wHeight;
+	uint32_t dwMinBitRate;
+	uint32_t dwMaxBitRate;
+	uint32_t dwMaxVideoFrameBufferSize;
+	uint32_t dwDefaultFrameInterval;
+	uint8_t bFrameIntervalType;
+	uint32_t dwFrameInterval[0];
+} usbh_uvc_frame_uncompressed_t;
+
+typedef PACKED_STRUCT {
+	uint8_t  bLength;
+	uint8_t  bDescriptorType;
+	uint8_t  bDescriptorSubType;
+	uint8_t  bFormatIndex;
+	uint8_t  bNumFrameDescriptors;
+	uint8_t  guidFormat[16];
+	uint8_t  bBitsPerPixel;
+	uint8_t  bDefaultFrameIndex;
+	uint8_t  bAspectRatioX;
+	uint8_t  bAspectRatioY;
+	uint8_t  bmInterfaceFlags;
+	uint8_t  bCopyProtect;
+} usbh_uvc_format_uncompressed;
+
+typedef PACKED_STRUCT {
+    uint16_t bmHint;
+    uint8_t bFormatIndex;
+    uint8_t bFrameIndex;
+    uint32_t dwFrameInterval;
+    uint16_t wKeyFrameRate;
+    uint16_t wPFrameRate;
+    uint16_t wCompQuality;
+    uint16_t wCompWindowSize;
+    uint16_t wDelay;
+    uint32_t dwMaxVideoFrameSize;
+    uint32_t dwMaxPayloadTransferSize;
+//    uint32_t dwClockFrequency;
+//    uint8_t bmFramingInfo;
+//    uint8_t bPreferedVersion;
+//    uint8_t bMinVersion;
+//    uint8_t bMaxVersion;
+} usbh_uvc_ctrl_vs_probecommit_data_t;
+
+
+
+/* D0: Frame ID.
+ * 	For frame-based formats, this bit toggles between 0 and 1 every time a new video frame begins.
+ * 	For stream-based formats, this bit toggles between 0 and 1 at the start of each new codec-specific
+ * 	segment. This behavior is required for frame-based payload formats (e.g., DV) and is optional
+ * 	for stream-based payload formats (e.g., MPEG-2 TS). For stream-based formats, support for this
+ * 	bit must be indicated via the bmFramingInfofield of the Video Probe and Commitcontrols
+ * 	(see section 4.3.1.1, “Video Probe and Commit Controls”).
+ *
+ * D1: End of Frame.
+ *  This bit is set if the following payload data marks the end of the current video or still image
+ *  frame (for framebased formats), or to indicate the end of a codec-specific segment
+ *  (for stream-based formats). This behavior is optional for all payload formats.
+ *  For stream-based formats, support for this bit must be indicated via the bmFramingInfofield
+ *  of the Video Probe and CommitControls (see section 4.3.1.1, “Video Probe and Commit Controls”).
+ *
+ * D2: Presentation Time.
+ *  This bit is set if the dwPresentationTimefield is being sent as part of the header.
+ *
+ * D3: Source Clock Reference
+ *  This bit is set if the dwSourceClockfield is being sent as part of the header.
+ *
+ * D4: Reserved
+ *
+ * D5: Still Image
+ *  This bit is set ifthe following data is part of a still image frame, and is only used for
+ *  methods 2 and 3 of still image capture.
+ *
+ * D6: Error
+ *  This bit is set ifthere was an error in the video or still image transmission
+ *  for this payload. The StreamError Code control would reflect the cause of the error.
+ *
+ * D7: End of header
+ *  This bit is set if this is the last header group in the packet, where the
+ *  header group refers to this field and any optional fields identified by the bits in this
+ *  field (Defined for future extension)
+*/
+
+#define UVC_HDR_EOH				(1 << 7)	/* End of header */
+#define UVC_HDR_ERR				(1 << 6)	/* Error */
+#define UVC_HDR_STILL			(1 << 5)	/* Still Image */
+#define UVC_HDR_SCR				(1 << 3)	/* Source Clock Reference */
+#define UVC_HDR_PT				(1 << 2)	/* Presentation Time */
+#define UVC_HDR_EOF				(1 << 1)	/* End of Frame */
+#define UVC_HDR_FID				(1 << 0)	/* Frame ID */
+
+
+
+typedef struct USBHUVCDriver USBHUVCDriver;
+
+#define USBHUVC_MESSAGETYPE_STATUS	1
+#define USBHUVC_MESSAGETYPE_DATA	2
+
+
+#define _usbhuvc_message_base_data				\
+		uint16_t type;							\
+		uint16_t length;						\
+		systime_t timestamp;
+
+typedef struct {
+	_usbhuvc_message_base_data
+} usbhuvc_message_base_t;
+
+typedef struct {
+	_usbhuvc_message_base_data
+	USBH_DECLARE_STRUCT_MEMBER(uint8_t data[0]);
+} usbhuvc_message_data_t;
+
+typedef struct {
+	_usbhuvc_message_base_data
+	USBH_DECLARE_STRUCT_MEMBER(uint8_t data[USBHUVC_MAX_STATUS_PACKET_SZ]);
+} usbhuvc_message_status_t;
+
+
+typedef enum {
+	USBHUVC_STATE_UNINITIALIZED = 0,	//must call usbhuvcObjectInit
+	USBHUVC_STATE_STOP	 		= 1,	//the device is disconnected
+	USBHUVC_STATE_ACTIVE 		= 2,	//the device is connected
+	USBHUVC_STATE_READY		 	= 3,	//the device has negotiated the parameters
+	USBHUVC_STATE_STREAMING 	= 4,	//the device is streaming data
+	USBHUVC_STATE_BUSY	 		= 5		//the driver is busy performing some action
+} usbhuvc_state_t;
+
+
+struct USBHUVCDriver {
+	/* inherited from abstract class driver */
+	_usbh_base_classdriver_data
+
+	usbhuvc_state_t state;
+
+	usbh_ep_t ep_int;
+	usbh_ep_t ep_iso;
+
+	usbh_urb_t urb_iso;
+	usbh_urb_t urb_int;
+
+	if_iterator_t ivc;
+	if_iterator_t ivs;
+
+	USBH_DECLARE_STRUCT_MEMBER(usbh_uvc_ctrl_vs_probecommit_data_t pc);
+	USBH_DECLARE_STRUCT_MEMBER(usbh_uvc_ctrl_vs_probecommit_data_t pc_min);
+	USBH_DECLARE_STRUCT_MEMBER(usbh_uvc_ctrl_vs_probecommit_data_t pc_max);
+
+	mailbox_t mb;
+	msg_t mb_buff[HAL_USBHUVC_MAX_MAILBOX_SZ];
+
+	memory_pool_t mp_data;
+	void *mp_data_buffer;
+
+	memory_pool_t mp_status;
+	usbhuvc_message_status_t mp_status_buffer[HAL_USBHUVC_STATUS_PACKETS_COUNT];
+
+	mutex_t mtx;
+};
+
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+extern USBHUVCDriver USBHUVCD[HAL_USBHUVC_MAX_INSTANCES];
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+	static inline usbhuvc_state_t usbhuvcGetState(USBHUVCDriver *uvcd) {
+		return uvcd->state;
+	}
+
+	bool usbhuvcVCRequest(USBHUVCDriver *uvcdp,
+			uint8_t bRequest, uint8_t entity, uint8_t control,
+			uint16_t wLength, uint8_t *data);
+	bool usbhuvcVSRequest(USBHUVCDriver *uvcdp,
+			uint8_t bRequest, uint8_t control,
+			uint16_t wLength, uint8_t *data);
+	bool usbhuvcFindVSDescriptor(USBHUVCDriver *uvcdp,
+			generic_iterator_t *ics,
+			uint8_t bDescriptorSubtype,
+			bool start);
+	uint32_t usbhuvcEstimateRequiredEPSize(USBHUVCDriver *uvcdp, const uint8_t *formatdesc,
+			const uint8_t *framedesc, uint32_t dwFrameInterval);
+
+#if	USBH_DEBUG_ENABLE && USBHUVC_DEBUG_ENABLE_INFO
+	void usbhuvcPrintProbeCommit(const usbh_uvc_ctrl_vs_probecommit_data_t *pc);
+#else
+#	define usbhuvcPrintProbeCommit(pc) do {} while(0)
+#endif
+	bool usbhuvcProbe(USBHUVCDriver *uvcdp);
+	bool usbhuvcCommit(USBHUVCDriver *uvcdp);
+	void usbhuvcResetPC(USBHUVCDriver *uvcdp);
+	static inline const usbh_uvc_ctrl_vs_probecommit_data_t *usbhuvcGetPCMin(USBHUVCDriver *uvcdp) {
+		return &uvcdp->pc_min;
+	}
+	static inline const usbh_uvc_ctrl_vs_probecommit_data_t *usbhuvcGetPCMax(USBHUVCDriver *uvcdp) {
+		return &uvcdp->pc_min;
+	}
+	static inline usbh_uvc_ctrl_vs_probecommit_data_t *usbhuvcGetPC(USBHUVCDriver *uvcdp) {
+		return &uvcdp->pc;
+	}
+
+	bool usbhuvcStreamStart(USBHUVCDriver *uvcdp, uint16_t min_ep_sz);
+	bool usbhuvcStreamStop(USBHUVCDriver *uvcdp);
+
+	static inline msg_t usbhuvcLockAndFetchS(USBHUVCDriver *uvcdp, msg_t *msg, systime_t timeout) {
+		chMtxLockS(&uvcdp->mtx);
+		msg_t ret = chMBFetchTimeoutS(&uvcdp->mb, msg, timeout);
+		if (ret != MSG_OK)
+			chMtxUnlockS(&uvcdp->mtx);
+		return ret;
+	}
+	static inline msg_t usbhuvcLockAndFetch(USBHUVCDriver *uvcdp, msg_t *msg, systime_t timeout) {
+		osalSysLock();
+		msg_t ret = usbhuvcLockAndFetchS(uvcdp, msg, timeout);
+		osalSysUnlock();
+		return ret;
+	}
+	static inline void usbhuvcUnlock(USBHUVCDriver *uvcdp) {
+		chMtxUnlock(&uvcdp->mtx);
+	}
+	static inline void usbhuvcFreeDataMessage(USBHUVCDriver *uvcdp, usbhuvc_message_data_t *msg) {
+		chPoolFree(&uvcdp->mp_data, msg);
+	}
+	static inline void usbhuvcFreeStatusMessage(USBHUVCDriver *uvcdp, usbhuvc_message_status_t *msg) {
+		chPoolFree(&uvcdp->mp_status, msg);
+	}
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif /* USBH_INCLUDE_USBH_UVC_H_ */
diff --git a/os/hal/include/usbh/internal.h b/os/hal/include/usbh/internal.h
index baa477f..f6f17b7 100644
--- a/os/hal/include/usbh/internal.h
+++ b/os/hal/include/usbh/internal.h
@@ -1,6 +1,6 @@
 /*

-    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio

-              Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail)

+    ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio

+              Copyright (C) 2015..2017 Diego Ismirlian, (dismirlian (at) google's mail)

 

     Licensed under the Apache License, Version 2.0 (the "License");

     you may not use this file except in compliance with the License.

@@ -29,9 +29,15 @@
 #if HAL_USBH_USE_FTDI

 extern const usbh_classdriverinfo_t usbhftdiClassDriverInfo;

 #endif

+#if HAL_USBH_USE_AOA

+extern const usbh_classdriverinfo_t usbhaoaClassDriverInfo;

+#endif

 #if HAL_USBH_USE_MSD

 extern const usbh_classdriverinfo_t usbhmsdClassDriverInfo;

 #endif

+#if HAL_USBH_USE_HID

+extern const usbh_classdriverinfo_t usbhhidClassDriverInfo;

+#endif

 #if HAL_USBH_USE_UVC

 extern const usbh_classdriverinfo_t usbhuvcClassDriverInfo;

 #endif

@@ -48,30 +54,21 @@ void _usbh_urb_completeI(usbh_urb_t *urb, usbh_urbstatus_t status);
 bool _usbh_urb_abortI(usbh_urb_t *urb, usbh_urbstatus_t status);

 void _usbh_urb_abort_and_waitS(usbh_urb_t *urb, usbh_urbstatus_t status);

 

+bool _usbh_match_vid_pid(usbh_device_t *dev, int32_t vid, int32_t pid);

+bool _usbh_match_descriptor(const uint8_t *descriptor, uint16_t rem,

+		int16_t type, int16_t _class, int16_t subclass, int16_t protocol);

 

-#define USBH_CLASSIN(type, req, value, index)	\

-	(USBH_REQTYPE_IN | type | USBH_REQTYPE_CLASS), \

-	req, \

-	value, \

-	index

+#define USBH_REQTYPE_CLASSIN(type)	\

+	(USBH_REQTYPE_DIR_IN | type | USBH_REQTYPE_TYPE_CLASS)

 

-#define USBH_CLASSOUT(type, req, value, index)	\

-	(USBH_REQTYPE_OUT | type | USBH_REQTYPE_CLASS), \

-	req, \

-	value, \

-	index

+#define USBH_REQTYPE_CLASSOUT(type)	\

+	(USBH_REQTYPE_DIR_OUT | type | USBH_REQTYPE_TYPE_CLASS)

 

-#define USBH_STANDARDIN(type, req, value, index)	\

-	(USBH_REQTYPE_IN | type | USBH_REQTYPE_STANDARD), \

-	req, \

-	value, \

-	index

+#define USBH_REQTYPE_STANDARDIN(type)	\

+	(USBH_REQTYPE_DIR_IN | type | USBH_REQTYPE_TYPE_STANDARD)

 

-#define USBH_STANDARDOUT(type, req, value, index)	\

-	(USBH_REQTYPE_OUT | type | USBH_REQTYPE_STANDARD), \

-	req, \

-	value, \

-	index

+#define USBH_REQTYPE_STANDARDOUT(type)	\

+	(USBH_REQTYPE_DIR_OUT | type | USBH_REQTYPE_TYPE_STANDARD)

 

 

 #define USBH_PID_DATA0            0

@@ -82,19 +79,19 @@ void _usbh_urb_abort_and_waitS(usbh_urb_t *urb, usbh_urbstatus_t status);
 

 

 /* GetBusState and SetHubDescriptor are optional, omitted */

-#define ClearHubFeature   (((USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_DEVICE) << 8) \

+#define ClearHubFeature   (((USBH_REQTYPE_DIR_OUT | USBH_REQTYPE_TYPE_CLASS | USBH_REQTYPE_RECIP_DEVICE) << 8) \

 							| USBH_REQ_CLEAR_FEATURE)

-#define SetHubFeature     (((USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_DEVICE) << 8) \

+#define SetHubFeature     (((USBH_REQTYPE_DIR_OUT | USBH_REQTYPE_TYPE_CLASS | USBH_REQTYPE_RECIP_DEVICE) << 8) \

 							| USBH_REQ_SET_FEATURE)

-#define ClearPortFeature   (((USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_OTHER) << 8) \

+#define ClearPortFeature   (((USBH_REQTYPE_DIR_OUT | USBH_REQTYPE_TYPE_CLASS | USBH_REQTYPE_RECIP_OTHER) << 8) \

 							| USBH_REQ_CLEAR_FEATURE)

-#define SetPortFeature     (((USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_OTHER) << 8) \

+#define SetPortFeature     (((USBH_REQTYPE_DIR_OUT | USBH_REQTYPE_TYPE_CLASS | USBH_REQTYPE_RECIP_OTHER) << 8) \

 							| USBH_REQ_SET_FEATURE)

-#define GetHubDescriptor  (((USBH_REQTYPE_IN | USBH_REQTYPE_CLASS | USBH_REQTYPE_DEVICE) << 8) \

+#define GetHubDescriptor  (((USBH_REQTYPE_DIR_IN | USBH_REQTYPE_TYPE_CLASS | USBH_REQTYPE_RECIP_DEVICE) << 8) \

 							| USBH_REQ_GET_DESCRIPTOR)

-#define GetHubStatus      (((USBH_REQTYPE_IN | USBH_REQTYPE_CLASS | USBH_REQTYPE_DEVICE) << 8) \

+#define GetHubStatus      (((USBH_REQTYPE_DIR_IN | USBH_REQTYPE_TYPE_CLASS | USBH_REQTYPE_RECIP_DEVICE) << 8) \

 							| USBH_REQ_GET_STATUS)

-#define GetPortStatus     (((USBH_REQTYPE_IN | USBH_REQTYPE_CLASS | USBH_REQTYPE_OTHER) << 8) \

+#define GetPortStatus     (((USBH_REQTYPE_DIR_IN | USBH_REQTYPE_TYPE_CLASS | USBH_REQTYPE_RECIP_OTHER) << 8) \

 							| USBH_REQ_GET_STATUS)

 

 

@@ -143,6 +140,9 @@ void _usbh_urb_abort_and_waitS(usbh_urb_t *urb, usbh_urbstatus_t status);
 

 #define sizeof_array(x) 	(sizeof(x)/sizeof(*(x)))

 

+#include "usbh/desciter.h"	/* descriptor iterators */

+#include "usbh/debug.h"

+

 #endif

 

 #endif /* USBH_INTERNAL_H_ */

diff --git a/os/hal/include/usbh/list.h b/os/hal/include/usbh/list.h
index 4eceacd..cdcca04 100644
--- a/os/hal/include/usbh/list.h
+++ b/os/hal/include/usbh/list.h
@@ -7,11 +7,8 @@
 #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)

 #endif

 

-#define container_of(ptr, type, member) ((type *)(void *)((char *)(ptr) - offsetof(type, member)))

 #ifndef container_of

-#define container_of(ptr, type, member) ({                  \

-	const typeof(((type *)0)->member) * __mptr = (ptr);     \

-	(type *)((char *)__mptr - offsetof(type, member)); })

+#define container_of(ptr, type, member) ((type *)(void *)((char *)(ptr) - offsetof(type, member)))

 #endif

 

 /*

@@ -44,21 +41,15 @@ static inline void INIT_LIST_HEAD(struct list_head *list)
  * This is only for internal list manipulation where we know

  * the prev/next entries already!

  */

-#ifndef CONFIG_DEBUG_LIST

-static inline void __list_add(struct list_head *new,

+static inline void __list_add(struct list_head *_new,

                               struct list_head *prev,

                               struct list_head *next)

 {

-        next->prev = new;

-        new->next = next;

-        new->prev = prev;

-        prev->next = new;

+        next->prev = _new;

+        _new->next = next;

+        _new->prev = prev;

+        prev->next = _new;

 }

-#else

-extern void __list_add(struct list_head *new,

-                              struct list_head *prev,

-                              struct list_head *next);

-#endif

 

 /**

  * list_add - add a new entry

@@ -68,9 +59,9 @@ extern void __list_add(struct list_head *new,
  * Insert a new entry after the specified head.

  * This is good for implementing stacks.

  */

-static inline void list_add(struct list_head *new, struct list_head *head)

+static inline void list_add(struct list_head *_new, struct list_head *head)

 {

-        __list_add(new, head, head->next);

+        __list_add(_new, head, head->next);

 }

 

 

@@ -82,9 +73,9 @@ static inline void list_add(struct list_head *new, struct list_head *head)
  * Insert a new entry before the specified head.

  * This is useful for implementing queues.

  */

-static inline void list_add_tail(struct list_head *new, struct list_head *head)

+static inline void list_add_tail(struct list_head *_new, struct list_head *head)

 {

-        __list_add(new, head->prev, head);

+        __list_add(_new, head->prev, head);

 }

 

 /*

@@ -106,7 +97,7 @@ static inline void __list_del(struct list_head * prev, struct list_head * next)
  * Note: list_empty() on entry does not return true after this, the entry is

  * in an undefined state.

  */

-#ifndef CONFIG_DEBUG_LIST

+

 static inline void __list_del_entry(struct list_head *entry)

 {

         __list_del(entry->prev, entry->next);

@@ -115,35 +106,6 @@ static inline void __list_del_entry(struct list_head *entry)
 static inline void list_del(struct list_head *entry)

 {

         __list_del(entry->prev, entry->next);

-       // entry->next = LIST_POISON1;

-       // entry->prev = LIST_POISON2;

-}

-#else

-extern void __list_del_entry(struct list_head *entry);

-extern void list_del(struct list_head *entry);

-#endif

-

-/**

- * list_replace - replace old entry by new one

- * @old : the element to be replaced

- * @new : the new element to insert

- *

- * If @old was empty, it will be overwritten.

- */

-static inline void list_replace(struct list_head *old,

-                                struct list_head *new)

-{

-        new->next = old->next;

-        new->next->prev = new;

-        new->prev = old->prev;

-        new->prev->next = new;

-}

-

-static inline void list_replace_init(struct list_head *old,

-                                        struct list_head *new)

-{

-        list_replace(old, new);

-        INIT_LIST_HEAD(old);

 }

 

 /**

@@ -157,26 +119,159 @@ static inline void list_del_init(struct list_head *entry)
 }

 

 /**

- * list_move - delete from one list and add as another's head

+ * list_move_tail - delete from one list and add as another's tail

  * @list: the entry to move

- * @head: the head that will precede our entry

+ * @head: the head that will follow our entry

  */

-static inline void list_move(struct list_head *list, struct list_head *head)

+static inline void list_move_tail(struct list_head *list,

+                                  struct list_head *head)

 {

         __list_del_entry(list);

-        list_add(list, head);

+        list_add_tail(list, head);

 }

 

+

 /**

- * list_move_tail - delete from one list and add as another's tail

+ * list_empty - tests whether a list is empty

+ * @head: the list to test.

+ */

+static inline int list_empty(const struct list_head *head)

+{

+        return head->next == head;

+}

+

+/**

+ * list_entry - get the struct for this entry

+ * @ptr:        the &struct list_head pointer.

+ * @type:       the type of the struct this is embedded in.

+ * @member:     the name of the list_head within the struct.

+ */

+#define list_entry(ptr, type, member) \

+        container_of(ptr, type, member)

+

+/**

+ * list_first_entry - get the first element from a list

+ * @ptr:        the list head to take the element from.

+ * @type:       the type of the struct this is embedded in.

+ * @member:     the name of the list_head within the struct.

+ *

+ * Note, that list is expected to be not empty.

+ */

+#define list_first_entry(ptr, type, member) \

+        list_entry((ptr)->next, type, member)

+

+/**

+ * list_next_entry - get the next element in list

+ * @pos:        the type * to cursor

+ * @member:     the name of the list_head within the struct.

+ */

+#define list_next_entry(pos, type, member) \

+        list_entry((pos)->member.next, type, member)

+

+/**

+ * list_for_each_entry  -       iterate over list of given type

+ * @pos:        the type * to use as a loop cursor.

+ * @head:       the head for your list.

+ * @member:     the name of the list_head within the struct.

+ */

+#define list_for_each_entry(pos, type, head, member)                          \

+        for (pos = list_first_entry(head, type, member);        \

+             &pos->member != (head);                                    \

+             pos = list_next_entry(pos, type, member))

+

+

+/**

+ * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry

+ * @pos:        the type * to use as a loop cursor.

+ * @n:          another type * to use as temporary storage

+ * @head:       the head for your list.

+ * @member:     the name of the list_head within the struct.

+ */

+#define list_for_each_entry_safe(pos, type, n, head, member)                  \

+        for (pos = list_first_entry(head, type, member),        \

+                n = list_next_entry(pos, type, member);                       \

+             &pos->member != (head);                                    \

+             pos = n, n = list_next_entry(n, type, member))

+

+#if 0

+

+/**

+ * list_for_each        -       iterate over a list

+ * @pos:        the &struct list_head to use as a loop cursor.

+ * @head:       the head for your list.

+ */

+#define list_for_each(pos, head) \

+        for (pos = (head)->next; pos != (head); pos = pos->next)

+

+/**

+ * list_for_each_safe - iterate over a list safe against removal of list entry

+ * @pos:        the &struct list_head to use as a loop cursor.

+ * @n:          another &struct list_head to use as temporary storage

+ * @head:       the head for your list.

+ */

+#define list_for_each_safe(pos, n, head) \

+        for (pos = (head)->next, n = pos->next; pos != (head); \

+                pos = n, n = pos->next)

+

+/**

+ * list_prev_entry - get the prev element in list

+ * @pos:        the type * to cursor

+ * @member:     the name of the list_head within the struct.

+ */

+#define list_prev_entry(pos, type, member) \

+        list_entry((pos)->member.prev, type, member)

+

+/**

+ * list_for_each_prev   -       iterate over a list backwards

+ * @pos:        the &struct list_head to use as a loop cursor.

+ * @head:       the head for your list.

+ */

+#define list_for_each_prev(pos, head) \

+        for (pos = (head)->prev; pos != (head); pos = pos->prev)

+

+/**

+ * list_for_each_prev_safe - iterate over a list backwards safe against removal of list entry

+ * @pos:        the &struct list_head to use as a loop cursor.

+ * @n:          another &struct list_head to use as temporary storage

+ * @head:       the head for your list.

+ */

+#define list_for_each_prev_safe(pos, n, head) \

+        for (pos = (head)->prev, n = pos->prev; \

+             pos != (head); \

+             pos = n, n = pos->prev)

+

+/**

+ * list_last_entry - get the last element from a list

+ * @ptr:        the list head to take the element from.

+ * @type:       the type of the struct this is embedded in.

+ * @member:     the name of the list_head within the struct.

+ *

+ * Note, that list is expected to be not empty.

+ */

+#define list_last_entry(ptr, type, member) \

+        list_entry((ptr)->prev, type, member)

+

+/**

+ * list_first_entry_or_null - get the first element from a list

+ * @ptr:        the list head to take the element from.

+ * @type:       the type of the struct this is embedded in.

+ * @member:     the name of the list_head within the struct.

+ *

+ * Note that if the list is empty, it returns NULL.

+ */

+#define list_first_entry_or_null(ptr, type, member) \

+        (!list_empty(ptr) ? list_first_entry(ptr, type, member) : NULL)

+

+

+/**

+ * list_move - delete from one list and add as another's head

  * @list: the entry to move

- * @head: the head that will follow our entry

+ * @head: the head that will precede our entry

  */

-static inline void list_move_tail(struct list_head *list,

-                                  struct list_head *head)

+static inline void list_move(struct list_head *list, struct list_head *head)

 {

         __list_del_entry(list);

-        list_add_tail(list, head);

+        list_add(list, head);

 }

 

 /**

@@ -191,15 +286,6 @@ static inline int list_is_last(const struct list_head *list,
 }

 

 /**

- * list_empty - tests whether a list is empty

- * @head: the list to test.

- */

-static inline int list_empty(const struct list_head *head)

-{

-        return head->next == head;

-}

-

-/**

  * list_empty_careful - tests whether a list is empty and not being modified

  * @head: the list to test

  *

@@ -353,110 +439,28 @@ static inline void list_splice_tail_init(struct list_head *list,
 }

 

 /**

- * list_entry - get the struct for this entry

- * @ptr:        the &struct list_head pointer.

- * @type:       the type of the struct this is embedded in.

- * @member:     the name of the list_head within the struct.

- */

-#define list_entry(ptr, type, member) \

-        container_of(ptr, type, member)

-

-/**

- * list_first_entry - get the first element from a list

- * @ptr:        the list head to take the element from.

- * @type:       the type of the struct this is embedded in.

- * @member:     the name of the list_head within the struct.

- *

- * Note, that list is expected to be not empty.

- */

-#define list_first_entry(ptr, type, member) \

-        list_entry((ptr)->next, type, member)

-

-/**

- * list_last_entry - get the last element from a list

- * @ptr:        the list head to take the element from.

- * @type:       the type of the struct this is embedded in.

- * @member:     the name of the list_head within the struct.

- *

- * Note, that list is expected to be not empty.

- */

-#define list_last_entry(ptr, type, member) \

-        list_entry((ptr)->prev, type, member)

-

-/**

- * list_first_entry_or_null - get the first element from a list

- * @ptr:        the list head to take the element from.

- * @type:       the type of the struct this is embedded in.

- * @member:     the name of the list_head within the struct.

+ * list_replace - replace old entry by new one

+ * @old : the element to be replaced

+ * @new : the new element to insert

  *

- * Note that if the list is empty, it returns NULL.

- */

-#define list_first_entry_or_null(ptr, type, member) \

-        (!list_empty(ptr) ? list_first_entry(ptr, type, member) : NULL)

-

-/**

- * list_next_entry - get the next element in list

- * @pos:        the type * to cursor

- * @member:     the name of the list_head within the struct.

- */

-#define list_next_entry(pos, type, member) \

-        list_entry((pos)->member.next, type, member)

-

-/**

- * list_prev_entry - get the prev element in list

- * @pos:        the type * to cursor

- * @member:     the name of the list_head within the struct.

- */

-#define list_prev_entry(pos, type, member) \

-        list_entry((pos)->member.prev, type, member)

-

-/**

- * list_for_each        -       iterate over a list

- * @pos:        the &struct list_head to use as a loop cursor.

- * @head:       the head for your list.

- */

-#define list_for_each(pos, head) \

-        for (pos = (head)->next; pos != (head); pos = pos->next)

-

-/**

- * list_for_each_prev   -       iterate over a list backwards

- * @pos:        the &struct list_head to use as a loop cursor.

- * @head:       the head for your list.

- */

-#define list_for_each_prev(pos, head) \

-        for (pos = (head)->prev; pos != (head); pos = pos->prev)

-

-/**

- * list_for_each_safe - iterate over a list safe against removal of list entry

- * @pos:        the &struct list_head to use as a loop cursor.

- * @n:          another &struct list_head to use as temporary storage

- * @head:       the head for your list.

+ * If @old was empty, it will be overwritten.

  */

-#define list_for_each_safe(pos, n, head) \

-        for (pos = (head)->next, n = pos->next; pos != (head); \

-                pos = n, n = pos->next)

+static inline void list_replace(struct list_head *old,

+                                struct list_head *_new)

+{

+        _new->next = old->next;

+        _new->next->prev = _new;

+        _new->prev = old->prev;

+        _new->prev->next = _new;

+}

 

-/**

- * list_for_each_prev_safe - iterate over a list backwards safe against removal of list entry

- * @pos:        the &struct list_head to use as a loop cursor.

- * @n:          another &struct list_head to use as temporary storage

- * @head:       the head for your list.

- */

-#define list_for_each_prev_safe(pos, n, head) \

-        for (pos = (head)->prev, n = pos->prev; \

-             pos != (head); \

-             pos = n, n = pos->prev)

+static inline void list_replace_init(struct list_head *old,

+                                        struct list_head *_new)

+{

+        list_replace(old, _new);

+        INIT_LIST_HEAD(old);

+}

 

-/**

- * list_for_each_entry  -       iterate over list of given type

- * @pos:        the type * to use as a loop cursor.

- * @head:       the head for your list.

- * @member:     the name of the list_head within the struct.

- */

-#define list_for_each_entry(pos, type, head, member)                          \

-        for (pos = list_first_entry(head, type, member);        \

-             &pos->member != (head);                                    \

-             pos = list_next_entry(pos, type, member))

 

 /**

  * list_for_each_entry_reverse - iterate backwards over list of given type.

@@ -521,19 +525,6 @@ static inline void list_splice_tail_init(struct list_head *list,
              pos = list_next_entry(pos, type, member))

 

 /**

- * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry

- * @pos:        the type * to use as a loop cursor.

- * @n:          another type * to use as temporary storage

- * @head:       the head for your list.

- * @member:     the name of the list_head within the struct.

- */

-#define list_for_each_entry_safe(pos, type, n, head, member)                  \

-        for (pos = list_first_entry(head, type, member),        \

-                n = list_next_entry(pos, type, member);                       \

-             &pos->member != (head);                                    \

-             pos = n, n = list_next_entry(n, type, member))

-

-/**

  * list_for_each_entry_safe_continue - continue list iteration safe against removal

  * @pos:        the type * to use as a loop cursor.

  * @n:          another type * to use as temporary storage

@@ -594,5 +585,6 @@ static inline void list_splice_tail_init(struct list_head *list,
  */

 #define list_safe_reset_next(pos, type, n, member)                            \

         n = list_next_entry(pos, type, member)

+#endif

 

 #endif /* USBH_LIST_H_ */

diff --git a/os/hal/ports/KINETIS/K20x/hal_lld.c b/os/hal/ports/KINETIS/K20x/hal_lld.c
index e6eeed8..594f7af 100644
--- a/os/hal/ports/KINETIS/K20x/hal_lld.c
+++ b/os/hal/ports/KINETIS/K20x/hal_lld.c
@@ -148,11 +148,10 @@ void k20x_clock_init(void) {
    *       frequency, which would required other registers to be modified.

    */

   /* Enable OSC, low power mode */

-  MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0;

   if (KINETIS_XTAL_FREQUENCY > 8000000UL)

-    MCG->C2 |= MCG_C2_RANGE0(2);

+    MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0 | MCG_C2_RANGE0(2);

   else

-    MCG->C2 |= MCG_C2_RANGE0(1);

+    MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0 | MCG_C2_RANGE0(1);

 

   frdiv = 7;

   ratio = KINETIS_XTAL_FREQUENCY / 31250UL;

diff --git a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c b/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c
index c6b3d11..a005c32 100644
--- a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c
+++ b/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c
@@ -442,7 +442,7 @@ static inline msg_t _i2c_txrx_timeout(I2CDriver *i2cp, i2caddr_t addr,
     /* wait until the bus is released */

     /* Calculating the time window for the timeout on the busy bus condition.*/

     start = osalOsGetSystemTimeX();

-    end = start + OSAL_MS2ST(KINETIS_I2C_BUSY_TIMEOUT);

+    end = start + OSAL_TIME_MS2I(KINETIS_I2C_BUSY_TIMEOUT);

 

     while(true) {

       osalSysLock();

diff --git a/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c b/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c
new file mode 100644
index 0000000..1b19a90
--- /dev/null
+++ b/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c
@@ -0,0 +1,977 @@
+/*

+    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio

+              Copyright (C) 2017..2018 Wim Lewis

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    hal_sdc_lld.c

+ * @brief   Kinetis SDC subsystem low level driver.

+ *

+ * This driver provides a single SDC driver based on the Kinetis

+ * "Secured Digital Host Controller (SDHC)" peripheral.

+ *

+ * In order to use this driver, other peripherals must also be configured:

+ *

+ * The MPU must either be disabled (CESR=0), or it must be configured

+ * to allow the SDHC peripheral DMA access to any data buffers (read

+ * or write).

+ *

+ * The SDHC signals must be routed to the desired pins, and pullups/pulldowns

+ * configured.
+ *

+ * @addtogroup SDC

+ * @{

+ */

+

+#include "hal.h"

+

+#if (HAL_USE_SDC == TRUE) || defined(__DOXYGEN__)

+

+#include "hal_mmcsd.h"

+

+/*===========================================================================*/

+/* Driver local definitions.                                                 */

+/*===========================================================================*/

+

+/* We configure the SDHC block to use the system clock */

+#define KINETIS_SDHC_PERIPHERAL_FREQUENCY KINETIS_SYSCLK_FREQUENCY

+

+#ifndef KINETIS_SDHC_PRIORITY

+#define KINETIS_SDHC_PRIORITY 12 /* TODO? Default IRQ priority for SDHC */

+#endif

+

+/* The DTOC value (data timeout counter) controls how long the SDHC

+   will wait for a data transfer before indicating a timeout to

+   us. The card can tell us how long that should be, but various SDHC

+   documentation suggests that we should always allow around 500 msec

+   even if the card says it will finish sooner. This only comes into

+   play if there's a malfunction or something, so it's not critical to

+   get it exactly right.

+

+   It controls the ratio between the SDCLK frequency and the

+   timeout, so we have a different DTOCV for each bus clock

+   frequency.

+*/

+#define DTOCV_300ms_400kHz    4  /* 4  -> 2^17 -> 328 msec */

+#define DTOCV_700ms_25MHz    11  /* 11 -> 2^24 -> 671 msec */

+#define DTOCV_700ms_50MHz    12  /* 12 -> 2^25 -> 671 msec */

+

+#if 0

+#define TRACE(t, val)   chDbgWriteTrace ((void *)t, (void *)(uintptr_t)(val))

+#define TRACEI(t, val)  chDbgWriteTraceI((void *)t, (void *)(uintptr_t)(val))

+#else

+#define TRACE(t, val)

+#define TRACEI(t, val)

+#endif

+

+#define DIV_RND_UP(a, b) ( ((a)+(b)-1) / (b) )

+

+/* Error bits from the SD / MMC Card Status response word. */

+/* TODO: These really belong in a HLD, not here. */

+#define MMC_ERR_OUT_OF_RANGE            (1U << 31)

+#define MMC_ERR_ADDRESS                 (1U << 30)

+#define MMC_ERR_BLOCK_LEN               (1U << 29)

+#define MMC_ERR_ERASE_SEQ               (1U << 28)

+#define MMC_ERR_ERASE_PARAM             (1U << 27)

+#define MMC_ERR_WP                      (1U << 26)

+#define MMC_ERR_CARD_IS_LOCKED          (1U << 25)

+#define MMC_ERR_LOCK_UNLOCK_FAILED      (1U << 24)

+#define MMC_ERR_COM_CRC_ERROR           (1U << 23)

+#define MMC_ERR_ILLEGAL_COMMAND         (1U << 22)

+#define MMC_ERR_CARD_ECC_FAILED         (1U << 21)

+#define MMC_ERR_CARD_CONTROLLER         (1U << 20)

+#define MMC_ERR_ERROR                   (1U << 19)

+#define MMC_ERR_CSD_OVERWRITE           (1U << 16)

+#define MMC_ERR_AKE_SEQ                 (1U << 3)

+

+/*===========================================================================*/

+/* Driver exported variables.                                                */

+/*===========================================================================*/

+

+/**

+ * @brief   SDCD1 driver identifier.

+ */

+#if (PLATFORM_SDC_USE_SDC1 == TRUE) || defined(__DOXYGEN__)

+SDCDriver SDCD1;

+#else

+#error HAL_USE_SDC is true but PLATFORM_SDC_USE_SDC1 is false

+#endif

+

+/*===========================================================================*/

+/* Driver local variables and types.                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver local functions.                                                   */

+/*===========================================================================*/

+

+static void recover_after_botched_transfer(SDCDriver *);

+static msg_t wait_interrupt(SDCDriver *, uint32_t);

+static bool sdc_lld_transfer(SDCDriver *, uint32_t, uintptr_t, uint32_t, uint32_t);

+

+/**

+ * Compute the SDCLKFS and DVS values for a given SDCLK divisor.

+ *

+ * Note that in the current code, this function is always called with

+ * a constant argument (there are only a handful of valid SDCLK

+ * frequencies), and so GCC computes the results at compile time and

+ * does not actually emit this function into the output at all unless

+ * you're compiling with optimizations turned off.

+ *

+ * However if someone compiles with a KINETIS_SDHC_PERIPHERAL_FREQUENCY

+ * that is not a compile-time constant, this function would get emitted.

+ */

+static uint32_t divisor_settings(unsigned divisor)

+{

+  /* First, handle all the special cases */

+  if (divisor <= 1) {

+    /* Pass through */

+    return SDHC_SYSCTL_SDCLKFS(0) | SDHC_SYSCTL_DVS(0);

+  }

+  if (divisor <= 16 && (divisor & 0x01)) {

+    /* Disable the prescaler, just use the divider. */

+    return SDHC_SYSCTL_SDCLKFS(0) | SDHC_SYSCTL_DVS(divisor - 1);

+  }

+  if (divisor <= 32 && !(divisor & 0x01)) {

+    /* Prescale by 2, but do the rest with the divider */

+    return SDHC_SYSCTL_SDCLKFS(0x01) | SDHC_SYSCTL_DVS((divisor >> 1) - 1);

+  }

+  if (divisor >= 0x1000) {

+    /* It's not possible to divide by more than 2^12. If we're asked to,

+       just do the best we can. */

+    return SDHC_SYSCTL_SDCLKFS(0x80) | SDHC_SYSCTL_DVS(0xF);

+  }

+

+  /* The bit position in SDCLKFS provides a power-of-two prescale

+     factor, and the four bits in DVS allow division by up to 16

+     (division by DVS+1). We want to approximate `divisor` using these

+     terms, but we want to round up --- it's OK to run the card a

+     little bit too slow, but not OK to run it a little bit too

+     fast. */

+

+  unsigned shift = (8 * sizeof(unsigned int) - 4) - __builtin_clz(divisor);

+

+  /* Shift the divisor value right so that it only occupies the four

+     lowest bits. Subtract one because that's how the DVS circuit

+     works. Add one if we shifted any 1-bits off the bottom, so that

+     we always round up. */

+  unsigned dvs = (divisor >> shift) - ((divisor & ((1 << shift)-1))? 0 : 1);

+

+  return SDHC_SYSCTL_SDCLKFS(1 << (shift-1)) | SDHC_SYSCTL_DVS(dvs);

+}

+

+/**

+ * @brief Enable the SDHC clock when stable.

+ *

+ * Waits for the clock divider in the SDHC block to stabilize, then

+ * enables the SD clock.

+ */

+static void enable_clock_when_stable(uint32_t new_sysctl)

+{

+  SDHC->SYSCTL = new_sysctl;

+  

+  /* Wait for clock divider to stabilize */

+  while(!(SDHC->PRSSTAT & SDHC_PRSSTAT_SDSTB)) {

+    osalThreadSleepMilliseconds(1);

+  }

+

+  /* Restart the clock */

+  SDHC->SYSCTL = new_sysctl | SDHC_SYSCTL_SDCLKEN;

+}

+

+/**

+ * Translate error bits from a CMD transaction to the HAL's error flag set.

+ */

+static sdcflags_t translate_cmd_error(uint32_t status) {

+  /* Translate the failure into the flags understood by the top half */

+

+  sdcflags_t errors = 0;

+

+  if (status & SDHC_IRQSTAT_CTOE || !(status & SDHC_IRQSTAT_CC)) {

+    errors |= SDC_COMMAND_TIMEOUT;

+  }

+  if (status & SDHC_IRQSTAT_CCE) {

+    errors |= SDC_CMD_CRC_ERROR;

+  }

+

+  /* If CTOE and CCE are both set, this indicates that the Kinetis

+     SDHC peripheral has detected a CMD line conflict in a

+     multi-master scenario. There's no specific code for that, so just

+     pass it through as a combined timeout+CRC failure. */

+

+  /* Translate any other framing and protocol errors into CRC errors. */

+  if (status & ~(SDHC_IRQSTAT_CCE|SDHC_IRQSTAT_CTOE|SDHC_IRQSTAT_CC)) {

+    errors |= SDC_CMD_CRC_ERROR;

+  }

+

+  return errors;

+}

+

+/**

+ * Translate error bits from a card's R1 response word into the HAL's

+ * error flag set.

+ *

+ * This function should probably be in the HLD, not here.

+ */

+static sdcflags_t translate_mmcsd_error(uint32_t cardstatus) {

+  sdcflags_t errors = 0;

+

+  cardstatus &= MMCSD_R1_ERROR_MASK;

+

+  if (cardstatus & MMC_ERR_COM_CRC_ERROR)

+    errors |= SDC_CMD_CRC_ERROR;

+

+  if (cardstatus & MMC_ERR_CARD_ECC_FAILED)

+    errors |= SDC_DATA_CRC_ERROR;

+

+  /* TODO: Extend the HLD error codes at least enough to distinguish

+     between invalid command/parameter errors (card is OK, but

+     retrying w/o change won't help) and other errors */

+  if (cardstatus & ~(MMC_ERR_COM_CRC_ERROR|MMC_ERR_CARD_ECC_FAILED))

+    errors |= SDC_UNHANDLED_ERROR;

+

+  return errors;

+}

+

+/**

+ * @brief Perform one CMD transaction on the SD bus.

+ */

+static bool send_and_wait_cmd(SDCDriver *sdcp, uint32_t cmd) {

+  /* SDCLKEN (CMD clock enabled) should be true;

+   * SDSTB (clock stable) should be true;

+   * CIHB (command inhibit / busy) should be false */

+  osalDbgAssert((SDHC->PRSSTAT & (SDHC_PRSSTAT_SDSTB|SDHC_PRSSTAT_CIHB)) == SDHC_PRSSTAT_SDSTB, "Not in expected state");

+  osalDbgAssert(SDHC->SYSCTL & SDHC_SYSCTL_SDCLKEN, "Clock disabled");

+  osalDbgCheck((cmd & SDHC_XFERTYP_DPSEL) == 0);

+  osalDbgCheck((SDHC->IRQSTAT & (SDHC_IRQSTAT_CIE | SDHC_IRQSTAT_CEBE | SDHC_IRQSTAT_CCE |

+                                 SDHC_IRQSTAT_CTOE | SDHC_IRQSTAT_CC)) == 0);

+

+  /* This initiates the CMD transaction */

+  TRACE(1, cmd);

+  SDHC->XFERTYP = cmd;

+

+  uint32_t events =

+    SDHC_IRQSTAT_CIE | SDHC_IRQSTAT_CEBE | SDHC_IRQSTAT_CCE |

+    SDHC_IRQSTAT_CTOE | /* SDHC_IRQSTAT_CRM | */ SDHC_IRQSTAT_CC;

+  wait_interrupt(sdcp, SDHC_IRQSTAT_CTOE | SDHC_IRQSTAT_CC);

+  uint32_t status = SDHC->IRQSTAT & events;

+

+  /* These bits are write-1-to-clear (w1c) */

+  SDHC->IRQSTAT = status;

+

+  /* In the normal case, the CC (command complete) bit is set but none

+     of the others are */

+  if (status == SDHC_IRQSTAT_CC)

+    return HAL_SUCCESS;

+

+  /* Translate the failure into the flags understood by the top half */

+  sdcp->errors |= translate_cmd_error(status);

+

+  TRACE(9, SDHC->PRSSTAT);

+

+  /* Issue a reset to the CMD portion of the SDHC peripheral to clear the

+     error bits and enable subsequent commands */

+  SDHC->SYSCTL |= SDHC_SYSCTL_RSTC;

+

+  return HAL_FAILED;

+}

+

+/**

+ * @brief Perform one data transaction on the SD bus.

+ */

+static bool send_and_wait_transfer(SDCDriver *sdcp, uint32_t cmd) {

+

+  osalDbgCheck(cmd & SDHC_XFERTYP_DPSEL);

+  osalDbgCheck(cmd & SDHC_XFERTYP_DMAEN);

+

+  const uint32_t cmd_end_bits =

+    SDHC_IRQSTAT_CIE | SDHC_IRQSTAT_CEBE | SDHC_IRQSTAT_CCE |

+    SDHC_IRQSTAT_CTOE | /* SDHC_IRQSTAT_CRM | */ SDHC_IRQSTAT_CC;

+

+  const uint32_t transfer_end_bits =

+    SDHC_IRQSTAT_DMAE | SDHC_IRQSTAT_AC12E | SDHC_IRQSTAT_DEBE |

+    SDHC_IRQSTAT_DCE | SDHC_IRQSTAT_DTOE | SDHC_IRQSTAT_TC;

+

+  TRACE(3, cmd);

+

+  osalSysLock();

+  osalDbgCheck(sdcp->thread == NULL);

+

+  /* Clear anything pending from an earlier transfer */

+  SDHC->IRQSTAT = cmd_end_bits | transfer_end_bits | SDHC_IRQSTAT_DINT;

+

+  /* Enable interrupts on completions or failures */

+  uint32_t old_staten = SDHC->IRQSTATEN;

+  SDHC->IRQSTATEN = (old_staten & ~(SDHC_IRQSTAT_BRR|SDHC_IRQSTAT_BWR)) | (cmd_end_bits | transfer_end_bits | SDHC_IRQSTAT_DINT);

+  SDHC->IRQSIGEN = SDHC_IRQSTAT_CTOE | SDHC_IRQSTAT_CC;

+

+  /* Start the transfer */

+  SDHC->XFERTYP = cmd;

+

+  /* Await an interrupt */

+  osalThreadSuspendS(&sdcp->thread);

+  osalSysUnlock();

+

+  /* Retrieve the flags and clear them */

+  uint32_t cmdstat = SDHC->IRQSTAT & cmd_end_bits;

+  SDHC->IRQSTAT = cmdstat;

+  TRACE(2, cmdstat);

+

+  /* If the command failed, the transfer won't happen */

+  if (cmdstat != SDHC_IRQSTAT_CC) {

+    /* The command couldn't be sent, or wasn't acknowledged */

+    sdcp->errors |= translate_cmd_error(cmdstat);

+

+    /* Clear the error status */

+    SDHC->SYSCTL |= SDHC_SYSCTL_RSTC;

+

+    if (cmdstat == (SDHC_IRQSTAT_CCE|SDHC_IRQSTAT_CTOE)) {

+      /* A CMD-line conflict is unlikely, but doesn't require further recovery */

+    } else {

+      /* For most error situations, we don't know whether the command

+	 failed to send or we got line noise while receiving. Make sure

+	 we're in a sane state by resetting the connection. */

+      recover_after_botched_transfer(sdcp);

+    }

+

+    return HAL_FAILED;

+  }

+

+  uint32_t cmdresp = SDHC->CMDRSP[0];

+  TRACE(11, cmdresp);

+  if (cmdresp & MMCSD_R1_ERROR_MASK) {

+    /* The command was sent, and the card responded with an error indication */

+    sdcp->errors |= translate_mmcsd_error(cmdresp);

+    return HAL_FAILED;

+  }

+

+  /* Check for end of data transfer phase */

+  uint32_t datastat;

+  for (;;) {

+    datastat = SDHC->IRQSTAT & (transfer_end_bits | SDHC_IRQSTAT_DINT);

+    if (datastat & transfer_end_bits)

+      break;

+    wait_interrupt(sdcp, transfer_end_bits);

+  }

+  TRACE(6, datastat);

+  SDHC->IRQSTAT = datastat;

+

+  /* Handle data transfer errors */

+  if ((datastat & ~(SDHC_IRQSTAT_DINT)) != SDHC_IRQSTAT_TC) {

+    bool should_cancel = false;

+

+    /* Data phase errors */

+    if (datastat & (SDHC_IRQSTAT_DCE|SDHC_IRQSTAT_DEBE)) {

+      sdcp->errors |= SDC_DATA_CRC_ERROR;

+      should_cancel = true;

+    }

+    if (datastat & SDHC_IRQSTAT_DTOE) {

+      sdcp->errors |= SDC_DATA_TIMEOUT;

+      should_cancel = true;

+    }

+

+    /* Internal DMA error */

+    if (datastat & SDHC_IRQSTAT_DMAE) {

+      sdcp->errors |= SDC_UNHANDLED_ERROR;

+      if (!(datastat & SDHC_IRQSTAT_TC))

+	should_cancel = true;

+    }

+

+    if (datastat & SDHC_IRQSTAT_AC12E) {

+      uint32_t cmd12error = SDHC->AC12ERR;

+

+      /* We don't know if CMD12 was successfully executed */

+      should_cancel = true;

+

+      if (cmd12error & SDHC_AC12ERR_AC12NE) {

+	sdcp->errors |= SDC_UNHANDLED_ERROR;

+      } else {

+	if (cmd12error & SDHC_AC12ERR_AC12TOE)

+	  sdcp->errors |= SDC_COMMAND_TIMEOUT;

+	if (cmd12error & (SDHC_AC12ERR_AC12CE|SDHC_AC12ERR_AC12EBE))

+	  sdcp->errors |= SDC_CMD_CRC_ERROR;

+      }

+    }

+

+    if (should_cancel) {

+      recover_after_botched_transfer(sdcp);

+    }

+

+    return HAL_FAILED;

+  }

+

+  /* For a read transfer, make sure the DMA has finished transferring

+   * to host memory. (For a write transfer, the DMA necessarily finishes

+   * before the transfer does, so we don't need to wait for it

+   * specially.) */

+  if (!(datastat & SDHC_IRQSTAT_DINT)) {

+    for(;;) {

+      datastat = SDHC->IRQSTAT & (SDHC_IRQSTAT_DINT|SDHC_IRQSTAT_DMAE);

+      if (datastat) {

+	SDHC->IRQSTAT = datastat;

+	TRACE(7, datastat);

+	break;

+      }

+      /* ...?? */

+    }

+  }

+

+  SDHC->IRQSTATEN = old_staten;

+

+  return HAL_SUCCESS;

+}

+

+/**

+ * @brief Wait for an interrupt from the SDHC peripheral.

+ *

+ * @param[in] mask    Bits to enable in IRQSIGEN.

+ *

+ * @return            MSG_OK

+ */

+static msg_t wait_interrupt(SDCDriver *sdcp, uint32_t mask) {

+  osalSysLock();

+  SDHC->IRQSIGEN = mask;

+  msg_t wakeup = osalThreadSuspendS(&sdcp->thread);

+  osalSysUnlock();

+  return wakeup;

+}

+

+static void recover_after_botched_transfer(SDCDriver *sdcp) {

+

+  /* Query the card state */

+  uint32_t cardstatus;

+  if (sdc_lld_send_cmd_short_crc(sdcp,

+                                 MMCSD_CMD_SEND_STATUS,

+                                 sdcp->rca, &cardstatus) == HAL_SUCCESS) {

+    sdcp->errors |= translate_mmcsd_error(cardstatus);

+    uint32_t state = MMCSD_R1_STS(cardstatus);

+    if (state == MMCSD_STS_DATA) {

+

+      /* Send a CMD12 to make sure the card isn't still transferring anything */

+      SDHC->CMDARG = 0;

+      send_and_wait_cmd(sdcp,

+                        SDHC_XFERTYP_CMDINX(MMCSD_CMD_STOP_TRANSMISSION) |

+                        SDHC_XFERTYP_CMDTYP_ABORT |

+                        /* TODO: Should we set CICEN and CCCEN here? */

+                        SDHC_XFERTYP_CICEN | SDHC_XFERTYP_CCCEN |

+                        SDHC_XFERTYP_RSPTYP_48b);

+    }

+  }

+

+  /* And reset the data block of the SDHC peripheral */

+  SDHC->SYSCTL |= SDHC_SYSCTL_RSTD;

+}

+

+/**

+ * @brief Perform one data transfer command

+ *

+ * Sends a command to the card and waits for the corresponding data transfer

+ * (either a read or write) to complete.

+ */

+static bool sdc_lld_transfer(SDCDriver *sdcp, uint32_t startblk,

+			     uintptr_t buf, uint32_t n,

+			     uint32_t cmdx) {

+

+  osalDbgCheck(n > 0);

+  osalDbgCheck((buf & 0x03) == 0);  /* Must be 32-bit aligned */

+

+  osalDbgAssert((SDHC->PRSSTAT & (SDHC_PRSSTAT_DLA|SDHC_PRSSTAT_CDIHB|SDHC_PRSSTAT_CIHB)) == 0,

+		"SDHC interface not ready");

+

+  /* We always operate in terms of 512-byte blocks; the upper-layer

+     driver doesn't change the block size. The SDHC spec suggests that

+     only low-capacity cards support block sizes other than 512 bytes

+     anyway (SDHC "Physical Layer Simplified Specification" ver 6.0) */

+

+  if (sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) {

+    SDHC->CMDARG = startblk;

+  } else {

+    SDHC->CMDARG = startblk * MMCSD_BLOCK_SIZE;

+  }

+

+  /* Store the DMA start address */

+  SDHC->DSADDR = buf;

+

+  uint32_t xfer;

+  /* For data transfers, we need to set some extra bits in XFERTYP according to the

+     transfer we're starting:

+     DPSEL -> enable data transfer

+     DTDSEL -> 1 for a read (card-to-host) transfer

+     MSBSEL, BCEN -> multiple block transfer using BLKATTR_BLKCNT

+     AC12EN -> Automatically issue MMCSD_CMD_STOP_TRANSMISSION at end of transfer

+

+     Setting BLKCOUNT to 1 seems to be necessary even if MSBSEL+BCEN

+     is not set, despite the datasheet suggesting otherwise. I'm not

+     sure if this is a silicon bug or if I'm misunderstanding the

+     datasheet.

+  */

+  SDHC->BLKATTR =

+    SDHC_BLKATTR_BLKCNT(n) |

+    SDHC_BLKATTR_BLKSIZE(MMCSD_BLOCK_SIZE);

+  if (n == 1) {

+    xfer =

+      cmdx |

+      SDHC_XFERTYP_CMDTYP_NORMAL |

+      SDHC_XFERTYP_CICEN | SDHC_XFERTYP_CCCEN |

+      SDHC_XFERTYP_RSPTYP_48b |

+      SDHC_XFERTYP_DPSEL | SDHC_XFERTYP_DMAEN;

+  } else {

+    xfer =

+      cmdx |

+      SDHC_XFERTYP_CMDTYP_NORMAL |

+      SDHC_XFERTYP_CICEN | SDHC_XFERTYP_CCCEN |

+      SDHC_XFERTYP_RSPTYP_48b |

+      SDHC_XFERTYP_MSBSEL | SDHC_XFERTYP_BCEN | SDHC_XFERTYP_AC12EN |

+      SDHC_XFERTYP_DPSEL | SDHC_XFERTYP_DMAEN;

+  }

+

+  return send_and_wait_transfer(sdcp, xfer);

+}

+

+/*===========================================================================*/

+/* Driver interrupt handlers.                                                */

+/*===========================================================================*/

+

+#if (PLATFORM_SDC_USE_SDC1 == TRUE) || defined(__DOXYGEN__)

+OSAL_IRQ_HANDLER(KINETIS_SDHC_IRQ_VECTOR) {

+  OSAL_IRQ_PROLOGUE();

+  osalSysLockFromISR();

+

+  TRACEI(4, SDHC->IRQSTAT);

+

+  /* We disable the interrupts, and wake up the usermode task to read

+   * the flags from IRQSTAT.

+   */

+  SDHC->IRQSIGEN = 0;

+

+  osalThreadResumeI(&SDCD1.thread, MSG_OK);

+

+  osalSysUnlockFromISR();

+  OSAL_IRQ_EPILOGUE();

+}

+#endif

+

+/*===========================================================================*/

+/* Driver exported functions.                                                */

+/*===========================================================================*/

+

+/**

+ * @brief   Low level SDC driver initialization.

+ *

+ * @notapi

+ */

+void sdc_lld_init(void) {

+#if PLATFORM_SDC_USE_SDC1 == TRUE

+  sdcObjectInit(&SDCD1);

+#endif

+}

+

+

+/**

+ * @brief   Configures and activates the SDC peripheral.

+ *

+ * @param[in] sdcp      pointer to the @p SDCDriver object

+ *

+ * @notapi

+ */

+void sdc_lld_start(SDCDriver *sdcp) {

+

+  if (sdcp->state == BLK_STOP) {

+    SIM->SOPT2 =

+      (SIM->SOPT2 & ~SIM_SOPT2_SDHCSRC_MASK) |

+      SIM_SOPT2_SDHCSRC(0);  /* SDHC clock source 0: Core/system clock. */

+    SIM->SCGC3 |= SIM_SCGC3_SDHC; /* Enable clock to SDHC peripheral */

+

+    /* Reset the SDHC block */

+    SDHC->SYSCTL |= SDHC_SYSCTL_RSTA;

+    while(SDHC->SYSCTL & SDHC_SYSCTL_RSTA) {

+      osalThreadSleepMilliseconds(1);

+    }

+

+    SDHC->IRQSIGEN = 0;

+    nvicEnableVector(SDHC_IRQn, KINETIS_SDHC_PRIORITY);

+  }

+}

+

+/**

+ * @brief   Deactivates the SDC peripheral.

+ *

+ * @param[in] sdcp      pointer to the @p SDCDriver object

+ *

+ * @notapi

+ */

+void sdc_lld_stop(SDCDriver *sdcp) {

+

+  if (sdcp->state != BLK_STOP) {

+    /* TODO: Should we perform a reset (RSTA) before putting the

+       peripheral to sleep? */

+

+    /* Disable the card clock */

+    SDHC->SYSCTL &= ~( SDHC_SYSCTL_SDCLKEN );

+

+    /* Turn off interrupts */

+    nvicDisableVector(SDHC_IRQn);

+    SDHC->IRQSIGEN = 0;

+    SDHC->IRQSTATEN &= ~( SDHC_IRQSTATEN_CINTSEN |

+			  SDHC_IRQSTATEN_CINSEN |

+			  SDHC_IRQSTATEN_CRMSEN );

+

+    /* Disable the clock to the SDHC peripheral block */

+    SIM->SCGC3 &= ~( SIM_SCGC3_SDHC );

+  }

+}

+

+/**

+ * @brief   Starts the SDIO clock and sets it to init mode (400kHz or less).

+ *

+ * @param[in] sdcp      pointer to the @p SDCDriver object

+ *

+ * @notapi

+ */

+void sdc_lld_start_clk(SDCDriver *sdcp) {

+

+  (void)sdcp;

+

+  /* Stop the card clock (it should already be stopped) */

+  SDHC->SYSCTL &= ~( SDHC_SYSCTL_SDCLKEN );

+

+  /* Change the divisor and DTOCV for a 400kHz card closk */

+  uint32_t sysctl =

+    SDHC_SYSCTL_DTOCV(DTOCV_300ms_400kHz) |

+    divisor_settings(DIV_RND_UP(KINETIS_SDHC_PERIPHERAL_FREQUENCY, 400000));

+

+  /* Restart the clock */

+  enable_clock_when_stable(sysctl);

+

+  /* Reset any protocol machinery; this also runs the clock for 80

+     cycles without any data bits to help initalize the card's state

+     (the Kinetis peripheral docs say that this is required after card

+     insertion or power-on, but the abridged SDHC specifications I

+     have don't seem to mention it) */

+  SDHC->SYSCTL |= SDHC_SYSCTL_INITA;

+

+  TRACE(9, SDHC->PRSSTAT);

+}

+

+/**

+ * @brief   Sets the SDIO clock to data mode (25MHz or less).

+ *

+ * @param[in] sdcp      pointer to the @p SDCDriver object

+ * @param[in] clk       the clock mode

+ *

+ * @notapi

+ */

+void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk) {

+

+  (void)sdcp;

+

+  /* Stop the card clock */

+  SDHC->SYSCTL &= ~( SDHC_SYSCTL_SDCLKEN );

+

+  /* Change the divisor */

+  uint32_t ctl;

+  switch (clk) {

+  default:

+  case SDC_CLK_25MHz:

+    ctl =

+      SDHC_SYSCTL_DTOCV(DTOCV_700ms_25MHz) |

+      divisor_settings(DIV_RND_UP(KINETIS_SDHC_PERIPHERAL_FREQUENCY, 25000000));

+    break;

+  case SDC_CLK_50MHz:

+    ctl =

+      SDHC_SYSCTL_DTOCV(DTOCV_700ms_50MHz) |

+      divisor_settings(DIV_RND_UP(KINETIS_SDHC_PERIPHERAL_FREQUENCY, 50000000));

+    break;

+  }

+

+  /* Restart the clock */

+  enable_clock_when_stable(ctl);

+}

+

+/**

+ * @brief   Stops the SDIO clock.

+ *

+ * @param[in] sdcp      pointer to the @p SDCDriver object

+ *

+ * @notapi

+ */

+void sdc_lld_stop_clk(SDCDriver *sdcp) {

+  (void)sdcp;

+  SDHC->SYSCTL &= ~( SDHC_SYSCTL_SDCLKEN );

+}

+

+/**

+ * @brief   Switches the bus to 4 bit or 8 bit mode.

+ *

+ * @param[in] sdcp      pointer to the @p SDCDriver object

+ * @param[in] mode      bus mode

+ *

+ * @notapi

+ */

+void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode) {

+  (void)sdcp;

+  uint32_t proctl = SDHC->PROCTL & ~( SDHC_PROCTL_DTW_MASK );

+

+  switch (mode) {

+  case SDC_MODE_1BIT:

+    proctl |= SDHC_PROCTL_DTW_1BIT;

+    break;

+  case SDC_MODE_4BIT:

+    proctl |= SDHC_PROCTL_DTW_4BIT;

+    break;

+  case SDC_MODE_8BIT:

+    proctl |= SDHC_PROCTL_DTW_8BIT;

+    break;

+  default:

+    osalDbgAssert(false, "invalid bus mode");

+    break;

+  }

+

+  SDHC->PROCTL = proctl;

+}

+

+/**

+ * @brief   Sends an SDIO command with no response expected.

+ *

+ * @param[in] sdcp      pointer to the @p SDCDriver object

+ * @param[in] cmd       card command

+ * @param[in] arg       command argument

+ *

+ * @notapi

+ */

+void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg) {

+  SDHC->CMDARG = arg;

+  uint32_t xfer =

+    SDHC_XFERTYP_CMDINX(cmd) |

+    SDHC_XFERTYP_CMDTYP_NORMAL |

+    /* DPSEL=0, CICEN=0, CCCEN=0 */

+    SDHC_XFERTYP_RSPTYP_NONE;

+

+  send_and_wait_cmd(sdcp, xfer);

+}

+

+/**

+ * @brief   Sends an SDIO command with a short response expected.

+ * @note    The CRC is not verified.

+ *

+ * @param[in] sdcp      pointer to the @p SDCDriver object

+ * @param[in] cmd       card command

+ * @param[in] arg       command argument

+ * @param[out] resp     pointer to the response buffer (one word)

+ *

+ * @return              The operation status.

+ * @retval HAL_SUCCESS  operation succeeded.

+ * @retval HAL_FAILED   operation failed.

+ *

+ * @notapi

+ */

+bool sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,

+                            uint32_t *resp) {

+  SDHC->CMDARG = arg;

+  uint32_t xfer =

+    SDHC_XFERTYP_CMDINX(cmd) |

+    SDHC_XFERTYP_CMDTYP_NORMAL |

+    /* DPSEL=0, CICEN=0, CCCEN=0 */

+    SDHC_XFERTYP_RSPTYP_48;

+

+  bool waited = send_and_wait_cmd(sdcp, xfer);

+

+  *resp = SDHC->CMDRSP[0];

+

+  return waited;

+}

+

+/**

+ * @brief   Sends an SDIO command with a short response expected and CRC.

+ *

+ * @param[in] sdcp      pointer to the @p SDCDriver object

+ * @param[in] cmd       card command

+ * @param[in] arg       command argument

+ * @param[out] resp     pointer to the response buffer (one word)

+ *

+ * @return              The operation status.

+ * @retval HAL_SUCCESS  operation succeeded.

+ * @retval HAL_FAILED   operation failed.

+ *

+ * @notapi

+ */

+bool sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,

+                                uint32_t *resp) {

+  SDHC->CMDARG = arg;

+  uint32_t xfer =

+    SDHC_XFERTYP_CMDINX(cmd) |

+    SDHC_XFERTYP_CMDTYP_NORMAL |

+    /* DPSEL=0, CICEN=1, CCCEN=1 */

+    SDHC_XFERTYP_CICEN | SDHC_XFERTYP_CCCEN |

+    SDHC_XFERTYP_RSPTYP_48;

+

+  bool waited = send_and_wait_cmd(sdcp, xfer);

+

+  *resp = SDHC->CMDRSP[0];

+  TRACE(11, *resp);

+

+  return waited;

+}

+

+/**

+ * @brief   Sends an SDIO command with a long response expected and CRC.

+ *

+ * @param[in] sdcp      pointer to the @p SDCDriver object

+ * @param[in] cmd       card command

+ * @param[in] arg       command argument

+ * @param[out] resp     pointer to the response buffer (four words)

+ *

+ * @return              The operation status.

+ * @retval HAL_SUCCESS  operation succeeded.

+ * @retval HAL_FAILED   operation failed.

+ *

+ * @notapi

+ */

+bool sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,

+                               uint32_t *resp) {

+

+  /* In response format R2 (the 136-bit or "long" response) the CRC7

+     field is valid, but the command index field is set to all 1s, so

+     we need to disable the command index check function (CICEN=0). */

+  

+  SDHC->CMDARG = arg;

+  uint32_t xfer =

+    SDHC_XFERTYP_CMDINX(cmd) |

+    SDHC_XFERTYP_CMDTYP_NORMAL |

+    /* DPSEL=0, CICEN=0, CCCEN=1 */

+    SDHC_XFERTYP_CCCEN |

+    SDHC_XFERTYP_RSPTYP_136;

+

+  bool waited = send_and_wait_cmd(sdcp, xfer);

+

+  resp[0] = SDHC->CMDRSP[0];

+  resp[1] = SDHC->CMDRSP[1];

+  resp[2] = SDHC->CMDRSP[2];

+  resp[3] = SDHC->CMDRSP[3];

+

+  return waited;

+}

+

+/**

+ * @brief   Reads one or more blocks.

+ *

+ * @param[in] sdcp      pointer to the @p SDCDriver object

+ * @param[in] startblk  first block to read

+ * @param[out] buf      pointer to the read buffer

+ * @param[in] n         number of blocks to read

+ *

+ * @return              The operation status.

+ * @retval HAL_SUCCESS  operation succeeded.

+ * @retval HAL_FAILED   operation failed.

+ *

+ * @notapi

+ */

+

+bool sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,

+		  uint8_t *buf, uint32_t n) {

+  uint32_t cmdx = (n == 1)?

+    SDHC_XFERTYP_CMDINX(MMCSD_CMD_READ_SINGLE_BLOCK) :

+    SDHC_XFERTYP_CMDINX(MMCSD_CMD_READ_MULTIPLE_BLOCK);

+  cmdx |= SDHC_XFERTYP_DTDSEL;

+

+  return sdc_lld_transfer(sdcp, startblk, (uintptr_t)buf, n, cmdx);

+}

+

+/**

+ * @brief   Writes one or more blocks.

+ *

+ * @param[in] sdcp      pointer to the @p SDCDriver object

+ * @param[in] startblk  first block to write

+ * @param[out] buf      pointer to the write buffer

+ * @param[in] n         number of blocks to write

+ *

+ * @return              The operation status.

+ * @retval HAL_SUCCESS operation succeeded.

+ * @retval HAL_FAILED   operation failed.

+ *

+ * @notapi

+ */

+bool sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,

+                   const uint8_t *buf, uint32_t n) {

+  uint32_t cmdx = (n == 1)?

+    SDHC_XFERTYP_CMDINX(MMCSD_CMD_WRITE_BLOCK) :

+    SDHC_XFERTYP_CMDINX(MMCSD_CMD_WRITE_MULTIPLE_BLOCK);

+

+  return sdc_lld_transfer(sdcp, startblk, (uintptr_t)buf, n, cmdx);

+}

+

+/**

+ * @brief   Waits for card idle condition.

+ *

+ * @param[in] sdcp      pointer to the @p SDCDriver object

+ *

+ * @return              The operation status.

+ * @retval HAL_SUCCESS  the operation succeeded.

+ * @retval HAL_FAILED   the operation failed.

+ *

+ * @api

+ */

+bool sdc_lld_sync(SDCDriver *sdcp) {

+

+  (void)sdcp;

+

+  return HAL_SUCCESS;

+}

+

+bool sdc_lld_read_special(SDCDriver *sdcp, uint8_t *buf, size_t bytes,

+			  uint8_t cmd, uint32_t argument) {

+  uintptr_t bufaddr = (uintptr_t)buf;

+

+  osalDbgCheck((bufaddr & 0x03) == 0);  /* Must be 32-bit aligned */

+  osalDbgCheck(bytes > 0);

+  osalDbgCheck(bytes < 4096);

+

+  osalDbgAssert((SDHC->PRSSTAT & (SDHC_PRSSTAT_DLA|SDHC_PRSSTAT_CDIHB|SDHC_PRSSTAT_CIHB)) == 0,

+		"SDHC interface not ready");

+

+  TRACE(5, argument);

+

+  /* Store the cmd argument and DMA start address */

+  SDHC->CMDARG = argument;

+  SDHC->DSADDR = bufaddr;

+

+  /* We're reading one block, of a (possibly) nonstandard size */

+  SDHC->BLKATTR = SDHC_BLKATTR_BLKSIZE(bytes);

+

+  uint32_t xfer =

+    SDHC_XFERTYP_CMDINX(cmd) |    /* the command */

+    SDHC_XFERTYP_DTDSEL |         /* read transfer (card -> host) */

+    SDHC_XFERTYP_CMDTYP_NORMAL |

+    SDHC_XFERTYP_CICEN | SDHC_XFERTYP_CCCEN |

+    SDHC_XFERTYP_RSPTYP_48 |

+    SDHC_XFERTYP_DPSEL | SDHC_XFERTYP_DMAEN;  /* DMA-assisted data transfer */

+

+  return send_and_wait_transfer(sdcp, xfer);

+}

+

+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {

+  (void)sdcp;

+

+  return ( SDHC->PRSSTAT & SDHC_PRSSTAT_CLSL )? true : false;

+}

+

+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {

+  (void)sdcp;

+  return false;

+}

+

+#endif /* HAL_USE_SDC == TRUE */

+

+/** @} */

diff --git a/os/hal/ports/KINETIS/LLD/hal_sdc_lld.h b/os/hal/ports/KINETIS/LLD/hal_sdc_lld.h
new file mode 100644
index 0000000..9f77bf6
--- /dev/null
+++ b/os/hal/ports/KINETIS/LLD/hal_sdc_lld.h
@@ -0,0 +1,202 @@
+/*

+    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio

+              Copyright (C) 2017 Wim Lewis

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    hal_sdc_lld.h

+ * @brief   PLATFORM SDC subsystem low level driver header.

+ *

+ * @addtogroup SDC

+ * @{

+ */

+

+#ifndef HAL_SDC_LLD_H

+#define HAL_SDC_LLD_H

+

+#if (HAL_USE_SDC == TRUE) || defined(__DOXYGEN__)

+

+/*===========================================================================*/

+/* Driver constants.                                                         */

+/*===========================================================================*/

+

+#define SDHC_XFERTYP_CMDTYP_NORMAL	SDHC_XFERTYP_CMDTYP(0)

+#define SDHC_XFERTYP_CMDTYP_SUSPEND	SDHC_XFERTYP_CMDTYP(1)

+#define SDHC_XFERTYP_CMDTYP_RESUME	SDHC_XFERTYP_CMDTYP(2)

+#define SDHC_XFERTYP_CMDTYP_ABORT	SDHC_XFERTYP_CMDTYP(3)

+

+#define SDHC_XFERTYP_RSPTYP_NONE	SDHC_XFERTYP_RSPTYP(0)  /* no response */

+#define SDHC_XFERTYP_RSPTYP_136		SDHC_XFERTYP_RSPTYP(1)	/* 136-bit response */

+#define SDHC_XFERTYP_RSPTYP_48		SDHC_XFERTYP_RSPTYP(2)	/* 48-bit response */

+#define SDHC_XFERTYP_RSPTYP_48b		SDHC_XFERTYP_RSPTYP(3)	/* 48-bit plus busy */

+

+#define SDHC_PROCTL_DTW_1BIT            SDHC_PROCTL_DTW(0)

+#define SDHC_PROCTL_DTW_4BIT            SDHC_PROCTL_DTW(1)

+#define SDHC_PROCTL_DTW_8BIT            SDHC_PROCTL_DTW(2)

+

+/*===========================================================================*/

+/* Driver pre-compile time settings.                                         */

+/*===========================================================================*/

+

+/**

+ * @name    PLATFORM configuration options

+ * @{

+ */

+/**

+ * @brief   SDC1 driver enable switch.

+ * @details If set to @p TRUE the support for SDC1 is included.

+ * @note    The default is @p TRUE if HAL_USE_SDC is set.

+ */

+#if !defined(PLATFORM_SDC_USE_SDC1) || defined(__DOXYGEN__)

+#define PLATFORM_SDC_USE_SDC1                  TRUE

+#endif

+/** @} */

+

+/*===========================================================================*/

+/* Derived constants and error checks.                                       */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver data structures and types.                                         */

+/*===========================================================================*/

+

+/**

+ * @brief   Type of card flags.

+ */

+typedef uint32_t sdcmode_t;

+

+/**

+ * @brief   SDC Driver condition flags type.

+ */

+typedef uint32_t sdcflags_t;

+

+/**

+ * @brief   Type of a structure representing an SDC driver.

+ */

+typedef struct SDCDriver SDCDriver;

+

+/**

+ * @brief   Driver configuration structure.

+ * @note    It could be empty on some architectures.

+ */

+typedef struct {

+  /**

+   * @brief   Working area for memory consuming operations.

+   * @note    It is mandatory for detecting MMC cards bigger than 2GB else it

+   *          can be @p NULL.

+   * @note    Memory pointed by this buffer is only used by @p sdcConnect(),

+   *          afterward it can be reused for other purposes.

+   */

+  uint8_t       *scratchpad;

+  /**

+   * @brief   Bus width.

+   */

+  sdcbusmode_t  bus_width;

+  /* End of the mandatory fields.*/

+} SDCConfig;

+

+/**

+ * @brief   @p SDCDriver specific methods.

+ */

+#define _sdc_driver_methods                                                 \

+  _mmcsd_block_device_methods

+

+/**

+ * @extends MMCSDBlockDeviceVMT

+ *

+ * @brief   @p SDCDriver virtual methods table.

+ */

+struct SDCDriverVMT {

+  _sdc_driver_methods

+};

+

+/**

+ * @brief   Structure representing an SDC driver.

+ */

+struct SDCDriver {

+  /**

+   * @brief Virtual Methods Table.

+   */

+  const struct SDCDriverVMT *vmt;

+  _mmcsd_block_device_data

+  /**

+   * @brief Current configuration data.

+   */

+  const SDCConfig           *config;

+  /**

+   * @brief Various flags regarding the mounted card.

+   */

+  sdcmode_t                 cardmode;

+  /**

+   * @brief Errors flags.

+   */

+  sdcflags_t                errors;

+  /**

+   * @brief Card RCA.

+   */

+  uint32_t                  rca;

+  /* End of the mandatory fields.*/

+

+  /* Platform specific fields */

+  thread_reference_t        thread;

+};

+

+/*===========================================================================*/

+/* Driver macros.                                                            */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* External declarations.                                                    */

+/*===========================================================================*/

+

+#if (PLATFORM_SDC_USE_SDC1 == TRUE) && !defined(__DOXYGEN__)

+extern SDCDriver SDCD1;

+#endif

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+  void sdc_lld_init(void);

+  void sdc_lld_start(SDCDriver *sdcp);

+  void sdc_lld_stop(SDCDriver *sdcp);

+  void sdc_lld_start_clk(SDCDriver *sdcp);

+  void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk);

+  void sdc_lld_stop_clk(SDCDriver *sdcp);

+  void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode);

+  void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg);

+  bool sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,

+                              uint32_t *resp);

+  bool sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,

+                                  uint32_t *resp);

+  bool sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,

+                                 uint32_t *resp);

+  bool sdc_lld_read_special(SDCDriver *sdcp, uint8_t *buf, size_t bytes,

+                            uint8_t cmd, uint32_t argument);

+  bool sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,

+                    uint8_t *buf, uint32_t n);

+  bool sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,

+                     const uint8_t *buf, uint32_t n);

+  bool sdc_lld_sync(SDCDriver *sdcp);

+  bool sdc_lld_is_card_inserted(SDCDriver *sdcp);

+  bool sdc_lld_is_write_protected(SDCDriver *sdcp);

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* HAL_USE_SDC == TRUE */

+

+#endif /* HAL_SDC_LLD_H */

+

+/** @} */

diff --git a/os/hal/ports/KINETIS/LLD/hal_serial_lld.c b/os/hal/ports/KINETIS/LLD/hal_serial_lld.c
index c75d41a..c92fa5c 100644
--- a/os/hal/ports/KINETIS/LLD/hal_serial_lld.c
+++ b/os/hal/ports/KINETIS/LLD/hal_serial_lld.c
@@ -1,5 +1,6 @@
 /*

     ChibiOS - Copyright (C) 2013-2015 Fabio Utzig

+              Copyright (C) 2017 Wim Lewis

 

     Licensed under the Apache License, Version 2.0 (the "License");

     you may not use this file except in compliance with the License.

@@ -107,33 +108,37 @@ static void serve_error_interrupt(SerialDriver *sdp) {
   UART_w_TypeDef *u = &(sdp->uart);

   uint8_t s1 = *(u->s1_p);

 

-  /* S1 bits are write-1-to-clear for UART0 on KL2x. */

-  /* Clearing on K20x and KL2x/UART>0 is done by reading S1 and

+  /* Clearing on K20x, K60x, and KL2x/UART>0 is done by reading S1 and

    * then reading D.*/

 

-#if defined(KL2x) && KINETIS_SERIAL_USE_UART0

-  if(sdp == &SD1) {

-    if(s1 & UARTx_S1_IDLE) {

-      *(u->s1_p) |= UARTx_S1_IDLE;

-    }

+  if(s1 & UARTx_S1_IDLE) {

+    (void)*(u->d_p);

+  }

 

-    if(s1 & (UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF)) {

-      set_error(sdp, s1);

-      *(u->s1_p) |= UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF;

-    }

-    return;

+  if(s1 & (UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF)) {

+    set_error(sdp, s1);

+    (void)*(u->d_p);

   }

-#endif /* KL2x && KINETIS_SERIAL_USE_UART0 */

+}

+

+#if defined(KL2x) && KINETIS_SERIAL_USE_UART0

+static void serve_error_interrupt_uart0(void) {

+  SerialDriver *sdp = &SD1;

+  UART_w_TypeDef *u = &(sdp->uart);

+  uint8_t s1 = *(u->s1_p);

+

+  /* S1 bits are write-1-to-clear for UART0 on KL2x. */

 

   if(s1 & UARTx_S1_IDLE) {

-    (void)*(u->d_p);

+    *(u->s1_p) |= UARTx_S1_IDLE;

   }

 

   if(s1 & (UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF)) {

     set_error(sdp, s1);

-    (void)*(u->d_p);

+    *(u->s1_p) |= UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF;

   }

 }

+#endif /* KL2x && KINETIS_SERIAL_USE_UART0 */

 

 /**

  * @brief   Common IRQ handler.

@@ -173,6 +178,12 @@ static void serve_interrupt(SerialDriver *sdp) {
     }

   }

 

+#if defined(KL2x) && KINETIS_SERIAL_USE_UART0

+  if (sdp == &SD1) {

+    serve_error_interrupt_uart0();

+    return;

+  }

+#endif

   serve_error_interrupt(sdp);

 }

 

@@ -196,29 +207,28 @@ static void preload(SerialDriver *sdp) {
 /**

  * @brief   Driver output notification.

  */

-#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)

-static void notify1(io_queue_t *qp)

+static void notify(io_queue_t *qp)

 {

-  (void)qp;

-  preload(&SD1);

+  preload(qp->q_link);

 }

-#endif

 

-#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)

-static void notify2(io_queue_t *qp)

-{

-  (void)qp;

-  preload(&SD2);

+/**

+ * @brief   Common driver initialization, except LP.

+ */

+static void sd_lld_init_driver(SerialDriver *SDn, UART_TypeDef *UARTn) {

+  /* Driver initialization.*/

+  sdObjectInit(SDn, NULL, notify);

+  SDn->uart.bdh_p = &(UARTn->BDH);

+  SDn->uart.bdl_p = &(UARTn->BDL);

+  SDn->uart.c1_p =  &(UARTn->C1);

+  SDn->uart.c2_p =  &(UARTn->C2);

+  SDn->uart.c3_p =  &(UARTn->C3);

+  SDn->uart.c4_p =  &(UARTn->C4);

+  SDn->uart.s1_p =  (volatile uint8_t *)&(UARTn->S1);

+  SDn->uart.s2_p =  &(UARTn->S2);

+  SDn->uart.d_p =   &(UARTn->D);

+  SDn->uart.uart_p = UARTn;

 }

-#endif

-

-#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)

-static void notify3(io_queue_t *qp)

-{

-  (void)qp;

-  preload(&SD3);

-}

-#endif

 

 /**

  * @brief   Common UART configuration.

@@ -252,9 +262,9 @@ static void configure_uart(SerialDriver *sdp, const SerialConfig *config) {
   }

 #endif /* KINETIS_SERIAL_USE_UART0 */

 

-#elif defined(K20x) /* KL2x */

+#elif defined(K20x) || defined(K60x) /* KL2x */

 

-  /* UARTs 0 and 1 are clocked from SYSCLK, others from BUSCLK on K20x. */

+  /* UARTs 0 and 1 are clocked from SYSCLK, others from BUSCLK on K20x and K60x. */

 #if KINETIS_SERIAL_USE_UART0

   if(sdp == &SD1)

     divisor = KINETIS_SYSCLK_FREQUENCY;

@@ -272,9 +282,9 @@ static void configure_uart(SerialDriver *sdp, const SerialConfig *config) {
 

   *(uart->bdh_p) = UARTx_BDH_SBR(divisor >> 13) | (*(uart->bdh_p) & ~UARTx_BDH_SBR_MASK);

   *(uart->bdl_p) = UARTx_BDL_SBR(divisor >> 5);

-#if defined(K20x)

+#if defined(K20x) || defined(K60x)

   *(uart->c4_p) = UARTx_C4_BRFA(divisor) | (*(uart->c4_p) & ~UARTx_C4_BRFA_MASK);

-#endif /* K20x */

+#endif /* K20x, K60x */

 

   /* Line settings. */

   *(uart->c1_p) = 0;

@@ -312,12 +322,40 @@ OSAL_IRQ_HANDLER(KINETIS_SERIAL2_IRQ_VECTOR) {
 }

 #endif

 

+#if KINETIS_SERIAL_USE_UART3 || defined(__DOXYGEN__)

+OSAL_IRQ_HANDLER(KINETIS_SERIAL3_IRQ_VECTOR) {

+  OSAL_IRQ_PROLOGUE();

+  serve_interrupt(&SD4);

+  OSAL_IRQ_EPILOGUE();

+}

+#endif

+

+#if KINETIS_SERIAL_USE_UART4 || defined(__DOXYGEN__)

+OSAL_IRQ_HANDLER(KINETIS_SERIAL4_IRQ_VECTOR) {

+  OSAL_IRQ_PROLOGUE();

+  serve_interrupt(&SD5);

+  OSAL_IRQ_EPILOGUE();

+}

+#endif

+

+#if KINETIS_SERIAL_USE_UART5 || defined(__DOXYGEN__)

+OSAL_IRQ_HANDLER(KINETIS_SERIAL5_IRQ_VECTOR) {

+  OSAL_IRQ_PROLOGUE();

+  serve_interrupt(&SD6);

+  OSAL_IRQ_EPILOGUE();

+}

+#endif

+

 #if KINETIS_HAS_SERIAL_ERROR_IRQ

 

 #if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)

 OSAL_IRQ_HANDLER(KINETIS_SERIAL0_ERROR_IRQ_VECTOR) {

   OSAL_IRQ_PROLOGUE();

+#if defined(KL2x)

+  serve_error_interrupt_uart0();

+#else

   serve_error_interrupt(&SD1);

+#endif

   OSAL_IRQ_EPILOGUE();

 }

 #endif

@@ -338,6 +376,30 @@ OSAL_IRQ_HANDLER(KINETIS_SERIAL2_ERROR_IRQ_VECTOR) {
 }

 #endif

 

+#if KINETIS_SERIAL_USE_UART3 || defined(__DOXYGEN__)

+OSAL_IRQ_HANDLER(KINETIS_SERIAL3_ERROR_IRQ_VECTOR) {

+  OSAL_IRQ_PROLOGUE();

+  serve_error_interrupt(&SD4);

+  OSAL_IRQ_EPILOGUE();

+}

+#endif

+

+#if KINETIS_SERIAL_USE_UART4 || defined(__DOXYGEN__)

+OSAL_IRQ_HANDLER(KINETIS_SERIAL4_ERROR_IRQ_VECTOR) {

+  OSAL_IRQ_PROLOGUE();

+  serve_error_interrupt(&SD5);

+  OSAL_IRQ_EPILOGUE();

+}

+#endif

+

+#if KINETIS_SERIAL_USE_UART5 || defined(__DOXYGEN__)

+OSAL_IRQ_HANDLER(KINETIS_SERIAL5_ERROR_IRQ_VECTOR) {

+  OSAL_IRQ_PROLOGUE();

+  serve_error_interrupt(&SD6);

+  OSAL_IRQ_EPILOGUE();

+}

+#endif

+

 #endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */

 

 /*===========================================================================*/

@@ -353,19 +415,11 @@ void sd_lld_init(void) {
 

 #if KINETIS_SERIAL_USE_UART0

   /* Driver initialization.*/

-  sdObjectInit(&SD1, NULL, notify1);

 #if ! KINETIS_SERIAL0_IS_LPUART

-  SD1.uart.bdh_p = &(UART0->BDH);

-  SD1.uart.bdl_p = &(UART0->BDL);

-  SD1.uart.c1_p =  &(UART0->C1);

-  SD1.uart.c2_p =  &(UART0->C2);

-  SD1.uart.c3_p =  &(UART0->C3);

-  SD1.uart.c4_p =  &(UART0->C4);

-  SD1.uart.s1_p =  (volatile uint8_t *)&(UART0->S1);

-  SD1.uart.s2_p =  &(UART0->S2);

-  SD1.uart.d_p =   &(UART0->D);

+  sd_lld_init_driver(&SD1, UART0);

 #else /* ! KINETIS_SERIAL0_IS_LPUART */

   /* little endian! */

+  sdObjectInit(&SD1, NULL, notify);

   SD1.uart.bdh_p = ((uint8_t *)&(LPUART0->BAUD)) + 1; /* BDH: BAUD, byte 3 */

   SD1.uart.bdl_p = ((uint8_t *)&(LPUART0->BAUD)) + 0; /* BDL: BAUD, byte 4 */

   SD1.uart.c1_p =  ((uint8_t *)&(LPUART0->CTRL)) + 0; /* C1: CTRL, byte 4 */

@@ -389,20 +443,11 @@ void sd_lld_init(void) {
 

 #if KINETIS_SERIAL_USE_UART1

   /* Driver initialization.*/

-  sdObjectInit(&SD2, NULL, notify2);

 #if ! KINETIS_SERIAL1_IS_LPUART

-  SD2.uart.bdh_p = &(UART1->BDH);

-  SD2.uart.bdl_p = &(UART1->BDL);

-  SD2.uart.c1_p =  &(UART1->C1);

-  SD2.uart.c2_p =  &(UART1->C2);

-  SD2.uart.c3_p =  &(UART1->C3);

-  SD2.uart.c4_p =  &(UART1->C4);

-  SD2.uart.s1_p =  (volatile uint8_t *)&(UART1->S1);

-  SD2.uart.s2_p =  &(UART1->S2);

-  SD2.uart.d_p =   &(UART1->D);

-  SD2.uart.uart_p = UART1;

+  sd_lld_init_driver(&SD2, UART1);

 #else /* ! KINETIS_SERIAL1_IS_LPUART */

   /* little endian! */

+  sdObjectInit(&SD2, NULL, notify);

   SD2.uart.bdh_p = ((uint8_t *)&(LPUART1->BAUD)) + 1; /* BDH: BAUD, byte 3 */

   SD2.uart.bdl_p = ((uint8_t *)&(LPUART1->BAUD)) + 0; /* BDL: BAUD, byte 4 */

   SD2.uart.c1_p =  ((uint8_t *)&(LPUART1->CTRL)) + 0; /* C1: CTRL, byte 4 */

@@ -418,19 +463,20 @@ void sd_lld_init(void) {
 #endif /* KINETIS_SERIAL_USE_UART1 */

 

 #if KINETIS_SERIAL_USE_UART2

-  /* Driver initialization.*/

-  sdObjectInit(&SD3, NULL, notify3);

-  SD3.uart.bdh_p = &(UART2->BDH);

-  SD3.uart.bdl_p = &(UART2->BDL);

-  SD3.uart.c1_p =  &(UART2->C1);

-  SD3.uart.c2_p =  &(UART2->C2);

-  SD3.uart.c3_p =  &(UART2->C3);

-  SD3.uart.c4_p =  &(UART2->C4);

-  SD3.uart.s1_p =  (volatile uint8_t *)&(UART2->S1);

-  SD3.uart.s2_p =  &(UART2->S2);

-  SD3.uart.d_p =   &(UART2->D);

-  SD3.uart.uart_p = UART2;

+  sd_lld_init_driver(&SD3, UART2);

 #endif /* KINETIS_SERIAL_USE_UART2 */

+

+#if KINETIS_SERIAL_USE_UART3

+  sd_lld_init_driver(&SD4, UART3);

+#endif /* KINETIS_SERIAL_USE_UART3 */

+

+#if KINETIS_SERIAL_USE_UART4

+  sd_lld_init_driver(&SD5, UART4);

+#endif /* KINETIS_SERIAL_USE_UART4 */

+

+#if KINETIS_SERIAL_USE_UART5

+  sd_lld_init_driver(&SD6, UART5);

+#endif /* KINETIS_SERIAL_USE_UART5 */

 }

 

 /**

@@ -517,6 +563,33 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
     }

 #endif /* KINETIS_SERIAL_USE_UART2 */

 

+#if KINETIS_SERIAL_USE_UART3

+    if (sdp == &SD4) {

+      SIM->SCGC4 |= SIM_SCGC4_UART3;

+      configure_uart(sdp, config);

+      nvicEnableVector(UART3Status_IRQn, KINETIS_SERIAL_UART3_PRIORITY);

+      nvicEnableVector(UART3Error_IRQn, KINETIS_SERIAL_UART3_PRIORITY);

+    }

+#endif /* KINETIS_SERIAL_USE_UART3 */

+

+#if KINETIS_SERIAL_USE_UART4

+    if (sdp == &SD5) {

+      SIM->SCGC1 |= SIM_SCGC1_UART4;

+      configure_uart(sdp, config);

+      nvicEnableVector(UART4Status_IRQn, KINETIS_SERIAL_UART4_PRIORITY);

+      nvicEnableVector(UART4Error_IRQn, KINETIS_SERIAL_UART4_PRIORITY);

+    }

+#endif /* KINETIS_SERIAL_USE_UART4 */

+

+#if KINETIS_SERIAL_USE_UART5

+    if (sdp == &SD6) {

+      SIM->SCGC1 |= SIM_SCGC1_UART5;

+      configure_uart(sdp, config);

+      nvicEnableVector(UART5Status_IRQn, KINETIS_SERIAL_UART5_PRIORITY);

+      nvicEnableVector(UART5Error_IRQn, KINETIS_SERIAL_UART5_PRIORITY);

+    }

+#endif /* KINETIS_SERIAL_USE_UART5 */

+

   }

   /* Configures the peripheral.*/

 

@@ -587,6 +660,30 @@ void sd_lld_stop(SerialDriver *sdp) {
       SIM->SCGC4 &= ~SIM_SCGC4_UART2;

     }

 #endif

+

+#if KINETIS_SERIAL_USE_UART3

+    if (sdp == &SD4) {

+      nvicDisableVector(UART3Status_IRQn);

+      nvicDisableVector(UART3Error_IRQn);

+      SIM->SCGC4 &= ~SIM_SCGC4_UART3;

+    }

+#endif

+

+#if KINETIS_SERIAL_USE_UART4

+    if (sdp == &SD5) {

+      nvicDisableVector(UART4Status_IRQn);

+      nvicDisableVector(UART4Error_IRQn);

+      SIM->SCGC1 &= ~SIM_SCGC1_UART4;

+    }

+#endif

+

+#if KINETIS_SERIAL_USE_UART5

+    if (sdp == &SD6) {

+      nvicDisableVector(UART5Status_IRQn);

+      nvicDisableVector(UART5Error_IRQn);

+      SIM->SCGC1 &= ~SIM_SCGC1_UART5;

+    }

+#endif

   }

 }

 

diff --git a/os/hal/ports/KINETIS/LLD/hal_usb_lld.c b/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
index 7b7aa0e..fee91c5 100644
--- a/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
+++ b/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
@@ -158,7 +158,7 @@ void usb_packet_transmit(USBDriver *usbp, usbep_t ep, size_t n)
   USBInEndpointState *isp = epc->in_state;

 

   bd_t *bd = (bd_t *)&_bdt[BDT_INDEX(ep, TX, isp->odd_even)];

-  

+

   if (n > (size_t)epc->in_maxsize)

     n = (size_t)epc->in_maxsize;

 

@@ -244,19 +244,16 @@ OSAL_IRQ_HANDLER(KINETIS_USB_IRQ_VECTOR) {
     {

       case BDT_PID_SETUP:                                              // SETUP

       {

-        /* Clear any pending IN stuff */

-        _bdt[BDT_INDEX(ep, TX, EVEN)].desc = 0;

-        _bdt[BDT_INDEX(ep, TX,  ODD)].desc = 0;

-        /* Also in the chibios state machine */

+        /* Clear receiving in the chibios state machine */

         (usbp)->receiving &= ~1;

-        /* After a SETUP, IN is always DATA1 */

-        usbp->epc[ep]->in_state->data_bank = DATA1;

-

-        /* Call SETUP function (ChibiOS core), which sends back stuff */

+        /* Call SETUP function (ChibiOS core), which prepares

+         * for send or receive and releases the buffer

+         */

         _usb_isr_invoke_setup_cb(usbp, ep);

-        /* Buffer is released by the above callback. */

-        /* from Paul: "unfreeze the USB, now that we're ready" */

-        USB0->CTL = USBx_CTL_USBENSOFEN;

+        /* When a setup packet is received, tx is suspended,

+         * so it needs to be resumed here.

+         */

+        USB0->CTL &= ~USBx_CTL_TXSUSPENDTOKENBUSY;

       } break;

       case BDT_PID_IN:                                                 // IN

       {

@@ -740,9 +737,23 @@ void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) {
   }

   /* Release the buffer

    * Setup packet is always DATA0

-   * Initialize buffers so current expects DATA0 & opposite DATA1 */

+   * Release the current DATA0 buffer

+   */

   bd->desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA0);

-  _bdt[BDT_INDEX(ep, RX, os->odd_even^ODD)].desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA1);

+  /* If DATA1 was expected, then the states are out of sync.

+   * So reset the other buffer too, and set it as DATA1.

+   * This should not happen in normal cases, but is possible in

+   * error situations. NOTE: it's possible that this is too late

+   * and the next packet has already been received and dropped, but

+   * there's nothing that we can do about that anymore at this point.

+   */

+  if (os->data_bank == DATA1)

+  {

+    bd_t *bd_next = (bd_t*)&_bdt[BDT_INDEX(ep, RX, os->odd_even^ODD)];

+    bd_next->desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA1);

+  }

+  /* After a SETUP, both in and out are always DATA1 */

+  usbp->epc[ep]->in_state->data_bank = DATA1;

   os->data_bank = DATA1;

 }

 

@@ -774,8 +785,22 @@ void usb_lld_start_out(USBDriver *usbp, usbep_t ep) {
  * @notapi

  */

 void usb_lld_start_in(USBDriver *usbp, usbep_t ep) {

-  (void)usbp;

-  (void)ep;

+  if (ep == 0 && usbp->ep0state == USB_EP0_IN_SENDING_STS) {

+    /* When a status packet is about to be sent on endpoint 0 the

+     * next packet will be a setup packet, which means that the

+     * buffer we expect after this should be DATA0, and the following

+     * DATA1. Since no out packets should be in flight at this time

+     * it's safe to initialize the buffers according to the expectations

+     * here.

+     */

+    const USBEndpointConfig* epc = usbp->epc[ep];

+    bd_t * bd = (bd_t*)&_bdt[BDT_INDEX(ep, RX, epc->out_state->odd_even)];

+    bd_t *bd_next = (bd_t*)&_bdt[BDT_INDEX(ep, RX, epc->out_state->odd_even^ODD)];

+

+    bd->desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA1);

+    bd_next->desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA0);

+    epc->out_state->data_bank = DATA0;

+  }

   usb_packet_transmit(usbp,ep,usbp->epc[ep]->in_state->txsize);

 }

 

diff --git a/os/hal/ports/KINETIS/LLD/hal_usb_lld.h b/os/hal/ports/KINETIS/LLD/hal_usb_lld.h
index 615d10d..bd4eb39 100644
--- a/os/hal/ports/KINETIS/LLD/hal_usb_lld.h
+++ b/os/hal/ports/KINETIS/LLD/hal_usb_lld.h
@@ -76,6 +76,13 @@
   #define KINETIS_USB_ENDPOINTS USB_MAX_ENDPOINTS+1

 #endif

 

+/**

+ * @brief   Host wake-up procedure duration.

+ */

+#if !defined(USB_HOST_WAKEUP_DURATION) || defined(__DOXYGEN__)

+#define USB_HOST_WAKEUP_DURATION            2

+#endif

+

 /*===========================================================================*/

 /* Derived constants and error checks.                                       */

 /*===========================================================================*/

@@ -97,6 +104,10 @@
 #error "KINETIS_USB_IRQ_VECTOR not defined"

 #endif

 

+#if (USB_HOST_WAKEUP_DURATION < 2) || (USB_HOST_WAKEUP_DURATION > 15)

+#error "invalid USB_HOST_WAKEUP_DURATION setting, it must be between 2 and 15"

+#endif

+

 /*===========================================================================*/

 /* Driver data structures and types.                                         */

 /*===========================================================================*/

@@ -345,25 +356,6 @@ struct USBDriver {
 /*===========================================================================*/

 

 /**

- * @brief   Host wake-up procedure duration.

- */

-#if !defined(USB_HOST_WAKEUP_DURATION) || defined(__DOXYGEN__)

-#define USB_HOST_WAKEUP_DURATION            2

-#endif

-

-/**

- * @brief   Start of host wake-up procedure.

- *

- * @notapi

- */

-#define usb_lld_wakeup_host(usbp)                                           \

-  do{                                                                       \

-    USB0->CTL |= USBx_CTL_RESUME;                                     \

-    osalThreadSleepMilliseconds(USB_HOST_WAKEUP_DURATION);                  \

-    USB0->CTL &= ~USBx_CTL_RESUME;                                    \

-  } while (false)

-

-/**

  * @brief   Returns the current frame number.

  *

  * @param[in] usbp      pointer to the @p USBDriver object

@@ -413,6 +405,18 @@ struct USBDriver {
 #endif /* KINETIS_USB0_IS_USBOTG */

 #endif

 

+/**

+ * @brief   Start of host wake-up procedure.

+ *

+ * @notapi

+ */

+#define usb_lld_wakeup_host(usbp)                                     \

+  do{                                                                 \

+    USB0->CTL |= USBx_CTL_RESUME;                                     \

+    osalThreadSleepMilliseconds(USB_HOST_WAKEUP_DURATION);            \

+    USB0->CTL &= ~USBx_CTL_RESUME;                                    \

+  } while (false)

+

 /*===========================================================================*/

 /* External declarations.                                                    */

 /*===========================================================================*/

diff --git a/os/hal/ports/MSP430X/hal_adc_lld.c b/os/hal/ports/MSP430X/hal_adc_lld.c
new file mode 100644
index 0000000..42d3cbe
--- /dev/null
+++ b/os/hal/ports/MSP430X/hal_adc_lld.c
@@ -0,0 +1,354 @@
+/*

+    ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    hal_adc_lld.c

+ * @brief   MSP430X ADC subsystem low level driver source.

+ *

+ * @addtogroup ADC

+ * @{

+ */

+

+#include "hal.h"

+

+#if (HAL_USE_ADC == TRUE) || defined(__DOXYGEN__)

+

+/*===========================================================================*/

+/* Driver local definitions.                                                 */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver exported variables.                                                */

+/*===========================================================================*/

+

+/**

+ * @brief   ADC1 driver identifier.

+ */

+#if (MSP430X_ADC_USE_ADC1 == TRUE) || defined(__DOXYGEN__)

+ADCDriver ADCD1;

+#endif

+

+/*===========================================================================*/

+/* Driver local variables and types.                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver local functions.                                                   */

+/*===========================================================================*/

+

+static void restart_dma(ADCDriver * adcp) {

+  /* TODO timeouts? */

+  /* Restart DMA transfer */

+  if (adcp->dma.registers == NULL) {

+    /* Acquire a DMA stream because dmaTransfer can be called from ISRs */

+    osalSysLockFromISR();

+    dmaAcquireI(&(adcp->dma), adcp->dma.index);

+    osalSysUnlockFromISR();

+    dmaTransfer(&(adcp->dma), &(adcp->req));

+  }

+  else {

+    dmaTransfer(&(adcp->dma), &(adcp->req));

+  }

+}

+

+static void dma_callback(void * args) {

+  ADCDriver * adcp = (ADCDriver *)args;

+

+  if (adcp->grpp == NULL)

+    return;

+

+  adcp->count++;

+

+  if (adcp->count == adcp->depth / 2) {

+    /* half-full interrupt */

+    _adc_isr_half_code(adcp);

+  }

+

+  if (adcp->count == adcp->depth) {

+    /* full interrupt */

+

+    /* adc_lld_stop_conversion is called automatically here if needed */

+    _adc_isr_full_code(adcp);

+    /* after isr_full, adcp->grpp is only non-NULL if it's a circular group */

+    if (adcp->grpp) {

+      /* Reset the buffer pointer */

+      adcp->req.dest_addr = adcp->samples;

+

+      restart_dma(adcp);

+

+      /* Reset the count */

+      adcp->count = 0;

+

+      /* Start next sequence */

+      adcp->regs->ctl[0] |= ADC12SC;

+    }

+  }

+  else {

+    /* Advance the buffer pointer */

+    adcp->req.dest_addr = adcp->samples + (adcp->req.size * adcp->count);

+

+    restart_dma(adcp);

+

+    /* Start next sequence */

+    adcp->regs->ctl[0] |= ADC12SC;

+  }

+}

+

+static void populate_tlv(ADCDriver * adcp) {

+  uint8_t * tlv_addr = (uint8_t *)TLV_START;

+

+  while (*tlv_addr != TLV_TAGEND && tlv_addr < (uint8_t *)TLV_END) {

+    if (*tlv_addr == TLV_ADC12CAL) {

+      adcp->adc_cal = (msp430x_adc_cal_t *)(tlv_addr + 2);

+    }

+    else if (*tlv_addr == TLV_REFCAL) {

+      adcp->ref_cal = (msp430x_ref_cal_t *)(tlv_addr + 2);

+    }

+    tlv_addr += (tlv_addr[1] + 2);

+  }

+}

+

+/*===========================================================================*/

+/* Driver interrupt handlers.                                                */

+/*===========================================================================*/

+

+PORT_IRQ_HANDLER(ADC12_VECTOR) {

+

+  OSAL_IRQ_PROLOGUE();

+

+  switch (__even_in_range(ADC12IV, ADC12IV_ADC12TOVIFG)) {

+

+  case ADC12IV_ADC12OVIFG: {

+    if (ADCD1.grpp == NULL)

+      break;

+    _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);

+    break;

+  }

+  case ADC12IV_ADC12TOVIFG: {

+    if (ADCD1.grpp == NULL)

+      break;

+    _adc_isr_error_code(&ADCD1, ADC_ERR_AWD);

+    break;

+  }

+  default:

+    osalDbgAssert(false, "unhandled ADC exception");

+    _adc_isr_error_code(&ADCD1, ADC_ERR_UNKNOWN);

+  }

+

+  OSAL_IRQ_EPILOGUE();

+}

+

+/*===========================================================================*/

+/* Driver exported functions.                                                */

+/*===========================================================================*/

+

+/**

+ * @brief   Low level ADC driver initialization.

+ *

+ * @notapi

+ */

+void adc_lld_init(void) {

+

+#if MSP430X_ADC_USE_ADC1 == TRUE

+  /* Driver initialization.*/

+  adcObjectInit(&ADCD1);

+  ADCD1.regs = (msp430x_adc_reg_t *)(&ADC12CTL0);

+  populate_tlv(&ADCD1);

+#endif

+}

+

+/**

+ * @brief   Configures and activates the ADC peripheral.

+ *

+ * @param[in] adcp      pointer to the @p ADCDriver object

+ *

+ * @notapi

+ */

+void adc_lld_start(ADCDriver * adcp) {

+

+  if (adcp->state == ADC_STOP) {

+    /* Enables the peripheral.*/

+    adcp->regs->ctl[0] = ADC12ON | ADC12MSC;

+    adcp->regs->ctl[1] =

+        MSP430X_ADC1_PDIV | MSP430X_ADC1_DIV | MSP430X_ADC1_SSEL | ADC12SHP;

+    adcp->regs->ctl[3] = ADC12ICH3MAP | ADC12ICH2MAP | ADC12ICH1MAP |

+                         ADC12ICH0MAP | ADC12TCMAP | ADC12BATMAP;

+    adcp->regs->ier[2] = ADC12TOVIE | ADC12OVIE;

+    adcp->req.trigger  = DMA_TRIGGER_MNEM(ADC12IFG);

+#if MSP430X_ADC_COMPACT_SAMPLES == TRUE

+    adcp->req.data_mode = MSP430X_DMA_SRCWORD | MSP430X_DMA_DSTBYTE;

+#else

+    adcp->req.data_mode = MSP430X_DMA_SRCWORD | MSP430X_DMA_DSTWORD;

+#endif

+    adcp->req.addr_mode         = MSP430X_DMA_SRCINCR | MSP430X_DMA_DSTINCR;

+    adcp->req.transfer_mode     = MSP430X_DMA_SINGLE;

+    adcp->req.callback.callback = dma_callback;

+    adcp->req.callback.args     = adcp;

+

+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE

+    bool b;

+    if (adcp->config->dma_index < MSP430X_DMA_CHANNELS) {

+      b = dmaAcquireI(&adcp->dma, adcp->config->dma_index);

+      osalDbgAssert(!b, "stream already allocated");

+    }

+    else {

+#endif

+      adcp->dma.registers = NULL;

+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE

+    }

+#endif

+  }

+  /* Configures the peripheral.*/

+}

+

+/**

+ * @brief   Deactivates the ADC peripheral.

+ *

+ * @param[in] adcp      pointer to the @p ADCDriver object

+ *

+ * @notapi

+ */

+void adc_lld_stop(ADCDriver * adcp) {

+

+  if (adcp->state == ADC_READY) {

+/* Resets the peripheral.*/

+

+/* Disables the peripheral.*/

+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE

+    if (adcp->config->dma_index < MSP430X_DMA_CHANNELS) {

+      dmaRelease(&(adcp->dma));

+    }

+#endif

+    adcp->regs->ctl[0] = 0;

+  }

+}

+

+/**

+ * @brief   Starts an ADC conversion.

+ *

+ * @param[in] adcp      pointer to the @p ADCDriver object

+ *

+ * @notapi

+ */

+void adc_lld_start_conversion(ADCDriver * adcp) {

+

+  /* always use sequential transfer mode - this is fine */

+  adcp->regs->ctl[1] |= ADC12CONSEQ0;

+

+  /* set resolution */

+  adcp->regs->ctl[2] |= adcp->grpp->res;

+  /* start from MEM0 */

+  adcp->regs->ctl[3] &= ~(ADC12CSTARTADD_31);

+

+  /* Configure voltage reference */

+  while (REFCTL0 & REFGENBUSY)

+    ;

+  REFCTL0 = adcp->grpp->vref_src;

+

+  for (int i = 0; i < adcp->grpp->num_channels; i++) {

+    osalDbgAssert(adcp->grpp->channels[i] < 32, "invalid channel number");

+    adcp->regs->mctl[i] = adcp->grpp->ref | adcp->grpp->channels[i];

+  }

+

+  adcp->regs->mctl[adcp->grpp->num_channels - 1] |= ADC12EOS;

+

+  adcp->req.source_addr = adcp->regs->mem;

+  adcp->req.dest_addr   = adcp->samples;

+  adcp->req.size        = adcp->grpp->num_channels;

+  adcp->count           = 0;

+

+/* TODO timeouts? */

+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE

+  if (adcp->config->dma_index >= MSP430X_DMA_CHANNELS) {

+    adcp->dma.index = dmaRequestS(&(adcp->req), TIME_INFINITE);

+  }

+  else {

+    dmaTransfer(&(adcp->dma), &(adcp->req));

+  }

+#else

+  adcp->dma.index       = dmaRequestS(&(adcp->req), TIME_INFINITE);

+#endif

+

+  adcp->regs->ctl[0] |= adcp->grpp->rate | ADC12MSC | ADC12ENC | ADC12SC;

+}

+

+/**

+ * @brief   Stops an ongoing conversion.

+ *

+ * @param[in] adcp      pointer to the @p ADCDriver object

+ *

+ * @notapi

+ */

+void adc_lld_stop_conversion(ADCDriver * adcp) {

+

+  /* TODO stop DMA transfers here */

+  adcp->regs->ctl[0] &= ~(ADC12ENC | ADC12SC);

+

+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE

+  if (adcp->config->dma_index >= MSP430X_DMA_CHANNELS) {

+#endif

+    if (adcp->dma.registers != NULL) {

+      dmaRelease(&(adcp->dma));

+      adcp->dma.registers = NULL;

+    }

+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE

+  }

+#endif

+}

+

+adcsample_t adcMSP430XAdjustResult(ADCConversionGroup * grpp,

+                                   adcsample_t sample) {

+  uint32_t tmp;

+  uint16_t fact;

+  if (grpp->ref == MSP430X_ADC_VSS_VREF_BUF ||

+      grpp->ref == MSP430X_ADC_VEREF_P_VREF_BUF ||

+      grpp->ref == MSP430X_ADC_VREF_BUF_VCC ||

+      grpp->ref == MSP430X_ADC_VREF_BUF_VEREF_P ||

+      grpp->ref == MSP430X_ADC_VEREF_N_VREF_BUF) {

+    /* Retrieve proper reference correction factor from TLV */

+    fact = (&(ADCD1.ref_cal->CAL_ADC_12VREF_FACTOR))[grpp->vref_src >> 4];

+    /* Calculate corrected value */

+    tmp    = (uint32_t)(sample << 1) * (uint32_t)fact;

+    sample = tmp >> 16;

+  }

+

+  /* Gain correction */

+  fact   = ADCD1.adc_cal->CAL_ADC_GAIN_FACTOR;

+  tmp    = (uint32_t)(sample << 1) * (uint32_t)fact;

+  sample = tmp >> 16;

+

+  /* Offset correction */

+  sample += ADCD1.adc_cal->CAL_ADC_OFFSET;

+

+  return sample;

+}

+

+adcsample_t adcMSP430XAdjustTemp(ADCConversionGroup * grpp,

+                                 adcsample_t sample) {

+  uint16_t t30;

+  uint16_t t85;

+

+  /* Retrieve proper T = 30 correction value from TLV */

+  t30 = (&(ADCD1.adc_cal->CAL_ADC_12T30))[grpp->vref_src >> 3];

+  /* Retrieve proper T = 85 correction value from TLV */

+  t85 = (&(ADCD1.adc_cal->CAL_ADC_12T30))[(grpp->vref_src >> 3) + 1];

+

+  return ((((int32_t)sample - (int32_t)t30) * (85 - 30)) / (t85 - t30)) + 30;

+}

+

+#endif /* HAL_USE_ADC == TRUE */

+

+/** @} */

diff --git a/os/hal/ports/MSP430X/hal_adc_lld.h b/os/hal/ports/MSP430X/hal_adc_lld.h
new file mode 100644
index 0000000..1cca36b
--- /dev/null
+++ b/os/hal/ports/MSP430X/hal_adc_lld.h
@@ -0,0 +1,516 @@
+/*

+    ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    hal_adc_lld.h

+ * @brief   MSP430X ADC subsystem low level driver header.

+ *

+ * @addtogroup ADC

+ * @{

+ */

+

+#ifndef HAL_ADC_LLD_H

+#define HAL_ADC_LLD_H

+

+#if (HAL_USE_ADC == TRUE) || defined(__DOXYGEN__)

+

+/*===========================================================================*/

+/* Driver constants.                                                         */

+/*===========================================================================*/

+

+/**

+ * @name    Sampling rates

+ * @{

+ */

+typedef enum {

+  MSP430X_ADC_SHT_4   = 0x0000,

+  MSP430X_ADC_SHT_8   = 0x1100,

+  MSP430X_ADC_SHT_16  = 0x2200,

+  MSP430X_ADC_SHT_32  = 0x3300,

+  MSP430X_ADC_SHT_64  = 0x4400,

+  MSP430X_ADC_SHT_96  = 0x5500,

+  MSP430X_ADC_SHT_128 = 0x6600,

+  MSP430X_ADC_SHT_192 = 0x7700,

+  MSP430X_ADC_SHT_256 = 0x8800,

+  MSP430X_ADC_SHT_384 = 0x9900,

+  MSP430X_ADC_SHT_512 = 0xAA00

+} MSP430XADCSampleRates;

+/** @} */

+

+/**

+ * @name    Resolution

+ * @{

+ */

+typedef enum {

+  MSP430X_ADC_RES_8BIT  = 0x0000,

+  MSP430X_ADC_RES_10BIT = 0x0010,

+  MSP430X_ADC_RES_12BIT = 0x0020

+} MSP430XADCResolution;

+/** @} */

+

+/**

+ * @name    References

+ * @{

+ */

+typedef enum {

+  MSP430X_ADC_VSS_VCC             = 0x0000,

+  MSP430X_ADC_VSS_VREF_BUF        = 0x0100,

+  MSP430X_ADC_VSS_VEREF_N         = 0x0200,

+  MSP430X_ADC_VSS_VEREF_P_BUF     = 0x0300,

+  MSP430X_ADC_VSS_VEREF_P         = 0x0400,

+  MSP430X_ADC_VEREF_P_BUF_VCC     = 0x0500,

+  MSP430X_ADC_VEREF_P_VCC         = 0x0600,

+  MSP430X_ADC_VEREF_P_VREF_BUF    = 0x0700,

+  MSP430X_ADC_VREF_BUF_VCC        = 0x0900,

+  MSP430X_ADC_VREF_BUF_VEREF_P    = 0x0B00,

+  MSP430X_ADC_VEREF_N_VCC         = 0x0C00,

+  MSP430X_ADC_VEREF_N_VREF_BUF    = 0x0D00,

+  MSP430X_ADC_VEREF_N_VEREF_P     = 0x0E00,

+  MSP430X_ADC_VEREF_N_VEREF_P_BUF = 0x0F00

+} MSP430XADCReferences;

+

+typedef enum {

+  MSP430X_REF_1V2     = 0x0000,

+  MSP430X_REF_2V0     = 0x0010,

+  MSP430X_REF_2V5     = 0x0020,

+  MSP430X_REF_1V2_EXT = 0x0002,

+  MSP430X_REF_2V0_EXT = 0x0012,

+  MSP430X_REF_2V5_EXT = 0x0022

+} MSP430XREFSources;

+

+#define MSP430X_REF_NONE MSP430X_REF_1V2

+

+/** @} */

+

+/*===========================================================================*/

+/* Driver pre-compile time settings.                                         */

+/*===========================================================================*/

+

+/**

+ * @name    MSP430X configuration options

+ * @{

+ */

+/**

+ * @brief   Stores ADC samples in an 8 bit integer.

+ * @note    10 and 12 bit sampling modes must not be used when this option is

+ *          enabled.

+ */

+#if !defined(MSP430X_ADC_COMPACT_SAMPLES) || defined(__DOXYGEN__)

+#define MSP430X_ADC_COMPACT_SAMPLES FALSE

+#endif

+

+/**

+ * @brief   ADC1 driver enable switch.

+ * @details If set to @p TRUE the support for ADC1 is included.

+ * @note    The default is @p TRUE.

+ */

+#if !defined(MSP430X_ADC_USE_ADC1) || defined(__DOXYGEN__)

+#define MSP430X_ADC_USE_ADC1 TRUE

+#endif

+

+/**]

+ * @brief   Exclusive DMA enable switch.

+ * @details If set to @p TRUE the support for exclusive DMA is included.

+ * @note    This increases the size of the compiled executable somewhat.

+ * @note    The default is @p FALSE.

+ */

+#if !defined(MSP430X_ADC_EXCLUSIVE_DMA) || defined(__DOXYGEN__)

+#define MSP430X_ADC_EXCLUSIVE_DMA FALSE

+#endif

+

+#if MSP430X_ADC_USE_ADC1

+

+/**

+ * @brief   ADC1 clock source configuration

+ */

+#if !defined(MSP430X_ADC1_CLK_SRC)

+#define MSP430X_ADC1_CLK_SRC MSP430X_MODCLK

+#endif

+

+#endif

+/** @} */

+

+/*===========================================================================*/

+/* Derived constants and error checks.                                       */

+/*===========================================================================*/

+

+#if MSP430X_ADC_USE_ADC1

+

+#if !defined(__MSP430_HAS_ADC12_B__)

+#error "No ADC present or ADC version not supported"

+#endif

+

+#if (MSP430X_ADC1_CLK_SRC == MSP430X_MODCLK)

+#define MSP430X_ADC1_CLK_FREQ MSP430X_MODCLK_FREQ

+#define MSP430X_ADC1_SSEL ADC12SSEL_0

+#elif (MSP430X_ADC1_CLK_SRC == MSP430X_ACLK)

+#define MSP430X_ADC1_CLK_FREQ MSP430X_ACLK_FREQ

+#define MSP430X_ADC1_SSEL ADC12SSEL_1

+#elif (MSP430X_ADC1_CLK_SRC == MSP430X_MCLK)

+#define MSP$30X_ADC1_CLK_FREQ MSP430X_MCLK_FREQ

+#define MSP430X_ADC1_SSEL ADC12SSEL_2

+#elif (MSP430X_ADC1_CLK_SRC == MSP430SMCLK)

+#define MSP430X_ADC1_CLK_FREQ MSP430X_SMCLK_FREQ

+#define MSP430X_ADC1_SSEL ADC12SSEL_3

+#else

+#error "Invalid ADC1 clock source requested!"

+#endif

+

+#if !defined(MSP430X_ADC1_FREQ)

+#warning "ADC clock frequency not defined - assuming 1 for all dividers"

+#define MSP430X_ADC1_DIV_CALC(x) (x == 1)

+#else

+#define MSP430X_ADC1_DIV_CALC(x)                                               \

+  ((MSP430X_ADC1_CLK_FREQ / x) == MSP430X_ADC1_FREQ)

+#endif

+

+/**

+ * @brief   ADC1 prescaler calculations

+ */

+#if MSP430X_ADC1_DIV_CALC(1)

+#define MSP430X_ADC1_PDIV ADC12PDIV__1

+#define MSP430X_ADC1_DIV ADC12DIV_0

+#elif MSP430X_ADC1_DIV_CALC(2)

+#define MSP430X_ADC1_PDIV ADC12PDIV__1

+#define MSP430X_ADC1_DIV ADC12DIV_1

+#elif MSP430X_ADC1_DIV_CALC(3)

+#define MSP430X_ADC1_PDIV ADC12PDIV__1

+#define MSP430X_ADC1_DIV ADC12DIV_2

+#elif MSP430X_ADC1_DIV_CALC(4)

+#define MSP430X_ADC1_PDIV ADC12PDIV__4

+#define MSP430X_ADC1_DIV ADC12DIV_0

+#elif MSP430X_ADC1_DIV_CALC(5)

+#define MSP430X_ADC1_PDIV ADC12PDIV__1

+#define MSP430X_ADC1_DIV ADC12DIV_4

+#elif MSP430X_ADC1_DIV_CALC(6)

+#define MSP430X_ADC1_PDIV ADC12PDIV__1

+#define MSP430X_ADC1_DIV ADC12DIV_5

+#elif MSP430X_ADC1_DIV_CALC(7)

+#define MSP430X_ADC1_PDIV ADC12PDIV__1

+#define MSP430X_ADC1_DIV ADC12DIV_6

+#elif MSP430X_ADC1_DIV_CALC(8)

+#define MSP430X_ADC1_PDIV ADC12PDIV__4

+#define MSP430X_ADC1_DIV ADC12DIV_2

+#elif MSP430X_ADC1_DIV_CALC(12)

+#define MSP430X_ADC1_PDIV ADC12PDIV__4

+#define MSP430X_ADC1_DIV ADC12DIV_2

+#elif MSP430X_ADC1_DIV_CALC(16)

+#define MSP430X_ADC1_PDIV ADC12PDIV__4

+#define MSP430X_ADC1_DIV ADC12DIV_3

+#elif MSP430X_ADC1_DIV_CALC(20)

+#define MSP430X_ADC1_PDIV ADC12PDIV__4

+#define MSP430X_ADC1_DIV ADC12DIV_4

+#elif MSP430X_ADC1_DIV_CALC(24)

+#define MSP430X_ADC1_PDIV ADC12PDIV__4

+#define MSP430X_ADC1_DIV ADC12DIV_5

+#elif MSP430X_ADC1_DIV_CALC(28)

+#define MSP430X_ADC1_PDIV ADC12PDIV__4

+#define MSP430X_ADC1_DIV ADC12DIV_6

+#elif MSP430X_ADC1_DIV_CALC(32)

+#define MSP430X_ADC1_PDIV ADC12PDIV__32

+#define MSP430X_ADC1_DIV ADC12DIV_0

+#elif MSP430X_ADC1_DIV_CALC(64)

+#define MSP430X_ADC1_PDIV ADC12PDIV__64

+#define MSP430X_ADC1_DIV ADC12DIV_0

+#elif MSP430X_ADC1_DIV_CALC(96)

+#define MSP430X_ADC1_PDIV ADC12PDIV__32

+#define MSP430X_ADC1_DIV ADC12DIV_2

+#elif MSP430X_ADC1_DIV_CALC(128)

+#define MSP430X_ADC1_PDIV ADC12PDIV__64

+#define MSP430X_ADC1_DIV ADC12DIV_1

+#elif MSP430X_ADC1_DIV_CALC(160)

+#define MSP430X_ADC1_PDIV ADC12PDIV__32

+#define MSP430X_ADC1_DIV ADC12DIV_4

+#elif MSP430X_ADC1_DIV_CALC(192)

+#define MSP430X_ADC1_PDIV ADC12PDIV__64

+#define MSP430X_ADC1_DIV ADC12DIV_2

+#elif MSP430X_ADC1_DIV_CALC(224)

+#define MSP430X_ADC1_PDIV ADC12PDIV__32

+#define MSP430X_ADC1_DIV ADC12DIV_6

+#elif MSP430X_ADC1_DIV_CALC(256)

+#define MSP430X_ADC1_PDIV ADC12PDIV__64

+#define MSP430X_ADC1_DIV ADC12DIV_3

+#elif MSP430X_ADC1_DIV_CALC(320)

+#define MSP430X_ADC1_PDIV ADC12PDIV__64

+#define MSP430X_ADC1_DIV ADC12DIV_4

+#elif MSP430X_ADC1_DIV_CALC(384)

+#define MSP430X_ADC1_PDIV ADC12PDIV__64

+#define MSP430X_ADC1_DIV ADC12DIV_5

+#elif MSP430X_ADC1_DIV_CALC(448)

+#define MSP430X_ADC1_PDIV ADC12PDIV__64

+#define MSP430X_ADC1_DIV ADC12DIV_6

+#elif MSP430X_ADC1_DIV_CALC(512)

+#define MSP430X_ADC1_PDIV ADC12PDIV__64

+#define MSP430X_ADC1_DIV ADC12DIV_7

+#else

+#error "MSP430X_ADC1_FREQ not achievable with MSP430X_ADC1_CLK_SRC"

+#endif

+

+#endif /* MSP430X_ADC_USE_ADC1 */

+

+/*===========================================================================*/

+/* Driver data structures and types.                                         */

+/*===========================================================================*/

+

+/**

+ * @brief   ADC sample data type.

+ */

+#if !MSP430X_ADC_COMPACT_SAMPLES || defined(__DOXYGEN__)

+typedef uint16_t adcsample_t;

+#else

+typedef uint8_t adcsample_t;

+#endif

+

+/**

+ * @brief   Channels number in a conversion group.

+ */

+typedef uint8_t adc_channels_num_t;

+

+/**

+ * @brief   Possible ADC failure causes.

+ * @note    Error codes are architecture dependent and should not relied

+ *          upon.

+ */

+typedef enum {

+  ADC_ERR_UNKNOWN  = 0, /**< Unknown error has occurred */

+  ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition.    */

+  ADC_ERR_AWD      = 2  /**< Analog watchdog triggered. */

+} adcerror_t;

+

+/**

+ * @brief   Type of a structure representing an ADC driver.

+ */

+typedef struct ADCDriver ADCDriver;

+

+/**

+ * @brief   ADC notification callback type.

+ *

+ * @param[in] adcp      pointer to the @p ADCDriver object triggering the

+ *                      callback

+ * @param[in] buffer    pointer to the most recent samples data

+ * @param[in] n         number of buffer rows available starting from @p buffer

+ */

+typedef void (*adccallback_t)(ADCDriver * adcp, adcsample_t * buffer, size_t n);

+

+/**

+ * @brief   ADC error callback type.

+ *

+ * @param[in] adcp      pointer to the @p ADCDriver object triggering the

+ *                      callback

+ * @param[in] err       ADC error code

+ */

+typedef void (*adcerrorcallback_t)(ADCDriver * adcp, adcerror_t err);

+

+/**

+ * @brief MSP430X ADC register structure.

+ */

+typedef struct {

+  uint16_t ctl[4];

+  uint16_t lo;

+  uint16_t hi;

+  uint16_t ifgr[3];

+  uint16_t ier[3];

+  uint16_t iv;

+  uint16_t padding[3];

+  uint16_t mctl[32];

+  uint16_t mem[32];

+} msp430x_adc_reg_t;

+

+/**

+ * @brief MSP430X ADC calibration structure.

+ */

+typedef struct {

+  uint16_t CAL_ADC_GAIN_FACTOR;

+  uint16_t CAL_ADC_OFFSET;

+  uint16_t CAL_ADC_12T30;

+  uint16_t CAL_ADC_12T85;

+  uint16_t CAL_ADC_20T30;

+  uint16_t CAL_ADC_20T85;

+  uint16_t CAL_ADC_25T30;

+  uint16_t CAL_ADC_25T85;

+} msp430x_adc_cal_t;

+

+/**

+ * @brief MSP430X REF calibration structure.

+ */

+typedef struct {

+  uint16_t CAL_ADC_12VREF_FACTOR;

+  uint16_t CAL_ADC_20VREF_FACTOR;

+  uint16_t CAL_ADC_25VREF_FACTOR;

+} msp430x_ref_cal_t;

+

+/**

+ * @brief   Conversion group configuration structure.

+ * @details This implementation-dependent structure describes a conversion

+ *          operation.

+ * @note    The use of this configuration structure requires knowledge of

+ *          MSP430X ADC cell registers interface, please refer to the MSP430X

+ *          reference manual for details.

+ */

+typedef struct {

+  /**

+   * @brief   Enables the circular buffer mode for the group.

+   */

+  bool circular;

+  /**

+   * @brief   Number of the analog channels belonging to the conversion group.

+   */

+  adc_channels_num_t num_channels;

+  /**

+   * @brief   Callback function associated to the group or @p NULL.

+   */

+  adccallback_t end_cb;

+  /**

+   * @brief   Error callback or @p NULL.

+   */

+  adcerrorcallback_t error_cb;

+  /* End of the mandatory fields.*/

+  /**

+   * @brief   Sequence of analog channels belonging to the conversion group.

+   * @note    Only the first num_channels are valid.

+   */

+  uint8_t channels[32];

+  /**

+   * @brief   Sample resolution

+   */

+  MSP430XADCResolution res;

+  /**

+   * @brief   Sampling time in clock cycles

+   */

+  MSP430XADCSampleRates rate;

+  /**

+   * @brief   Voltage references to use

+   */

+  MSP430XADCReferences ref;

+  /**

+   * @brief   VREF source

+   */

+  MSP430XREFSources vref_src;

+} ADCConversionGroup;

+

+/**

+ * @brief   Driver configuration structure.

+ * @note    It could be empty on some architectures.

+ */

+typedef struct {

+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE || defined(__DOXYGEN__)

+  /**

+   * @brief The index of the DMA channel.

+   * @note  This may be >MSP430X_DMA_CHANNELS to indicate that exclusive DMA

+   *        is not used.

+   */

+  uint8_t dma_index;

+#endif

+} ADCConfig;

+

+/**

+ * @brief   Structure representing an ADC driver.

+ */

+struct ADCDriver {

+  /**

+   * @brief Driver state.

+   */

+  adcstate_t state;

+  /**

+   * @brief Current configuration data.

+   */

+  const ADCConfig * config;

+  /**

+   * @brief Current samples buffer pointer or @p NULL.

+   */

+  adcsample_t * samples;

+  /**

+   * @brief Current samples buffer depth or @p 0.

+   */

+  size_t depth;

+  /**

+   * @brief Current conversion group pointer or @p NULL.

+   */

+  const ADCConversionGroup * grpp;

+#if (ADC_USE_WAIT == TRUE) || defined(__DOXYGEN__)

+  /**

+   * @brief Waiting thread.

+   */

+  thread_reference_t thread;

+#endif

+#if (ADC_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__)

+  /**

+   * @brief Mutex protecting the peripheral.

+   */

+  mutex_t mutex;

+#endif

+#if defined(ADC_DRIVER_EXT_FIELDS)

+  ADC_DRIVER_EXT_FIELDS

+#endif

+  /* End of the mandatory fields.*/

+  /**

+   * @brief Base address of ADC12_B registers

+   */

+  msp430x_adc_reg_t * regs;

+  /**

+   * @brief DMA request structure

+   */

+  msp430x_dma_req_t req;

+  /**

+   * @brief ADC calibration structure from TLV

+   */

+  msp430x_adc_cal_t * adc_cal;

+  /**

+   * @brief REF calibration structure from TLV

+   */

+  msp430x_ref_cal_t * ref_cal;

+  /**

+   * @brief Count of times DMA callback has been called

+   */

+  uint8_t count;

+  /**

+   * @brief DMA stream

+   */

+  msp430x_dma_ch_t dma;

+};

+

+/*===========================================================================*/

+/* Driver macros.                                                            */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* External declarations.                                                    */

+/*===========================================================================*/

+

+#if (MSP430X_ADC_USE_ADC1 == TRUE) && !defined(__DOXYGEN__)

+extern ADCDriver ADCD1;

+#endif

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+void adc_lld_init(void);

+void adc_lld_start(ADCDriver * adcp);

+void adc_lld_stop(ADCDriver * adcp);

+void adc_lld_start_conversion(ADCDriver * adcp);

+void adc_lld_stop_conversion(ADCDriver * adcp);

+adcsample_t adcMSP430XAdjustResult(ADCConversionGroup * grpp,

+                                   adcsample_t sample);

+adcsample_t adcMSP430XAdjustTemp(ADCConversionGroup * grpp, adcsample_t sample);

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* HAL_USE_ADC == TRUE */

+

+#endif /* HAL_ADC_LLD_H */

+

+/** @} */

diff --git a/os/hal/ports/MSP430X/hal_dma_lld.c b/os/hal/ports/MSP430X/hal_dma_lld.c
index 43e1d6c..82bf39f 100644
--- a/os/hal/ports/MSP430X/hal_dma_lld.c
+++ b/os/hal/ports/MSP430X/hal_dma_lld.c
@@ -44,9 +44,8 @@ static msp430x_dma_ch_reg_t * const dma_channels =
     (msp430x_dma_ch_reg_t *)&DMA0CTL;

 

 static msp430x_dma_cb_t callbacks[MSP430X_DMA_CHANNELS];

-#if CH_CFG_USE_SEMAPHORES

-static semaphore_t dma_lock;

-#endif

+static threads_queue_t dma_queue;

+static unsigned int queue_length;

 

 /*===========================================================================*/

 /* Driver local functions.                                                   */

@@ -88,9 +87,9 @@ PORT_IRQ_HANDLER(DMA_VECTOR) {
   index = (DMAIV >> 1) - 1;

 

   if (index < MSP430X_DMA_CHANNELS) {

-#if CH_CFG_USE_SEMAPHORES

-    chSemSignalI(&dma_lock);

-#endif

+    osalSysLockFromISR();

+    osalThreadDequeueNextI(&dma_queue, MSG_OK);

+    osalSysUnlockFromISR();

 

     msp430x_dma_cb_t * cb = &callbacks[index];

 

@@ -113,9 +112,7 @@ PORT_IRQ_HANDLER(DMA_VECTOR) {
  * @init

  */

 void dmaInit(void) {

-#if CH_CFG_USE_SEMAPHORES

-  chSemObjectInit(&dma_lock, MSP430X_DMA_CHANNELS);

-#endif

+  osalThreadQueueObjectInit(&dma_queue);

 }

 

 /**

@@ -125,134 +122,124 @@ void dmaInit(void) {
  *          semaphores are enabled, the calling thread will sleep until a

  *          channel is available or the request times out. If semaphores are

  *          disabled, the calling thread will busy-wait instead of sleeping.

+ *          

+ *  @sclass

  */

-bool dmaRequest(msp430x_dma_req_t * request, systime_t timeout) {

-/* Check if a DMA channel is available */

-#if CH_CFG_USE_SEMAPHORES

-  msg_t semresult = chSemWaitTimeout(&dma_lock, timeout);

-  if (semresult != MSG_OK)

-    return true;

-#endif

-

-#if !(CH_CFG_USE_SEMAPHORES)

-  systime_t start = chVTGetSystemTimeX();

-

-  do {

-#endif

-    /* Grab the correct DMA channel to use */

-    int i = 0;

-    for (i = 0; i < MSP430X_DMA_CHANNELS; i++) {

-      if (!(dma_channels[i].ctl & DMAEN)) {

-        break;

-      }

-    }

-#if !(CH_CFG_USE_SEMAPHORES)

-    while (chVTTimeElapsedSinceX(start) < timeout)

-      ;

-#endif

-

-#if !(CH_CFG_USE_SEMAPHORES)

-    if (i == MSP430X_DMA_CHANNELS) {

-      return true;

+int dmaRequestS(msp430x_dma_req_t * request, systime_t timeout) {

+  

+  osalDbgCheckClassS();

+  

+  /* Check if a DMA channel is available */

+  if (queue_length >= MSP430X_DMA_CHANNELS) {

+    msg_t queueresult = osalThreadEnqueueTimeoutS(&dma_queue, timeout);

+    if (queueresult != MSG_OK)

+      return -1;

+  }

+

+  /* Grab the correct DMA channel to use */

+  int i = 0;

+  for (i = 0; i < MSP430X_DMA_CHANNELS; i++) {

+    if (!(dma_channels[i].ctl & DMAEN)) {

+      break;

     }

-#endif

+  }

+

+  /* Make the request */

+  init_request(request, i);

+  

+  return i;

+}

 

-    /* Make the request */

-    init_request(request, i);

+/**

+ * @brief   Acquires exclusive control of a DMA channel.

+ * @pre     The channel must not be already acquired or an error is returned.

+ * @note    If the channel is in use by the DMA engine, blocks until acquired.

+ * @post    This channel must be interacted with using only the functions

+ *          defined in this module.

+ *

+ * @param[out] channel    The channel handle. Must be pre-allocated.

+ * @param[in]  index      The index of the channel (< MSP430X_DMA_CHANNELS).

+ * @return                The operation status.

+ * @retval false          no error, channel acquired.

+ * @retval true           error, channel already acquired.

+ * 

+ * @iclass

+ */

+bool dmaAcquireI(msp430x_dma_ch_t * channel, uint8_t index) {

+  

+  osalDbgCheckClassI();

 

-    return false;

+  /* Is the channel already acquired? */

+  osalDbgAssert(index < MSP430X_DMA_CHANNELS, "invalid channel index");

+  if (dma_channels[index].ctl & DMADT_4) {

+    return true;

   }

 

-  /**

-   * @brief   Acquires exclusive control of a DMA channel.

-   * @pre     The channel must not be already acquired or an error is returned.

-   * @note    If the channel is in use by the DMA engine, blocks until acquired.

-   * @post    This channel must be interacted with using only the functions

-   *          defined in this module.

-   *

-   * @param[out] channel    The channel handle. Must be pre-allocated.

-   * @param[in]  index      The index of the channel (< MSP430X_DMA_CHANNELS).

-   * @return                The operation status.

-   * @retval false          no error, channel acquired.

-   * @retval true           error, channel already acquired.

-   */

-  bool dmaAcquire(msp430x_dma_ch_t * channel, uint8_t index) {

-    /* Acquire the channel in an idle mode */

-

-    /* Is the channel already acquired? */

-    osalDbgAssert(index < MSP430X_DMA_CHANNELS, "invalid channel index");

-    if (dma_channels[index].ctl & DMADT_4) {

-      return true;

-    }

+  /* Increment the DMA counter */

+  queue_length++;

 

-/* Increment the DMA counter */

-#if CH_CFG_USE_SEMAPHORES

-    msg_t semresult = chSemWait(&dma_lock);

-    if (semresult != MSG_OK)

-      return true;

-#endif

+  while (dma_channels[index].ctl & DMAEN)

+    ;

 

-    while (dma_channels[index].ctl & DMAEN)

-      ;

+  /* Acquire the channel in an idle mode */

+  dma_trigger_set(index, DMA_TRIGGER_MNEM(DMAREQ));

+  dma_channels[index].sz  = 0;

+  dma_channels[index].ctl = DMAEN | DMAABORT | DMADT_4;

 

-    dma_trigger_set(index, DMA_TRIGGER_MNEM(DMAREQ));

-    dma_channels[index].sz  = 0;

-    dma_channels[index].ctl = DMAEN | DMAABORT | DMADT_4;

+  channel->registers = dma_channels + index;

+  channel->index     = index;

+  channel->cb        = callbacks + index;

+  

+  return false;

+}

 

-    channel->registers = dma_channels + index;

-    channel->index     = index;

-    channel->cb        = callbacks + index;

+/**

+ * @brief   Initiates a DMA transfer operation using an acquired channel.

+ * @pre     The channel must have been acquired using @p dmaAcquire().

+ *

+ * @param[in] channel   pointer to a DMA channel from @p dmaAcquire().

+ * @param[in] request   pointer to a DMA request object.

+ */

+void dmaTransfer(msp430x_dma_ch_t * channel, msp430x_dma_req_t * request) {

 

-    return false;

-  }

+  dma_trigger_set(channel->index, request->trigger);

+  /**(channel->ctl) = request->trigger;*/

 

-  /**

-   * @brief   Initiates a DMA transfer operation using an acquired channel.

-   * @pre     The channel must have been acquired using @p dmaAcquire().

-   *

-   * @param[in] channel   pointer to a DMA channel from @p dmaAcquire().

-   * @param[in] request   pointer to a DMA request object.

-   */

-  void dmaTransfer(msp430x_dma_ch_t * channel, msp430x_dma_req_t * request) {

-

-    dma_trigger_set(channel->index, request->trigger);

-    /**(channel->ctl) = request->trigger;*/

-

-    channel->cb->callback = request->callback.callback;

-    channel->cb->args     = request->callback.args;

-

-    chSysLock();

-    channel->registers->ctl &= (~DMAEN);

-    channel->registers->sa  = (uintptr_t)request->source_addr;

-    channel->registers->da  = (uintptr_t)request->dest_addr;

-    channel->registers->sz  = request->size;

-    channel->registers->ctl = DMAIE | request->data_mode | request->addr_mode |

-                              request->transfer_mode | DMADT_4 | DMAEN |

-                              DMAREQ; /* repeated transfers */

-    chSysUnlock();

-  }

+  channel->cb->callback = request->callback.callback;

+  channel->cb->args     = request->callback.args;

 

-  /**

-   * @brief   Releases exclusive control of a DMA channel.

-   * @details The channel is released from control and returned to the DMA

-   * engine

-   *          pool. Trying to release an unallocated channel is an illegal

-   *          operation and is trapped if assertions are enabled.

-   * @pre     The channel must have been acquired using @p dmaAcquire().

-   * @post    The channel is returned to the DMA engine pool.

-   */

-  void dmaRelease(msp430x_dma_ch_t * channel) {

-

-    osalDbgCheck(channel != NULL);

-

-    /* Release the channel in an idle mode */

-    channel->registers->ctl = DMAABORT;

-

-/* release the DMA counter */

-#if CH_CFG_USE_SEMAPHORES

-    chSemSignal(&dma_lock);

-#endif

-  }

+  channel->registers->ctl &= (~DMAEN);

+  channel->registers->sa  = (uintptr_t)request->source_addr;

+  channel->registers->da  = (uintptr_t)request->dest_addr;

+  channel->registers->sz  = request->size;

+  channel->registers->ctl = DMAIE | request->data_mode | request->addr_mode |

+                            request->transfer_mode | DMADT_4 | DMAEN |

+                            DMAREQ; /* repeated transfers */

+}

+

+/**

+ * @brief   Releases exclusive control of a DMA channel.

+ * @details The channel is released from control and returned to the DMA

+ * engine

+ *          pool. Trying to release an unallocated channel is an illegal

+ *          operation and is trapped if assertions are enabled.

+ * @pre     The channel must have been acquired using @p dmaAcquire().

+ * @post    The channel is returned to the DMA engine pool.

+ */

+void dmaRelease(msp430x_dma_ch_t * channel) {

+  syssts_t sts;

+

+  sts = osalSysGetStatusAndLockX();

+  osalDbgCheck(channel != NULL);

+

+  /* Release the channel in an idle mode */

+  channel->registers->ctl = DMAABORT;

+

+  /* release the DMA counter */

+  osalThreadDequeueAllI(&dma_queue, MSG_RESET);

+  queue_length = 0;

+  osalSysRestoreStatusX(sts);

+}

 

 #endif /* HAL_USE_DMA == TRUE */

 

diff --git a/os/hal/ports/MSP430X/hal_dma_lld.h b/os/hal/ports/MSP430X/hal_dma_lld.h
index d1495d2..f558e78 100644
--- a/os/hal/ports/MSP430X/hal_dma_lld.h
+++ b/os/hal/ports/MSP430X/hal_dma_lld.h
@@ -159,8 +159,8 @@ typedef struct {
 extern "C" {

 #endif

 void dmaInit(void);

-bool dmaRequest(msp430x_dma_req_t * request, systime_t timeout);

-bool dmaAcquire(msp430x_dma_ch_t * channel, uint8_t index);

+int dmaRequestS(msp430x_dma_req_t * request, systime_t timeout);

+bool dmaAcquireI(msp430x_dma_ch_t * channel, uint8_t index);

 void dmaTransfer(msp430x_dma_ch_t * channel, msp430x_dma_req_t * request);

 void dmaRelease(msp430x_dma_ch_t * channel);

 

diff --git a/os/hal/ports/MSP430X/hal_lld.c b/os/hal/ports/MSP430X/hal_lld.c
index 872fe97..812a0cf 100644
--- a/os/hal/ports/MSP430X/hal_lld.c
+++ b/os/hal/ports/MSP430X/hal_lld.c
@@ -82,6 +82,10 @@ void hal_lld_init(void) {
   } while (SFRIFG1 & OFIFG);

   #endif

   CSCTL0_H = 0xFF; /* Lock clock system */

+  

+#if (HAL_USE_DMA == TRUE)

+  dmaInit();

+#endif

 }

 

 /** @} */

diff --git a/os/hal/ports/MSP430X/hal_lld.h b/os/hal/ports/MSP430X/hal_lld.h
index 9549453..62f07e9 100644
--- a/os/hal/ports/MSP430X/hal_lld.h
+++ b/os/hal/ports/MSP430X/hal_lld.h
@@ -25,6 +25,8 @@
 #ifndef _HAL_LLD_H_

 #define _HAL_LLD_H_

 

+#include "hal_dma_lld.h"

+

 /*===========================================================================*/

 /* Driver constants.                                                         */

 /*===========================================================================*/

diff --git a/os/hal/ports/MSP430X/hal_serial_lld.c b/os/hal/ports/MSP430X/hal_serial_lld.c
index 0d9aa1c..feb00ac 100644
--- a/os/hal/ports/MSP430X/hal_serial_lld.c
+++ b/os/hal/ports/MSP430X/hal_serial_lld.c
@@ -374,11 +374,11 @@ PORT_IRQ_HANDLER(USCI_A0_VECTOR) {
     if (oqIsEmptyI(&SD0.oqueue))

       chnAddFlagsI(&SD0, CHN_TRANSMISSION_END);

     UCA0IE &= ~UCTXCPTIE;

+    osalSysUnlockFromISR();

     break;

 

   default: /* other interrupts */

-    while (1)

-      ;

+    osalDbgAssert(false, "unhandled serial interrupt");

     break;

   }

 

@@ -432,11 +432,11 @@ PORT_IRQ_HANDLER(USCI_A1_VECTOR) {
     if (oqIsEmptyI(&SD1.oqueue))

       chnAddFlagsI(&SD1, CHN_TRANSMISSION_END);

     UCA1IE &= ~UCTXCPTIE;

+    osalSysUnlockFromISR();

     break;

 

   default: /* other interrupts */

-    while (1)

-      ;

+    osalDbgAssert(false, "unhandled serial interrupt");

     break;

   }

 

@@ -490,11 +490,11 @@ PORT_IRQ_HANDLER(USCI_A2_VECTOR) {
     if (oqIsEmptyI(&SD2.oqueue))

       chnAddFlagsI(&SD2, CHN_TRANSMISSION_END);

     UCA2IE &= ~UCTXCPTIE;

+    osalSysUnlockFromISR();

     break;

 

   default: /* other interrupts */

-    while (1)

-      ;

+    osalDbgAssert(false, "unhandled serial interrupt");

     break;

   }

 

@@ -548,11 +548,11 @@ PORT_IRQ_HANDLER(USCI_A3_VECTOR) {
     if (oqIsEmptyI(&SD3.oqueue))

       chnAddFlagsI(&SD3, CHN_TRANSMISSION_END);

     UCA3IE &= ~UCTXCPTIE;

+    osalSysUnlockFromISR();

     break;

 

   default: /* other interrupts */

-    while (1)

-      ;

+    osalDbgAssert(false, "unhandled serial interrupt");

     break;

   }

 

diff --git a/os/hal/ports/MSP430X/hal_spi_lld.c b/os/hal/ports/MSP430X/hal_spi_lld.c
index 70a357e..3a54b1e 100644
--- a/os/hal/ports/MSP430X/hal_spi_lld.c
+++ b/os/hal/ports/MSP430X/hal_spi_lld.c
@@ -104,21 +104,21 @@ static uint16_t dummyrx;
 static void init_transfer(SPIDriver * spip) {

 

 #if MSP430X_SPI_EXCLUSIVE_DMA == TRUE || defined(__DOXYGEN__)

-  if (spip->config->dmarx_index > MSP430X_DMA_CHANNELS) {

-    dmaRequest(&(spip->rx_req), TIME_INFINITE);

+  if (spip->config->dmarx_index >= MSP430X_DMA_CHANNELS) {

+    dmaRequestS(&(spip->rx_req), TIME_INFINITE);

   }

   else {

     dmaTransfer(&(spip->dmarx), &(spip->rx_req));

   }

-  if (spip->config->dmatx_index > MSP430X_DMA_CHANNELS) {

-    dmaRequest(&(spip->tx_req), TIME_INFINITE);

+  if (spip->config->dmatx_index >= MSP430X_DMA_CHANNELS) {

+    dmaRequestS(&(spip->tx_req), TIME_INFINITE);

   }

   else {

     dmaTransfer(&(spip->dmatx), &(spip->tx_req));

   }

 #else

-  dmaRequest(&(spip->rx_req), TIME_INFINITE);

-  dmaRequest(&(spip->tx_req), TIME_INFINITE);

+  dmaRequestS(&(spip->rx_req), TIME_INFINITE);

+  dmaRequestS(&(spip->tx_req), TIME_INFINITE);

 #endif

 

   *(spip->ifg) |= UCTXIFG;

@@ -325,11 +325,11 @@ void spi_lld_start(SPIDriver * spip) {
     /* Claim DMA streams here */

     bool b;

     if (spip->config->dmatx_index < MSP430X_DMA_CHANNELS) {

-      b = dmaAcquire(&(spip->dmatx), spip->config->dmatx_index);

+      b = dmaAcquireI(&(spip->dmatx), spip->config->dmatx_index);

       osalDbgAssert(!b, "stream already allocated");

     }

     if (spip->config->dmarx_index < MSP430X_DMA_CHANNELS) {

-      b = dmaAcquire(&(spip->dmarx), spip->config->dmarx_index);

+      b = dmaAcquireI(&(spip->dmarx), spip->config->dmarx_index);

       osalDbgAssert(!b, "stream already allocated");

     }

 #endif /* MSP430X_SPI_EXCLUSIVE_DMA */

@@ -388,10 +388,11 @@ void spi_lld_start(SPIDriver * spip) {
   spip->regs->ctlw0 = UCSWRST;

   spip->regs->brw   = brw;

   spip->regs->ctlw0 =

-      (spip->config->spi_mode << 14) | (spip->config->bit_order << 13) |

+      ((spip->config->spi_mode ^ 0x02) << 14) | (spip->config->bit_order << 13) |

       (spip->config->data_size << 12) | (UCMST) |

       ((spip->config->ss_line ? 0 : 2) << 9) | (UCSYNC) | (ssel) | (UCSTEM);

   *(spip->ifg) = 0;

+  spi_lld_unselect(spip);

 }

 

 /**

@@ -406,8 +407,12 @@ void spi_lld_stop(SPIDriver * spip) {
   if (spip->state == SPI_READY) {

 /* Disables the peripheral.*/

 #if MSP430X_SPI_EXCLUSIVE_DMA == TRUE

-    dmaRelease(&(spip->dmatx));

-    dmaRelease(&(spip->dmarx));

+    if (spip->config->dmatx_index < MSP430X_DMA_CHANNELS) {

+      dmaRelease(&(spip->dmatx));

+    }

+    if (spip->config->dmarx_index < MSP430X_DMA_CHANNELS) {

+      dmaRelease(&(spip->dmarx));

+    }

 #endif

     spip->regs->ctlw0 = UCSWRST;

   }

@@ -561,15 +566,12 @@ void spi_lld_receive(SPIDriver * spip, size_t n, void * rxbuf) {
  * @param[in] frame     the data frame to send over the SPI bus

  * @return              The received data frame from the SPI bus.

  */

-uint16_t spi_lld_polled_exchange(SPIDriver * spip, uint16_t frame) {

-

-  osalDbgAssert(!(frame & 0xFF00U), "16-bit transfers not supported");

+uint8_t spi_lld_polled_exchange(SPIDriver * spip, uint8_t frame) {

 

-  while (!(*(spip->ifg) & UCTXIFG))

-    ;

   spip->regs->txbuf = frame;

   while (!(*(spip->ifg) & UCRXIFG))

     ;

+  *(spip->ifg) &= ~(UCRXIFG | UCTXIFG);

   return spip->regs->rxbuf;

 }

 

diff --git a/os/hal/ports/MSP430X/hal_spi_lld.h b/os/hal/ports/MSP430X/hal_spi_lld.h
index ebf14c8..949a8a0 100644
--- a/os/hal/ports/MSP430X/hal_spi_lld.h
+++ b/os/hal/ports/MSP430X/hal_spi_lld.h
@@ -118,7 +118,7 @@
  * @note    This increases the size of the compiled executable somewhat.

  * @note    The default is @p FALSE.

  */

-#if !defined(MSP430X_SPI_EXCLUSIVE_DMA) | defined(__DOXYGEN__)

+#if !defined(MSP430X_SPI_EXCLUSIVE_DMA) || defined(__DOXYGEN__)

 #define MSP430X_SPI_EXCLUSIVE_DMA              FALSE

 #endif

 

@@ -630,7 +630,7 @@ extern "C" {
                         const void *txbuf, void *rxbuf);

   void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);

   void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);

-  uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);

+  uint8_t spi_lld_polled_exchange(SPIDriver *spip, uint8_t frame);

 #ifdef __cplusplus

 }

 #endif

diff --git a/os/hal/ports/MSP430X/platform.mk b/os/hal/ports/MSP430X/platform.mk
index 832814b..627a2f0 100644
--- a/os/hal/ports/MSP430X/platform.mk
+++ b/os/hal/ports/MSP430X/platform.mk
@@ -4,7 +4,8 @@ PLATFORMSRC = ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_lld.c \
               ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_serial_lld.c \

               ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_pal_lld.c \

               ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_dma_lld.c \

-              ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_spi_lld.c 

+              ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_spi_lld.c \

+              ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_adc_lld.c

 

 # Required include directories

 PLATFORMINC = ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X

diff --git a/os/hal/ports/NRF51/NRF51822/hal_gpt_lld.c b/os/hal/ports/NRF5/LLD/hal_gpt_lld.c
index f39470f..20dbcef 100644
--- a/os/hal/ports/NRF51/NRF51822/hal_gpt_lld.c
+++ b/os/hal/ports/NRF5/LLD/hal_gpt_lld.c
@@ -15,8 +15,8 @@
 */

 

 /**

- * @file    NRF51x22/gpt_lld.c

- * @brief   NRF51x22 GPT subsystem low level driver source.

+ * @file    NRF5/LLD/hal_gpt_lld.c

+ * @brief   NRF5 GPT subsystem low level driver source.

  *

  * @addtogroup GPT

  * @{

@@ -30,8 +30,8 @@
 /* Driver local definitions.                                                 */

 /*===========================================================================*/

 

-#define NRF51_TIMER_PRESCALER_NUM 10

-#define NRF51_TIMER_COMPARE_NUM   4

+#define NRF5_TIMER_PRESCALER_NUM 10

+#define NRF5_TIMER_COMPARE_NUM   4

 

 /*===========================================================================*/

 /* Driver exported variables.                                                */

@@ -41,7 +41,7 @@
  * @brief   GPTD1 driver identifier.

  * @note    The driver GPTD1 allocates the complex timer TIM1 when enabled.

  */

-#if NRF51_GPT_USE_TIMER0 || defined(__DOXYGEN__)

+#if NRF5_GPT_USE_TIMER0 || defined(__DOXYGEN__)

 GPTDriver GPTD1;

 #endif

 

@@ -49,7 +49,7 @@ GPTDriver GPTD1;
  * @brief   GPTD2 driver identifier.

  * @note    The driver GPTD2 allocates the timer TIM2 when enabled.

  */

-#if NRF51_GPT_USE_TIMER1 || defined(__DOXYGEN__)

+#if NRF5_GPT_USE_TIMER1 || defined(__DOXYGEN__)

 GPTDriver GPTD2;

 #endif

 

@@ -57,7 +57,7 @@ GPTDriver GPTD2;
  * @brief   GPTD3 driver identifier.

  * @note    The driver GPTD3 allocates the timer TIM3 when enabled.

  */

-#if NRF51_GPT_USE_TIMER2 || defined(__DOXYGEN__)

+#if NRF5_GPT_USE_TIMER2 || defined(__DOXYGEN__)

 GPTDriver GPTD3;

 #endif

 

@@ -73,19 +73,19 @@ static uint8_t prescaler(uint16_t freq)
 {

   uint8_t i;

   static const gptfreq_t frequencies[] = {

-    NRF51_GPT_FREQ_16MHZ,

-    NRF51_GPT_FREQ_8MHZ,

-    NRF51_GPT_FREQ_4MHZ,

-    NRF51_GPT_FREQ_2MHZ,

-    NRF51_GPT_FREQ_1MHZ,

-    NRF51_GPT_FREQ_500KHZ,

-    NRF51_GPT_FREQ_250KHZ,

-    NRF51_GPT_FREQ_125KHZ,

-    NRF51_GPT_FREQ_62500HZ,

-    NRF51_GPT_FREQ_31250HZ,

+    NRF5_GPT_FREQ_16MHZ,

+    NRF5_GPT_FREQ_8MHZ,

+    NRF5_GPT_FREQ_4MHZ,

+    NRF5_GPT_FREQ_2MHZ,

+    NRF5_GPT_FREQ_1MHZ,

+    NRF5_GPT_FREQ_500KHZ,

+    NRF5_GPT_FREQ_250KHZ,

+    NRF5_GPT_FREQ_125KHZ,

+    NRF5_GPT_FREQ_62500HZ,

+    NRF5_GPT_FREQ_31250HZ,

   };

 

-  for (i = 0; i < NRF51_TIMER_PRESCALER_NUM; i++)

+  for (i = 0; i < NRF5_TIMER_PRESCALER_NUM; i++)

     if (freq == frequencies[i])

       return i;

 

@@ -102,6 +102,9 @@ static uint8_t prescaler(uint16_t freq)
 static void gpt_lld_serve_interrupt(GPTDriver *gptp) {

 

   gptp->tim->EVENTS_COMPARE[gptp->cc_int] = 0;

+#if CORTEX_MODEL >= 4

+  (void)gptp->tim->EVENTS_COMPARE[gptp->cc_int];

+#endif

   if (gptp->state == GPT_ONESHOT)

     gptp->state = GPT_READY;                 /* Back in GPT_READY state.     */

   gptp->config->callback(gptp);

@@ -111,7 +114,7 @@ static void gpt_lld_serve_interrupt(GPTDriver *gptp) {
 /* Driver interrupt handlers.                                                */

 /*===========================================================================*/

 

-#if NRF51_GPT_USE_TIMER0

+#if NRF5_GPT_USE_TIMER0

 /**

  * @brief   TIMER0 interrupt handler.

  *

@@ -125,9 +128,9 @@ OSAL_IRQ_HANDLER(Vector60) {
 

   OSAL_IRQ_EPILOGUE();

 }

-#endif /* NRF51_GPT_USE_TIMER0 */

+#endif /* NRF5_GPT_USE_TIMER0 */

 

-#if NRF51_GPT_USE_TIMER1

+#if NRF5_GPT_USE_TIMER1

 /**

  * @brief   TIMER1 interrupt handler.

  *

@@ -141,9 +144,9 @@ OSAL_IRQ_HANDLER(Vector64) {
 

   OSAL_IRQ_EPILOGUE();

 }

-#endif /* NRF51_GPT_USE_TIMER1 */

+#endif /* NRF5_GPT_USE_TIMER1 */

 

-#if NRF51_GPT_USE_TIMER2

+#if NRF5_GPT_USE_TIMER2

 /**

  * @brief   TIMER2 interrupt handler.

  *

@@ -157,7 +160,7 @@ OSAL_IRQ_HANDLER(Vector68) {
 

   OSAL_IRQ_EPILOGUE();

 }

-#endif /* NRF51_GPT_USE_TIMER2 */

+#endif /* NRF5_GPT_USE_TIMER2 */

 

 /*===========================================================================*/

 /* Driver exported functions.                                                */

@@ -170,19 +173,19 @@ OSAL_IRQ_HANDLER(Vector68) {
  */

 void gpt_lld_init(void) {

 

-#if NRF51_GPT_USE_TIMER0

+#if NRF5_GPT_USE_TIMER0

   /* Driver initialization.*/

   GPTD1.tim = NRF_TIMER0;

   gptObjectInit(&GPTD1);

 #endif

 

-#if NRF51_GPT_USE_TIMER1

+#if NRF5_GPT_USE_TIMER1

   /* Driver initialization.*/

   GPTD2.tim = NRF_TIMER1;

   gptObjectInit(&GPTD2);

 #endif

 

-#if NRF51_GPT_USE_TIMER2

+#if NRF5_GPT_USE_TIMER2

   /* Driver initialization.*/

   GPTD3.tim = NRF_TIMER2;

   gptObjectInit(&GPTD3);

@@ -201,21 +204,21 @@ void gpt_lld_start(GPTDriver *gptp) {
   NRF_TIMER_Type *tim = gptp->tim;

 

   if (gptp->state == GPT_STOP) {

-    osalDbgAssert(gptp->cc_int < NRF51_TIMER_COMPARE_NUM,

+    osalDbgAssert(gptp->cc_int < NRF5_TIMER_COMPARE_NUM,

         "invalid capture/compare index");

 

     tim->INTENSET = TIMER_INTENSET_COMPARE0_Msk << gptp->cc_int;

-#if NRF51_GPT_USE_TIMER0

+#if NRF5_GPT_USE_TIMER0

     if (&GPTD1 == gptp)

-      nvicEnableVector(TIMER0_IRQn, NRF51_GPT_TIMER0_IRQ_PRIORITY);

+      nvicEnableVector(TIMER0_IRQn, NRF5_GPT_TIMER0_IRQ_PRIORITY);

 #endif

-#if NRF51_GPT_USE_TIMER1

+#if NRF5_GPT_USE_TIMER1

     if (&GPTD2 == gptp)

-      nvicEnableVector(TIMER1_IRQn, NRF51_GPT_TIMER1_IRQ_PRIORITY);

+      nvicEnableVector(TIMER1_IRQn, NRF5_GPT_TIMER1_IRQ_PRIORITY);

 #endif

-#if NRF51_GPT_USE_TIMER2

+#if NRF5_GPT_USE_TIMER2

     if (&GPTD3 == gptp)

-      nvicEnableVector(TIMER2_IRQn, NRF51_GPT_TIMER2_IRQ_PRIORITY);

+      nvicEnableVector(TIMER2_IRQn, NRF5_GPT_TIMER2_IRQ_PRIORITY);

 #endif

   }

 

@@ -235,7 +238,7 @@ void gpt_lld_start(GPTDriver *gptp) {
       tim->BITMODE = TIMER_BITMODE_BITMODE_16Bit << TIMER_BITMODE_BITMODE_Pos;

       break;

 

-#if NRF51_GPT_USE_TIMER0

+#if NRF5_GPT_USE_TIMER0

     case 24:

       tim->BITMODE = TIMER_BITMODE_BITMODE_24Bit << TIMER_BITMODE_BITMODE_Pos;

       break;

@@ -263,15 +266,15 @@ void gpt_lld_stop(GPTDriver *gptp) {
   if (gptp->state == GPT_READY) {

     gptp->tim->TASKS_SHUTDOWN = 1;

 

-#if NRF51_GPT_USE_TIMER0

+#if NRF5_GPT_USE_TIMER0

     if (&GPTD1 == gptp)

       nvicDisableVector(TIMER0_IRQn);

 #endif

-#if NRF51_GPT_USE_TIMER1

+#if NRF5_GPT_USE_TIMER1

     if (&GPTD2 == gptp)

       nvicDisableVector(TIMER1_IRQn);

 #endif

-#if NRF51_GPT_USE_TIMER2

+#if NRF5_GPT_USE_TIMER2

     if (&GPTD3 == gptp)

       nvicDisableVector(TIMER2_IRQn);

 #endif

diff --git a/os/hal/ports/NRF51/NRF51822/hal_gpt_lld.h b/os/hal/ports/NRF5/LLD/hal_gpt_lld.h
index 9b4cc9b..4173a3a 100644
--- a/os/hal/ports/NRF51/NRF51822/hal_gpt_lld.h
+++ b/os/hal/ports/NRF5/LLD/hal_gpt_lld.h
@@ -15,8 +15,8 @@
 */

 

 /**

- * @file    NRF51x22/gpt_lld.h

- * @brief   NRF51x22 GPT subsystem low level driver header.

+ * @file    NRF5/LLD/gpt_lld.h

+ * @brief   NRF5 GPT subsystem low level driver header.

  *

  * @addtogroup GPT

  * @{

@@ -44,8 +44,8 @@
  * @details If set to @p TRUE the support for GPTD1 is included.

  * @note    The default is @p TRUE.

  */

-#if !defined(NRF51_GPT_USE_TIMER0) || defined(__DOXYGEN__)

-#define NRF51_GPT_USE_TIMER0                  FALSE

+#if !defined(NRF5_GPT_USE_TIMER0) || defined(__DOXYGEN__)

+#define NRF5_GPT_USE_TIMER0                  FALSE

 #endif

 

 /**

@@ -53,8 +53,8 @@
  * @details If set to @p TRUE the support for GPTD2 is included.

  * @note    The default is @p TRUE.

  */

-#if !defined(NRF51_GPT_USE_TIMER1) || defined(__DOXYGEN__)

-#define NRF51_GPT_USE_TIMER1                  FALSE

+#if !defined(NRF5_GPT_USE_TIMER1) || defined(__DOXYGEN__)

+#define NRF5_GPT_USE_TIMER1                  FALSE

 #endif

 

 /**

@@ -62,29 +62,29 @@
  * @details If set to @p TRUE the support for GPTD3 is included.

  * @note    The default is @p TRUE.

  */

-#if !defined(NRF51_GPT_USE_TIMER2) || defined(__DOXYGEN__)

-#define NRF51_GPT_USE_TIMER2                  FALSE

+#if !defined(NRF5_GPT_USE_TIMER2) || defined(__DOXYGEN__)

+#define NRF5_GPT_USE_TIMER2                  FALSE

 #endif

 

 /**

  * @brief   GPTD1 interrupt priority level setting.

  */

-#if !defined(NRF51_GPT_TIMER0_IRQ_PRIORITY) || defined(__DOXYGEN__)

-#define NRF51_GPT_TIMER0_IRQ_PRIORITY         3

+#if !defined(NRF5_GPT_TIMER0_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define NRF5_GPT_TIMER0_IRQ_PRIORITY         3

 #endif

 

 /**

  * @brief   GPTD2 interrupt priority level setting.

  */

-#if !defined(NRF51_GPT_TIMER1_IRQ_PRIORITY) || defined(__DOXYGEN__)

-#define NRF51_GPT_TIMER1_IRQ_PRIORITY         3

+#if !defined(NRF5_GPT_TIMER1_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define NRF5_GPT_TIMER1_IRQ_PRIORITY         3

 #endif

 

 /**

  * @brief   GPTD3 interrupt priority level setting.

  */

-#if !defined(NRF51_GPT_TIMER2_IRQ_PRIORITY) || defined(__DOXYGEN__)

-#define NRF51_GPT_TIMER2_IRQ_PRIORITY         3

+#if !defined(NRF5_GPT_TIMER2_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define NRF5_GPT_TIMER2_IRQ_PRIORITY         3

 #endif

 /** @} */

 

@@ -92,23 +92,23 @@
 /* Derived constants and error checks.                                       */

 /*===========================================================================*/

 

-#if !NRF51_GPT_USE_TIMER0 && !NRF51_GPT_USE_TIMER1 &&                         \

-    !NRF51_GPT_USE_TIMER2

+#if !NRF5_GPT_USE_TIMER0 && !NRF5_GPT_USE_TIMER1 &&                         \

+    !NRF5_GPT_USE_TIMER2

 #error "GPT driver activated but no TIMER peripheral assigned"

 #endif

 

-#if NRF51_GPT_USE_TIMER0 &&                                                   \

-    !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_GPT_TIMER0_IRQ_PRIORITY)

+#if NRF5_GPT_USE_TIMER0 &&                                                   \

+    !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_GPT_TIMER0_IRQ_PRIORITY)

 #error "Invalid IRQ priority assigned to TIMER0"

 #endif

 

-#if NRF51_GPT_USE_TIMER1 &&                                                   \

-    !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_GPT_TIMER1_IRQ_PRIORITY)

+#if NRF5_GPT_USE_TIMER1 &&                                                   \

+    !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_GPT_TIMER1_IRQ_PRIORITY)

 #error "Invalid IRQ priority assigned to TIMER1"

 #endif

 

-#if NRF51_GPT_USE_TIMER2 &&                                                   \

-    !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_GPT_TIMER2_IRQ_PRIORITY)

+#if NRF5_GPT_USE_TIMER2 &&                                                   \

+    !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_GPT_TIMER2_IRQ_PRIORITY)

 #error "Invalid IRQ priority assigned to TIMER2"

 #endif

 

@@ -120,16 +120,16 @@
  * @brief   GPT frequency type.

  */

 typedef enum {

-  NRF51_GPT_FREQ_31250HZ = 31250,

-  NRF51_GPT_FREQ_62500HZ = 62500,

-  NRF51_GPT_FREQ_125KHZ = 125000,

-  NRF51_GPT_FREQ_250KHZ = 250000,

-  NRF51_GPT_FREQ_500KHZ = 500000,

-  NRF51_GPT_FREQ_1MHZ = 1000000,

-  NRF51_GPT_FREQ_2MHZ = 2000000,

-  NRF51_GPT_FREQ_4MHZ = 4000000,

-  NRF51_GPT_FREQ_8MHZ = 8000000,

-  NRF51_GPT_FREQ_16MHZ = 16000000,

+  NRF5_GPT_FREQ_31250HZ = 31250,

+  NRF5_GPT_FREQ_62500HZ = 62500,

+  NRF5_GPT_FREQ_125KHZ = 125000,

+  NRF5_GPT_FREQ_250KHZ = 250000,

+  NRF5_GPT_FREQ_500KHZ = 500000,

+  NRF5_GPT_FREQ_1MHZ = 1000000,

+  NRF5_GPT_FREQ_2MHZ = 2000000,

+  NRF5_GPT_FREQ_4MHZ = 4000000,

+  NRF5_GPT_FREQ_8MHZ = 8000000,

+  NRF5_GPT_FREQ_16MHZ = 16000000,

 } gptfreq_t;

 

 /**

@@ -231,15 +231,15 @@ struct GPTDriver {
 /* External declarations.                                                    */

 /*===========================================================================*/

 

-#if NRF51_GPT_USE_TIMER0 && !defined(__DOXYGEN__)

+#if NRF5_GPT_USE_TIMER0 && !defined(__DOXYGEN__)

 extern GPTDriver GPTD1;

 #endif

 

-#if NRF51_GPT_USE_TIMER1 && !defined(__DOXYGEN__)

+#if NRF5_GPT_USE_TIMER1 && !defined(__DOXYGEN__)

 extern GPTDriver GPTD2;

 #endif

 

-#if NRF51_GPT_USE_TIMER2 && !defined(__DOXYGEN__)

+#if NRF5_GPT_USE_TIMER2 && !defined(__DOXYGEN__)

 extern GPTDriver GPTD3;

 #endif

 

diff --git a/os/hal/ports/NRF51/NRF51822/hal_i2c_lld.c b/os/hal/ports/NRF5/LLD/hal_i2c_lld.c
index 611a004..fefca0c 100644
--- a/os/hal/ports/NRF51/NRF51822/hal_i2c_lld.c
+++ b/os/hal/ports/NRF5/LLD/hal_i2c_lld.c
@@ -15,8 +15,8 @@
 */

 

 /**

- * @file    NRF51822/i2c_lld.c

- * @brief   NRF51822 I2C subsystem low level driver source.

+ * @file    NRF5/LLD/hal_i2c_lld.c

+ * @brief   NRF5 I2C subsystem low level driver source.

  *

  * @addtogroup I2C

  * @{

@@ -24,7 +24,7 @@
 

 #include "osal.h"

 #include "hal.h"

-#include "nrf51_delay.h"

+#include "nrf_delay.h"

 

 #if HAL_USE_I2C || defined(__DOXYGEN__)

 

@@ -33,10 +33,10 @@
 /*===========================================================================*/

 

 /* These macros are needed to see if the slave is stuck and we as master send dummy clock cycles to end its wait */

-#define I2C_HIGH(p)   do { NRF_GPIO->OUTSET = (1UL << (p)); } while(0)   /*!< Pulls I2C line high */

-#define I2C_LOW(p)    do { NRF_GPIO->OUTCLR = (1UL << (p)); } while(0)   /*!< Pulls I2C line low  */

-#define I2C_INPUT(p)  do { NRF_GPIO->DIRCLR = (1UL << (p)); } while(0)   /*!< Configures I2C pin as input  */

-#define I2C_OUTPUT(p) do { NRF_GPIO->DIRSET = (1UL << (p)); } while(0)   /*!< Configures I2C pin as output */

+#define I2C_HIGH(p)   do { IOPORT1->OUTSET = (1UL << (p)); } while(0)   /*!< Pulls I2C line high */

+#define I2C_LOW(p)    do { IOPORT1->OUTCLR = (1UL << (p)); } while(0)   /*!< Pulls I2C line low  */

+#define I2C_INPUT(p)  do { IOPORT1->DIRCLR = (1UL << (p)); } while(0)   /*!< Configures I2C pin as input  */

+#define I2C_OUTPUT(p) do { IOPORT1->DIRSET = (1UL << (p)); } while(0)   /*!< Configures I2C pin as output */

 

 #define I2C_PIN_CNF \

       ((GPIO_PIN_CNF_SENSE_Disabled  << GPIO_PIN_CNF_SENSE_Pos) \

@@ -52,12 +52,12 @@
       | (GPIO_PIN_CNF_INPUT_Connect  << GPIO_PIN_CNF_INPUT_Pos) \

       | (GPIO_PIN_CNF_DIR_Output     << GPIO_PIN_CNF_DIR_Pos))

 

-#if NRF51_I2C_USE_I2C0

+#if NRF5_I2C_USE_I2C0

 #define I2C_IRQ_NUM     SPI0_TWI0_IRQn

-#define I2C_IRQ_PRI     NRF51_I2C_I2C0_IRQ_PRIORITY

-#elif NRF51_I2C_USE_I2C1

+#define I2C_IRQ_PRI     NRF5_I2C_I2C0_IRQ_PRIORITY

+#elif NRF5_I2C_USE_I2C1

 #define I2C_IRQ_NUM     SPI1_TWI1_IRQn

-#define I2C_IRQ_PRI     NRF51_I2C_I2C1_IRQ_PRIORITY

+#define I2C_IRQ_PRI     NRF5_I2C_I2C1_IRQ_PRIORITY

 #endif

 

 /*===========================================================================*/

@@ -67,14 +67,14 @@
 /**

  * @brief   I2C0 driver identifier.

  */

-#if NRF51_I2C_USE_I2C0 || defined(__DOXYGEN__)

+#if NRF5_I2C_USE_I2C0 || defined(__DOXYGEN__)

 I2CDriver I2CD1;

 #endif

 

 /**

  * @brief   I2C1 driver identifier.

  */

-#if NRF51_I2C_USE_I2C1 || defined(__DOXYGEN__)

+#if NRF5_I2C_USE_I2C1 || defined(__DOXYGEN__)

 I2CDriver I2CD2;

 #endif

 

@@ -102,14 +102,14 @@ static void i2c_clear_bus(I2CDriver *i2cp)
   const I2CConfig *cfg = i2cp->config;

   int i;

 

-  NRF_GPIO->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF;

-  NRF_GPIO->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF;

+  IOPORT1->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF;

+  IOPORT1->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF;

 

   I2C_HIGH(cfg->sda_pad);

   I2C_HIGH(cfg->scl_pad);

 

-  NRF_GPIO->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF_CLR;

-  NRF_GPIO->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF_CLR;

+  IOPORT1->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF_CLR;

+  IOPORT1->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF_CLR;

 

   nrf_delay_us(4);

 

@@ -165,7 +165,10 @@ static void serve_interrupt(I2CDriver *i2cp) {
   if(i2c->EVENTS_TXDSENT) {

 

     i2c->EVENTS_TXDSENT = 0;

-

+#if CORTEX_MODEL >= 4

+    (void)i2c->EVENTS_TXDSENT;

+#endif

+    

     if(--i2cp->txbytes) {

 

       i2c->TXD = *i2cp->txptr++;

@@ -182,6 +185,10 @@ static void serve_interrupt(I2CDriver *i2cp) {
   if(i2c->EVENTS_RXDREADY) {

 

     i2c->EVENTS_RXDREADY = 0;

+#if CORTEX_MODEL >= 4

+    (void)i2c->EVENTS_RXDREADY;

+#endif

+    

     *i2cp->rxptr++ = i2c->RXD;

 

     if(--i2cp->rxbytes) {

@@ -194,7 +201,9 @@ static void serve_interrupt(I2CDriver *i2cp) {
 

     uint32_t err = i2c->ERRORSRC;

     i2c->EVENTS_ERROR = 0;

-

+#if CORTEX_MODEL >= 4

+    (void)i2c->EVENTS_ERROR;

+#endif

     if (err & TWI_ERRORSRC_OVERRUN_Msk)

       i2cp->errors |= I2C_OVERRUN;

     if (err & (TWI_ERRORSRC_ANACK_Msk | TWI_ERRORSRC_DNACK_Msk))

@@ -206,6 +215,9 @@ static void serve_interrupt(I2CDriver *i2cp) {
 

     stop_count++;

     i2c->EVENTS_STOPPED = 0;

+#if CORTEX_MODEL >= 4

+    (void)i2c->EVENTS_STOPPED;

+#endif

     _i2c_wakeup_isr(i2cp);

   }

 }

@@ -214,7 +226,7 @@ static void serve_interrupt(I2CDriver *i2cp) {
 /* Driver interrupt handlers.                                                */

 /*===========================================================================*/

 

-#if NRF51_I2C_USE_I2C0 || defined(__DOXYGEN__)

+#if NRF5_I2C_USE_I2C0 || defined(__DOXYGEN__)

 

 OSAL_IRQ_HANDLER(Vector4C) {

 

@@ -225,7 +237,7 @@ OSAL_IRQ_HANDLER(Vector4C) {
 

 #endif

 

-#if NRF51_I2C_USE_I2C1 || defined(__DOXYGEN__)

+#if NRF5_I2C_USE_I2C1 || defined(__DOXYGEN__)

 

 OSAL_IRQ_HANDLER(Vector50) {

 

@@ -247,13 +259,13 @@ OSAL_IRQ_HANDLER(Vector50) {
  */

 void i2c_lld_init(void) {

 

-#if NRF51_I2C_USE_I2C0

+#if NRF5_I2C_USE_I2C0

   i2cObjectInit(&I2CD1);

   I2CD1.thread = NULL;

   I2CD1.i2c = NRF_TWI0;

 #endif

 

-#if NRF51_I2C_USE_I2C1

+#if NRF5_I2C_USE_I2C1

   i2cObjectInit(&I2CD2);

   I2CD2.thread = NULL;

   I2CD2.i2c = NRF_TWI1;

@@ -278,14 +290,23 @@ void i2c_lld_start(I2CDriver *i2cp) {
 

   i2c_clear_bus(i2cp);

 

-  NRF_GPIO->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF;

-  NRF_GPIO->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF;

+  IOPORT1->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF;

+  IOPORT1->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF;

 

   i2c->EVENTS_RXDREADY = 0;

   i2c->EVENTS_TXDSENT = 0;

+#if CORTEX_MODEL >= 4

+  (void)i2c->EVENTS_RXDREADY;

+  (void)i2c->EVENTS_TXDSENT;

+#endif

+#if NRF_SERIES == 51

   i2c->PSELSCL = cfg->scl_pad;

   i2c->PSELSDA = cfg->sda_pad;

-

+#else

+  i2c->PSEL.SCL = cfg->scl_pad;

+  i2c->PSEL.SDA = cfg->sda_pad;

+#endif

+  

   switch (cfg->clock) {

     case 100000:

       i2c->FREQUENCY = TWI_FREQUENCY_FREQUENCY_K100 << TWI_FREQUENCY_FREQUENCY_Pos;

@@ -330,8 +351,8 @@ void i2c_lld_stop(I2CDriver *i2cp) {
 

     nvicDisableVector(I2C_IRQ_NUM);

 

-    NRF_GPIO->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF_CLR;

-    NRF_GPIO->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF_CLR;

+    IOPORT1->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF_CLR;

+    IOPORT1->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF_CLR;

   }

 }

 

diff --git a/os/hal/ports/NRF51/NRF51822/hal_i2c_lld.h b/os/hal/ports/NRF5/LLD/hal_i2c_lld.h
index e2c3d07..578d69b 100644
--- a/os/hal/ports/NRF51/NRF51822/hal_i2c_lld.h
+++ b/os/hal/ports/NRF5/LLD/hal_i2c_lld.h
@@ -15,8 +15,8 @@
 */

 

 /**

- * @file    NRF51822/i2c_lld.h

- * @brief   NRF51822 I2C subsystem low level driver header.

+ * @file    NRF5/LLD/hal_i2c_lld.h

+ * @brief   NRF5 I2C subsystem low level driver header.

  *

  * @addtogroup I2C

  * @{

@@ -49,8 +49,8 @@
  * @details If set to @p TRUE the support for I2C0 is included.

  * @note    The default is @p FALSE.

  */

-#if !defined(NRF51_I2C_USE_I2C0) || defined(__DOXYGEN__)

-#define NRF51_I2C_USE_I2C0               FALSE

+#if !defined(NRF5_I2C_USE_I2C0) || defined(__DOXYGEN__)

+#define NRF5_I2C_USE_I2C0               FALSE

 #endif

 

 /**

@@ -58,22 +58,22 @@
  * @details If set to @p TRUE the support for I2C1 is included.

  * @note    The default is @p FALSE.

  */

-#if !defined(NRF51_I2C_USE_I2C1) || defined(__DOXYGEN__)

-#define NRF51_I2C_USE_I2C1               FALSE

+#if !defined(NRF5_I2C_USE_I2C1) || defined(__DOXYGEN__)

+#define NRF5_I2C_USE_I2C1               FALSE

 #endif

 

 /**

  * @brief   I2C0 interrupt priority level setting.

  */

-#if !defined(NRF51_I2C_I2C0_IRQ_PRIORITY) || defined(__DOXYGEN__)

-#define NRF51_I2C_I2C0_IRQ_PRIORITY         3

+#if !defined(NRF5_I2C_I2C0_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define NRF5_I2C_I2C0_IRQ_PRIORITY         3

 #endif

 

 /**

  * @brief   I2C1 interrupt priority level setting.

  */

-#if !defined(NRF51_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)

-#define NRF51_I2C_I2C1_IRQ_PRIORITY         3

+#if !defined(NRF5_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define NRF5_I2C_I2C1_IRQ_PRIORITY         3

 #endif

 /** @} */

 

@@ -81,13 +81,13 @@
 /* Derived constants and error checks.                                       */

 /*===========================================================================*/

 

-#if NRF51_I2C_USE_I2C0 &&						    \

-    !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_I2C_I2C0_IRQ_PRIORITY)

+#if NRF5_I2C_USE_I2C0 &&						    \

+    !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_I2C_I2C0_IRQ_PRIORITY)

 #error "Invalid IRQ priority assigned to I2C0"

 #endif

 

-#if NRF51_I2C_USE_I2C1 &&						    \

-    !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_I2C_I2C1_IRQ_PRIORITY)

+#if NRF5_I2C_USE_I2C1 &&						    \

+    !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_I2C_I2C1_IRQ_PRIORITY)

 #error "Invalid IRQ priority assigned to I2C1"

 #endif

 

@@ -198,11 +198,11 @@ struct I2CDriver {
 

 #if !defined(__DOXYGEN__)

 

-#if NRF51_I2C_USE_I2C0

+#if NRF5_I2C_USE_I2C0

 extern I2CDriver I2CD1;

 #endif

 

-#if NRF51_I2C_USE_I2C1

+#if NRF5_I2C_USE_I2C1

 extern I2CDriver I2CD2;

 #endif

 

diff --git a/os/hal/ports/NRF51/NRF51822/hal_pal_lld.c b/os/hal/ports/NRF5/LLD/hal_pal_lld.c
index 69fc9fe..21e4b0b 100644
--- a/os/hal/ports/NRF51/NRF51822/hal_pal_lld.c
+++ b/os/hal/ports/NRF5/LLD/hal_pal_lld.c
@@ -15,8 +15,8 @@
 */

 

 /**

- * @file    pal_lld.c

- * @brief   NRF51822 PAL subsystem low level driver source.

+ * @file    NRF5/LLD/hal_pal_lld.c

+ * @brief   NRF5 PAL subsystem low level driver source.

  *

  * @addtogroup PAL

  * @{

@@ -46,12 +46,12 @@
 void _pal_lld_setpadmode(ioportid_t port, uint8_t pad, iomode_t mode)

 {

   (void)port;

-  osalDbgAssert(pad <= 31, "pal_lld_setpadmode() - invalid pad");

+  osalDbgAssert(pad < PAL_IOPORTS_WIDTH, "pal_lld_setpadmode() - invalid pad");

 

   switch (mode) {

   case PAL_MODE_RESET:

   case PAL_MODE_UNCONNECTED:

-    NRF_GPIO->PIN_CNF[pad] =

+    IOPORT1->PIN_CNF[pad] =

       (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) |

       (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) |

       (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) |

@@ -60,7 +60,7 @@ void _pal_lld_setpadmode(ioportid_t port, uint8_t pad, iomode_t mode)
     break;

   case PAL_MODE_INPUT:

   case PAL_MODE_INPUT_ANALOG:

-    NRF_GPIO->PIN_CNF[pad] =

+    IOPORT1->PIN_CNF[pad] =

       (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) |

       (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) |

       (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) |

@@ -68,7 +68,7 @@ void _pal_lld_setpadmode(ioportid_t port, uint8_t pad, iomode_t mode)
       (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);

     break;

   case PAL_MODE_INPUT_PULLUP:

-    NRF_GPIO->PIN_CNF[pad] =

+    IOPORT1->PIN_CNF[pad] =

       (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) |

       (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) |

       (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) |

@@ -76,7 +76,7 @@ void _pal_lld_setpadmode(ioportid_t port, uint8_t pad, iomode_t mode)
       (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);

     break;

   case PAL_MODE_INPUT_PULLDOWN:

-    NRF_GPIO->PIN_CNF[pad] =

+    IOPORT1->PIN_CNF[pad] =

       (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) |

       (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) |

       (GPIO_PIN_CNF_PULL_Pulldown << GPIO_PIN_CNF_PULL_Pos) |

@@ -84,7 +84,7 @@ void _pal_lld_setpadmode(ioportid_t port, uint8_t pad, iomode_t mode)
       (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);

     break;

   case PAL_MODE_OUTPUT_PUSHPULL:

-    NRF_GPIO->PIN_CNF[pad] =

+    IOPORT1->PIN_CNF[pad] =

       (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) |

       (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) |

       (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) |

@@ -92,7 +92,7 @@ void _pal_lld_setpadmode(ioportid_t port, uint8_t pad, iomode_t mode)
       (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);

     break;

   case PAL_MODE_OUTPUT_OPENDRAIN:

-    NRF_GPIO->PIN_CNF[pad] =

+    IOPORT1->PIN_CNF[pad] =

       (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) |

       (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) |

       (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) |

@@ -114,9 +114,9 @@ void _pal_lld_setpadmode(ioportid_t port, uint8_t pad, iomode_t mode)
 /*===========================================================================*/

 

 /**

- * @brief   NRF51 I/O ports configuration.

+ * @brief   NRF5 I/O ports configuration.

  *

- * @param[in] config    the NRF51 ports configuration

+ * @param[in] config    the NRF5 ports configuration

  *

  * @notapi

  */

diff --git a/os/hal/ports/NRF51/NRF51822/hal_pal_lld.h b/os/hal/ports/NRF5/LLD/hal_pal_lld.h
index 5032916..745afd3 100644
--- a/os/hal/ports/NRF51/NRF51822/hal_pal_lld.h
+++ b/os/hal/ports/NRF5/LLD/hal_pal_lld.h
@@ -15,8 +15,8 @@
 */

 

 /**

- * @file    pal_lld.h

- * @brief   NRF51822 PAL subsystem low level driver header.

+ * @file    NRF5/LLD/hal_pal_lld.h

+ * @brief   NRF5 PAL subsystem low level driver header.

  *

  * @addtogroup PAL

  * @{

@@ -128,7 +128,11 @@ typedef NRF_GPIO_Type *ioportid_t;
  * @details Low level drivers can define multiple ports, it is suggested to

  *          use this naming convention.

  */

+#if   NRF_SERIES == 51

 #define IOPORT1         NRF_GPIO

+#else

+#define IOPORT1         NRF_P0

+#endif

 

 /*===========================================================================*/

 /* Implementation, some of the following macros could be implemented as      */

@@ -152,7 +156,7 @@ typedef NRF_GPIO_Type *ioportid_t;
  *

  * @notapi

  */

-#define pal_lld_readport(port) (NRF_GPIO->IN)

+#define pal_lld_readport(port) (IOPORT1->IN)

 

 /**

  * @brief   Reads the output latch.

@@ -164,7 +168,7 @@ typedef NRF_GPIO_Type *ioportid_t;
  *

  * @notapi

  */

-#define pal_lld_readlatch(port) (NRF_GPIO->OUT)

+#define pal_lld_readlatch(port) (IOPORT1->OUT)

 

 /**

  * @brief   Writes a bits mask on a I/O port.

@@ -174,7 +178,7 @@ typedef NRF_GPIO_Type *ioportid_t;
  *

  * @notapi

  */

-#define pal_lld_writeport(port, bits) (NRF_GPIO->OUT = (bits))

+#define pal_lld_writeport(port, bits) (IOPORT1->OUT = (bits))

 

 /**

  * @brief   Sets a bits mask on a I/O port.

@@ -187,7 +191,7 @@ typedef NRF_GPIO_Type *ioportid_t;
  *

  * @notapi

  */

-#define pal_lld_setport(port, bits) (NRF_GPIO->OUTSET = (bits))

+#define pal_lld_setport(port, bits) (IOPORT1->OUTSET = (bits))

 

 

 /**

@@ -201,7 +205,7 @@ typedef NRF_GPIO_Type *ioportid_t;
  *

  * @notapi

  */

-#define pal_lld_clearport(port, bits) (NRF_GPIO->OUTCLR = (bits))

+#define pal_lld_clearport(port, bits) (IOPORT1->OUTCLR = (bits))

 

 /**

  * @brief   Pads group mode setup.

@@ -234,7 +238,7 @@ typedef NRF_GPIO_Type *ioportid_t;
  * @notapi

  */

 #define pal_lld_readpad(port, pad)                                          \

-  ((NRF_GPIO->IN & ((uint32_t) 1 << pad)) ? PAL_HIGH : PAL_LOW)

+  ((IOPORT1->IN & ((uint32_t) 1 << pad)) ? PAL_HIGH : PAL_LOW)

 

 /**

  * @brief   Writes a logical state on an output pad.

@@ -255,9 +259,9 @@ typedef NRF_GPIO_Type *ioportid_t;
   do {                                                                      \

     (void)port;                                                             \

     if (bit == PAL_HIGH)                                                    \

-      NRF_GPIO->OUTSET = ((uint32_t) 1 << pad);                             \

+      IOPORT1->OUTSET = ((uint32_t) 1 << pad);                              \

     else                                                                    \

-      NRF_GPIO->OUTCLR = ((uint32_t) 1 << pad);                             \

+      IOPORT1->OUTCLR = ((uint32_t) 1 << pad);                              \

   } while (false)

 

 /**

@@ -271,7 +275,7 @@ typedef NRF_GPIO_Type *ioportid_t;
  *

  * @notapi

  */

-#define pal_lld_setpad(port, pad) (NRF_GPIO->OUTSET = (uint32_t) 1 << (pad))

+#define pal_lld_setpad(port, pad) (IOPORT1->OUTSET = (uint32_t) 1 << (pad))

 

 /**

  * @brief   Clears a pad logical state to @p PAL_LOW.

@@ -284,7 +288,7 @@ typedef NRF_GPIO_Type *ioportid_t;
  *

  * @notapi

  */

-#define pal_lld_clearpad(port, pad) (NRF_GPIO->OUTCLR = (uint32_t) 1 << (pad))

+#define pal_lld_clearpad(port, pad) (IOPORT1->OUTCLR = (uint32_t) 1 << (pad))

 

 /**

  * @brief   Toggles a pad logical state.

@@ -299,11 +303,11 @@ typedef NRF_GPIO_Type *ioportid_t;
  */

 #define pal_lld_togglepad(port, pad)                                        \

   do {                                                                      \

-    uint8_t bit = (NRF_GPIO->IN >> (pad)) & 1;                              \

+    uint8_t bit = (IOPORT1->OUT >> (pad)) & 1;                              \

     if (bit)                                                                \

-      NRF_GPIO->OUTCLR = 1 << (pad);                                        \

+      IOPORT1->OUTCLR = 1 << (pad);                                         \

     else                                                                    \

-      NRF_GPIO->OUTSET = 1 << (pad);                                        \

+      IOPORT1->OUTSET = 1 << (pad);                                         \

   } while (0)

 

 /**

diff --git a/os/hal/ports/NRF5/LLD/hal_qei_lld.c b/os/hal/ports/NRF5/LLD/hal_qei_lld.c
new file mode 100644
index 0000000..d3b99cd
--- /dev/null
+++ b/os/hal/ports/NRF5/LLD/hal_qei_lld.c
@@ -0,0 +1,300 @@
+/*

+    ChibiOS - Copyright (C) 2016..2016 Stéphane D'Alu

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    NRF51/hal_qei_lld.c

+ * @brief   NRF51 QEI subsystem low level driver.

+ *

+ * @addtogroup QEI

+ * @{

+ */

+

+#include "hal.h"

+

+#if (HAL_USE_QEI == TRUE) || defined(__DOXYGEN__)

+

+

+/*===========================================================================*/

+/* Driver local definitions.                                                 */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver exported variables.                                                */

+/*===========================================================================*/

+

+/**

+ * @brief   QEID1 driver identifier.

+ */

+#if NRF5_QEI_USE_QDEC0 || defined(__DOXYGEN__)

+QEIDriver QEID1;

+#endif

+

+

+/*===========================================================================*/

+/* Driver local variables and types.                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver local functions.                                                   */

+/*===========================================================================*/

+

+/**

+ * @brief   Common IRQ handler.

+ *

+ * @param[in] qeip         pointer to an QEIDriver

+ */

+static void serve_interrupt(QEIDriver *qeip) {

+  NRF_QDEC_Type *qdec = qeip->qdec;

+

+#if NRF5_QEI_USE_ACC_OVERFLOWED_CB == TRUE

+  /* Accumulator overflowed

+   */

+  if (qdec->EVENTS_ACCOF) {

+    qdec->EVENTS_ACCOF = 0;

+#if CORTEX_MODEL >= 4

+    (void)qdec->EVENTS_ACCOF;

+#endif

+    

+    qeip->overflowed++;

+    if (qeip->config->overflowed_cb)

+      qeip->config->overflowed_cb(qeip);

+  }

+#endif

+  

+  /* Report ready

+   */

+  if (qdec->EVENTS_REPORTRDY) {

+    qdec->EVENTS_REPORTRDY = 0;

+#if CORTEX_MODEL >= 4

+    (void)qdec->EVENTS_REPORTRDY;

+#endif

+    

+    /* Read (and clear counters due to shortcut) */

+    int16_t  acc    = ( int16_t)qdec->ACCREAD;

+    uint16_t accdbl = (uint16_t)qdec->ACCDBLREAD;

+

+    /* Inverse direction if requested */

+    if (qeip->config->dirinv)

+      acc = -acc; // acc is [-1024..+1023], its okay on int16_t

+

+    /* Adjust counter */

+    qeiAdjustI(qeip, acc);

+  }

+}

+

+/*===========================================================================*/

+/* Driver interrupt handlers.                                                */

+/*===========================================================================*/

+

+#if NRF5_QEI_USE_QDEC0 == TRUE

+/**

+ * @brief   Quadrature decoder vector (QDEC)

+ *

+ * @isr

+ */

+OSAL_IRQ_HANDLER(Vector88) {

+

+  OSAL_IRQ_PROLOGUE();

+  serve_interrupt(&QEID1);

+  OSAL_IRQ_EPILOGUE();

+}

+#endif

+

+/*===========================================================================*/

+/* Driver exported functions.                                                */

+/*===========================================================================*/

+

+/**

+ * @brief   Low level QEI driver initialization.

+ *

+ * @notapi

+ */

+void qei_lld_init(void) {

+

+#if NRF5_QEI_USE_QDEC0 == TRUE

+  /* Driver initialization.*/

+  qeiObjectInit(&QEID1);

+  QEID1.qdec = NRF_QDEC; 

+#endif

+}

+

+/**

+ * @brief   Configures and activates the QEI peripheral.

+ *

+ * @param[in] qeip      pointer to the @p QEIDriver object

+ *

+ * @notapi

+ */

+void qei_lld_start(QEIDriver *qeip) {

+  NRF_QDEC_Type *qdec = qeip->qdec; 

+  const QEIConfig *cfg = qeip->config;

+

+  if (qeip->state == QEI_STOP) {

+    /* Set Pins */

+    palSetLineMode(cfg->phase_a, PAL_MODE_INPUT);

+    palSetLineMode(cfg->phase_b, PAL_MODE_INPUT);

+#if NRF5_QEI_USE_LED == TRUE

+    if (cfg->led != PAL_NOLINE) {

+      palSetLineMode(cfg->led, PAL_MODE_INPUT);

+    }

+#endif

+      

+    /* Set interrupt masks and enable interrupt */

+#if NRF5_QEI_USE_ACC_OVERFLOWED_CB == TRUE

+    qdec->INTENSET = QDEC_INTENSET_REPORTRDY_Msk |

+	             QDEC_INTENSET_ACCOF_Msk;

+#else

+    qdec->INTENSET = QDEC_INTENSET_REPORTRDY_Msk;

+#endif

+#if NRF5_QEI_USE_QDEC0 == TRUE

+    if (&QEID1 == qeip) {

+      nvicEnableVector(QDEC_IRQn, NRF5_QEI_QDEC0_IRQ_PRIORITY);

+    }

+#endif

+

+    /* Select pin for Phase A and Phase B */

+#if   NRF_SERIES == 51

+    qdec->PSELA      = PAL_PAD(cfg->phase_a);

+    qdec->PSELB      = PAL_PAD(cfg->phase_b);

+#else

+    qdec->PSEL.A     = PAL_PAD(cfg->phase_a);

+    qdec->PSEL.B     = PAL_PAD(cfg->phase_b);

+#endif

+    /* Select (optional) pin for LED, and configure it */

+#if NRF5_QEI_USE_LED == TRUE

+#if   NRF_SERIES == 51

+    qdec->PSELLED    = PAL_PAD(cfg->led);

+#else

+    qdec->PSEL.LED   = PAL_PAD(cfg->led);

+#endif

+    qdec->LEDPOL     = ((cfg->led_polarity == QEI_LED_POLARITY_LOW)

+                         ? QDEC_LEDPOL_LEDPOL_ActiveLow 

+		         : QDEC_LEDPOL_LEDPOL_ActiveHigh)

+                       << QDEC_LEDPOL_LEDPOL_Pos; 

+    qdec->LEDPRE     = cfg->led_warming;

+#else

+#if   NRF_SERIES == 51

+    qdec->PSELLED    = (uint32_t)-1;

+#else

+    qdec->PSEL.LED   = (uint32_t)-1;

+#endif

+#endif

+    

+    /* Set sampling resolution and debouncing */

+    qdec->SAMPLEPER  = cfg->resolution;

+    qdec->DBFEN      = (cfg->debouncing ? QDEC_DBFEN_DBFEN_Enabled

+			                : QDEC_DBFEN_DBFEN_Disabled)

+                       << QDEC_DBFEN_DBFEN_Pos;

+

+    /* Define minimum sampling before reporting

+       and create shortcut to clear accumulation */

+    qdec->REPORTPER  = cfg->report;

+    qdec->SHORTS     = QDEC_SHORTS_REPORTRDY_READCLRACC_Msk;

+

+    /* Enable peripheric */

+    qdec->ENABLE     = 1;

+  }

+

+  /* Initially state is stopped, events cleared */

+  qdec->TASKS_STOP       = 1;

+  qdec->EVENTS_SAMPLERDY = 0;

+  qdec->EVENTS_REPORTRDY = 0;

+  qdec->EVENTS_ACCOF     = 0;

+#if CORTEX_MODEL >= 4

+  (void)qdec->EVENTS_SAMPLERDY;

+  (void)qdec->EVENTS_REPORTRDY;

+  (void)qdec->EVENTS_ACCOF;

+#endif

+}

+

+/**

+ * @brief   Deactivates the QEI peripheral.

+ *

+ * @param[in] qeip      pointer to the @p QEIDriver object

+ *

+ * @notapi

+ */

+void qei_lld_stop(QEIDriver *qeip) {

+

+  NRF_QDEC_Type *qdec = qeip->qdec;

+  const QEIConfig *cfg = qeip->config;

+

+  if (qeip->state == QEI_READY) {

+    qdec->TASKS_STOP = 1;

+    qdec->ENABLE     = 0;

+

+    /* Unset interrupt masks and disable interrupt */

+#if NRF5_QEI_USE_QDEC0 == TRUE

+    if (&QEID1 == qeip) {

+      nvicDisableVector(QDEC_IRQn);

+    }

+#endif

+#if NRF5_QEI_USE_ACC_OVERFLOWED_CB == TRUE

+    qdec->INTENCLR = QDEC_INTENCLR_REPORTRDY_Msk |

+	             QDEC_INTENCLR_ACCOF_Msk;

+#else

+    qdec->INTENCLR = QDEC_INTENCLR_REPORTRDY_Msk;

+#endif

+    

+    /* Return pins to reset state */

+    palSetLineMode(cfg->phase_a, PAL_MODE_RESET);

+    palSetLineMode(cfg->phase_b, PAL_MODE_RESET);

+#if NRF5_QEI_USE_LED == TRUE

+    if (cfg->led != PAL_NOLINE) {

+      palSetLineMode(cfg->led, PAL_MODE_RESET);

+    }

+#endif

+  }

+}

+

+/**

+ * @brief   Enables the input capture.

+ *

+ * @param[in] qeip      pointer to the @p QEIDriver object

+ *

+ * @notapi

+ */

+void qei_lld_enable(QEIDriver *qeip) {

+#if NRF5_QEI_USE_ACC_OVERFLOWED_CB == TRUE

+  qeip->overflowed = 0;

+#endif

+  

+  qeip->qdec->EVENTS_SAMPLERDY = 0;

+  qeip->qdec->EVENTS_REPORTRDY = 0;

+  qeip->qdec->EVENTS_ACCOF = 0;

+#if CORTEX_MODEL >= 4

+  (void)qeip->qdec->EVENTS_SAMPLERDY;

+  (void)qeip->qdec->EVENTS_REPORTRDY;

+  (void)qeip->qdec->EVENTS_ACCOF;

+#endif

+  qeip->qdec->TASKS_START = 1;

+}

+

+/**

+ * @brief   Disables the input capture.

+ *

+ * @param[in] qeip      pointer to the @p QEIDriver object

+ *

+ * @notapi

+ */

+void qei_lld_disable(QEIDriver *qeip) {

+  qeip->qdec->TASKS_STOP = 1;

+}

+

+

+#endif /* HAL_USE_QEI */

+

+/** @} */

diff --git a/os/hal/ports/NRF5/LLD/hal_qei_lld.h b/os/hal/ports/NRF5/LLD/hal_qei_lld.h
new file mode 100644
index 0000000..85c96a5
--- /dev/null
+++ b/os/hal/ports/NRF5/LLD/hal_qei_lld.h
@@ -0,0 +1,390 @@
+/*

+    ChibiOS - Copyright (C) 2016..2016 Stéphane D'Alu

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    NRF51/hal_qei_lld.h

+ * @brief   NRF51 QEI subsystem low level driver header.

+ *

+ * @note    Not tested with LED pin

+ *

+ * @note    Pins are configured as input with no pull.

+ *

+ * @addtogroup QEI

+ * @{

+ */

+

+#ifndef HAL_QEI_LLD_H

+#define HAL_QEI_LLD_H

+

+#if (HAL_USE_QEI == TRUE) || defined(__DOXYGEN__)

+

+/*===========================================================================*/

+/* Driver constants.                                                         */

+/*===========================================================================*/

+

+/**

+ * @brief For LED active on LOW

+ */

+#define QEI_LED_POLARITY_LOW   0

+

+/**

+ * @brief For LED active on HIGH

+ */

+#define QEI_LED_POLARITY_HIGH  1

+

+/**

+ * @brief Mininum usable value for defining counter underflow

+ */

+#define QEI_COUNT_MIN (-2147483648)

+

+/**

+ * @brief Maximum usable value for defining counter overflow

+ */

+#define QEI_COUNT_MAX ( 2147483647)

+

+

+

+/*===========================================================================*/

+/* Driver pre-compile time settings.                                         */

+/*===========================================================================*/

+

+/**

+ * @name    Configuration options

+ * @{

+ */

+/**

+ * @brief   LED control enable switch.

+ * @details If set to @p TRUE the support for LED control

+ *          is included.

+ * @note    The default is @p FALSE.

+ */

+#if !defined(NRF5_QEI_USE_LED) || defined(__DOXYGEN__)

+#define NRF5_QEI_USE_LED                   FALSE

+#endif

+

+/**

+ * @brief   Accumulator overflow notification enable switch.

+ * @details If set to @p TRUE the support for accumulator overflow

+ *          is included.

+ * @note    The default is @p FALSE.

+ */

+#if !defined(NRF5_QEI_USE_ACC_OVERFLOWED_CB) || defined(__DOXYGEN__)

+#define NRF5_QEI_USE_ACC_OVERFLOWED_CB       FALSE

+#endif

+

+/**

+ * @brief   QEID1 driver enable switch.

+ * @details If set to @p TRUE the support for QEID1 is included.

+ * @note    The default is @p FALSE.

+ */

+#if !defined(NRF5_QEI_USE_QDEC0) || defined(__DOXYGEN__)

+#define NRF5_QEI_USE_QDEC0                 FALSE

+#endif

+

+/**

+ * @brief   QEID interrupt priority level setting for QDEC0.

+ */

+#if !defined(NRF5_QEI_QDEC0_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define NRF5_QEI_QDEC0_IRQ_PRIORITY              2

+#endif

+/** @} */

+

+/*===========================================================================*/

+/* Derived constants and error checks.                                       */

+/*===========================================================================*/

+

+#if NRF5_QEI_USE_QDEC0 == FALSE

+#error "Requesting QEI driver, but no QDEC peripheric attached"

+#endif

+

+#if NRF5_QEI_USE_QDEC0 &&					\

+    !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_QEI_QDEC0_IRQ_PRIORITY)

+#error "Invalid IRQ priority assigned to QDEC0"

+#endif

+

+

+/*===========================================================================*/

+/* Driver data structures and types.                                         */

+/*===========================================================================*/

+

+/**

+ * @brief   QEI count mode.

+ */

+typedef enum {

+  QEI_MODE_QUADRATURE = 0,          /**< Quadrature encoder mode.           */

+} qeimode_t;

+

+/**

+ * @brief   QEI resolution.

+ */

+typedef enum {

+  QEI_RESOLUTION_128us   = 0x00UL,  /**<   128us sample period. */

+  QEI_RESOLUTION_256us   = 0x01UL,  /**<   256us sample period. */

+  QEI_RESOLUTION_512us   = 0x02UL,  /**<   512us sample period. */

+  QEI_RESOLUTION_1024us  = 0x03UL,  /**<  1024us sample period. */

+  QEI_RESOLUTION_2048us  = 0x04UL,  /**<  2048us sample period. */

+  QEI_RESOLUTION_4096us  = 0x05UL,  /**<  4096us sample period. */

+  QEI_RESOLUTION_8192us  = 0x06UL,  /**<  8192us sample period. */

+  QEI_RESOLUTION_16384us = 0x07UL,  /**< 16384us sample period. */

+} qeiresolution_t;

+

+/**

+ * @brief   Clusters of samples.

+ */

+typedef enum {

+  QEI_REPORT_10          = 0x00UL,  /**<  10 samples per report. */

+  QEI_REPORT_40          = 0x01UL,  /**<  40 samples per report. */

+  QEI_REPORT_80          = 0x02UL,  /**<  80 samples per report. */

+  QEI_REPORT_120         = 0x03UL,  /**< 120 samples per report. */

+  QEI_REPORT_160         = 0x04UL,  /**< 160 samples per report. */

+  QEI_REPORT_200         = 0x05UL,  /**< 200 samples per report. */

+  QEI_REPORT_240         = 0x06UL,  /**< 240 samples per report. */

+  QEI_REPORT_280         = 0x07UL,  /**< 280 samples per report. */

+} qeireport_t;

+

+/**

+ * @brief   QEI direction inversion.

+ */

+typedef enum {

+  QEI_DIRINV_FALSE = 0,             /**< Do not invert counter direction.   */

+  QEI_DIRINV_TRUE = 1,              /**< Invert counter direction.          */

+} qeidirinv_t;

+

+/**

+ * @brief   QEI counter type.

+ */

+typedef int16_t qeicnt_t;

+

+/**

+ * @brief   QEI delta type.

+ */

+typedef int16_t qeidelta_t;

+

+/**

+ * @brief   Driver configuration structure.

+ * @note    It could be empty on some architectures.

+ */

+typedef struct {

+  /**

+   * @brief   Count mode.

+   */

+  qeimode_t                 mode;

+  /**

+   * @brief   Resolution.

+   */

+  qeiresolution_t           resolution;

+  /**

+   * @brief   Direction inversion.

+   */

+  qeidirinv_t               dirinv;

+  /**

+   * @brief   Handling of counter overflow/underflow

+   *

+   * @details When overflow occurs, the counter value is updated

+   *          according to:

+   *            - QEI_OVERFLOW_DISCARD:

+   *                discard the update value, counter doesn't change

+   *            - QEI_OVERFLOW_MINMAX

+   *                counter will be updated to reach min or max

+   *            - QEI_OVERFLOW_WRAP:

+   *                counter value will wrap around

+   */

+  qeioverflow_t             overflow;

+  /**

+   * @brief   Min count value.

+   * 

+   * @note    If min == max, then QEI_COUNT_MIN is used.

+   */

+  qeicnt_t                  min;

+  /**

+   * @brief   Max count value.

+   * 

+   * @note    If min == max, then QEI_COUNT_MAX is used.

+   */

+  qeicnt_t                  max;

+  /**

+    * @brief  Notify of value change

+    *

+    * @note   Called from ISR context.

+    */

+  qeicallback_t             notify_cb;

+  /**

+   * @brief   Notify of overflow

+   *

+   * @note    Overflow notification is performed after 

+   *          value changed notification.

+   * @note    Called from ISR context.

+   */

+  void (*overflow_cb)(QEIDriver *qeip, qeidelta_t delta);

+  /* End of the mandatory fields.*/

+  /**

+   * @brief   Line for reading Phase A

+   */

+  ioline_t                  phase_a;

+  /**

+   * @brief   Line for reading Phase B

+   */

+  ioline_t                  phase_b;

+#if (NRF5_QEI_USE_LED == TRUE) || defined(__DOXYGEN__)

+  /**

+   * @brief   Line used to control LED

+   *

+   * @note    If LED is not controlled by MCU, you need to use the 

+   *          PAL_NOLINE value.

+   */

+  ioline_t                  led;

+  /**

+   * @brief   Period in µs the LED is switched on prior to sampling.

+   *

+   * @details LED warming is expressed in micro-seconds and value

+   *          is [0..511]

+   *

+   * @note    31µs is the recommanded default.

+   *

+   * @note    If debouncing is activated, LED is always on for the

+   *          whole sampling period (aka: resolution)

+   */

+  uint16_t                  led_warming;

+  /**

+   * @brief   LED polarity to used (when LED is controlled by MCU) 

+   */

+  uint8_t                   led_polarity;

+#endif

+   /**

+    * @brief  Activate debouncing filter

+    *

+    * @note   If LED is controlled by MCU, the led_warming is ignored and,

+    *         LED is always on for the whole sampling period (aka: resolution)

+    */

+  bool                      debouncing;

+   /**

+    * @brief  Number of samples per report

+    *

+    * @details Default to QEI_REPORT_10

+    */

+  qeireport_t 		    report;

+#if NRF5_QEI_USE_ACC_OVERFLOWED_CB == TRUE

+   /**

+    * @brief  Notify of internal accumulator overflowed

+    *         (ie: MCU discarding samples)

+    * 

+    * @note   Called from ISR context.

+    */

+  qeicallback_t             overflowed_cb;

+#endif

+} QEIConfig;

+

+/**

+ * @brief   Structure representing an QEI driver.

+ */

+struct QEIDriver {

+  /**

+   * @brief Driver state.

+   */

+  qeistate_t                state;

+  /**

+   * @brief Last count value.

+   */

+  qeicnt_t                  last;

+  /**

+   * @brief Current configuration data.

+   */

+  const QEIConfig           *config;

+#if defined(QEI_DRIVER_EXT_FIELDS)

+  QEI_DRIVER_EXT_FIELDS

+#endif

+  /* End of the mandatory fields.*/

+  /**

+   * @brief Counter

+   */

+  qeicnt_t                  count;

+#if NRF5_QEI_USE_ACC_OVERFLOWED_CB == TRUE

+  /**

+   * @brief Number of time the MCU discarded updates due to

+   *        accumulator overflow

+   */

+  uint32_t                  overflowed;

+#endif

+  /**

+   * @brief Pointer to the QDECx registers block.

+   */

+  NRF_QDEC_Type             *qdec;

+};

+

+/*===========================================================================*/

+/* Driver macros.                                                            */

+/*===========================================================================*/

+

+/**

+ * @brief   Returns the counter value.

+ *

+ * @param[in] qeip      pointer to the @p QEIDriver object

+ * @return              The current counter value.

+ *

+ * @notapi

+ */

+#define qei_lld_get_count(qeip) ((qeip)->count)

+

+

+/**

+ * @brief   Set the counter value.

+ *

+ * @param[in] qeip      pointer to the @p QEIDriver object

+ * @param[in] value     counter value

+ *

+ * @notapi

+ */

+#define qei_lld_set_count(qeip, value)		\

+    if ((qeip)->count != ((qeicnt_t)value)) {	\

+      (qeip)->count = value;			\

+      if ((qeip)->config->notify_cb)		\

+        (qeip)->config->notify_cb(qeip);	\

+    } while(0)

+

+

+/*===========================================================================*/

+/* External declarations.                                                    */

+/*===========================================================================*/

+

+#if NRF5_QEI_USE_QDEC0 && !defined(__DOXYGEN__)

+extern QEIDriver QEID1;

+#endif

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+  void qei_lld_init(void);

+  void qei_lld_start(QEIDriver *qeip);

+  void qei_lld_stop(QEIDriver *qeip);

+  void qei_lld_enable(QEIDriver *qeip);

+  void qei_lld_disable(QEIDriver *qeip);

+  qeidelta_t qei_lld_adjust_count(QEIDriver *qeip, qeidelta_t delta);

+#ifdef __cplusplus

+}

+#endif

+

+/*===========================================================================*/

+/* To be moved in hal_qei                                                    */

+/*===========================================================================*/

+

+void qeiSetCount(QEIDriver *qeip, qeicnt_t value);

+qeidelta_t qeiAdjust(QEIDriver *qeip, qeidelta_t delta);

+

+#endif /* HAL_USE_QEI */

+

+#endif /* HAL_QEI_LLD_H */

+

+/** @} */

diff --git a/os/hal/ports/NRF51/NRF51822/hal_rng_lld.c b/os/hal/ports/NRF5/LLD/hal_rng_lld.c
index 5e501ed..9712150 100644
--- a/os/hal/ports/NRF51/NRF51822/hal_rng_lld.c
+++ b/os/hal/ports/NRF5/LLD/hal_rng_lld.c
@@ -15,8 +15,8 @@
 */
 
 /**
- * @file    NRF51/RNGv1/rng_lld.c
- * @brief   NRF51 RNG subsystem low level driver source.
+ * @file    NRF5/LLD/hal_rng_lld.c
+ * @brief   NRF5 RNG subsystem low level driver source.
  *
  * @addtogroup RNG
  * @{
@@ -41,8 +41,8 @@ static const RNGConfig default_config = {
 /* Driver exported variables.                                                */
 /*===========================================================================*/
 
-/** @brief RNG1 driver identifier.*/
-#if NRF51_RNG_USE_RNG1 || defined(__DOXYGEN__)
+/** @brief RNGD1 driver identifier.*/
+#if NRF5_RNG_USE_RNG0 || defined(__DOXYGEN__)
 RNGDriver RNGD1;
 #endif
 
@@ -70,6 +70,7 @@ RNGDriver RNGD1;
 void rng_lld_init(void) {
   rngObjectInit(&RNGD1);
   RNGD1.rng    = NRF_RNG;
+  RNGD1.irq    = RNG_IRQn;
 }
 
 /**
@@ -80,19 +81,29 @@ void rng_lld_init(void) {
  * @notapi
  */
 void rng_lld_start(RNGDriver *rngp) {
+  NRF_RNG_Type *rng = rngp->rng;
+
+  /* If not specified, set default configuration */
   if (rngp->config == NULL)
     rngp->config = &default_config;
 
-  rngp->rng->POWER         = 1;
-
+  /* Configure digital error correction */
   if (rngp->config->digital_error_correction) 
-    rngp->rng->CONFIG |=  RNG_CONFIG_DERCEN_Msk;
+    rng->CONFIG |=  RNG_CONFIG_DERCEN_Msk;
   else
-    rngp->rng->CONFIG &= ~RNG_CONFIG_DERCEN_Msk;
+    rng->CONFIG &= ~RNG_CONFIG_DERCEN_Msk;
+
+  /* Clear pending events */
+  rng->EVENTS_VALRDY = 0;
+#if CORTEX_MODEL >= 4
+    (void)rng->EVENTS_VALRDY;
+#endif
+    
+  /* Set interrupt mask */
+  rng->INTENSET      = RNG_INTENSET_VALRDY_Msk;
 
-  rngp->rng->EVENTS_VALRDY = 0;
-  rngp->rng->INTENSET      = RNG_INTENSET_VALRDY_Msk;
-  rngp->rng->TASKS_START   = 1;
+  /* Start */
+  rng->TASKS_START   = 1;
 }
 
 
@@ -104,8 +115,10 @@ void rng_lld_start(RNGDriver *rngp) {
  * @notapi
  */
 void rng_lld_stop(RNGDriver *rngp) {
-  rngp->rng->TASKS_STOP = 1;
-  rngp->rng->POWER      = 0;
+  NRF_RNG_Type *rng = rngp->rng;
+
+  /* Stop peripheric */
+  rng->TASKS_STOP = 1;
 }
 
 
@@ -120,6 +133,7 @@ void rng_lld_stop(RNGDriver *rngp) {
  */
 msg_t rng_lld_write(RNGDriver *rngp, uint8_t *buf, size_t n,
                     systime_t timeout) {
+  NRF_RNG_Type *rng = rngp->rng;
   size_t i;
 
   for (i = 0 ; i < n ; i++) {
@@ -127,7 +141,7 @@ msg_t rng_lld_write(RNGDriver *rngp, uint8_t *buf, size_t n,
      * It take about 677µs to generate a new byte, not sure if
      * forcing a context switch will be a benefit
      */
-    while (NRF_RNG->EVENTS_VALRDY == 0) {
+    while (rng->EVENTS_VALRDY == 0) {
       /* Sleep and wakeup on ARM event (interrupt) */
       SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
       __SEV();
@@ -136,13 +150,16 @@ msg_t rng_lld_write(RNGDriver *rngp, uint8_t *buf, size_t n,
     }
 
     /* Read byte */
-    buf[i] = (char)NRF_RNG->VALUE;
+    buf[i] = (char)rng->VALUE;
 
     /* Mark as read */
-    NRF_RNG->EVENTS_VALRDY = 0;
-
+    rng->EVENTS_VALRDY = 0;
+#if CORTEX_MODEL >= 4
+    (void)rng->EVENTS_VALRDY;
+#endif
+    
     /* Clear interrupt so we can wake up again */
-    nvicClearPending(RNG_IRQn);
+    nvicClearPending(rngp->irq);
   }
   return MSG_OK;
 }
diff --git a/os/hal/ports/NRF51/NRF51822/hal_rng_lld.h b/os/hal/ports/NRF5/LLD/hal_rng_lld.h
index 0ad0bc6..5c56be2 100644
--- a/os/hal/ports/NRF51/NRF51822/hal_rng_lld.h
+++ b/os/hal/ports/NRF5/LLD/hal_rng_lld.h
@@ -15,8 +15,8 @@
 */
 
 /**
- * @file    NRF51/NRF51822/rng_lld.h
- * @brief   NRF51 RNG subsystem low level driver header.
+ * @file    NRF5/LLD/hal_rng_lld.h
+ * @brief   NRF5 RNG subsystem low level driver header.
  *
  * @addtogroup RNG
  * @{
@@ -40,28 +40,19 @@
  * @{
  */
 /**
- * @brief   RNG1 driver enable switch.
- * @details If set to @p TRUE the support for RNG1 is included.
+ * @brief   RNGD1 driver enable switch.
+ * @details If set to @p TRUE the support for RNGD1 is included.
  * @note    The default is @p FALSE.
  */
-#if !defined(NRF51_RNG_USE_RNG1) || defined(__DOXYGEN__)
-#define NRF51_RNG_USE_RNG1                  FALSE
+#if !defined(NRF5_RNG_USE_RNG0) || defined(__DOXYGEN__)
+#define NRF5_RNG_USE_RNG0                  FALSE
 #endif
 
 /**
- * @brief   RNG1 driver enable switch.
- * @details If set to @p TRUE the support for RNG1 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(NRF51_RNG_USE_RNG1) || defined(__DOXYGEN__)
-#define NRF51_RNG_USE_POWER_ON_WRITE        FALSE
-#endif
-
-/**
- * @brief   RNG1 interrupt priority level setting.
+ * @brief   RNG interrupt priority level setting for RNG0.
  */
-#if !defined(NRF51_RNG_RNG1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define NRF51_RNG_RNG1_IRQ_PRIORITY         3
+#if !defined(NRF5_RNG_RNG0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define NRF5_RNG_RNG0_IRQ_PRIORITY         3
 #endif
 
 
@@ -69,9 +60,13 @@
 /* Derived constants and error checks.                                       */
 /*===========================================================================*/
 
-#if NRF51_RNG_USE_RNG1 &&					\
-    !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_RNG_RNG1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to RNG1"
+#if NRF5_RNG_USE_RNG0 == FALSE
+#error "Requesting RNG driver, but no RNG peripheric attached"
+#endif
+
+#if NRF5_RNG_USE_RNG0 &&					\
+    !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_RNG_RNG0_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to RNG0"
 #endif
 
 /*===========================================================================*/
@@ -96,18 +91,11 @@ typedef struct {
    *          speed advantage, but may result in a statistical distribution
    *          that is not perfectly uniform.
    *
-   * @note    On average, it take 167µs to get a byte without digitial
-   *          error correction and 677µs with, but no garantee is made
-   *          on the necessary time to generate one byte.
+   * @note    For nRF51, on average, it take 167µs to get a byte without
+   *          digitial error correction and 677µs with, but no garantee 
+   *          is made on the necessary time to generate one byte.
    */
   uint8_t digital_error_correction:1;
-  /**
-   * @brief   Only power the RNG device when requeting random bytes
-   *
-   * @details Device will not be powered when started/stopped 
-   *          but only when writint bytes.
-   */
-  uint8_t power_on_write:1;
 } RNGConfig;
 
 
@@ -134,6 +122,10 @@ struct RNGDriver {
    * @brief Pointer to the RNGx registers block.
    */
   NRF_RNG_Type             *rng;
+  /**
+   * @brief IRQ number
+   */
+  uint32_t                  irq;
 };
 
 /*===========================================================================*/
@@ -144,9 +136,9 @@ struct RNGDriver {
 /* External declarations.                                                    */
 /*===========================================================================*/
 
-#if NRF51_RNG_USE_RNG1 && !defined(__DOXYGEN__)
+#if NRF5_RNG_USE_RNG0 && !defined(__DOXYGEN__)
 extern RNGDriver RNGD1;
-#endif /* NRF51_RNG_USE_RNG1 */
+#endif /* NRF5_RNG_USE_RNG0 */
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/os/hal/ports/NRF51/NRF51822/hal_serial_lld.c b/os/hal/ports/NRF5/LLD/hal_serial_lld.c
index 029c5da..42091e8 100644
--- a/os/hal/ports/NRF51/NRF51822/hal_serial_lld.c
+++ b/os/hal/ports/NRF5/LLD/hal_serial_lld.c
@@ -15,8 +15,8 @@
 */

 

 /**

- * @file    serial_lld.c

- * @brief   NRF51822 serial subsystem low level driver source.

+ * @file    NRF5/LLD/hal_serial_lld.c

+ * @brief   NRF5 serial subsystem low level driver source.

  *

  * @addtogroup SERIAL

  * @{

@@ -26,18 +26,24 @@
 

 #if (HAL_USE_SERIAL == TRUE) || defined(__DOXYGEN__)

 

+#if   NRF_SERIES == 51

 #include "nrf51.h"

+#elif NRF_SERIES == 52

+#include "nrf52.h"

+#define UART0_IRQn UARTE0_UART0_IRQn

+#endif

 

 /*===========================================================================*/

 /* Driver local definitions.                                                 */

 /*===========================================================================*/

 

+

 /*===========================================================================*/

 /* Driver exported variables.                                                */

 /*===========================================================================*/

 

 /** @brief USART1 serial driver identifier.*/

-#if (NRF51_SERIAL_USE_UART0 == TRUE) || defined(__DOXYGEN__)

+#if (NRF5_SERIAL_USE_UART0 == TRUE) || defined(__DOXYGEN__)

 SerialDriver SD1;

 #endif

 

@@ -50,11 +56,11 @@ SerialDriver SD1;
  */

 static const SerialConfig default_config = {

   .speed   = 38400,

-  .tx_pad  = NRF51_SERIAL_PAD_DISCONNECTED,

-  .rx_pad  = NRF51_SERIAL_PAD_DISCONNECTED,

-#if (NRF51_SERIAL_USE_HWFLOWCTRL == TRUE)

-  .rts_pad = NRF51_SERIAL_PAD_DISCONNECTED,

-  .cts_pad = NRF51_SERIAL_PAD_DISCONNECTED,

+  .tx_pad  = NRF5_SERIAL_PAD_DISCONNECTED,

+  .rx_pad  = NRF5_SERIAL_PAD_DISCONNECTED,

+#if (NRF5_SERIAL_USE_HWFLOWCTRL == TRUE)

+  .rts_pad = NRF5_SERIAL_PAD_DISCONNECTED,

+  .cts_pad = NRF5_SERIAL_PAD_DISCONNECTED,

 #endif

 };

 

@@ -95,17 +101,17 @@ static void configure_uart(const SerialConfig *config)
   };

 

   /* Configure PINs mode */

-  if (config->tx_pad != NRF51_SERIAL_PAD_DISCONNECTED) {

+  if (config->tx_pad != NRF5_SERIAL_PAD_DISCONNECTED) {

     palSetPadMode(IOPORT1, config->tx_pad, PAL_MODE_OUTPUT_PUSHPULL);

   }

-  if (config->rx_pad != NRF51_SERIAL_PAD_DISCONNECTED) {

+  if (config->rx_pad != NRF5_SERIAL_PAD_DISCONNECTED) {

     palSetPadMode(IOPORT1, config->rx_pad, PAL_MODE_INPUT);

   }

-#if (NRF51_SERIAL_USE_HWFLOWCTRL == TRUE)

-  if (config->rts_pad != NRF51_SERIAL_PAD_DISCONNECTED) {

+#if (NRF5_SERIAL_USE_HWFLOWCTRL == TRUE)

+  if (config->rts_pad != NRF5_SERIAL_PAD_DISCONNECTED) {

     palSetPadMode(IOPORT1, config->rts_pad, PAL_MODE_OUTPUT_PUSHPULL);

   }

-  if (config->cts_pad != NRF51_SERIAL_PAD_DISCONNECTED) {

+  if (config->cts_pad != NRF5_SERIAL_PAD_DISCONNECTED) {

     palSetPadMode(IOPORT1, config->cts_pad, PAL_MODE_INPUT);

   }

 #endif

@@ -113,12 +119,12 @@ static void configure_uart(const SerialConfig *config)
   /* Select PINs used by UART */

   NRF_UART0->PSELTXD = config->tx_pad;

   NRF_UART0->PSELRXD = config->rx_pad;

-#if (NRF51_SERIAL_USE_HWFLOWCTRL == TRUE)

+#if (NRF5_SERIAL_USE_HWFLOWCTRL == TRUE)

   NRF_UART0->PSELRTS = config->rts_pad;

   NRF_UART0->PSELCTS = config->cts_pad;

 #else

-  NRF_UART0->PSELRTS = NRF51_SERIAL_PAD_DISCONNECTED;

-  NRF_UART0->PSELCTS = NRF51_SERIAL_PAD_DISCONNECTED;

+  NRF_UART0->PSELRTS = NRF5_SERIAL_PAD_DISCONNECTED;

+  NRF_UART0->PSELCTS = NRF5_SERIAL_PAD_DISCONNECTED;

 #endif

 

   /* Set baud rate */

@@ -128,7 +134,7 @@ static void configure_uart(const SerialConfig *config)
   NRF_UART0->CONFIG = (UART_CONFIG_PARITY_Excluded << UART_CONFIG_PARITY_Pos);

 

   /* Adjust flow control */

-#if (NRF51_SERIAL_USE_HWFLOWCTRL == TRUE)

+#if (NRF5_SERIAL_USE_HWFLOWCTRL == TRUE)

   if ((config->rts_pad < TOTAL_GPIO_PADS) ||

       (config->cts_pad < TOTAL_GPIO_PADS)) {

     NRF_UART0->CONFIG |=   UART_CONFIG_HWFC_Enabled << UART_CONFIG_HWFC_Pos;

@@ -143,9 +149,12 @@ static void configure_uart(const SerialConfig *config)
   NRF_UART0->ENABLE = UART_ENABLE_ENABLE_Enabled;

   NRF_UART0->EVENTS_RXDRDY = 0;

   NRF_UART0->EVENTS_TXDRDY = 0;

-

-

-  if (config->rx_pad != NRF51_SERIAL_PAD_DISCONNECTED) {

+#if CORTEX_MODEL >= 4

+  (void)NRF_UART0->EVENTS_RXDRDY;

+  (void)NRF_UART0->EVENTS_TXDRDY;

+#endif

+  

+  if (config->rx_pad != NRF5_SERIAL_PAD_DISCONNECTED) {

     while (NRF_UART0->EVENTS_RXDRDY != 0) {

       (void)NRF_UART0->RXD;

     }

@@ -156,14 +165,14 @@ static void configure_uart(const SerialConfig *config)
 /**

  * @brief   Driver output notification.

  */

-#if NRF51_SERIAL_USE_UART0 || defined(__DOXYGEN__)

+#if NRF5_SERIAL_USE_UART0 || defined(__DOXYGEN__)

 static void notify1(io_queue_t *qp)

 {

   SerialDriver *sdp = &SD1;

 

   (void)qp;

 

-  if (NRF_UART0->PSELTXD == NRF51_SERIAL_PAD_DISCONNECTED)

+  if (NRF_UART0->PSELTXD == NRF5_SERIAL_PAD_DISCONNECTED)

     return;

 

   if (!sdp->tx_busy) {

@@ -186,7 +195,7 @@ static void notify1(io_queue_t *qp)
 /* Driver interrupt handlers.                                                */

 /*===========================================================================*/

 

-#if NRF51_SERIAL_USE_UART0 || defined(__DOXYGEN__)

+#if NRF5_SERIAL_USE_UART0 || defined(__DOXYGEN__)

 OSAL_IRQ_HANDLER(Vector48) {

 

   OSAL_IRQ_PROLOGUE();

@@ -197,7 +206,10 @@ OSAL_IRQ_HANDLER(Vector48) {
   if ((NRF_UART0->EVENTS_RXDRDY != 0) && (isr & UART_INTENSET_RXDRDY_Msk)) {

     // Clear UART RX event flag

     NRF_UART0->EVENTS_RXDRDY = 0;

-

+#if CORTEX_MODEL >= 4

+    (void)NRF_UART0->EVENTS_RXDRDY;

+#endif

+    

     osalSysLockFromISR();

     if (iqIsEmptyI(&sdp->iqueue))

       chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE);

@@ -211,7 +223,10 @@ OSAL_IRQ_HANDLER(Vector48) {
 

     // Clear UART TX event flag.

     NRF_UART0->EVENTS_TXDRDY = 0;

-

+#if CORTEX_MODEL >= 4

+    (void)NRF_UART0->EVENTS_TXDRDY;

+#endif

+    

     osalSysLockFromISR();

     b = oqGetI(&sdp->oqueue);

     osalSysUnlockFromISR();

@@ -232,6 +247,9 @@ OSAL_IRQ_HANDLER(Vector48) {
   if ((NRF_UART0->EVENTS_ERROR != 0) && (isr & UART_INTENSET_ERROR_Msk)) {

     // Clear UART ERROR event flag.

     NRF_UART0->EVENTS_ERROR = 0;

+#if CORTEX_MODEL >= 4

+    (void)NRF_UART0->EVENTS_ERROR;

+#endif

   }

 

 

@@ -250,7 +268,7 @@ OSAL_IRQ_HANDLER(Vector48) {
  */

 void sd_lld_init(void) {

 

-#if NRF51_SERIAL_USE_UART0 == TRUE

+#if NRF5_SERIAL_USE_UART0 == TRUE

   sdObjectInit(&SD1, NULL, notify1);

 #endif

 }

@@ -276,21 +294,21 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
 

   if (sdp->state == SD_STOP) {

 

-#if NRF51_SERIAL_USE_UART0 == TRUE

+#if NRF5_SERIAL_USE_UART0 == TRUE

     if (sdp == &SD1) {

       configure_uart(config);

 

       // Enable UART interrupt

       NRF_UART0->INTENCLR = (uint32_t)-1;

       NRF_UART0->INTENSET = UART_INTENSET_ERROR_Msk;

-      if (config->rx_pad != NRF51_SERIAL_PAD_DISCONNECTED)

+      if (config->rx_pad != NRF5_SERIAL_PAD_DISCONNECTED)

           NRF_UART0->INTENSET |= UART_INTENSET_RXDRDY_Msk;

-      if (config->tx_pad != NRF51_SERIAL_PAD_DISCONNECTED)

+      if (config->tx_pad != NRF5_SERIAL_PAD_DISCONNECTED)

           NRF_UART0->INTENSET |= UART_INTENSET_TXDRDY_Msk;

 

-      nvicEnableVector(UART0_IRQn, NRF51_SERIAL_UART0_PRIORITY);

+      nvicEnableVector(UART0_IRQn, NRF5_SERIAL_UART0_PRIORITY);

 

-      if (config->rx_pad != NRF51_SERIAL_PAD_DISCONNECTED)

+      if (config->rx_pad != NRF5_SERIAL_PAD_DISCONNECTED)

         NRF_UART0->TASKS_STARTRX = 1;

     }

 #endif

@@ -311,7 +329,7 @@ void sd_lld_stop(SerialDriver *sdp) {
 

   if (sdp->state == SD_READY) {

 

-#if NRF51_SERIAL_USE_UART0 == TRUE

+#if NRF5_SERIAL_USE_UART0 == TRUE

     if (&SD1 == sdp) {

       nvicDisableVector(UART0_IRQn);

       NRF_UART0->ENABLE = UART_ENABLE_ENABLE_Disabled;

diff --git a/os/hal/ports/NRF51/NRF51822/hal_serial_lld.h b/os/hal/ports/NRF5/LLD/hal_serial_lld.h
index 79955b1..741a40a 100644
--- a/os/hal/ports/NRF51/NRF51822/hal_serial_lld.h
+++ b/os/hal/ports/NRF5/LLD/hal_serial_lld.h
@@ -15,8 +15,8 @@
 */

 

 /**

- * @file    serial_lld.h

- * @brief   NRF51822 serial subsystem low level driver header.

+ * @file    NRF5/LLD/hal_serial_lld.h

+ * @brief   NRF5 serial subsystem low level driver header.

  *

  * @addtogroup SERIAL

  * @{

@@ -45,8 +45,8 @@
  *          is included.

  * @note    The default is @p FALSE.

  */

-#if !defined(NRF51_SERIAL_USE_HWFLOWCTRL) || defined(__DOXYGEN__)

-#define NRF51_SERIAL_USE_HWFLOWCTRL        FALSE

+#if !defined(NRF5_SERIAL_USE_HWFLOWCTRL) || defined(__DOXYGEN__)

+#define NRF5_SERIAL_USE_HWFLOWCTRL        FALSE

 #endif

 

 /**

@@ -54,20 +54,20 @@
  * @details If set to @p TRUE the support for SD1 is included.

  * @note    The default is @p FALSE.

  */

-#if !defined(NRF51_SERIAL_USE_UART0) || defined(__DOXYGEN__)

-#define NRF51_SERIAL_USE_UART0             FALSE

+#if !defined(NRF5_SERIAL_USE_UART0) || defined(__DOXYGEN__)

+#define NRF5_SERIAL_USE_UART0             FALSE

 #endif

 

 /**

  * @brief   UART0 interrupt priority level setting.

  */

-#if !defined(NRF51_SERIAL_UART0_PRIORITY) || defined(__DOXYGEN__)

-#define NRF51_SERIAL_UART0_PRIORITY        3

+#if !defined(NRF5_SERIAL_UART0_PRIORITY) || defined(__DOXYGEN__)

+#define NRF5_SERIAL_UART0_PRIORITY        3

 #endif

 

 /* Value indicating that no pad is connected to this UART register. */

-#define  NRF51_SERIAL_PAD_DISCONNECTED 0xFFFFFFFFU

-#define  NRF51_SERIAL_INVALID_BAUDRATE 0xFFFFFFFFU

+#define  NRF5_SERIAL_PAD_DISCONNECTED 0xFFFFFFFFU

+#define  NRF5_SERIAL_INVALID_BAUDRATE 0xFFFFFFFFU

 

 /** @} */

 

@@ -75,8 +75,8 @@
 /* Derived constants and error checks.                                       */

 /*===========================================================================*/

 

-#if NRF51_SERIAL_USE_UART0 &&					\

-    !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_SERIAL_UART0_PRIORITY)

+#if NRF5_SERIAL_USE_UART0 &&					\

+    !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_SERIAL_UART0_PRIORITY)

 #error "Invalid IRQ priority assigned to UART0"

 #endif

 

@@ -100,7 +100,7 @@ typedef struct {
   /* End of the mandatory fields.*/

   uint32_t                  tx_pad;

   uint32_t                  rx_pad;

-#if (NRF51_SERIAL_USE_HWFLOWCTRL == TRUE)

+#if (NRF5_SERIAL_USE_HWFLOWCTRL == TRUE)

   uint32_t                  rts_pad;

   uint32_t                  cts_pad;

 #endif

@@ -134,7 +134,7 @@ typedef struct {
 /* External declarations.                                                    */

 /*===========================================================================*/

 

-#if (NRF51_SERIAL_USE_UART0 == TRUE) && !defined(__DOXYGEN__)

+#if (NRF5_SERIAL_USE_UART0 == TRUE) && !defined(__DOXYGEN__)

 extern SerialDriver SD1;

 #endif

 

diff --git a/os/hal/ports/NRF51/NRF51822/hal_spi_lld.c b/os/hal/ports/NRF5/LLD/hal_spi_lld.c
index 7a70c13..2c6ec91 100644
--- a/os/hal/ports/NRF51/NRF51822/hal_spi_lld.c
+++ b/os/hal/ports/NRF5/LLD/hal_spi_lld.c
@@ -15,8 +15,8 @@
 */

 

 /**

- * @file    NRF51822/spi_lld.c

- * @brief   NRF51822 low level SPI driver code.

+ * @file    NRF5/LLD/hal_spi_lld.c

+ * @brief   NRF5 low level SPI driver code.

  *

  * @addtogroup SPI

  * @{

@@ -30,12 +30,12 @@
 /* Driver exported variables.                                                */

 /*===========================================================================*/

 

-#if NRF51_SPI_USE_SPI0 || defined(__DOXYGEN__)

+#if NRF5_SPI_USE_SPI0 || defined(__DOXYGEN__)

 /** @brief SPI1 driver identifier.*/

 SPIDriver SPID1;

 #endif

 

-#if NRF51_SPI_USE_SPI1 || defined(__DOXYGEN__)

+#if NRF5_SPI_USE_SPI1 || defined(__DOXYGEN__)

 /** @brief SPI2 driver identifier.*/

 SPIDriver SPID2;

 #endif

@@ -76,7 +76,10 @@ static void serve_interrupt(SPIDriver *spip) {
 

   // Clear SPI READY event flag

   port->EVENTS_READY = 0;

-

+#if CORTEX_MODEL >= 4

+  (void)port->EVENTS_READY;

+#endif

+  

   if (spip->rxptr != NULL) {

     *(uint8_t *)spip->rxptr++ = port->RXD;

   }

@@ -107,7 +110,7 @@ static void serve_interrupt(SPIDriver *spip) {
 /* Driver interrupt handlers.                                                */

 /*===========================================================================*/

 

-#if NRF51_SPI_USE_SPI0 || defined(__DOXYGEN__)

+#if NRF5_SPI_USE_SPI0 || defined(__DOXYGEN__)

 /**

  * @brief   SPI0 interrupt handler.

  *

@@ -120,7 +123,7 @@ CH_IRQ_HANDLER(Vector4C) {
   CH_IRQ_EPILOGUE();

 }

 #endif

-#if NRF51_SPI_USE_SPI1 || defined(__DOXYGEN__)

+#if NRF5_SPI_USE_SPI1 || defined(__DOXYGEN__)

 /**

  * @brief   SPI1 interrupt handler.

  *

@@ -145,11 +148,11 @@ CH_IRQ_HANDLER(Vector50) {
  */

 void spi_lld_init(void) {

 

-#if NRF51_SPI_USE_SPI0

+#if NRF5_SPI_USE_SPI0

   spiObjectInit(&SPID1);

   SPID1.port = NRF_SPI0;

 #endif

-#if NRF51_SPI_USE_SPI1

+#if NRF5_SPI_USE_SPI1

   spiObjectInit(&SPID2);

   SPID2.port = NRF_SPI1;

 #endif

@@ -166,13 +169,13 @@ void spi_lld_start(SPIDriver *spip) {
   uint32_t config;

 

   if (spip->state == SPI_STOP) {

-#if NRF51_SPI_USE_SPI0

+#if NRF5_SPI_USE_SPI0

     if (&SPID1 == spip)

-      nvicEnableVector(SPI0_TWI0_IRQn, NRF51_SPI_SPI0_IRQ_PRIORITY);

+      nvicEnableVector(SPI0_TWI0_IRQn, NRF5_SPI_SPI0_IRQ_PRIORITY);

 #endif

-#if NRF51_SPI_USE_SPI1

+#if NRF5_SPI_USE_SPI1

     if (&SPID2 == spip)

-      nvicEnableVector(SPI1_TWI1_IRQn, NRF51_SPI_SPI1_IRQ_PRIORITY);

+      nvicEnableVector(SPI1_TWI1_IRQn, NRF5_SPI_SPI1_IRQ_PRIORITY);

 #endif

   }

 

@@ -201,14 +204,23 @@ void spi_lld_start(SPIDriver *spip) {
 

   /* Configuration.*/

   spip->port->CONFIG = config;

+#if NRF_SERIES == 51

   spip->port->PSELSCK = spip->config->sckpad;

   spip->port->PSELMOSI = spip->config->mosipad;

   spip->port->PSELMISO = spip->config->misopad;

+#else

+  spip->port->PSEL.SCK = spip->config->sckpad;

+  spip->port->PSEL.MOSI = spip->config->mosipad;

+  spip->port->PSEL.MISO = spip->config->misopad;

+#endif

   spip->port->FREQUENCY = spip->config->freq;

   spip->port->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos);

 

   /* clear events flag */

   spip->port->EVENTS_READY = 0;

+#if CORTEX_MODEL >= 4

+  (void)spip->port->EVENTS_READY;

+#endif

 }

 

 /**

@@ -223,11 +235,11 @@ void spi_lld_stop(SPIDriver *spip) {
   if (spip->state != SPI_STOP) {

     spip->port->ENABLE  = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos);

     spip->port->INTENCLR = (SPI_INTENCLR_READY_Clear << SPI_INTENCLR_READY_Pos);

-#if NRF51_SPI_USE_SPI0

+#if NRF5_SPI_USE_SPI0

     if (&SPID1 == spip)

       nvicDisableVector(SPI0_TWI0_IRQn);

 #endif

-#if NRF51_SPI_USE_SPI1

+#if NRF5_SPI_USE_SPI1

     if (&SPID2 == spip)

       nvicDisableVector(SPI1_TWI1_IRQn);

 #endif

@@ -366,6 +378,9 @@ uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
   while (spip->port->EVENTS_READY == 0)

     ;

   spip->port->EVENTS_READY = 0;

+#if CORTEX_MODEL >= 4

+  (void)spip->port->EVENTS_READY;

+#endif

   return spip->port->RXD;

 }

 

diff --git a/os/hal/ports/NRF51/NRF51822/hal_spi_lld.h b/os/hal/ports/NRF5/LLD/hal_spi_lld.h
index 4d1c452..afad5ab 100644
--- a/os/hal/ports/NRF51/NRF51822/hal_spi_lld.h
+++ b/os/hal/ports/NRF5/LLD/hal_spi_lld.h
@@ -15,8 +15,8 @@
 */

 

 /**

- * @file    NRF51822/spi_lld.h

- * @brief   NRF51822 low level SPI driver header.

+ * @file    NRF/LLD/hal_spi_lld.h

+ * @brief   NRF5 low level SPI driver header.

  *

  * @addtogroup SPI

  * @{

@@ -38,40 +38,40 @@
 /**

  * @brief   SPI0 interrupt priority level setting.

  */

-#if !defined(NRF51_SPI_SPI0_IRQ_PRIORITY) || defined(__DOXYGEN__)

-#define NRF51_SPI_SPI0_IRQ_PRIORITY    3

+#if !defined(NRF5_SPI_SPI0_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define NRF5_SPI_SPI0_IRQ_PRIORITY    3

 #endif

 

 /**

  * @brief   SPI1 interrupt priority level setting.

  */

-#if !defined(NRF51_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)

-#define NRF51_SPI_SPI1_IRQ_PRIORITY    3

+#if !defined(NRF5_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define NRF5_SPI_SPI1_IRQ_PRIORITY    3

 #endif

 

 /**

  * @brief   Overflow error hook.

  * @details The default action is to stop the system.

  */

-#if !defined(NRF51_SPI_SPI_ERROR_HOOK) || defined(__DOXYGEN__)

-#define NRF51_SPI_SPI_ERROR_HOOK()    chSysHalt()

+#if !defined(NRF5_SPI_SPI_ERROR_HOOK) || defined(__DOXYGEN__)

+#define NRF5_SPI_SPI_ERROR_HOOK()    chSysHalt()

 #endif

 

 /*===========================================================================*/

 /* Derived constants and error checks.                                       */

 /*===========================================================================*/

 

-#if !NRF51_SPI_USE_SPI0 && !NRF51_SPI_USE_SPI1

+#if !NRF5_SPI_USE_SPI0 && !NRF5_SPI_USE_SPI1

 #error "SPI driver activated but no SPI peripheral assigned"

 #endif

 

-#if NRF51_SPI_USE_SPI0 &&						    \

-    !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_SPI_SPI0_IRQ_PRIORITY)

+#if NRF5_SPI_USE_SPI0 &&						    \

+    !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_SPI_SPI0_IRQ_PRIORITY)

 #error "Invalid IRQ priority assigned to SPI0"

 #endif

 

-#if NRF51_SPI_USE_SPI1 &&						    \

-    !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_SPI_SPI1_IRQ_PRIORITY)

+#if NRF5_SPI_USE_SPI1 &&						    \

+    !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_SPI_SPI1_IRQ_PRIORITY)

 #error "Invalid IRQ priority assigned to SPI1"

 #endif

 

@@ -96,13 +96,13 @@ typedef void (*spicallback_t)(SPIDriver *spip);
  * @brief   SPI frequency

  */

 typedef enum {

-  NRF51_SPI_FREQ_125KBPS = (SPI_FREQUENCY_FREQUENCY_K125 << SPI_FREQUENCY_FREQUENCY_Pos),

-  NRF51_SPI_FREQ_250KBPS = (SPI_FREQUENCY_FREQUENCY_K250 << SPI_FREQUENCY_FREQUENCY_Pos),

-  NRF51_SPI_FREQ_500KBPS = (SPI_FREQUENCY_FREQUENCY_K500 << SPI_FREQUENCY_FREQUENCY_Pos),

-  NRF51_SPI_FREQ_1MBPS = (SPI_FREQUENCY_FREQUENCY_M1 << SPI_FREQUENCY_FREQUENCY_Pos),

-  NRF51_SPI_FREQ_2MBPS = (SPI_FREQUENCY_FREQUENCY_M2 << SPI_FREQUENCY_FREQUENCY_Pos),

-  NRF51_SPI_FREQ_4MBPS = (SPI_FREQUENCY_FREQUENCY_M4 << SPI_FREQUENCY_FREQUENCY_Pos),

-  NRF51_SPI_FREQ_8MBPS = (SPI_FREQUENCY_FREQUENCY_M8 << SPI_FREQUENCY_FREQUENCY_Pos),

+  NRF5_SPI_FREQ_125KBPS = (SPI_FREQUENCY_FREQUENCY_K125 << SPI_FREQUENCY_FREQUENCY_Pos),

+  NRF5_SPI_FREQ_250KBPS = (SPI_FREQUENCY_FREQUENCY_K250 << SPI_FREQUENCY_FREQUENCY_Pos),

+  NRF5_SPI_FREQ_500KBPS = (SPI_FREQUENCY_FREQUENCY_K500 << SPI_FREQUENCY_FREQUENCY_Pos),

+  NRF5_SPI_FREQ_1MBPS = (SPI_FREQUENCY_FREQUENCY_M1 << SPI_FREQUENCY_FREQUENCY_Pos),

+  NRF5_SPI_FREQ_2MBPS = (SPI_FREQUENCY_FREQUENCY_M2 << SPI_FREQUENCY_FREQUENCY_Pos),

+  NRF5_SPI_FREQ_4MBPS = (SPI_FREQUENCY_FREQUENCY_M4 << SPI_FREQUENCY_FREQUENCY_Pos),

+  NRF5_SPI_FREQ_8MBPS = (SPI_FREQUENCY_FREQUENCY_M8 << SPI_FREQUENCY_FREQUENCY_Pos),

 } spifreq_t;

 

 /**

@@ -206,10 +206,10 @@ struct SPIDriver {
 /* External declarations.                                                    */

 /*===========================================================================*/

 

-#if NRF51_SPI_USE_SPI0 && !defined(__DOXYGEN__)

+#if NRF5_SPI_USE_SPI0 && !defined(__DOXYGEN__)

 extern SPIDriver SPID1;

 #endif

-#if NRF51_SPI_USE_SPI1 && !defined(__DOXYGEN__)

+#if NRF5_SPI_USE_SPI1 && !defined(__DOXYGEN__)

 extern SPIDriver SPID2;

 #endif

 

diff --git a/os/hal/ports/NRF51/NRF51822/hal_st_lld.c b/os/hal/ports/NRF5/LLD/hal_st_lld.c
index 181bc06..8e42029 100644
--- a/os/hal/ports/NRF51/NRF51822/hal_st_lld.c
+++ b/os/hal/ports/NRF5/LLD/hal_st_lld.c
@@ -16,8 +16,8 @@
 */

 

 /**

- * @file    st_lld.c

- * @brief   NRF51822 ST subsystem low level driver source.

+ * @file    NRF5/LLD/hal_st_lld.c

+ * @brief   NRF5 ST subsystem low level driver source.

  *

  * @addtogroup ST

  * @{

@@ -52,11 +52,11 @@
 /*===========================================================================*/

 

 #if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__)

-#if NRF51_ST_USE_RTC0 == TRUE

+#if NRF5_ST_USE_RTC0 == TRUE

 /**

  * @brief   System Timer vector (RTC0)

  * @details This interrupt is used for system tick in periodic mode

- *          if selected with NRF51_ST_USE_RTC0

+ *          if selected with NRF5_ST_USE_RTC0

  *

  * @isr

  */

@@ -65,7 +65,10 @@ OSAL_IRQ_HANDLER(Vector6C) {
   OSAL_IRQ_PROLOGUE();

 

   NRF_RTC0->EVENTS_TICK = 0;

-

+#if CORTEX_MODEL >= 4

+  (void)NRF_RTC0->EVENTS_TICK;

+#endif

+  

   osalSysLockFromISR();

   osalOsTimerHandlerI();

   osalSysUnlockFromISR();

@@ -74,11 +77,11 @@ OSAL_IRQ_HANDLER(Vector6C) {
 }

 #endif

 

-#if NRF51_ST_USE_RTC1 == TRUE

+#if NRF5_ST_USE_RTC1 == TRUE

 /**

  * @brief   System Timer vector (RTC1)

  * @details This interrupt is used for system tick in periodic mode

- *          if selected with NRF51_ST_USE_RTC1

+ *          if selected with NRF5_ST_USE_RTC1

  *

  * @isr

  */

@@ -87,7 +90,10 @@ OSAL_IRQ_HANDLER(Vector84) {
   OSAL_IRQ_PROLOGUE();

 

   NRF_RTC1->EVENTS_TICK = 0;

-

+#if CORTEX_MODEL >= 4

+  (void)NRF_RTC1->EVENTS_TICK;

+#endif

+  

   osalSysLockFromISR();

   osalOsTimerHandlerI();

   osalSysUnlockFromISR();

@@ -96,11 +102,11 @@ OSAL_IRQ_HANDLER(Vector84) {
 }

 #endif

 

-#if NRF51_ST_USE_TIMER0 == TRUE

+#if NRF5_ST_USE_TIMER0 == TRUE

 /**

  * @brief   System Timer vector. (TIMER0)

  * @details This interrupt is used for system tick in periodic mode

- *          if selected with NRF51_ST_USE_TIMER0

+ *          if selected with NRF5_ST_USE_TIMER0

  *

  * @isr

  */

@@ -109,12 +115,16 @@ OSAL_IRQ_HANDLER(Vector60) {
   OSAL_IRQ_PROLOGUE();

 

   /* Clear timer compare event */

-  if (NRF_TIMER0->EVENTS_COMPARE[0] != 0)

+  if (NRF_TIMER0->EVENTS_COMPARE[0] != 0) {

     NRF_TIMER0->EVENTS_COMPARE[0] = 0;

-

-  osalSysLockFromISR();

-  osalOsTimerHandlerI();

-  osalSysUnlockFromISR();

+#if CORTEX_MODEL >= 4

+    (void)NRF_TIMER0->EVENTS_COMPARE[0];

+#endif

+    

+    osalSysLockFromISR();

+    osalOsTimerHandlerI();

+    osalSysUnlockFromISR();

+  }

 

   OSAL_IRQ_EPILOGUE();

 }

@@ -122,11 +132,11 @@ OSAL_IRQ_HANDLER(Vector60) {
 #endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */

 

 #if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) || defined(__DOXYGEN__)

-#if NRF51_ST_USE_RTC0 == TRUE

+#if NRF5_ST_USE_RTC0 == TRUE

 /**

  * @brief   System Timer vector (RTC0)

  * @details This interrupt is used for freerunning mode (tick-less)

- *          if selected with NRF51_ST_USE_RTC0 

+ *          if selected with NRF5_ST_USE_RTC0 

  *

  * @isr

  */

@@ -136,7 +146,10 @@ OSAL_IRQ_HANDLER(Vector6C) {
 

   if (NRF_RTC0->EVENTS_COMPARE[0]) {

     NRF_RTC0->EVENTS_COMPARE[0] = 0;

-

+#if CORTEX_MODEL >= 4

+    (void)NRF_RTC0->EVENTS_COMPARE[0];

+#endif

+    

     osalSysLockFromISR();

     osalOsTimerHandlerI();

     osalSysUnlockFromISR();

@@ -145,6 +158,9 @@ OSAL_IRQ_HANDLER(Vector6C) {
 #if OSAL_ST_RESOLUTION == 16

   if (NRF_RTC0->EVENTS_COMPARE[1]) {

     NRF_RTC0->EVENTS_COMPARE[1] = 0;

+#if CORTEX_MODEL >= 4

+    (void)NRF_RTC0->EVENTS_COMPARE[1];

+#endif

     NRF_RTC0->TASKS_CLEAR = 1;

   }

 #endif

@@ -153,11 +169,11 @@ OSAL_IRQ_HANDLER(Vector6C) {
 }

 #endif

 

-#if NRF51_ST_USE_RTC1 == TRUE

+#if NRF5_ST_USE_RTC1 == TRUE

 /**

  * @brief   System Timer vector (RTC1)

  * @details This interrupt is used for freerunning mode (tick-less)

- *          if selected with NRF51_ST_USE_RTC1

+ *          if selected with NRF5_ST_USE_RTC1

  *

  * @isr

  */

@@ -167,7 +183,10 @@ OSAL_IRQ_HANDLER(Vector84) {
 

   if (NRF_RTC1->EVENTS_COMPARE[0]) {

     NRF_RTC1->EVENTS_COMPARE[0] = 0;

-

+#if CORTEX_MODEL >= 4

+    (void)NRF_RTC1->EVENTS_COMPARE[0];

+#endif

+    

     osalSysLockFromISR();

     osalOsTimerHandlerI();

     osalSysUnlockFromISR();

@@ -176,6 +195,9 @@ OSAL_IRQ_HANDLER(Vector84) {
 #if OSAL_ST_RESOLUTION == 16

   if (NRF_RTC1->EVENTS_COMPARE[1]) {

     NRF_RTC1->EVENTS_COMPARE[1] = 0;

+#if CORTEX_MODEL >= 4

+    (void)NRF_RTC1->EVENTS_COMPARE[1];

+#endif

     NRF_RTC1->TASKS_CLEAR = 1;

   }

 #endif

@@ -197,80 +219,92 @@ OSAL_IRQ_HANDLER(Vector84) {
 void st_lld_init(void) {

 #if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING

 

-#if NRF51_ST_USE_RTC0 == TRUE

+#if NRF5_ST_USE_RTC0 == TRUE

   /* Using RTC with prescaler */

   NRF_RTC0->TASKS_STOP  = 1;

-  NRF_RTC0->PRESCALER   = (NRF51_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1; 

+  NRF_RTC0->PRESCALER   = (NRF5_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1; 

   NRF_RTC0->EVTENCLR    = RTC_EVTENSET_COMPARE0_Msk;

   NRF_RTC0->EVENTS_COMPARE[0] = 0;

+#if CORTEX_MODEL >= 4

+  (void)NRF_RTC0->EVENTS_COMPARE[0];

+#endif

   NRF_RTC0->INTENSET    = RTC_INTENSET_COMPARE0_Msk;

 #if OSAL_ST_RESOLUTION == 16

   NRF_RTC0->CC[1]       = 0x10000; /* 2^16 */

   NRF_RTC0->EVENTS_COMPARE[1] = 0;

+#if CORTEX_MODEL >= 4

+  (void)NRF_RTC0->EVENTS_COMPARE[1];

+#endif

   NRF_RTC0->EVTENSET    = RTC_EVTENSET_COMPARE0_Msk;

   NRF_RTC0->INTENSET    = RTC_INTENSET_COMPARE1_Msk;

 #endif

   NRF_RTC0->TASKS_CLEAR  = 1;

 

     /* Start timer */

-  nvicEnableVector(RTC0_IRQn, NRF51_ST_PRIORITY);

+  nvicEnableVector(RTC0_IRQn, NRF5_ST_PRIORITY);

   NRF_RTC0->TASKS_START = 1;

-#endif /* NRF51_ST_USE_RTC0 == TRUE */

+#endif /* NRF5_ST_USE_RTC0 == TRUE */

 

-#if NRF51_ST_USE_RTC1 == TRUE

+#if NRF5_ST_USE_RTC1 == TRUE

   /* Using RTC with prescaler */

   NRF_RTC1->TASKS_STOP  = 1;

-  NRF_RTC1->PRESCALER   = (NRF51_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1; 

+  NRF_RTC1->PRESCALER   = (NRF5_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1; 

   NRF_RTC1->EVTENCLR    = RTC_EVTENSET_COMPARE0_Msk;

   NRF_RTC1->EVENTS_COMPARE[0] = 0;

+#if CORTEX_MODEL >= 4

+  (void)NRF_RTC1->EVENTS_COMPARE[0];

+#endif

   NRF_RTC1->INTENSET    = RTC_INTENSET_COMPARE0_Msk;

 #if OSAL_ST_RESOLUTION == 16

   NRF_RTC1->CC[1]       = 0x10000; /* 2^16 */

   NRF_RTC1->EVENTS_COMPARE[1] = 0;

+#if CORTEX_MODEL >= 4

+  NRF_RTC1->EVENTS_COMPARE[1];

+#endif

   NRF_RTC1->EVTENSET    = RTC_EVTENSET_COMPARE0_Msk;

   NRF_RTC1->INTENSET    = RTC_INTENSET_COMPARE1_Msk;

 #endif

   NRF_RTC1->TASKS_CLEAR  = 1;

 

   /* Start timer */

-  nvicEnableVector(RTC1_IRQn, NRF51_ST_PRIORITY);

+  nvicEnableVector(RTC1_IRQn, NRF5_ST_PRIORITY);

   NRF_RTC1->TASKS_START = 1;

-#endif /* NRF51_ST_USE_RTC1 == TRUE */

+#endif /* NRF5_ST_USE_RTC1 == TRUE */

 

 #endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */

 

 #if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC

 

-#if NRF51_ST_USE_RTC0 == TRUE

+#if NRF5_ST_USE_RTC0 == TRUE

   /* Using RTC with prescaler */

   NRF_RTC0->TASKS_STOP  = 1;

-  NRF_RTC0->PRESCALER   = (NRF51_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1; 

+  NRF_RTC0->PRESCALER   = (NRF5_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1; 

   NRF_RTC0->INTENSET    = RTC_INTENSET_TICK_Msk;

 

   /* Start timer */

-  nvicEnableVector(RTC0_IRQn, NRF51_ST_PRIORITY);

+  nvicEnableVector(RTC0_IRQn, NRF5_ST_PRIORITY);

   NRF_RTC0->TASKS_START = 1;

-#endif /* NRF51_ST_USE_RTC0 == TRUE */

+#endif /* NRF5_ST_USE_RTC0 == TRUE */

 

-#if NRF51_ST_USE_RTC1 == TRUE

+#if NRF5_ST_USE_RTC1 == TRUE

   /* Using RTC with prescaler */

   NRF_RTC1->TASKS_STOP  = 1;

-  NRF_RTC1->PRESCALER   = (NRF51_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1; 

+  NRF_RTC1->PRESCALER   = (NRF5_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1; 

   NRF_RTC1->INTENSET    = RTC_INTENSET_TICK_Msk;

 

   /* Start timer */

-  nvicEnableVector(RTC1_IRQn, NRF51_ST_PRIORITY);

+  nvicEnableVector(RTC1_IRQn, NRF5_ST_PRIORITY);

   NRF_RTC1->TASKS_START = 1;

-#endif /* NRF51_ST_USE_RTC1 == TRUE */

+#endif /* NRF5_ST_USE_RTC1 == TRUE */

 

-#if NRF51_ST_USE_TIMER0 == TRUE

+#if NRF5_ST_USE_TIMER0 == TRUE

   NRF_TIMER0->TASKS_CLEAR = 1;

 

   /*

-   * Using 32-bit mode with prescaler 16 configures this

-   * timer with a 1MHz clock.

+   * Using 32-bit mode with prescaler 1/16 configures this

+   * timer with a 1MHz clock, reducing power consumption.

    */

-  NRF_TIMER0->BITMODE = 3;

+  NRF_TIMER0->BITMODE = TIMER_BITMODE_BITMODE_32Bit;

   NRF_TIMER0->PRESCALER = 4;

 

   /*

@@ -279,12 +313,12 @@ void st_lld_init(void) {
    */

   NRF_TIMER0->CC[0] = (1000000 / OSAL_ST_FREQUENCY) - 1;

   NRF_TIMER0->SHORTS = 1;

-  NRF_TIMER0->INTENSET = 0x10000;

+  NRF_TIMER0->INTENSET = TIMER_INTENSET_COMPARE0_Msk;

 

   /* Start timer */

-  nvicEnableVector(TIMER0_IRQn, NRF51_ST_PRIORITY);

+  nvicEnableVector(TIMER0_IRQn, NRF5_ST_PRIORITY);

   NRF_TIMER0->TASKS_START = 1;

-#endif /* NRF51_ST_USE_TIMER0 == TRUE */

+#endif /* NRF5_ST_USE_TIMER0 == TRUE */

 

 #endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */

 }

diff --git a/os/hal/ports/NRF51/NRF51822/hal_st_lld.h b/os/hal/ports/NRF5/LLD/hal_st_lld.h
index 8d12d2e..93c2abb 100644
--- a/os/hal/ports/NRF51/NRF51822/hal_st_lld.h
+++ b/os/hal/ports/NRF5/LLD/hal_st_lld.h
@@ -15,8 +15,8 @@
 */

 

 /**

- * @file    st_lld.h

- * @brief   NRF51822 ST subsystem low level driver header.

+ * @file    NRF5/LLD/st_lld.h

+ * @brief   NRF5 ST subsystem low level driver header.

  * @details This header is designed to be include-able without having to

  *          include other files from the HAL.

  *

@@ -39,41 +39,38 @@
 

 /**

  * @brief   Use RTC0 to generates system ticks

+ *

+ * @note    Avoid using RTC0, as PPI has pre-programmed channels on it

+ *          that can be used to control RADIO or TIMER0

  */

-#if !defined(NRF51_ST_USE_RTC0) || defined(__DOXYGEN__)

-#if !defined(SOFTDEVICE_PRESENT)

-#define NRF51_ST_USE_RTC0        TRUE

-#else

-#define NRF51_ST_USE_RTC0        FALSE

-#endif

+#if !defined(NRF5_ST_USE_RTC0) || defined(__DOXYGEN__)

+#define NRF5_ST_USE_RTC0        FALSE

 #endif

 

 /**

  * @brief   Use RTC1 to generates system ticks

  */

-#if !defined(NRF51_ST_USE_RTC1) || defined(__DOXYGEN__)

-#if !defined(SOFTDEVICE_PRESENT)

-#define NRF51_ST_USE_RTC1        FALSE

-#else

-#define NRF51_ST_USE_RTC1        TRUE

-#endif

+#if !defined(NRF5_ST_USE_RTC1) || defined(__DOXYGEN__)

+#define NRF5_ST_USE_RTC1        TRUE

 #endif

 

 /**

  * @brief   Use TIMER0 to generates system ticks

+ *

+ * @note    Avoid using TIMER0 as it will draw more current

  */

-#if !defined(NRF51_ST_USE_TIMER0) || defined(__DOXYGEN__)

-#define NRF51_ST_USE_TIMER0      FALSE

+#if !defined(NRF5_ST_USE_TIMER0) || defined(__DOXYGEN__)

+#define NRF5_ST_USE_TIMER0      FALSE

 #endif

 

 /**

  * @brief   ST interrupt priority level setting.

  */

-#if !defined(NRF51_ST_PRIORITY) || defined(__DOXYGEN__)

+#if !defined(NRF5_ST_PRIORITY) || defined(__DOXYGEN__)

 #if !defined(SOFTDEVICE_PRESENT)

-#define NRF51_ST_PRIORITY        1

+#define NRF5_ST_PRIORITY        CORTEX_MAX_KERNEL_PRIORITY

 #else

-#define NRF51_ST_PRIORITY        1

+#define NRF5_ST_PRIORITY        1

 #endif

 #endif

 

@@ -82,32 +79,32 @@
 /*===========================================================================*/

 

 #if OSAL_ST_MODE != OSAL_ST_MODE_NONE

-#if (NRF51_ST_USE_TIMER0 == TRUE) && (NRF51_GPT_USE_TIMER0 == TRUE)

+#if (NRF5_ST_USE_TIMER0 == TRUE) && (NRF5_GPT_USE_TIMER0 == TRUE)

 #error "TIMER0 already used by GPT driver"

 #endif

 

-#if (NRF51_ST_USE_RTC0   == FALSE) && \

-    (NRF51_ST_USE_RTC1   == FALSE) && \

-    (NRF51_ST_USE_TIMER0 == FALSE)

+#if (NRF5_ST_USE_RTC0   == FALSE) && \

+    (NRF5_ST_USE_RTC1   == FALSE) && \

+    (NRF5_ST_USE_TIMER0 == FALSE)

 #error "One clock source is needed, enable one (RTC0, RTC1, or TIMER0)"

 #endif

 

-#if ((NRF51_ST_USE_RTC0   == TRUE ? 1 : 0) + \

-     (NRF51_ST_USE_RTC1   == TRUE ? 1 : 0) + \

-     (NRF51_ST_USE_TIMER0 == TRUE ? 1 : 0)) > 1

+#if ((NRF5_ST_USE_RTC0   == TRUE ? 1 : 0) + \

+     (NRF5_ST_USE_RTC1   == TRUE ? 1 : 0) + \

+     (NRF5_ST_USE_TIMER0 == TRUE ? 1 : 0)) > 1

 #error "Only one clock source can be used (RTC0, RTC1, or TIMER0)"

 #endif

 

 #if defined(SOFTDEVICE_PRESENT)

-#if NRF51_ST_USE_RTC0 == TRUE

+#if NRF5_ST_USE_RTC0 == TRUE

 #error "RTC0 cannot be used for system ticks when SOFTDEVICE present"

 #endif

 

-#if NRF51_ST_USE_TIMER0 == TRUE

+#if NRF5_ST_USE_TIMER0 == TRUE

 #error "TIMER0 cannot be used for system ticks when SOFTDEVICE present"

 #endif

 

-#if NRF51_ST_PRIORITY != 1

+#if NRF5_ST_PRIORITY != 1

 #error "ST priority must be 1 when SOFTDEVICE present"

 #endif

 

@@ -118,15 +115,16 @@
 #if defined(CH_CFG_ST_TIMEDELTA) && (CH_CFG_ST_TIMEDELTA < 5)

 #error "CH_CFG_ST_TIMEDELTA is too low"

 #endif

-#if NRF51_ST_USE_TIMER0 == TRUE

+#if NRF5_ST_USE_TIMER0 == TRUE

 #error "Freeruning (tick-less) mode not supported with TIMER, use RTC"

 #endif

 #endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */

 

-#if !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_ST_PRIORITY)

+#if !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_ST_PRIORITY)

 #error "Invalid IRQ priority assigned to ST driver"

 #endif

 

+

 /*===========================================================================*/

 /* Driver data structures and types.                                         */

 /*===========================================================================*/

@@ -159,13 +157,13 @@ extern "C" {
  * @notapi

  */

 static inline systime_t st_lld_get_counter(void) {

-#if NRF51_ST_USE_RTC0 == TRUE

+#if NRF5_ST_USE_RTC0 == TRUE

   return (systime_t)NRF_RTC0->COUNTER;

 #endif

-#if NRF51_ST_USE_RTC1 == TRUE

+#if NRF5_ST_USE_RTC1 == TRUE

   return (systime_t)NRF_RTC1->COUNTER;

 #endif

-#if NRF51_ST_USE_TIMER0 == TRUE

+#if NRF5_ST_USE_TIMER0 == TRUE

   return (systime_t)0;

 #endif

 }

@@ -180,17 +178,23 @@ static inline systime_t st_lld_get_counter(void) {
  * @notapi

  */

 static inline void st_lld_start_alarm(systime_t abstime) {

-#if NRF51_ST_USE_RTC0 == TRUE

+#if NRF5_ST_USE_RTC0 == TRUE

   NRF_RTC0->CC[0]               = abstime;

   NRF_RTC0->EVENTS_COMPARE[0]   = 0;

+#if CORTEX_MODEL >= 4

+  (void)NRF_RTC0->EVENTS_COMPARE[0];

+#endif

   NRF_RTC0->EVTENSET            = RTC_EVTENSET_COMPARE0_Msk;

 #endif

-#if NRF51_ST_USE_RTC1 == TRUE

+#if NRF5_ST_USE_RTC1 == TRUE

   NRF_RTC1->CC[0]               = abstime;

   NRF_RTC1->EVENTS_COMPARE[0]   = 0;

+#if CORTEX_MODEL >= 4

+  (void)NRF_RTC1->EVENTS_COMPARE[0];

+#endif

   NRF_RTC1->EVTENSET            = RTC_EVTENSET_COMPARE0_Msk;

 #endif

-#if NRF51_ST_USE_TIMER0 == TRUE

+#if NRF5_ST_USE_TIMER0 == TRUE

   (void)abstime;

 #endif

 }

@@ -201,13 +205,19 @@ static inline void st_lld_start_alarm(systime_t abstime) {
  * @notapi

  */

 static inline void st_lld_stop_alarm(void) {

-#if NRF51_ST_USE_RTC0 == TRUE

+#if NRF5_ST_USE_RTC0 == TRUE

   NRF_RTC0->EVTENCLR            = RTC_EVTENCLR_COMPARE0_Msk;

   NRF_RTC0->EVENTS_COMPARE[0]   = 0;

+#if CORTEX_MODEL >= 4

+  (void)NRF_RTC0->EVENTS_COMPARE[0];

+#endif

 #endif

-#if NRF51_ST_USE_RTC1 == TRUE

+#if NRF5_ST_USE_RTC1 == TRUE

   NRF_RTC1->EVTENCLR            = RTC_EVTENCLR_COMPARE0_Msk;

   NRF_RTC1->EVENTS_COMPARE[0]   = 0;

+#if CORTEX_MODEL >= 4

+  (void)NRF_RTC1->EVENTS_COMPARE[0];

+#endif

 #endif

 }

 

@@ -219,13 +229,13 @@ static inline void st_lld_stop_alarm(void) {
  * @notapi

  */

 static inline void st_lld_set_alarm(systime_t abstime) {

-#if NRF51_ST_USE_RTC0 == TRUE

+#if NRF5_ST_USE_RTC0 == TRUE

     NRF_RTC0->CC[0]             = abstime;

 #endif

-#if NRF51_ST_USE_RTC1 == TRUE

+#if NRF5_ST_USE_RTC1 == TRUE

     NRF_RTC1->CC[0]             = abstime;

 #endif

-#if NRF51_ST_USE_TIMER0 == TRUE

+#if NRF5_ST_USE_TIMER0 == TRUE

   (void)abstime;

 #endif

 }

@@ -238,13 +248,13 @@ static inline void st_lld_set_alarm(systime_t abstime) {
  * @notapi

  */

 static inline systime_t st_lld_get_alarm(void) {

-#if NRF51_ST_USE_RTC0 == TRUE

+#if NRF5_ST_USE_RTC0 == TRUE

   return (systime_t)NRF_RTC0->CC[0];

 #endif

-#if NRF51_ST_USE_RTC1 == TRUE

+#if NRF5_ST_USE_RTC1 == TRUE

   return (systime_t)NRF_RTC1->CC[0];

 #endif

-#if NRF51_ST_USE_TIMER0 == TRUE

+#if NRF5_ST_USE_TIMER0 == TRUE

   return (systime_t)0;

 #endif

 }

@@ -259,13 +269,13 @@ static inline systime_t st_lld_get_alarm(void) {
  * @notapi

  */

 static inline bool st_lld_is_alarm_active(void) {

-#if NRF51_ST_USE_RTC0 == TRUE

+#if NRF5_ST_USE_RTC0 == TRUE

   return NRF_RTC0->EVTEN & RTC_EVTEN_COMPARE0_Msk;

 #endif

-#if NRF51_ST_USE_RTC1 == TRUE

+#if NRF5_ST_USE_RTC1 == TRUE

   return NRF_RTC1->EVTEN & RTC_EVTEN_COMPARE0_Msk;

 #endif

-#if NRF51_ST_USE_TIMER0 == TRUE

+#if NRF5_ST_USE_TIMER0 == TRUE

   return false;

 #endif

 }

diff --git a/os/hal/ports/NRF51/NRF51822/hal_wdg_lld.c b/os/hal/ports/NRF5/LLD/hal_wdg_lld.c
index 0ce37ee..35c079f 100644
--- a/os/hal/ports/NRF51/NRF51822/hal_wdg_lld.c
+++ b/os/hal/ports/NRF5/LLD/hal_wdg_lld.c
@@ -15,8 +15,8 @@
 */

 

 /**

- * @file    NRF51822/wdg_lld.c

- * @brief   WDG Driver subsystem low level driver source template.

+ * @file    NRF5/LLD/hal_wdg_lld.c

+ * @brief   NRF5 Watchdog Driver subsystem low level driver source template.

  *

  * @addtogroup WDG

  * @{

@@ -55,12 +55,12 @@ WDGDriver WDGD1;
  * @brief   Watchdog vector.

  * @details This interrupt is used when watchdog timeout.

  *

- * @note    Only 2 cycles at NRF51_LFCLK_FREQUENCY are available

+ * @note    Only 2 cycles at NRF5_LFCLK_FREQUENCY are available

  *          to they good bye.

  *

  * @isr

  */

-OSAL_IRQ_HANDLER(Vector84) {

+OSAL_IRQ_HANDLER(Vector80) {

 

   OSAL_IRQ_PROLOGUE();

   osalSysLockFromISR();

@@ -101,18 +101,25 @@ void wdg_lld_init(void) {
  * @notapi

  */

 void wdg_lld_start(WDGDriver *wdgp) {

+  osalDbgAssert((wdgp->state == WDG_STOP),

+		"This WDG driver cannot be restarted once activated");

+

+  /* Generate interrupt on timeout */

 #if WDG_USE_TIMEOUT_CALLBACK == TRUE

   wdgp->wdt->INTENSET = WDT_INTENSET_TIMEOUT_Msk;

 #endif

 

   /* When to pause? (halt, sleep) */

-  wdgp->wdt->CONFIG      =

-      (wdgp->config->flags.pause_on_sleep * WDT_CONFIG_SLEEP_Msk) |

-      (wdgp->config->flags.pause_on_halt  * WDT_CONFIG_HALT_Msk );

+  uint32_t config = 0;

+  if (!wdgp->config->pause_on_sleep)

+      config |= WDT_CONFIG_SLEEP_Msk;

+  if (!wdgp->config->pause_on_halt)

+      config |= WDT_CONFIG_HALT_Msk;

+  wdgp->wdt->CONFIG = config;

 

   /* Timeout in milli-seconds */

-  uint64_t tout = (NRF51_LFCLK_FREQUENCY * wdgp->config->timeout_ms / 1000) - 1;

-  osalDbgAssert(tout <= 0xFFFFFFFF, "watchdog timout value exceeded");  

+  uint64_t tout = (NRF5_LFCLK_FREQUENCY * wdgp->config->timeout_ms / 1000) - 1;

+  osalDbgAssert(tout <= 0xFFFFFFFF, "watchdog timout value exceeded");

   wdgp->wdt->CRV         = (uint32_t)tout;

 

   /* Reload request (using RR0) */

@@ -131,7 +138,7 @@ void wdg_lld_start(WDGDriver *wdgp) {
  */

 void wdg_lld_stop(WDGDriver *wdgp) {

   (void)wdgp;

-  osalDbgAssert(false, "WDG cannot be stopped once activated");

+  osalDbgAssert(false, "This WDG driver cannot be stopped once activated");

 }

 

 /**

diff --git a/os/hal/ports/NRF51/NRF51822/hal_wdg_lld.h b/os/hal/ports/NRF5/LLD/hal_wdg_lld.h
index 8fea304..109b67e 100644
--- a/os/hal/ports/NRF51/NRF51822/hal_wdg_lld.h
+++ b/os/hal/ports/NRF5/LLD/hal_wdg_lld.h
@@ -15,8 +15,8 @@
 */

 

 /**

- * @file    NRF51822/wdg_lld.h

- * @brief   WDG Driver subsystem low level driver header template.

+ * @file    NRF5/LLD/hal_wdg_lld.h

+ * @brief   NRF5 Watchdog Driver subsystem low level driver header template.

  *

  * @addtogroup WDG

  * @{

@@ -32,7 +32,7 @@
 /*===========================================================================*/

 

 #define WDG_MAX_TIMEOUT_MS \

-    ((uint32_t)(0xFFFFFFFFu * 1000 / NRF51_LFCLK_FREQUENCY))

+    ((uint32_t)(0xFFFFFFFFu * 1000 / NRF5_LFCLK_FREQUENCY))

 

 /*===========================================================================*/

 /* Driver pre-compile time settings.                                         */

@@ -72,11 +72,27 @@ typedef struct WDGDriver WDGDriver;
  */

 typedef struct {

   struct {

-  uint8_t pause_on_sleep : 1;

-  uint8_t pause_on_halt  : 1;

-  } flags;

+    /**

+     * @brief Pause watchdog while the CPU is sleeping

+     */

+    uint8_t pause_on_sleep : 1;

+    /**

+     * @brief Pause watchdog while the CPU is halted by the debugger

+     */

+    uint8_t pause_on_halt  : 1;

+  };

+  /**

+   *

+   */

   uint32_t timeout_ms;

 #if WDG_USE_TIMEOUT_CALLBACK == TRUE

+  /**

+   * @brief  Notification callback when watchdog timedout

+   *

+   * @note   About 2 cycles at NRF5_LFCLK_FREQUENCY are available

+   *         before automatic reboot.

+   *

+   */

   void (*callback)(void);

 #endif

 } WDGConfig;

diff --git a/os/hal/ports/NRF51/NRF51822/hal_adc_lld.c b/os/hal/ports/NRF5/NRF51822/hal_adc_lld.c
index 7f3413c..6c0f2c6 100644
--- a/os/hal/ports/NRF51/NRF51822/hal_adc_lld.c
+++ b/os/hal/ports/NRF5/NRF51822/hal_adc_lld.c
@@ -36,7 +36,7 @@
 /*===========================================================================*/

 

 /** @brief ADC1 driver identifier.*/

-#if NRF51_ADC_USE_ADC1 || defined(__DOXYGEN__)

+#if NRF5_ADC_USE_ADC1 || defined(__DOXYGEN__)

 ADCDriver ADCD1;

 #endif

 

@@ -68,7 +68,7 @@ static void adc_lld_config_next_channel(ADCDriver *adcp, uint32_t config) {
 /* Driver interrupt handlers.                                                */

 /*===========================================================================*/

 

-#if NRF51_ADC_USE_ADC1 || defined(__DOXYGEN__)

+#if NRF5_ADC_USE_ADC1 || defined(__DOXYGEN__)

 /**

  * @brief   ADC interrupt handler.

  *

@@ -130,7 +130,7 @@ OSAL_IRQ_HANDLER(Vector5C) {
  */

 void adc_lld_init(void) {

 

-#if NRF51_ADC_USE_ADC1

+#if NRF5_ADC_USE_ADC1

   /* Driver initialization.*/

   adcObjectInit(&ADCD1);

   ADCD1.adc = NRF_ADC;

@@ -148,13 +148,13 @@ void adc_lld_start(ADCDriver *adcp) {
 

   /* If in stopped state then configures and enables the ADC. */

   if (adcp->state == ADC_STOP) {

-#if NRF51_ADC_USE_ADC1

+#if NRF5_ADC_USE_ADC1

     if (&ADCD1 == adcp) {

 

       adcp->adc->INTENSET = ADC_INTENSET_END_Enabled << ADC_INTENSET_END_Pos;

-      nvicEnableVector(ADC_IRQn, NRF51_ADC_IRQ_PRIORITY);

+      nvicEnableVector(ADC_IRQn, NRF5_ADC_IRQ_PRIORITY);

     }

-#endif /* NRF51_ADC_USE_ADC1 */

+#endif /* NRF5_ADC_USE_ADC1 */

   }

 }

 

@@ -170,7 +170,7 @@ void adc_lld_stop(ADCDriver *adcp) {
   /* If in ready state then disables the ADC clock and analog part.*/

   if (adcp->state == ADC_READY) {

 

-#if NRF51_ADC_USE_ADC1

+#if NRF5_ADC_USE_ADC1

     if (&ADCD1 == adcp) {

 

       nvicDisableVector(ADC_IRQn);

diff --git a/os/hal/ports/NRF51/NRF51822/hal_adc_lld.h b/os/hal/ports/NRF5/NRF51822/hal_adc_lld.h
index 36854fb..2ee30ac 100644
--- a/os/hal/ports/NRF51/NRF51822/hal_adc_lld.h
+++ b/os/hal/ports/NRF5/NRF51822/hal_adc_lld.h
@@ -44,15 +44,15 @@
  * @details If set to @p TRUE the support for ADC1 is included.

  * @note    The default is @p FALSE.

  */

-#if !defined(NRF51_ADC_USE_ADC1) || defined(__DOXYGEN__)

-#define NRF51_ADC_USE_ADC1                  FALSE

+#if !defined(NRF5_ADC_USE_ADC1) || defined(__DOXYGEN__)

+#define NRF5_ADC_USE_ADC1                  FALSE

 #endif

 

 /**

  * @brief   ADC interrupt priority level setting.

  */

-#if !defined(NRF51_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)

-#define NRF51_ADC_IRQ_PRIORITY              2

+#if !defined(NRF5_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define NRF5_ADC_IRQ_PRIORITY              2

 #endif

 

 /** @} */

@@ -61,12 +61,12 @@
 /* Derived constants and error checks.                                       */

 /*===========================================================================*/

 

-#if !NRF51_ADC_USE_ADC1

+#if !NRF5_ADC_USE_ADC1

 #error "ADC driver activated but no ADC peripheral assigned"

 #endif

 

-#if NRF51_ADC_USE_ADC1 &&                                                   \

-    !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_ADC_IRQ_PRIORITY)

+#if NRF5_ADC_USE_ADC1 &&                                                   \

+    !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_ADC_IRQ_PRIORITY)

 #error "Invalid IRQ priority assigned to ADC1"

 #endif

 

@@ -206,7 +206,7 @@ struct ADCDriver {
 /* External declarations.                                                    */

 /*===========================================================================*/

 

-#if NRF51_ADC_USE_ADC1 && !defined(__DOXYGEN__)

+#if NRF5_ADC_USE_ADC1 && !defined(__DOXYGEN__)

 extern ADCDriver ADCD1;

 #endif

 

diff --git a/os/hal/ports/NRF51/NRF51822/hal_ext_lld.c b/os/hal/ports/NRF5/NRF51822/hal_ext_lld.c
index 47736c7..47736c7 100644
--- a/os/hal/ports/NRF51/NRF51822/hal_ext_lld.c
+++ b/os/hal/ports/NRF5/NRF51822/hal_ext_lld.c
diff --git a/os/hal/ports/NRF51/NRF51822/hal_ext_lld.h b/os/hal/ports/NRF5/NRF51822/hal_ext_lld.h
index 37ae721..37ae721 100644
--- a/os/hal/ports/NRF51/NRF51822/hal_ext_lld.h
+++ b/os/hal/ports/NRF5/NRF51822/hal_ext_lld.h
diff --git a/os/hal/ports/NRF51/NRF51822/hal_ext_lld_isr.c b/os/hal/ports/NRF5/NRF51822/hal_ext_lld_isr.c
index 52f07d6..ca8e24d 100644
--- a/os/hal/ports/NRF51/NRF51822/hal_ext_lld_isr.c
+++ b/os/hal/ports/NRF5/NRF51822/hal_ext_lld_isr.c
@@ -92,7 +92,7 @@ OSAL_IRQ_HANDLER(Vector58) {
  */

 void ext_lld_exti_irq_enable(void) {

 

-  nvicEnableVector(GPIOTE_IRQn, NRF51_EXT_GPIOTE_IRQ_PRIORITY);

+  nvicEnableVector(GPIOTE_IRQn, NRF5_EXT_GPIOTE_IRQ_PRIORITY);

 }

 

 /**

diff --git a/os/hal/ports/NRF51/NRF51822/hal_ext_lld_isr.h b/os/hal/ports/NRF5/NRF51822/hal_ext_lld_isr.h
index 736e55c..d606866 100644
--- a/os/hal/ports/NRF51/NRF51822/hal_ext_lld_isr.h
+++ b/os/hal/ports/NRF5/NRF51822/hal_ext_lld_isr.h
@@ -42,8 +42,8 @@
 /**

  * @brief   GPIOTE interrupt priority level setting.

  */

-#if !defined(NRF51_EXT_GPIOTE_IRQ_PRIORITY) || defined(__DOXYGEN__)

-#define NRF51_EXT_GPIOTE_IRQ_PRIORITY      3

+#if !defined(NRF5_EXT_GPIOTE_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define NRF5_EXT_GPIOTE_IRQ_PRIORITY      3

 #endif

 /** @} */

 

diff --git a/os/hal/ports/NRF51/NRF51822/hal_lld.c b/os/hal/ports/NRF5/NRF51822/hal_lld.c
index af5e377..f33fdda 100644
--- a/os/hal/ports/NRF51/NRF51822/hal_lld.c
+++ b/os/hal/ports/NRF5/NRF51822/hal_lld.c
@@ -56,14 +56,16 @@
 void hal_lld_init(void)
 {
   /* High frequency clock initialisation
-   *  (If NRF51_XTAL_VALUE is not defined assume its an RC oscillator)
+   *  (If NRF5_XTAL_VALUE is not defined assume its an 16Mhz RC oscillator)
    */
   NRF_CLOCK->TASKS_HFCLKSTOP = 1;
-#if defined(NRF51_XTAL_VALUE)
-#if   NRF51_XTAL_VALUE == 16000000
+#if defined(NRF5_XTAL_VALUE)
+#if   NRF5_XTAL_VALUE == 16000000
   NRF_CLOCK->XTALFREQ = 0xFF;
-#elif NRF51_XTAL_VALUE == 32000000
+#elif NRF5_XTAL_VALUE == 32000000
   NRF_CLOCK->XTALFREQ = 0x00;
+#else
+#error "Unsupported XTAL value"
 #endif
 #endif
 
@@ -72,10 +74,10 @@ void hal_lld_init(void)
    * Clock is only started if st driver requires it
    */
   NRF_CLOCK->TASKS_LFCLKSTOP = 1;
-  NRF_CLOCK->LFCLKSRC = NRF51_LFCLK_SOURCE;
+  NRF_CLOCK->LFCLKSRC = NRF5_LFCLK_SOURCE;
   
 #if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) &&			\
-    (NRF51_SYSTEM_TICKS == NRF51_SYSTEM_TICKS_AS_RTC)
+    (NRF5_SYSTEM_TICKS == NRF5_SYSTEM_TICKS_AS_RTC)
   NRF_CLOCK->TASKS_LFCLKSTART = 1;
 #endif
 }
diff --git a/os/hal/ports/NRF51/NRF51822/hal_lld.h b/os/hal/ports/NRF5/NRF51822/hal_lld.h
index e404020..a1d2460 100644
--- a/os/hal/ports/NRF51/NRF51822/hal_lld.h
+++ b/os/hal/ports/NRF5/NRF51822/hal_lld.h
@@ -15,7 +15,7 @@
 */
 
 /**
- * @file    NRF51/NRF51822/hal_lld.h
+ * @file    NRF5/NRF51822/hal_lld.h
  * @brief   NRF51822 HAL subsystem low level driver header.
  *
  * @addtogroup HAL
@@ -36,13 +36,25 @@
 #define PLATFORM_NAME           "Nordic Semiconductor nRF51822"
 
 /**
- * @}
+ * @name    Chip series
+ */
+#define NRF_SERIES 51
+
+/**
+ * @brief  Frequency value for the Low Frequency Clock
+ */
+#define NRF5_LFCLK_FREQUENCY       32768
+
+/**
+ * @brief  Frequency value for the High Frequency Clock
  */
+#define NRF5_HFCLK_FREQUENCY       16000000
 
 /**
- * @brief  Frequency valuefor the Low Frequency Clock
+ * @}
  */
-#define NRF51_LFCLK_FREQUENCY  32768
+
+
 
 /*===========================================================================*/
 /* Driver pre-compile time settings.                                         */
@@ -57,16 +69,16 @@
  *          When cristal is not available it's preferable to use the
  *          internal RC oscillator that synthezing the clock.
  */
-#if !defined(NRF51_LFCLK_SOURCE) || defined(__DOXYGEN__)
-#define NRF51_LFCLK_SOURCE             0
+#if !defined(NRF5_LFCLK_SOURCE) || defined(__DOXYGEN__)
+#define NRF5_LFCLK_SOURCE             0
 #endif
 
 /*===========================================================================*/
 /* Derived constants and error checks.                                       */
 /*===========================================================================*/
 
-#if (NRF51_LFCLK_SOURCE < 0) || (NRF51_LFCLK_SOURCE > 2)
-#error "Possible value for NRF51_LFCLK_SOURCE are 0=RC, 1=XTAL, 2=Synth"
+#if (NRF5_LFCLK_SOURCE < 0) || (NRF5_LFCLK_SOURCE > 2)
+#error "Possible value for NRF5_LFCLK_SOURCE are 0=RC, 1=XTAL, 2=Synth"
 #endif
 
 /*===========================================================================*/
@@ -83,14 +95,11 @@
 
 #include "nvic.h"
 
-#define NRF51_LFCLK_FREQUENCY       32768
-#define NRF51_HFCLK_FREQUENCY       16000000
 
 #ifdef __cplusplus
 extern "C" {
 #endif
   void hal_lld_init(void);
-  void nrf51_clock_init(void);
 #ifdef __cplusplus
 }
 #endif
diff --git a/os/hal/ports/NRF51/NRF51822/hal_pwm_lld.c b/os/hal/ports/NRF5/NRF51822/hal_pwm_lld.c
index 456dcff..e2b4b6b 100644
--- a/os/hal/ports/NRF51/NRF51822/hal_pwm_lld.c
+++ b/os/hal/ports/NRF5/NRF51822/hal_pwm_lld.c
@@ -18,6 +18,11 @@
  * @file    hal_pwm_lld.c

  * @brief   NRF51 PWM subsystem low level driver source.

  *

+ * @note    Using the method described in nrf51-pwm-library to correctly

+ *          handle toggling of the pin with GPIOTE when changing period.

+ *          It means it is generally unsafe to use GPIOTE with a period

+ *          less than (2 * PWM_GPIOTE_DECISION_TIME / 16MHz)

+ *

  * @addtogroup PWM

  * @{

  */

@@ -30,6 +35,8 @@
 /* Driver local definitions.                                                 */

 /*===========================================================================*/

 

+#define PWM_GPIOTE_PPI_CC 3

+#define PWM_GPIOTE_DECISION_TIME 160

 

 /*===========================================================================*/

 /* Driver exported variables.                                                */

@@ -39,7 +46,7 @@
  * @brief   PWMD1 driver identifier.

  * @note    The driver PWMD1 allocates the timer TIMER0 when enabled.

  */

-#if NRF51_PWM_USE_TIMER0 || defined(__DOXYGEN__)

+#if NRF5_PWM_USE_TIMER0 || defined(__DOXYGEN__)

 PWMDriver PWMD1;

 #endif

 

@@ -47,7 +54,7 @@ PWMDriver PWMD1;
  * @brief   PWMD2 driver identifier.

  * @note    The driver PWMD2 allocates the timer TIMER1 when enabled.

  */

-#if NRF51_PWM_USE_TIMER1 || defined(__DOXYGEN__)

+#if NRF5_PWM_USE_TIMER1 || defined(__DOXYGEN__)

 PWMDriver PWMD2;

 #endif

 

@@ -55,7 +62,7 @@ PWMDriver PWMD2;
  * @brief   PWMD3 driver identifier.

  * @note    The driver PWMD3 allocates the timer TIMER2 when enabled.

  */

-#if NRF51_PWM_USE_TIMER2 || defined(__DOXYGEN__)

+#if NRF5_PWM_USE_TIMER2 || defined(__DOXYGEN__)

 PWMDriver PWMD3;

 #endif

 

@@ -63,24 +70,39 @@ PWMDriver PWMD3;
 /* Driver local variables and types.                                         */

 /*===========================================================================*/

 

+static const uint8_t pwm_margin_by_prescaler[] = {

+  (PWM_GPIOTE_DECISION_TIME +   0) >> 0,

+  (PWM_GPIOTE_DECISION_TIME +   1) >> 1,

+  (PWM_GPIOTE_DECISION_TIME +   3) >> 2,

+  (PWM_GPIOTE_DECISION_TIME +   7) >> 3,

+  (PWM_GPIOTE_DECISION_TIME +  15) >> 4,

+  (PWM_GPIOTE_DECISION_TIME +  31) >> 5,

+  (PWM_GPIOTE_DECISION_TIME +  63) >> 6,

+  (PWM_GPIOTE_DECISION_TIME + 127) >> 7,

+  (PWM_GPIOTE_DECISION_TIME + 255) >> 8,

+  (PWM_GPIOTE_DECISION_TIME + 511) >> 9

+};

+

 /*===========================================================================*/

 /* Driver local functions.                                                   */

 /*===========================================================================*/

 

 static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {

-  // Deal with PWM channels     

-  uint8_t n;

-  for (n = 0 ; n < pwmp->channels ; n++) {

-    if (pwmp->timer->EVENTS_COMPARE[n]) {

-      pwmp->timer->EVENTS_COMPARE[n] = 0;

-

-      if (pwmp->config->channels[n].callback != NULL) {

-	pwmp->config->channels[n].callback(pwmp);

+  uint8_t channel;

+  /* Deal with PWM channels

+   */

+  for (channel = 0 ; channel < pwmp->channels ; channel++) {

+    if (pwmp->timer->EVENTS_COMPARE[channel]) {

+      pwmp->timer->EVENTS_COMPARE[channel] = 0;

+

+      if (pwmp->config->channels[channel].callback != NULL) {

+        pwmp->config->channels[channel].callback(pwmp);

       }

     }      

   }

 

-  // Deal with PWM period

+  /* Deal with PWM period

+   */

   if (pwmp->timer->EVENTS_COMPARE[pwmp->channels]) {

     pwmp->timer->EVENTS_COMPARE[pwmp->channels] = 0;

 

@@ -88,14 +110,21 @@ static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
       pwmp->config->callback(pwmp);

     }

   }

+}

 

+static inline

+bool pwm_within_safe_margins(PWMDriver *pwmp, uint32_t timer, uint32_t width)  {

+  const uint32_t margin = pwm_margin_by_prescaler[pwmp->timer->PRESCALER];

+  return (width <= margin)

+       ? ((width <= timer) && (timer < (pwmp->period + width - margin)))

+       : ((width <= timer) || (timer < (width - margin)));

 }

 

 /*===========================================================================*/

 /* Driver interrupt handlers.                                                */

 /*===========================================================================*/

 

-#if NRF51_PWM_USE_TIMER0

+#if NRF5_PWM_USE_TIMER0

 /**

  * @brief   TIMER0 interrupt handler.

  *

@@ -106,9 +135,9 @@ OSAL_IRQ_HANDLER(Vector60) {
   pwm_lld_serve_interrupt(&PWMD1);

   OSAL_IRQ_EPILOGUE();

 }

-#endif /* NRF51_PWM_USE_TIMER0 */

+#endif /* NRF5_PWM_USE_TIMER0 */

 

-#if NRF51_PWM_USE_TIMER1

+#if NRF5_PWM_USE_TIMER1

 /**

  * @brief   TIMER1 interrupt handler.

  *

@@ -119,9 +148,9 @@ OSAL_IRQ_HANDLER(Vector64) {
   pwm_lld_serve_interrupt(&PWMD2);

   OSAL_IRQ_EPILOGUE();

 }

-#endif /* NRF51_PWM_USE_TIMER1 */

+#endif /* NRF5_PWM_USE_TIMER1 */

 

-#if NRF51_PWM_USE_TIMER2

+#if NRF5_PWM_USE_TIMER2

 /**

  * @brief   TIMER2 interrupt handler.

  *

@@ -132,7 +161,7 @@ OSAL_IRQ_HANDLER(Vector68) {
   pwm_lld_serve_interrupt(&PWMD3);

   OSAL_IRQ_EPILOGUE();

 }

-#endif /* NRF51_PWM_USE_TIMER2 */

+#endif /* NRF5_PWM_USE_TIMER2 */

 

 /*===========================================================================*/

 /* Driver exported functions.                                                */

@@ -145,19 +174,19 @@ OSAL_IRQ_HANDLER(Vector68) {
  */

 void pwm_lld_init(void) {

 

-#if NRF51_PWM_USE_TIMER0

+#if NRF5_PWM_USE_TIMER0

   pwmObjectInit(&PWMD1);

   PWMD1.channels = PWM_CHANNELS;

   PWMD1.timer = NRF_TIMER0;

 #endif

 

-#if NRF51_PWM_USE_TIMER1

+#if NRF5_PWM_USE_TIMER1

   pwmObjectInit(&PWMD2);

   PWMD2.channels = PWM_CHANNELS;

   PWMD2.timer = NRF_TIMER1;

 #endif

 

-#if NRF51_PWM_USE_TIMER2

+#if NRF5_PWM_USE_TIMER2

   pwmObjectInit(&PWMD3);

   PWMD3.channels = PWM_CHANNELS;

   PWMD3.timer = NRF_TIMER2;

@@ -174,66 +203,64 @@ void pwm_lld_init(void) {
  * @notapi

  */

 void pwm_lld_start(PWMDriver *pwmp) {

-  // Prescaler value calculation: ftimer = 16MHz / 2^PRESCALER

-  uint16_t psc_ratio = NRF51_HFCLK_FREQUENCY / pwmp->config->frequency;

-  // Prescaler ratio must be between 1 and 512, and a power of two.

+  /* Prescaler value calculation: ftimer = 16MHz / 2^PRESCALER */

+  uint16_t psc_ratio = NRF5_HFCLK_FREQUENCY / pwmp->config->frequency;

+  /* Prescaler ratio must be between 1 and 512, and a power of two. */

   osalDbgAssert(psc_ratio <= 512 && !(psc_ratio & (psc_ratio - 1)),

-		"invalid frequency");

-  // Prescaler value as a power of 2, must be 0..9

+                "invalid frequency");

+  /* Prescaler value as a power of 2, must be 0..9 */

   uint32_t psc_value;

   for (psc_value = 0; psc_value < 10; psc_value++)

-      if (psc_ratio == (unsigned)(1 << psc_value))

-	  break;

+    if (psc_ratio == (unsigned)(1 << psc_value))

+      break;

 

-  

-  // Configure as 16bits timer (only TIMER0 support 32bits)

+  /* Configure as 16bits timer (only TIMER0 support 32bits) */

   pwmp->timer->BITMODE = TIMER_BITMODE_BITMODE_16Bit;

   pwmp->timer->MODE = TIMER_MODE_MODE_Timer;

 

-  // With clear shortcuts for period

+  /* With clear shortcuts for period */

   pwmp->timer->SHORTS =

-      0x1UL << (TIMER_SHORTS_COMPARE0_CLEAR_Pos + pwmp->channels);

+    0x1UL << (TIMER_SHORTS_COMPARE0_CLEAR_Pos + pwmp->channels);

 

-  // Disable and reset interrupts for compare events

+  /* Disable and reset interrupts for compare events */

   pwmp->timer->INTENCLR = (TIMER_INTENCLR_COMPARE0_Msk |

-			   TIMER_INTENCLR_COMPARE1_Msk |

-			   TIMER_INTENCLR_COMPARE2_Msk |

-			   TIMER_INTENCLR_COMPARE3_Msk );

+                           TIMER_INTENCLR_COMPARE1_Msk |

+                           TIMER_INTENCLR_COMPARE2_Msk |

+                           TIMER_INTENCLR_COMPARE3_Msk );

   pwmp->timer->EVENTS_COMPARE[0] = 0;

   pwmp->timer->EVENTS_COMPARE[1] = 0;

   pwmp->timer->EVENTS_COMPARE[2] = 0;

   pwmp->timer->EVENTS_COMPARE[3] = 0;

 

-  // Set prescaler

+  /* Set prescaler */

   pwmp->timer->PRESCALER = psc_value;

 

-  // Set period

+  /* Set period */

   pwmp->timer->CC[pwmp->channels] = pwmp->period; 

 

-  // Clear everything

+  /* Clear everything */

   pwmp->timer->TASKS_CLEAR = 1;

 

-

-  // Enable interrupt

-#if NRF51_PWM_USE_TIMER0

+  /* Enable interrupt */

+#if NRF5_PWM_USE_TIMER0

   if (&PWMD1 == pwmp) {

-    nvicEnableVector(TIMER0_IRQn, NRF51_PWM_TIMER0_PRIORITY);

+    nvicEnableVector(TIMER0_IRQn, NRF5_PWM_TIMER0_PRIORITY);

   }

 #endif

 

-#if NRF51_PWM_USE_TIMER1

+#if NRF5_PWM_USE_TIMER1

   if (&PWMD2 == pwmp) {

-    nvicEnableVector(TIMER1_IRQn, NRF51_PWM_TIMER1_PRIORITY);

+    nvicEnableVector(TIMER1_IRQn, NRF5_PWM_TIMER1_PRIORITY);

   }

 #endif

 

-#if NRF51_PWM_USE_TIMER2

+#if NRF5_PWM_USE_TIMER2

   if (&PWMD3 == pwmp) {

-    nvicEnableVector(TIMER2_IRQn, NRF51_PWM_TIMER2_PRIORITY);

+    nvicEnableVector(TIMER2_IRQn, NRF5_PWM_TIMER2_PRIORITY);

   }

 #endif

 

-  // Start timer

+  /* Start timer */

   pwmp->timer->TASKS_START = 1;

 }

 

@@ -245,21 +272,21 @@ void pwm_lld_start(PWMDriver *pwmp) {
  * @notapi

  */

 void pwm_lld_stop(PWMDriver *pwmp) {

-  pwmp->timer->TASKS_STOP = 1;

+  pwmp->timer->TASKS_SHUTDOWN = 1;

 

-#if NRF51_PWM_USE_TIMER0

+#if NRF5_PWM_USE_TIMER0

   if (&PWMD1 == pwmp) {

     nvicDisableVector(TIMER0_IRQn);

   }

 #endif

 

-#if NRF51_PWM_USE_TIMER1

+#if NRF5_PWM_USE_TIMER1

   if (&PWMD2 == pwmp) {

     nvicDisableVector(TIMER1_IRQn);

   }

 #endif

 

-#if NRF51_PWM_USE_TIMER2

+#if NRF5_PWM_USE_TIMER2

   if (&PWMD3 == pwmp) {

     nvicDisableVector(TIMER2_IRQn);

   }

@@ -282,43 +309,83 @@ void pwm_lld_stop(PWMDriver *pwmp) {
 void pwm_lld_enable_channel(PWMDriver *pwmp,

                             pwmchannel_t channel,

                             pwmcnt_t width) {

-#if NRF51_PWM_USE_GPIOTE_PPI

+#if NRF5_PWM_USE_GPIOTE_PPI

   const PWMChannelConfig *cfg_channel = &pwmp->config->channels[channel];

-

+  const uint8_t  gpiote_channel = cfg_channel->gpiote_channel;

+  const uint8_t *ppi_channel    = cfg_channel->ppi_channel;

+  

   uint32_t outinit;

   switch(cfg_channel->mode & PWM_OUTPUT_MASK) {

-  case PWM_OUTPUT_ACTIVE_LOW:

-    outinit = GPIOTE_CONFIG_OUTINIT_Low;

-    break;

-  case PWM_OUTPUT_ACTIVE_HIGH:

-    outinit = GPIOTE_CONFIG_OUTINIT_High;

-    break;

-  case PWM_OUTPUT_DISABLED:

-  default:

-      goto no_output_config;

+  case PWM_OUTPUT_ACTIVE_LOW : outinit = GPIOTE_CONFIG_OUTINIT_Low;  break;

+  case PWM_OUTPUT_ACTIVE_HIGH: outinit = GPIOTE_CONFIG_OUTINIT_High; break;

+  case PWM_OUTPUT_DISABLED   : /* fall-through */

+  default                    : goto no_output_config;

   }

 

-  const uint32_t gpio_pin       = PAL_PAD(cfg_channel->ioline);

-  const uint8_t  gpiote_channel = cfg_channel->gpiote_channel;

-  const uint8_t *ppi_channel    = cfg_channel->ppi_channel;

-  const uint32_t polarity       = GPIOTE_CONFIG_POLARITY_Toggle;

-

-  // Create GPIO Task

-  NRF_GPIOTE->CONFIG[gpiote_channel] = GPIOTE_CONFIG_MODE_Task |

-      ((gpio_pin << GPIOTE_CONFIG_PSEL_Pos    ) & GPIOTE_CONFIG_PSEL_Msk) |

-      ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) |

-      ((outinit  << GPIOTE_CONFIG_OUTINIT_Pos ) & GPIOTE_CONFIG_OUTINIT_Msk);

-

-  // Program tasks (one for duty cycle, one for periode)

-  NRF_PPI->CH[ppi_channel[0]].EEP =

+  /* Deal with corner case: 0% and 100% */

+  if ((width <= 0) || (width >= pwmp->period)) {

+      /* Disable GPIOTE/PPI task */

+    NRF_GPIOTE->CONFIG[gpiote_channel] = GPIOTE_CONFIG_MODE_Disabled;

+    NRF_PPI->CHENCLR = ((1 << ppi_channel[0]) | (1 << ppi_channel[1]));

+    /* Set Line */

+    palWriteLine(cfg_channel->ioline,

+           ((width <= 0) ^

+            ((cfg_channel->mode & PWM_OUTPUT_MASK) == PWM_OUTPUT_ACTIVE_HIGH)));

+

+  /* Really doing PWM */

+  } else {

+    const uint32_t gpio_pin = PAL_PAD(cfg_channel->ioline);

+    const uint32_t polarity = GPIOTE_CONFIG_POLARITY_Toggle;

+

+    /* Program tasks (one for duty cycle, one for periode) */

+    NRF_PPI->CH[ppi_channel[0]].EEP =

       (uint32_t)&pwmp->timer->EVENTS_COMPARE[channel];

-  NRF_PPI->CH[ppi_channel[0]].TEP =

+    NRF_PPI->CH[ppi_channel[0]].TEP =

       (uint32_t)&NRF_GPIOTE->TASKS_OUT[gpiote_channel];

-  NRF_PPI->CH[ppi_channel[1]].EEP =

+    NRF_PPI->CH[ppi_channel[1]].EEP =

       (uint32_t)&pwmp->timer->EVENTS_COMPARE[pwmp->channels];

-  NRF_PPI->CH[ppi_channel[1]].TEP =

+    NRF_PPI->CH[ppi_channel[1]].TEP =

       (uint32_t)&NRF_GPIOTE->TASKS_OUT[gpiote_channel];

-  NRF_PPI->CHENSET = ((1 << ppi_channel[0]) | (1 << ppi_channel[1]));

+    NRF_PPI->CHENSET = ((1 << ppi_channel[0]) | (1 << ppi_channel[1]));

+

+    /* Something Old, something New */

+    const uint32_t old_width = pwmp->timer->CC[channel];

+    const uint32_t new_width = width;

+

+    /* Check GPIOTE state */

+    const bool gpiote = (NRF_GPIOTE->CONFIG[gpiote_channel] &

+                   GPIOTE_CONFIG_MODE_Msk) != GPIOTE_CONFIG_MODE_Disabled;

+

+    /* GPIOTE is currently running */

+    if (gpiote) {

+      uint32_t current;

+      while (true) {

+        pwmp->timer->TASKS_CAPTURE[PWM_GPIOTE_PPI_CC] = 1;

+        current = pwmp->timer->CC[PWM_GPIOTE_PPI_CC];

+

+        if (pwm_within_safe_margins(pwmp, current, old_width) &&

+            pwm_within_safe_margins(pwmp, current, new_width))

+          break;

+      }

+      if (((old_width <= current) && (current < new_width)) ||

+          ((new_width <= current) && (current < old_width))) {

+        NRF_GPIOTE->TASKS_OUT[gpiote_channel] = 1;

+      }

+

+    /* GPIOTE need to be restarted */

+    } else {

+      /* Create GPIO Task */

+      NRF_GPIOTE->CONFIG[gpiote_channel] =

+        (GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos) |

+        ((gpio_pin << GPIOTE_CONFIG_PSEL_Pos    ) & GPIOTE_CONFIG_PSEL_Msk    )|

+        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk)|

+        ((outinit  << GPIOTE_CONFIG_OUTINIT_Pos ) & GPIOTE_CONFIG_OUTINIT_Msk );

+

+      pwmp->timer->TASKS_CAPTURE[PWM_GPIOTE_PPI_CC] = 1;

+      if (pwmp->timer->CC[PWM_GPIOTE_PPI_CC] > width)

+        NRF_GPIOTE->TASKS_OUT[gpiote_channel] = 1;

+    }

+  }

 

  no_output_config:

 #endif

@@ -340,7 +407,7 @@ void pwm_lld_enable_channel(PWMDriver *pwmp,
  */

 void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {

   pwmp->timer->CC[channel] = 0;

-#if NRF51_PWM_USE_GPIOTE_PPI

+#if NRF5_PWM_USE_GPIOTE_PPI

   const PWMChannelConfig *cfg_channel = &pwmp->config->channels[channel];

   switch(cfg_channel->mode & PWM_OUTPUT_MASK) {

   case PWM_OUTPUT_ACTIVE_LOW:

@@ -369,7 +436,7 @@ void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
  */

 void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) {

   pwmp->timer->INTENSET =

-      0x1UL << (TIMER_INTENSET_COMPARE0_Pos + pwmp->channels);

+    0x1UL << (TIMER_INTENSET_COMPARE0_Pos + pwmp->channels);

 }

 

 /**

@@ -383,7 +450,7 @@ void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) {
  */

 void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) {

   pwmp->timer->INTENCLR =

-      0x1UL << (TIMER_INTENCLR_COMPARE0_Pos + pwmp->channels);

+    0x1UL << (TIMER_INTENCLR_COMPARE0_Pos + pwmp->channels);

 }

 

 /**

@@ -400,7 +467,7 @@ void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) {
 void pwm_lld_enable_channel_notification(PWMDriver *pwmp,

                                          pwmchannel_t channel) {

   pwmp->timer->INTENSET =

-      0x1UL << (TIMER_INTENSET_COMPARE0_Pos + channel);

+    0x1UL << (TIMER_INTENSET_COMPARE0_Pos + channel);

 }

 

 /**

@@ -409,15 +476,15 @@ void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
  * @pre     The channel must have been activated using @p pwmEnableChannel().

  * @note    If the notification is already disabled then the call has no effect.

  *

- * @param[in] pwmp      pointer to a @p PWMDriver object

- * @param[in] channel   PWM channel identifier (0...channels-1)

+ * @param[in] pwmp	pointer to a @p PWMDriver object

+ * @param[in] channel	PWM channel identifier (0...channels-1)

  *

  * @notapi

  */

 void pwm_lld_disable_channel_notification(PWMDriver *pwmp,

-                                          pwmchannel_t channel) {

+					  pwmchannel_t channel) {

   pwmp->timer->INTENCLR =

-      0x1UL << (TIMER_INTENCLR_COMPARE0_Pos + channel);

+    0x1UL << (TIMER_INTENCLR_COMPARE0_Pos + channel);

 }

 

 #endif /* HAL_USE_PWM */

diff --git a/os/hal/ports/NRF51/NRF51822/hal_pwm_lld.h b/os/hal/ports/NRF5/NRF51822/hal_pwm_lld.h
index e2982d8..2cad6e7 100644
--- a/os/hal/ports/NRF51/NRF51822/hal_pwm_lld.h
+++ b/os/hal/ports/NRF5/NRF51822/hal_pwm_lld.h
@@ -34,8 +34,11 @@
 /**

  * @brief   Number of PWM channels per PWM driver.

  */

+#if NRF5_PWM_USE_GPIOTE_PPI

+#define PWM_CHANNELS                            2

+#else

 #define PWM_CHANNELS                            3

-

+#endif

 

 #define PWM_FREQUENCY_16MHZ  16000000 /** @brief   16MHz */

 #define PWM_FREQUENCY_8MHZ    8000000 /** @brief    8MHz */

@@ -60,50 +63,50 @@
 /**

  * @brief   TIMER0 as driver implementation

  */

-#if !defined(NRF51_PWM_USE_TIMER0)

-#define NRF51_PWM_USE_TIMER0 FALSE

+#if !defined(NRF5_PWM_USE_TIMER0)

+#define NRF5_PWM_USE_TIMER0 FALSE

 #endif

 

 /**

  * @brief   TIMER1 as driver implementation

  */

-#if !defined(NRF51_PWM_USE_TIMER1)

-#define NRF51_PWM_USE_TIMER1 FALSE

+#if !defined(NRF5_PWM_USE_TIMER1)

+#define NRF5_PWM_USE_TIMER1 FALSE

 #endif

 

 /**

  * @brief   TIMER2 as driver implementation

  */

-#if !defined(NRF51_PWM_USE_TIMER2)

-#define NRF51_PWM_USE_TIMER2 FALSE

+#if !defined(NRF5_PWM_USE_TIMER2)

+#define NRF5_PWM_USE_TIMER2 FALSE

 #endif

 

 /**

  * @brief   TIMER0 interrupt priority level setting.

  */

-#if !defined(NRF51_PWM_TIMER0_PRIORITY) || defined(__DOXYGEN__)

-#define NRF51_PWM_TIMER0_PRIORITY        3

+#if !defined(NRF5_PWM_TIMER0_PRIORITY) || defined(__DOXYGEN__)

+#define NRF5_PWM_TIMER0_PRIORITY        3

 #endif

 

 /**

  * @brief   TIMER1 interrupt priority level setting.

  */

-#if !defined(NRF51_PWM_TIMER1_PRIORITY) || defined(__DOXYGEN__)

-#define NRF51_PWM_TIMER1_PRIORITY        3

+#if !defined(NRF5_PWM_TIMER1_PRIORITY) || defined(__DOXYGEN__)

+#define NRF5_PWM_TIMER1_PRIORITY        3

 #endif

 

 /**

  * @brief   TIMER2 interrupt priority level setting.

  */

-#if !defined(NRF51_PWM_TIMER2_PRIORITY) || defined(__DOXYGEN__)

-#define NRF51_PWM_TIMER2_PRIORITY        3

+#if !defined(NRF5_PWM_TIMER2_PRIORITY) || defined(__DOXYGEN__)

+#define NRF5_PWM_TIMER2_PRIORITY        3

 #endif

 

 /**

  * @brief   Allow driver to use GPIOTE/PPI to control PAL line

  */

-#if !defined(NRF51_PWM_USE_GPIOTE_PPI)

-#define NRF51_PWM_USE_GPIOTE_PPI FALSE

+#if !defined(NRF5_PWM_USE_GPIOTE_PPI)

+#define NRF5_PWM_USE_GPIOTE_PPI TRUE

 #endif

 

 /** @} */

@@ -112,26 +115,26 @@
 /* Configuration checks.                                                     */

 /*===========================================================================*/

 

-#if !NRF51_PWM_USE_TIMER0 && !NRF51_PWM_USE_TIMER1 && !NRF51_PWM_USE_TIMER2

+#if !NRF5_PWM_USE_TIMER0 && !NRF5_PWM_USE_TIMER1 && !NRF5_PWM_USE_TIMER2

 #error "PWM driver activated but no TIMER peripheral assigned"

 #endif

 

-#if (NRF51_ST_USE_TIMER0 == TRUE) && (NRF51_PWM_USE_TIMER0 == TRUE)

+#if (NRF5_ST_USE_TIMER0 == TRUE) && (NRF5_PWM_USE_TIMER0 == TRUE)

 #error "TIMER0 used for ST and PWM"

 #endif

 

-#if NRF51_PWM_USE_TIMER0 &&						    \

-    !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_PWM_TIMER0_PRIORITY)

+#if NRF5_PWM_USE_TIMER0 &&						    \

+    !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_PWM_TIMER0_PRIORITY)

 #error "Invalid IRQ priority assigned to TIMER0"

 #endif

 

-#if NRF51_PWM_USE_TIMER1 &&						    \

-    !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_PWM_TIMER1_PRIORITY)

+#if NRF5_PWM_USE_TIMER1 &&						    \

+    !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_PWM_TIMER1_PRIORITY)

 #error "Invalid IRQ priority assigned to TIMER1"

 #endif

 

-#if NRF51_PWM_USE_TIMER2 &&						    \

-    !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_PWM_TIMER2_PRIORITY)

+#if NRF5_PWM_USE_TIMER2 &&						    \

+    !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_PWM_TIMER2_PRIORITY)

 #error "Invalid IRQ priority assigned to TIMER2"

 #endif

 

@@ -177,26 +180,24 @@ typedef struct {
   pwmcallback_t             callback;

   /* End of the mandatory fields.*/

 

+#if NRF5_PWM_USE_GPIOTE_PPI || defined(__DOXYGEN__)

   /**

    * @brief PAL line to toggle.

    * @note  Only used if mode is PWM_OUTPUT_HIGH or PWM_OUTPUT_LOW.

-   * @note  When NRF51_PWM_USE_GPIOTE_PPI is used and channel enabled,

+   * @note  When NRF5_PWM_USE_GPIOTE_PPI is used and channel enabled,

    *        it wont be possible to access this PAL line using the PAL

    *        driver.

    */

   ioline_t ioline;

 

-#if NRF51_PWM_USE_GPIOTE_PPI || defined(__DOXYGEN__)

   /**

    * @brief Unique GPIOTE channel to use. (1 channel)

-   * @note  Only used if mode is PWM_OUTPUT_HIGH or PWM_OUTPUT_LOW.

    * @note  Only 4 GPIOTE channels are available on nRF51.

    */

   uint8_t gpiote_channel;

 

   /**

    * @brief Unique PPI channels to use. (2 channels)

-   * @note  Only used if mode is PWM_OUTPUT_HIGH or PWM_OUTPUT_LOW.

    * @note  Only 16 PPI channels are available on nRF51

    *        (When Softdevice is enabled, only channels 0-7 are available)

    */

@@ -296,13 +297,13 @@ struct PWMDriver {
 /* External declarations.                                                    */

 /*===========================================================================*/

 

-#if NRF51_PWM_USE_TIMER0 || defined(__DOXYGEN__)

+#if NRF5_PWM_USE_TIMER0 || defined(__DOXYGEN__)

 extern PWMDriver PWMD1;

 #endif

-#if NRF51_PWM_USE_TIMER1 || defined(__DOXYGEN__)

+#if NRF5_PWM_USE_TIMER1 || defined(__DOXYGEN__)

 extern PWMDriver PWMD2;

 #endif

-#if NRF51_PWM_USE_TIMER2 || defined(__DOXYGEN__)

+#if NRF5_PWM_USE_TIMER2 || defined(__DOXYGEN__)

 extern PWMDriver PWMD3;

 #endif

 

diff --git a/os/hal/ports/NRF51/NRF51822/nrf51.h b/os/hal/ports/NRF5/NRF51822/nrf51.h
index 1ed33d6..0b63f7c 100644
--- a/os/hal/ports/NRF51/NRF51822/nrf51.h
+++ b/os/hal/ports/NRF5/NRF51822/nrf51.h
@@ -6,28 +6,28 @@
  *           nrf51 from Nordic Semiconductor.

  *

  * @version  V522

- * @date     26. January 2015

+ * @date     23. February 2016

  *

  * @note     Generated with SVDConv V2.81d 

- *           from CMSIS SVD File 'nrf51.xml' Version 522,

+ *           from CMSIS SVD File 'nrf51.svd' Version 522,

  *

  * @par      Copyright (c) 2013, Nordic Semiconductor ASA

  *           All rights reserved.

- *

+ *           

  *           Redistribution and use in source and binary forms, with or without

  *           modification, are permitted provided that the following conditions are met:

- *

+ *           

  *           * Redistributions of source code must retain the above copyright notice, this

  *           list of conditions and the following disclaimer.

- *

+ *           

  *           * Redistributions in binary form must reproduce the above copyright notice,

  *           this list of conditions and the following disclaimer in the documentation

  *           and/or other materials provided with the distribution.

- *

+ *           

  *           * Neither the name of Nordic Semiconductor ASA nor the names of its

  *           contributors may be used to endorse or promote products derived from

  *           this software without specific prior written permission.

- *

+ *           

  *           THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

  *           AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

  *           IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

@@ -38,7 +38,7 @@
  *           CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

  *           OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

  *           OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

- *

+ *           

  *

  *******************************************************************************************************/

 

@@ -294,27 +294,6 @@ typedef struct {                                    /*!< MPU Structure
 

 

 /* ================================================================================ */

-/* ================                       PU                       ================ */

-/* ================================================================================ */

-

-

-/**

-  * @brief Patch unit. (PU)

-  */

-

-typedef struct {                                    /*!< PU Structure                                                          */

-  __I  uint32_t  RESERVED0[448];

-  __IO uint32_t  REPLACEADDR[8];                    /*!< Address of first instruction to replace.                              */

-  __I  uint32_t  RESERVED1[24];

-  __IO uint32_t  PATCHADDR[8];                      /*!< Relative address of patch instructions.                               */

-  __I  uint32_t  RESERVED2[24];

-  __IO uint32_t  PATCHEN;                           /*!< Patch enable register.                                                */

-  __IO uint32_t  PATCHENSET;                        /*!< Patch enable register.                                                */

-  __IO uint32_t  PATCHENCLR;                        /*!< Patch disable register.                                               */

-} NRF_PU_Type;

-

-

-/* ================================================================================ */

 /* ================                      AMLI                      ================ */

 /* ================================================================================ */

 

@@ -367,11 +346,11 @@ typedef struct {                                    /*!< RADIO Structure
   __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */

   __I  uint32_t  RESERVED4[61];

   __I  uint32_t  CRCSTATUS;                         /*!< CRC status of received packet.                                        */

-  __I  uint32_t  CD;                                /*!< Carrier detect.                                                       */

+  __I  uint32_t  RESERVED5;

   __I  uint32_t  RXMATCH;                           /*!< Received address.                                                     */

   __I  uint32_t  RXCRC;                             /*!< Received CRC.                                                         */

   __I  uint32_t  DAI;                               /*!< Device address match index.                                           */

-  __I  uint32_t  RESERVED5[60];

+  __I  uint32_t  RESERVED6[60];

   __IO uint32_t  PACKETPTR;                         /*!< Packet pointer. Decision point: START task.                           */

   __IO uint32_t  FREQUENCY;                         /*!< Frequency.                                                            */

   __IO uint32_t  TXPOWER;                           /*!< Output power.                                                         */

@@ -390,22 +369,22 @@ typedef struct {                                    /*!< RADIO Structure
   __IO uint32_t  TEST;                              /*!< Test features enable register.                                        */

   __IO uint32_t  TIFS;                              /*!< Inter Frame Spacing in microseconds.                                  */

   __I  uint32_t  RSSISAMPLE;                        /*!< RSSI sample.                                                          */

-  __I  uint32_t  RESERVED6;

+  __I  uint32_t  RESERVED7;

   __I  uint32_t  STATE;                             /*!< Current radio state.                                                  */

   __IO uint32_t  DATAWHITEIV;                       /*!< Data whitening initial value.                                         */

-  __I  uint32_t  RESERVED7[2];

+  __I  uint32_t  RESERVED8[2];

   __IO uint32_t  BCC;                               /*!< Bit counter compare.                                                  */

-  __I  uint32_t  RESERVED8[39];

+  __I  uint32_t  RESERVED9[39];

   __IO uint32_t  DAB[8];                            /*!< Device address base segment.                                          */

   __IO uint32_t  DAP[8];                            /*!< Device address prefix.                                                */

   __IO uint32_t  DACNF;                             /*!< Device address match configuration.                                   */

-  __I  uint32_t  RESERVED9[56];

+  __I  uint32_t  RESERVED10[56];

   __IO uint32_t  OVERRIDE0;                         /*!< Trim value override register 0.                                       */

   __IO uint32_t  OVERRIDE1;                         /*!< Trim value override register 1.                                       */

   __IO uint32_t  OVERRIDE2;                         /*!< Trim value override register 2.                                       */

   __IO uint32_t  OVERRIDE3;                         /*!< Trim value override register 3.                                       */

   __IO uint32_t  OVERRIDE4;                         /*!< Trim value override register 4.                                       */

-  __I  uint32_t  RESERVED10[561];

+  __I  uint32_t  RESERVED11[561];

   __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */

 } NRF_RADIO_Type;

 

@@ -564,39 +543,41 @@ typedef struct {                                    /*!< SPIS Structure
   __O  uint32_t  TASKS_RELEASE;                     /*!< Release SPI semaphore.                                                */

   __I  uint32_t  RESERVED1[54];

   __IO uint32_t  EVENTS_END;                        /*!< Granted transaction completed.                                        */

-  __I  uint32_t  RESERVED2[8];

+  __I  uint32_t  RESERVED2[2];

+  __IO uint32_t  EVENTS_ENDRX;                      /*!< End of RXD buffer reached                                             */

+  __I  uint32_t  RESERVED3[5];

   __IO uint32_t  EVENTS_ACQUIRED;                   /*!< Semaphore acquired.                                                   */

-  __I  uint32_t  RESERVED3[53];

+  __I  uint32_t  RESERVED4[53];

   __IO uint32_t  SHORTS;                            /*!< Shortcuts for SPIS.                                                   */

-  __I  uint32_t  RESERVED4[64];

+  __I  uint32_t  RESERVED5[64];

   __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */

   __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */

-  __I  uint32_t  RESERVED5[61];

+  __I  uint32_t  RESERVED6[61];

   __I  uint32_t  SEMSTAT;                           /*!< Semaphore status.                                                     */

-  __I  uint32_t  RESERVED6[15];

+  __I  uint32_t  RESERVED7[15];

   __IO uint32_t  STATUS;                            /*!< Status from last transaction.                                         */

-  __I  uint32_t  RESERVED7[47];

+  __I  uint32_t  RESERVED8[47];

   __IO uint32_t  ENABLE;                            /*!< Enable SPIS.                                                          */

-  __I  uint32_t  RESERVED8;

+  __I  uint32_t  RESERVED9;

   __IO uint32_t  PSELSCK;                           /*!< Pin select for SCK.                                                   */

   __IO uint32_t  PSELMISO;                          /*!< Pin select for MISO.                                                  */

   __IO uint32_t  PSELMOSI;                          /*!< Pin select for MOSI.                                                  */

   __IO uint32_t  PSELCSN;                           /*!< Pin select for CSN.                                                   */

-  __I  uint32_t  RESERVED9[7];

+  __I  uint32_t  RESERVED10[7];

   __IO uint32_t  RXDPTR;                            /*!< RX data pointer.                                                      */

   __IO uint32_t  MAXRX;                             /*!< Maximum number of bytes in the receive buffer.                        */

   __I  uint32_t  AMOUNTRX;                          /*!< Number of bytes received in last granted transaction.                 */

-  __I  uint32_t  RESERVED10;

+  __I  uint32_t  RESERVED11;

   __IO uint32_t  TXDPTR;                            /*!< TX data pointer.                                                      */

   __IO uint32_t  MAXTX;                             /*!< Maximum number of bytes in the transmit buffer.                       */

   __I  uint32_t  AMOUNTTX;                          /*!< Number of bytes transmitted in last granted transaction.              */

-  __I  uint32_t  RESERVED11;

-  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */

   __I  uint32_t  RESERVED12;

+  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */

+  __I  uint32_t  RESERVED13;

   __IO uint32_t  DEF;                               /*!< Default character.                                                    */

-  __I  uint32_t  RESERVED13[24];

+  __I  uint32_t  RESERVED14[24];

   __IO uint32_t  ORC;                               /*!< Over-read character.                                                  */

-  __I  uint32_t  RESERVED14[654];

+  __I  uint32_t  RESERVED15[654];

   __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */

 } NRF_SPIS_Type;

 

@@ -621,32 +602,28 @@ typedef struct {                                    /*!< SPIM Structure
   __IO uint32_t  EVENTS_STOPPED;                    /*!< SPI transaction has stopped.                                          */

   __I  uint32_t  RESERVED3[2];

   __IO uint32_t  EVENTS_ENDRX;                      /*!< End of RXD buffer reached.                                            */

-  __I  uint32_t  RESERVED4;

-  __IO uint32_t  EVENTS_END;                        /*!< End of RXD buffer and TXD buffer reached.                             */

-  __I  uint32_t  RESERVED5;

+  __I  uint32_t  RESERVED4[3];

   __IO uint32_t  EVENTS_ENDTX;                      /*!< End of TXD buffer reached.                                            */

-  __I  uint32_t  RESERVED6[10];

+  __I  uint32_t  RESERVED5[10];

   __IO uint32_t  EVENTS_STARTED;                    /*!< Transaction started.                                                  */

-  __I  uint32_t  RESERVED7[44];

-  __IO uint32_t  SHORTS;                            /*!< Shortcuts for SPIM.                                                   */

-  __I  uint32_t  RESERVED8[64];

+  __I  uint32_t  RESERVED6[109];

   __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */

   __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */

-  __I  uint32_t  RESERVED9[125];

+  __I  uint32_t  RESERVED7[125];

   __IO uint32_t  ENABLE;                            /*!< Enable SPIM.                                                          */

-  __I  uint32_t  RESERVED10;

+  __I  uint32_t  RESERVED8;

   SPIM_PSEL_Type PSEL;                              /*!< Pin select configuration.                                             */

-  __I  uint32_t  RESERVED11[4];

+  __I  uint32_t  RESERVED9[4];

   __IO uint32_t  FREQUENCY;                         /*!< SPI frequency.                                                        */

-  __I  uint32_t  RESERVED12[3];

+  __I  uint32_t  RESERVED10[3];

   SPIM_RXD_Type RXD;                                /*!< RXD EasyDMA configuration and status.                                 */

-  __I  uint32_t  RESERVED13;

+  __I  uint32_t  RESERVED11;

   SPIM_TXD_Type TXD;                                /*!< TXD EasyDMA configuration and status.                                 */

-  __I  uint32_t  RESERVED14;

+  __I  uint32_t  RESERVED12;

   __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */

-  __I  uint32_t  RESERVED15[26];

+  __I  uint32_t  RESERVED13[26];

   __IO uint32_t  ORC;                               /*!< Over-read character.                                                  */

-  __I  uint32_t  RESERVED16[654];

+  __I  uint32_t  RESERVED14[654];

   __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */

 } NRF_SPIM_Type;

 

@@ -889,8 +866,8 @@ typedef struct {                                    /*!< AAR Structure
   __IO uint32_t  IRKPTR;                            /*!< Pointer to the IRK data structure.                                    */

   __I  uint32_t  RESERVED5;

   __IO uint32_t  ADDRPTR;                           /*!< Pointer to the resolvable address (6 bytes).                          */

-  __IO uint32_t  SCRATCHPTR;                        /*!< Pointer to a "scratch" data area used for temporary storage

-                                                         during resolution. A minimum of 3 bytes must be reserved.             */

+  __IO uint32_t  SCRATCHPTR;                        /*!< Pointer to a scratch data area used for temporary storage during

+                                                         resolution. A minimum of 3 bytes must be reserved.                    */

   __I  uint32_t  RESERVED6[697];

   __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */

 } NRF_AAR_Type;

@@ -928,8 +905,8 @@ typedef struct {                                    /*!< CCM Structure
   __IO uint32_t  CNFPTR;                            /*!< Pointer to a data structure holding AES key and NONCE vector.         */

   __IO uint32_t  INPTR;                             /*!< Pointer to the input packet.                                          */

   __IO uint32_t  OUTPTR;                            /*!< Pointer to the output packet.                                         */

-  __IO uint32_t  SCRATCHPTR;                        /*!< Pointer to a "scratch" data area used for temporary storage

-                                                         during resolution. A minimum of 43 bytes must be reserved.            */

+  __IO uint32_t  SCRATCHPTR;                        /*!< Pointer to a scratch data area used for temporary storage during

+                                                         resolution. A minimum of 43 bytes must be reserved.                   */

   __I  uint32_t  RESERVED5[697];

   __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */

 } NRF_CCM_Type;

@@ -1083,11 +1060,7 @@ typedef struct {                                    /*!< NVMC Structure
     __IO uint32_t  ERASEPAGE;                       /*!< Register for erasing a non-protected non-volatile memory page.        */

   };

   __IO uint32_t  ERASEALL;                          /*!< Register for erasing all non-volatile user memory.                    */

-  

-  union {

-    __IO uint32_t  ERASEPCR0;                       /*!< Register for erasing a protected non-volatile memory page.            */

-    __IO uint32_t  ERASEPROTECTEDPAGE;              /*!< Register for erasing a protected non-volatile memory page.            */

-  };

+  __IO uint32_t  ERASEPCR0;                         /*!< Register for erasing a protected non-volatile memory page.            */

   __IO uint32_t  ERASEUICR;                         /*!< Register for start erasing User Information Congfiguration Registers. */

 } NRF_NVMC_Type;

 

@@ -1229,7 +1202,6 @@ typedef struct {                                    /*!< GPIO Structure
 #define NRF_POWER_BASE                  0x40000000UL

 #define NRF_CLOCK_BASE                  0x40000000UL

 #define NRF_MPU_BASE                    0x40000000UL

-#define NRF_PU_BASE                     0x40000000UL

 #define NRF_AMLI_BASE                   0x40000000UL

 #define NRF_RADIO_BASE                  0x40001000UL

 #define NRF_UART0_BASE                  0x40002000UL

@@ -1269,7 +1241,6 @@ typedef struct {                                    /*!< GPIO Structure
 #define NRF_POWER                       ((NRF_POWER_Type          *) NRF_POWER_BASE)

 #define NRF_CLOCK                       ((NRF_CLOCK_Type          *) NRF_CLOCK_BASE)

 #define NRF_MPU                         ((NRF_MPU_Type            *) NRF_MPU_BASE)

-#define NRF_PU                          ((NRF_PU_Type             *) NRF_PU_BASE)

 #define NRF_AMLI                        ((NRF_AMLI_Type           *) NRF_AMLI_BASE)

 #define NRF_RADIO                       ((NRF_RADIO_Type          *) NRF_RADIO_BASE)

 #define NRF_UART0                       ((NRF_UART_Type           *) NRF_UART0_BASE)

diff --git a/os/hal/ports/NRF51/NRF51822/nrf51_bitfields.h b/os/hal/ports/NRF5/NRF51822/nrf51_bitfields.h
index 0ab4598..5c5af9a 100644
--- a/os/hal/ports/NRF51/NRF51822/nrf51_bitfields.h
+++ b/os/hal/ports/NRF5/NRF51822/nrf51_bitfields.h
@@ -1,7088 +1,6892 @@
-/* Copyright (c) 2015, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- *   * Redistributions of source code must retain the above copyright notice, this
- *     list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright notice,
- *     this list of conditions and the following disclaimer in the documentation
- *     and/or other materials provided with the distribution.
- *
- *   * Neither the name of Nordic Semiconductor ASA nor the names of its
- *     contributors may be used to endorse or promote products derived from
- *     this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-#ifndef __NRF51_BITS_H
-#define __NRF51_BITS_H
-
-/*lint ++flb "Enter library region" */
-
-/* Peripheral: AAR */
-/* Description: Accelerated Address Resolver. */
-
-/* Register: AAR_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 2 : Enable interrupt on NOTRESOLVED event. */
-#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
-#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
-#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
-#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
-#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on RESOLVED event. */
-#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
-#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
-#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
-#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
-#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on END event. */
-#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
-#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
-#define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
-#define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
-#define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: AAR_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 2 : Disable interrupt on NOTRESOLVED event. */
-#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
-#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
-#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
-#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
-#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on RESOLVED event. */
-#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
-#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
-#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
-#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
-#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on ENDKSGEN event. */
-#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
-#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
-#define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
-#define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
-#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: AAR_STATUS */
-/* Description: Resolution status. */
-
-/* Bits 3..0 : The IRK used last time an address was resolved. */
-#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
-#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
-
-/* Register: AAR_ENABLE */
-/* Description: Enable AAR. */
-
-/* Bits 1..0 : Enable AAR. */
-#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */
-#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */
-
-/* Register: AAR_NIRK */
-/* Description: Number of Identity root Keys in the IRK data structure. */
-
-/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
-#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
-#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
-
-/* Register: AAR_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define AAR_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: ADC */
-/* Description: Analog to digital converter. */
-
-/* Register: ADC_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 0 : Enable interrupt on END event. */
-#define ADC_INTENSET_END_Pos (0UL) /*!< Position of END field. */
-#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
-#define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
-#define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
-#define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: ADC_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 0 : Disable interrupt on END event. */
-#define ADC_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
-#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
-#define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
-#define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
-#define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: ADC_BUSY */
-/* Description: ADC busy register. */
-
-/* Bit 0 : ADC busy register. */
-#define ADC_BUSY_BUSY_Pos (0UL) /*!< Position of BUSY field. */
-#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /*!< Bit mask of BUSY field. */
-#define ADC_BUSY_BUSY_Ready (0UL) /*!< No ongoing ADC conversion is taking place. ADC is ready. */
-#define ADC_BUSY_BUSY_Busy (1UL) /*!< An ADC conversion is taking place. ADC is busy. */
-
-/* Register: ADC_ENABLE */
-/* Description: ADC enable. */
-
-/* Bits 1..0 : ADC enable. */
-#define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */
-#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. */
-
-/* Register: ADC_CONFIG */
-/* Description: ADC configuration register. */
-
-/* Bits 17..16 : ADC external reference pin selection. */
-#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /*!< Position of EXTREFSEL field. */
-#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
-#define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */
-#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /*!< Use analog reference 0 as reference. */
-#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */
-
-/* Bits 15..8 : ADC analog pin selection. */
-#define ADC_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
-#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
-#define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */
-#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /*!< Use analog input 0 as analog input. */
-#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */
-#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */
-#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /*!< Use analog input 3 as analog input. */
-#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /*!< Use analog input 4 as analog input. */
-#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /*!< Use analog input 5 as analog input. */
-#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /*!< Use analog input 6 as analog input. */
-#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /*!< Use analog input 7 as analog input. */
-
-/* Bits 6..5 : ADC reference selection. */
-#define ADC_CONFIG_REFSEL_Pos (5UL) /*!< Position of REFSEL field. */
-#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
-#define ADC_CONFIG_REFSEL_VBG (0x00UL) /*!< Use internal 1.2V bandgap voltage as reference for conversion. */
-#define ADC_CONFIG_REFSEL_External (0x01UL) /*!< Use external source configured by EXTREFSEL as reference for conversion. */
-#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. */
-#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /*!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. */
-
-/* Bits 4..2 : ADC input selection. */
-#define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */
-#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /*!< Bit mask of INPSEL field. */
-#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /*!< Analog input specified by PSEL with no prescaling used as input for the conversion. */
-#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. */
-#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /*!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. */
-#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescaling used as input for the conversion. */
-#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /*!< Supply voltage with 1/3 prescaling used as input for the conversion. */
-
-/* Bits 1..0 : ADC resolution. */
-#define ADC_CONFIG_RES_Pos (0UL) /*!< Position of RES field. */
-#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /*!< Bit mask of RES field. */
-#define ADC_CONFIG_RES_8bit (0x00UL) /*!< 8bit ADC resolution. */
-#define ADC_CONFIG_RES_9bit (0x01UL) /*!< 9bit ADC resolution. */
-#define ADC_CONFIG_RES_10bit (0x02UL) /*!< 10bit ADC resolution. */
-
-/* Register: ADC_RESULT */
-/* Description: Result of ADC conversion. */
-
-/* Bits 9..0 : Result of ADC conversion. */
-#define ADC_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
-#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
-
-/* Register: ADC_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define ADC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: AMLI */
-/* Description: AHB Multi-Layer Interface. */
-
-/* Register: AMLI_RAMPRI_CPU0 */
-/* Description: Configurable priority configuration register for CPU0. */
-
-/* Bits 31..28 : Configuration field for RAM block 7. */
-#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
-#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */
-#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 27..24 : Configuration field for RAM block 6. */
-#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
-#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */
-#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 23..20 : Configuration field for RAM block 5. */
-#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
-#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */
-#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 19..16 : Configuration field for RAM block 4. */
-#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
-#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */
-#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 15..12 : Configuration field for RAM block 3. */
-#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
-#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */
-#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 11..8 : Configuration field for RAM block 2. */
-#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
-#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */
-#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 7..4 : Configuration field for RAM block 1. */
-#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
-#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */
-#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 3..0 : Configuration field for RAM block 0. */
-#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
-#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */
-#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Register: AMLI_RAMPRI_SPIS1 */
-/* Description: Configurable priority configuration register for SPIS1. */
-
-/* Bits 31..28 : Configuration field for RAM block 7. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 27..24 : Configuration field for RAM block 6. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 23..20 : Configuration field for RAM block 5. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 19..16 : Configuration field for RAM block 4. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 15..12 : Configuration field for RAM block 3. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 11..8 : Configuration field for RAM block 2. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 7..4 : Configuration field for RAM block 1. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 3..0 : Configuration field for RAM block 0. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Register: AMLI_RAMPRI_RADIO */
-/* Description: Configurable priority configuration register for RADIO. */
-
-/* Bits 31..28 : Configuration field for RAM block 7. */
-#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
-#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */
-#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 27..24 : Configuration field for RAM block 6. */
-#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
-#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */
-#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 23..20 : Configuration field for RAM block 5. */
-#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
-#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */
-#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 19..16 : Configuration field for RAM block 4. */
-#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
-#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */
-#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 15..12 : Configuration field for RAM block 3. */
-#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
-#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */
-#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 11..8 : Configuration field for RAM block 2. */
-#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
-#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */
-#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 7..4 : Configuration field for RAM block 1. */
-#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
-#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */
-#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 3..0 : Configuration field for RAM block 0. */
-#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
-#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */
-#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Register: AMLI_RAMPRI_ECB */
-/* Description: Configurable priority configuration register for ECB. */
-
-/* Bits 31..28 : Configuration field for RAM block 7. */
-#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
-#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */
-#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 27..24 : Configuration field for RAM block 6. */
-#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
-#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */
-#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 23..20 : Configuration field for RAM block 5. */
-#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
-#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */
-#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 19..16 : Configuration field for RAM block 4. */
-#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
-#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */
-#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 15..12 : Configuration field for RAM block 3. */
-#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
-#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */
-#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 11..8 : Configuration field for RAM block 2. */
-#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
-#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */
-#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 7..4 : Configuration field for RAM block 1. */
-#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
-#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */
-#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 3..0 : Configuration field for RAM block 0. */
-#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
-#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */
-#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Register: AMLI_RAMPRI_CCM */
-/* Description: Configurable priority configuration register for CCM. */
-
-/* Bits 31..28 : Configuration field for RAM block 7. */
-#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
-#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */
-#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 27..24 : Configuration field for RAM block 6. */
-#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
-#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */
-#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 23..20 : Configuration field for RAM block 5. */
-#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
-#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */
-#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 19..16 : Configuration field for RAM block 4. */
-#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
-#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */
-#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 15..12 : Configuration field for RAM block 3. */
-#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
-#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
-#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 11..8 : Configuration field for RAM block 2. */
-#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
-#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
-#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 7..4 : Configuration field for RAM block 1. */
-#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
-#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
-#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 3..0 : Configuration field for RAM block 0. */
-#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
-#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
-#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Register: AMLI_RAMPRI_AAR */
-/* Description: Configurable priority configuration register for AAR. */
-
-/* Bits 31..28 : Configuration field for RAM block 7. */
-#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
-#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */
-#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 27..24 : Configuration field for RAM block 6. */
-#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
-#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */
-#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 23..20 : Configuration field for RAM block 5. */
-#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
-#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */
-#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 19..16 : Configuration field for RAM block 4. */
-#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
-#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */
-#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 15..12 : Configuration field for RAM block 3. */
-#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
-#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */
-#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 11..8 : Configuration field for RAM block 2. */
-#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
-#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */
-#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 7..4 : Configuration field for RAM block 1. */
-#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
-#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */
-#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 3..0 : Configuration field for RAM block 0. */
-#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
-#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */
-#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
-
-
-/* Peripheral: CCM */
-/* Description: AES CCM Mode Encryption. */
-
-/* Register: CCM_SHORTS */
-/* Description: Shortcuts for the CCM. */
-
-/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */
-#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
-#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
-#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */
-#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: CCM_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 2 : Enable interrupt on ERROR event. */
-#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
-#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
-#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
-#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
-#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on ENDCRYPT event. */
-#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
-#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
-#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
-#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
-#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on ENDKSGEN event. */
-#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
-#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
-#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
-#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
-#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: CCM_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 2 : Disable interrupt on ERROR event. */
-#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
-#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
-#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
-#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
-#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on ENDCRYPT event. */
-#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
-#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
-#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
-#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
-#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on ENDKSGEN event. */
-#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
-#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
-#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
-#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
-#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: CCM_MICSTATUS */
-/* Description: CCM RX MIC check result. */
-
-/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
-#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
-#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
-#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed. */
-#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed. */
-
-/* Register: CCM_ENABLE */
-/* Description: CCM enable. */
-
-/* Bits 1..0 : CCM enable. */
-#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */
-#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */
-
-/* Register: CCM_MODE */
-/* Description: Operation mode. */
-
-/* Bit 0 : CCM mode operation. */
-#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
-#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
-#define CCM_MODE_MODE_Encryption (0UL) /*!< CCM mode TX */
-#define CCM_MODE_MODE_Decryption (1UL) /*!< CCM mode TX */
-
-/* Register: CCM_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define CCM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: CLOCK */
-/* Description: Clock control. */
-
-/* Register: CLOCK_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 4 : Enable interrupt on CTTO event. */
-#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
-#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
-#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
-#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
-#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 3 : Enable interrupt on DONE event. */
-#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
-#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
-#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */
-#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */
-#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
-#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
-#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
-#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
-#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
-#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
-#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
-#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
-#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
-#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
-#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: CLOCK_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 4 : Disable interrupt on CTTO event. */
-#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
-#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
-#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
-#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
-#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 3 : Disable interrupt on DONE event. */
-#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
-#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
-#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */
-#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */
-#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
-#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
-#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
-#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
-#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
-#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
-#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
-#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
-#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
-#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
-#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: CLOCK_HFCLKRUN */
-/* Description: Task HFCLKSTART trigger status. */
-
-/* Bit 0 : Task HFCLKSTART trigger status. */
-#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
-#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
-#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task HFCLKSTART has not been triggered. */
-#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task HFCLKSTART has been triggered. */
-
-/* Register: CLOCK_HFCLKSTAT */
-/* Description: High frequency clock status. */
-
-/* Bit 16 : State for the HFCLK. */
-#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
-#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
-#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK clock not running. */
-#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK clock running. */
-
-/* Bit 0 : Active clock source for the HF clock. */
-#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
-#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
-#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */
-#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */
-
-/* Register: CLOCK_LFCLKRUN */
-/* Description: Task LFCLKSTART triggered status. */
-
-/* Bit 0 : Task LFCLKSTART triggered status. */
-#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
-#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
-#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task LFCLKSTART has not been triggered. */
-#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task LFCLKSTART has been triggered. */
-
-/* Register: CLOCK_LFCLKSTAT */
-/* Description: Low frequency clock status. */
-
-/* Bit 16 : State for the LF clock. */
-#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
-#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
-#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK clock not running. */
-#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK clock running. */
-
-/* Bits 1..0 : Active clock source for the LF clock. */
-#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
-#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
-#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. */
-#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */
-#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */
-
-/* Register: CLOCK_LFCLKSRCCOPY */
-/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
-
-/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
-#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
-#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
-#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
-#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
-#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
-
-/* Register: CLOCK_LFCLKSRC */
-/* Description: Clock source for the LFCLK clock. */
-
-/* Bits 1..0 : Clock source. */
-#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
-#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
-#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
-#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
-#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
-
-/* Register: CLOCK_CTIV */
-/* Description: Calibration timer interval. */
-
-/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
-#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
-#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
-
-/* Register: CLOCK_XTALFREQ */
-/* Description: Crystal frequency. */
-
-/* Bits 7..0 : External Xtal frequency selection. */
-#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
-#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
-#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used as source for the HFCLK oscillator. */
-#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */
-
-
-/* Peripheral: ECB */
-/* Description: AES ECB Mode Encryption. */
-
-/* Register: ECB_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 1 : Enable interrupt on ERRORECB event. */
-#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
-#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
-#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
-#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
-#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on ENDECB event. */
-#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
-#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
-#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
-#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
-#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: ECB_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 1 : Disable interrupt on ERRORECB event. */
-#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
-#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
-#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
-#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
-#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on ENDECB event. */
-#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
-#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
-#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
-#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
-#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: ECB_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define ECB_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: FICR */
-/* Description: Factory Information Configuration. */
-
-/* Register: FICR_PPFC */
-/* Description: Pre-programmed factory code present. */
-
-/* Bits 7..0 : Pre-programmed factory code present. */
-#define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */
-#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */
-#define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */
-#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */
-
-/* Register: FICR_CONFIGID */
-/* Description: Configuration identifier. */
-
-/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
-#define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */
-#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */
-
-/* Bits 15..0 : Hardware Identification Number. */
-#define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */
-#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */
-
-/* Register: FICR_DEVICEADDRTYPE */
-/* Description: Device address type. */
-
-/* Bit 0 : Device address type. */
-#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
-#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
-#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address. */
-#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address. */
-
-/* Register: FICR_OVERRIDEEN */
-/* Description: Radio calibration override enable. */
-
-/* Bit 3 : Override default values for BLE_1Mbit mode. */
-#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /*!< Position of BLE_1MBIT field. */
-#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /*!< Bit mask of BLE_1MBIT field. */
-#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */
-#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */
-
-/* Bit 0 : Override default values for NRF_1Mbit mode. */
-#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /*!< Position of NRF_1MBIT field. */
-#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /*!< Bit mask of NRF_1MBIT field. */
-#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /*!< Override the default values for NRF_1Mbit mode. */
-#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /*!< Do not override the default values for NRF_1Mbit mode. */
-
-
-/* Peripheral: GPIO */
-/* Description: General purpose input and output. */
-
-/* Register: GPIO_OUT */
-/* Description: Write GPIO port. */
-
-/* Bit 31 : Pin 31. */
-#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
-#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
-#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 30 : Pin 30. */
-#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
-#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
-#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 29 : Pin 29. */
-#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
-#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
-#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 28 : Pin 28. */
-#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
-#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
-#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 27 : Pin 27. */
-#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
-#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
-#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 26 : Pin 26. */
-#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
-#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
-#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 25 : Pin 25. */
-#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
-#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
-#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 24 : Pin 24. */
-#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
-#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
-#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 23 : Pin 23. */
-#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
-#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
-#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 22 : Pin 22. */
-#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
-#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
-#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 21 : Pin 21. */
-#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
-#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
-#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 20 : Pin 20. */
-#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
-#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
-#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 19 : Pin 19. */
-#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
-#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
-#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 18 : Pin 18. */
-#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
-#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
-#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 17 : Pin 17. */
-#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
-#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
-#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 16 : Pin 16. */
-#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
-#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
-#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 15 : Pin 15. */
-#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
-#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
-#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 14 : Pin 14. */
-#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
-#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
-#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 13 : Pin 13. */
-#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
-#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
-#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 12 : Pin 12. */
-#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
-#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
-#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 11 : Pin 11. */
-#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
-#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
-#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 10 : Pin 10. */
-#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
-#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
-#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 9 : Pin 9. */
-#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
-#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
-#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 8 : Pin 8. */
-#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
-#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
-#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 7 : Pin 7. */
-#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
-#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
-#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 6 : Pin 6. */
-#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
-#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
-#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 5 : Pin 5. */
-#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
-#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
-#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 4 : Pin 4. */
-#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
-#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
-#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 3 : Pin 3. */
-#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
-#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
-#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 2 : Pin 2. */
-#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
-#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
-#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 1 : Pin 1. */
-#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
-#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
-#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 0 : Pin 0. */
-#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
-#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
-#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high. */
-
-/* Register: GPIO_OUTSET */
-/* Description: Set individual bits in GPIO port. */
-
-/* Bit 31 : Pin 31. */
-#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
-#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
-#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN31_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 30 : Pin 30. */
-#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
-#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
-#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN30_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 29 : Pin 29. */
-#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
-#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
-#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN29_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 28 : Pin 28. */
-#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
-#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
-#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN28_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 27 : Pin 27. */
-#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
-#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
-#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN27_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 26 : Pin 26. */
-#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
-#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
-#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN26_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 25 : Pin 25. */
-#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
-#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
-#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN25_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 24 : Pin 24. */
-#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
-#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
-#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN24_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 23 : Pin 23. */
-#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
-#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
-#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN23_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 22 : Pin 22. */
-#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
-#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
-#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN22_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 21 : Pin 21. */
-#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
-#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
-#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN21_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 20 : Pin 20. */
-#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
-#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
-#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN20_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 19 : Pin 19. */
-#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
-#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
-#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN19_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 18 : Pin 18. */
-#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
-#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
-#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN18_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 17 : Pin 17. */
-#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
-#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
-#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN17_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 16 : Pin 16. */
-#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
-#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
-#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN16_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 15 : Pin 15. */
-#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
-#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
-#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN15_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 14 : Pin 14. */
-#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
-#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
-#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN14_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 13 : Pin 13. */
-#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
-#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
-#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN13_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 12 : Pin 12. */
-#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
-#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
-#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN12_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 11 : Pin 11. */
-#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
-#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
-#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN11_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 10 : Pin 10. */
-#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
-#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
-#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN10_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 9 : Pin 9. */
-#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
-#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
-#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN9_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 8 : Pin 8. */
-#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
-#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
-#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN8_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 7 : Pin 7. */
-#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
-#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
-#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN7_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 6 : Pin 6. */
-#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
-#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
-#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN6_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 5 : Pin 5. */
-#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
-#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
-#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN5_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 4 : Pin 4. */
-#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
-#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
-#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN4_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 3 : Pin 3. */
-#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
-#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
-#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN3_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 2 : Pin 2. */
-#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
-#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
-#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN2_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 1 : Pin 1. */
-#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
-#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
-#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN1_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 0 : Pin 0. */
-#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
-#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
-#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN0_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Set pin driver high. */
-
-/* Register: GPIO_OUTCLR */
-/* Description: Clear individual bits in GPIO port. */
-
-/* Bit 31 : Pin 31. */
-#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
-#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
-#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 30 : Pin 30. */
-#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
-#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
-#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 29 : Pin 29. */
-#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
-#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
-#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 28 : Pin 28. */
-#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
-#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
-#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 27 : Pin 27. */
-#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
-#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
-#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 26 : Pin 26. */
-#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
-#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
-#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 25 : Pin 25. */
-#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
-#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
-#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 24 : Pin 24. */
-#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
-#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
-#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 23 : Pin 23. */
-#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
-#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
-#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 22 : Pin 22. */
-#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
-#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
-#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 21 : Pin 21. */
-#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
-#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
-#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 20 : Pin 20. */
-#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
-#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
-#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 19 : Pin 19. */
-#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
-#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
-#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 18 : Pin 18. */
-#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
-#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
-#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 17 : Pin 17. */
-#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
-#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
-#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 16 : Pin 16. */
-#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
-#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
-#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 15 : Pin 15. */
-#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
-#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
-#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 14 : Pin 14. */
-#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
-#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
-#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 13 : Pin 13. */
-#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
-#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
-#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 12 : Pin 12. */
-#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
-#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
-#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 11 : Pin 11. */
-#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
-#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
-#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 10 : Pin 10. */
-#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
-#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
-#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 9 : Pin 9. */
-#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
-#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
-#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 8 : Pin 8. */
-#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
-#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
-#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 7 : Pin 7. */
-#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
-#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
-#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 6 : Pin 6. */
-#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
-#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
-#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 5 : Pin 5. */
-#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
-#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
-#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 4 : Pin 4. */
-#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
-#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
-#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 3 : Pin 3. */
-#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
-#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
-#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 2 : Pin 2. */
-#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
-#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
-#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 1 : Pin 1. */
-#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
-#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
-#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 0 : Pin 0. */
-#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
-#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
-#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Set pin driver low. */
-
-/* Register: GPIO_IN */
-/* Description: Read GPIO port. */
-
-/* Bit 31 : Pin 31. */
-#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
-#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
-#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high. */
-
-/* Bit 30 : Pin 30. */
-#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
-#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
-#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high. */
-
-/* Bit 29 : Pin 29. */
-#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
-#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
-#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high. */
-
-/* Bit 28 : Pin 28. */
-#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
-#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
-#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high. */
-
-/* Bit 27 : Pin 27. */
-#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
-#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
-#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high. */
-
-/* Bit 26 : Pin 26. */
-#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
-#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
-#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high. */
-
-/* Bit 25 : Pin 25. */
-#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
-#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
-#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high. */
-
-/* Bit 24 : Pin 24. */
-#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
-#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
-#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high. */
-
-/* Bit 23 : Pin 23. */
-#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
-#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
-#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high. */
-
-/* Bit 22 : Pin 22. */
-#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
-#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
-#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high. */
-
-/* Bit 21 : Pin 21. */
-#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
-#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
-#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high. */
-
-/* Bit 20 : Pin 20. */
-#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
-#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
-#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high. */
-
-/* Bit 19 : Pin 19. */
-#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
-#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
-#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high. */
-
-/* Bit 18 : Pin 18. */
-#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
-#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
-#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high. */
-
-/* Bit 17 : Pin 17. */
-#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
-#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
-#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high. */
-
-/* Bit 16 : Pin 16. */
-#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
-#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
-#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high. */
-
-/* Bit 15 : Pin 15. */
-#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
-#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
-#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high. */
-
-/* Bit 14 : Pin 14. */
-#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
-#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
-#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high. */
-
-/* Bit 13 : Pin 13. */
-#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
-#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
-#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high. */
-
-/* Bit 12 : Pin 12. */
-#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
-#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
-#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high. */
-
-/* Bit 11 : Pin 11. */
-#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
-#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
-#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high. */
-
-/* Bit 10 : Pin 10. */
-#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
-#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
-#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high. */
-
-/* Bit 9 : Pin 9. */
-#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
-#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
-#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high. */
-
-/* Bit 8 : Pin 8. */
-#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
-#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
-#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high. */
-
-/* Bit 7 : Pin 7. */
-#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
-#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
-#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high. */
-
-/* Bit 6 : Pin 6. */
-#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
-#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
-#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high. */
-
-/* Bit 5 : Pin 5. */
-#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
-#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
-#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high. */
-
-/* Bit 4 : Pin 4. */
-#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
-#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
-#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high. */
-
-/* Bit 3 : Pin 3. */
-#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
-#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
-#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high. */
-
-/* Bit 2 : Pin 2. */
-#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
-#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
-#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high. */
-
-/* Bit 1 : Pin 1. */
-#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
-#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
-#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high. */
-
-/* Bit 0 : Pin 0. */
-#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
-#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
-#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high. */
-
-/* Register: GPIO_DIR */
-/* Description: Direction of GPIO pins. */
-
-/* Bit 31 : Pin 31. */
-#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
-#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
-#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 30 : Pin 30. */
-#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
-#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
-#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 29 : Pin 29. */
-#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
-#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
-#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 28 : Pin 28. */
-#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
-#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
-#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 27 : Pin 27. */
-#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
-#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
-#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 26 : Pin 26. */
-#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
-#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
-#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 25 : Pin 25. */
-#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
-#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
-#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 24 : Pin 24. */
-#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
-#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
-#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 23 : Pin 23. */
-#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
-#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
-#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 22 : Pin 22. */
-#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
-#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
-#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 21 : Pin 21. */
-#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
-#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
-#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 20 : Pin 20. */
-#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
-#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
-#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 19 : Pin 19. */
-#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
-#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
-#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 18 : Pin 18. */
-#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
-#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
-#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 17 : Pin 17. */
-#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
-#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
-#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 16 : Pin 16. */
-#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
-#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
-#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 15 : Pin 15. */
-#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
-#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
-#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 14 : Pin 14. */
-#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
-#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
-#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 13 : Pin 13. */
-#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
-#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
-#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 12 : Pin 12. */
-#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
-#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
-#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 11 : Pin 11. */
-#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
-#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
-#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 10 : Pin 10. */
-#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
-#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
-#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 9 : Pin 9. */
-#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
-#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
-#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 8 : Pin 8. */
-#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
-#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
-#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 7 : Pin 7. */
-#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
-#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
-#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 6 : Pin 6. */
-#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
-#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
-#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 5 : Pin 5. */
-#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
-#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
-#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 4 : Pin 4. */
-#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
-#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
-#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 3 : Pin 3. */
-#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
-#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
-#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 2 : Pin 2. */
-#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
-#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
-#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 1 : Pin 1. */
-#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
-#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
-#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 0 : Pin 0. */
-#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
-#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
-#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output. */
-
-/* Register: GPIO_DIRSET */
-/* Description: DIR set register. */
-
-/* Bit 31 : Set as output pin 31. */
-#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
-#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
-#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 30 : Set as output pin 30. */
-#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
-#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
-#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 29 : Set as output pin 29. */
-#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
-#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
-#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 28 : Set as output pin 28. */
-#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
-#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
-#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 27 : Set as output pin 27. */
-#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
-#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
-#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 26 : Set as output pin 26. */
-#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
-#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
-#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 25 : Set as output pin 25. */
-#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
-#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
-#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 24 : Set as output pin 24. */
-#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
-#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
-#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 23 : Set as output pin 23. */
-#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
-#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
-#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 22 : Set as output pin 22. */
-#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
-#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
-#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 21 : Set as output pin 21. */
-#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
-#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
-#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 20 : Set as output pin 20. */
-#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
-#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
-#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 19 : Set as output pin 19. */
-#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
-#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
-#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 18 : Set as output pin 18. */
-#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
-#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
-#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 17 : Set as output pin 17. */
-#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
-#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
-#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 16 : Set as output pin 16. */
-#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
-#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
-#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 15 : Set as output pin 15. */
-#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
-#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
-#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 14 : Set as output pin 14. */
-#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
-#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
-#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 13 : Set as output pin 13. */
-#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
-#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
-#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 12 : Set as output pin 12. */
-#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
-#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
-#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 11 : Set as output pin 11. */
-#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
-#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
-#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 10 : Set as output pin 10. */
-#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
-#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
-#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 9 : Set as output pin 9. */
-#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
-#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
-#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 8 : Set as output pin 8. */
-#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
-#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
-#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 7 : Set as output pin 7. */
-#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
-#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
-#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 6 : Set as output pin 6. */
-#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
-#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
-#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 5 : Set as output pin 5. */
-#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
-#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
-#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 4 : Set as output pin 4. */
-#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
-#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
-#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 3 : Set as output pin 3. */
-#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
-#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
-#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 2 : Set as output pin 2. */
-#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
-#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
-#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 1 : Set as output pin 1. */
-#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
-#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
-#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 0 : Set as output pin 0. */
-#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
-#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
-#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Set pin as output. */
-
-/* Register: GPIO_DIRCLR */
-/* Description: DIR clear register. */
-
-/* Bit 31 : Set as input pin 31. */
-#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
-#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
-#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 30 : Set as input pin 30. */
-#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
-#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
-#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 29 : Set as input pin 29. */
-#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
-#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
-#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 28 : Set as input pin 28. */
-#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
-#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
-#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 27 : Set as input pin 27. */
-#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
-#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
-#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 26 : Set as input pin 26. */
-#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
-#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
-#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 25 : Set as input pin 25. */
-#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
-#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
-#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 24 : Set as input pin 24. */
-#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
-#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
-#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 23 : Set as input pin 23. */
-#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
-#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
-#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 22 : Set as input pin 22. */
-#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
-#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
-#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 21 : Set as input pin 21. */
-#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
-#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
-#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 20 : Set as input pin 20. */
-#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
-#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
-#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 19 : Set as input pin 19. */
-#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
-#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
-#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 18 : Set as input pin 18. */
-#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
-#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
-#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 17 : Set as input pin 17. */
-#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
-#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
-#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 16 : Set as input pin 16. */
-#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
-#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
-#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 15 : Set as input pin 15. */
-#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
-#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
-#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 14 : Set as input pin 14. */
-#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
-#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
-#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 13 : Set as input pin 13. */
-#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
-#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
-#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 12 : Set as input pin 12. */
-#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
-#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
-#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 11 : Set as input pin 11. */
-#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
-#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
-#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 10 : Set as input pin 10. */
-#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
-#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
-#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 9 : Set as input pin 9. */
-#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
-#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
-#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 8 : Set as input pin 8. */
-#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
-#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
-#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 7 : Set as input pin 7. */
-#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
-#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
-#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 6 : Set as input pin 6. */
-#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
-#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
-#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 5 : Set as input pin 5. */
-#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
-#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
-#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 4 : Set as input pin 4. */
-#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
-#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
-#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 3 : Set as input pin 3. */
-#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
-#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
-#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 2 : Set as input pin 2. */
-#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
-#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
-#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 1 : Set as input pin 1. */
-#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
-#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
-#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 0 : Set as input pin 0. */
-#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
-#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
-#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Set pin as input. */
-
-/* Register: GPIO_PIN_CNF */
-/* Description: Configuration of GPIO pins. */
-
-/* Bits 17..16 : Pin sensing mechanism. */
-#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
-#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
-#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */
-#define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */
-#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */
-
-/* Bits 10..8 : Drive configuration. */
-#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
-#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
-#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /*!< Standard '0', Standard '1'. */
-#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /*!< High '0', Standard '1'. */
-#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /*!< Standard '0', High '1'. */
-#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /*!< High '0', High '1'. */
-#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /*!< Disconnected '0', Standard '1'. */
-#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /*!< Disconnected '0', High '1'. */
-#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /*!< Standard '0', Disconnected '1'. */
-#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /*!< High '0', Disconnected '1'. */
-
-/* Bits 3..2 : Pull-up or -down configuration. */
-#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
-#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
-#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /*!< No pull. */
-#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */
-#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */
-
-/* Bit 1 : Connect or disconnect input path. */
-#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
-#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
-#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input pin. */
-#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input pin. */
-
-/* Bit 0 : Pin direction. */
-#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
-#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
-#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin. */
-#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin. */
-
-
-/* Peripheral: GPIOTE */
-/* Description: GPIO tasks and events. */
-
-/* Register: GPIOTE_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 31 : Enable interrupt on PORT event. */
-#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
-#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
-#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 3 : Enable interrupt on IN[3] event. */
-#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
-#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
-#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 2 : Enable interrupt on IN[2] event. */
-#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
-#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
-#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on IN[1] event. */
-#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
-#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
-#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on IN[0] event. */
-#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
-#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
-#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: GPIOTE_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 31 : Disable interrupt on PORT event. */
-#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
-#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
-#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 3 : Disable interrupt on IN[3] event. */
-#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
-#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
-#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 2 : Disable interrupt on IN[2] event. */
-#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
-#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
-#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on IN[1] event. */
-#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
-#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
-#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on IN[0] event. */
-#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
-#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
-#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: GPIOTE_CONFIG */
-/* Description: Channel configuration registers. */
-
-/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
-#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
-#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
-#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Initial low output when in task mode. */
-#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Initial high output when in task mode. */
-
-/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
-#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
-#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
-#define GPIOTE_CONFIG_POLARITY_None (0x00UL) /*!< No task or event. */
-#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */
-#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */
-#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */
-
-/* Bits 12..8 : Pin select. */
-#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
-#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
-
-/* Bits 1..0 : Mode */
-#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
-#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
-#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */
-#define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */
-#define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */
-
-/* Register: GPIOTE_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define GPIOTE_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: LPCOMP */
-/* Description: Low power comparator. */
-
-/* Register: LPCOMP_SHORTS */
-/* Description: Shortcuts for the LPCOMP. */
-
-/* Bit 4 : Shortcut between CROSS event and STOP task. */
-#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
-#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
-#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 3 : Shortcut between UP event and STOP task. */
-#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
-#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
-#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 2 : Shortcut between DOWN event and STOP task. */
-#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
-#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
-#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 1 : Shortcut between RADY event and STOP task. */
-#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
-#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
-#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 0 : Shortcut between READY event and SAMPLE task. */
-#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
-#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
-#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */
-#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: LPCOMP_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 3 : Enable interrupt on CROSS event. */
-#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
-#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
-#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
-#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
-#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 2 : Enable interrupt on UP event. */
-#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
-#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
-#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */
-#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */
-#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on DOWN event. */
-#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
-#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
-#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
-#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
-#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on READY event. */
-#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
-#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
-#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
-#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
-#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: LPCOMP_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 3 : Disable interrupt on CROSS event. */
-#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
-#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
-#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
-#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
-#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 2 : Disable interrupt on UP event. */
-#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
-#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
-#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */
-#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */
-#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on DOWN event. */
-#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
-#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
-#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
-#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
-#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on READY event. */
-#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
-#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
-#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
-#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
-#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: LPCOMP_RESULT */
-/* Description: Result of last compare. */
-
-/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
-#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
-#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
-#define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */
-#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */
-
-/* Register: LPCOMP_ENABLE */
-/* Description: Enable the LPCOMP. */
-
-/* Bits 1..0 : Enable or disable LPCOMP. */
-#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */
-#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */
-
-/* Register: LPCOMP_PSEL */
-/* Description: Input pin select. */
-
-/* Bits 2..0 : Analog input pin select. */
-#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
-#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
-#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */
-#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */
-#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */
-#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */
-#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */
-#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */
-#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */
-#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */
-
-/* Register: LPCOMP_REFSEL */
-/* Description: Reference select. */
-
-/* Bits 2..0 : Reference select. */
-#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
-#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
-#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use supply with a 1/8 prescaler as reference. */
-#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use supply with a 2/8 prescaler as reference. */
-#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use supply with a 3/8 prescaler as reference. */
-#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use supply with a 4/8 prescaler as reference. */
-#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use supply with a 5/8 prescaler as reference. */
-#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use supply with a 6/8 prescaler as reference. */
-#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use supply with a 7/8 prescaler as reference. */
-#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */
-
-/* Register: LPCOMP_EXTREFSEL */
-/* Description: External reference select. */
-
-/* Bit 0 : External analog reference pin selection. */
-#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
-#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
-#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */
-#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */
-
-/* Register: LPCOMP_ANADETECT */
-/* Description: Analog detect configuration. */
-
-/* Bits 1..0 : Analog detect configuration. */
-#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
-#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
-#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and downwards crossing. */
-#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */
-#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */
-
-/* Register: LPCOMP_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define LPCOMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: MPU */
-/* Description: Memory Protection Unit. */
-
-/* Register: MPU_PERR0 */
-/* Description: Configuration of peripherals in mpu regions. */
-
-/* Bit 31 : PPI region configuration. */
-#define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */
-#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */
-#define MPU_PERR0_PPI_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_PPI_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 30 : NVMC region configuration. */
-#define MPU_PERR0_NVMC_Pos (30UL) /*!< Position of NVMC field. */
-#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /*!< Bit mask of NVMC field. */
-#define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 19 : LPCOMP region configuration. */
-#define MPU_PERR0_LPCOMP_Pos (19UL) /*!< Position of LPCOMP field. */
-#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
-#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 18 : QDEC region configuration. */
-#define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */
-#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /*!< Bit mask of QDEC field. */
-#define MPU_PERR0_QDEC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_QDEC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 17 : RTC1 region configuration. */
-#define MPU_PERR0_RTC1_Pos (17UL) /*!< Position of RTC1 field. */
-#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /*!< Bit mask of RTC1 field. */
-#define MPU_PERR0_RTC1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_RTC1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 16 : WDT region configuration. */
-#define MPU_PERR0_WDT_Pos (16UL) /*!< Position of WDT field. */
-#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /*!< Bit mask of WDT field. */
-#define MPU_PERR0_WDT_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_WDT_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 15 : CCM and AAR region configuration. */
-#define MPU_PERR0_CCM_AAR_Pos (15UL) /*!< Position of CCM_AAR field. */
-#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /*!< Bit mask of CCM_AAR field. */
-#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 14 : ECB region configuration. */
-#define MPU_PERR0_ECB_Pos (14UL) /*!< Position of ECB field. */
-#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /*!< Bit mask of ECB field. */
-#define MPU_PERR0_ECB_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_ECB_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 13 : RNG region configuration. */
-#define MPU_PERR0_RNG_Pos (13UL) /*!< Position of RNG field. */
-#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /*!< Bit mask of RNG field. */
-#define MPU_PERR0_RNG_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_RNG_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 12 : TEMP region configuration. */
-#define MPU_PERR0_TEMP_Pos (12UL) /*!< Position of TEMP field. */
-#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /*!< Bit mask of TEMP field. */
-#define MPU_PERR0_TEMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_TEMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 11 : RTC0 region configuration. */
-#define MPU_PERR0_RTC0_Pos (11UL) /*!< Position of RTC0 field. */
-#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /*!< Bit mask of RTC0 field. */
-#define MPU_PERR0_RTC0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_RTC0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 10 : TIMER2 region configuration. */
-#define MPU_PERR0_TIMER2_Pos (10UL) /*!< Position of TIMER2 field. */
-#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /*!< Bit mask of TIMER2 field. */
-#define MPU_PERR0_TIMER2_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_TIMER2_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 9 : TIMER1 region configuration. */
-#define MPU_PERR0_TIMER1_Pos (9UL) /*!< Position of TIMER1 field. */
-#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /*!< Bit mask of TIMER1 field. */
-#define MPU_PERR0_TIMER1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_TIMER1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 8 : TIMER0 region configuration. */
-#define MPU_PERR0_TIMER0_Pos (8UL) /*!< Position of TIMER0 field. */
-#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /*!< Bit mask of TIMER0 field. */
-#define MPU_PERR0_TIMER0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_TIMER0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 7 : ADC region configuration. */
-#define MPU_PERR0_ADC_Pos (7UL) /*!< Position of ADC field. */
-#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /*!< Bit mask of ADC field. */
-#define MPU_PERR0_ADC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_ADC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 6 : GPIOTE region configuration. */
-#define MPU_PERR0_GPIOTE_Pos (6UL) /*!< Position of GPIOTE field. */
-#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /*!< Bit mask of GPIOTE field. */
-#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 4 : SPI1 and TWI1 region configuration. */
-#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /*!< Position of SPI1_TWI1 field. */
-#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /*!< Bit mask of SPI1_TWI1 field. */
-#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 3 : SPI0 and TWI0 region configuration. */
-#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /*!< Position of SPI0_TWI0 field. */
-#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /*!< Bit mask of SPI0_TWI0 field. */
-#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 2 : UART0 region configuration. */
-#define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */
-#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /*!< Bit mask of UART0 field. */
-#define MPU_PERR0_UART0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_UART0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 1 : RADIO region configuration. */
-#define MPU_PERR0_RADIO_Pos (1UL) /*!< Position of RADIO field. */
-#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /*!< Bit mask of RADIO field. */
-#define MPU_PERR0_RADIO_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_RADIO_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 0 : POWER_CLOCK region configuration. */
-#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /*!< Position of POWER_CLOCK field. */
-#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /*!< Bit mask of POWER_CLOCK field. */
-#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Register: MPU_PROTENSET0 */
-/* Description: Erase and write protection bit enable set register. */
-
-/* Bit 31 : Protection enable for region 31. */
-#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */
-#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /*!< Bit mask of PROTREG31 field. */
-#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 30 : Protection enable for region 30. */
-#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /*!< Position of PROTREG30 field. */
-#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /*!< Bit mask of PROTREG30 field. */
-#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 29 : Protection enable for region 29. */
-#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /*!< Position of PROTREG29 field. */
-#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /*!< Bit mask of PROTREG29 field. */
-#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 28 : Protection enable for region 28. */
-#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /*!< Position of PROTREG28 field. */
-#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /*!< Bit mask of PROTREG28 field. */
-#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 27 : Protection enable for region 27. */
-#define MPU_PROTENSET0_PROTREG27_Pos (27UL) /*!< Position of PROTREG27 field. */
-#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /*!< Bit mask of PROTREG27 field. */
-#define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 26 : Protection enable for region 26. */
-#define MPU_PROTENSET0_PROTREG26_Pos (26UL) /*!< Position of PROTREG26 field. */
-#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /*!< Bit mask of PROTREG26 field. */
-#define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 25 : Protection enable for region 25. */
-#define MPU_PROTENSET0_PROTREG25_Pos (25UL) /*!< Position of PROTREG25 field. */
-#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /*!< Bit mask of PROTREG25 field. */
-#define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 24 : Protection enable for region 24. */
-#define MPU_PROTENSET0_PROTREG24_Pos (24UL) /*!< Position of PROTREG24 field. */
-#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /*!< Bit mask of PROTREG24 field. */
-#define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 23 : Protection enable for region 23. */
-#define MPU_PROTENSET0_PROTREG23_Pos (23UL) /*!< Position of PROTREG23 field. */
-#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /*!< Bit mask of PROTREG23 field. */
-#define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 22 : Protection enable for region 22. */
-#define MPU_PROTENSET0_PROTREG22_Pos (22UL) /*!< Position of PROTREG22 field. */
-#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /*!< Bit mask of PROTREG22 field. */
-#define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 21 : Protection enable for region 21. */
-#define MPU_PROTENSET0_PROTREG21_Pos (21UL) /*!< Position of PROTREG21 field. */
-#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /*!< Bit mask of PROTREG21 field. */
-#define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 20 : Protection enable for region 20. */
-#define MPU_PROTENSET0_PROTREG20_Pos (20UL) /*!< Position of PROTREG20 field. */
-#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /*!< Bit mask of PROTREG20 field. */
-#define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 19 : Protection enable for region 19. */
-#define MPU_PROTENSET0_PROTREG19_Pos (19UL) /*!< Position of PROTREG19 field. */
-#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /*!< Bit mask of PROTREG19 field. */
-#define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 18 : Protection enable for region 18. */
-#define MPU_PROTENSET0_PROTREG18_Pos (18UL) /*!< Position of PROTREG18 field. */
-#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /*!< Bit mask of PROTREG18 field. */
-#define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 17 : Protection enable for region 17. */
-#define MPU_PROTENSET0_PROTREG17_Pos (17UL) /*!< Position of PROTREG17 field. */
-#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /*!< Bit mask of PROTREG17 field. */
-#define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 16 : Protection enable for region 16. */
-#define MPU_PROTENSET0_PROTREG16_Pos (16UL) /*!< Position of PROTREG16 field. */
-#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /*!< Bit mask of PROTREG16 field. */
-#define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 15 : Protection enable for region 15. */
-#define MPU_PROTENSET0_PROTREG15_Pos (15UL) /*!< Position of PROTREG15 field. */
-#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /*!< Bit mask of PROTREG15 field. */
-#define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 14 : Protection enable for region 14. */
-#define MPU_PROTENSET0_PROTREG14_Pos (14UL) /*!< Position of PROTREG14 field. */
-#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /*!< Bit mask of PROTREG14 field. */
-#define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 13 : Protection enable for region 13. */
-#define MPU_PROTENSET0_PROTREG13_Pos (13UL) /*!< Position of PROTREG13 field. */
-#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /*!< Bit mask of PROTREG13 field. */
-#define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 12 : Protection enable for region 12. */
-#define MPU_PROTENSET0_PROTREG12_Pos (12UL) /*!< Position of PROTREG12 field. */
-#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /*!< Bit mask of PROTREG12 field. */
-#define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 11 : Protection enable for region 11. */
-#define MPU_PROTENSET0_PROTREG11_Pos (11UL) /*!< Position of PROTREG11 field. */
-#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /*!< Bit mask of PROTREG11 field. */
-#define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 10 : Protection enable for region 10. */
-#define MPU_PROTENSET0_PROTREG10_Pos (10UL) /*!< Position of PROTREG10 field. */
-#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /*!< Bit mask of PROTREG10 field. */
-#define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 9 : Protection enable for region 9. */
-#define MPU_PROTENSET0_PROTREG9_Pos (9UL) /*!< Position of PROTREG9 field. */
-#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /*!< Bit mask of PROTREG9 field. */
-#define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 8 : Protection enable for region 8. */
-#define MPU_PROTENSET0_PROTREG8_Pos (8UL) /*!< Position of PROTREG8 field. */
-#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /*!< Bit mask of PROTREG8 field. */
-#define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 7 : Protection enable for region 7. */
-#define MPU_PROTENSET0_PROTREG7_Pos (7UL) /*!< Position of PROTREG7 field. */
-#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /*!< Bit mask of PROTREG7 field. */
-#define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 6 : Protection enable for region 6. */
-#define MPU_PROTENSET0_PROTREG6_Pos (6UL) /*!< Position of PROTREG6 field. */
-#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /*!< Bit mask of PROTREG6 field. */
-#define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 5 : Protection enable for region 5. */
-#define MPU_PROTENSET0_PROTREG5_Pos (5UL) /*!< Position of PROTREG5 field. */
-#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /*!< Bit mask of PROTREG5 field. */
-#define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 4 : Protection enable for region 4. */
-#define MPU_PROTENSET0_PROTREG4_Pos (4UL) /*!< Position of PROTREG4 field. */
-#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /*!< Bit mask of PROTREG4 field. */
-#define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 3 : Protection enable for region 3. */
-#define MPU_PROTENSET0_PROTREG3_Pos (3UL) /*!< Position of PROTREG3 field. */
-#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /*!< Bit mask of PROTREG3 field. */
-#define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 2 : Protection enable for region 2. */
-#define MPU_PROTENSET0_PROTREG2_Pos (2UL) /*!< Position of PROTREG2 field. */
-#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /*!< Bit mask of PROTREG2 field. */
-#define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 1 : Protection enable for region 1. */
-#define MPU_PROTENSET0_PROTREG1_Pos (1UL) /*!< Position of PROTREG1 field. */
-#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /*!< Bit mask of PROTREG1 field. */
-#define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 0 : Protection enable for region 0. */
-#define MPU_PROTENSET0_PROTREG0_Pos (0UL) /*!< Position of PROTREG0 field. */
-#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /*!< Bit mask of PROTREG0 field. */
-#define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */
-
-/* Register: MPU_PROTENSET1 */
-/* Description: Erase and write protection bit enable set register. */
-
-/* Bit 31 : Protection enable for region 63. */
-#define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */
-#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /*!< Bit mask of PROTREG63 field. */
-#define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 30 : Protection enable for region 62. */
-#define MPU_PROTENSET1_PROTREG62_Pos (30UL) /*!< Position of PROTREG62 field. */
-#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /*!< Bit mask of PROTREG62 field. */
-#define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 29 : Protection enable for region 61. */
-#define MPU_PROTENSET1_PROTREG61_Pos (29UL) /*!< Position of PROTREG61 field. */
-#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /*!< Bit mask of PROTREG61 field. */
-#define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 28 : Protection enable for region 60. */
-#define MPU_PROTENSET1_PROTREG60_Pos (28UL) /*!< Position of PROTREG60 field. */
-#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /*!< Bit mask of PROTREG60 field. */
-#define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 27 : Protection enable for region 59. */
-#define MPU_PROTENSET1_PROTREG59_Pos (27UL) /*!< Position of PROTREG59 field. */
-#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /*!< Bit mask of PROTREG59 field. */
-#define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 26 : Protection enable for region 58. */
-#define MPU_PROTENSET1_PROTREG58_Pos (26UL) /*!< Position of PROTREG58 field. */
-#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /*!< Bit mask of PROTREG58 field. */
-#define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 25 : Protection enable for region 57. */
-#define MPU_PROTENSET1_PROTREG57_Pos (25UL) /*!< Position of PROTREG57 field. */
-#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /*!< Bit mask of PROTREG57 field. */
-#define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 24 : Protection enable for region 56. */
-#define MPU_PROTENSET1_PROTREG56_Pos (24UL) /*!< Position of PROTREG56 field. */
-#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /*!< Bit mask of PROTREG56 field. */
-#define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 23 : Protection enable for region 55. */
-#define MPU_PROTENSET1_PROTREG55_Pos (23UL) /*!< Position of PROTREG55 field. */
-#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /*!< Bit mask of PROTREG55 field. */
-#define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 22 : Protection enable for region 54. */
-#define MPU_PROTENSET1_PROTREG54_Pos (22UL) /*!< Position of PROTREG54 field. */
-#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /*!< Bit mask of PROTREG54 field. */
-#define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 21 : Protection enable for region 53. */
-#define MPU_PROTENSET1_PROTREG53_Pos (21UL) /*!< Position of PROTREG53 field. */
-#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /*!< Bit mask of PROTREG53 field. */
-#define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 20 : Protection enable for region 52. */
-#define MPU_PROTENSET1_PROTREG52_Pos (20UL) /*!< Position of PROTREG52 field. */
-#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /*!< Bit mask of PROTREG52 field. */
-#define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 19 : Protection enable for region 51. */
-#define MPU_PROTENSET1_PROTREG51_Pos (19UL) /*!< Position of PROTREG51 field. */
-#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /*!< Bit mask of PROTREG51 field. */
-#define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 18 : Protection enable for region 50. */
-#define MPU_PROTENSET1_PROTREG50_Pos (18UL) /*!< Position of PROTREG50 field. */
-#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /*!< Bit mask of PROTREG50 field. */
-#define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 17 : Protection enable for region 49. */
-#define MPU_PROTENSET1_PROTREG49_Pos (17UL) /*!< Position of PROTREG49 field. */
-#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /*!< Bit mask of PROTREG49 field. */
-#define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 16 : Protection enable for region 48. */
-#define MPU_PROTENSET1_PROTREG48_Pos (16UL) /*!< Position of PROTREG48 field. */
-#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /*!< Bit mask of PROTREG48 field. */
-#define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 15 : Protection enable for region 47. */
-#define MPU_PROTENSET1_PROTREG47_Pos (15UL) /*!< Position of PROTREG47 field. */
-#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /*!< Bit mask of PROTREG47 field. */
-#define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 14 : Protection enable for region 46. */
-#define MPU_PROTENSET1_PROTREG46_Pos (14UL) /*!< Position of PROTREG46 field. */
-#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /*!< Bit mask of PROTREG46 field. */
-#define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 13 : Protection enable for region 45. */
-#define MPU_PROTENSET1_PROTREG45_Pos (13UL) /*!< Position of PROTREG45 field. */
-#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /*!< Bit mask of PROTREG45 field. */
-#define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 12 : Protection enable for region 44. */
-#define MPU_PROTENSET1_PROTREG44_Pos (12UL) /*!< Position of PROTREG44 field. */
-#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /*!< Bit mask of PROTREG44 field. */
-#define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 11 : Protection enable for region 43. */
-#define MPU_PROTENSET1_PROTREG43_Pos (11UL) /*!< Position of PROTREG43 field. */
-#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /*!< Bit mask of PROTREG43 field. */
-#define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 10 : Protection enable for region 42. */
-#define MPU_PROTENSET1_PROTREG42_Pos (10UL) /*!< Position of PROTREG42 field. */
-#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /*!< Bit mask of PROTREG42 field. */
-#define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 9 : Protection enable for region 41. */
-#define MPU_PROTENSET1_PROTREG41_Pos (9UL) /*!< Position of PROTREG41 field. */
-#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /*!< Bit mask of PROTREG41 field. */
-#define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 8 : Protection enable for region 40. */
-#define MPU_PROTENSET1_PROTREG40_Pos (8UL) /*!< Position of PROTREG40 field. */
-#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /*!< Bit mask of PROTREG40 field. */
-#define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 7 : Protection enable for region 39. */
-#define MPU_PROTENSET1_PROTREG39_Pos (7UL) /*!< Position of PROTREG39 field. */
-#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /*!< Bit mask of PROTREG39 field. */
-#define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 6 : Protection enable for region 38. */
-#define MPU_PROTENSET1_PROTREG38_Pos (6UL) /*!< Position of PROTREG38 field. */
-#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /*!< Bit mask of PROTREG38 field. */
-#define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 5 : Protection enable for region 37. */
-#define MPU_PROTENSET1_PROTREG37_Pos (5UL) /*!< Position of PROTREG37 field. */
-#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /*!< Bit mask of PROTREG37 field. */
-#define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 4 : Protection enable for region 36. */
-#define MPU_PROTENSET1_PROTREG36_Pos (4UL) /*!< Position of PROTREG36 field. */
-#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /*!< Bit mask of PROTREG36 field. */
-#define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 3 : Protection enable for region 35. */
-#define MPU_PROTENSET1_PROTREG35_Pos (3UL) /*!< Position of PROTREG35 field. */
-#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /*!< Bit mask of PROTREG35 field. */
-#define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 2 : Protection enable for region 34. */
-#define MPU_PROTENSET1_PROTREG34_Pos (2UL) /*!< Position of PROTREG34 field. */
-#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /*!< Bit mask of PROTREG34 field. */
-#define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 1 : Protection enable for region 33. */
-#define MPU_PROTENSET1_PROTREG33_Pos (1UL) /*!< Position of PROTREG33 field. */
-#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /*!< Bit mask of PROTREG33 field. */
-#define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 0 : Protection enable for region 32. */
-#define MPU_PROTENSET1_PROTREG32_Pos (0UL) /*!< Position of PROTREG32 field. */
-#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /*!< Bit mask of PROTREG32 field. */
-#define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */
-
-/* Register: MPU_DISABLEINDEBUG */
-/* Description: Disable erase and write protection mechanism in debug mode. */
-
-/* Bit 0 : Disable protection mechanism in debug mode. */
-#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
-#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
-#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */
-#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */
-
-/* Register: MPU_PROTBLOCKSIZE */
-/* Description: Erase and write protection block size. */
-
-/* Bits 1..0 : Erase and write protection block size. */
-#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /*!< Position of PROTBLOCKSIZE field. */
-#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /*!< Bit mask of PROTBLOCKSIZE field. */
-#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /*!< Erase and write protection block size is 4k. */
-
-
-/* Peripheral: NVMC */
-/* Description: Non Volatile Memory Controller. */
-
-/* Register: NVMC_READY */
-/* Description: Ready flag. */
-
-/* Bit 0 : NVMC ready. */
-#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
-#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
-#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation). */
-#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready. */
-
-/* Register: NVMC_CONFIG */
-/* Description: Configuration register. */
-
-/* Bits 1..0 : Program write enable. */
-#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
-#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
-#define NVMC_CONFIG_WEN_Ren (0x00UL) /*!< Read only access. */
-#define NVMC_CONFIG_WEN_Wen (0x01UL) /*!< Write enabled. */
-#define NVMC_CONFIG_WEN_Een (0x02UL) /*!< Erase enabled. */
-
-/* Register: NVMC_ERASEALL */
-/* Description: Register for erasing all non-volatile user memory. */
-
-/* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
-#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
-#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
-#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation. */
-#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase. */
-
-/* Register: NVMC_ERASEUICR */
-/* Description: Register for start erasing User Information Congfiguration Registers. */
-
-/* Bit 0 : It can only be used when all contents of code region 1 are erased. */
-#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
-#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
-#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation. */
-#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start UICR erase. */
-
-
-/* Peripheral: POWER */
-/* Description: Power Control. */
-
-/* Register: POWER_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 2 : Enable interrupt on POFWARN event. */
-#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
-#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
-#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
-#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
-#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: POWER_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 2 : Disable interrupt on POFWARN event. */
-#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
-#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
-#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
-#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
-#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: POWER_RESETREAS */
-/* Description: Reset reason. */
-
-/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
-#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
-#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
-#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Reset not detected. */
-#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Reset detected. */
-
-/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
-#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
-#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
-#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Reset not detected. */
-#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Reset detected. */
-
-/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
-#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
-#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
-#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Reset not detected. */
-#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Reset detected. */
-
-/* Bit 3 : Reset from CPU lock-up detected. */
-#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
-#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
-#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Reset not detected. */
-#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Reset detected. */
-
-/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
-#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
-#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
-#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Reset not detected. */
-#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Reset detected. */
-
-/* Bit 1 : Reset from watchdog detected. */
-#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
-#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
-#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Reset not detected. */
-#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Reset detected. */
-
-/* Bit 0 : Reset from pin-reset detected. */
-#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
-#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
-#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Reset not detected. */
-#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Reset detected. */
-
-/* Register: POWER_RAMSTATUS */
-/* Description: Ram status register. */
-
-/* Bit 3 : RAM block 3 status. */
-#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
-#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
-#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< RAM block 3 is off or powering up. */
-#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< RAM block 3 is on. */
-
-/* Bit 2 : RAM block 2 status. */
-#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
-#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
-#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< RAM block 2 is off or powering up. */
-#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< RAM block 2 is on. */
-
-/* Bit 1 : RAM block 1 status. */
-#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
-#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
-#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< RAM block 1 is off or powering up. */
-#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< RAM block 1 is on. */
-
-/* Bit 0 : RAM block 0 status. */
-#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
-#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
-#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< RAM block 0 is off or powering up. */
-#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< RAM block 0 is on. */
-
-/* Register: POWER_SYSTEMOFF */
-/* Description: System off register. */
-
-/* Bit 0 : Enter system off mode. */
-#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
-#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
-#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enter system off mode. */
-
-/* Register: POWER_POFCON */
-/* Description: Power failure configuration. */
-
-/* Bits 2..1 : Set threshold level. */
-#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
-#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
-#define POWER_POFCON_THRESHOLD_V21 (0x00UL) /*!< Set threshold to 2.1Volts. */
-#define POWER_POFCON_THRESHOLD_V23 (0x01UL) /*!< Set threshold to 2.3Volts. */
-#define POWER_POFCON_THRESHOLD_V25 (0x02UL) /*!< Set threshold to 2.5Volts. */
-#define POWER_POFCON_THRESHOLD_V27 (0x03UL) /*!< Set threshold to 2.7Volts. */
-
-/* Bit 0 : Power failure comparator enable. */
-#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
-#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
-#define POWER_POFCON_POF_Disabled (0UL) /*!< Disabled. */
-#define POWER_POFCON_POF_Enabled (1UL) /*!< Enabled. */
-
-/* Register: POWER_GPREGRET */
-/* Description: General purpose retention register. This register is a retained register. */
-
-/* Bits 7..0 : General purpose retention register. */
-#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
-#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
-
-/* Register: POWER_RAMON */
-/* Description: Ram on/off. */
-
-/* Bit 17 : RAM block 1 behaviour in OFF mode. */
-#define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
-#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
-#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in OFF mode. */
-#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< RAM block 1 ON in OFF mode. */
-
-/* Bit 16 : RAM block 0 behaviour in OFF mode. */
-#define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
-#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
-#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */
-#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */
-
-/* Bit 1 : RAM block 1 behaviour in ON mode. */
-#define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
-#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
-#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in ON mode. */
-#define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< RAM block 1 ON in ON mode. */
-
-/* Bit 0 : RAM block 0 behaviour in ON mode. */
-#define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
-#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
-#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in ON mode. */
-#define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< RAM block 0 ON in ON mode. */
-
-/* Register: POWER_RESET */
-/* Description: Pin reset functionality configuration register. This register is a retained register. */
-
-/* Bit 0 : Enable or disable pin reset in debug interface mode. */
-#define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
-#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
-#define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */
-#define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */
-
-/* Register: POWER_RAMONB */
-/* Description: Ram on/off. */
-
-/* Bit 17 : RAM block 3 behaviour in OFF mode. */
-#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */
-#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
-#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */
-#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */
-
-/* Bit 16 : RAM block 2 behaviour in OFF mode. */
-#define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */
-#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
-#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */
-#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */
-
-/* Bit 1 : RAM block 3 behaviour in ON mode. */
-#define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */
-#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
-#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< RAM block 33 OFF in ON mode. */
-#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */
-
-/* Bit 0 : RAM block 2 behaviour in ON mode. */
-#define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */
-#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
-#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */
-#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */
-
-/* Register: POWER_DCDCEN */
-/* Description: DCDC converter enable configuration register. */
-
-/* Bit 0 : Enable DCDC converter. */
-#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
-#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
-#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */
-#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */
-
-/* Register: POWER_DCDCFORCE */
-/* Description: DCDC power-up force register. */
-
-/* Bit 1 : DCDC power-up force on. */
-#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /*!< Position of FORCEON field. */
-#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /*!< Bit mask of FORCEON field. */
-#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /*!< No force. */
-#define POWER_DCDCFORCE_FORCEON_Force (1UL) /*!< Force. */
-
-/* Bit 0 : DCDC power-up force off. */
-#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */
-#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */
-#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /*!< No force. */
-#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /*!< Force. */
-
-
-/* Peripheral: PPI */
-/* Description: PPI controller. */
-
-/* Register: PPI_CHEN */
-/* Description: Channel enable. */
-
-/* Bit 31 : Enable PPI channel 31. */
-#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
-#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
-#define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 30 : Enable PPI channel 30. */
-#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
-#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
-#define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 29 : Enable PPI channel 29. */
-#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
-#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
-#define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 28 : Enable PPI channel 28. */
-#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
-#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
-#define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 27 : Enable PPI channel 27. */
-#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
-#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
-#define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 26 : Enable PPI channel 26. */
-#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
-#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
-#define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 25 : Enable PPI channel 25. */
-#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
-#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
-#define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 24 : Enable PPI channel 24. */
-#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
-#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
-#define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 23 : Enable PPI channel 23. */
-#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
-#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
-#define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 22 : Enable PPI channel 22. */
-#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
-#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
-#define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 21 : Enable PPI channel 21. */
-#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
-#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
-#define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 20 : Enable PPI channel 20. */
-#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
-#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
-#define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 15 : Enable PPI channel 15. */
-#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
-#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
-#define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 14 : Enable PPI channel 14. */
-#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
-#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
-#define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 13 : Enable PPI channel 13. */
-#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
-#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
-#define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 12 : Enable PPI channel 12. */
-#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
-#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
-#define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 11 : Enable PPI channel 11. */
-#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
-#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
-#define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 10 : Enable PPI channel 10. */
-#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
-#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
-#define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 9 : Enable PPI channel 9. */
-#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
-#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
-#define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 8 : Enable PPI channel 8. */
-#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
-#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
-#define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 7 : Enable PPI channel 7. */
-#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
-#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
-#define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 6 : Enable PPI channel 6. */
-#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
-#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
-#define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 5 : Enable PPI channel 5. */
-#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
-#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
-#define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 4 : Enable PPI channel 4. */
-#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
-#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
-#define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 3 : Enable PPI channel 3. */
-#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
-#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
-#define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */
-#define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */
-
-/* Bit 2 : Enable PPI channel 2. */
-#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
-#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
-#define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 1 : Enable PPI channel 1. */
-#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
-#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
-#define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 0 : Enable PPI channel 0. */
-#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
-#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
-#define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */
-
-/* Register: PPI_CHENSET */
-/* Description: Channel enable set. */
-
-/* Bit 31 : Enable PPI channel 31. */
-#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
-#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
-#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 30 : Enable PPI channel 30. */
-#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
-#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
-#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 29 : Enable PPI channel 29. */
-#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
-#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
-#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 28 : Enable PPI channel 28. */
-#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
-#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
-#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 27 : Enable PPI channel 27. */
-#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
-#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
-#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 26 : Enable PPI channel 26. */
-#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
-#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
-#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 25 : Enable PPI channel 25. */
-#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
-#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
-#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 24 : Enable PPI channel 24. */
-#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
-#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
-#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 23 : Enable PPI channel 23. */
-#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
-#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
-#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 22 : Enable PPI channel 22. */
-#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
-#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
-#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 21 : Enable PPI channel 21. */
-#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
-#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
-#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 20 : Enable PPI channel 20. */
-#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
-#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
-#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 15 : Enable PPI channel 15. */
-#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
-#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
-#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 14 : Enable PPI channel 14. */
-#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
-#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
-#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 13 : Enable PPI channel 13. */
-#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
-#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
-#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 12 : Enable PPI channel 12. */
-#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
-#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
-#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 11 : Enable PPI channel 11. */
-#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
-#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
-#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 10 : Enable PPI channel 10. */
-#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
-#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
-#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 9 : Enable PPI channel 9. */
-#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
-#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
-#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 8 : Enable PPI channel 8. */
-#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
-#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
-#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 7 : Enable PPI channel 7. */
-#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
-#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
-#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 6 : Enable PPI channel 6. */
-#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
-#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
-#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 5 : Enable PPI channel 5. */
-#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
-#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
-#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 4 : Enable PPI channel 4. */
-#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
-#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
-#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 3 : Enable PPI channel 3. */
-#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
-#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
-#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 2 : Enable PPI channel 2. */
-#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
-#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
-#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 1 : Enable PPI channel 1. */
-#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
-#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
-#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 0 : Enable PPI channel 0. */
-#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
-#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
-#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */
-
-/* Register: PPI_CHENCLR */
-/* Description: Channel enable clear. */
-
-/* Bit 31 : Disable PPI channel 31. */
-#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
-#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
-#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 30 : Disable PPI channel 30. */
-#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
-#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
-#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 29 : Disable PPI channel 29. */
-#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
-#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
-#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 28 : Disable PPI channel 28. */
-#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
-#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
-#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 27 : Disable PPI channel 27. */
-#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
-#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
-#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 26 : Disable PPI channel 26. */
-#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
-#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
-#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 25 : Disable PPI channel 25. */
-#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
-#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
-#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 24 : Disable PPI channel 24. */
-#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
-#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
-#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 23 : Disable PPI channel 23. */
-#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
-#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
-#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 22 : Disable PPI channel 22. */
-#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
-#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
-#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 21 : Disable PPI channel 21. */
-#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
-#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
-#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 20 : Disable PPI channel 20. */
-#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
-#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
-#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 15 : Disable PPI channel 15. */
-#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
-#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
-#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 14 : Disable PPI channel 14. */
-#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
-#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
-#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 13 : Disable PPI channel 13. */
-#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
-#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
-#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 12 : Disable PPI channel 12. */
-#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
-#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
-#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 11 : Disable PPI channel 11. */
-#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
-#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
-#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 10 : Disable PPI channel 10. */
-#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
-#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
-#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 9 : Disable PPI channel 9. */
-#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
-#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
-#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 8 : Disable PPI channel 8. */
-#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
-#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
-#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 7 : Disable PPI channel 7. */
-#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
-#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
-#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 6 : Disable PPI channel 6. */
-#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
-#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
-#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 5 : Disable PPI channel 5. */
-#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
-#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
-#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 4 : Disable PPI channel 4. */
-#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
-#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
-#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 3 : Disable PPI channel 3. */
-#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
-#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
-#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 2 : Disable PPI channel 2. */
-#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
-#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
-#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 1 : Disable PPI channel 1. */
-#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
-#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
-#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 0 : Disable PPI channel 0. */
-#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
-#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
-#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */
-
-/* Register: PPI_CHG */
-/* Description: Channel group configuration. */
-
-/* Bit 31 : Include CH31 in channel group. */
-#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
-#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
-#define PPI_CHG_CH31_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH31_Included (1UL) /*!< Channel included. */
-
-/* Bit 30 : Include CH30 in channel group. */
-#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
-#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
-#define PPI_CHG_CH30_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH30_Included (1UL) /*!< Channel included. */
-
-/* Bit 29 : Include CH29 in channel group. */
-#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
-#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
-#define PPI_CHG_CH29_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH29_Included (1UL) /*!< Channel included. */
-
-/* Bit 28 : Include CH28 in channel group. */
-#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
-#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
-#define PPI_CHG_CH28_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH28_Included (1UL) /*!< Channel included. */
-
-/* Bit 27 : Include CH27 in channel group. */
-#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
-#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
-#define PPI_CHG_CH27_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH27_Included (1UL) /*!< Channel included. */
-
-/* Bit 26 : Include CH26 in channel group. */
-#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
-#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
-#define PPI_CHG_CH26_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH26_Included (1UL) /*!< Channel included. */
-
-/* Bit 25 : Include CH25 in channel group. */
-#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
-#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
-#define PPI_CHG_CH25_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH25_Included (1UL) /*!< Channel included. */
-
-/* Bit 24 : Include CH24 in channel group. */
-#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
-#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
-#define PPI_CHG_CH24_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH24_Included (1UL) /*!< Channel included. */
-
-/* Bit 23 : Include CH23 in channel group. */
-#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
-#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
-#define PPI_CHG_CH23_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH23_Included (1UL) /*!< Channel included. */
-
-/* Bit 22 : Include CH22 in channel group. */
-#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
-#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
-#define PPI_CHG_CH22_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH22_Included (1UL) /*!< Channel included. */
-
-/* Bit 21 : Include CH21 in channel group. */
-#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
-#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
-#define PPI_CHG_CH21_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH21_Included (1UL) /*!< Channel included. */
-
-/* Bit 20 : Include CH20 in channel group. */
-#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
-#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
-#define PPI_CHG_CH20_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH20_Included (1UL) /*!< Channel included. */
-
-/* Bit 15 : Include CH15 in channel group. */
-#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
-#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
-#define PPI_CHG_CH15_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH15_Included (1UL) /*!< Channel included. */
-
-/* Bit 14 : Include CH14 in channel group. */
-#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
-#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
-#define PPI_CHG_CH14_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH14_Included (1UL) /*!< Channel included. */
-
-/* Bit 13 : Include CH13 in channel group. */
-#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
-#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
-#define PPI_CHG_CH13_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH13_Included (1UL) /*!< Channel included. */
-
-/* Bit 12 : Include CH12 in channel group. */
-#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
-#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
-#define PPI_CHG_CH12_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH12_Included (1UL) /*!< Channel included. */
-
-/* Bit 11 : Include CH11 in channel group. */
-#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
-#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
-#define PPI_CHG_CH11_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH11_Included (1UL) /*!< Channel included. */
-
-/* Bit 10 : Include CH10 in channel group. */
-#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
-#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
-#define PPI_CHG_CH10_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH10_Included (1UL) /*!< Channel included. */
-
-/* Bit 9 : Include CH9 in channel group. */
-#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
-#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
-#define PPI_CHG_CH9_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH9_Included (1UL) /*!< Channel included. */
-
-/* Bit 8 : Include CH8 in channel group. */
-#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
-#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
-#define PPI_CHG_CH8_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH8_Included (1UL) /*!< Channel included. */
-
-/* Bit 7 : Include CH7 in channel group. */
-#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
-#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
-#define PPI_CHG_CH7_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH7_Included (1UL) /*!< Channel included. */
-
-/* Bit 6 : Include CH6 in channel group. */
-#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
-#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
-#define PPI_CHG_CH6_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH6_Included (1UL) /*!< Channel included. */
-
-/* Bit 5 : Include CH5 in channel group. */
-#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
-#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
-#define PPI_CHG_CH5_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH5_Included (1UL) /*!< Channel included. */
-
-/* Bit 4 : Include CH4 in channel group. */
-#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
-#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
-#define PPI_CHG_CH4_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH4_Included (1UL) /*!< Channel included. */
-
-/* Bit 3 : Include CH3 in channel group. */
-#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
-#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
-#define PPI_CHG_CH3_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH3_Included (1UL) /*!< Channel included. */
-
-/* Bit 2 : Include CH2 in channel group. */
-#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
-#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
-#define PPI_CHG_CH2_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH2_Included (1UL) /*!< Channel included. */
-
-/* Bit 1 : Include CH1 in channel group. */
-#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
-#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
-#define PPI_CHG_CH1_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH1_Included (1UL) /*!< Channel included. */
-
-/* Bit 0 : Include CH0 in channel group. */
-#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
-#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
-#define PPI_CHG_CH0_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */
-
-
-/* Peripheral: PU */
-/* Description: Patch unit. */
-
-/* Register: PU_PATCHADDR */
-/* Description: Relative address of patch instructions. */
-
-/* Bits 24..0 : Relative address of patch instructions. */
-#define PU_PATCHADDR_PATCHADDR_Pos (0UL) /*!< Position of PATCHADDR field. */
-#define PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos) /*!< Bit mask of PATCHADDR field. */
-
-/* Register: PU_PATCHEN */
-/* Description: Patch enable register. */
-
-/* Bit 7 : Patch 7 enabled. */
-#define PU_PATCHEN_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
-#define PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
-#define PU_PATCHEN_PATCH7_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHEN_PATCH7_Enabled (1UL) /*!< Patch enabled. */
-
-/* Bit 6 : Patch 6 enabled. */
-#define PU_PATCHEN_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
-#define PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
-#define PU_PATCHEN_PATCH6_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHEN_PATCH6_Enabled (1UL) /*!< Patch enabled. */
-
-/* Bit 5 : Patch 5 enabled. */
-#define PU_PATCHEN_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
-#define PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
-#define PU_PATCHEN_PATCH5_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHEN_PATCH5_Enabled (1UL) /*!< Patch enabled. */
-
-/* Bit 4 : Patch 4 enabled. */
-#define PU_PATCHEN_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
-#define PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
-#define PU_PATCHEN_PATCH4_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHEN_PATCH4_Enabled (1UL) /*!< Patch enabled. */
-
-/* Bit 3 : Patch 3 enabled. */
-#define PU_PATCHEN_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
-#define PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
-#define PU_PATCHEN_PATCH3_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHEN_PATCH3_Enabled (1UL) /*!< Patch enabled. */
-
-/* Bit 2 : Patch 2 enabled. */
-#define PU_PATCHEN_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
-#define PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
-#define PU_PATCHEN_PATCH2_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHEN_PATCH2_Enabled (1UL) /*!< Patch enabled. */
-
-/* Bit 1 : Patch 1 enabled. */
-#define PU_PATCHEN_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
-#define PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
-#define PU_PATCHEN_PATCH1_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHEN_PATCH1_Enabled (1UL) /*!< Patch enabled. */
-
-/* Bit 0 : Patch 0 enabled. */
-#define PU_PATCHEN_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
-#define PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
-#define PU_PATCHEN_PATCH0_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHEN_PATCH0_Enabled (1UL) /*!< Patch enabled. */
-
-/* Register: PU_PATCHENSET */
-/* Description: Patch enable register. */
-
-/* Bit 7 : Patch 7 enabled. */
-#define PU_PATCHENSET_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
-#define PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
-#define PU_PATCHENSET_PATCH7_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENSET_PATCH7_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENSET_PATCH7_Set (1UL) /*!< Enable patch on write. */
-
-/* Bit 6 : Patch 6 enabled. */
-#define PU_PATCHENSET_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
-#define PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
-#define PU_PATCHENSET_PATCH6_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENSET_PATCH6_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENSET_PATCH6_Set (1UL) /*!< Enable patch on write. */
-
-/* Bit 5 : Patch 5 enabled. */
-#define PU_PATCHENSET_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
-#define PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
-#define PU_PATCHENSET_PATCH5_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENSET_PATCH5_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENSET_PATCH5_Set (1UL) /*!< Enable patch on write. */
-
-/* Bit 4 : Patch 4 enabled. */
-#define PU_PATCHENSET_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
-#define PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
-#define PU_PATCHENSET_PATCH4_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENSET_PATCH4_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENSET_PATCH4_Set (1UL) /*!< Enable patch on write. */
-
-/* Bit 3 : Patch 3 enabled. */
-#define PU_PATCHENSET_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
-#define PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
-#define PU_PATCHENSET_PATCH3_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENSET_PATCH3_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENSET_PATCH3_Set (1UL) /*!< Enable patch on write. */
-
-/* Bit 2 : Patch 2 enabled. */
-#define PU_PATCHENSET_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
-#define PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
-#define PU_PATCHENSET_PATCH2_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENSET_PATCH2_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENSET_PATCH2_Set (1UL) /*!< Enable patch on write. */
-
-/* Bit 1 : Patch 1 enabled. */
-#define PU_PATCHENSET_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
-#define PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
-#define PU_PATCHENSET_PATCH1_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENSET_PATCH1_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENSET_PATCH1_Set (1UL) /*!< Enable patch on write. */
-
-/* Bit 0 : Patch 0 enabled. */
-#define PU_PATCHENSET_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
-#define PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
-#define PU_PATCHENSET_PATCH0_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENSET_PATCH0_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENSET_PATCH0_Set (1UL) /*!< Enable patch on write. */
-
-/* Register: PU_PATCHENCLR */
-/* Description: Patch disable register. */
-
-/* Bit 7 : Patch 7 enabled. */
-#define PU_PATCHENCLR_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
-#define PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
-#define PU_PATCHENCLR_PATCH7_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENCLR_PATCH7_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENCLR_PATCH7_Clear (1UL) /*!< Disable patch on write. */
-
-/* Bit 6 : Patch 6 enabled. */
-#define PU_PATCHENCLR_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
-#define PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
-#define PU_PATCHENCLR_PATCH6_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENCLR_PATCH6_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENCLR_PATCH6_Clear (1UL) /*!< Disable patch on write. */
-
-/* Bit 5 : Patch 5 enabled. */
-#define PU_PATCHENCLR_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
-#define PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
-#define PU_PATCHENCLR_PATCH5_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENCLR_PATCH5_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENCLR_PATCH5_Clear (1UL) /*!< Disable patch on write. */
-
-/* Bit 4 : Patch 4 enabled. */
-#define PU_PATCHENCLR_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
-#define PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
-#define PU_PATCHENCLR_PATCH4_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENCLR_PATCH4_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENCLR_PATCH4_Clear (1UL) /*!< Disable patch on write. */
-
-/* Bit 3 : Patch 3 enabled. */
-#define PU_PATCHENCLR_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
-#define PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
-#define PU_PATCHENCLR_PATCH3_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENCLR_PATCH3_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENCLR_PATCH3_Clear (1UL) /*!< Disable patch on write. */
-
-/* Bit 2 : Patch 2 enabled. */
-#define PU_PATCHENCLR_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
-#define PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
-#define PU_PATCHENCLR_PATCH2_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENCLR_PATCH2_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENCLR_PATCH2_Clear (1UL) /*!< Disable patch on write. */
-
-/* Bit 1 : Patch 1 enabled. */
-#define PU_PATCHENCLR_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
-#define PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
-#define PU_PATCHENCLR_PATCH1_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENCLR_PATCH1_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENCLR_PATCH1_Clear (1UL) /*!< Disable patch on write. */
-
-/* Bit 0 : Patch 0 enabled. */
-#define PU_PATCHENCLR_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
-#define PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
-#define PU_PATCHENCLR_PATCH0_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENCLR_PATCH0_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENCLR_PATCH0_Clear (1UL) /*!< Disable patch on write. */
-
-
-/* Peripheral: QDEC */
-/* Description: Rotary decoder. */
-
-/* Register: QDEC_SHORTS */
-/* Description: Shortcuts for the QDEC. */
-
-/* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */
-#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
-#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
-#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */
-#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
-#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
-#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */
-#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: QDEC_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 2 : Enable interrupt on ACCOF event. */
-#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
-#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
-#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
-#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
-#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on REPORTRDY event. */
-#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
-#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
-#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on SAMPLERDY event. */
-#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
-#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
-#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: QDEC_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 2 : Disable interrupt on ACCOF event. */
-#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
-#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
-#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
-#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
-#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on REPORTRDY event. */
-#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
-#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
-#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on SAMPLERDY event. */
-#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
-#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
-#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: QDEC_ENABLE */
-/* Description: Enable the QDEC. */
-
-/* Bit 0 : Enable or disable QDEC. */
-#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled QDEC. */
-#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QDEC. */
-
-/* Register: QDEC_LEDPOL */
-/* Description: LED output pin polarity. */
-
-/* Bit 0 : LED output pin polarity. */
-#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
-#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
-#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< LED output is active low. */
-#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< LED output is active high. */
-
-/* Register: QDEC_SAMPLEPER */
-/* Description: Sample period. */
-
-/* Bits 2..0 : Sample period. */
-#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
-#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
-#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /*!< 128us sample period. */
-#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /*!< 256us sample period. */
-#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /*!< 512us sample period. */
-#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /*!< 1024us sample period. */
-#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /*!< 2048us sample period. */
-#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /*!< 4096us sample period. */
-#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /*!< 8192us sample period. */
-#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /*!< 16384us sample period. */
-
-/* Register: QDEC_SAMPLE */
-/* Description: Motion sample value. */
-
-/* Bits 31..0 : Last sample taken in compliment to 2. */
-#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
-#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
-
-/* Register: QDEC_REPORTPER */
-/* Description: Number of samples to generate an EVENT_REPORTRDY. */
-
-/* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
-#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
-#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
-#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /*!< 10 samples per report. */
-#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /*!< 40 samples per report. */
-#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /*!< 80 samples per report. */
-#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /*!< 120 samples per report. */
-#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /*!< 160 samples per report. */
-#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /*!< 200 samples per report. */
-#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /*!< 240 samples per report. */
-#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /*!< 280 samples per report. */
-
-/* Register: QDEC_DBFEN */
-/* Description: Enable debouncer input filters. */
-
-/* Bit 0 : Enable debounce input filters. */
-#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
-#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
-#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled. */
-#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled. */
-
-/* Register: QDEC_LEDPRE */
-/* Description: Time LED is switched ON before the sample. */
-
-/* Bits 8..0 : Period in us the LED in switched on prior to sampling. */
-#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
-#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
-
-/* Register: QDEC_ACCDBL */
-/* Description: Accumulated double (error) transitions register. */
-
-/* Bits 3..0 : Accumulated double (error) transitions. */
-#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
-#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
-
-/* Register: QDEC_ACCDBLREAD */
-/* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
-
-/* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
-#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
-#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
-
-/* Register: QDEC_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define QDEC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define QDEC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define QDEC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: RADIO */
-/* Description: The radio. */
-
-/* Register: RADIO_SHORTS */
-/* Description: Shortcuts for the radio. */
-
-/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
-#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
-#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
-#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
-#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
-#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
-#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Shortcut disabled. */
-#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 5 : Shortcut between END event and START task. */
-#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
-#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
-#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */
-#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
-#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
-#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
-#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Shortcut disabled. */
-#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 3 : Shortcut between DISABLED event and RXEN task. */
-#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
-#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
-#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Shortcut disabled. */
-#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 2 : Shortcut between DISABLED event and TXEN task.  */
-#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
-#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
-#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Shortcut disabled. */
-#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 1 : Shortcut between END event and DISABLE task. */
-#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
-#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
-#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Shortcut disabled. */
-#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 0 : Shortcut between READY event and START task. */
-#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
-#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
-#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Shortcut disabled. */
-#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: RADIO_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 10 : Enable interrupt on BCMATCH event. */
-#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
-#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
-#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 7 : Enable interrupt on RSSIEND event. */
-#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
-#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
-#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 6 : Enable interrupt on DEVMISS event. */
-#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
-#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
-#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 5 : Enable interrupt on DEVMATCH event. */
-#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
-#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
-#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 4 : Enable interrupt on DISABLED event. */
-#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
-#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
-#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 3 : Enable interrupt on END event. */
-#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
-#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
-#define RADIO_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 2 : Enable interrupt on PAYLOAD event. */
-#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
-#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
-#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on ADDRESS event. */
-#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
-#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
-#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on READY event. */
-#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
-#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
-#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: RADIO_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 10 : Disable interrupt on BCMATCH event. */
-#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
-#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
-#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 7 : Disable interrupt on RSSIEND event. */
-#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
-#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
-#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 6 : Disable interrupt on DEVMISS event. */
-#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
-#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
-#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 5 : Disable interrupt on DEVMATCH event. */
-#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
-#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
-#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 4 : Disable interrupt on DISABLED event. */
-#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
-#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
-#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 3 : Disable interrupt on END event. */
-#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
-#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
-#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 2 : Disable interrupt on PAYLOAD event. */
-#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
-#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
-#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on ADDRESS event. */
-#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
-#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
-#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on READY event. */
-#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
-#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
-#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: RADIO_CRCSTATUS */
-/* Description: CRC status of received packet. */
-
-/* Bit 0 : CRC status of received packet. */
-#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
-#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
-#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */
-#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */
-
-/* Register: RADIO_CD */
-/* Description: Carrier detect. */
-
-/* Bit 0 : Carrier detect. */
-#define RADIO_CD_CD_Pos (0UL) /*!< Position of CD field. */
-#define RADIO_CD_CD_Msk (0x1UL << RADIO_CD_CD_Pos) /*!< Bit mask of CD field. */
-
-/* Register: RADIO_RXMATCH */
-/* Description: Received address. */
-
-/* Bits 2..0 : Logical address in which previous packet was received. */
-#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
-#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
-
-/* Register: RADIO_RXCRC */
-/* Description: Received CRC. */
-
-/* Bits 23..0 : CRC field of previously received packet. */
-#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
-#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
-
-/* Register: RADIO_DAI */
-/* Description: Device address match index. */
-
-/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */
-#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
-#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
-
-/* Register: RADIO_FREQUENCY */
-/* Description: Frequency. */
-
-/* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task.  */
-#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
-#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
-
-/* Register: RADIO_TXPOWER */
-/* Description: Output power. */
-
-/* Bits 7..0 : Radio output power. Decision point: TXEN task. */
-#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
-#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
-#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */
-#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */
-#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */
-#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */
-#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */
-#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */
-#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */
-#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */
-
-/* Register: RADIO_MODE */
-/* Description: Data rate and modulation. */
-
-/* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
-#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
-#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
-#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /*!< 1Mbit/s Nordic propietary radio mode. */
-#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /*!< 2Mbit/s Nordic propietary radio mode. */
-#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /*!< 250kbit/s Nordic propietary radio mode. */
-#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /*!< 1Mbit/s Bluetooth Low Energy */
-
-/* Register: RADIO_PCNF0 */
-/* Description: Packet configuration 0. */
-
-/* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
-#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
-#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
-
-/* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
-#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
-#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
-
-/* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
-#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
-#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
-
-/* Register: RADIO_PCNF1 */
-/* Description: Packet configuration 1. */
-
-/* Bit 25 : Packet whitening enable. */
-#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
-#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
-#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Whitening disabled. */
-#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Whitening enabled. */
-
-/* Bit 24 : On air endianness of packet length field. Decision point: START task. */
-#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
-#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
-#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */
-#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
-
-/* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
-#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
-#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
-
-/* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
-#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
-#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
-
-/* Bits 7..0 : Maximum length of packet payload in number of bytes. */
-#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
-#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
-
-/* Register: RADIO_PREFIX0 */
-/* Description: Prefixes bytes for logical addresses 0 to 3. */
-
-/* Bits 31..24 : Address prefix 3. Decision point: START task. */
-#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
-#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
-
-/* Bits 23..16 : Address prefix 2. Decision point: START task. */
-#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
-#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
-
-/* Bits 15..8 : Address prefix 1. Decision point: START task. */
-#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
-#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
-
-/* Bits 7..0 : Address prefix 0. Decision point: START task. */
-#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
-#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
-
-/* Register: RADIO_PREFIX1 */
-/* Description: Prefixes bytes for logical addresses 4 to 7. */
-
-/* Bits 31..24 : Address prefix 7. Decision point: START task. */
-#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
-#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
-
-/* Bits 23..16 : Address prefix 6. Decision point: START task. */
-#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
-#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
-
-/* Bits 15..8 : Address prefix 5. Decision point: START task. */
-#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
-#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
-
-/* Bits 7..0 : Address prefix 4. Decision point: START task. */
-#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
-#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
-
-/* Register: RADIO_TXADDRESS */
-/* Description: Transmit address select. */
-
-/* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
-#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
-#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
-
-/* Register: RADIO_RXADDRESSES */
-/* Description: Receive address select. */
-
-/* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
-#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
-#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
-#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Reception disabled. */
-#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Reception enabled. */
-
-/* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
-#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
-#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
-#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Reception disabled. */
-#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Reception enabled. */
-
-/* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
-#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
-#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
-#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Reception disabled. */
-#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Reception enabled. */
-
-/* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
-#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
-#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
-#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Reception disabled. */
-#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Reception enabled. */
-
-/* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
-#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
-#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
-#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Reception disabled. */
-#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Reception enabled. */
-
-/* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
-#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
-#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
-#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Reception disabled. */
-#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Reception enabled. */
-
-/* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
-#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
-#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
-#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Reception disabled. */
-#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Reception enabled. */
-
-/* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
-#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
-#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
-#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Reception disabled. */
-#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Reception enabled. */
-
-/* Register: RADIO_CRCCNF */
-/* Description: CRC configuration. */
-
-/* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
-#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
-#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
-#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< Include packet address in CRC calculation. */
-#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */
-
-/* Bits 1..0 : CRC length. Decision point: START task. */
-#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
-#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
-#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC calculation disabled. */
-#define RADIO_CRCCNF_LEN_One (1UL) /*!< One byte long CRC. */
-#define RADIO_CRCCNF_LEN_Two (2UL) /*!< Two bytes long CRC. */
-#define RADIO_CRCCNF_LEN_Three (3UL) /*!< Three bytes long CRC. */
-
-/* Register: RADIO_CRCPOLY */
-/* Description: CRC polynomial. */
-
-/* Bits 23..0 : CRC polynomial. Decision point: START task. */
-#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
-#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
-
-/* Register: RADIO_CRCINIT */
-/* Description: CRC initial value. */
-
-/* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
-#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
-#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
-
-/* Register: RADIO_TEST */
-/* Description: Test features enable register. */
-
-/* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
-#define RADIO_TEST_PLLLOCK_Pos (1UL) /*!< Position of PLLLOCK field. */
-#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /*!< Bit mask of PLLLOCK field. */
-#define RADIO_TEST_PLLLOCK_Disabled (0UL) /*!< PLL lock disabled. */
-#define RADIO_TEST_PLLLOCK_Enabled (1UL) /*!< PLL lock enabled. */
-
-/* Bit 0 : Constant carrier. Decision point: TXEN task. */
-#define RADIO_TEST_CONSTCARRIER_Pos (0UL) /*!< Position of CONSTCARRIER field. */
-#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /*!< Bit mask of CONSTCARRIER field. */
-#define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /*!< Constant carrier disabled. */
-#define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /*!< Constant carrier enabled. */
-
-/* Register: RADIO_TIFS */
-/* Description: Inter Frame Spacing in microseconds. */
-
-/* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
-#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
-#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
-
-/* Register: RADIO_RSSISAMPLE */
-/* Description: RSSI sample. */
-
-/* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
-#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
-#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
-
-/* Register: RADIO_STATE */
-/* Description: Current radio state. */
-
-/* Bits 3..0 : Current radio state. */
-#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
-#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
-#define RADIO_STATE_STATE_Disabled (0x00UL) /*!< Radio is in the Disabled state. */
-#define RADIO_STATE_STATE_RxRu (0x01UL) /*!< Radio is in the Rx Ramp Up state. */
-#define RADIO_STATE_STATE_RxIdle (0x02UL) /*!< Radio is in the Rx Idle state. */
-#define RADIO_STATE_STATE_Rx (0x03UL) /*!< Radio is in the Rx state. */
-#define RADIO_STATE_STATE_RxDisable (0x04UL) /*!< Radio is in the Rx Disable state. */
-#define RADIO_STATE_STATE_TxRu (0x09UL) /*!< Radio is in the Tx Ramp Up state. */
-#define RADIO_STATE_STATE_TxIdle (0x0AUL) /*!< Radio is in the Tx Idle state. */
-#define RADIO_STATE_STATE_Tx (0x0BUL) /*!< Radio is in the Tx state. */
-#define RADIO_STATE_STATE_TxDisable (0x0CUL) /*!< Radio is in the Tx Disable state. */
-
-/* Register: RADIO_DATAWHITEIV */
-/* Description: Data whitening initial value. */
-
-/* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
-#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
-#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
-
-/* Register: RADIO_DAP */
-/* Description: Device address prefix. */
-
-/* Bits 15..0 : Device address prefix. */
-#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
-#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
-
-/* Register: RADIO_DACNF */
-/* Description: Device address match configuration. */
-
-/* Bit 15 : TxAdd for device address 7. */
-#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
-#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
-
-/* Bit 14 : TxAdd for device address 6. */
-#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
-#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
-
-/* Bit 13 : TxAdd for device address 5. */
-#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
-#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
-
-/* Bit 12 : TxAdd for device address 4. */
-#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
-#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
-
-/* Bit 11 : TxAdd for device address 3. */
-#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
-#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
-
-/* Bit 10 : TxAdd for device address 2. */
-#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
-#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
-
-/* Bit 9 : TxAdd for device address 1. */
-#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
-#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
-
-/* Bit 8 : TxAdd for device address 0. */
-#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
-#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
-
-/* Bit 7 : Enable or disable device address matching using device address 7. */
-#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
-#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
-#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled. */
-#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled. */
-
-/* Bit 6 : Enable or disable device address matching using device address 6. */
-#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
-#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
-#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled. */
-#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled. */
-
-/* Bit 5 : Enable or disable device address matching using device address 5. */
-#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
-#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
-#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled. */
-#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled. */
-
-/* Bit 4 : Enable or disable device address matching using device address 4. */
-#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
-#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
-#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled. */
-#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled. */
-
-/* Bit 3 : Enable or disable device address matching using device address 3. */
-#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
-#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
-#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled. */
-#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled. */
-
-/* Bit 2 : Enable or disable device address matching using device address 2. */
-#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
-#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
-#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled. */
-#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled. */
-
-/* Bit 1 : Enable or disable device address matching using device address 1. */
-#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
-#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
-#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled. */
-#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled. */
-
-/* Bit 0 : Enable or disable device address matching using device address 0. */
-#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
-#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
-#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled. */
-#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled. */
-
-/* Register: RADIO_OVERRIDE0 */
-/* Description: Trim value override register 0. */
-
-/* Bits 31..0 : Trim value override 0. */
-#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */
-#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */
-
-/* Register: RADIO_OVERRIDE1 */
-/* Description: Trim value override register 1. */
-
-/* Bits 31..0 : Trim value override 1. */
-#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */
-#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */
-
-/* Register: RADIO_OVERRIDE2 */
-/* Description: Trim value override register 2. */
-
-/* Bits 31..0 : Trim value override 2. */
-#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */
-#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */
-
-/* Register: RADIO_OVERRIDE3 */
-/* Description: Trim value override register 3. */
-
-/* Bits 31..0 : Trim value override 3. */
-#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */
-#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */
-
-/* Register: RADIO_OVERRIDE4 */
-/* Description: Trim value override register 4. */
-
-/* Bit 31 : Enable or disable override of default trim values. */
-#define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */
-#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */
-#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */
-
-/* Bits 27..0 : Trim value override 4. */
-#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */
-#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */
-
-/* Register: RADIO_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define RADIO_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define RADIO_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: RNG */
-/* Description: Random Number Generator. */
-
-/* Register: RNG_SHORTS */
-/* Description: Shortcuts for the RNG. */
-
-/* Bit 0 : Shortcut between VALRDY event and STOP task. */
-#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
-#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
-#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: RNG_INTENSET */
-/* Description: Interrupt enable set register */
-
-/* Bit 0 : Enable interrupt on VALRDY event. */
-#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
-#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
-#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: RNG_INTENCLR */
-/* Description: Interrupt enable clear register */
-
-/* Bit 0 : Disable interrupt on VALRDY event. */
-#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
-#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
-#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: RNG_CONFIG */
-/* Description: Configuration register. */
-
-/* Bit 0 : Digital error correction enable. */
-#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
-#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
-#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Digital error correction disabled. */
-#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Digital error correction enabled. */
-
-/* Register: RNG_VALUE */
-/* Description: RNG random number. */
-
-/* Bits 7..0 : Generated random number. */
-#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
-#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
-
-/* Register: RNG_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define RNG_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define RNG_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define RNG_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: RTC */
-/* Description: Real time counter 0. */
-
-/* Register: RTC_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 19 : Enable interrupt on COMPARE[3] event. */
-#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
-#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
-#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 18 : Enable interrupt on COMPARE[2] event. */
-#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
-#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
-#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 17 : Enable interrupt on COMPARE[1] event. */
-#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
-#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
-#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 16 : Enable interrupt on COMPARE[0] event. */
-#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
-#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
-#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on OVRFLW event. */
-#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
-#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
-#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on TICK event. */
-#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
-#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
-#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: RTC_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 19 : Disable interrupt on COMPARE[3] event. */
-#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
-#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
-#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 18 : Disable interrupt on COMPARE[2] event. */
-#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
-#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
-#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 17 : Disable interrupt on COMPARE[1] event. */
-#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
-#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
-#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 16 : Disable interrupt on COMPARE[0] event. */
-#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
-#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
-#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on OVRFLW event. */
-#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
-#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
-#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on TICK event. */
-#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
-#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
-#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: RTC_EVTEN */
-/* Description: Configures event enable routing to PPI for each RTC event. */
-
-/* Bit 19 : COMPARE[3] event enable. */
-#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
-#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
-#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Event enabled. */
-
-/* Bit 18 : COMPARE[2] event enable. */
-#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
-#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
-#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Event enabled. */
-
-/* Bit 17 : COMPARE[1] event enable. */
-#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
-#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
-#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Event enabled. */
-
-/* Bit 16 : COMPARE[0] event enable. */
-#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
-#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
-#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Event enabled. */
-
-/* Bit 1 : OVRFLW event enable. */
-#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
-#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
-#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Event enabled. */
-
-/* Bit 0 : TICK event enable. */
-#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
-#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
-#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Event enabled. */
-
-/* Register: RTC_EVTENSET */
-/* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
-
-/* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
-#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
-#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
-#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */
-
-/* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
-#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
-#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
-#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */
-
-/* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
-#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
-#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
-#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */
-
-/* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
-#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
-#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
-#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */
-
-/* Bit 1 : Enable routing to PPI of OVRFLW event. */
-#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
-#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
-#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */
-
-/* Bit 0 : Enable routing to PPI of TICK event. */
-#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
-#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
-#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */
-
-/* Register: RTC_EVTENCLR */
-/* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
-
-/* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
-#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
-#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
-#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable event on write. */
-
-/* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
-#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
-#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
-#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable event on write. */
-
-/* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
-#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
-#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
-#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable event on write. */
-
-/* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
-#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
-#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
-#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable event on write. */
-
-/* Bit 1 : Disable routing to PPI of OVRFLW event. */
-#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
-#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
-#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable event on write. */
-
-/* Bit 0 : Disable routing to PPI of TICK event. */
-#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
-#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
-#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable event on write. */
-
-/* Register: RTC_COUNTER */
-/* Description: Current COUNTER value. */
-
-/* Bits 23..0 : Counter value. */
-#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
-#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
-
-/* Register: RTC_PRESCALER */
-/* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
-
-/* Bits 11..0 : RTC PRESCALER value. */
-#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
-#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
-
-/* Register: RTC_CC */
-/* Description: Capture/compare registers. */
-
-/* Bits 23..0 : Compare value. */
-#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
-#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
-
-/* Register: RTC_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define RTC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define RTC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define RTC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: SPI */
-/* Description: SPI master 0. */
-
-/* Register: SPI_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 2 : Enable interrupt on READY event. */
-#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
-#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
-#define SPI_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPI_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: SPI_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 2 : Disable interrupt on READY event. */
-#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
-#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
-#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: SPI_ENABLE */
-/* Description: Enable SPI. */
-
-/* Bits 2..0 : Enable or disable SPI. */
-#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define SPI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPI. */
-#define SPI_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable SPI. */
-
-/* Register: SPI_RXD */
-/* Description: RX data. */
-
-/* Bits 7..0 : RX data from last transfer. */
-#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
-#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
-
-/* Register: SPI_TXD */
-/* Description: TX data. */
-
-/* Bits 7..0 : TX data for next transfer. */
-#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
-#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
-
-/* Register: SPI_FREQUENCY */
-/* Description: SPI frequency */
-
-/* Bits 31..0 : SPI data rate. */
-#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
-#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
-#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125kbps. */
-#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250kbps. */
-#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500kbps. */
-#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1Mbps. */
-#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2Mbps. */
-#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4Mbps. */
-#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8Mbps. */
-
-/* Register: SPI_CONFIG */
-/* Description: Configuration register. */
-
-/* Bit 2 : Serial clock (SCK) polarity. */
-#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
-#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
-#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
-#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
-
-/* Bit 1 : Serial clock (SCK) phase. */
-#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
-#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
-#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
-#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
-
-/* Bit 0 : Bit order. */
-#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
-#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
-#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
-#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
-
-/* Register: SPI_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define SPI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define SPI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: SPIM */
-/* Description: SPI master with easyDMA 1. */
-
-/* Register: SPIM_SHORTS */
-/* Description: Shortcuts for SPIM. */
-
-/* Bit 17 : Shortcut between END event and START task. */
-#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
-#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
-#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */
-#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: SPIM_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 19 : Enable interrupt on STARTED event. */
-#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
-#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
-#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 8 : Enable interrupt on ENDTX event. */
-#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
-#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
-#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 6 : Enable interrupt on END event. */
-#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
-#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
-#define SPIM_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIM_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIM_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 4 : Enable interrupt on ENDRX event. */
-#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
-#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
-#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on STOPPED event. */
-#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
-#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
-#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: SPIM_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 19 : Disable interrupt on STARTED event. */
-#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
-#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
-#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 8 : Disable interrupt on ENDTX event. */
-#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
-#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
-#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 6 : Disable interrupt on END event. */
-#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
-#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
-#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 4 : Disable interrupt on ENDRX event. */
-#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
-#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
-#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on STOPPED event. */
-#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
-#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
-#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: SPIM_ENABLE */
-/* Description: Enable SPIM. */
-
-/* Bits 3..0 : Enable or disable SPIM. */
-#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIM. */
-#define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /*!< Enable SPIM. */
-
-/* Register: SPIM_FREQUENCY */
-/* Description: SPI frequency. */
-
-/* Bits 31..0 : SPI master data rate. */
-#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
-#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
-#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps. */
-#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */
-#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps. */
-#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps. */
-#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps. */
-#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps. */
-#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps. */
-
-/* Register: SPIM_RXD_PTR */
-/* Description: Data pointer. */
-
-/* Bits 31..0 : Data pointer. */
-#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
-#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
-
-/* Register: SPIM_RXD_MAXCNT */
-/* Description: Maximum number of buffer bytes to receive. */
-
-/* Bits 7..0 : Maximum number of buffer bytes to receive. */
-#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
-#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
-
-/* Register: SPIM_RXD_AMOUNT */
-/* Description: Number of bytes received in the last transaction. */
-
-/* Bits 7..0 : Number of bytes received in the last transaction. */
-#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
-#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
-
-/* Register: SPIM_TXD_PTR */
-/* Description: Data pointer. */
-
-/* Bits 31..0 : Data pointer. */
-#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
-#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
-
-/* Register: SPIM_TXD_MAXCNT */
-/* Description: Maximum number of buffer bytes to send. */
-
-/* Bits 7..0 : Maximum number of buffer bytes to send. */
-#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
-#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
-
-/* Register: SPIM_TXD_AMOUNT */
-/* Description: Number of bytes sent in the last transaction. */
-
-/* Bits 7..0 : Number of bytes sent in the last transaction. */
-#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
-#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
-
-/* Register: SPIM_CONFIG */
-/* Description: Configuration register. */
-
-/* Bit 2 : Serial clock (SCK) polarity. */
-#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
-#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
-#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
-#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
-
-/* Bit 1 : Serial clock (SCK) phase. */
-#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
-#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
-#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
-#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
-
-/* Bit 0 : Bit order. */
-#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
-#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
-#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
-#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
-
-/* Register: SPIM_ORC */
-/* Description: Over-read character. */
-
-/* Bits 7..0 : Over-read character. */
-#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
-#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
-
-/* Register: SPIM_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define SPIM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define SPIM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define SPIM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: SPIS */
-/* Description: SPI slave 1. */
-
-/* Register: SPIS_SHORTS */
-/* Description: Shortcuts for SPIS. */
-
-/* Bit 2 : Shortcut between END event and the ACQUIRE task. */
-#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
-#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
-#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Shortcut disabled. */
-#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: SPIS_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 10 : Enable interrupt on ACQUIRED event. */
-#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
-#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
-#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on END event. */
-#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
-#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
-#define SPIS_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIS_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: SPIS_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 10 : Disable interrupt on ACQUIRED event. */
-#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
-#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
-#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on END event. */
-#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
-#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
-#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: SPIS_SEMSTAT */
-/* Description: Semaphore status. */
-
-/* Bits 1..0 : Semaphore status. */
-#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
-#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
-#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /*!< Semaphore is free. */
-#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /*!< Semaphore is assigned to the CPU. */
-#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /*!< Semaphore is assigned to the SPIS. */
-#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /*!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. */
-
-/* Register: SPIS_STATUS */
-/* Description: Status from last transaction. */
-
-/* Bit 1 : RX buffer overflow detected, and prevented. */
-#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
-#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
-#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Error not present. */
-#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Error present. */
-#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Clear on write. */
-
-/* Bit 0 : TX buffer overread detected, and prevented. */
-#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
-#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
-#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Error not present. */
-#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Error present. */
-#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Clear on write. */
-
-/* Register: SPIS_ENABLE */
-/* Description: Enable SPIS. */
-
-/* Bits 2..0 : Enable or disable SPIS. */
-#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIS. */
-#define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable SPIS. */
-
-/* Register: SPIS_MAXRX */
-/* Description: Maximum number of bytes in the receive buffer. */
-
-/* Bits 7..0 : Maximum number of bytes in the receive buffer. */
-#define SPIS_MAXRX_MAXRX_Pos (0UL) /*!< Position of MAXRX field. */
-#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /*!< Bit mask of MAXRX field. */
-
-/* Register: SPIS_AMOUNTRX */
-/* Description: Number of bytes received in last granted transaction. */
-
-/* Bits 7..0 : Number of bytes received in last granted transaction. */
-#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /*!< Position of AMOUNTRX field. */
-#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /*!< Bit mask of AMOUNTRX field. */
-
-/* Register: SPIS_MAXTX */
-/* Description: Maximum number of bytes in the transmit buffer. */
-
-/* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
-#define SPIS_MAXTX_MAXTX_Pos (0UL) /*!< Position of MAXTX field. */
-#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /*!< Bit mask of MAXTX field. */
-
-/* Register: SPIS_AMOUNTTX */
-/* Description: Number of bytes transmitted in last granted transaction. */
-
-/* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
-#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /*!< Position of AMOUNTTX field. */
-#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /*!< Bit mask of AMOUNTTX field. */
-
-/* Register: SPIS_CONFIG */
-/* Description: Configuration register. */
-
-/* Bit 2 : Serial clock (SCK) polarity. */
-#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
-#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
-#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
-#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
-
-/* Bit 1 : Serial clock (SCK) phase. */
-#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
-#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
-#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
-#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
-
-/* Bit 0 : Bit order. */
-#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
-#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
-#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
-#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
-
-/* Register: SPIS_DEF */
-/* Description: Default character. */
-
-/* Bits 7..0 : Default character. */
-#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
-#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
-
-/* Register: SPIS_ORC */
-/* Description: Over-read character. */
-
-/* Bits 7..0 : Over-read character. */
-#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
-#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
-
-/* Register: SPIS_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define SPIS_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define SPIS_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define SPIS_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: TEMP */
-/* Description: Temperature Sensor. */
-
-/* Register: TEMP_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 0 : Enable interrupt on DATARDY event. */
-#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
-#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
-#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: TEMP_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 0 : Disable interrupt on DATARDY event. */
-#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
-#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
-#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: TEMP_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define TEMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define TEMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define TEMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: TIMER */
-/* Description: Timer 0. */
-
-/* Register: TIMER_SHORTS */
-/* Description: Shortcuts for Timer. */
-
-/* Bit 11 : Shortcut between CC[3] event and the STOP task. */
-#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
-#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
-#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 10 : Shortcut between CC[2] event and the STOP task. */
-#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
-#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
-#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 9 : Shortcut between CC[1] event and the STOP task. */
-#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
-#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
-#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 8 : Shortcut between CC[0] event and the STOP task. */
-#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
-#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
-#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
-#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
-#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
-#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
-#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
-#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
-#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
-#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
-#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
-#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
-#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
-#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
-#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
-#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
-#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
-#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
-#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: TIMER_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 19 : Enable interrupt on COMPARE[3] */
-#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
-#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
-#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
-#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
-#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 18 : Enable interrupt on COMPARE[2] */
-#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
-#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
-#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
-#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
-#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 17 : Enable interrupt on COMPARE[1] */
-#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
-#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
-#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
-#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
-#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 16 : Enable interrupt on COMPARE[0] */
-#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
-#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
-#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
-#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
-#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: TIMER_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 19 : Disable interrupt on COMPARE[3] */
-#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
-#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
-#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
-#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
-#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 18 : Disable interrupt on COMPARE[2] */
-#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
-#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
-#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
-#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
-#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 17 : Disable interrupt on COMPARE[1] */
-#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
-#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
-#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
-#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
-#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 16 : Disable interrupt on COMPARE[0] */
-#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
-#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
-#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
-#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
-#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: TIMER_MODE */
-/* Description: Timer Mode selection. */
-
-/* Bit 0 : Select Normal or Counter mode. */
-#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
-#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
-#define TIMER_MODE_MODE_Timer (0UL) /*!< Timer in Normal mode. */
-#define TIMER_MODE_MODE_Counter (1UL) /*!< Timer in Counter mode. */
-
-/* Register: TIMER_BITMODE */
-/* Description: Sets timer behaviour. */
-
-/* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
-#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
-#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
-#define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /*!< 16-bit timer behaviour. */
-#define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /*!< 8-bit timer behaviour. */
-#define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /*!< 24-bit timer behaviour. */
-#define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /*!< 32-bit timer behaviour. */
-
-/* Register: TIMER_PRESCALER */
-/* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
-
-/* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
-#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
-#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
-
-/* Register: TIMER_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define TIMER_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define TIMER_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define TIMER_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: TWI */
-/* Description: Two-wire interface master 0. */
-
-/* Register: TWI_SHORTS */
-/* Description: Shortcuts for TWI. */
-
-/* Bit 1 : Shortcut between BB event and the STOP task. */
-#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
-#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
-#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 0 : Shortcut between BB event and the SUSPEND task. */
-#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
-#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
-#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Shortcut disabled. */
-#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: TWI_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 18 : Enable interrupt on SUSPENDED event. */
-#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
-#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
-#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 14 : Enable interrupt on BB event. */
-#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
-#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
-#define TWI_INTENSET_BB_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENSET_BB_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 9 : Enable interrupt on ERROR event. */
-#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
-#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
-#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 7 : Enable interrupt on TXDSENT event. */
-#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
-#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
-#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 2 : Enable interrupt on READY event. */
-#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
-#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
-#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on STOPPED event. */
-#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
-#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
-#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: TWI_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 18 : Disable interrupt on SUSPENDED event. */
-#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
-#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
-#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 14 : Disable interrupt on BB event. */
-#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
-#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
-#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 9 : Disable interrupt on ERROR event. */
-#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
-#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
-#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 7 : Disable interrupt on TXDSENT event. */
-#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
-#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
-#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 2 : Disable interrupt on RXDREADY event. */
-#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
-#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
-#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on STOPPED event. */
-#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
-#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
-#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: TWI_ERRORSRC */
-/* Description: Two-wire error source. Write error field to 1 to clear error. */
-
-/* Bit 2 : NACK received after sending a data byte. */
-#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
-#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
-#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Error not present. */
-#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Error present. */
-#define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Clear error on write. */
-
-/* Bit 1 : NACK received after sending the address. */
-#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
-#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
-#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Error not present. */
-#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */
-#define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */
-
-/* Bit 0 : Byte received in RXD register before read of the last received byte (data loss). */
-#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
-#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
-#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */
-#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */
-#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */
-
-/* Register: TWI_ENABLE */
-/* Description: Enable two-wire master. */
-
-/* Bits 2..0 : Enable or disable W2M */
-#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define TWI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled. */
-#define TWI_ENABLE_ENABLE_Enabled (0x05UL) /*!< Enabled. */
-
-/* Register: TWI_RXD */
-/* Description: RX data register. */
-
-/* Bits 7..0 : RX data from last transfer. */
-#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
-#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
-
-/* Register: TWI_TXD */
-/* Description: TX data register. */
-
-/* Bits 7..0 : TX data for next transfer. */
-#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
-#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
-
-/* Register: TWI_FREQUENCY */
-/* Description: Two-wire frequency. */
-
-/* Bits 31..0 : Two-wire master clock frequency. */
-#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
-#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
-#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */
-#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */
-#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps. */
-
-/* Register: TWI_ADDRESS */
-/* Description: Address used in the two-wire transfer. */
-
-/* Bits 6..0 : Two-wire address. */
-#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
-#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
-
-/* Register: TWI_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define TWI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define TWI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define TWI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: UART */
-/* Description: Universal Asynchronous Receiver/Transmitter. */
-
-/* Register: UART_SHORTS */
-/* Description: Shortcuts for UART. */
-
-/* Bit 4 : Shortcut between NCTS event and the STOPRX task. */
-#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
-#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
-#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */
-#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 3 : Shortcut between CTS event and the STARTRX task. */
-#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
-#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
-#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */
-#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: UART_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 17 : Enable interrupt on RXTO event. */
-#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
-#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
-#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 9 : Enable interrupt on ERROR event. */
-#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
-#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
-#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 7 : Enable interrupt on TXRDY event. */
-#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
-#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
-#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 2 : Enable interrupt on RXRDY event. */
-#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
-#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
-#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on NCTS event. */
-#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
-#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
-#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on CTS event. */
-#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
-#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
-#define UART_INTENSET_CTS_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENSET_CTS_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: UART_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 17 : Disable interrupt on RXTO event. */
-#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
-#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
-#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 9 : Disable interrupt on ERROR event. */
-#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
-#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
-#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 7 : Disable interrupt on TXRDY event. */
-#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
-#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
-#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 2 : Disable interrupt on RXRDY event. */
-#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
-#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
-#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on NCTS event. */
-#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
-#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
-#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on CTS event. */
-#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
-#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
-#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: UART_ERRORSRC */
-/* Description: Error source. Write error field to 1 to clear error. */
-
-/* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
-#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
-#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
-#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Error not present. */
-#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Error present. */
-#define UART_ERRORSRC_BREAK_Clear (1UL) /*!< Clear error on write. */
-
-/* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
-#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
-#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
-#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Error not present. */
-#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Error present. */
-#define UART_ERRORSRC_FRAMING_Clear (1UL) /*!< Clear error on write. */
-
-/* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
-#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
-#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
-#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Error not present. */
-#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Error present. */
-#define UART_ERRORSRC_PARITY_Clear (1UL) /*!< Clear error on write. */
-
-/* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
-#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
-#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
-#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */
-#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */
-#define UART_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */
-
-/* Register: UART_ENABLE */
-/* Description: Enable UART and acquire IOs. */
-
-/* Bits 2..0 : Enable or disable UART and acquire IOs. */
-#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define UART_ENABLE_ENABLE_Disabled (0x00UL) /*!< UART disabled. */
-#define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */
-
-/* Register: UART_RXD */
-/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */
-
-/* Bits 7..0 : RX data from previous transfer. Double buffered. */
-#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
-#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
-
-/* Register: UART_TXD */
-/* Description: TXD register. */
-
-/* Bits 7..0 : TX data for transfer. */
-#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
-#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
-
-/* Register: UART_BAUDRATE */
-/* Description: UART Baudrate. */
-
-/* Bits 31..0 : UART baudrate. */
-#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
-#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
-#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */
-
-/* Register: UART_CONFIG */
-/* Description: Configuration of parity and hardware flow control register. */
-
-/* Bits 3..1 : Include parity bit. */
-#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
-#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
-#define UART_CONFIG_PARITY_Excluded (0UL) /*!< Parity bit excluded. */
-#define UART_CONFIG_PARITY_Included (7UL) /*!< Parity bit included. */
-
-/* Bit 0 : Hardware flow control. */
-#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
-#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
-#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Hardware flow control disabled. */
-#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Hardware flow control enabled. */
-
-/* Register: UART_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define UART_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define UART_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define UART_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: UICR */
-/* Description: User Information Configuration. */
-
-/* Register: UICR_RBPCONF */
-/* Description: Readback protection configuration. */
-
-/* Bits 15..8 : Readback protect all code in the device. */
-#define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */
-#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */
-#define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */
-#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */
-
-/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
-#define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */
-#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */
-#define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */
-#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */
-
-/* Register: UICR_XTALFREQ */
-/* Description: Reset value for CLOCK XTALFREQ register. */
-
-/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
-#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
-#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
-#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */
-#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */
-
-/* Register: UICR_FWID */
-/* Description: Firmware ID. */
-
-/* Bits 15..0 : Identification number for the firmware loaded into the chip. */
-#define UICR_FWID_FWID_Pos (0UL) /*!< Position of FWID field. */
-#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /*!< Bit mask of FWID field. */
-
-
-/* Peripheral: WDT */
-/* Description: Watchdog Timer. */
-
-/* Register: WDT_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 0 : Enable interrupt on TIMEOUT event. */
-#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
-#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
-#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
-#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
-#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: WDT_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 0 : Disable interrupt on TIMEOUT event. */
-#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
-#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
-#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
-#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
-#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: WDT_RUNSTATUS */
-/* Description: Watchdog running status. */
-
-/* Bit 0 : Watchdog running status. */
-#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
-#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
-#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog timer is not running. */
-#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog timer is running. */
-
-/* Register: WDT_REQSTATUS */
-/* Description: Request status. */
-
-/* Bit 7 : Request status for RR[7]. */
-#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
-#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
-#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled or has already requested reload. */
-#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled and has not jet requested. */
-
-/* Bit 6 : Request status for RR[6]. */
-#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
-#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
-#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled or has already requested reload. */
-#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled and has not jet requested. */
-
-/* Bit 5 : Request status for RR[5]. */
-#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
-#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
-#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled or has already requested reload. */
-#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled and has not jet requested. */
-
-/* Bit 4 : Request status for RR[4]. */
-#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
-#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
-#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled or has already requested reload. */
-#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled and has not jet requested. */
-
-/* Bit 3 : Request status for RR[3]. */
-#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
-#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
-#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled or has already requested reload. */
-#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled and has not jet requested. */
-
-/* Bit 2 : Request status for RR[2]. */
-#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
-#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
-#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has already requested reload. */
-#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not jet requested. */
-
-/* Bit 1 : Request status for RR[1]. */
-#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
-#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
-#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled or has already requested reload. */
-#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled and has not jet requested. */
-
-/* Bit 0 : Request status for RR[0]. */
-#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
-#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
-#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled or has already requested reload. */
-#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled and has not jet requested. */
-
-/* Register: WDT_RREN */
-/* Description: Reload request enable. */
-
-/* Bit 7 : Enable or disable RR[7] register. */
-#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
-#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
-#define WDT_RREN_RR7_Disabled (0UL) /*!< RR[7] register is disabled. */
-#define WDT_RREN_RR7_Enabled (1UL) /*!< RR[7] register is enabled. */
-
-/* Bit 6 : Enable or disable RR[6] register. */
-#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
-#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
-#define WDT_RREN_RR6_Disabled (0UL) /*!< RR[6] register is disabled. */
-#define WDT_RREN_RR6_Enabled (1UL) /*!< RR[6] register is enabled. */
-
-/* Bit 5 : Enable or disable RR[5] register. */
-#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
-#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
-#define WDT_RREN_RR5_Disabled (0UL) /*!< RR[5] register is disabled. */
-#define WDT_RREN_RR5_Enabled (1UL) /*!< RR[5] register is enabled. */
-
-/* Bit 4 : Enable or disable RR[4] register. */
-#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
-#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
-#define WDT_RREN_RR4_Disabled (0UL) /*!< RR[4] register is disabled. */
-#define WDT_RREN_RR4_Enabled (1UL) /*!< RR[4] register is enabled. */
-
-/* Bit 3 : Enable or disable RR[3] register. */
-#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
-#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
-#define WDT_RREN_RR3_Disabled (0UL) /*!< RR[3] register is disabled. */
-#define WDT_RREN_RR3_Enabled (1UL) /*!< RR[3] register is enabled. */
-
-/* Bit 2 : Enable or disable RR[2] register. */
-#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
-#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
-#define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */
-#define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */
-
-/* Bit 1 : Enable or disable RR[1] register. */
-#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
-#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
-#define WDT_RREN_RR1_Disabled (0UL) /*!< RR[1] register is disabled. */
-#define WDT_RREN_RR1_Enabled (1UL) /*!< RR[1] register is enabled. */
-
-/* Bit 0 : Enable or disable RR[0] register. */
-#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
-#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
-#define WDT_RREN_RR0_Disabled (0UL) /*!< RR[0] register is disabled. */
-#define WDT_RREN_RR0_Enabled (1UL) /*!< RR[0] register is enabled. */
-
-/* Register: WDT_CONFIG */
-/* Description: Configuration register. */
-
-/* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
-#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
-#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
-#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger. */
-#define WDT_CONFIG_HALT_Run (1UL) /*!< Do not pause watchdog while the CPU is halted by the debugger. */
-
-/* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
-#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
-#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
-#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is asleep. */
-#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Do not pause watchdog while the CPU is asleep. */
-
-/* Register: WDT_RR */
-/* Description: Reload requests registers. */
-
-/* Bits 31..0 : Reload register. */
-#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
-#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
-#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer. */
-
-/* Register: WDT_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define WDT_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define WDT_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define WDT_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/*lint --flb "Leave library region" */
-#endif
+/* Copyright (c) 2015, Nordic Semiconductor ASA

+ * All rights reserved.

+ *

+ * Redistribution and use in source and binary forms, with or without

+ * modification, are permitted provided that the following conditions are met:

+ *

+ *   * Redistributions of source code must retain the above copyright notice, this

+ *     list of conditions and the following disclaimer.

+ *

+ *   * Redistributions in binary form must reproduce the above copyright notice,

+ *     this list of conditions and the following disclaimer in the documentation

+ *     and/or other materials provided with the distribution.

+ *

+ *   * Neither the name of Nordic Semiconductor ASA nor the names of its

+ *     contributors may be used to endorse or promote products derived from

+ *     this software without specific prior written permission.

+ *

+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE

+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

+ *

+ */

+#ifndef __NRF51_BITS_H

+#define __NRF51_BITS_H

+

+/*lint ++flb "Enter library region" */

+

+/* Peripheral: AAR */

+/* Description: Accelerated Address Resolver. */

+

+/* Register: AAR_INTENSET */

+/* Description: Interrupt enable set register. */

+

+/* Bit 2 : Enable interrupt on NOTRESOLVED event. */

+#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */

+#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */

+#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */

+#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */

+#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 1 : Enable interrupt on RESOLVED event. */

+#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */

+#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */

+#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */

+#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */

+#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 0 : Enable interrupt on END event. */

+#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */

+#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */

+#define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */

+#define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */

+#define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Register: AAR_INTENCLR */

+/* Description: Interrupt enable clear register. */

+

+/* Bit 2 : Disable interrupt on NOTRESOLVED event. */

+#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */

+#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */

+#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */

+#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */

+#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 1 : Disable interrupt on RESOLVED event. */

+#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */

+#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */

+#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */

+#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */

+#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 0 : Disable interrupt on ENDKSGEN event. */

+#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */

+#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */

+#define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */

+#define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */

+#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Register: AAR_STATUS */

+/* Description: Resolution status. */

+

+/* Bits 3..0 : The IRK used last time an address was resolved. */

+#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */

+#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */

+

+/* Register: AAR_ENABLE */

+/* Description: Enable AAR. */

+

+/* Bits 1..0 : Enable AAR. */

+#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */

+#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */

+#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */

+#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */

+

+/* Register: AAR_NIRK */

+/* Description: Number of Identity root Keys in the IRK data structure. */

+

+/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */

+#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */

+#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */

+

+/* Register: AAR_POWER */

+/* Description: Peripheral power control. */

+

+/* Bit 0 : Peripheral power control. */

+#define AAR_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */

+#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /*!< Bit mask of POWER field. */

+#define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */

+#define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */

+

+

+/* Peripheral: ADC */

+/* Description: Analog to digital converter. */

+

+/* Register: ADC_INTENSET */

+/* Description: Interrupt enable set register. */

+

+/* Bit 0 : Enable interrupt on END event. */

+#define ADC_INTENSET_END_Pos (0UL) /*!< Position of END field. */

+#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /*!< Bit mask of END field. */

+#define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */

+#define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */

+#define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Register: ADC_INTENCLR */

+/* Description: Interrupt enable clear register. */

+

+/* Bit 0 : Disable interrupt on END event. */

+#define ADC_INTENCLR_END_Pos (0UL) /*!< Position of END field. */

+#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */

+#define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */

+#define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */

+#define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Register: ADC_BUSY */

+/* Description: ADC busy register. */

+

+/* Bit 0 : ADC busy register. */

+#define ADC_BUSY_BUSY_Pos (0UL) /*!< Position of BUSY field. */

+#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /*!< Bit mask of BUSY field. */

+#define ADC_BUSY_BUSY_Ready (0UL) /*!< No ongoing ADC conversion is taking place. ADC is ready. */

+#define ADC_BUSY_BUSY_Busy (1UL) /*!< An ADC conversion is taking place. ADC is busy. */

+

+/* Register: ADC_ENABLE */

+/* Description: ADC enable. */

+

+/* Bits 1..0 : ADC enable. */

+#define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */

+#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */

+#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */

+#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. */

+

+/* Register: ADC_CONFIG */

+/* Description: ADC configuration register. */

+

+/* Bits 17..16 : ADC external reference pin selection. */

+#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /*!< Position of EXTREFSEL field. */

+#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */

+#define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */

+#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /*!< Use analog reference 0 as reference. */

+#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */

+

+/* Bits 15..8 : ADC analog pin selection. */

+#define ADC_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */

+#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */

+#define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */

+#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /*!< Use analog input 0 as analog input. */

+#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */

+#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */

+#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /*!< Use analog input 3 as analog input. */

+#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /*!< Use analog input 4 as analog input. */

+#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /*!< Use analog input 5 as analog input. */

+#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /*!< Use analog input 6 as analog input. */

+#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /*!< Use analog input 7 as analog input. */

+

+/* Bits 6..5 : ADC reference selection. */

+#define ADC_CONFIG_REFSEL_Pos (5UL) /*!< Position of REFSEL field. */

+#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */

+#define ADC_CONFIG_REFSEL_VBG (0x00UL) /*!< Use internal 1.2V bandgap voltage as reference for conversion. */

+#define ADC_CONFIG_REFSEL_External (0x01UL) /*!< Use external source configured by EXTREFSEL as reference for conversion. */

+#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. */

+#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /*!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. */

+

+/* Bits 4..2 : ADC input selection. */

+#define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */

+#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /*!< Bit mask of INPSEL field. */

+#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /*!< Analog input specified by PSEL with no prescaling used as input for the conversion. */

+#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. */

+#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /*!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. */

+#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescaling used as input for the conversion. */

+#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /*!< Supply voltage with 1/3 prescaling used as input for the conversion. */

+

+/* Bits 1..0 : ADC resolution. */

+#define ADC_CONFIG_RES_Pos (0UL) /*!< Position of RES field. */

+#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /*!< Bit mask of RES field. */

+#define ADC_CONFIG_RES_8bit (0x00UL) /*!< 8bit ADC resolution. */

+#define ADC_CONFIG_RES_9bit (0x01UL) /*!< 9bit ADC resolution. */

+#define ADC_CONFIG_RES_10bit (0x02UL) /*!< 10bit ADC resolution. */

+

+/* Register: ADC_RESULT */

+/* Description: Result of ADC conversion. */

+

+/* Bits 9..0 : Result of ADC conversion. */

+#define ADC_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */

+#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */

+

+/* Register: ADC_POWER */

+/* Description: Peripheral power control. */

+

+/* Bit 0 : Peripheral power control. */

+#define ADC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */

+#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */

+#define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */

+#define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */

+

+

+/* Peripheral: AMLI */

+/* Description: AHB Multi-Layer Interface. */

+

+/* Register: AMLI_RAMPRI_CPU0 */

+/* Description: Configurable priority configuration register for CPU0. */

+

+/* Bits 31..28 : Configuration field for RAM block 7. */

+#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */

+#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */

+#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 27..24 : Configuration field for RAM block 6. */

+#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */

+#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */

+#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 23..20 : Configuration field for RAM block 5. */

+#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */

+#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */

+#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 19..16 : Configuration field for RAM block 4. */

+#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */

+#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */

+#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 15..12 : Configuration field for RAM block 3. */

+#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */

+#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */

+#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 11..8 : Configuration field for RAM block 2. */

+#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */

+#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */

+#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 7..4 : Configuration field for RAM block 1. */

+#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */

+#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */

+#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 3..0 : Configuration field for RAM block 0. */

+#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */

+#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */

+#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Register: AMLI_RAMPRI_SPIS1 */

+/* Description: Configurable priority configuration register for SPIS1. */

+

+/* Bits 31..28 : Configuration field for RAM block 7. */

+#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */

+#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */

+#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 27..24 : Configuration field for RAM block 6. */

+#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */

+#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */

+#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 23..20 : Configuration field for RAM block 5. */

+#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */

+#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */

+#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 19..16 : Configuration field for RAM block 4. */

+#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */

+#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */

+#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 15..12 : Configuration field for RAM block 3. */

+#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */

+#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */

+#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 11..8 : Configuration field for RAM block 2. */

+#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */

+#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */

+#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 7..4 : Configuration field for RAM block 1. */

+#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */

+#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */

+#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 3..0 : Configuration field for RAM block 0. */

+#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */

+#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */

+#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Register: AMLI_RAMPRI_RADIO */

+/* Description: Configurable priority configuration register for RADIO. */

+

+/* Bits 31..28 : Configuration field for RAM block 7. */

+#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */

+#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */

+#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 27..24 : Configuration field for RAM block 6. */

+#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */

+#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */

+#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 23..20 : Configuration field for RAM block 5. */

+#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */

+#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */

+#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 19..16 : Configuration field for RAM block 4. */

+#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */

+#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */

+#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 15..12 : Configuration field for RAM block 3. */

+#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */

+#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */

+#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 11..8 : Configuration field for RAM block 2. */

+#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */

+#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */

+#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 7..4 : Configuration field for RAM block 1. */

+#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */

+#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */

+#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 3..0 : Configuration field for RAM block 0. */

+#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */

+#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */

+#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Register: AMLI_RAMPRI_ECB */

+/* Description: Configurable priority configuration register for ECB. */

+

+/* Bits 31..28 : Configuration field for RAM block 7. */

+#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */

+#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */

+#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 27..24 : Configuration field for RAM block 6. */

+#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */

+#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */

+#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 23..20 : Configuration field for RAM block 5. */

+#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */

+#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */

+#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 19..16 : Configuration field for RAM block 4. */

+#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */

+#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */

+#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 15..12 : Configuration field for RAM block 3. */

+#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */

+#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */

+#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 11..8 : Configuration field for RAM block 2. */

+#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */

+#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */

+#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 7..4 : Configuration field for RAM block 1. */

+#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */

+#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */

+#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 3..0 : Configuration field for RAM block 0. */

+#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */

+#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */

+#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Register: AMLI_RAMPRI_CCM */

+/* Description: Configurable priority configuration register for CCM. */

+

+/* Bits 31..28 : Configuration field for RAM block 7. */

+#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */

+#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */

+#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 27..24 : Configuration field for RAM block 6. */

+#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */

+#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */

+#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 23..20 : Configuration field for RAM block 5. */

+#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */

+#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */

+#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 19..16 : Configuration field for RAM block 4. */

+#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */

+#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */

+#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 15..12 : Configuration field for RAM block 3. */

+#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */

+#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */

+#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 11..8 : Configuration field for RAM block 2. */

+#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */

+#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */

+#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 7..4 : Configuration field for RAM block 1. */

+#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */

+#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */

+#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 3..0 : Configuration field for RAM block 0. */

+#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */

+#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */

+#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Register: AMLI_RAMPRI_AAR */

+/* Description: Configurable priority configuration register for AAR. */

+

+/* Bits 31..28 : Configuration field for RAM block 7. */

+#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */

+#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */

+#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 27..24 : Configuration field for RAM block 6. */

+#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */

+#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */

+#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 23..20 : Configuration field for RAM block 5. */

+#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */

+#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */

+#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 19..16 : Configuration field for RAM block 4. */

+#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */

+#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */

+#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 15..12 : Configuration field for RAM block 3. */

+#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */

+#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */

+#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 11..8 : Configuration field for RAM block 2. */

+#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */

+#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */

+#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 7..4 : Configuration field for RAM block 1. */

+#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */

+#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */

+#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /*!< Priority 14. */

+

+/* Bits 3..0 : Configuration field for RAM block 0. */

+#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */

+#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */

+#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /*!< Priority 0. */

+#define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /*!< Priority 2. */

+#define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /*!< Priority 4. */

+#define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /*!< Priority 6. */

+#define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /*!< Priority 8. */

+#define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /*!< Priority 10. */

+#define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /*!< Priority 12. */

+#define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /*!< Priority 14. */

+

+

+/* Peripheral: CCM */

+/* Description: AES CCM Mode Encryption. */

+

+/* Register: CCM_SHORTS */

+/* Description: Shortcuts for the CCM. */

+

+/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */

+#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */

+#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */

+#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */

+#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Register: CCM_INTENSET */

+/* Description: Interrupt enable set register. */

+

+/* Bit 2 : Enable interrupt on ERROR event. */

+#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */

+#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */

+#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */

+#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */

+#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 1 : Enable interrupt on ENDCRYPT event. */

+#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */

+#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */

+#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */

+#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */

+#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 0 : Enable interrupt on ENDKSGEN event. */

+#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */

+#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */

+#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */

+#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */

+#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Register: CCM_INTENCLR */

+/* Description: Interrupt enable clear register. */

+

+/* Bit 2 : Disable interrupt on ERROR event. */

+#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */

+#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */

+#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */

+#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */

+#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 1 : Disable interrupt on ENDCRYPT event. */

+#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */

+#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */

+#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */

+#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */

+#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 0 : Disable interrupt on ENDKSGEN event. */

+#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */

+#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */

+#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */

+#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */

+#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Register: CCM_MICSTATUS */

+/* Description: CCM RX MIC check result. */

+

+/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */

+#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */

+#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */

+#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed. */

+#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed. */

+

+/* Register: CCM_ENABLE */

+/* Description: CCM enable. */

+

+/* Bits 1..0 : CCM enable. */

+#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */

+#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */

+#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */

+#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */

+

+/* Register: CCM_MODE */

+/* Description: Operation mode. */

+

+/* Bit 0 : CCM mode operation. */

+#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */

+#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */

+#define CCM_MODE_MODE_Encryption (0UL) /*!< CCM mode TX */

+#define CCM_MODE_MODE_Decryption (1UL) /*!< CCM mode TX */

+

+/* Register: CCM_POWER */

+/* Description: Peripheral power control. */

+

+/* Bit 0 : Peripheral power control. */

+#define CCM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */

+#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */

+#define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */

+#define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */

+

+

+/* Peripheral: CLOCK */

+/* Description: Clock control. */

+

+/* Register: CLOCK_INTENSET */

+/* Description: Interrupt enable set register. */

+

+/* Bit 4 : Enable interrupt on CTTO event. */

+#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */

+#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */

+#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */

+#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */

+#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 3 : Enable interrupt on DONE event. */

+#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */

+#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */

+#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */

+#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */

+#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */

+#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */

+#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */

+#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */

+#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */

+#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */

+#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */

+#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */

+#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */

+#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */

+#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Register: CLOCK_INTENCLR */

+/* Description: Interrupt enable clear register. */

+

+/* Bit 4 : Disable interrupt on CTTO event. */

+#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */

+#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */

+#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */

+#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */

+#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 3 : Disable interrupt on DONE event. */

+#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */

+#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */

+#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */

+#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */

+#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */

+#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */

+#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */

+#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */

+#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */

+#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */

+#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */

+#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */

+#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */

+#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */

+#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Register: CLOCK_HFCLKRUN */

+/* Description: Task HFCLKSTART trigger status. */

+

+/* Bit 0 : Task HFCLKSTART trigger status. */

+#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */

+#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */

+#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task HFCLKSTART has not been triggered. */

+#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task HFCLKSTART has been triggered. */

+

+/* Register: CLOCK_HFCLKSTAT */

+/* Description: High frequency clock status. */

+

+/* Bit 16 : State for the HFCLK. */

+#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */

+#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */

+#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK clock not running. */

+#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK clock running. */

+

+/* Bit 0 : Active clock source for the HF clock. */

+#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */

+#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */

+#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */

+#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */

+

+/* Register: CLOCK_LFCLKRUN */

+/* Description: Task LFCLKSTART triggered status. */

+

+/* Bit 0 : Task LFCLKSTART triggered status. */

+#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */

+#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */

+#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task LFCLKSTART has not been triggered. */

+#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task LFCLKSTART has been triggered. */

+

+/* Register: CLOCK_LFCLKSTAT */

+/* Description: Low frequency clock status. */

+

+/* Bit 16 : State for the LF clock. */

+#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */

+#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */

+#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK clock not running. */

+#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK clock running. */

+

+/* Bits 1..0 : Active clock source for the LF clock. */

+#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */

+#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */

+#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. */

+#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */

+#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */

+

+/* Register: CLOCK_LFCLKSRCCOPY */

+/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */

+

+/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */

+#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */

+#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */

+#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */

+#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */

+#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */

+

+/* Register: CLOCK_LFCLKSRC */

+/* Description: Clock source for the LFCLK clock. */

+

+/* Bits 1..0 : Clock source. */

+#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */

+#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */

+#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */

+#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */

+#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */

+

+/* Register: CLOCK_CTIV */

+/* Description: Calibration timer interval. */

+

+/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */

+#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */

+#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */

+

+/* Register: CLOCK_XTALFREQ */

+/* Description: Crystal frequency. */

+

+/* Bits 7..0 : External Xtal frequency selection. */

+#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */

+#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */

+#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used as source for the HFCLK oscillator. */

+#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */

+

+

+/* Peripheral: ECB */

+/* Description: AES ECB Mode Encryption. */

+

+/* Register: ECB_INTENSET */

+/* Description: Interrupt enable set register. */

+

+/* Bit 1 : Enable interrupt on ERRORECB event. */

+#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */

+#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */

+#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */

+#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */

+#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 0 : Enable interrupt on ENDECB event. */

+#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */

+#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */

+#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */

+#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */

+#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Register: ECB_INTENCLR */

+/* Description: Interrupt enable clear register. */

+

+/* Bit 1 : Disable interrupt on ERRORECB event. */

+#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */

+#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */

+#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */

+#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */

+#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 0 : Disable interrupt on ENDECB event. */

+#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */

+#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */

+#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */

+#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */

+#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Register: ECB_POWER */

+/* Description: Peripheral power control. */

+

+/* Bit 0 : Peripheral power control. */

+#define ECB_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */

+#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /*!< Bit mask of POWER field. */

+#define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */

+#define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */

+

+

+/* Peripheral: FICR */

+/* Description: Factory Information Configuration. */

+

+/* Register: FICR_PPFC */

+/* Description: Pre-programmed factory code present. */

+

+/* Bits 7..0 : Pre-programmed factory code present. */

+#define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */

+#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */

+#define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */

+#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */

+

+/* Register: FICR_CONFIGID */

+/* Description: Configuration identifier. */

+

+/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */

+#define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */

+#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */

+

+/* Bits 15..0 : Hardware Identification Number. */

+#define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */

+#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */

+

+/* Register: FICR_DEVICEADDRTYPE */

+/* Description: Device address type. */

+

+/* Bit 0 : Device address type. */

+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */

+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */

+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address. */

+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address. */

+

+/* Register: FICR_OVERRIDEEN */

+/* Description: Radio calibration override enable. */

+

+/* Bit 3 : Override default values for BLE_1Mbit mode. */

+#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /*!< Position of BLE_1MBIT field. */

+#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /*!< Bit mask of BLE_1MBIT field. */

+#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */

+#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */

+

+/* Bit 0 : Override default values for NRF_1Mbit mode. */

+#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /*!< Position of NRF_1MBIT field. */

+#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /*!< Bit mask of NRF_1MBIT field. */

+#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /*!< Override the default values for NRF_1Mbit mode. */

+#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /*!< Do not override the default values for NRF_1Mbit mode. */

+

+

+/* Peripheral: GPIO */

+/* Description: General purpose input and output. */

+

+/* Register: GPIO_OUT */

+/* Description: Write GPIO port. */

+

+/* Bit 31 : Pin 31. */

+#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */

+#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */

+#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 30 : Pin 30. */

+#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */

+#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */

+#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 29 : Pin 29. */

+#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */

+#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */

+#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 28 : Pin 28. */

+#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */

+#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */

+#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 27 : Pin 27. */

+#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */

+#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */

+#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 26 : Pin 26. */

+#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */

+#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */

+#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 25 : Pin 25. */

+#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */

+#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */

+#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 24 : Pin 24. */

+#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */

+#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */

+#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 23 : Pin 23. */

+#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */

+#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */

+#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 22 : Pin 22. */

+#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */

+#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */

+#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 21 : Pin 21. */

+#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */

+#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */

+#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 20 : Pin 20. */

+#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */

+#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */

+#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 19 : Pin 19. */

+#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */

+#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */

+#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 18 : Pin 18. */

+#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */

+#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */

+#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 17 : Pin 17. */

+#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */

+#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */

+#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 16 : Pin 16. */

+#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */

+#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */

+#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 15 : Pin 15. */

+#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */

+#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */

+#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 14 : Pin 14. */

+#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */

+#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */

+#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 13 : Pin 13. */

+#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */

+#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */

+#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 12 : Pin 12. */

+#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */

+#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */

+#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 11 : Pin 11. */

+#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */

+#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */

+#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 10 : Pin 10. */

+#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */

+#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */

+#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 9 : Pin 9. */

+#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */

+#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */

+#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 8 : Pin 8. */

+#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */

+#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */

+#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 7 : Pin 7. */

+#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */

+#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */

+#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 6 : Pin 6. */

+#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */

+#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */

+#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 5 : Pin 5. */

+#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */

+#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */

+#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 4 : Pin 4. */

+#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */

+#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */

+#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 3 : Pin 3. */

+#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */

+#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */

+#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 2 : Pin 2. */

+#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */

+#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */

+#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 1 : Pin 1. */

+#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */

+#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */

+#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high. */

+

+/* Bit 0 : Pin 0. */

+#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */

+#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */

+#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high. */

+

+/* Register: GPIO_OUTSET */

+/* Description: Set individual bits in GPIO port. */

+

+/* Bit 31 : Pin 31. */

+#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */

+#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */

+#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN31_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 30 : Pin 30. */

+#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */

+#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */

+#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN30_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 29 : Pin 29. */

+#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */

+#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */

+#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN29_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 28 : Pin 28. */

+#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */

+#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */

+#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN28_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 27 : Pin 27. */

+#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */

+#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */

+#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN27_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 26 : Pin 26. */

+#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */

+#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */

+#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN26_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 25 : Pin 25. */

+#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */

+#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */

+#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN25_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 24 : Pin 24. */

+#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */

+#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */

+#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN24_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 23 : Pin 23. */

+#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */

+#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */

+#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN23_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 22 : Pin 22. */

+#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */

+#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */

+#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN22_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 21 : Pin 21. */

+#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */

+#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */

+#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN21_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 20 : Pin 20. */

+#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */

+#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */

+#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN20_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 19 : Pin 19. */

+#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */

+#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */

+#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN19_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 18 : Pin 18. */

+#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */

+#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */

+#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN18_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 17 : Pin 17. */

+#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */

+#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */

+#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN17_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 16 : Pin 16. */

+#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */

+#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */

+#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN16_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 15 : Pin 15. */

+#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */

+#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */

+#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN15_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 14 : Pin 14. */

+#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */

+#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */

+#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN14_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 13 : Pin 13. */

+#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */

+#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */

+#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN13_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 12 : Pin 12. */

+#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */

+#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */

+#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN12_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 11 : Pin 11. */

+#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */

+#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */

+#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN11_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 10 : Pin 10. */

+#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */

+#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */

+#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN10_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 9 : Pin 9. */

+#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */

+#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */

+#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN9_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 8 : Pin 8. */

+#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */

+#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */

+#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN8_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 7 : Pin 7. */

+#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */

+#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */

+#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN7_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 6 : Pin 6. */

+#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */

+#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */

+#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN6_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 5 : Pin 5. */

+#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */

+#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */

+#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN5_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 4 : Pin 4. */

+#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */

+#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */

+#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN4_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 3 : Pin 3. */

+#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */

+#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */

+#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN3_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 2 : Pin 2. */

+#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */

+#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */

+#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN2_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 1 : Pin 1. */

+#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */

+#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */

+#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN1_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Set pin driver high. */

+

+/* Bit 0 : Pin 0. */

+#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */

+#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */

+#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTSET_PIN0_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Set pin driver high. */

+

+/* Register: GPIO_OUTCLR */

+/* Description: Clear individual bits in GPIO port. */

+

+/* Bit 31 : Pin 31. */

+#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */

+#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */

+#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 30 : Pin 30. */

+#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */

+#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */

+#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 29 : Pin 29. */

+#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */

+#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */

+#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 28 : Pin 28. */

+#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */

+#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */

+#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 27 : Pin 27. */

+#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */

+#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */

+#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 26 : Pin 26. */

+#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */

+#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */

+#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 25 : Pin 25. */

+#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */

+#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */

+#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 24 : Pin 24. */

+#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */

+#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */

+#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 23 : Pin 23. */

+#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */

+#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */

+#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 22 : Pin 22. */

+#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */

+#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */

+#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 21 : Pin 21. */

+#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */

+#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */

+#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 20 : Pin 20. */

+#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */

+#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */

+#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 19 : Pin 19. */

+#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */

+#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */

+#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 18 : Pin 18. */

+#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */

+#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */

+#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 17 : Pin 17. */

+#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */

+#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */

+#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 16 : Pin 16. */

+#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */

+#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */

+#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 15 : Pin 15. */

+#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */

+#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */

+#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 14 : Pin 14. */

+#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */

+#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */

+#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 13 : Pin 13. */

+#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */

+#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */

+#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 12 : Pin 12. */

+#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */

+#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */

+#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 11 : Pin 11. */

+#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */

+#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */

+#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 10 : Pin 10. */

+#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */

+#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */

+#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 9 : Pin 9. */

+#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */

+#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */

+#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 8 : Pin 8. */

+#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */

+#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */

+#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 7 : Pin 7. */

+#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */

+#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */

+#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 6 : Pin 6. */

+#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */

+#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */

+#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 5 : Pin 5. */

+#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */

+#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */

+#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 4 : Pin 4. */

+#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */

+#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */

+#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 3 : Pin 3. */

+#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */

+#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */

+#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 2 : Pin 2. */

+#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */

+#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */

+#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 1 : Pin 1. */

+#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */

+#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */

+#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Set pin driver low. */

+

+/* Bit 0 : Pin 0. */

+#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */

+#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */

+#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Pin driver is low. */

+#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Pin driver is high. */

+#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Set pin driver low. */

+

+/* Register: GPIO_IN */

+/* Description: Read GPIO port. */

+

+/* Bit 31 : Pin 31. */

+#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */

+#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */

+#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high. */

+

+/* Bit 30 : Pin 30. */

+#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */

+#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */

+#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high. */

+

+/* Bit 29 : Pin 29. */

+#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */

+#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */

+#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high. */

+

+/* Bit 28 : Pin 28. */

+#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */

+#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */

+#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high. */

+

+/* Bit 27 : Pin 27. */

+#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */

+#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */

+#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high. */

+

+/* Bit 26 : Pin 26. */

+#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */

+#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */

+#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high. */

+

+/* Bit 25 : Pin 25. */

+#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */

+#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */

+#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high. */

+

+/* Bit 24 : Pin 24. */

+#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */

+#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */

+#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high. */

+

+/* Bit 23 : Pin 23. */

+#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */

+#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */

+#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high. */

+

+/* Bit 22 : Pin 22. */

+#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */

+#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */

+#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high. */

+

+/* Bit 21 : Pin 21. */

+#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */

+#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */

+#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high. */

+

+/* Bit 20 : Pin 20. */

+#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */

+#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */

+#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high. */

+

+/* Bit 19 : Pin 19. */

+#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */

+#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */

+#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high. */

+

+/* Bit 18 : Pin 18. */

+#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */

+#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */

+#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high. */

+

+/* Bit 17 : Pin 17. */

+#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */

+#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */

+#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high. */

+

+/* Bit 16 : Pin 16. */

+#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */

+#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */

+#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high. */

+

+/* Bit 15 : Pin 15. */

+#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */

+#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */

+#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high. */

+

+/* Bit 14 : Pin 14. */

+#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */

+#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */

+#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high. */

+

+/* Bit 13 : Pin 13. */

+#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */

+#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */

+#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high. */

+

+/* Bit 12 : Pin 12. */

+#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */

+#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */

+#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high. */

+

+/* Bit 11 : Pin 11. */

+#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */

+#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */

+#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high. */

+

+/* Bit 10 : Pin 10. */

+#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */

+#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */

+#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high. */

+

+/* Bit 9 : Pin 9. */

+#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */

+#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */

+#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high. */

+

+/* Bit 8 : Pin 8. */

+#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */

+#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */

+#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high. */

+

+/* Bit 7 : Pin 7. */

+#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */

+#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */

+#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high. */

+

+/* Bit 6 : Pin 6. */

+#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */

+#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */

+#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high. */

+

+/* Bit 5 : Pin 5. */

+#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */

+#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */

+#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high. */

+

+/* Bit 4 : Pin 4. */

+#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */

+#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */

+#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high. */

+

+/* Bit 3 : Pin 3. */

+#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */

+#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */

+#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high. */

+

+/* Bit 2 : Pin 2. */

+#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */

+#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */

+#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high. */

+

+/* Bit 1 : Pin 1. */

+#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */

+#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */

+#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high. */

+

+/* Bit 0 : Pin 0. */

+#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */

+#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */

+#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low. */

+#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high. */

+

+/* Register: GPIO_DIR */

+/* Description: Direction of GPIO pins. */

+

+/* Bit 31 : Pin 31. */

+#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */

+#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */

+#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 30 : Pin 30. */

+#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */

+#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */

+#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 29 : Pin 29. */

+#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */

+#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */

+#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 28 : Pin 28. */

+#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */

+#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */

+#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 27 : Pin 27. */

+#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */

+#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */

+#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 26 : Pin 26. */

+#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */

+#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */

+#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 25 : Pin 25. */

+#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */

+#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */

+#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 24 : Pin 24. */

+#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */

+#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */

+#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 23 : Pin 23. */

+#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */

+#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */

+#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 22 : Pin 22. */

+#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */

+#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */

+#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 21 : Pin 21. */

+#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */

+#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */

+#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 20 : Pin 20. */

+#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */

+#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */

+#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 19 : Pin 19. */

+#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */

+#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */

+#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 18 : Pin 18. */

+#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */

+#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */

+#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 17 : Pin 17. */

+#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */

+#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */

+#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 16 : Pin 16. */

+#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */

+#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */

+#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 15 : Pin 15. */

+#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */

+#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */

+#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 14 : Pin 14. */

+#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */

+#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */

+#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 13 : Pin 13. */

+#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */

+#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */

+#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 12 : Pin 12. */

+#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */

+#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */

+#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 11 : Pin 11. */

+#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */

+#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */

+#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 10 : Pin 10. */

+#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */

+#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */

+#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 9 : Pin 9. */

+#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */

+#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */

+#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 8 : Pin 8. */

+#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */

+#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */

+#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 7 : Pin 7. */

+#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */

+#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */

+#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 6 : Pin 6. */

+#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */

+#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */

+#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 5 : Pin 5. */

+#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */

+#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */

+#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 4 : Pin 4. */

+#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */

+#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */

+#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 3 : Pin 3. */

+#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */

+#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */

+#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 2 : Pin 2. */

+#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */

+#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */

+#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 1 : Pin 1. */

+#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */

+#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */

+#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output. */

+

+/* Bit 0 : Pin 0. */

+#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */

+#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */

+#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output. */

+

+/* Register: GPIO_DIRSET */

+/* Description: DIR set register. */

+

+/* Bit 31 : Set as output pin 31. */

+#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */

+#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */

+#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 30 : Set as output pin 30. */

+#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */

+#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */

+#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 29 : Set as output pin 29. */

+#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */

+#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */

+#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 28 : Set as output pin 28. */

+#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */

+#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */

+#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 27 : Set as output pin 27. */

+#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */

+#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */

+#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 26 : Set as output pin 26. */

+#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */

+#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */

+#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 25 : Set as output pin 25. */

+#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */

+#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */

+#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 24 : Set as output pin 24. */

+#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */

+#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */

+#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 23 : Set as output pin 23. */

+#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */

+#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */

+#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 22 : Set as output pin 22. */

+#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */

+#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */

+#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 21 : Set as output pin 21. */

+#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */

+#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */

+#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 20 : Set as output pin 20. */

+#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */

+#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */

+#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 19 : Set as output pin 19. */

+#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */

+#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */

+#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 18 : Set as output pin 18. */

+#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */

+#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */

+#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 17 : Set as output pin 17. */

+#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */

+#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */

+#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 16 : Set as output pin 16. */

+#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */

+#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */

+#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 15 : Set as output pin 15. */

+#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */

+#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */

+#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 14 : Set as output pin 14. */

+#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */

+#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */

+#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 13 : Set as output pin 13. */

+#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */

+#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */

+#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 12 : Set as output pin 12. */

+#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */

+#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */

+#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 11 : Set as output pin 11. */

+#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */

+#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */

+#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 10 : Set as output pin 10. */

+#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */

+#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */

+#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 9 : Set as output pin 9. */

+#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */

+#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */

+#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 8 : Set as output pin 8. */

+#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */

+#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */

+#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 7 : Set as output pin 7. */

+#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */

+#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */

+#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 6 : Set as output pin 6. */

+#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */

+#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */

+#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 5 : Set as output pin 5. */

+#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */

+#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */

+#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 4 : Set as output pin 4. */

+#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */

+#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */

+#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 3 : Set as output pin 3. */

+#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */

+#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */

+#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 2 : Set as output pin 2. */

+#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */

+#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */

+#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 1 : Set as output pin 1. */

+#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */

+#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */

+#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Set pin as output. */

+

+/* Bit 0 : Set as output pin 0. */

+#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */

+#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */

+#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Set pin as output. */

+

+/* Register: GPIO_DIRCLR */

+/* Description: DIR clear register. */

+

+/* Bit 31 : Set as input pin 31. */

+#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */

+#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */

+#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 30 : Set as input pin 30. */

+#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */

+#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */

+#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 29 : Set as input pin 29. */

+#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */

+#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */

+#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 28 : Set as input pin 28. */

+#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */

+#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */

+#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 27 : Set as input pin 27. */

+#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */

+#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */

+#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 26 : Set as input pin 26. */

+#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */

+#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */

+#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 25 : Set as input pin 25. */

+#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */

+#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */

+#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 24 : Set as input pin 24. */

+#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */

+#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */

+#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 23 : Set as input pin 23. */

+#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */

+#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */

+#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 22 : Set as input pin 22. */

+#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */

+#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */

+#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 21 : Set as input pin 21. */

+#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */

+#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */

+#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 20 : Set as input pin 20. */

+#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */

+#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */

+#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 19 : Set as input pin 19. */

+#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */

+#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */

+#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 18 : Set as input pin 18. */

+#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */

+#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */

+#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 17 : Set as input pin 17. */

+#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */

+#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */

+#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 16 : Set as input pin 16. */

+#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */

+#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */

+#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 15 : Set as input pin 15. */

+#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */

+#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */

+#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 14 : Set as input pin 14. */

+#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */

+#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */

+#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 13 : Set as input pin 13. */

+#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */

+#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */

+#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 12 : Set as input pin 12. */

+#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */

+#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */

+#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 11 : Set as input pin 11. */

+#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */

+#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */

+#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 10 : Set as input pin 10. */

+#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */

+#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */

+#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 9 : Set as input pin 9. */

+#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */

+#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */

+#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 8 : Set as input pin 8. */

+#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */

+#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */

+#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 7 : Set as input pin 7. */

+#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */

+#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */

+#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 6 : Set as input pin 6. */

+#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */

+#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */

+#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 5 : Set as input pin 5. */

+#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */

+#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */

+#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 4 : Set as input pin 4. */

+#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */

+#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */

+#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 3 : Set as input pin 3. */

+#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */

+#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */

+#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 2 : Set as input pin 2. */

+#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */

+#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */

+#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 1 : Set as input pin 1. */

+#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */

+#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */

+#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Set pin as input. */

+

+/* Bit 0 : Set as input pin 0. */

+#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */

+#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */

+#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Pin set as input. */

+#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Pin set as output. */

+#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Set pin as input. */

+

+/* Register: GPIO_PIN_CNF */

+/* Description: Configuration of GPIO pins. */

+

+/* Bits 17..16 : Pin sensing mechanism. */

+#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */

+#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */

+#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */

+#define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */

+#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */

+

+/* Bits 10..8 : Drive configuration. */

+#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */

+#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */

+#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /*!< Standard '0', Standard '1'. */

+#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /*!< High '0', Standard '1'. */

+#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /*!< Standard '0', High '1'. */

+#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /*!< High '0', High '1'. */

+#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /*!< Disconnected '0', Standard '1'. */

+#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /*!< Disconnected '0', High '1'. */

+#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /*!< Standard '0', Disconnected '1'. */

+#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /*!< High '0', Disconnected '1'. */

+

+/* Bits 3..2 : Pull-up or -down configuration. */

+#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */

+#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */

+#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /*!< No pull. */

+#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */

+#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */

+

+/* Bit 1 : Connect or disconnect input path. */

+#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */

+#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */

+#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input pin. */

+#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input pin. */

+

+/* Bit 0 : Pin direction. */

+#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */

+#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */

+#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin. */

+#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin. */

+

+

+/* Peripheral: GPIOTE */

+/* Description: GPIO tasks and events. */

+

+/* Register: GPIOTE_INTENSET */

+/* Description: Interrupt enable set register. */

+

+/* Bit 31 : Enable interrupt on PORT event. */

+#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */

+#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */

+#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */

+#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */

+#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 3 : Enable interrupt on IN[3] event. */

+#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */

+#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */

+#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */

+#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */

+#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 2 : Enable interrupt on IN[2] event. */

+#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */

+#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */

+#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */

+#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */

+#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 1 : Enable interrupt on IN[1] event. */

+#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */

+#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */

+#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */

+#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */

+#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 0 : Enable interrupt on IN[0] event. */

+#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */

+#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */

+#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */

+#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */

+#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Register: GPIOTE_INTENCLR */

+/* Description: Interrupt enable clear register. */

+

+/* Bit 31 : Disable interrupt on PORT event. */

+#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */

+#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */

+#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */

+#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */

+#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 3 : Disable interrupt on IN[3] event. */

+#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */

+#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */

+#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */

+#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */

+#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 2 : Disable interrupt on IN[2] event. */

+#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */

+#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */

+#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */

+#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */

+#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 1 : Disable interrupt on IN[1] event. */

+#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */

+#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */

+#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */

+#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */

+#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 0 : Disable interrupt on IN[0] event. */

+#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */

+#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */

+#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */

+#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */

+#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Register: GPIOTE_CONFIG */

+/* Description: Channel configuration registers. */

+

+/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */

+#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */

+#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */

+#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Initial low output when in task mode. */

+#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Initial high output when in task mode. */

+

+/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */

+#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */

+#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */

+#define GPIOTE_CONFIG_POLARITY_None (0x00UL) /*!< No task or event. */

+#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */

+#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */

+#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */

+

+/* Bits 12..8 : Pin select. */

+#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */

+#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */

+

+/* Bits 1..0 : Mode */

+#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */

+#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */

+#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */

+#define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */

+#define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */

+

+/* Register: GPIOTE_POWER */

+/* Description: Peripheral power control. */

+

+/* Bit 0 : Peripheral power control. */

+#define GPIOTE_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */

+#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /*!< Bit mask of POWER field. */

+#define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */

+#define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */

+

+

+/* Peripheral: LPCOMP */

+/* Description: Low power comparator. */

+

+/* Register: LPCOMP_SHORTS */

+/* Description: Shortcuts for the LPCOMP. */

+

+/* Bit 4 : Shortcut between CROSS event and STOP task. */

+#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */

+#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */

+#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */

+#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Bit 3 : Shortcut between UP event and STOP task. */

+#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */

+#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */

+#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */

+#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Bit 2 : Shortcut between DOWN event and STOP task. */

+#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */

+#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */

+#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */

+#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Bit 1 : Shortcut between RADY event and STOP task. */

+#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */

+#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */

+#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */

+#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Bit 0 : Shortcut between READY event and SAMPLE task. */

+#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */

+#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */

+#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */

+#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Register: LPCOMP_INTENSET */

+/* Description: Interrupt enable set register. */

+

+/* Bit 3 : Enable interrupt on CROSS event. */

+#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */

+#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */

+#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */

+#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */

+#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 2 : Enable interrupt on UP event. */

+#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */

+#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */

+#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */

+#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */

+#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 1 : Enable interrupt on DOWN event. */

+#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */

+#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */

+#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */

+#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */

+#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 0 : Enable interrupt on READY event. */

+#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */

+#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */

+#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */

+#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */

+#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Register: LPCOMP_INTENCLR */

+/* Description: Interrupt enable clear register. */

+

+/* Bit 3 : Disable interrupt on CROSS event. */

+#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */

+#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */

+#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */

+#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */

+#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 2 : Disable interrupt on UP event. */

+#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */

+#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */

+#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */

+#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */

+#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 1 : Disable interrupt on DOWN event. */

+#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */

+#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */

+#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */

+#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */

+#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 0 : Disable interrupt on READY event. */

+#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */

+#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */

+#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */

+#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */

+#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Register: LPCOMP_RESULT */

+/* Description: Result of last compare. */

+

+/* Bit 0 : Result of last compare. Decision point SAMPLE task. */

+#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */

+#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */

+#define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */

+#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */

+

+/* Register: LPCOMP_ENABLE */

+/* Description: Enable the LPCOMP. */

+

+/* Bits 1..0 : Enable or disable LPCOMP. */

+#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */

+#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */

+#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */

+#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */

+

+/* Register: LPCOMP_PSEL */

+/* Description: Input pin select. */

+

+/* Bits 2..0 : Analog input pin select. */

+#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */

+#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */

+#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */

+#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */

+#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */

+#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */

+#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */

+#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */

+#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */

+#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */

+

+/* Register: LPCOMP_REFSEL */

+/* Description: Reference select. */

+

+/* Bits 2..0 : Reference select. */

+#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */

+#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */

+#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use supply with a 1/8 prescaler as reference. */

+#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use supply with a 2/8 prescaler as reference. */

+#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use supply with a 3/8 prescaler as reference. */

+#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use supply with a 4/8 prescaler as reference. */

+#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use supply with a 5/8 prescaler as reference. */

+#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use supply with a 6/8 prescaler as reference. */

+#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use supply with a 7/8 prescaler as reference. */

+#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */

+

+/* Register: LPCOMP_EXTREFSEL */

+/* Description: External reference select. */

+

+/* Bit 0 : External analog reference pin selection. */

+#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */

+#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */

+#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */

+#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */

+

+/* Register: LPCOMP_ANADETECT */

+/* Description: Analog detect configuration. */

+

+/* Bits 1..0 : Analog detect configuration. */

+#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */

+#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */

+#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and downwards crossing. */

+#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */

+#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */

+

+/* Register: LPCOMP_POWER */

+/* Description: Peripheral power control. */

+

+/* Bit 0 : Peripheral power control. */

+#define LPCOMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */

+#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */

+#define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */

+#define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */

+

+

+/* Peripheral: MPU */

+/* Description: Memory Protection Unit. */

+

+/* Register: MPU_PERR0 */

+/* Description: Configuration of peripherals in mpu regions. */

+

+/* Bit 31 : PPI region configuration. */

+#define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */

+#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */

+#define MPU_PERR0_PPI_InRegion1 (0UL) /*!< Peripheral configured in region 1. */

+#define MPU_PERR0_PPI_InRegion0 (1UL) /*!< Peripheral configured in region 0. */

+

+/* Bit 30 : NVMC region configuration. */

+#define MPU_PERR0_NVMC_Pos (30UL) /*!< Position of NVMC field. */

+#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /*!< Bit mask of NVMC field. */

+#define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */

+#define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */

+

+/* Bit 19 : LPCOMP region configuration. */

+#define MPU_PERR0_LPCOMP_Pos (19UL) /*!< Position of LPCOMP field. */

+#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */

+#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */

+#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */

+

+/* Bit 18 : QDEC region configuration. */

+#define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */

+#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /*!< Bit mask of QDEC field. */

+#define MPU_PERR0_QDEC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */

+#define MPU_PERR0_QDEC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */

+

+/* Bit 17 : RTC1 region configuration. */

+#define MPU_PERR0_RTC1_Pos (17UL) /*!< Position of RTC1 field. */

+#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /*!< Bit mask of RTC1 field. */

+#define MPU_PERR0_RTC1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */

+#define MPU_PERR0_RTC1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */

+

+/* Bit 16 : WDT region configuration. */

+#define MPU_PERR0_WDT_Pos (16UL) /*!< Position of WDT field. */

+#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /*!< Bit mask of WDT field. */

+#define MPU_PERR0_WDT_InRegion1 (0UL) /*!< Peripheral configured in region 1. */

+#define MPU_PERR0_WDT_InRegion0 (1UL) /*!< Peripheral configured in region 0. */

+

+/* Bit 15 : CCM and AAR region configuration. */

+#define MPU_PERR0_CCM_AAR_Pos (15UL) /*!< Position of CCM_AAR field. */

+#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /*!< Bit mask of CCM_AAR field. */

+#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /*!< Peripheral configured in region 1. */

+#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /*!< Peripheral configured in region 0. */

+

+/* Bit 14 : ECB region configuration. */

+#define MPU_PERR0_ECB_Pos (14UL) /*!< Position of ECB field. */

+#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /*!< Bit mask of ECB field. */

+#define MPU_PERR0_ECB_InRegion1 (0UL) /*!< Peripheral configured in region 1. */

+#define MPU_PERR0_ECB_InRegion0 (1UL) /*!< Peripheral configured in region 0. */

+

+/* Bit 13 : RNG region configuration. */

+#define MPU_PERR0_RNG_Pos (13UL) /*!< Position of RNG field. */

+#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /*!< Bit mask of RNG field. */

+#define MPU_PERR0_RNG_InRegion1 (0UL) /*!< Peripheral configured in region 1. */

+#define MPU_PERR0_RNG_InRegion0 (1UL) /*!< Peripheral configured in region 0. */

+

+/* Bit 12 : TEMP region configuration. */

+#define MPU_PERR0_TEMP_Pos (12UL) /*!< Position of TEMP field. */

+#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /*!< Bit mask of TEMP field. */

+#define MPU_PERR0_TEMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */

+#define MPU_PERR0_TEMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */

+

+/* Bit 11 : RTC0 region configuration. */

+#define MPU_PERR0_RTC0_Pos (11UL) /*!< Position of RTC0 field. */

+#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /*!< Bit mask of RTC0 field. */

+#define MPU_PERR0_RTC0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */

+#define MPU_PERR0_RTC0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */

+

+/* Bit 10 : TIMER2 region configuration. */

+#define MPU_PERR0_TIMER2_Pos (10UL) /*!< Position of TIMER2 field. */

+#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /*!< Bit mask of TIMER2 field. */

+#define MPU_PERR0_TIMER2_InRegion1 (0UL) /*!< Peripheral configured in region 1. */

+#define MPU_PERR0_TIMER2_InRegion0 (1UL) /*!< Peripheral configured in region 0. */

+

+/* Bit 9 : TIMER1 region configuration. */

+#define MPU_PERR0_TIMER1_Pos (9UL) /*!< Position of TIMER1 field. */

+#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /*!< Bit mask of TIMER1 field. */

+#define MPU_PERR0_TIMER1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */

+#define MPU_PERR0_TIMER1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */

+

+/* Bit 8 : TIMER0 region configuration. */

+#define MPU_PERR0_TIMER0_Pos (8UL) /*!< Position of TIMER0 field. */

+#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /*!< Bit mask of TIMER0 field. */

+#define MPU_PERR0_TIMER0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */

+#define MPU_PERR0_TIMER0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */

+

+/* Bit 7 : ADC region configuration. */

+#define MPU_PERR0_ADC_Pos (7UL) /*!< Position of ADC field. */

+#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /*!< Bit mask of ADC field. */

+#define MPU_PERR0_ADC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */

+#define MPU_PERR0_ADC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */

+

+/* Bit 6 : GPIOTE region configuration. */

+#define MPU_PERR0_GPIOTE_Pos (6UL) /*!< Position of GPIOTE field. */

+#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /*!< Bit mask of GPIOTE field. */

+#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /*!< Peripheral configured in region 1. */

+#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /*!< Peripheral configured in region 0. */

+

+/* Bit 4 : SPI1 and TWI1 region configuration. */

+#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /*!< Position of SPI1_TWI1 field. */

+#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /*!< Bit mask of SPI1_TWI1 field. */

+#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */

+#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */

+

+/* Bit 3 : SPI0 and TWI0 region configuration. */

+#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /*!< Position of SPI0_TWI0 field. */

+#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /*!< Bit mask of SPI0_TWI0 field. */

+#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */

+#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */

+

+/* Bit 2 : UART0 region configuration. */

+#define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */

+#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /*!< Bit mask of UART0 field. */

+#define MPU_PERR0_UART0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */

+#define MPU_PERR0_UART0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */

+

+/* Bit 1 : RADIO region configuration. */

+#define MPU_PERR0_RADIO_Pos (1UL) /*!< Position of RADIO field. */

+#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /*!< Bit mask of RADIO field. */

+#define MPU_PERR0_RADIO_InRegion1 (0UL) /*!< Peripheral configured in region 1. */

+#define MPU_PERR0_RADIO_InRegion0 (1UL) /*!< Peripheral configured in region 0. */

+

+/* Bit 0 : POWER_CLOCK region configuration. */

+#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /*!< Position of POWER_CLOCK field. */

+#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /*!< Bit mask of POWER_CLOCK field. */

+#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /*!< Peripheral configured in region 1. */

+#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */

+

+/* Register: MPU_PROTENSET0 */

+/* Description: Erase and write protection bit enable set register. */

+

+/* Bit 31 : Protection enable for region 31. */

+#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */

+#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /*!< Bit mask of PROTREG31 field. */

+#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 30 : Protection enable for region 30. */

+#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /*!< Position of PROTREG30 field. */

+#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /*!< Bit mask of PROTREG30 field. */

+#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 29 : Protection enable for region 29. */

+#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /*!< Position of PROTREG29 field. */

+#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /*!< Bit mask of PROTREG29 field. */

+#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 28 : Protection enable for region 28. */

+#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /*!< Position of PROTREG28 field. */

+#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /*!< Bit mask of PROTREG28 field. */

+#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 27 : Protection enable for region 27. */

+#define MPU_PROTENSET0_PROTREG27_Pos (27UL) /*!< Position of PROTREG27 field. */

+#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /*!< Bit mask of PROTREG27 field. */

+#define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 26 : Protection enable for region 26. */

+#define MPU_PROTENSET0_PROTREG26_Pos (26UL) /*!< Position of PROTREG26 field. */

+#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /*!< Bit mask of PROTREG26 field. */

+#define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 25 : Protection enable for region 25. */

+#define MPU_PROTENSET0_PROTREG25_Pos (25UL) /*!< Position of PROTREG25 field. */

+#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /*!< Bit mask of PROTREG25 field. */

+#define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 24 : Protection enable for region 24. */

+#define MPU_PROTENSET0_PROTREG24_Pos (24UL) /*!< Position of PROTREG24 field. */

+#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /*!< Bit mask of PROTREG24 field. */

+#define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 23 : Protection enable for region 23. */

+#define MPU_PROTENSET0_PROTREG23_Pos (23UL) /*!< Position of PROTREG23 field. */

+#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /*!< Bit mask of PROTREG23 field. */

+#define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 22 : Protection enable for region 22. */

+#define MPU_PROTENSET0_PROTREG22_Pos (22UL) /*!< Position of PROTREG22 field. */

+#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /*!< Bit mask of PROTREG22 field. */

+#define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 21 : Protection enable for region 21. */

+#define MPU_PROTENSET0_PROTREG21_Pos (21UL) /*!< Position of PROTREG21 field. */

+#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /*!< Bit mask of PROTREG21 field. */

+#define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 20 : Protection enable for region 20. */

+#define MPU_PROTENSET0_PROTREG20_Pos (20UL) /*!< Position of PROTREG20 field. */

+#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /*!< Bit mask of PROTREG20 field. */

+#define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 19 : Protection enable for region 19. */

+#define MPU_PROTENSET0_PROTREG19_Pos (19UL) /*!< Position of PROTREG19 field. */

+#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /*!< Bit mask of PROTREG19 field. */

+#define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 18 : Protection enable for region 18. */

+#define MPU_PROTENSET0_PROTREG18_Pos (18UL) /*!< Position of PROTREG18 field. */

+#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /*!< Bit mask of PROTREG18 field. */

+#define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 17 : Protection enable for region 17. */

+#define MPU_PROTENSET0_PROTREG17_Pos (17UL) /*!< Position of PROTREG17 field. */

+#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /*!< Bit mask of PROTREG17 field. */

+#define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 16 : Protection enable for region 16. */

+#define MPU_PROTENSET0_PROTREG16_Pos (16UL) /*!< Position of PROTREG16 field. */

+#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /*!< Bit mask of PROTREG16 field. */

+#define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 15 : Protection enable for region 15. */

+#define MPU_PROTENSET0_PROTREG15_Pos (15UL) /*!< Position of PROTREG15 field. */

+#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /*!< Bit mask of PROTREG15 field. */

+#define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 14 : Protection enable for region 14. */

+#define MPU_PROTENSET0_PROTREG14_Pos (14UL) /*!< Position of PROTREG14 field. */

+#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /*!< Bit mask of PROTREG14 field. */

+#define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 13 : Protection enable for region 13. */

+#define MPU_PROTENSET0_PROTREG13_Pos (13UL) /*!< Position of PROTREG13 field. */

+#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /*!< Bit mask of PROTREG13 field. */

+#define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 12 : Protection enable for region 12. */

+#define MPU_PROTENSET0_PROTREG12_Pos (12UL) /*!< Position of PROTREG12 field. */

+#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /*!< Bit mask of PROTREG12 field. */

+#define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 11 : Protection enable for region 11. */

+#define MPU_PROTENSET0_PROTREG11_Pos (11UL) /*!< Position of PROTREG11 field. */

+#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /*!< Bit mask of PROTREG11 field. */

+#define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 10 : Protection enable for region 10. */

+#define MPU_PROTENSET0_PROTREG10_Pos (10UL) /*!< Position of PROTREG10 field. */

+#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /*!< Bit mask of PROTREG10 field. */

+#define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 9 : Protection enable for region 9. */

+#define MPU_PROTENSET0_PROTREG9_Pos (9UL) /*!< Position of PROTREG9 field. */

+#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /*!< Bit mask of PROTREG9 field. */

+#define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 8 : Protection enable for region 8. */

+#define MPU_PROTENSET0_PROTREG8_Pos (8UL) /*!< Position of PROTREG8 field. */

+#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /*!< Bit mask of PROTREG8 field. */

+#define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 7 : Protection enable for region 7. */

+#define MPU_PROTENSET0_PROTREG7_Pos (7UL) /*!< Position of PROTREG7 field. */

+#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /*!< Bit mask of PROTREG7 field. */

+#define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 6 : Protection enable for region 6. */

+#define MPU_PROTENSET0_PROTREG6_Pos (6UL) /*!< Position of PROTREG6 field. */

+#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /*!< Bit mask of PROTREG6 field. */

+#define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 5 : Protection enable for region 5. */

+#define MPU_PROTENSET0_PROTREG5_Pos (5UL) /*!< Position of PROTREG5 field. */

+#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /*!< Bit mask of PROTREG5 field. */

+#define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 4 : Protection enable for region 4. */

+#define MPU_PROTENSET0_PROTREG4_Pos (4UL) /*!< Position of PROTREG4 field. */

+#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /*!< Bit mask of PROTREG4 field. */

+#define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 3 : Protection enable for region 3. */

+#define MPU_PROTENSET0_PROTREG3_Pos (3UL) /*!< Position of PROTREG3 field. */

+#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /*!< Bit mask of PROTREG3 field. */

+#define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 2 : Protection enable for region 2. */

+#define MPU_PROTENSET0_PROTREG2_Pos (2UL) /*!< Position of PROTREG2 field. */

+#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /*!< Bit mask of PROTREG2 field. */

+#define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 1 : Protection enable for region 1. */

+#define MPU_PROTENSET0_PROTREG1_Pos (1UL) /*!< Position of PROTREG1 field. */

+#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /*!< Bit mask of PROTREG1 field. */

+#define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 0 : Protection enable for region 0. */

+#define MPU_PROTENSET0_PROTREG0_Pos (0UL) /*!< Position of PROTREG0 field. */

+#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /*!< Bit mask of PROTREG0 field. */

+#define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */

+

+/* Register: MPU_PROTENSET1 */

+/* Description: Erase and write protection bit enable set register. */

+

+/* Bit 31 : Protection enable for region 63. */

+#define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */

+#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /*!< Bit mask of PROTREG63 field. */

+#define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 30 : Protection enable for region 62. */

+#define MPU_PROTENSET1_PROTREG62_Pos (30UL) /*!< Position of PROTREG62 field. */

+#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /*!< Bit mask of PROTREG62 field. */

+#define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 29 : Protection enable for region 61. */

+#define MPU_PROTENSET1_PROTREG61_Pos (29UL) /*!< Position of PROTREG61 field. */

+#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /*!< Bit mask of PROTREG61 field. */

+#define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 28 : Protection enable for region 60. */

+#define MPU_PROTENSET1_PROTREG60_Pos (28UL) /*!< Position of PROTREG60 field. */

+#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /*!< Bit mask of PROTREG60 field. */

+#define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 27 : Protection enable for region 59. */

+#define MPU_PROTENSET1_PROTREG59_Pos (27UL) /*!< Position of PROTREG59 field. */

+#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /*!< Bit mask of PROTREG59 field. */

+#define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 26 : Protection enable for region 58. */

+#define MPU_PROTENSET1_PROTREG58_Pos (26UL) /*!< Position of PROTREG58 field. */

+#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /*!< Bit mask of PROTREG58 field. */

+#define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 25 : Protection enable for region 57. */

+#define MPU_PROTENSET1_PROTREG57_Pos (25UL) /*!< Position of PROTREG57 field. */

+#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /*!< Bit mask of PROTREG57 field. */

+#define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 24 : Protection enable for region 56. */

+#define MPU_PROTENSET1_PROTREG56_Pos (24UL) /*!< Position of PROTREG56 field. */

+#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /*!< Bit mask of PROTREG56 field. */

+#define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 23 : Protection enable for region 55. */

+#define MPU_PROTENSET1_PROTREG55_Pos (23UL) /*!< Position of PROTREG55 field. */

+#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /*!< Bit mask of PROTREG55 field. */

+#define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 22 : Protection enable for region 54. */

+#define MPU_PROTENSET1_PROTREG54_Pos (22UL) /*!< Position of PROTREG54 field. */

+#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /*!< Bit mask of PROTREG54 field. */

+#define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 21 : Protection enable for region 53. */

+#define MPU_PROTENSET1_PROTREG53_Pos (21UL) /*!< Position of PROTREG53 field. */

+#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /*!< Bit mask of PROTREG53 field. */

+#define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 20 : Protection enable for region 52. */

+#define MPU_PROTENSET1_PROTREG52_Pos (20UL) /*!< Position of PROTREG52 field. */

+#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /*!< Bit mask of PROTREG52 field. */

+#define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 19 : Protection enable for region 51. */

+#define MPU_PROTENSET1_PROTREG51_Pos (19UL) /*!< Position of PROTREG51 field. */

+#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /*!< Bit mask of PROTREG51 field. */

+#define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 18 : Protection enable for region 50. */

+#define MPU_PROTENSET1_PROTREG50_Pos (18UL) /*!< Position of PROTREG50 field. */

+#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /*!< Bit mask of PROTREG50 field. */

+#define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 17 : Protection enable for region 49. */

+#define MPU_PROTENSET1_PROTREG49_Pos (17UL) /*!< Position of PROTREG49 field. */

+#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /*!< Bit mask of PROTREG49 field. */

+#define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 16 : Protection enable for region 48. */

+#define MPU_PROTENSET1_PROTREG48_Pos (16UL) /*!< Position of PROTREG48 field. */

+#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /*!< Bit mask of PROTREG48 field. */

+#define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 15 : Protection enable for region 47. */

+#define MPU_PROTENSET1_PROTREG47_Pos (15UL) /*!< Position of PROTREG47 field. */

+#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /*!< Bit mask of PROTREG47 field. */

+#define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 14 : Protection enable for region 46. */

+#define MPU_PROTENSET1_PROTREG46_Pos (14UL) /*!< Position of PROTREG46 field. */

+#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /*!< Bit mask of PROTREG46 field. */

+#define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 13 : Protection enable for region 45. */

+#define MPU_PROTENSET1_PROTREG45_Pos (13UL) /*!< Position of PROTREG45 field. */

+#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /*!< Bit mask of PROTREG45 field. */

+#define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 12 : Protection enable for region 44. */

+#define MPU_PROTENSET1_PROTREG44_Pos (12UL) /*!< Position of PROTREG44 field. */

+#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /*!< Bit mask of PROTREG44 field. */

+#define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 11 : Protection enable for region 43. */

+#define MPU_PROTENSET1_PROTREG43_Pos (11UL) /*!< Position of PROTREG43 field. */

+#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /*!< Bit mask of PROTREG43 field. */

+#define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 10 : Protection enable for region 42. */

+#define MPU_PROTENSET1_PROTREG42_Pos (10UL) /*!< Position of PROTREG42 field. */

+#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /*!< Bit mask of PROTREG42 field. */

+#define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 9 : Protection enable for region 41. */

+#define MPU_PROTENSET1_PROTREG41_Pos (9UL) /*!< Position of PROTREG41 field. */

+#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /*!< Bit mask of PROTREG41 field. */

+#define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 8 : Protection enable for region 40. */

+#define MPU_PROTENSET1_PROTREG40_Pos (8UL) /*!< Position of PROTREG40 field. */

+#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /*!< Bit mask of PROTREG40 field. */

+#define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 7 : Protection enable for region 39. */

+#define MPU_PROTENSET1_PROTREG39_Pos (7UL) /*!< Position of PROTREG39 field. */

+#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /*!< Bit mask of PROTREG39 field. */

+#define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 6 : Protection enable for region 38. */

+#define MPU_PROTENSET1_PROTREG38_Pos (6UL) /*!< Position of PROTREG38 field. */

+#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /*!< Bit mask of PROTREG38 field. */

+#define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 5 : Protection enable for region 37. */

+#define MPU_PROTENSET1_PROTREG37_Pos (5UL) /*!< Position of PROTREG37 field. */

+#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /*!< Bit mask of PROTREG37 field. */

+#define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 4 : Protection enable for region 36. */

+#define MPU_PROTENSET1_PROTREG36_Pos (4UL) /*!< Position of PROTREG36 field. */

+#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /*!< Bit mask of PROTREG36 field. */

+#define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 3 : Protection enable for region 35. */

+#define MPU_PROTENSET1_PROTREG35_Pos (3UL) /*!< Position of PROTREG35 field. */

+#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /*!< Bit mask of PROTREG35 field. */

+#define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 2 : Protection enable for region 34. */

+#define MPU_PROTENSET1_PROTREG34_Pos (2UL) /*!< Position of PROTREG34 field. */

+#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /*!< Bit mask of PROTREG34 field. */

+#define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 1 : Protection enable for region 33. */

+#define MPU_PROTENSET1_PROTREG33_Pos (1UL) /*!< Position of PROTREG33 field. */

+#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /*!< Bit mask of PROTREG33 field. */

+#define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */

+

+/* Bit 0 : Protection enable for region 32. */

+#define MPU_PROTENSET1_PROTREG32_Pos (0UL) /*!< Position of PROTREG32 field. */

+#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /*!< Bit mask of PROTREG32 field. */

+#define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /*!< Protection disabled. */

+#define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /*!< Protection enabled. */

+#define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */

+

+/* Register: MPU_DISABLEINDEBUG */

+/* Description: Disable erase and write protection mechanism in debug mode. */

+

+/* Bit 0 : Disable protection mechanism in debug mode. */

+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */

+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */

+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */

+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */

+

+/* Register: MPU_PROTBLOCKSIZE */

+/* Description: Erase and write protection block size. */

+

+/* Bits 1..0 : Erase and write protection block size. */

+#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /*!< Position of PROTBLOCKSIZE field. */

+#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /*!< Bit mask of PROTBLOCKSIZE field. */

+#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /*!< Erase and write protection block size is 4k. */

+

+

+/* Peripheral: NVMC */

+/* Description: Non Volatile Memory Controller. */

+

+/* Register: NVMC_READY */

+/* Description: Ready flag. */

+

+/* Bit 0 : NVMC ready. */

+#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */

+#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */

+#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation). */

+#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready. */

+

+/* Register: NVMC_CONFIG */

+/* Description: Configuration register. */

+

+/* Bits 1..0 : Program write enable. */

+#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */

+#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */

+#define NVMC_CONFIG_WEN_Ren (0x00UL) /*!< Read only access. */

+#define NVMC_CONFIG_WEN_Wen (0x01UL) /*!< Write enabled. */

+#define NVMC_CONFIG_WEN_Een (0x02UL) /*!< Erase enabled. */

+

+/* Register: NVMC_ERASEALL */

+/* Description: Register for erasing all non-volatile user memory. */

+

+/* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */

+#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */

+#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */

+#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation. */

+#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase. */

+

+/* Register: NVMC_ERASEUICR */

+/* Description: Register for start erasing User Information Congfiguration Registers. */

+

+/* Bit 0 : It can only be used when all contents of code region 1 are erased. */

+#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */

+#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */

+#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation. */

+#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start UICR erase. */

+

+

+/* Peripheral: POWER */

+/* Description: Power Control. */

+

+/* Register: POWER_INTENSET */

+/* Description: Interrupt enable set register. */

+

+/* Bit 2 : Enable interrupt on POFWARN event. */

+#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */

+#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */

+#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */

+#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */

+#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Register: POWER_INTENCLR */

+/* Description: Interrupt enable clear register. */

+

+/* Bit 2 : Disable interrupt on POFWARN event. */

+#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */

+#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */

+#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */

+#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */

+#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Register: POWER_RESETREAS */

+/* Description: Reset reason. */

+

+/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */

+#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */

+#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */

+#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Reset not detected. */

+#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Reset detected. */

+

+/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */

+#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */

+#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */

+#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Reset not detected. */

+#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Reset detected. */

+

+/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */

+#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */

+#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */

+#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Reset not detected. */

+#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Reset detected. */

+

+/* Bit 3 : Reset from CPU lock-up detected. */

+#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */

+#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */

+#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Reset not detected. */

+#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Reset detected. */

+

+/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */

+#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */

+#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */

+#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Reset not detected. */

+#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Reset detected. */

+

+/* Bit 1 : Reset from watchdog detected. */

+#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */

+#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */

+#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Reset not detected. */

+#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Reset detected. */

+

+/* Bit 0 : Reset from pin-reset detected. */

+#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */

+#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */

+#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Reset not detected. */

+#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Reset detected. */

+

+/* Register: POWER_RAMSTATUS */

+/* Description: Ram status register. */

+

+/* Bit 3 : RAM block 3 status. */

+#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */

+#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */

+#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< RAM block 3 is off or powering up. */

+#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< RAM block 3 is on. */

+

+/* Bit 2 : RAM block 2 status. */

+#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */

+#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */

+#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< RAM block 2 is off or powering up. */

+#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< RAM block 2 is on. */

+

+/* Bit 1 : RAM block 1 status. */

+#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */

+#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */

+#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< RAM block 1 is off or powering up. */

+#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< RAM block 1 is on. */

+

+/* Bit 0 : RAM block 0 status. */

+#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */

+#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */

+#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< RAM block 0 is off or powering up. */

+#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< RAM block 0 is on. */

+

+/* Register: POWER_SYSTEMOFF */

+/* Description: System off register. */

+

+/* Bit 0 : Enter system off mode. */

+#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */

+#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */

+#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enter system off mode. */

+

+/* Register: POWER_POFCON */

+/* Description: Power failure configuration. */

+

+/* Bits 2..1 : Set threshold level. */

+#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */

+#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */

+#define POWER_POFCON_THRESHOLD_V21 (0x00UL) /*!< Set threshold to 2.1Volts. */

+#define POWER_POFCON_THRESHOLD_V23 (0x01UL) /*!< Set threshold to 2.3Volts. */

+#define POWER_POFCON_THRESHOLD_V25 (0x02UL) /*!< Set threshold to 2.5Volts. */

+#define POWER_POFCON_THRESHOLD_V27 (0x03UL) /*!< Set threshold to 2.7Volts. */

+

+/* Bit 0 : Power failure comparator enable. */

+#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */

+#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */

+#define POWER_POFCON_POF_Disabled (0UL) /*!< Disabled. */

+#define POWER_POFCON_POF_Enabled (1UL) /*!< Enabled. */

+

+/* Register: POWER_GPREGRET */

+/* Description: General purpose retention register. This register is a retained register. */

+

+/* Bits 7..0 : General purpose retention register. */

+#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */

+#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */

+

+/* Register: POWER_RAMON */

+/* Description: Ram on/off. */

+

+/* Bit 17 : RAM block 1 behaviour in OFF mode. */

+#define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */

+#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */

+#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in OFF mode. */

+#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< RAM block 1 ON in OFF mode. */

+

+/* Bit 16 : RAM block 0 behaviour in OFF mode. */

+#define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */

+#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */

+#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */

+#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */

+

+/* Bit 1 : RAM block 1 behaviour in ON mode. */

+#define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */

+#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */

+#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in ON mode. */

+#define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< RAM block 1 ON in ON mode. */

+

+/* Bit 0 : RAM block 0 behaviour in ON mode. */

+#define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */

+#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */

+#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in ON mode. */

+#define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< RAM block 0 ON in ON mode. */

+

+/* Register: POWER_RESET */

+/* Description: Pin reset functionality configuration register. This register is a retained register. */

+

+/* Bit 0 : Enable or disable pin reset in debug interface mode. */

+#define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */

+#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */

+#define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */

+#define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */

+

+/* Register: POWER_RAMONB */

+/* Description: Ram on/off. */

+

+/* Bit 17 : RAM block 3 behaviour in OFF mode. */

+#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */

+#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */

+#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */

+#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */

+

+/* Bit 16 : RAM block 2 behaviour in OFF mode. */

+#define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */

+#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */

+#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */

+#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */

+

+/* Bit 1 : RAM block 3 behaviour in ON mode. */

+#define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */

+#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */

+#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< RAM block 33 OFF in ON mode. */

+#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */

+

+/* Bit 0 : RAM block 2 behaviour in ON mode. */

+#define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */

+#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */

+#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */

+#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */

+

+/* Register: POWER_DCDCEN */

+/* Description: DCDC converter enable configuration register. */

+

+/* Bit 0 : Enable DCDC converter. */

+#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */

+#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */

+#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */

+#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */

+

+/* Register: POWER_DCDCFORCE */

+/* Description: DCDC power-up force register. */

+

+/* Bit 1 : DCDC power-up force on. */

+#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /*!< Position of FORCEON field. */

+#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /*!< Bit mask of FORCEON field. */

+#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /*!< No force. */

+#define POWER_DCDCFORCE_FORCEON_Force (1UL) /*!< Force. */

+

+/* Bit 0 : DCDC power-up force off. */

+#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */

+#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */

+#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /*!< No force. */

+#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /*!< Force. */

+

+

+/* Peripheral: PPI */

+/* Description: PPI controller. */

+

+/* Register: PPI_CHEN */

+/* Description: Channel enable. */

+

+/* Bit 31 : Enable PPI channel 31. */

+#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */

+#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */

+#define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */

+

+/* Bit 30 : Enable PPI channel 30. */

+#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */

+#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */

+#define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */

+

+/* Bit 29 : Enable PPI channel 29. */

+#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */

+#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */

+#define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */

+

+/* Bit 28 : Enable PPI channel 28. */

+#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */

+#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */

+#define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */

+

+/* Bit 27 : Enable PPI channel 27. */

+#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */

+#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */

+#define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */

+

+/* Bit 26 : Enable PPI channel 26. */

+#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */

+#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */

+#define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */

+

+/* Bit 25 : Enable PPI channel 25. */

+#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */

+#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */

+#define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */

+

+/* Bit 24 : Enable PPI channel 24. */

+#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */

+#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */

+#define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */

+

+/* Bit 23 : Enable PPI channel 23. */

+#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */

+#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */

+#define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */

+

+/* Bit 22 : Enable PPI channel 22. */

+#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */

+#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */

+#define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */

+

+/* Bit 21 : Enable PPI channel 21. */

+#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */

+#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */

+#define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */

+

+/* Bit 20 : Enable PPI channel 20. */

+#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */

+#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */

+#define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */

+

+/* Bit 15 : Enable PPI channel 15. */

+#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */

+#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */

+#define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */

+

+/* Bit 14 : Enable PPI channel 14. */

+#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */

+#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */

+#define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */

+

+/* Bit 13 : Enable PPI channel 13. */

+#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */

+#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */

+#define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */

+

+/* Bit 12 : Enable PPI channel 12. */

+#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */

+#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */

+#define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */

+

+/* Bit 11 : Enable PPI channel 11. */

+#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */

+#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */

+#define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */

+

+/* Bit 10 : Enable PPI channel 10. */

+#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */

+#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */

+#define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */

+

+/* Bit 9 : Enable PPI channel 9. */

+#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */

+#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */

+#define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */

+

+/* Bit 8 : Enable PPI channel 8. */

+#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */

+#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */

+#define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */

+

+/* Bit 7 : Enable PPI channel 7. */

+#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */

+#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */

+#define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */

+

+/* Bit 6 : Enable PPI channel 6. */

+#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */

+#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */

+#define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */

+

+/* Bit 5 : Enable PPI channel 5. */

+#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */

+#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */

+#define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */

+

+/* Bit 4 : Enable PPI channel 4. */

+#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */

+#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */

+#define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */

+

+/* Bit 3 : Enable PPI channel 3. */

+#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */

+#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */

+#define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */

+#define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */

+

+/* Bit 2 : Enable PPI channel 2. */

+#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */

+#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */

+#define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */

+

+/* Bit 1 : Enable PPI channel 1. */

+#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */

+#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */

+#define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */

+

+/* Bit 0 : Enable PPI channel 0. */

+#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */

+#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */

+#define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */

+

+/* Register: PPI_CHENSET */

+/* Description: Channel enable set. */

+

+/* Bit 31 : Enable PPI channel 31. */

+#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */

+#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */

+#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */

+

+/* Bit 30 : Enable PPI channel 30. */

+#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */

+#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */

+#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */

+

+/* Bit 29 : Enable PPI channel 29. */

+#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */

+#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */

+#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */

+

+/* Bit 28 : Enable PPI channel 28. */

+#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */

+#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */

+#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */

+

+/* Bit 27 : Enable PPI channel 27. */

+#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */

+#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */

+#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */

+

+/* Bit 26 : Enable PPI channel 26. */

+#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */

+#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */

+#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */

+

+/* Bit 25 : Enable PPI channel 25. */

+#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */

+#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */

+#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */

+

+/* Bit 24 : Enable PPI channel 24. */

+#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */

+#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */

+#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */

+

+/* Bit 23 : Enable PPI channel 23. */

+#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */

+#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */

+#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */

+

+/* Bit 22 : Enable PPI channel 22. */

+#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */

+#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */

+#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */

+

+/* Bit 21 : Enable PPI channel 21. */

+#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */

+#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */

+#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */

+

+/* Bit 20 : Enable PPI channel 20. */

+#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */

+#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */

+#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */

+

+/* Bit 15 : Enable PPI channel 15. */

+#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */

+#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */

+#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */

+

+/* Bit 14 : Enable PPI channel 14. */

+#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */

+#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */

+#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */

+

+/* Bit 13 : Enable PPI channel 13. */

+#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */

+#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */

+#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */

+

+/* Bit 12 : Enable PPI channel 12. */

+#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */

+#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */

+#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */

+

+/* Bit 11 : Enable PPI channel 11. */

+#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */

+#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */

+#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */

+

+/* Bit 10 : Enable PPI channel 10. */

+#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */

+#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */

+#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */

+

+/* Bit 9 : Enable PPI channel 9. */

+#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */

+#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */

+#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */

+

+/* Bit 8 : Enable PPI channel 8. */

+#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */

+#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */

+#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */

+

+/* Bit 7 : Enable PPI channel 7. */

+#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */

+#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */

+#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */

+

+/* Bit 6 : Enable PPI channel 6. */

+#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */

+#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */

+#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */

+

+/* Bit 5 : Enable PPI channel 5. */

+#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */

+#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */

+#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */

+

+/* Bit 4 : Enable PPI channel 4. */

+#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */

+#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */

+#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */

+

+/* Bit 3 : Enable PPI channel 3. */

+#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */

+#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */

+#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */

+

+/* Bit 2 : Enable PPI channel 2. */

+#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */

+#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */

+#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */

+

+/* Bit 1 : Enable PPI channel 1. */

+#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */

+#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */

+#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */

+

+/* Bit 0 : Enable PPI channel 0. */

+#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */

+#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */

+#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */

+

+/* Register: PPI_CHENCLR */

+/* Description: Channel enable clear. */

+

+/* Bit 31 : Disable PPI channel 31. */

+#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */

+#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */

+#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */

+

+/* Bit 30 : Disable PPI channel 30. */

+#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */

+#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */

+#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */

+

+/* Bit 29 : Disable PPI channel 29. */

+#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */

+#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */

+#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */

+

+/* Bit 28 : Disable PPI channel 28. */

+#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */

+#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */

+#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */

+

+/* Bit 27 : Disable PPI channel 27. */

+#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */

+#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */

+#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */

+

+/* Bit 26 : Disable PPI channel 26. */

+#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */

+#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */

+#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */

+

+/* Bit 25 : Disable PPI channel 25. */

+#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */

+#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */

+#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */

+

+/* Bit 24 : Disable PPI channel 24. */

+#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */

+#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */

+#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */

+

+/* Bit 23 : Disable PPI channel 23. */

+#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */

+#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */

+#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */

+

+/* Bit 22 : Disable PPI channel 22. */

+#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */

+#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */

+#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */

+

+/* Bit 21 : Disable PPI channel 21. */

+#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */

+#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */

+#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */

+

+/* Bit 20 : Disable PPI channel 20. */

+#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */

+#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */

+#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */

+

+/* Bit 15 : Disable PPI channel 15. */

+#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */

+#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */

+#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */

+

+/* Bit 14 : Disable PPI channel 14. */

+#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */

+#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */

+#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */

+

+/* Bit 13 : Disable PPI channel 13. */

+#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */

+#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */

+#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */

+

+/* Bit 12 : Disable PPI channel 12. */

+#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */

+#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */

+#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */

+

+/* Bit 11 : Disable PPI channel 11. */

+#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */

+#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */

+#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */

+

+/* Bit 10 : Disable PPI channel 10. */

+#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */

+#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */

+#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */

+

+/* Bit 9 : Disable PPI channel 9. */

+#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */

+#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */

+#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */

+

+/* Bit 8 : Disable PPI channel 8. */

+#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */

+#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */

+#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */

+

+/* Bit 7 : Disable PPI channel 7. */

+#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */

+#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */

+#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */

+

+/* Bit 6 : Disable PPI channel 6. */

+#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */

+#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */

+#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */

+

+/* Bit 5 : Disable PPI channel 5. */

+#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */

+#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */

+#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */

+

+/* Bit 4 : Disable PPI channel 4. */

+#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */

+#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */

+#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */

+

+/* Bit 3 : Disable PPI channel 3. */

+#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */

+#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */

+#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */

+

+/* Bit 2 : Disable PPI channel 2. */

+#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */

+#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */

+#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */

+

+/* Bit 1 : Disable PPI channel 1. */

+#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */

+#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */

+#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */

+

+/* Bit 0 : Disable PPI channel 0. */

+#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */

+#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */

+#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */

+#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */

+#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */

+

+/* Register: PPI_CHG */

+/* Description: Channel group configuration. */

+

+/* Bit 31 : Include CH31 in channel group. */

+#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */

+#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */

+#define PPI_CHG_CH31_Excluded (0UL) /*!< Channel excluded. */

+#define PPI_CHG_CH31_Included (1UL) /*!< Channel included. */

+

+/* Bit 30 : Include CH30 in channel group. */

+#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */

+#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */

+#define PPI_CHG_CH30_Excluded (0UL) /*!< Channel excluded. */

+#define PPI_CHG_CH30_Included (1UL) /*!< Channel included. */

+

+/* Bit 29 : Include CH29 in channel group. */

+#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */

+#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */

+#define PPI_CHG_CH29_Excluded (0UL) /*!< Channel excluded. */

+#define PPI_CHG_CH29_Included (1UL) /*!< Channel included. */

+

+/* Bit 28 : Include CH28 in channel group. */

+#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */

+#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */

+#define PPI_CHG_CH28_Excluded (0UL) /*!< Channel excluded. */

+#define PPI_CHG_CH28_Included (1UL) /*!< Channel included. */

+

+/* Bit 27 : Include CH27 in channel group. */

+#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */

+#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */

+#define PPI_CHG_CH27_Excluded (0UL) /*!< Channel excluded. */

+#define PPI_CHG_CH27_Included (1UL) /*!< Channel included. */

+

+/* Bit 26 : Include CH26 in channel group. */

+#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */

+#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */

+#define PPI_CHG_CH26_Excluded (0UL) /*!< Channel excluded. */

+#define PPI_CHG_CH26_Included (1UL) /*!< Channel included. */

+

+/* Bit 25 : Include CH25 in channel group. */

+#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */

+#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */

+#define PPI_CHG_CH25_Excluded (0UL) /*!< Channel excluded. */

+#define PPI_CHG_CH25_Included (1UL) /*!< Channel included. */

+

+/* Bit 24 : Include CH24 in channel group. */

+#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */

+#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */

+#define PPI_CHG_CH24_Excluded (0UL) /*!< Channel excluded. */

+#define PPI_CHG_CH24_Included (1UL) /*!< Channel included. */

+

+/* Bit 23 : Include CH23 in channel group. */

+#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */

+#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */

+#define PPI_CHG_CH23_Excluded (0UL) /*!< Channel excluded. */

+#define PPI_CHG_CH23_Included (1UL) /*!< Channel included. */

+

+/* Bit 22 : Include CH22 in channel group. */

+#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */

+#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */

+#define PPI_CHG_CH22_Excluded (0UL) /*!< Channel excluded. */

+#define PPI_CHG_CH22_Included (1UL) /*!< Channel included. */

+

+/* Bit 21 : Include CH21 in channel group. */

+#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */

+#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */

+#define PPI_CHG_CH21_Excluded (0UL) /*!< Channel excluded. */

+#define PPI_CHG_CH21_Included (1UL) /*!< Channel included. */

+

+/* Bit 20 : Include CH20 in channel group. */

+#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */

+#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */

+#define PPI_CHG_CH20_Excluded (0UL) /*!< Channel excluded. */

+#define PPI_CHG_CH20_Included (1UL) /*!< Channel included. */

+

+/* Bit 15 : Include CH15 in channel group. */

+#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */

+#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */

+#define PPI_CHG_CH15_Excluded (0UL) /*!< Channel excluded. */

+#define PPI_CHG_CH15_Included (1UL) /*!< Channel included. */

+

+/* Bit 14 : Include CH14 in channel group. */

+#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */

+#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */

+#define PPI_CHG_CH14_Excluded (0UL) /*!< Channel excluded. */

+#define PPI_CHG_CH14_Included (1UL) /*!< Channel included. */

+

+/* Bit 13 : Include CH13 in channel group. */

+#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */

+#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */

+#define PPI_CHG_CH13_Excluded (0UL) /*!< Channel excluded. */

+#define PPI_CHG_CH13_Included (1UL) /*!< Channel included. */

+

+/* Bit 12 : Include CH12 in channel group. */

+#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */

+#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */

+#define PPI_CHG_CH12_Excluded (0UL) /*!< Channel excluded. */

+#define PPI_CHG_CH12_Included (1UL) /*!< Channel included. */

+

+/* Bit 11 : Include CH11 in channel group. */

+#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */

+#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */

+#define PPI_CHG_CH11_Excluded (0UL) /*!< Channel excluded. */

+#define PPI_CHG_CH11_Included (1UL) /*!< Channel included. */

+

+/* Bit 10 : Include CH10 in channel group. */

+#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */

+#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */

+#define PPI_CHG_CH10_Excluded (0UL) /*!< Channel excluded. */

+#define PPI_CHG_CH10_Included (1UL) /*!< Channel included. */

+

+/* Bit 9 : Include CH9 in channel group. */

+#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */

+#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */

+#define PPI_CHG_CH9_Excluded (0UL) /*!< Channel excluded. */

+#define PPI_CHG_CH9_Included (1UL) /*!< Channel included. */

+

+/* Bit 8 : Include CH8 in channel group. */

+#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */

+#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */

+#define PPI_CHG_CH8_Excluded (0UL) /*!< Channel excluded. */

+#define PPI_CHG_CH8_Included (1UL) /*!< Channel included. */

+

+/* Bit 7 : Include CH7 in channel group. */

+#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */

+#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */

+#define PPI_CHG_CH7_Excluded (0UL) /*!< Channel excluded. */

+#define PPI_CHG_CH7_Included (1UL) /*!< Channel included. */

+

+/* Bit 6 : Include CH6 in channel group. */

+#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */

+#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */

+#define PPI_CHG_CH6_Excluded (0UL) /*!< Channel excluded. */

+#define PPI_CHG_CH6_Included (1UL) /*!< Channel included. */

+

+/* Bit 5 : Include CH5 in channel group. */

+#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */

+#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */

+#define PPI_CHG_CH5_Excluded (0UL) /*!< Channel excluded. */

+#define PPI_CHG_CH5_Included (1UL) /*!< Channel included. */

+

+/* Bit 4 : Include CH4 in channel group. */

+#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */

+#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */

+#define PPI_CHG_CH4_Excluded (0UL) /*!< Channel excluded. */

+#define PPI_CHG_CH4_Included (1UL) /*!< Channel included. */

+

+/* Bit 3 : Include CH3 in channel group. */

+#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */

+#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */

+#define PPI_CHG_CH3_Excluded (0UL) /*!< Channel excluded. */

+#define PPI_CHG_CH3_Included (1UL) /*!< Channel included. */

+

+/* Bit 2 : Include CH2 in channel group. */

+#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */

+#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */

+#define PPI_CHG_CH2_Excluded (0UL) /*!< Channel excluded. */

+#define PPI_CHG_CH2_Included (1UL) /*!< Channel included. */

+

+/* Bit 1 : Include CH1 in channel group. */

+#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */

+#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */

+#define PPI_CHG_CH1_Excluded (0UL) /*!< Channel excluded. */

+#define PPI_CHG_CH1_Included (1UL) /*!< Channel included. */

+

+/* Bit 0 : Include CH0 in channel group. */

+#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */

+#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */

+#define PPI_CHG_CH0_Excluded (0UL) /*!< Channel excluded. */

+#define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */

+

+

+/* Peripheral: QDEC */

+/* Description: Rotary decoder. */

+

+/* Register: QDEC_SHORTS */

+/* Description: Shortcuts for the QDEC. */

+

+/* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */

+#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */

+#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */

+#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */

+#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */

+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */

+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */

+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */

+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Register: QDEC_INTENSET */

+/* Description: Interrupt enable set register. */

+

+/* Bit 2 : Enable interrupt on ACCOF event. */

+#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */

+#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */

+#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */

+#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */

+#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 1 : Enable interrupt on REPORTRDY event. */

+#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */

+#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */

+#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */

+#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */

+#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 0 : Enable interrupt on SAMPLERDY event. */

+#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */

+#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */

+#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */

+#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */

+#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Register: QDEC_INTENCLR */

+/* Description: Interrupt enable clear register. */

+

+/* Bit 2 : Disable interrupt on ACCOF event. */

+#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */

+#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */

+#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */

+#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */

+#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 1 : Disable interrupt on REPORTRDY event. */

+#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */

+#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */

+#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */

+#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */

+#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 0 : Disable interrupt on SAMPLERDY event. */

+#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */

+#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */

+#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */

+#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */

+#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Register: QDEC_ENABLE */

+/* Description: Enable the QDEC. */

+

+/* Bit 0 : Enable or disable QDEC. */

+#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */

+#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */

+#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled QDEC. */

+#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QDEC. */

+

+/* Register: QDEC_LEDPOL */

+/* Description: LED output pin polarity. */

+

+/* Bit 0 : LED output pin polarity. */

+#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */

+#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */

+#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< LED output is active low. */

+#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< LED output is active high. */

+

+/* Register: QDEC_SAMPLEPER */

+/* Description: Sample period. */

+

+/* Bits 2..0 : Sample period. */

+#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */

+#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */

+#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /*!< 128us sample period. */

+#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /*!< 256us sample period. */

+#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /*!< 512us sample period. */

+#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /*!< 1024us sample period. */

+#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /*!< 2048us sample period. */

+#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /*!< 4096us sample period. */

+#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /*!< 8192us sample period. */

+#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /*!< 16384us sample period. */

+

+/* Register: QDEC_SAMPLE */

+/* Description: Motion sample value. */

+

+/* Bits 31..0 : Last sample taken in compliment to 2. */

+#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */

+#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */

+

+/* Register: QDEC_REPORTPER */

+/* Description: Number of samples to generate an EVENT_REPORTRDY. */

+

+/* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */

+#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */

+#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */

+#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /*!< 10 samples per report. */

+#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /*!< 40 samples per report. */

+#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /*!< 80 samples per report. */

+#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /*!< 120 samples per report. */

+#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /*!< 160 samples per report. */

+#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /*!< 200 samples per report. */

+#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /*!< 240 samples per report. */

+#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /*!< 280 samples per report. */

+

+/* Register: QDEC_DBFEN */

+/* Description: Enable debouncer input filters. */

+

+/* Bit 0 : Enable debounce input filters. */

+#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */

+#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */

+#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled. */

+#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled. */

+

+/* Register: QDEC_LEDPRE */

+/* Description: Time LED is switched ON before the sample. */

+

+/* Bits 8..0 : Period in us the LED in switched on prior to sampling. */

+#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */

+#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */

+

+/* Register: QDEC_ACCDBL */

+/* Description: Accumulated double (error) transitions register. */

+

+/* Bits 3..0 : Accumulated double (error) transitions. */

+#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */

+#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */

+

+/* Register: QDEC_ACCDBLREAD */

+/* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */

+

+/* Bits 3..0 : Snapshot of accumulated double (error) transitions. */

+#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */

+#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */

+

+/* Register: QDEC_POWER */

+/* Description: Peripheral power control. */

+

+/* Bit 0 : Peripheral power control. */

+#define QDEC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */

+#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */

+#define QDEC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */

+#define QDEC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */

+

+

+/* Peripheral: RADIO */

+/* Description: The radio. */

+

+/* Register: RADIO_SHORTS */

+/* Description: Shortcuts for the radio. */

+

+/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */

+#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */

+#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */

+#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Shortcut disabled. */

+#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */

+#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */

+#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */

+#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Shortcut disabled. */

+#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Bit 5 : Shortcut between END event and START task. */

+#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */

+#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */

+#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */

+#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */

+#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */

+#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */

+#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Shortcut disabled. */

+#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Bit 3 : Shortcut between DISABLED event and RXEN task. */

+#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */

+#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */

+#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Shortcut disabled. */

+#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Bit 2 : Shortcut between DISABLED event and TXEN task.  */

+#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */

+#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */

+#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Shortcut disabled. */

+#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Bit 1 : Shortcut between END event and DISABLE task. */

+#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */

+#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */

+#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Shortcut disabled. */

+#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Bit 0 : Shortcut between READY event and START task. */

+#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */

+#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */

+#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Shortcut disabled. */

+#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Register: RADIO_INTENSET */

+/* Description: Interrupt enable set register. */

+

+/* Bit 10 : Enable interrupt on BCMATCH event. */

+#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */

+#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */

+#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */

+#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */

+#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 7 : Enable interrupt on RSSIEND event. */

+#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */

+#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */

+#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */

+#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */

+#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 6 : Enable interrupt on DEVMISS event. */

+#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */

+#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */

+#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */

+#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */

+#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 5 : Enable interrupt on DEVMATCH event. */

+#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */

+#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */

+#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */

+#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */

+#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 4 : Enable interrupt on DISABLED event. */

+#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */

+#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */

+#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */

+#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */

+#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 3 : Enable interrupt on END event. */

+#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */

+#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */

+#define RADIO_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */

+#define RADIO_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */

+#define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 2 : Enable interrupt on PAYLOAD event. */

+#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */

+#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */

+#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */

+#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */

+#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 1 : Enable interrupt on ADDRESS event. */

+#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */

+#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */

+#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */

+#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */

+#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 0 : Enable interrupt on READY event. */

+#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */

+#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */

+#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */

+#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */

+#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Register: RADIO_INTENCLR */

+/* Description: Interrupt enable clear register. */

+

+/* Bit 10 : Disable interrupt on BCMATCH event. */

+#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */

+#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */

+#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */

+#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */

+#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 7 : Disable interrupt on RSSIEND event. */

+#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */

+#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */

+#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */

+#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */

+#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 6 : Disable interrupt on DEVMISS event. */

+#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */

+#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */

+#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */

+#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */

+#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 5 : Disable interrupt on DEVMATCH event. */

+#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */

+#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */

+#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */

+#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */

+#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 4 : Disable interrupt on DISABLED event. */

+#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */

+#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */

+#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */

+#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */

+#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 3 : Disable interrupt on END event. */

+#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */

+#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */

+#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */

+#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */

+#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 2 : Disable interrupt on PAYLOAD event. */

+#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */

+#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */

+#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */

+#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */

+#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 1 : Disable interrupt on ADDRESS event. */

+#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */

+#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */

+#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */

+#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */

+#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 0 : Disable interrupt on READY event. */

+#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */

+#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */

+#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */

+#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */

+#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Register: RADIO_CRCSTATUS */

+/* Description: CRC status of received packet. */

+

+/* Bit 0 : CRC status of received packet. */

+#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */

+#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */

+#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */

+#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */

+

+/* Register: RADIO_RXMATCH */

+/* Description: Received address. */

+

+/* Bits 2..0 : Logical address in which previous packet was received. */

+#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */

+#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */

+

+/* Register: RADIO_RXCRC */

+/* Description: Received CRC. */

+

+/* Bits 23..0 : CRC field of previously received packet. */

+#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */

+#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */

+

+/* Register: RADIO_DAI */

+/* Description: Device address match index. */

+

+/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */

+#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */

+#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */

+

+/* Register: RADIO_FREQUENCY */

+/* Description: Frequency. */

+

+/* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task.  */

+#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */

+#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */

+

+/* Register: RADIO_TXPOWER */

+/* Description: Output power. */

+

+/* Bits 7..0 : Radio output power. Decision point: TXEN task. */

+#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */

+#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */

+#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */

+#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */

+#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */

+#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */

+#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */

+#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */

+#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */

+#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */

+

+/* Register: RADIO_MODE */

+/* Description: Data rate and modulation. */

+

+/* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */

+#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */

+#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */

+#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /*!< 1Mbit/s Nordic propietary radio mode. */

+#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /*!< 2Mbit/s Nordic propietary radio mode. */

+#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /*!< 250kbit/s Nordic propietary radio mode. */

+#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /*!< 1Mbit/s Bluetooth Low Energy */

+

+/* Register: RADIO_PCNF0 */

+/* Description: Packet configuration 0. */

+

+/* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */

+#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */

+#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */

+

+/* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */

+#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */

+#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */

+

+/* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */

+#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */

+#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */

+

+/* Register: RADIO_PCNF1 */

+/* Description: Packet configuration 1. */

+

+/* Bit 25 : Packet whitening enable. */

+#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */

+#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */

+#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Whitening disabled. */

+#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Whitening enabled. */

+

+/* Bit 24 : On air endianness of packet length field. Decision point: START task. */

+#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */

+#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */

+#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */

+#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */

+

+/* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */

+#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */

+#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */

+

+/* Bits 15..8 : Static length in number of bytes. Decision point: START task. */

+#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */

+#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */

+

+/* Bits 7..0 : Maximum length of packet payload in number of bytes. */

+#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */

+#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */

+

+/* Register: RADIO_PREFIX0 */

+/* Description: Prefixes bytes for logical addresses 0 to 3. */

+

+/* Bits 31..24 : Address prefix 3. Decision point: START task. */

+#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */

+#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */

+

+/* Bits 23..16 : Address prefix 2. Decision point: START task. */

+#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */

+#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */

+

+/* Bits 15..8 : Address prefix 1. Decision point: START task. */

+#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */

+#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */

+

+/* Bits 7..0 : Address prefix 0. Decision point: START task. */

+#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */

+#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */

+

+/* Register: RADIO_PREFIX1 */

+/* Description: Prefixes bytes for logical addresses 4 to 7. */

+

+/* Bits 31..24 : Address prefix 7. Decision point: START task. */

+#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */

+#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */

+

+/* Bits 23..16 : Address prefix 6. Decision point: START task. */

+#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */

+#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */

+

+/* Bits 15..8 : Address prefix 5. Decision point: START task. */

+#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */

+#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */

+

+/* Bits 7..0 : Address prefix 4. Decision point: START task. */

+#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */

+#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */

+

+/* Register: RADIO_TXADDRESS */

+/* Description: Transmit address select. */

+

+/* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */

+#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */

+#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */

+

+/* Register: RADIO_RXADDRESSES */

+/* Description: Receive address select. */

+

+/* Bit 7 : Enable reception on logical address 7. Decision point: START task. */

+#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */

+#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */

+#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Reception disabled. */

+#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Reception enabled. */

+

+/* Bit 6 : Enable reception on logical address 6. Decision point: START task. */

+#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */

+#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */

+#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Reception disabled. */

+#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Reception enabled. */

+

+/* Bit 5 : Enable reception on logical address 5. Decision point: START task. */

+#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */

+#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */

+#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Reception disabled. */

+#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Reception enabled. */

+

+/* Bit 4 : Enable reception on logical address 4. Decision point: START task. */

+#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */

+#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */

+#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Reception disabled. */

+#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Reception enabled. */

+

+/* Bit 3 : Enable reception on logical address 3. Decision point: START task. */

+#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */

+#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */

+#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Reception disabled. */

+#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Reception enabled. */

+

+/* Bit 2 : Enable reception on logical address 2. Decision point: START task. */

+#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */

+#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */

+#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Reception disabled. */

+#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Reception enabled. */

+

+/* Bit 1 : Enable reception on logical address 1. Decision point: START task. */

+#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */

+#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */

+#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Reception disabled. */

+#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Reception enabled. */

+

+/* Bit 0 : Enable reception on logical address 0. Decision point: START task. */

+#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */

+#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */

+#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Reception disabled. */

+#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Reception enabled. */

+

+/* Register: RADIO_CRCCNF */

+/* Description: CRC configuration. */

+

+/* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */

+#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */

+#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */

+#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< Include packet address in CRC calculation. */

+#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */

+

+/* Bits 1..0 : CRC length. Decision point: START task. */

+#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */

+#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */

+#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC calculation disabled. */

+#define RADIO_CRCCNF_LEN_One (1UL) /*!< One byte long CRC. */

+#define RADIO_CRCCNF_LEN_Two (2UL) /*!< Two bytes long CRC. */

+#define RADIO_CRCCNF_LEN_Three (3UL) /*!< Three bytes long CRC. */

+

+/* Register: RADIO_CRCPOLY */

+/* Description: CRC polynomial. */

+

+/* Bits 23..0 : CRC polynomial. Decision point: START task. */

+#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */

+#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */

+

+/* Register: RADIO_CRCINIT */

+/* Description: CRC initial value. */

+

+/* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */

+#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */

+#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */

+

+/* Register: RADIO_TEST */

+/* Description: Test features enable register. */

+

+/* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */

+#define RADIO_TEST_PLLLOCK_Pos (1UL) /*!< Position of PLLLOCK field. */

+#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /*!< Bit mask of PLLLOCK field. */

+#define RADIO_TEST_PLLLOCK_Disabled (0UL) /*!< PLL lock disabled. */

+#define RADIO_TEST_PLLLOCK_Enabled (1UL) /*!< PLL lock enabled. */

+

+/* Bit 0 : Constant carrier. Decision point: TXEN task. */

+#define RADIO_TEST_CONSTCARRIER_Pos (0UL) /*!< Position of CONSTCARRIER field. */

+#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /*!< Bit mask of CONSTCARRIER field. */

+#define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /*!< Constant carrier disabled. */

+#define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /*!< Constant carrier enabled. */

+

+/* Register: RADIO_TIFS */

+/* Description: Inter Frame Spacing in microseconds. */

+

+/* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */

+#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */

+#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */

+

+/* Register: RADIO_RSSISAMPLE */

+/* Description: RSSI sample. */

+

+/* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */

+#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */

+#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */

+

+/* Register: RADIO_STATE */

+/* Description: Current radio state. */

+

+/* Bits 3..0 : Current radio state. */

+#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */

+#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */

+#define RADIO_STATE_STATE_Disabled (0x00UL) /*!< Radio is in the Disabled state. */

+#define RADIO_STATE_STATE_RxRu (0x01UL) /*!< Radio is in the Rx Ramp Up state. */

+#define RADIO_STATE_STATE_RxIdle (0x02UL) /*!< Radio is in the Rx Idle state. */

+#define RADIO_STATE_STATE_Rx (0x03UL) /*!< Radio is in the Rx state. */

+#define RADIO_STATE_STATE_RxDisable (0x04UL) /*!< Radio is in the Rx Disable state. */

+#define RADIO_STATE_STATE_TxRu (0x09UL) /*!< Radio is in the Tx Ramp Up state. */

+#define RADIO_STATE_STATE_TxIdle (0x0AUL) /*!< Radio is in the Tx Idle state. */

+#define RADIO_STATE_STATE_Tx (0x0BUL) /*!< Radio is in the Tx state. */

+#define RADIO_STATE_STATE_TxDisable (0x0CUL) /*!< Radio is in the Tx Disable state. */

+

+/* Register: RADIO_DATAWHITEIV */

+/* Description: Data whitening initial value. */

+

+/* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */

+#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */

+#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */

+

+/* Register: RADIO_DAP */

+/* Description: Device address prefix. */

+

+/* Bits 15..0 : Device address prefix. */

+#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */

+#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */

+

+/* Register: RADIO_DACNF */

+/* Description: Device address match configuration. */

+

+/* Bit 15 : TxAdd for device address 7. */

+#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */

+#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */

+

+/* Bit 14 : TxAdd for device address 6. */

+#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */

+#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */

+

+/* Bit 13 : TxAdd for device address 5. */

+#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */

+#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */

+

+/* Bit 12 : TxAdd for device address 4. */

+#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */

+#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */

+

+/* Bit 11 : TxAdd for device address 3. */

+#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */

+#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */

+

+/* Bit 10 : TxAdd for device address 2. */

+#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */

+#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */

+

+/* Bit 9 : TxAdd for device address 1. */

+#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */

+#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */

+

+/* Bit 8 : TxAdd for device address 0. */

+#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */

+#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */

+

+/* Bit 7 : Enable or disable device address matching using device address 7. */

+#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */

+#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */

+#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled. */

+#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled. */

+

+/* Bit 6 : Enable or disable device address matching using device address 6. */

+#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */

+#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */

+#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled. */

+#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled. */

+

+/* Bit 5 : Enable or disable device address matching using device address 5. */

+#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */

+#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */

+#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled. */

+#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled. */

+

+/* Bit 4 : Enable or disable device address matching using device address 4. */

+#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */

+#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */

+#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled. */

+#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled. */

+

+/* Bit 3 : Enable or disable device address matching using device address 3. */

+#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */

+#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */

+#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled. */

+#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled. */

+

+/* Bit 2 : Enable or disable device address matching using device address 2. */

+#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */

+#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */

+#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled. */

+#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled. */

+

+/* Bit 1 : Enable or disable device address matching using device address 1. */

+#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */

+#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */

+#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled. */

+#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled. */

+

+/* Bit 0 : Enable or disable device address matching using device address 0. */

+#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */

+#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */

+#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled. */

+#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled. */

+

+/* Register: RADIO_OVERRIDE0 */

+/* Description: Trim value override register 0. */

+

+/* Bits 31..0 : Trim value override 0. */

+#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */

+#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */

+

+/* Register: RADIO_OVERRIDE1 */

+/* Description: Trim value override register 1. */

+

+/* Bits 31..0 : Trim value override 1. */

+#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */

+#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */

+

+/* Register: RADIO_OVERRIDE2 */

+/* Description: Trim value override register 2. */

+

+/* Bits 31..0 : Trim value override 2. */

+#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */

+#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */

+

+/* Register: RADIO_OVERRIDE3 */

+/* Description: Trim value override register 3. */

+

+/* Bits 31..0 : Trim value override 3. */

+#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */

+#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */

+

+/* Register: RADIO_OVERRIDE4 */

+/* Description: Trim value override register 4. */

+

+/* Bit 31 : Enable or disable override of default trim values. */

+#define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */

+#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /*!< Bit mask of ENABLE field. */

+#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */

+#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */

+

+/* Bits 27..0 : Trim value override 4. */

+#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */

+#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */

+

+/* Register: RADIO_POWER */

+/* Description: Peripheral power control. */

+

+/* Bit 0 : Peripheral power control. */

+#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */

+#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */

+#define RADIO_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */

+#define RADIO_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */

+

+

+/* Peripheral: RNG */

+/* Description: Random Number Generator. */

+

+/* Register: RNG_SHORTS */

+/* Description: Shortcuts for the RNG. */

+

+/* Bit 0 : Shortcut between VALRDY event and STOP task. */

+#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */

+#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */

+#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */

+#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Register: RNG_INTENSET */

+/* Description: Interrupt enable set register */

+

+/* Bit 0 : Enable interrupt on VALRDY event. */

+#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */

+#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */

+#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */

+#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */

+#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Register: RNG_INTENCLR */

+/* Description: Interrupt enable clear register */

+

+/* Bit 0 : Disable interrupt on VALRDY event. */

+#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */

+#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */

+#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */

+#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */

+#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Register: RNG_CONFIG */

+/* Description: Configuration register. */

+

+/* Bit 0 : Digital error correction enable. */

+#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */

+#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */

+#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Digital error correction disabled. */

+#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Digital error correction enabled. */

+

+/* Register: RNG_VALUE */

+/* Description: RNG random number. */

+

+/* Bits 7..0 : Generated random number. */

+#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */

+#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */

+

+/* Register: RNG_POWER */

+/* Description: Peripheral power control. */

+

+/* Bit 0 : Peripheral power control. */

+#define RNG_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */

+#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /*!< Bit mask of POWER field. */

+#define RNG_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */

+#define RNG_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */

+

+

+/* Peripheral: RTC */

+/* Description: Real time counter 0. */

+

+/* Register: RTC_INTENSET */

+/* Description: Interrupt enable set register. */

+

+/* Bit 19 : Enable interrupt on COMPARE[3] event. */

+#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */

+#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */

+#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */

+#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */

+#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 18 : Enable interrupt on COMPARE[2] event. */

+#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */

+#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */

+#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */

+#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */

+#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 17 : Enable interrupt on COMPARE[1] event. */

+#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */

+#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */

+#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */

+#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */

+#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 16 : Enable interrupt on COMPARE[0] event. */

+#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */

+#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */

+#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */

+#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */

+#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 1 : Enable interrupt on OVRFLW event. */

+#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */

+#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */

+#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */

+#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */

+#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 0 : Enable interrupt on TICK event. */

+#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */

+#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */

+#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Interrupt disabled. */

+#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Interrupt enabled. */

+#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Register: RTC_INTENCLR */

+/* Description: Interrupt enable clear register. */

+

+/* Bit 19 : Disable interrupt on COMPARE[3] event. */

+#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */

+#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */

+#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */

+#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */

+#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 18 : Disable interrupt on COMPARE[2] event. */

+#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */

+#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */

+#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */

+#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */

+#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 17 : Disable interrupt on COMPARE[1] event. */

+#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */

+#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */

+#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */

+#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */

+#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 16 : Disable interrupt on COMPARE[0] event. */

+#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */

+#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */

+#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */

+#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */

+#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 1 : Disable interrupt on OVRFLW event. */

+#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */

+#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */

+#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */

+#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */

+#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 0 : Disable interrupt on TICK event. */

+#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */

+#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */

+#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Interrupt disabled. */

+#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Interrupt enabled. */

+#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Register: RTC_EVTEN */

+/* Description: Configures event enable routing to PPI for each RTC event. */

+

+/* Bit 19 : COMPARE[3] event enable. */

+#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */

+#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */

+#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Event disabled. */

+#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Event enabled. */

+

+/* Bit 18 : COMPARE[2] event enable. */

+#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */

+#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */

+#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Event disabled. */

+#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Event enabled. */

+

+/* Bit 17 : COMPARE[1] event enable. */

+#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */

+#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */

+#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Event disabled. */

+#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Event enabled. */

+

+/* Bit 16 : COMPARE[0] event enable. */

+#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */

+#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */

+#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Event disabled. */

+#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Event enabled. */

+

+/* Bit 1 : OVRFLW event enable. */

+#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */

+#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */

+#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Event disabled. */

+#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Event enabled. */

+

+/* Bit 0 : TICK event enable. */

+#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */

+#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */

+#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Event disabled. */

+#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Event enabled. */

+

+/* Register: RTC_EVTENSET */

+/* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */

+

+/* Bit 19 : Enable routing to PPI of COMPARE[3] event. */

+#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */

+#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */

+#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Event disabled. */

+#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Event enabled. */

+#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */

+

+/* Bit 18 : Enable routing to PPI of COMPARE[2] event. */

+#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */

+#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */

+#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Event disabled. */

+#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Event enabled. */

+#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */

+

+/* Bit 17 : Enable routing to PPI of COMPARE[1] event. */

+#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */

+#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */

+#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Event disabled. */

+#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Event enabled. */

+#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */

+

+/* Bit 16 : Enable routing to PPI of COMPARE[0] event. */

+#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */

+#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */

+#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Event disabled. */

+#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Event enabled. */

+#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */

+

+/* Bit 1 : Enable routing to PPI of OVRFLW event. */

+#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */

+#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */

+#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Event disabled. */

+#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Event enabled. */

+#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */

+

+/* Bit 0 : Enable routing to PPI of TICK event. */

+#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */

+#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */

+#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Event disabled. */

+#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Event enabled. */

+#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */

+

+/* Register: RTC_EVTENCLR */

+/* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */

+

+/* Bit 19 : Disable routing to PPI of COMPARE[3] event. */

+#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */

+#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */

+#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Event disabled. */

+#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Event enabled. */

+#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable event on write. */

+

+/* Bit 18 : Disable routing to PPI of COMPARE[2] event. */

+#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */

+#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */

+#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Event disabled. */

+#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Event enabled. */

+#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable event on write. */

+

+/* Bit 17 : Disable routing to PPI of COMPARE[1] event. */

+#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */

+#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */

+#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Event disabled. */

+#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Event enabled. */

+#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable event on write. */

+

+/* Bit 16 : Disable routing to PPI of COMPARE[0] event. */

+#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */

+#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */

+#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Event disabled. */

+#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Event enabled. */

+#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable event on write. */

+

+/* Bit 1 : Disable routing to PPI of OVRFLW event. */

+#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */

+#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */

+#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Event disabled. */

+#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Event enabled. */

+#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable event on write. */

+

+/* Bit 0 : Disable routing to PPI of TICK event. */

+#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */

+#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */

+#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Event disabled. */

+#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Event enabled. */

+#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable event on write. */

+

+/* Register: RTC_COUNTER */

+/* Description: Current COUNTER value. */

+

+/* Bits 23..0 : Counter value. */

+#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */

+#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */

+

+/* Register: RTC_PRESCALER */

+/* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */

+

+/* Bits 11..0 : RTC PRESCALER value. */

+#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */

+#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */

+

+/* Register: RTC_CC */

+/* Description: Capture/compare registers. */

+

+/* Bits 23..0 : Compare value. */

+#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */

+#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */

+

+/* Register: RTC_POWER */

+/* Description: Peripheral power control. */

+

+/* Bit 0 : Peripheral power control. */

+#define RTC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */

+#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */

+#define RTC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */

+#define RTC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */

+

+

+/* Peripheral: SPI */

+/* Description: SPI master 0. */

+

+/* Register: SPI_INTENSET */

+/* Description: Interrupt enable set register. */

+

+/* Bit 2 : Enable interrupt on READY event. */

+#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */

+#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */

+#define SPI_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */

+#define SPI_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */

+#define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Register: SPI_INTENCLR */

+/* Description: Interrupt enable clear register. */

+

+/* Bit 2 : Disable interrupt on READY event. */

+#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */

+#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */

+#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */

+#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */

+#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Register: SPI_ENABLE */

+/* Description: Enable SPI. */

+

+/* Bits 2..0 : Enable or disable SPI. */

+#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */

+#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */

+#define SPI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPI. */

+#define SPI_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable SPI. */

+

+/* Register: SPI_RXD */

+/* Description: RX data. */

+

+/* Bits 7..0 : RX data from last transfer. */

+#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */

+#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */

+

+/* Register: SPI_TXD */

+/* Description: TX data. */

+

+/* Bits 7..0 : TX data for next transfer. */

+#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */

+#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */

+

+/* Register: SPI_FREQUENCY */

+/* Description: SPI frequency */

+

+/* Bits 31..0 : SPI data rate. */

+#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */

+#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */

+#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125kbps. */

+#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250kbps. */

+#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500kbps. */

+#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1Mbps. */

+#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2Mbps. */

+#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4Mbps. */

+#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8Mbps. */

+

+/* Register: SPI_CONFIG */

+/* Description: Configuration register. */

+

+/* Bit 2 : Serial clock (SCK) polarity. */

+#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */

+#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */

+#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */

+#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */

+

+/* Bit 1 : Serial clock (SCK) phase. */

+#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */

+#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */

+#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */

+#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */

+

+/* Bit 0 : Bit order. */

+#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */

+#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */

+#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */

+#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */

+

+/* Register: SPI_POWER */

+/* Description: Peripheral power control. */

+

+/* Bit 0 : Peripheral power control. */

+#define SPI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */

+#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */

+#define SPI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */

+#define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */

+

+

+/* Peripheral: SPIM */

+/* Description: SPI master with easyDMA 1. */

+

+/* Register: SPIM_INTENSET */

+/* Description: Interrupt enable set register. */

+

+/* Bit 19 : Enable interrupt on STARTED event. */

+#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */

+#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */

+#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Interrupt disabled. */

+#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Interrupt enabled. */

+#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 8 : Enable interrupt on ENDTX event. */

+#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */

+#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */

+#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */

+#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */

+#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 4 : Enable interrupt on ENDRX event. */

+#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */

+#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */

+#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */

+#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */

+#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 1 : Enable interrupt on STOPPED event. */

+#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */

+#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */

+#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */

+#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */

+#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Register: SPIM_INTENCLR */

+/* Description: Interrupt enable clear register. */

+

+/* Bit 19 : Disable interrupt on STARTED event. */

+#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */

+#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */

+#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Interrupt disabled. */

+#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Interrupt enabled. */

+#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 8 : Disable interrupt on ENDTX event. */

+#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */

+#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */

+#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */

+#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */

+#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 4 : Disable interrupt on ENDRX event. */

+#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */

+#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */

+#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */

+#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */

+#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 1 : Disable interrupt on STOPPED event. */

+#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */

+#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */

+#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */

+#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */

+#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Register: SPIM_ENABLE */

+/* Description: Enable SPIM. */

+

+/* Bits 3..0 : Enable or disable SPIM. */

+#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */

+#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */

+#define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIM. */

+#define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /*!< Enable SPIM. */

+

+/* Register: SPIM_FREQUENCY */

+/* Description: SPI frequency. */

+

+/* Bits 31..0 : SPI master data rate. */

+#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */

+#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */

+#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps. */

+#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */

+#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps. */

+#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps. */

+#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps. */

+#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps. */

+#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps. */

+

+/* Register: SPIM_RXD_PTR */

+/* Description: Data pointer. */

+

+/* Bits 31..0 : Data pointer. */

+#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */

+#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

+

+/* Register: SPIM_RXD_MAXCNT */

+/* Description: Maximum number of buffer bytes to receive. */

+

+/* Bits 7..0 : Maximum number of buffer bytes to receive. */

+#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */

+#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

+

+/* Register: SPIM_RXD_AMOUNT */

+/* Description: Number of bytes received in the last transaction. */

+

+/* Bits 7..0 : Number of bytes received in the last transaction. */

+#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */

+#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */

+

+/* Register: SPIM_TXD_PTR */

+/* Description: Data pointer. */

+

+/* Bits 31..0 : Data pointer. */

+#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */

+#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

+

+/* Register: SPIM_TXD_MAXCNT */

+/* Description: Maximum number of buffer bytes to send. */

+

+/* Bits 7..0 : Maximum number of buffer bytes to send. */

+#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */

+#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

+

+/* Register: SPIM_TXD_AMOUNT */

+/* Description: Number of bytes sent in the last transaction. */

+

+/* Bits 7..0 : Number of bytes sent in the last transaction. */

+#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */

+#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */

+

+/* Register: SPIM_CONFIG */

+/* Description: Configuration register. */

+

+/* Bit 2 : Serial clock (SCK) polarity. */

+#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */

+#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */

+#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */

+#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */

+

+/* Bit 1 : Serial clock (SCK) phase. */

+#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */

+#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */

+#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */

+#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */

+

+/* Bit 0 : Bit order. */

+#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */

+#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */

+#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */

+#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */

+

+/* Register: SPIM_ORC */

+/* Description: Over-read character. */

+

+/* Bits 7..0 : Over-read character. */

+#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */

+#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */

+

+/* Register: SPIM_POWER */

+/* Description: Peripheral power control. */

+

+/* Bit 0 : Peripheral power control. */

+#define SPIM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */

+#define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */

+#define SPIM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */

+#define SPIM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */

+

+

+/* Peripheral: SPIS */

+/* Description: SPI slave 1. */

+

+/* Register: SPIS_SHORTS */

+/* Description: Shortcuts for SPIS. */

+

+/* Bit 2 : Shortcut between END event and the ACQUIRE task. */

+#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */

+#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */

+#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Shortcut disabled. */

+#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Register: SPIS_INTENSET */

+/* Description: Interrupt enable set register. */

+

+/* Bit 10 : Enable interrupt on ACQUIRED event. */

+#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */

+#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */

+#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */

+#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */

+#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 4 : enable interrupt on ENDRX event. */

+#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */

+#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */

+#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */

+#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */

+#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 1 : Enable interrupt on END event. */

+#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */

+#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */

+#define SPIS_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */

+#define SPIS_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */

+#define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Register: SPIS_INTENCLR */

+/* Description: Interrupt enable clear register. */

+

+/* Bit 10 : Disable interrupt on ACQUIRED event. */

+#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */

+#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */

+#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */

+#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */

+#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 4 : Disable interrupt on ENDRX event. */

+#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */

+#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */

+#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */

+#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */

+#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 1 : Disable interrupt on END event. */

+#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */

+#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */

+#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */

+#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */

+#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Register: SPIS_SEMSTAT */

+/* Description: Semaphore status. */

+

+/* Bits 1..0 : Semaphore status. */

+#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */

+#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */

+#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /*!< Semaphore is free. */

+#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /*!< Semaphore is assigned to the CPU. */

+#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /*!< Semaphore is assigned to the SPIS. */

+#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /*!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. */

+

+/* Register: SPIS_STATUS */

+/* Description: Status from last transaction. */

+

+/* Bit 1 : RX buffer overflow detected, and prevented. */

+#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */

+#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */

+#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Error not present. */

+#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Error present. */

+#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Clear on write. */

+

+/* Bit 0 : TX buffer overread detected, and prevented. */

+#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */

+#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */

+#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Error not present. */

+#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Error present. */

+#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Clear on write. */

+

+/* Register: SPIS_ENABLE */

+/* Description: Enable SPIS. */

+

+/* Bits 2..0 : Enable or disable SPIS. */

+#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */

+#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */

+#define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIS. */

+#define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable SPIS. */

+

+/* Register: SPIS_MAXRX */

+/* Description: Maximum number of bytes in the receive buffer. */

+

+/* Bits 7..0 : Maximum number of bytes in the receive buffer. */

+#define SPIS_MAXRX_MAXRX_Pos (0UL) /*!< Position of MAXRX field. */

+#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /*!< Bit mask of MAXRX field. */

+

+/* Register: SPIS_AMOUNTRX */

+/* Description: Number of bytes received in last granted transaction. */

+

+/* Bits 7..0 : Number of bytes received in last granted transaction. */

+#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /*!< Position of AMOUNTRX field. */

+#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /*!< Bit mask of AMOUNTRX field. */

+

+/* Register: SPIS_MAXTX */

+/* Description: Maximum number of bytes in the transmit buffer. */

+

+/* Bits 7..0 : Maximum number of bytes in the transmit buffer. */

+#define SPIS_MAXTX_MAXTX_Pos (0UL) /*!< Position of MAXTX field. */

+#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /*!< Bit mask of MAXTX field. */

+

+/* Register: SPIS_AMOUNTTX */

+/* Description: Number of bytes transmitted in last granted transaction. */

+

+/* Bits 7..0 : Number of bytes transmitted in last granted transaction. */

+#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /*!< Position of AMOUNTTX field. */

+#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /*!< Bit mask of AMOUNTTX field. */

+

+/* Register: SPIS_CONFIG */

+/* Description: Configuration register. */

+

+/* Bit 2 : Serial clock (SCK) polarity. */

+#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */

+#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */

+#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */

+#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */

+

+/* Bit 1 : Serial clock (SCK) phase. */

+#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */

+#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */

+#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */

+#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */

+

+/* Bit 0 : Bit order. */

+#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */

+#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */

+#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */

+#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */

+

+/* Register: SPIS_DEF */

+/* Description: Default character. */

+

+/* Bits 7..0 : Default character. */

+#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */

+#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */

+

+/* Register: SPIS_ORC */

+/* Description: Over-read character. */

+

+/* Bits 7..0 : Over-read character. */

+#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */

+#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */

+

+/* Register: SPIS_POWER */

+/* Description: Peripheral power control. */

+

+/* Bit 0 : Peripheral power control. */

+#define SPIS_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */

+#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /*!< Bit mask of POWER field. */

+#define SPIS_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */

+#define SPIS_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */

+

+

+/* Peripheral: TEMP */

+/* Description: Temperature Sensor. */

+

+/* Register: TEMP_INTENSET */

+/* Description: Interrupt enable set register. */

+

+/* Bit 0 : Enable interrupt on DATARDY event. */

+#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */

+#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */

+#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */

+#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */

+#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Register: TEMP_INTENCLR */

+/* Description: Interrupt enable clear register. */

+

+/* Bit 0 : Disable interrupt on DATARDY event. */

+#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */

+#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */

+#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */

+#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */

+#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Register: TEMP_POWER */

+/* Description: Peripheral power control. */

+

+/* Bit 0 : Peripheral power control. */

+#define TEMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */

+#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */

+#define TEMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */

+#define TEMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */

+

+

+/* Peripheral: TIMER */

+/* Description: Timer 0. */

+

+/* Register: TIMER_SHORTS */

+/* Description: Shortcuts for Timer. */

+

+/* Bit 11 : Shortcut between CC[3] event and the STOP task. */

+#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */

+#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */

+#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Shortcut disabled. */

+#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Bit 10 : Shortcut between CC[2] event and the STOP task. */

+#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */

+#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */

+#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Shortcut disabled. */

+#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Bit 9 : Shortcut between CC[1] event and the STOP task. */

+#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */

+#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */

+#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Shortcut disabled. */

+#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Bit 8 : Shortcut between CC[0] event and the STOP task. */

+#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */

+#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */

+#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Shortcut disabled. */

+#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */

+#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */

+#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */

+#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */

+#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */

+#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */

+#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */

+#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */

+#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */

+#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */

+#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */

+#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */

+#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */

+#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */

+#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */

+#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */

+#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Register: TIMER_INTENSET */

+/* Description: Interrupt enable set register. */

+

+/* Bit 19 : Enable interrupt on COMPARE[3] */

+#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */

+#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */

+#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */

+#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */

+#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 18 : Enable interrupt on COMPARE[2] */

+#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */

+#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */

+#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */

+#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */

+#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 17 : Enable interrupt on COMPARE[1] */

+#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */

+#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */

+#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */

+#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */

+#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 16 : Enable interrupt on COMPARE[0] */

+#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */

+#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */

+#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */

+#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */

+#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Register: TIMER_INTENCLR */

+/* Description: Interrupt enable clear register. */

+

+/* Bit 19 : Disable interrupt on COMPARE[3] */

+#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */

+#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */

+#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */

+#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */

+#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 18 : Disable interrupt on COMPARE[2] */

+#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */

+#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */

+#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */

+#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */

+#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 17 : Disable interrupt on COMPARE[1] */

+#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */

+#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */

+#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */

+#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */

+#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 16 : Disable interrupt on COMPARE[0] */

+#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */

+#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */

+#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */

+#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */

+#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Register: TIMER_MODE */

+/* Description: Timer Mode selection. */

+

+/* Bit 0 : Select Normal or Counter mode. */

+#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */

+#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */

+#define TIMER_MODE_MODE_Timer (0UL) /*!< Timer in Normal mode. */

+#define TIMER_MODE_MODE_Counter (1UL) /*!< Timer in Counter mode. */

+

+/* Register: TIMER_BITMODE */

+/* Description: Sets timer behaviour. */

+

+/* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */

+#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */

+#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */

+#define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /*!< 16-bit timer behaviour. */

+#define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /*!< 8-bit timer behaviour. */

+#define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /*!< 24-bit timer behaviour. */

+#define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /*!< 32-bit timer behaviour. */

+

+/* Register: TIMER_PRESCALER */

+/* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */

+

+/* Bits 3..0 : Timer PRESCALER value. Max value is 9. */

+#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */

+#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */

+

+/* Register: TIMER_POWER */

+/* Description: Peripheral power control. */

+

+/* Bit 0 : Peripheral power control. */

+#define TIMER_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */

+#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /*!< Bit mask of POWER field. */

+#define TIMER_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */

+#define TIMER_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */

+

+

+/* Peripheral: TWI */

+/* Description: Two-wire interface master 0. */

+

+/* Register: TWI_SHORTS */

+/* Description: Shortcuts for TWI. */

+

+/* Bit 1 : Shortcut between BB event and the STOP task. */

+#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */

+#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */

+#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Shortcut disabled. */

+#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Bit 0 : Shortcut between BB event and the SUSPEND task. */

+#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */

+#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */

+#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Shortcut disabled. */

+#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Register: TWI_INTENSET */

+/* Description: Interrupt enable set register. */

+

+/* Bit 18 : Enable interrupt on SUSPENDED event. */

+#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */

+#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */

+#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */

+#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */

+#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 14 : Enable interrupt on BB event. */

+#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */

+#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */

+#define TWI_INTENSET_BB_Disabled (0UL) /*!< Interrupt disabled. */

+#define TWI_INTENSET_BB_Enabled (1UL) /*!< Interrupt enabled. */

+#define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 9 : Enable interrupt on ERROR event. */

+#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */

+#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */

+#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */

+#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */

+#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 7 : Enable interrupt on TXDSENT event. */

+#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */

+#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */

+#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */

+#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */

+#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 2 : Enable interrupt on READY event. */

+#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */

+#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */

+#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */

+#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */

+#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 1 : Enable interrupt on STOPPED event. */

+#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */

+#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */

+#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */

+#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */

+#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Register: TWI_INTENCLR */

+/* Description: Interrupt enable clear register. */

+

+/* Bit 18 : Disable interrupt on SUSPENDED event. */

+#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */

+#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */

+#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */

+#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */

+#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 14 : Disable interrupt on BB event. */

+#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */

+#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */

+#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Interrupt disabled. */

+#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Interrupt enabled. */

+#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 9 : Disable interrupt on ERROR event. */

+#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */

+#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */

+#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */

+#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */

+#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 7 : Disable interrupt on TXDSENT event. */

+#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */

+#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */

+#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */

+#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */

+#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 2 : Disable interrupt on RXDREADY event. */

+#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */

+#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */

+#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */

+#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */

+#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 1 : Disable interrupt on STOPPED event. */

+#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */

+#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */

+#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */

+#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */

+#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Register: TWI_ERRORSRC */

+/* Description: Two-wire error source. Write error field to 1 to clear error. */

+

+/* Bit 2 : NACK received after sending a data byte. */

+#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */

+#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */

+#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Error not present. */

+#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Error present. */

+#define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Clear error on write. */

+

+/* Bit 1 : NACK received after sending the address. */

+#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */

+#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */

+#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Error not present. */

+#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */

+#define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */

+

+/* Bit 0 : Byte received in RXD register before read of the last received byte (data loss). */

+#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */

+#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */

+#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */

+#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */

+#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */

+

+/* Register: TWI_ENABLE */

+/* Description: Enable two-wire master. */

+

+/* Bits 2..0 : Enable or disable W2M */

+#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */

+#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */

+#define TWI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled. */

+#define TWI_ENABLE_ENABLE_Enabled (0x05UL) /*!< Enabled. */

+

+/* Register: TWI_RXD */

+/* Description: RX data register. */

+

+/* Bits 7..0 : RX data from last transfer. */

+#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */

+#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */

+

+/* Register: TWI_TXD */

+/* Description: TX data register. */

+

+/* Bits 7..0 : TX data for next transfer. */

+#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */

+#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */

+

+/* Register: TWI_FREQUENCY */

+/* Description: Two-wire frequency. */

+

+/* Bits 31..0 : Two-wire master clock frequency. */

+#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */

+#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */

+#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */

+#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */

+#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps. */

+

+/* Register: TWI_ADDRESS */

+/* Description: Address used in the two-wire transfer. */

+

+/* Bits 6..0 : Two-wire address. */

+#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */

+#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */

+

+/* Register: TWI_POWER */

+/* Description: Peripheral power control. */

+

+/* Bit 0 : Peripheral power control. */

+#define TWI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */

+#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */

+#define TWI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */

+#define TWI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */

+

+

+/* Peripheral: UART */

+/* Description: Universal Asynchronous Receiver/Transmitter. */

+

+/* Register: UART_SHORTS */

+/* Description: Shortcuts for UART. */

+

+/* Bit 4 : Shortcut between NCTS event and STOPRX task. */

+#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */

+#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */

+#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */

+#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Bit 3 : Shortcut between CTS event and STARTRX task. */

+#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */

+#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */

+#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */

+#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */

+

+/* Register: UART_INTENSET */

+/* Description: Interrupt enable set register. */

+

+/* Bit 17 : Enable interrupt on RXTO event. */

+#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */

+#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */

+#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Interrupt disabled. */

+#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Interrupt enabled. */

+#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 9 : Enable interrupt on ERROR event. */

+#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */

+#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */

+#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */

+#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */

+#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 7 : Enable interrupt on TXRDY event. */

+#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */

+#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */

+#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */

+#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */

+#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 2 : Enable interrupt on RXRDY event. */

+#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */

+#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */

+#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */

+#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */

+#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 1 : Enable interrupt on NCTS event. */

+#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */

+#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */

+#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Interrupt disabled. */

+#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Interrupt enabled. */

+#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Bit 0 : Enable interrupt on CTS event. */

+#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */

+#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */

+#define UART_INTENSET_CTS_Disabled (0UL) /*!< Interrupt disabled. */

+#define UART_INTENSET_CTS_Enabled (1UL) /*!< Interrupt enabled. */

+#define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Register: UART_INTENCLR */

+/* Description: Interrupt enable clear register. */

+

+/* Bit 17 : Disable interrupt on RXTO event. */

+#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */

+#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */

+#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Interrupt disabled. */

+#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Interrupt enabled. */

+#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 9 : Disable interrupt on ERROR event. */

+#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */

+#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */

+#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */

+#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */

+#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 7 : Disable interrupt on TXRDY event. */

+#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */

+#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */

+#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */

+#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */

+#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 2 : Disable interrupt on RXRDY event. */

+#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */

+#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */

+#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */

+#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */

+#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 1 : Disable interrupt on NCTS event. */

+#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */

+#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */

+#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Interrupt disabled. */

+#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Interrupt enabled. */

+#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Bit 0 : Disable interrupt on CTS event. */

+#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */

+#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */

+#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Interrupt disabled. */

+#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Interrupt enabled. */

+#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Register: UART_ERRORSRC */

+/* Description: Error source. Write error field to 1 to clear error. */

+

+/* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */

+#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */

+#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */

+#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Error not present. */

+#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Error present. */

+#define UART_ERRORSRC_BREAK_Clear (1UL) /*!< Clear error on write. */

+

+/* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */

+#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */

+#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */

+#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Error not present. */

+#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Error present. */

+#define UART_ERRORSRC_FRAMING_Clear (1UL) /*!< Clear error on write. */

+

+/* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */

+#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */

+#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */

+#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Error not present. */

+#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Error present. */

+#define UART_ERRORSRC_PARITY_Clear (1UL) /*!< Clear error on write. */

+

+/* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */

+#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */

+#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */

+#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */

+#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */

+#define UART_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */

+

+/* Register: UART_ENABLE */

+/* Description: Enable UART and acquire IOs. */

+

+/* Bits 2..0 : Enable or disable UART and acquire IOs. */

+#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */

+#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */

+#define UART_ENABLE_ENABLE_Disabled (0x00UL) /*!< UART disabled. */

+#define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */

+

+/* Register: UART_RXD */

+/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */

+

+/* Bits 7..0 : RX data from previous transfer. Double buffered. */

+#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */

+#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */

+

+/* Register: UART_TXD */

+/* Description: TXD register. */

+

+/* Bits 7..0 : TX data for transfer. */

+#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */

+#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */

+

+/* Register: UART_BAUDRATE */

+/* Description: UART Baudrate. */

+

+/* Bits 31..0 : UART baudrate. */

+#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */

+#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */

+#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud. */

+#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud. */

+#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud. */

+#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud. */

+#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */

+#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */

+#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */

+#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */

+#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */

+#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud. */

+#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud. */

+#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */

+#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */

+#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */

+#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud. */

+#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */

+

+/* Register: UART_CONFIG */

+/* Description: Configuration of parity and hardware flow control register. */

+

+/* Bits 3..1 : Include parity bit. */

+#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */

+#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */

+#define UART_CONFIG_PARITY_Excluded (0UL) /*!< Parity bit excluded. */

+#define UART_CONFIG_PARITY_Included (7UL) /*!< Parity bit included. */

+

+/* Bit 0 : Hardware flow control. */

+#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */

+#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */

+#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Hardware flow control disabled. */

+#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Hardware flow control enabled. */

+

+/* Register: UART_POWER */

+/* Description: Peripheral power control. */

+

+/* Bit 0 : Peripheral power control. */

+#define UART_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */

+#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /*!< Bit mask of POWER field. */

+#define UART_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */

+#define UART_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */

+

+

+/* Peripheral: UICR */

+/* Description: User Information Configuration. */

+

+/* Register: UICR_RBPCONF */

+/* Description: Readback protection configuration. */

+

+/* Bits 15..8 : Readback protect all code in the device. */

+#define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */

+#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */

+#define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */

+#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */

+

+/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */

+#define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */

+#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */

+#define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */

+#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */

+

+/* Register: UICR_XTALFREQ */

+/* Description: Reset value for CLOCK XTALFREQ register. */

+

+/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */

+#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */

+#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */

+#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */

+#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */

+

+/* Register: UICR_FWID */

+/* Description: Firmware ID. */

+

+/* Bits 15..0 : Identification number for the firmware loaded into the chip. */

+#define UICR_FWID_FWID_Pos (0UL) /*!< Position of FWID field. */

+#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /*!< Bit mask of FWID field. */

+

+

+/* Peripheral: WDT */

+/* Description: Watchdog Timer. */

+

+/* Register: WDT_INTENSET */

+/* Description: Interrupt enable set register. */

+

+/* Bit 0 : Enable interrupt on TIMEOUT event. */

+#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */

+#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */

+#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */

+#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */

+#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */

+

+/* Register: WDT_INTENCLR */

+/* Description: Interrupt enable clear register. */

+

+/* Bit 0 : Disable interrupt on TIMEOUT event. */

+#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */

+#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */

+#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */

+#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */

+#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable interrupt on write. */

+

+/* Register: WDT_RUNSTATUS */

+/* Description: Watchdog running status. */

+

+/* Bit 0 : Watchdog running status. */

+#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */

+#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */

+#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog timer is not running. */

+#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog timer is running. */

+

+/* Register: WDT_REQSTATUS */

+/* Description: Request status. */

+

+/* Bit 7 : Request status for RR[7]. */

+#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */

+#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */

+#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled or has already requested reload. */

+#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled and has not jet requested. */

+

+/* Bit 6 : Request status for RR[6]. */

+#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */

+#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */

+#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled or has already requested reload. */

+#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled and has not jet requested. */

+

+/* Bit 5 : Request status for RR[5]. */

+#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */

+#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */

+#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled or has already requested reload. */

+#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled and has not jet requested. */

+

+/* Bit 4 : Request status for RR[4]. */

+#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */

+#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */

+#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled or has already requested reload. */

+#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled and has not jet requested. */

+

+/* Bit 3 : Request status for RR[3]. */

+#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */

+#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */

+#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled or has already requested reload. */

+#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled and has not jet requested. */

+

+/* Bit 2 : Request status for RR[2]. */

+#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */

+#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */

+#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has already requested reload. */

+#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not jet requested. */

+

+/* Bit 1 : Request status for RR[1]. */

+#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */

+#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */

+#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled or has already requested reload. */

+#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled and has not jet requested. */

+

+/* Bit 0 : Request status for RR[0]. */

+#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */

+#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */

+#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled or has already requested reload. */

+#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled and has not jet requested. */

+

+/* Register: WDT_RREN */

+/* Description: Reload request enable. */

+

+/* Bit 7 : Enable or disable RR[7] register. */

+#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */

+#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */

+#define WDT_RREN_RR7_Disabled (0UL) /*!< RR[7] register is disabled. */

+#define WDT_RREN_RR7_Enabled (1UL) /*!< RR[7] register is enabled. */

+

+/* Bit 6 : Enable or disable RR[6] register. */

+#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */

+#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */

+#define WDT_RREN_RR6_Disabled (0UL) /*!< RR[6] register is disabled. */

+#define WDT_RREN_RR6_Enabled (1UL) /*!< RR[6] register is enabled. */

+

+/* Bit 5 : Enable or disable RR[5] register. */

+#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */

+#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */

+#define WDT_RREN_RR5_Disabled (0UL) /*!< RR[5] register is disabled. */

+#define WDT_RREN_RR5_Enabled (1UL) /*!< RR[5] register is enabled. */

+

+/* Bit 4 : Enable or disable RR[4] register. */

+#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */

+#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */

+#define WDT_RREN_RR4_Disabled (0UL) /*!< RR[4] register is disabled. */

+#define WDT_RREN_RR4_Enabled (1UL) /*!< RR[4] register is enabled. */

+

+/* Bit 3 : Enable or disable RR[3] register. */

+#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */

+#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */

+#define WDT_RREN_RR3_Disabled (0UL) /*!< RR[3] register is disabled. */

+#define WDT_RREN_RR3_Enabled (1UL) /*!< RR[3] register is enabled. */

+

+/* Bit 2 : Enable or disable RR[2] register. */

+#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */

+#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */

+#define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */

+#define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */

+

+/* Bit 1 : Enable or disable RR[1] register. */

+#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */

+#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */

+#define WDT_RREN_RR1_Disabled (0UL) /*!< RR[1] register is disabled. */

+#define WDT_RREN_RR1_Enabled (1UL) /*!< RR[1] register is enabled. */

+

+/* Bit 0 : Enable or disable RR[0] register. */

+#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */

+#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */

+#define WDT_RREN_RR0_Disabled (0UL) /*!< RR[0] register is disabled. */

+#define WDT_RREN_RR0_Enabled (1UL) /*!< RR[0] register is enabled. */

+

+/* Register: WDT_CONFIG */

+/* Description: Configuration register. */

+

+/* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */

+#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */

+#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */

+#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger. */

+#define WDT_CONFIG_HALT_Run (1UL) /*!< Do not pause watchdog while the CPU is halted by the debugger. */

+

+/* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */

+#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */

+#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */

+#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is asleep. */

+#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Do not pause watchdog while the CPU is asleep. */

+

+/* Register: WDT_RR */

+/* Description: Reload requests registers. */

+

+/* Bits 31..0 : Reload register. */

+#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */

+#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */

+#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer. */

+

+/* Register: WDT_POWER */

+/* Description: Peripheral power control. */

+

+/* Bit 0 : Peripheral power control. */

+#define WDT_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */

+#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /*!< Bit mask of POWER field. */

+#define WDT_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */

+#define WDT_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */

+

+

+/*lint --flb "Leave library region" */

+#endif

diff --git a/os/hal/ports/NRF51/NRF51822/nrf51_delay.h b/os/hal/ports/NRF5/NRF51822/nrf_delay.h
index 2a672db..f8668d6 100644
--- a/os/hal/ports/NRF51/NRF51822/nrf51_delay.h
+++ b/os/hal/ports/NRF5/NRF51822/nrf_delay.h
@@ -15,8 +15,8 @@
 */
 
 /**
- * @file    NRF51822/nrf51_delay.h
- * @brief   NRF51822 Delay routines
+ * @file    NRF5/NRF51822/nrf_delay.h
+ * @brief   NRF5 Delay routines
  *
  * @{
  */
@@ -27,7 +27,7 @@
 inline static void nrf_delay_us(uint32_t volatile number_of_us) __attribute__((always_inline));
 inline static void nrf_delay_us(uint32_t volatile number_of_us)
 {
-register uint32_t delay asm ("r0") = number_of_us;
+register uint32_t delay __asm ("r0") = number_of_us;
 __asm volatile (
 ".syntax unified\n"
     "1:\n"
diff --git a/os/hal/ports/NRF5/NRF51822/platform.mk b/os/hal/ports/NRF5/NRF51822/platform.mk
new file mode 100644
index 0000000..7305acf
--- /dev/null
+++ b/os/hal/ports/NRF5/NRF51822/platform.mk
@@ -0,0 +1,66 @@
+ifeq ($(USE_SMART_BUILD),yes)
+HALCONF := $(strip $(shell cat halconf.h halconf_community.h 2>/dev/null | egrep -e "define"))
+
+# List of all the NRF51x platform files.
+PLATFORMSRC  = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_st_lld.c
+
+ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_pal_lld.c
+endif
+ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_serial_lld.c
+endif
+ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_spi_lld.c
+endif
+ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_ext_lld_isr.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_ext_lld.c
+endif
+ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_i2c_lld.c
+endif
+ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_adc_lld.c
+endif
+ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_gpt_lld.c
+endif
+ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_wdg_lld.c
+endif
+ifneq ($(findstring HAL_USE_RNG TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_rng_lld.c
+endif
+ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_pwm_lld.c
+endif
+ifneq ($(findstring HAL_USE_QEI TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_qei_lld.c
+endif
+else
+PLATFORMSRC  = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_pal_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_serial_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_st_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_spi_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_ext_lld_isr.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_ext_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_i2c_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_adc_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_gpt_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_wdg_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_rng_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_pwm_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_qei_lld.c
+endif
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822 
+
+
diff --git a/os/hal/ports/NRF5/NRF52832/hal_lld.c b/os/hal/ports/NRF5/NRF52832/hal_lld.c
new file mode 100644
index 0000000..500de13
--- /dev/null
+++ b/os/hal/ports/NRF5/NRF52832/hal_lld.c
@@ -0,0 +1,80 @@
+/*
+    Copyright (C) 2016 Stephane D'Alu
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    NRF5/NRF52832/hal_lld.c
+ * @brief   NRF52832 HAL Driver subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void)
+{
+  /* High frequency clock initialisation
+   */
+  NRF_CLOCK->TASKS_HFCLKSTOP = 1;
+#if !defined(NRF5_XTAL_VALUE) && (NRF5_XTAL_VALUE != 32000000)
+#error "A 32Mhz crystal is mandatory on nRF52 boards."
+#endif
+
+  
+  /* Low frequency clock initialisation
+   * Clock is only started if st driver requires it
+   */
+  NRF_CLOCK->TASKS_LFCLKSTOP = 1;
+  NRF_CLOCK->LFCLKSRC = NRF5_LFCLK_SOURCE;
+  
+#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) &&			\
+    (NRF5_SYSTEM_TICKS == NRF5_SYSTEM_TICKS_AS_RTC)
+  NRF_CLOCK->TASKS_LFCLKSTART = 1;
+#endif
+}
+
+/**
+ * @}
+ */
diff --git a/os/hal/ports/NRF5/NRF52832/hal_lld.h b/os/hal/ports/NRF5/NRF52832/hal_lld.h
new file mode 100644
index 0000000..24784d3
--- /dev/null
+++ b/os/hal/ports/NRF5/NRF52832/hal_lld.h
@@ -0,0 +1,110 @@
+/*
+    Copyright (C) 2016 Stephane D'Alu
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    NRF5/NRF52832/hal_lld.h
+ * @brief   NRF52832 HAL subsystem low level driver header.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef HAL_LLD_H
+#define HAL_LLD_H
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Platform identification
+ * @{
+ */
+#define PLATFORM_NAME           "Nordic Semiconductor nRF52832"
+
+/**
+ * @name    Chip series
+ */
+#define NRF_SERIES              52
+
+/**
+ * @brief  Frequency value for the Low Frequency Clock
+ */
+#define NRF5_LFCLK_FREQUENCY    32768
+
+/**
+ * @brief  Frequency value for the High Frequency Clock
+ */
+#define NRF5_HFCLK_FREQUENCY    64000000
+
+/**
+ * @}
+ */
+
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Select source of Low Frequency Clock (LFCLK)
+ * @details Possible values for source are:
+ *            0 : RC oscillator
+ *            1 : External cristal
+ *            2 : Synthetized clock from High Frequency Clock (HFCLK)
+ *          When cristal is not available it's preferable to use the
+ *          internal RC oscillator that synthezing the clock.
+ */
+#if !defined(NRF5_LFCLK_SOURCE) || defined(__DOXYGEN__)
+#define NRF5_LFCLK_SOURCE             0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if (NRF5_LFCLK_SOURCE < 0) || (NRF5_LFCLK_SOURCE > 2)
+#error "Possible value for NRF5_LFCLK_SOURCE are 0=RC, 1=XTAL, 2=Synth"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#include "nvic.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void hal_lld_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_LLD_H */
+
+/**
+ * @}
+ */
diff --git a/os/hal/ports/NRF5/NRF52832/nrf52.h b/os/hal/ports/NRF5/NRF52832/nrf52.h
new file mode 100644
index 0000000..1902d33
--- /dev/null
+++ b/os/hal/ports/NRF5/NRF52832/nrf52.h
@@ -0,0 +1,2126 @@
+

+/****************************************************************************************************//**

+ * @file     nrf52.h

+ *

+ * @brief    CMSIS Cortex-M4 Peripheral Access Layer Header File for

+ *           nrf52 from Nordic Semiconductor.

+ *

+ * @version  V1

+ * @date     23. February 2016

+ *

+ * @note     Generated with SVDConv V2.81d 

+ *           from CMSIS SVD File 'nrf52.svd' Version 1,

+ *

+ * @par      Copyright (c) 2015, Nordic Semiconductor ASA

+ *           All rights reserved.

+ *           

+ *           Redistribution and use in source and binary forms, with or without

+ *           modification, are permitted provided that the following conditions are met:

+ *           

+ *           * Redistributions of source code must retain the above copyright notice, this

+ *           list of conditions and the following disclaimer.

+ *           

+ *           * Redistributions in binary form must reproduce the above copyright notice,

+ *           this list of conditions and the following disclaimer in the documentation

+ *           and/or other materials provided with the distribution.

+ *           

+ *           * Neither the name of Nordic Semiconductor ASA nor the names of its

+ *           contributors may be used to endorse or promote products derived from

+ *           this software without specific prior written permission.

+ *           

+ *           THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+ *           AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+ *           IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

+ *           DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE

+ *           FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

+ *           DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

+ *           SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

+ *           CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

+ *           OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

+ *           OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

+ *           

+ *

+ *******************************************************************************************************/

+

+

+

+/** @addtogroup Nordic Semiconductor

+  * @{

+  */

+

+/** @addtogroup nrf52

+  * @{

+  */

+

+#ifndef NRF52_H

+#define NRF52_H

+

+#include "nrf52_bitfields.h"

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+

+/* -------------------------  Interrupt Number Definition  ------------------------ */

+

+typedef enum {

+/* -------------------  Cortex-M4 Processor Exceptions Numbers  ------------------- */

+  Reset_IRQn                    = -15,              /*!<   1  Reset Vector, invoked on Power up and warm reset                 */

+  NonMaskableInt_IRQn           = -14,              /*!<   2  Non maskable Interrupt, cannot be stopped or preempted           */

+  HardFault_IRQn                = -13,              /*!<   3  Hard Fault, all classes of Fault                                 */

+  MemoryManagement_IRQn         = -12,              /*!<   4  Memory Management, MPU mismatch, including Access Violation

+                                                         and No Match                                                          */

+  BusFault_IRQn                 = -11,              /*!<   5  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory

+                                                         related Fault                                                         */

+  UsageFault_IRQn               = -10,              /*!<   6  Usage Fault, i.e. Undef Instruction, Illegal State Transition    */

+  SVCall_IRQn                   =  -5,              /*!<  11  System Service Call via SVC instruction                          */

+  DebugMonitor_IRQn             =  -4,              /*!<  12  Debug Monitor                                                    */

+  PendSV_IRQn                   =  -2,              /*!<  14  Pendable request for system service                              */

+  SysTick_IRQn                  =  -1,              /*!<  15  System Tick Timer                                                */

+/* ----------------------  nrf52 Specific Interrupt Numbers  ---------------------- */

+  POWER_CLOCK_IRQn              =   0,              /*!<   0  POWER_CLOCK                                                      */

+  RADIO_IRQn                    =   1,              /*!<   1  RADIO                                                            */

+  UARTE0_UART0_IRQn             =   2,              /*!<   2  UARTE0_UART0                                                     */

+  SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn=   3,      /*!<   3  SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0                                */

+  SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn=   4,      /*!<   4  SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1                                */

+  NFCT_IRQn                     =   5,              /*!<   5  NFCT                                                             */

+  GPIOTE_IRQn                   =   6,              /*!<   6  GPIOTE                                                           */

+  SAADC_IRQn                    =   7,              /*!<   7  SAADC                                                            */

+  TIMER0_IRQn                   =   8,              /*!<   8  TIMER0                                                           */

+  TIMER1_IRQn                   =   9,              /*!<   9  TIMER1                                                           */

+  TIMER2_IRQn                   =  10,              /*!<  10  TIMER2                                                           */

+  RTC0_IRQn                     =  11,              /*!<  11  RTC0                                                             */

+  TEMP_IRQn                     =  12,              /*!<  12  TEMP                                                             */

+  RNG_IRQn                      =  13,              /*!<  13  RNG                                                              */

+  ECB_IRQn                      =  14,              /*!<  14  ECB                                                              */

+  CCM_AAR_IRQn                  =  15,              /*!<  15  CCM_AAR                                                          */

+  WDT_IRQn                      =  16,              /*!<  16  WDT                                                              */

+  RTC1_IRQn                     =  17,              /*!<  17  RTC1                                                             */

+  QDEC_IRQn                     =  18,              /*!<  18  QDEC                                                             */

+  COMP_LPCOMP_IRQn              =  19,              /*!<  19  COMP_LPCOMP                                                      */

+  SWI0_EGU0_IRQn                =  20,              /*!<  20  SWI0_EGU0                                                        */

+  SWI1_EGU1_IRQn                =  21,              /*!<  21  SWI1_EGU1                                                        */

+  SWI2_EGU2_IRQn                =  22,              /*!<  22  SWI2_EGU2                                                        */

+  SWI3_EGU3_IRQn                =  23,              /*!<  23  SWI3_EGU3                                                        */

+  SWI4_EGU4_IRQn                =  24,              /*!<  24  SWI4_EGU4                                                        */

+  SWI5_EGU5_IRQn                =  25,              /*!<  25  SWI5_EGU5                                                        */

+  TIMER3_IRQn                   =  26,              /*!<  26  TIMER3                                                           */

+  TIMER4_IRQn                   =  27,              /*!<  27  TIMER4                                                           */

+  PWM0_IRQn                     =  28,              /*!<  28  PWM0                                                             */

+  PDM_IRQn                      =  29,              /*!<  29  PDM                                                              */

+  MWU_IRQn                      =  32,              /*!<  32  MWU                                                              */

+  PWM1_IRQn                     =  33,              /*!<  33  PWM1                                                             */

+  PWM2_IRQn                     =  34,              /*!<  34  PWM2                                                             */

+  SPIM2_SPIS2_SPI2_IRQn         =  35,              /*!<  35  SPIM2_SPIS2_SPI2                                                 */

+  RTC2_IRQn                     =  36,              /*!<  36  RTC2                                                             */

+  I2S_IRQn                      =  37,              /*!<  37  I2S                                                              */

+  FPU_IRQn                      =  38               /*!<  38  FPU                                                              */

+} IRQn_Type;

+

+

+/** @addtogroup Configuration_of_CMSIS

+  * @{

+  */

+

+

+/* ================================================================================ */

+/* ================      Processor and Core Peripheral Section     ================ */

+/* ================================================================================ */

+

+/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */

+#define __CM4_REV                 0x0001            /*!< Cortex-M4 Core Revision                                               */

+#define __MPU_PRESENT                  1            /*!< MPU present or not                                                    */

+#define __NVIC_PRIO_BITS               3            /*!< Number of Bits used for Priority Levels                               */

+#define __Vendor_SysTickConfig         0            /*!< Set to 1 if different SysTick Config is used                          */

+#define __FPU_PRESENT                  1            /*!< FPU present or not                                                    */

+/** @} */ /* End of group Configuration_of_CMSIS */

+

+#include "core_cm4.h"                               /*!< Cortex-M4 processor and core peripherals                              */

+

+

+/* ================================================================================ */

+/* ================       Device Specific Peripheral Section       ================ */

+/* ================================================================================ */

+

+

+/** @addtogroup Device_Peripheral_Registers

+  * @{

+  */

+

+

+/* -------------------  Start of section using anonymous unions  ------------------ */

+#if defined(__CC_ARM)

+  #pragma push

+  #pragma anon_unions

+#elif defined(__ICCARM__)

+  #pragma language=extended

+#elif defined(__GNUC__)

+  /* anonymous unions are enabled by default */

+#elif defined(__TMS470__)

+/* anonymous unions are enabled by default */

+#elif defined(__TASKING__)

+  #pragma warning 586

+#else

+  #warning Not supported compiler type

+#endif

+

+

+typedef struct {

+  __I  uint32_t  PART;                              /*!< Part code                                                             */

+  __I  uint32_t  VARIANT;                           /*!< Part Variant, Hardware version and Production configuration           */

+  __I  uint32_t  PACKAGE;                           /*!< Package option                                                        */

+  __I  uint32_t  RAM;                               /*!< RAM variant                                                           */

+  __I  uint32_t  FLASH;                             /*!< Flash variant                                                         */

+  __IO uint32_t  UNUSED0[3];                        /*!< Description collection[0]: Unspecified                                */

+} FICR_INFO_Type;

+

+typedef struct {

+  __I  uint32_t  A0;                                /*!< Slope definition A0.                                                  */

+  __I  uint32_t  A1;                                /*!< Slope definition A1.                                                  */

+  __I  uint32_t  A2;                                /*!< Slope definition A2.                                                  */

+  __I  uint32_t  A3;                                /*!< Slope definition A3.                                                  */

+  __I  uint32_t  A4;                                /*!< Slope definition A4.                                                  */

+  __I  uint32_t  A5;                                /*!< Slope definition A5.                                                  */

+  __I  uint32_t  B0;                                /*!< y-intercept B0.                                                       */

+  __I  uint32_t  B1;                                /*!< y-intercept B1.                                                       */

+  __I  uint32_t  B2;                                /*!< y-intercept B2.                                                       */

+  __I  uint32_t  B3;                                /*!< y-intercept B3.                                                       */

+  __I  uint32_t  B4;                                /*!< y-intercept B4.                                                       */

+  __I  uint32_t  B5;                                /*!< y-intercept B5.                                                       */

+  __I  uint32_t  T0;                                /*!< Segment end T0.                                                       */

+  __I  uint32_t  T1;                                /*!< Segment end T1.                                                       */

+  __I  uint32_t  T2;                                /*!< Segment end T2.                                                       */

+  __I  uint32_t  T3;                                /*!< Segment end T3.                                                       */

+  __I  uint32_t  T4;                                /*!< Segment end T4.                                                       */

+} FICR_TEMP_Type;

+

+typedef struct {

+  __I  uint32_t  TAGHEADER0;                        /*!< Default header for NFC Tag. Software can read these values to

+                                                         populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.            */

+  __I  uint32_t  TAGHEADER1;                        /*!< Default header for NFC Tag. Software can read these values to

+                                                         populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.            */

+  __I  uint32_t  TAGHEADER2;                        /*!< Default header for NFC Tag. Software can read these values to

+                                                         populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.            */

+  __I  uint32_t  TAGHEADER3;                        /*!< Default header for NFC Tag. Software can read these values to

+                                                         populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.            */

+} FICR_NFC_Type;

+

+typedef struct {

+  __IO uint32_t  POWER;                             /*!< Description cluster[0]: RAM0 power control register                   */

+  __O  uint32_t  POWERSET;                          /*!< Description cluster[0]: RAM0 power control set register               */

+  __O  uint32_t  POWERCLR;                          /*!< Description cluster[0]: RAM0 power control clear register             */

+  __I  uint32_t  RESERVED0;

+} POWER_RAM_Type;

+

+typedef struct {

+  __IO uint32_t  CPU0;                              /*!< AHB bus master priority register for CPU0                             */

+  __IO uint32_t  SPIS1;                             /*!< AHB bus master priority register for SPIM1, SPIS1, TWIM1 and

+                                                         TWIS1                                                                 */

+  __IO uint32_t  RADIO;                             /*!< AHB bus master priority register for RADIO                            */

+  __IO uint32_t  ECB;                               /*!< AHB bus master priority register for ECB                              */

+  __IO uint32_t  CCM;                               /*!< AHB bus master priority register for CCM                              */

+  __IO uint32_t  AAR;                               /*!< AHB bus master priority register for AAR                              */

+  __IO uint32_t  SAADC;                             /*!< AHB bus master priority register for SAADC                            */

+  __IO uint32_t  UARTE;                             /*!< AHB bus master priority register for UARTE                            */

+  __IO uint32_t  SERIAL0;                           /*!< AHB bus master priority register for SPIM0, SPIS0, TWIM0 and

+                                                         TWIS0                                                                 */

+  __IO uint32_t  SERIAL2;                           /*!< AHB bus master priority register for SPIM2 and SPIS2                  */

+  __IO uint32_t  NFCT;                              /*!< AHB bus master priority register for NFCT                             */

+  __IO uint32_t  I2S;                               /*!< AHB bus master priority register for I2S                              */

+  __IO uint32_t  PDM;                               /*!< AHB bus master priority register for PDM                              */

+  __IO uint32_t  PWM;                               /*!< AHB bus master priority register for PWM0, PWM1 and PWM2              */

+} AMLI_RAMPRI_Type;

+

+typedef struct {

+  __IO uint32_t  RTS;                               /*!< Pin select for RTS signal                                             */

+  __IO uint32_t  TXD;                               /*!< Pin select for TXD signal                                             */

+  __IO uint32_t  CTS;                               /*!< Pin select for CTS signal                                             */

+  __IO uint32_t  RXD;                               /*!< Pin select for RXD signal                                             */

+} UARTE_PSEL_Type;

+

+typedef struct {

+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */

+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in receive buffer                             */

+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */

+} UARTE_RXD_Type;

+

+typedef struct {

+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */

+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in transmit buffer                            */

+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */

+} UARTE_TXD_Type;

+

+typedef struct {

+  __IO uint32_t  SCK;                               /*!< Pin select for SCK                                                    */

+  __IO uint32_t  MOSI;                              /*!< Pin select for MOSI signal                                            */

+  __IO uint32_t  MISO;                              /*!< Pin select for MISO signal                                            */

+} SPIM_PSEL_Type;

+

+typedef struct {

+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */

+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in receive buffer                             */

+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */

+  __IO uint32_t  LIST;                              /*!< EasyDMA list type                                                     */

+} SPIM_RXD_Type;

+

+typedef struct {

+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */

+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in transmit buffer                            */

+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */

+  __IO uint32_t  LIST;                              /*!< EasyDMA list type                                                     */

+} SPIM_TXD_Type;

+

+typedef struct {

+  __IO uint32_t  SCK;                               /*!< Pin select for SCK                                                    */

+  __IO uint32_t  MISO;                              /*!< Pin select for MISO signal                                            */

+  __IO uint32_t  MOSI;                              /*!< Pin select for MOSI signal                                            */

+  __IO uint32_t  CSN;                               /*!< Pin select for CSN signal                                             */

+} SPIS_PSEL_Type;

+

+typedef struct {

+  __IO uint32_t  PTR;                               /*!< RXD data pointer                                                      */

+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in receive buffer                             */

+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes received in last granted transaction                  */

+} SPIS_RXD_Type;

+

+typedef struct {

+  __IO uint32_t  PTR;                               /*!< TXD data pointer                                                      */

+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in transmit buffer                            */

+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transmitted in last granted transaction               */

+} SPIS_TXD_Type;

+

+typedef struct {

+  __IO uint32_t  SCL;                               /*!< Pin select for SCL signal                                             */

+  __IO uint32_t  SDA;                               /*!< Pin select for SDA signal                                             */

+} TWIM_PSEL_Type;

+

+typedef struct {

+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */

+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in receive buffer                             */

+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */

+  __IO uint32_t  LIST;                              /*!< EasyDMA list type                                                     */

+} TWIM_RXD_Type;

+

+typedef struct {

+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */

+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in transmit buffer                            */

+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */

+  __IO uint32_t  LIST;                              /*!< EasyDMA list type                                                     */

+} TWIM_TXD_Type;

+

+typedef struct {

+  __IO uint32_t  SCL;                               /*!< Pin select for SCL signal                                             */

+  __IO uint32_t  SDA;                               /*!< Pin select for SDA signal                                             */

+} TWIS_PSEL_Type;

+

+typedef struct {

+  __IO uint32_t  PTR;                               /*!< RXD Data pointer                                                      */

+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in RXD buffer                                 */

+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last RXD transaction               */

+} TWIS_RXD_Type;

+

+typedef struct {

+  __IO uint32_t  PTR;                               /*!< TXD Data pointer                                                      */

+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in TXD buffer                                 */

+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last TXD transaction               */

+} TWIS_TXD_Type;

+

+typedef struct {

+  __IO uint32_t  SCK;                               /*!< Pin select for SCK                                                    */

+  __IO uint32_t  MOSI;                              /*!< Pin select for MOSI                                                   */

+  __IO uint32_t  MISO;                              /*!< Pin select for MISO                                                   */

+} SPI_PSEL_Type;

+

+typedef struct {

+  __IO uint32_t  RX;                                /*!< Result of last incoming frames                                        */

+} NFCT_FRAMESTATUS_Type;

+

+typedef struct {

+  __IO uint32_t  FRAMECONFIG;                       /*!< Configuration of outgoing frames                                      */

+  __IO uint32_t  AMOUNT;                            /*!< Size of outgoing frame                                                */

+} NFCT_TXD_Type;

+

+typedef struct {

+  __IO uint32_t  FRAMECONFIG;                       /*!< Configuration of incoming frames                                      */

+  __I  uint32_t  AMOUNT;                            /*!< Size of last incoming frame                                           */

+} NFCT_RXD_Type;

+

+typedef struct {

+  __IO uint32_t  LIMITH;                            /*!< Description cluster[0]: Last results is equal or above CH[0].LIMIT.HIGH */

+  __IO uint32_t  LIMITL;                            /*!< Description cluster[0]: Last results is equal or below CH[0].LIMIT.LOW */

+} SAADC_EVENTS_CH_Type;

+

+typedef struct {

+  __IO uint32_t  PSELP;                             /*!< Description cluster[0]: Input positive pin selection for CH[0]        */

+  __IO uint32_t  PSELN;                             /*!< Description cluster[0]: Input negative pin selection for CH[0]        */

+  __IO uint32_t  CONFIG;                            /*!< Description cluster[0]: Input configuration for CH[0]                 */

+  __IO uint32_t  LIMIT;                             /*!< Description cluster[0]: High/low limits for event monitoring

+                                                         a channel                                                             */

+} SAADC_CH_Type;

+

+typedef struct {

+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */

+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of buffer words to transfer                            */

+  __I  uint32_t  AMOUNT;                            /*!< Number of buffer words transferred since last START                   */

+} SAADC_RESULT_Type;

+

+typedef struct {

+  __IO uint32_t  LED;                               /*!< Pin select for LED signal                                             */

+  __IO uint32_t  A;                                 /*!< Pin select for A signal                                               */

+  __IO uint32_t  B;                                 /*!< Pin select for B signal                                               */

+} QDEC_PSEL_Type;

+

+typedef struct {

+  __IO uint32_t  PTR;                               /*!< Description cluster[0]: Beginning address in Data RAM of sequence

+                                                         A                                                                     */

+  __IO uint32_t  CNT;                               /*!< Description cluster[0]: Amount of values (duty cycles) in sequence

+                                                         A                                                                     */

+  __IO uint32_t  REFRESH;                           /*!< Description cluster[0]: Amount of additional PWM periods between

+                                                         samples loaded to compare register (load every CNT+1 PWM periods)     */

+  __IO uint32_t  ENDDELAY;                          /*!< Description cluster[0]: Time added after the sequence                 */

+  __I  uint32_t  RESERVED1[4];

+} PWM_SEQ_Type;

+

+typedef struct {

+  __IO uint32_t  OUT[4];                            /*!< Description collection[0]: Output pin select for PWM channel

+                                                         0                                                                     */

+} PWM_PSEL_Type;

+

+typedef struct {

+  __IO uint32_t  CLK;                               /*!< Pin number configuration for PDM CLK signal                           */

+  __IO uint32_t  DIN;                               /*!< Pin number configuration for PDM DIN signal                           */

+} PDM_PSEL_Type;

+

+typedef struct {

+  __IO uint32_t  PTR;                               /*!< RAM address pointer to write samples to with EasyDMA                  */

+  __IO uint32_t  MAXCNT;                            /*!< Number of samples to allocate memory for in EasyDMA mode              */

+} PDM_SAMPLE_Type;

+

+typedef struct {

+  __O  uint32_t  EN;                                /*!< Description cluster[0]: Enable channel group 0                        */

+  __O  uint32_t  DIS;                               /*!< Description cluster[0]: Disable channel group 0                       */

+} PPI_TASKS_CHG_Type;

+

+typedef struct {

+  __IO uint32_t  EEP;                               /*!< Description cluster[0]: Channel 0 event end-point                     */

+  __IO uint32_t  TEP;                               /*!< Description cluster[0]: Channel 0 task end-point                      */

+} PPI_CH_Type;

+

+typedef struct {

+  __IO uint32_t  TEP;                               /*!< Description cluster[0]: Channel 0 task end-point                      */

+} PPI_FORK_Type;

+

+typedef struct {

+  __IO uint32_t  WA;                                /*!< Description cluster[0]: Write access to region 0 detected             */

+  __IO uint32_t  RA;                                /*!< Description cluster[0]: Read access to region 0 detected              */

+} MWU_EVENTS_REGION_Type;

+

+typedef struct {

+  __IO uint32_t  WA;                                /*!< Description cluster[0]: Write access to peripheral region 0

+                                                         detected                                                              */

+  __IO uint32_t  RA;                                /*!< Description cluster[0]: Read access to peripheral region 0 detected   */

+} MWU_EVENTS_PREGION_Type;

+

+typedef struct {

+  __IO uint32_t  SUBSTATWA;                         /*!< Description cluster[0]: Source of event/interrupt in region

+                                                         0, write access detected while corresponding subregion was enabled

+                                                          for watching                                                         */

+  __IO uint32_t  SUBSTATRA;                         /*!< Description cluster[0]: Source of event/interrupt in region

+                                                         0, read access detected while corresponding subregion was enabled

+                                                          for watching                                                         */

+} MWU_PERREGION_Type;

+

+typedef struct {

+  __IO uint32_t  START;                             /*!< Description cluster[0]: Start address for region 0                    */

+  __IO uint32_t  END;                               /*!< Description cluster[0]: End address of region 0                       */

+  __I  uint32_t  RESERVED2[2];

+} MWU_REGION_Type;

+

+typedef struct {

+  __I  uint32_t  START;                             /*!< Description cluster[0]: Reserved for future use                       */

+  __I  uint32_t  END;                               /*!< Description cluster[0]: Reserved for future use                       */

+  __IO uint32_t  SUBS;                              /*!< Description cluster[0]: Subregions of region 0                        */

+  __I  uint32_t  RESERVED3;

+} MWU_PREGION_Type;

+

+typedef struct {

+  __IO uint32_t  MODE;                              /*!< I2S mode.                                                             */

+  __IO uint32_t  RXEN;                              /*!< Reception (RX) enable.                                                */

+  __IO uint32_t  TXEN;                              /*!< Transmission (TX) enable.                                             */

+  __IO uint32_t  MCKEN;                             /*!< Master clock generator enable.                                        */

+  __IO uint32_t  MCKFREQ;                           /*!< Master clock generator frequency.                                     */

+  __IO uint32_t  RATIO;                             /*!< MCK / LRCK ratio.                                                     */

+  __IO uint32_t  SWIDTH;                            /*!< Sample width.                                                         */

+  __IO uint32_t  ALIGN;                             /*!< Alignment of sample within a frame.                                   */

+  __IO uint32_t  FORMAT;                            /*!< Frame format.                                                         */

+  __IO uint32_t  CHANNELS;                          /*!< Enable channels.                                                      */

+} I2S_CONFIG_Type;

+

+typedef struct {

+  __IO uint32_t  PTR;                               /*!< Receive buffer RAM start address.                                     */

+} I2S_RXD_Type;

+

+typedef struct {

+  __IO uint32_t  PTR;                               /*!< Transmit buffer RAM start address.                                    */

+} I2S_TXD_Type;

+

+typedef struct {

+  __IO uint32_t  MAXCNT;                            /*!< Size of RXD and TXD buffers.                                          */

+} I2S_RXTXD_Type;

+

+typedef struct {

+  __IO uint32_t  MCK;                               /*!< Pin select for MCK signal.                                            */

+  __IO uint32_t  SCK;                               /*!< Pin select for SCK signal.                                            */

+  __IO uint32_t  LRCK;                              /*!< Pin select for LRCK signal.                                           */

+  __IO uint32_t  SDIN;                              /*!< Pin select for SDIN signal.                                           */

+  __IO uint32_t  SDOUT;                             /*!< Pin select for SDOUT signal.                                          */

+} I2S_PSEL_Type;

+

+

+/* ================================================================================ */

+/* ================                      FICR                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief Factory Information Configuration Registers (FICR)

+  */

+

+typedef struct {                                    /*!< FICR Structure                                                        */

+  __I  uint32_t  RESERVED0[4];

+  __I  uint32_t  CODEPAGESIZE;                      /*!< Code memory page size                                                 */

+  __I  uint32_t  CODESIZE;                          /*!< Code memory size                                                      */

+  __I  uint32_t  RESERVED1[18];

+  __I  uint32_t  DEVICEID[2];                       /*!< Description collection[0]: Device identifier                          */

+  __I  uint32_t  RESERVED2[6];

+  __I  uint32_t  ER[4];                             /*!< Description collection[0]: Encryption Root, word 0                    */

+  __I  uint32_t  IR[4];                             /*!< Description collection[0]: Identity Root, word 0                      */

+  __I  uint32_t  DEVICEADDRTYPE;                    /*!< Device address type                                                   */

+  __I  uint32_t  DEVICEADDR[2];                     /*!< Description collection[0]: Device address 0                           */

+  __I  uint32_t  RESERVED3[21];

+  FICR_INFO_Type INFO;                              /*!< Device info                                                           */

+  __I  uint32_t  RESERVED4[185];

+  FICR_TEMP_Type TEMP;                              /*!< Registers storing factory TEMP module linearization coefficients      */

+  __I  uint32_t  RESERVED5[2];

+  FICR_NFC_Type NFC;                                /*!< Unspecified                                                           */

+} NRF_FICR_Type;

+

+

+/* ================================================================================ */

+/* ================                      UICR                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief User Information Configuration Registers (UICR)

+  */

+

+typedef struct {                                    /*!< UICR Structure                                                        */

+  __IO uint32_t  UNUSED0;                           /*!< Unspecified                                                           */

+  __IO uint32_t  UNUSED1;                           /*!< Unspecified                                                           */

+  __IO uint32_t  UNUSED2;                           /*!< Unspecified                                                           */

+  __I  uint32_t  RESERVED0;

+  __IO uint32_t  UNUSED3;                           /*!< Unspecified                                                           */

+  __IO uint32_t  NRFFW[15];                         /*!< Description collection[0]: Reserved for Nordic firmware design        */

+  __IO uint32_t  NRFHW[12];                         /*!< Description collection[0]: Reserved for Nordic hardware design        */

+  __IO uint32_t  CUSTOMER[32];                      /*!< Description collection[0]: Reserved for customer                      */

+  __I  uint32_t  RESERVED1[64];

+  __IO uint32_t  PSELRESET[2];                      /*!< Description collection[0]: Mapping of the nRESET function (see

+                                                         POWER chapter for details)                                            */

+  __IO uint32_t  APPROTECT;                         /*!< Access Port protection                                                */

+  __IO uint32_t  NFCPINS;                           /*!< Setting of pins dedicated to NFC functionality: NFC antenna

+                                                         or GPIO                                                               */

+} NRF_UICR_Type;

+

+

+/* ================================================================================ */

+/* ================                      BPROT                     ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief Block Protect (BPROT)

+  */

+

+typedef struct {                                    /*!< BPROT Structure                                                       */

+  __I  uint32_t  RESERVED0[384];

+  __IO uint32_t  CONFIG0;                           /*!< Block protect configuration register 0                                */

+  __IO uint32_t  CONFIG1;                           /*!< Block protect configuration register 1                                */

+  __IO uint32_t  DISABLEINDEBUG;                    /*!< Disable protection mechanism in debug interface mode                  */

+  __IO uint32_t  UNUSED0;                           /*!< Unspecified                                                           */

+  __IO uint32_t  CONFIG2;                           /*!< Block protect configuration register 2                                */

+  __IO uint32_t  CONFIG3;                           /*!< Block protect configuration register 3                                */

+} NRF_BPROT_Type;

+

+

+/* ================================================================================ */

+/* ================                      POWER                     ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief Power control (POWER)

+  */

+

+typedef struct {                                    /*!< POWER Structure                                                       */

+  __I  uint32_t  RESERVED0[30];

+  __O  uint32_t  TASKS_CONSTLAT;                    /*!< Enable constant latency mode                                          */

+  __O  uint32_t  TASKS_LOWPWR;                      /*!< Enable low power mode (variable latency)                              */

+  __I  uint32_t  RESERVED1[34];

+  __IO uint32_t  EVENTS_POFWARN;                    /*!< Power failure warning                                                 */

+  __I  uint32_t  RESERVED2[2];

+  __IO uint32_t  EVENTS_SLEEPENTER;                 /*!< CPU entered WFI/WFE sleep                                             */

+  __IO uint32_t  EVENTS_SLEEPEXIT;                  /*!< CPU exited WFI/WFE sleep                                              */

+  __I  uint32_t  RESERVED3[122];

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED4[61];

+  __IO uint32_t  RESETREAS;                         /*!< Reset reason                                                          */

+  __I  uint32_t  RESERVED5[9];

+  __I  uint32_t  RAMSTATUS;                         /*!< Deprecated register - RAM status register                             */

+  __I  uint32_t  RESERVED6[53];

+  __O  uint32_t  SYSTEMOFF;                         /*!< System OFF register                                                   */

+  __I  uint32_t  RESERVED7[3];

+  __IO uint32_t  POFCON;                            /*!< Power failure comparator configuration                                */

+  __I  uint32_t  RESERVED8[2];

+  __IO uint32_t  GPREGRET;                          /*!< General purpose retention register                                    */

+  __IO uint32_t  GPREGRET2;                         /*!< General purpose retention register                                    */

+  __IO uint32_t  RAMON;                             /*!< Deprecated register - RAM on/off register (this register is

+                                                         retained)                                                             */

+  __I  uint32_t  RESERVED9[11];

+  __IO uint32_t  RAMONB;                            /*!< Deprecated register - RAM on/off register (this register is

+                                                         retained)                                                             */

+  __I  uint32_t  RESERVED10[8];

+  __IO uint32_t  DCDCEN;                            /*!< DC/DC enable register                                                 */

+  __I  uint32_t  RESERVED11[225];

+  POWER_RAM_Type RAM[8];                            /*!< Unspecified                                                           */

+} NRF_POWER_Type;

+

+

+/* ================================================================================ */

+/* ================                      CLOCK                     ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief Clock control (CLOCK)

+  */

+

+typedef struct {                                    /*!< CLOCK Structure                                                       */

+  __O  uint32_t  TASKS_HFCLKSTART;                  /*!< Start HFCLK crystal oscillator                                        */

+  __O  uint32_t  TASKS_HFCLKSTOP;                   /*!< Stop HFCLK crystal oscillator                                         */

+  __O  uint32_t  TASKS_LFCLKSTART;                  /*!< Start LFCLK source                                                    */

+  __O  uint32_t  TASKS_LFCLKSTOP;                   /*!< Stop LFCLK source                                                     */

+  __O  uint32_t  TASKS_CAL;                         /*!< Start calibration of LFRC oscillator                                  */

+  __O  uint32_t  TASKS_CTSTART;                     /*!< Start calibration timer                                               */

+  __O  uint32_t  TASKS_CTSTOP;                      /*!< Stop calibration timer                                                */

+  __I  uint32_t  RESERVED0[57];

+  __IO uint32_t  EVENTS_HFCLKSTARTED;               /*!< HFCLK oscillator started                                              */

+  __IO uint32_t  EVENTS_LFCLKSTARTED;               /*!< LFCLK started                                                         */

+  __I  uint32_t  RESERVED1;

+  __IO uint32_t  EVENTS_DONE;                       /*!< Calibration of LFCLK RC oscillator complete event                     */

+  __IO uint32_t  EVENTS_CTTO;                       /*!< Calibration timer timeout                                             */

+  __I  uint32_t  RESERVED2[124];

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED3[63];

+  __I  uint32_t  HFCLKRUN;                          /*!< Status indicating that HFCLKSTART task has been triggered             */

+  __I  uint32_t  HFCLKSTAT;                         /*!< HFCLK status                                                          */

+  __I  uint32_t  RESERVED4;

+  __I  uint32_t  LFCLKRUN;                          /*!< Status indicating that LFCLKSTART task has been triggered             */

+  __I  uint32_t  LFCLKSTAT;                         /*!< LFCLK status                                                          */

+  __I  uint32_t  LFCLKSRCCOPY;                      /*!< Copy of LFCLKSRC register, set when LFCLKSTART task was triggered     */

+  __I  uint32_t  RESERVED5[62];

+  __IO uint32_t  LFCLKSRC;                          /*!< Clock source for the LFCLK                                            */

+  __I  uint32_t  RESERVED6[7];

+  __IO uint32_t  CTIV;                              /*!< Calibration timer interval (retained register, same reset behaviour

+                                                         as RESETREAS)                                                         */

+  __I  uint32_t  RESERVED7[8];

+  __IO uint32_t  TRACECONFIG;                       /*!< Clocking options for the Trace Port debug interface                   */

+} NRF_CLOCK_Type;

+

+

+/* ================================================================================ */

+/* ================                      AMLI                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief AHB Multi-Layer Interface (AMLI)

+  */

+

+typedef struct {                                    /*!< AMLI Structure                                                        */

+  __I  uint32_t  RESERVED0[896];

+  AMLI_RAMPRI_Type RAMPRI;                          /*!< RAM configurable priority configuration structure                     */

+} NRF_AMLI_Type;

+

+

+/* ================================================================================ */

+/* ================                      RADIO                     ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief 2.4 GHz Radio (RADIO)

+  */

+

+typedef struct {                                    /*!< RADIO Structure                                                       */

+  __O  uint32_t  TASKS_TXEN;                        /*!< Enable RADIO in TX mode                                               */

+  __O  uint32_t  TASKS_RXEN;                        /*!< Enable RADIO in RX mode                                               */

+  __O  uint32_t  TASKS_START;                       /*!< Start RADIO                                                           */

+  __O  uint32_t  TASKS_STOP;                        /*!< Stop RADIO                                                            */

+  __O  uint32_t  TASKS_DISABLE;                     /*!< Disable RADIO                                                         */

+  __O  uint32_t  TASKS_RSSISTART;                   /*!< Start the RSSI and take one single sample of the receive signal

+                                                         strength.                                                             */

+  __O  uint32_t  TASKS_RSSISTOP;                    /*!< Stop the RSSI measurement                                             */

+  __O  uint32_t  TASKS_BCSTART;                     /*!< Start the bit counter                                                 */

+  __O  uint32_t  TASKS_BCSTOP;                      /*!< Stop the bit counter                                                  */

+  __I  uint32_t  RESERVED0[55];

+  __IO uint32_t  EVENTS_READY;                      /*!< RADIO has ramped up and is ready to be started                        */

+  __IO uint32_t  EVENTS_ADDRESS;                    /*!< Address sent or received                                              */

+  __IO uint32_t  EVENTS_PAYLOAD;                    /*!< Packet payload sent or received                                       */

+  __IO uint32_t  EVENTS_END;                        /*!< Packet sent or received                                               */

+  __IO uint32_t  EVENTS_DISABLED;                   /*!< RADIO has been disabled                                               */

+  __IO uint32_t  EVENTS_DEVMATCH;                   /*!< A device address match occurred on the last received packet           */

+  __IO uint32_t  EVENTS_DEVMISS;                    /*!< No device address match occurred on the last received packet          */

+  __IO uint32_t  EVENTS_RSSIEND;                    /*!< Sampling of receive signal strength complete.                         */

+  __I  uint32_t  RESERVED1[2];

+  __IO uint32_t  EVENTS_BCMATCH;                    /*!< Bit counter reached bit count value.                                  */

+  __I  uint32_t  RESERVED2;

+  __IO uint32_t  EVENTS_CRCOK;                      /*!< Packet received with CRC ok                                           */

+  __IO uint32_t  EVENTS_CRCERROR;                   /*!< Packet received with CRC error                                        */

+  __I  uint32_t  RESERVED3[50];

+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */

+  __I  uint32_t  RESERVED4[64];

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED5[61];

+  __I  uint32_t  CRCSTATUS;                         /*!< CRC status                                                            */

+  __I  uint32_t  RESERVED6;

+  __I  uint32_t  RXMATCH;                           /*!< Received address                                                      */

+  __I  uint32_t  RXCRC;                             /*!< CRC field of previously received packet                               */

+  __I  uint32_t  DAI;                               /*!< Device address match index                                            */

+  __I  uint32_t  RESERVED7[60];

+  __IO uint32_t  PACKETPTR;                         /*!< Packet pointer                                                        */

+  __IO uint32_t  FREQUENCY;                         /*!< Frequency                                                             */

+  __IO uint32_t  TXPOWER;                           /*!< Output power                                                          */

+  __IO uint32_t  MODE;                              /*!< Data rate and modulation                                              */

+  __IO uint32_t  PCNF0;                             /*!< Packet configuration register 0                                       */

+  __IO uint32_t  PCNF1;                             /*!< Packet configuration register 1                                       */

+  __IO uint32_t  BASE0;                             /*!< Base address 0                                                        */

+  __IO uint32_t  BASE1;                             /*!< Base address 1                                                        */

+  __IO uint32_t  PREFIX0;                           /*!< Prefixes bytes for logical addresses 0-3                              */

+  __IO uint32_t  PREFIX1;                           /*!< Prefixes bytes for logical addresses 4-7                              */

+  __IO uint32_t  TXADDRESS;                         /*!< Transmit address select                                               */

+  __IO uint32_t  RXADDRESSES;                       /*!< Receive address select                                                */

+  __IO uint32_t  CRCCNF;                            /*!< CRC configuration                                                     */

+  __IO uint32_t  CRCPOLY;                           /*!< CRC polynomial                                                        */

+  __IO uint32_t  CRCINIT;                           /*!< CRC initial value                                                     */

+  __IO uint32_t  UNUSED0;                           /*!< Unspecified                                                           */

+  __IO uint32_t  TIFS;                              /*!< Inter Frame Spacing in us                                             */

+  __I  uint32_t  RSSISAMPLE;                        /*!< RSSI sample                                                           */

+  __I  uint32_t  RESERVED8;

+  __I  uint32_t  STATE;                             /*!< Current radio state                                                   */

+  __IO uint32_t  DATAWHITEIV;                       /*!< Data whitening initial value                                          */

+  __I  uint32_t  RESERVED9[2];

+  __IO uint32_t  BCC;                               /*!< Bit counter compare                                                   */

+  __I  uint32_t  RESERVED10[39];

+  __IO uint32_t  DAB[8];                            /*!< Description collection[0]: Device address base segment 0              */

+  __IO uint32_t  DAP[8];                            /*!< Description collection[0]: Device address prefix 0                    */

+  __IO uint32_t  DACNF;                             /*!< Device address match configuration                                    */

+  __I  uint32_t  RESERVED11[3];

+  __IO uint32_t  MODECNF0;                          /*!< Radio mode configuration register 0                                   */

+  __I  uint32_t  RESERVED12[618];

+  __IO uint32_t  POWER;                             /*!< Peripheral power control                                              */

+} NRF_RADIO_Type;

+

+

+/* ================================================================================ */

+/* ================                      UARTE                     ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief UART with EasyDMA (UARTE)

+  */

+

+typedef struct {                                    /*!< UARTE Structure                                                       */

+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start UART receiver                                                   */

+  __O  uint32_t  TASKS_STOPRX;                      /*!< Stop UART receiver                                                    */

+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start UART transmitter                                                */

+  __O  uint32_t  TASKS_STOPTX;                      /*!< Stop UART transmitter                                                 */

+  __I  uint32_t  RESERVED0[7];

+  __O  uint32_t  TASKS_FLUSHRX;                     /*!< Flush RX FIFO into RX buffer                                          */

+  __I  uint32_t  RESERVED1[52];

+  __IO uint32_t  EVENTS_CTS;                        /*!< CTS is activated (set low). Clear To Send.                            */

+  __IO uint32_t  EVENTS_NCTS;                       /*!< CTS is deactivated (set high). Not Clear To Send.                     */

+  __I  uint32_t  RESERVED2[2];

+  __IO uint32_t  EVENTS_ENDRX;                      /*!< Receive buffer is filled up                                           */

+  __I  uint32_t  RESERVED3[3];

+  __IO uint32_t  EVENTS_ENDTX;                      /*!< Last TX byte transmitted                                              */

+  __IO uint32_t  EVENTS_ERROR;                      /*!< Error detected                                                        */

+  __I  uint32_t  RESERVED4[7];

+  __IO uint32_t  EVENTS_RXTO;                       /*!< Receiver timeout                                                      */

+  __I  uint32_t  RESERVED5;

+  __IO uint32_t  EVENTS_RXSTARTED;                  /*!< UART receiver has started                                             */

+  __IO uint32_t  EVENTS_TXSTARTED;                  /*!< UART transmitter has started                                          */

+  __I  uint32_t  RESERVED6;

+  __IO uint32_t  EVENTS_TXSTOPPED;                  /*!< Transmitter stopped                                                   */

+  __I  uint32_t  RESERVED7[41];

+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */

+  __I  uint32_t  RESERVED8[63];

+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED9[93];

+  __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */

+  __I  uint32_t  RESERVED10[31];

+  __IO uint32_t  ENABLE;                            /*!< Enable UART                                                           */

+  __I  uint32_t  RESERVED11;

+  UARTE_PSEL_Type PSEL;                             /*!< Unspecified                                                           */

+  __I  uint32_t  RESERVED12[3];

+  __IO uint32_t  BAUDRATE;                          /*!< Baud rate                                                             */

+  __I  uint32_t  RESERVED13[3];

+  UARTE_RXD_Type RXD;                               /*!< RXD EasyDMA channel                                                   */

+  __I  uint32_t  RESERVED14;

+  UARTE_TXD_Type TXD;                               /*!< TXD EasyDMA channel                                                   */

+  __I  uint32_t  RESERVED15[7];

+  __IO uint32_t  CONFIG;                            /*!< Configuration of parity and hardware flow control                     */

+} NRF_UARTE_Type;

+

+

+/* ================================================================================ */

+/* ================                      UART                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief Universal Asynchronous Receiver/Transmitter (UART)

+  */

+

+typedef struct {                                    /*!< UART Structure                                                        */

+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start UART receiver                                                   */

+  __O  uint32_t  TASKS_STOPRX;                      /*!< Stop UART receiver                                                    */

+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start UART transmitter                                                */

+  __O  uint32_t  TASKS_STOPTX;                      /*!< Stop UART transmitter                                                 */

+  __I  uint32_t  RESERVED0[3];

+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend UART                                                          */

+  __I  uint32_t  RESERVED1[56];

+  __IO uint32_t  EVENTS_CTS;                        /*!< CTS is activated (set low). Clear To Send.                            */

+  __IO uint32_t  EVENTS_NCTS;                       /*!< CTS is deactivated (set high). Not Clear To Send.                     */

+  __IO uint32_t  EVENTS_RXDRDY;                     /*!< Data received in RXD                                                  */

+  __I  uint32_t  RESERVED2[4];

+  __IO uint32_t  EVENTS_TXDRDY;                     /*!< Data sent from TXD                                                    */

+  __I  uint32_t  RESERVED3;

+  __IO uint32_t  EVENTS_ERROR;                      /*!< Error detected                                                        */

+  __I  uint32_t  RESERVED4[7];

+  __IO uint32_t  EVENTS_RXTO;                       /*!< Receiver timeout                                                      */

+  __I  uint32_t  RESERVED5[46];

+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */

+  __I  uint32_t  RESERVED6[64];

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED7[93];

+  __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */

+  __I  uint32_t  RESERVED8[31];

+  __IO uint32_t  ENABLE;                            /*!< Enable UART                                                           */

+  __I  uint32_t  RESERVED9;

+  __IO uint32_t  PSELRTS;                           /*!< Pin select for RTS                                                    */

+  __IO uint32_t  PSELTXD;                           /*!< Pin select for TXD                                                    */

+  __IO uint32_t  PSELCTS;                           /*!< Pin select for CTS                                                    */

+  __IO uint32_t  PSELRXD;                           /*!< Pin select for RXD                                                    */

+  __I  uint32_t  RXD;                               /*!< RXD register                                                          */

+  __O  uint32_t  TXD;                               /*!< TXD register                                                          */

+  __I  uint32_t  RESERVED10;

+  __IO uint32_t  BAUDRATE;                          /*!< Baud rate                                                             */

+  __I  uint32_t  RESERVED11[17];

+  __IO uint32_t  CONFIG;                            /*!< Configuration of parity and hardware flow control                     */

+} NRF_UART_Type;

+

+

+/* ================================================================================ */

+/* ================                      SPIM                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM)

+  */

+

+typedef struct {                                    /*!< SPIM Structure                                                        */

+  __I  uint32_t  RESERVED0[4];

+  __O  uint32_t  TASKS_START;                       /*!< Start SPI transaction                                                 */

+  __O  uint32_t  TASKS_STOP;                        /*!< Stop SPI transaction                                                  */

+  __I  uint32_t  RESERVED1;

+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend SPI transaction                                               */

+  __O  uint32_t  TASKS_RESUME;                      /*!< Resume SPI transaction                                                */

+  __I  uint32_t  RESERVED2[56];

+  __IO uint32_t  EVENTS_STOPPED;                    /*!< SPI transaction has stopped                                           */

+  __I  uint32_t  RESERVED3[2];

+  __IO uint32_t  EVENTS_ENDRX;                      /*!< End of RXD buffer reached                                             */

+  __I  uint32_t  RESERVED4;

+  __IO uint32_t  EVENTS_END;                        /*!< End of RXD buffer and TXD buffer reached                              */

+  __I  uint32_t  RESERVED5;

+  __IO uint32_t  EVENTS_ENDTX;                      /*!< End of TXD buffer reached                                             */

+  __I  uint32_t  RESERVED6[10];

+  __IO uint32_t  EVENTS_STARTED;                    /*!< Transaction started                                                   */

+  __I  uint32_t  RESERVED7[44];

+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */

+  __I  uint32_t  RESERVED8[64];

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED9[125];

+  __IO uint32_t  ENABLE;                            /*!< Enable SPIM                                                           */

+  __I  uint32_t  RESERVED10;

+  SPIM_PSEL_Type PSEL;                              /*!< Unspecified                                                           */

+  __I  uint32_t  RESERVED11[4];

+  __IO uint32_t  FREQUENCY;                         /*!< SPI frequency                                                         */

+  __I  uint32_t  RESERVED12[3];

+  SPIM_RXD_Type RXD;                                /*!< RXD EasyDMA channel                                                   */

+  SPIM_TXD_Type TXD;                                /*!< TXD EasyDMA channel                                                   */

+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */

+  __I  uint32_t  RESERVED13[26];

+  __IO uint32_t  ORC;                               /*!< Over-read character. Character clocked out in case and over-read

+                                                         of the TXD buffer.                                                    */

+} NRF_SPIM_Type;

+

+

+/* ================================================================================ */

+/* ================                      SPIS                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief SPI Slave 0 (SPIS)

+  */

+

+typedef struct {                                    /*!< SPIS Structure                                                        */

+  __I  uint32_t  RESERVED0[9];

+  __O  uint32_t  TASKS_ACQUIRE;                     /*!< Acquire SPI semaphore                                                 */

+  __O  uint32_t  TASKS_RELEASE;                     /*!< Release SPI semaphore, enabling the SPI slave to acquire it           */

+  __I  uint32_t  RESERVED1[54];

+  __IO uint32_t  EVENTS_END;                        /*!< Granted transaction completed                                         */

+  __I  uint32_t  RESERVED2[2];

+  __IO uint32_t  EVENTS_ENDRX;                      /*!< End of RXD buffer reached                                             */

+  __I  uint32_t  RESERVED3[5];

+  __IO uint32_t  EVENTS_ACQUIRED;                   /*!< Semaphore acquired                                                    */

+  __I  uint32_t  RESERVED4[53];

+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */

+  __I  uint32_t  RESERVED5[64];

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED6[61];

+  __I  uint32_t  SEMSTAT;                           /*!< Semaphore status register                                             */

+  __I  uint32_t  RESERVED7[15];

+  __IO uint32_t  STATUS;                            /*!< Status from last transaction                                          */

+  __I  uint32_t  RESERVED8[47];

+  __IO uint32_t  ENABLE;                            /*!< Enable SPI slave                                                      */

+  __I  uint32_t  RESERVED9;

+  SPIS_PSEL_Type PSEL;                              /*!< Unspecified                                                           */

+  __I  uint32_t  RESERVED10[7];

+  SPIS_RXD_Type RXD;                                /*!< Unspecified                                                           */

+  __I  uint32_t  RESERVED11;

+  SPIS_TXD_Type TXD;                                /*!< Unspecified                                                           */

+  __I  uint32_t  RESERVED12;

+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */

+  __I  uint32_t  RESERVED13;

+  __IO uint32_t  DEF;                               /*!< Default character. Character clocked out in case of an ignored

+                                                         transaction.                                                          */

+  __I  uint32_t  RESERVED14[24];

+  __IO uint32_t  ORC;                               /*!< Over-read character                                                   */

+} NRF_SPIS_Type;

+

+

+/* ================================================================================ */

+/* ================                      TWIM                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM)

+  */

+

+typedef struct {                                    /*!< TWIM Structure                                                        */

+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start TWI receive sequence                                            */

+  __I  uint32_t  RESERVED0;

+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start TWI transmit sequence                                           */

+  __I  uint32_t  RESERVED1[2];

+  __O  uint32_t  TASKS_STOP;                        /*!< Stop TWI transaction. Must be issued while the TWI master is

+                                                         not suspended.                                                        */

+  __I  uint32_t  RESERVED2;

+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend TWI transaction                                               */

+  __O  uint32_t  TASKS_RESUME;                      /*!< Resume TWI transaction                                                */

+  __I  uint32_t  RESERVED3[56];

+  __IO uint32_t  EVENTS_STOPPED;                    /*!< TWI stopped                                                           */

+  __I  uint32_t  RESERVED4[7];

+  __IO uint32_t  EVENTS_ERROR;                      /*!< TWI error                                                             */

+  __I  uint32_t  RESERVED5[8];

+  __IO uint32_t  EVENTS_SUSPENDED;                  /*!< Last byte has been sent out after the SUSPEND task has been

+                                                         issued, TWI traffic is now suspended.                                 */

+  __IO uint32_t  EVENTS_RXSTARTED;                  /*!< Receive sequence started                                              */

+  __IO uint32_t  EVENTS_TXSTARTED;                  /*!< Transmit sequence started                                             */

+  __I  uint32_t  RESERVED6[2];

+  __IO uint32_t  EVENTS_LASTRX;                     /*!< Byte boundary, starting to receive the last byte                      */

+  __IO uint32_t  EVENTS_LASTTX;                     /*!< Byte boundary, starting to transmit the last byte                     */

+  __I  uint32_t  RESERVED7[39];

+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */

+  __I  uint32_t  RESERVED8[63];

+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED9[110];

+  __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */

+  __I  uint32_t  RESERVED10[14];

+  __IO uint32_t  ENABLE;                            /*!< Enable TWIM                                                           */

+  __I  uint32_t  RESERVED11;

+  TWIM_PSEL_Type PSEL;                              /*!< Unspecified                                                           */

+  __I  uint32_t  RESERVED12[5];

+  __IO uint32_t  FREQUENCY;                         /*!< TWI frequency                                                         */

+  __I  uint32_t  RESERVED13[3];

+  TWIM_RXD_Type RXD;                                /*!< RXD EasyDMA channel                                                   */

+  TWIM_TXD_Type TXD;                                /*!< TXD EasyDMA channel                                                   */

+  __I  uint32_t  RESERVED14[13];

+  __IO uint32_t  ADDRESS;                           /*!< Address used in the TWI transfer                                      */

+} NRF_TWIM_Type;

+

+

+/* ================================================================================ */

+/* ================                      TWIS                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS)

+  */

+

+typedef struct {                                    /*!< TWIS Structure                                                        */

+  __I  uint32_t  RESERVED0[5];

+  __O  uint32_t  TASKS_STOP;                        /*!< Stop TWI transaction                                                  */

+  __I  uint32_t  RESERVED1;

+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend TWI transaction                                               */

+  __O  uint32_t  TASKS_RESUME;                      /*!< Resume TWI transaction                                                */

+  __I  uint32_t  RESERVED2[3];

+  __O  uint32_t  TASKS_PREPARERX;                   /*!< Prepare the TWI slave to respond to a write command                   */

+  __O  uint32_t  TASKS_PREPARETX;                   /*!< Prepare the TWI slave to respond to a read command                    */

+  __I  uint32_t  RESERVED3[51];

+  __IO uint32_t  EVENTS_STOPPED;                    /*!< TWI stopped                                                           */

+  __I  uint32_t  RESERVED4[7];

+  __IO uint32_t  EVENTS_ERROR;                      /*!< TWI error                                                             */

+  __I  uint32_t  RESERVED5[9];

+  __IO uint32_t  EVENTS_RXSTARTED;                  /*!< Receive sequence started                                              */

+  __IO uint32_t  EVENTS_TXSTARTED;                  /*!< Transmit sequence started                                             */

+  __I  uint32_t  RESERVED6[4];

+  __IO uint32_t  EVENTS_WRITE;                      /*!< Write command received                                                */

+  __IO uint32_t  EVENTS_READ;                       /*!< Read command received                                                 */

+  __I  uint32_t  RESERVED7[37];

+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */

+  __I  uint32_t  RESERVED8[63];

+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED9[113];

+  __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */

+  __I  uint32_t  MATCH;                             /*!< Status register indicating which address had a match                  */

+  __I  uint32_t  RESERVED10[10];

+  __IO uint32_t  ENABLE;                            /*!< Enable TWIS                                                           */

+  __I  uint32_t  RESERVED11;

+  TWIS_PSEL_Type PSEL;                              /*!< Unspecified                                                           */

+  __I  uint32_t  RESERVED12[9];

+  TWIS_RXD_Type RXD;                                /*!< RXD EasyDMA channel                                                   */

+  __I  uint32_t  RESERVED13;

+  TWIS_TXD_Type TXD;                                /*!< TXD EasyDMA channel                                                   */

+  __I  uint32_t  RESERVED14[14];

+  __IO uint32_t  ADDRESS[2];                        /*!< Description collection[0]: TWI slave address 0                        */

+  __I  uint32_t  RESERVED15;

+  __IO uint32_t  CONFIG;                            /*!< Configuration register for the address match mechanism                */

+  __I  uint32_t  RESERVED16[10];

+  __IO uint32_t  ORC;                               /*!< Over-read character. Character sent out in case of an over-read

+                                                         of the transmit buffer.                                               */

+} NRF_TWIS_Type;

+

+

+/* ================================================================================ */

+/* ================                       SPI                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief Serial Peripheral Interface 0 (SPI)

+  */

+

+typedef struct {                                    /*!< SPI Structure                                                         */

+  __I  uint32_t  RESERVED0[66];

+  __IO uint32_t  EVENTS_READY;                      /*!< TXD byte sent and RXD byte received                                   */

+  __I  uint32_t  RESERVED1[126];

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED2[125];

+  __IO uint32_t  ENABLE;                            /*!< Enable SPI                                                            */

+  __I  uint32_t  RESERVED3;

+  SPI_PSEL_Type PSEL;                               /*!< Unspecified                                                           */

+  __I  uint32_t  RESERVED4;

+  __I  uint32_t  RXD;                               /*!< RXD register                                                          */

+  __IO uint32_t  TXD;                               /*!< TXD register                                                          */

+  __I  uint32_t  RESERVED5;

+  __IO uint32_t  FREQUENCY;                         /*!< SPI frequency                                                         */

+  __I  uint32_t  RESERVED6[11];

+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */

+} NRF_SPI_Type;

+

+

+/* ================================================================================ */

+/* ================                       TWI                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief I2C compatible Two-Wire Interface 0 (TWI)

+  */

+

+typedef struct {                                    /*!< TWI Structure                                                         */

+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start TWI receive sequence                                            */

+  __I  uint32_t  RESERVED0;

+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start TWI transmit sequence                                           */

+  __I  uint32_t  RESERVED1[2];

+  __O  uint32_t  TASKS_STOP;                        /*!< Stop TWI transaction                                                  */

+  __I  uint32_t  RESERVED2;

+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend TWI transaction                                               */

+  __O  uint32_t  TASKS_RESUME;                      /*!< Resume TWI transaction                                                */

+  __I  uint32_t  RESERVED3[56];

+  __IO uint32_t  EVENTS_STOPPED;                    /*!< TWI stopped                                                           */

+  __IO uint32_t  EVENTS_RXDREADY;                   /*!< TWI RXD byte received                                                 */

+  __I  uint32_t  RESERVED4[4];

+  __IO uint32_t  EVENTS_TXDSENT;                    /*!< TWI TXD byte sent                                                     */

+  __I  uint32_t  RESERVED5;

+  __IO uint32_t  EVENTS_ERROR;                      /*!< TWI error                                                             */

+  __I  uint32_t  RESERVED6[4];

+  __IO uint32_t  EVENTS_BB;                         /*!< TWI byte boundary, generated before each byte that is sent or

+                                                         received                                                              */

+  __I  uint32_t  RESERVED7[3];

+  __IO uint32_t  EVENTS_SUSPENDED;                  /*!< TWI entered the suspended state                                       */

+  __I  uint32_t  RESERVED8[45];

+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */

+  __I  uint32_t  RESERVED9[64];

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED10[110];

+  __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */

+  __I  uint32_t  RESERVED11[14];

+  __IO uint32_t  ENABLE;                            /*!< Enable TWI                                                            */

+  __I  uint32_t  RESERVED12;

+  __IO uint32_t  PSELSCL;                           /*!< Pin select for SCL                                                    */

+  __IO uint32_t  PSELSDA;                           /*!< Pin select for SDA                                                    */

+  __I  uint32_t  RESERVED13[2];

+  __I  uint32_t  RXD;                               /*!< RXD register                                                          */

+  __IO uint32_t  TXD;                               /*!< TXD register                                                          */

+  __I  uint32_t  RESERVED14;

+  __IO uint32_t  FREQUENCY;                         /*!< TWI frequency                                                         */

+  __I  uint32_t  RESERVED15[24];

+  __IO uint32_t  ADDRESS;                           /*!< Address used in the TWI transfer                                      */

+} NRF_TWI_Type;

+

+

+/* ================================================================================ */

+/* ================                      NFCT                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief NFC-A compatible radio (NFCT)

+  */

+

+typedef struct {                                    /*!< NFCT Structure                                                        */

+  __O  uint32_t  TASKS_ACTIVATE;                    /*!< Activate NFC peripheral for incoming and outgoing frames, change

+                                                         state to activated                                                    */

+  __O  uint32_t  TASKS_DISABLE;                     /*!< Disable NFC peripheral                                                */

+  __O  uint32_t  TASKS_SENSE;                       /*!< Enable NFC sense field mode, change state to sense mode               */

+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start transmission of a outgoing frame, change state to transmit      */

+  __I  uint32_t  RESERVED0[3];

+  __O  uint32_t  TASKS_ENABLERXDATA;                /*!< Initializes the EasyDMA for receive.                                  */

+  __I  uint32_t  RESERVED1;

+  __O  uint32_t  TASKS_GOIDLE;                      /*!< Force state machine to IDLE state                                     */

+  __O  uint32_t  TASKS_GOSLEEP;                     /*!< Force state machine to SLEEP_A state                                  */

+  __I  uint32_t  RESERVED2[53];

+  __IO uint32_t  EVENTS_READY;                      /*!< The NFC peripheral is ready to receive and send frames                */

+  __IO uint32_t  EVENTS_FIELDDETECTED;              /*!< Remote NFC field detected                                             */

+  __IO uint32_t  EVENTS_FIELDLOST;                  /*!< Remote NFC field lost                                                 */

+  __IO uint32_t  EVENTS_TXFRAMESTART;               /*!< Marks the start of the first symbol of a transmitted frame            */

+  __IO uint32_t  EVENTS_TXFRAMEEND;                 /*!< Marks the end of the last transmitted on-air symbol of a frame        */

+  __IO uint32_t  EVENTS_RXFRAMESTART;               /*!< Marks the end of the first symbol of a received frame                 */

+  __IO uint32_t  EVENTS_RXFRAMEEND;                 /*!< Received data have been checked (CRC, parity) and transferred

+                                                         to RAM, and EasyDMA has ended accessing the RX buffer                 */

+  __IO uint32_t  EVENTS_ERROR;                      /*!< NFC error reported. The ERRORSTATUS register contains details

+                                                         on the source of the error.                                           */

+  __I  uint32_t  RESERVED3[2];

+  __IO uint32_t  EVENTS_RXERROR;                    /*!< NFC RX frame error reported. The FRAMESTATUS.RX register contains

+                                                         details on the source of the error.                                   */

+  __IO uint32_t  EVENTS_ENDRX;                      /*!< RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.      */

+  __IO uint32_t  EVENTS_ENDTX;                      /*!< Transmission of data in RAM has ended, and EasyDMA has ended

+                                                         accessing the TX buffer                                               */

+  __I  uint32_t  RESERVED4;

+  __IO uint32_t  EVENTS_AUTOCOLRESSTARTED;          /*!< Auto collision resolution process has started                         */

+  __I  uint32_t  RESERVED5[3];

+  __IO uint32_t  EVENTS_COLLISION;                  /*!< NFC Auto collision resolution error reported.                         */

+  __IO uint32_t  EVENTS_SELECTED;                   /*!< NFC Auto collision resolution successfully completed                  */

+  __IO uint32_t  EVENTS_STARTED;                    /*!< EasyDMA is ready to receive or send frames.                           */

+  __I  uint32_t  RESERVED6[43];

+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */

+  __I  uint32_t  RESERVED7[63];

+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED8[62];

+  __IO uint32_t  ERRORSTATUS;                       /*!< NFC Error Status register                                             */

+  __I  uint32_t  RESERVED9;

+  NFCT_FRAMESTATUS_Type FRAMESTATUS;                /*!< Unspecified                                                           */

+  __I  uint32_t  RESERVED10[8];

+  __I  uint32_t  CURRENTLOADCTRL;                   /*!< Current value driven to the NFC Load Control                          */

+  __I  uint32_t  RESERVED11[2];

+  __I  uint32_t  FIELDPRESENT;                      /*!< Indicates the presence or not of a valid field                        */

+  __I  uint32_t  RESERVED12[49];

+  __IO uint32_t  FRAMEDELAYMIN;                     /*!< Minimum frame delay                                                   */

+  __IO uint32_t  FRAMEDELAYMAX;                     /*!< Maximum frame delay                                                   */

+  __IO uint32_t  FRAMEDELAYMODE;                    /*!< Configuration register for the Frame Delay Timer                      */

+  __IO uint32_t  PACKETPTR;                         /*!< Packet pointer for TXD and RXD data storage in Data RAM               */

+  __IO uint32_t  MAXLEN;                            /*!< Size of allocated for TXD and RXD data storage buffer in Data

+                                                         RAM                                                                   */

+  NFCT_TXD_Type TXD;                                /*!< Unspecified                                                           */

+  NFCT_RXD_Type RXD;                                /*!< Unspecified                                                           */

+  __I  uint32_t  RESERVED13[26];

+  __IO uint32_t  NFCID1_LAST;                       /*!< Last NFCID1 part (4, 7 or 10 bytes ID)                                */

+  __IO uint32_t  NFCID1_2ND_LAST;                   /*!< Second last NFCID1 part (7 or 10 bytes ID)                            */

+  __IO uint32_t  NFCID1_3RD_LAST;                   /*!< Third last NFCID1 part (10 bytes ID)                                  */

+  __I  uint32_t  RESERVED14;

+  __IO uint32_t  SENSRES;                           /*!< NFC-A SENS_RES auto-response settings                                 */

+  __IO uint32_t  SELRES;                            /*!< NFC-A SEL_RES auto-response settings                                  */

+} NRF_NFCT_Type;

+

+

+/* ================================================================================ */

+/* ================                     GPIOTE                     ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief GPIO Tasks and Events (GPIOTE)

+  */

+

+typedef struct {                                    /*!< GPIOTE Structure                                                      */

+  __O  uint32_t  TASKS_OUT[8];                      /*!< Description collection[0]: Task for writing to pin specified

+                                                         in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. */

+  __I  uint32_t  RESERVED0[4];

+  __O  uint32_t  TASKS_SET[8];                      /*!< Description collection[0]: Task for writing to pin specified

+                                                         in CONFIG[0].PSEL. Action on pin is to set it high.                   */

+  __I  uint32_t  RESERVED1[4];

+  __O  uint32_t  TASKS_CLR[8];                      /*!< Description collection[0]: Task for writing to pin specified

+                                                         in CONFIG[0].PSEL. Action on pin is to set it low.                    */

+  __I  uint32_t  RESERVED2[32];

+  __IO uint32_t  EVENTS_IN[8];                      /*!< Description collection[0]: Event generated from pin specified

+                                                         in CONFIG[0].PSEL                                                     */

+  __I  uint32_t  RESERVED3[23];

+  __IO uint32_t  EVENTS_PORT;                       /*!< Event generated from multiple input GPIO pins with SENSE mechanism

+                                                         enabled                                                               */

+  __I  uint32_t  RESERVED4[97];

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED5[129];

+  __IO uint32_t  CONFIG[8];                         /*!< Description collection[0]: Configuration for OUT[n], SET[n]

+                                                         and CLR[n] tasks and IN[n] event                                      */

+} NRF_GPIOTE_Type;

+

+

+/* ================================================================================ */

+/* ================                      SAADC                     ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief Analog to Digital Converter (SAADC)

+  */

+

+typedef struct {                                    /*!< SAADC Structure                                                       */

+  __O  uint32_t  TASKS_START;                       /*!< Start the ADC and prepare the result buffer in RAM                    */

+  __O  uint32_t  TASKS_SAMPLE;                      /*!< Take one ADC sample, if scan is enabled all channels are sampled      */

+  __O  uint32_t  TASKS_STOP;                        /*!< Stop the ADC and terminate any on-going conversion                    */

+  __O  uint32_t  TASKS_CALIBRATEOFFSET;             /*!< Starts offset auto-calibration                                        */

+  __I  uint32_t  RESERVED0[60];

+  __IO uint32_t  EVENTS_STARTED;                    /*!< The ADC has started                                                   */

+  __IO uint32_t  EVENTS_END;                        /*!< The ADC has filled up the Result buffer                               */

+  __IO uint32_t  EVENTS_DONE;                       /*!< A conversion task has been completed. Depending on the mode,

+                                                         multiple conversions might be needed for a result to be transferred

+                                                          to RAM.                                                              */

+  __IO uint32_t  EVENTS_RESULTDONE;                 /*!< A result is ready to get transferred to RAM.                          */

+  __IO uint32_t  EVENTS_CALIBRATEDONE;              /*!< Calibration is complete                                               */

+  __IO uint32_t  EVENTS_STOPPED;                    /*!< The ADC has stopped                                                   */

+  SAADC_EVENTS_CH_Type EVENTS_CH[8];                /*!< Unspecified                                                           */

+  __I  uint32_t  RESERVED1[106];

+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED2[61];

+  __I  uint32_t  STATUS;                            /*!< Status                                                                */

+  __I  uint32_t  RESERVED3[63];

+  __IO uint32_t  ENABLE;                            /*!< Enable or disable ADC                                                 */

+  __I  uint32_t  RESERVED4[3];

+  SAADC_CH_Type CH[8];                              /*!< Unspecified                                                           */

+  __I  uint32_t  RESERVED5[24];

+  __IO uint32_t  RESOLUTION;                        /*!< Resolution configuration                                              */

+  __IO uint32_t  OVERSAMPLE;                        /*!< Oversampling configuration. OVERSAMPLE should not be combined

+                                                         with SCAN. The RESOLUTION is applied before averaging, thus

+                                                          for high OVERSAMPLE a higher RESOLUTION should be used.              */

+  __IO uint32_t  SAMPLERATE;                        /*!< Controls normal or continuous sample rate                             */

+  __I  uint32_t  RESERVED6[12];

+  SAADC_RESULT_Type RESULT;                         /*!< RESULT EasyDMA channel                                                */

+} NRF_SAADC_Type;

+

+

+/* ================================================================================ */

+/* ================                      TIMER                     ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief Timer/Counter 0 (TIMER)

+  */

+

+typedef struct {                                    /*!< TIMER Structure                                                       */

+  __O  uint32_t  TASKS_START;                       /*!< Start Timer                                                           */

+  __O  uint32_t  TASKS_STOP;                        /*!< Stop Timer                                                            */

+  __O  uint32_t  TASKS_COUNT;                       /*!< Increment Timer (Counter mode only)                                   */

+  __O  uint32_t  TASKS_CLEAR;                       /*!< Clear time                                                            */

+  __O  uint32_t  TASKS_SHUTDOWN;                    /*!< Deprecated register - Shut down timer                                 */

+  __I  uint32_t  RESERVED0[11];

+  __O  uint32_t  TASKS_CAPTURE[6];                  /*!< Description collection[0]: Capture Timer value to CC[0] register      */

+  __I  uint32_t  RESERVED1[58];

+  __IO uint32_t  EVENTS_COMPARE[6];                 /*!< Description collection[0]: Compare event on CC[0] match               */

+  __I  uint32_t  RESERVED2[42];

+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */

+  __I  uint32_t  RESERVED3[64];

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED4[126];

+  __IO uint32_t  MODE;                              /*!< Timer mode selection                                                  */

+  __IO uint32_t  BITMODE;                           /*!< Configure the number of bits used by the TIMER                        */

+  __I  uint32_t  RESERVED5;

+  __IO uint32_t  PRESCALER;                         /*!< Timer prescaler register                                              */

+  __I  uint32_t  RESERVED6[11];

+  __IO uint32_t  CC[6];                             /*!< Description collection[0]: Capture/Compare register 0                 */

+} NRF_TIMER_Type;

+

+

+/* ================================================================================ */

+/* ================                       RTC                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief Real time counter 0 (RTC)

+  */

+

+typedef struct {                                    /*!< RTC Structure                                                         */

+  __O  uint32_t  TASKS_START;                       /*!< Start RTC COUNTER                                                     */

+  __O  uint32_t  TASKS_STOP;                        /*!< Stop RTC COUNTER                                                      */

+  __O  uint32_t  TASKS_CLEAR;                       /*!< Clear RTC COUNTER                                                     */

+  __O  uint32_t  TASKS_TRIGOVRFLW;                  /*!< Set COUNTER to 0xFFFFF0                                               */

+  __I  uint32_t  RESERVED0[60];

+  __IO uint32_t  EVENTS_TICK;                       /*!< Event on COUNTER increment                                            */

+  __IO uint32_t  EVENTS_OVRFLW;                     /*!< Event on COUNTER overflow                                             */

+  __I  uint32_t  RESERVED1[14];

+  __IO uint32_t  EVENTS_COMPARE[4];                 /*!< Description collection[0]: Compare event on CC[0] match               */

+  __I  uint32_t  RESERVED2[109];

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED3[13];

+  __IO uint32_t  EVTEN;                             /*!< Enable or disable event routing                                       */

+  __IO uint32_t  EVTENSET;                          /*!< Enable event routing                                                  */

+  __IO uint32_t  EVTENCLR;                          /*!< Disable event routing                                                 */

+  __I  uint32_t  RESERVED4[110];

+  __I  uint32_t  COUNTER;                           /*!< Current COUNTER value                                                 */

+  __IO uint32_t  PRESCALER;                         /*!< 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must

+                                                         be written when RTC is stopped                                        */

+  __I  uint32_t  RESERVED5[13];

+  __IO uint32_t  CC[4];                             /*!< Description collection[0]: Compare register 0                         */

+} NRF_RTC_Type;

+

+

+/* ================================================================================ */

+/* ================                      TEMP                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief Temperature Sensor (TEMP)

+  */

+

+typedef struct {                                    /*!< TEMP Structure                                                        */

+  __O  uint32_t  TASKS_START;                       /*!< Start temperature measurement                                         */

+  __O  uint32_t  TASKS_STOP;                        /*!< Stop temperature measurement                                          */

+  __I  uint32_t  RESERVED0[62];

+  __IO uint32_t  EVENTS_DATARDY;                    /*!< Temperature measurement complete, data ready                          */

+  __I  uint32_t  RESERVED1[128];

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED2[127];

+  __I  int32_t   TEMP;                              /*!< Temperature in degC (0.25deg steps)                                   */

+  __I  uint32_t  RESERVED3[5];

+  __IO uint32_t  A0;                                /*!< Slope of 1st piece wise linear function                               */

+  __IO uint32_t  A1;                                /*!< Slope of 2nd piece wise linear function                               */

+  __IO uint32_t  A2;                                /*!< Slope of 3rd piece wise linear function                               */

+  __IO uint32_t  A3;                                /*!< Slope of 4th piece wise linear function                               */

+  __IO uint32_t  A4;                                /*!< Slope of 5th piece wise linear function                               */

+  __IO uint32_t  A5;                                /*!< Slope of 6th piece wise linear function                               */

+  __I  uint32_t  RESERVED4[2];

+  __IO uint32_t  B0;                                /*!< y-intercept of 1st piece wise linear function                         */

+  __IO uint32_t  B1;                                /*!< y-intercept of 2nd piece wise linear function                         */

+  __IO uint32_t  B2;                                /*!< y-intercept of 3rd piece wise linear function                         */

+  __IO uint32_t  B3;                                /*!< y-intercept of 4th piece wise linear function                         */

+  __IO uint32_t  B4;                                /*!< y-intercept of 5th piece wise linear function                         */

+  __IO uint32_t  B5;                                /*!< y-intercept of 6th piece wise linear function                         */

+  __I  uint32_t  RESERVED5[2];

+  __IO uint32_t  T0;                                /*!< End point of 1st piece wise linear function                           */

+  __IO uint32_t  T1;                                /*!< End point of 2nd piece wise linear function                           */

+  __IO uint32_t  T2;                                /*!< End point of 3rd piece wise linear function                           */

+  __IO uint32_t  T3;                                /*!< End point of 4th piece wise linear function                           */

+  __IO uint32_t  T4;                                /*!< End point of 5th piece wise linear function                           */

+} NRF_TEMP_Type;

+

+

+/* ================================================================================ */

+/* ================                       RNG                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief Random Number Generator (RNG)

+  */

+

+typedef struct {                                    /*!< RNG Structure                                                         */

+  __O  uint32_t  TASKS_START;                       /*!< Task starting the random number generator                             */

+  __O  uint32_t  TASKS_STOP;                        /*!< Task stopping the random number generator                             */

+  __I  uint32_t  RESERVED0[62];

+  __IO uint32_t  EVENTS_VALRDY;                     /*!< Event being generated for every new random number written to

+                                                         the VALUE register                                                    */

+  __I  uint32_t  RESERVED1[63];

+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */

+  __I  uint32_t  RESERVED2[64];

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED3[126];

+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */

+  __I  uint32_t  VALUE;                             /*!< Output random number                                                  */

+} NRF_RNG_Type;

+

+

+/* ================================================================================ */

+/* ================                       ECB                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief AES ECB Mode Encryption (ECB)

+  */

+

+typedef struct {                                    /*!< ECB Structure                                                         */

+  __O  uint32_t  TASKS_STARTECB;                    /*!< Start ECB block encrypt                                               */

+  __O  uint32_t  TASKS_STOPECB;                     /*!< Abort a possible executing ECB operation                              */

+  __I  uint32_t  RESERVED0[62];

+  __IO uint32_t  EVENTS_ENDECB;                     /*!< ECB block encrypt complete                                            */

+  __IO uint32_t  EVENTS_ERRORECB;                   /*!< ECB block encrypt aborted because of a STOPECB task or due to

+                                                         an error                                                              */

+  __I  uint32_t  RESERVED1[127];

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED2[126];

+  __IO uint32_t  ECBDATAPTR;                        /*!< ECB block encrypt memory pointers                                     */

+} NRF_ECB_Type;

+

+

+/* ================================================================================ */

+/* ================                       CCM                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief AES CCM Mode Encryption (CCM)

+  */

+

+typedef struct {                                    /*!< CCM Structure                                                         */

+  __O  uint32_t  TASKS_KSGEN;                       /*!< Start generation of key-stream. This operation will stop by

+                                                         itself when completed.                                                */

+  __O  uint32_t  TASKS_CRYPT;                       /*!< Start encryption/decryption. This operation will stop by itself

+                                                         when completed.                                                       */

+  __O  uint32_t  TASKS_STOP;                        /*!< Stop encryption/decryption                                            */

+  __I  uint32_t  RESERVED0[61];

+  __IO uint32_t  EVENTS_ENDKSGEN;                   /*!< Key-stream generation complete                                        */

+  __IO uint32_t  EVENTS_ENDCRYPT;                   /*!< Encrypt/decrypt complete                                              */

+  __IO uint32_t  EVENTS_ERROR;                      /*!< CCM error event                                                       */

+  __I  uint32_t  RESERVED1[61];

+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */

+  __I  uint32_t  RESERVED2[64];

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED3[61];

+  __I  uint32_t  MICSTATUS;                         /*!< MIC check result                                                      */

+  __I  uint32_t  RESERVED4[63];

+  __IO uint32_t  ENABLE;                            /*!< Enable                                                                */

+  __IO uint32_t  MODE;                              /*!< Operation mode                                                        */

+  __IO uint32_t  CNFPTR;                            /*!< Pointer to data structure holding AES key and NONCE vector            */

+  __IO uint32_t  INPTR;                             /*!< Input pointer                                                         */

+  __IO uint32_t  OUTPTR;                            /*!< Output pointer                                                        */

+  __IO uint32_t  SCRATCHPTR;                        /*!< Pointer to data area used for temporary storage                       */

+} NRF_CCM_Type;

+

+

+/* ================================================================================ */

+/* ================                       AAR                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief Accelerated Address Resolver (AAR)

+  */

+

+typedef struct {                                    /*!< AAR Structure                                                         */

+  __O  uint32_t  TASKS_START;                       /*!< Start resolving addresses based on IRKs specified in the IRK

+                                                         data structure                                                        */

+  __I  uint32_t  RESERVED0;

+  __O  uint32_t  TASKS_STOP;                        /*!< Stop resolving addresses                                              */

+  __I  uint32_t  RESERVED1[61];

+  __IO uint32_t  EVENTS_END;                        /*!< Address resolution procedure complete                                 */

+  __IO uint32_t  EVENTS_RESOLVED;                   /*!< Address resolved                                                      */

+  __IO uint32_t  EVENTS_NOTRESOLVED;                /*!< Address not resolved                                                  */

+  __I  uint32_t  RESERVED2[126];

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED3[61];

+  __I  uint32_t  STATUS;                            /*!< Resolution status                                                     */

+  __I  uint32_t  RESERVED4[63];

+  __IO uint32_t  ENABLE;                            /*!< Enable AAR                                                            */

+  __IO uint32_t  NIRK;                              /*!< Number of IRKs                                                        */

+  __IO uint32_t  IRKPTR;                            /*!< Pointer to IRK data structure                                         */

+  __I  uint32_t  RESERVED5;

+  __IO uint32_t  ADDRPTR;                           /*!< Pointer to the resolvable address                                     */

+  __IO uint32_t  SCRATCHPTR;                        /*!< Pointer to data area used for temporary storage                       */

+} NRF_AAR_Type;

+

+

+/* ================================================================================ */

+/* ================                       WDT                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief Watchdog Timer (WDT)

+  */

+

+typedef struct {                                    /*!< WDT Structure                                                         */

+  __O  uint32_t  TASKS_START;                       /*!< Start the watchdog                                                    */

+  __I  uint32_t  RESERVED0[63];

+  __IO uint32_t  EVENTS_TIMEOUT;                    /*!< Watchdog timeout                                                      */

+  __I  uint32_t  RESERVED1[128];

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED2[61];

+  __I  uint32_t  RUNSTATUS;                         /*!< Run status                                                            */

+  __I  uint32_t  REQSTATUS;                         /*!< Request status                                                        */

+  __I  uint32_t  RESERVED3[63];

+  __IO uint32_t  CRV;                               /*!< Counter reload value                                                  */

+  __IO uint32_t  RREN;                              /*!< Enable register for reload request registers                          */

+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */

+  __I  uint32_t  RESERVED4[60];

+  __O  uint32_t  RR[8];                             /*!< Description collection[0]: Reload request 0                           */

+} NRF_WDT_Type;

+

+

+/* ================================================================================ */

+/* ================                      QDEC                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief Quadrature Decoder (QDEC)

+  */

+

+typedef struct {                                    /*!< QDEC Structure                                                        */

+  __O  uint32_t  TASKS_START;                       /*!< Task starting the quadrature decoder                                  */

+  __O  uint32_t  TASKS_STOP;                        /*!< Task stopping the quadrature decoder                                  */

+  __O  uint32_t  TASKS_READCLRACC;                  /*!< Read and clear ACC and ACCDBL                                         */

+  __O  uint32_t  TASKS_RDCLRACC;                    /*!< Read and clear ACC                                                    */

+  __O  uint32_t  TASKS_RDCLRDBL;                    /*!< Read and clear ACCDBL                                                 */

+  __I  uint32_t  RESERVED0[59];

+  __IO uint32_t  EVENTS_SAMPLERDY;                  /*!< Event being generated for every new sample value written to

+                                                         the SAMPLE register                                                   */

+  __IO uint32_t  EVENTS_REPORTRDY;                  /*!< Non-null report ready                                                 */

+  __IO uint32_t  EVENTS_ACCOF;                      /*!< ACC or ACCDBL register overflow                                       */

+  __IO uint32_t  EVENTS_DBLRDY;                     /*!< Double displacement(s) detected                                       */

+  __IO uint32_t  EVENTS_STOPPED;                    /*!< QDEC has been stopped                                                 */

+  __I  uint32_t  RESERVED1[59];

+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */

+  __I  uint32_t  RESERVED2[64];

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED3[125];

+  __IO uint32_t  ENABLE;                            /*!< Enable the quadrature decoder                                         */

+  __IO uint32_t  LEDPOL;                            /*!< LED output pin polarity                                               */

+  __IO uint32_t  SAMPLEPER;                         /*!< Sample period                                                         */

+  __I  int32_t   SAMPLE;                            /*!< Motion sample value                                                   */

+  __IO uint32_t  REPORTPER;                         /*!< Number of samples to be taken before REPORTRDY and DBLRDY events

+                                                         can be generated                                                      */

+  __I  int32_t   ACC;                               /*!< Register accumulating the valid transitions                           */

+  __I  int32_t   ACCREAD;                           /*!< Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC

+                                                         task                                                                  */

+  QDEC_PSEL_Type PSEL;                              /*!< Unspecified                                                           */

+  __IO uint32_t  DBFEN;                             /*!< Enable input debounce filters                                         */

+  __I  uint32_t  RESERVED4[5];

+  __IO uint32_t  LEDPRE;                            /*!< Time period the LED is switched ON prior to sampling                  */

+  __I  uint32_t  ACCDBL;                            /*!< Register accumulating the number of detected double transitions       */

+  __I  uint32_t  ACCDBLREAD;                        /*!< Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL

+                                                         task                                                                  */

+} NRF_QDEC_Type;

+

+

+/* ================================================================================ */

+/* ================                      COMP                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief Comparator (COMP)

+  */

+

+typedef struct {                                    /*!< COMP Structure                                                        */

+  __O  uint32_t  TASKS_START;                       /*!< Start comparator                                                      */

+  __O  uint32_t  TASKS_STOP;                        /*!< Stop comparator                                                       */

+  __O  uint32_t  TASKS_SAMPLE;                      /*!< Sample comparator value                                               */

+  __I  uint32_t  RESERVED0[61];

+  __IO uint32_t  EVENTS_READY;                      /*!< COMP is ready and output is valid                                     */

+  __IO uint32_t  EVENTS_DOWN;                       /*!< Downward crossing                                                     */

+  __IO uint32_t  EVENTS_UP;                         /*!< Upward crossing                                                       */

+  __IO uint32_t  EVENTS_CROSS;                      /*!< Downward or upward crossing                                           */

+  __I  uint32_t  RESERVED1[60];

+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */

+  __I  uint32_t  RESERVED2[63];

+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED3[61];

+  __I  uint32_t  RESULT;                            /*!< Compare result                                                        */

+  __I  uint32_t  RESERVED4[63];

+  __IO uint32_t  ENABLE;                            /*!< COMP enable                                                           */

+  __IO uint32_t  PSEL;                              /*!< Pin select                                                            */

+  __IO uint32_t  REFSEL;                            /*!< Reference source select                                               */

+  __IO uint32_t  EXTREFSEL;                         /*!< External reference select                                             */

+  __I  uint32_t  RESERVED5[8];

+  __IO uint32_t  TH;                                /*!< Threshold configuration for hysteresis unit                           */

+  __IO uint32_t  MODE;                              /*!< Mode configuration                                                    */

+  __IO uint32_t  HYST;                              /*!< Comparator hysteresis enable                                          */

+  __IO uint32_t  ISOURCE;                           /*!< Current source select on analog input                                 */

+} NRF_COMP_Type;

+

+

+/* ================================================================================ */

+/* ================                     LPCOMP                     ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief Low Power Comparator (LPCOMP)

+  */

+

+typedef struct {                                    /*!< LPCOMP Structure                                                      */

+  __O  uint32_t  TASKS_START;                       /*!< Start comparator                                                      */

+  __O  uint32_t  TASKS_STOP;                        /*!< Stop comparator                                                       */

+  __O  uint32_t  TASKS_SAMPLE;                      /*!< Sample comparator value                                               */

+  __I  uint32_t  RESERVED0[61];

+  __IO uint32_t  EVENTS_READY;                      /*!< LPCOMP is ready and output is valid                                   */

+  __IO uint32_t  EVENTS_DOWN;                       /*!< Downward crossing                                                     */

+  __IO uint32_t  EVENTS_UP;                         /*!< Upward crossing                                                       */

+  __IO uint32_t  EVENTS_CROSS;                      /*!< Downward or upward crossing                                           */

+  __I  uint32_t  RESERVED1[60];

+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */

+  __I  uint32_t  RESERVED2[64];

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED3[61];

+  __I  uint32_t  RESULT;                            /*!< Compare result                                                        */

+  __I  uint32_t  RESERVED4[63];

+  __IO uint32_t  ENABLE;                            /*!< Enable LPCOMP                                                         */

+  __IO uint32_t  PSEL;                              /*!< Input pin select                                                      */

+  __IO uint32_t  REFSEL;                            /*!< Reference select                                                      */

+  __IO uint32_t  EXTREFSEL;                         /*!< External reference select                                             */

+  __I  uint32_t  RESERVED5[4];

+  __IO uint32_t  ANADETECT;                         /*!< Analog detect configuration                                           */

+  __I  uint32_t  RESERVED6[5];

+  __IO uint32_t  HYST;                              /*!< Comparator hysteresis enable                                          */

+} NRF_LPCOMP_Type;

+

+

+/* ================================================================================ */

+/* ================                       SWI                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief Software interrupt 0 (SWI)

+  */

+

+typedef struct {                                    /*!< SWI Structure                                                         */

+  __I  uint32_t  UNUSED;                            /*!< Unused.                                                               */

+} NRF_SWI_Type;

+

+

+/* ================================================================================ */

+/* ================                       EGU                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief Event Generator Unit 0 (EGU)

+  */

+

+typedef struct {                                    /*!< EGU Structure                                                         */

+  __O  uint32_t  TASKS_TRIGGER[16];                 /*!< Description collection[0]: Trigger 0 for triggering the corresponding

+                                                         TRIGGERED[0] event                                                    */

+  __I  uint32_t  RESERVED0[48];

+  __IO uint32_t  EVENTS_TRIGGERED[16];              /*!< Description collection[0]: Event number 0 generated by triggering

+                                                         the corresponding TRIGGER[0] task                                     */

+  __I  uint32_t  RESERVED1[112];

+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+} NRF_EGU_Type;

+

+

+/* ================================================================================ */

+/* ================                       PWM                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief Pulse Width Modulation Unit 0 (PWM)

+  */

+

+typedef struct {                                    /*!< PWM Structure                                                         */

+  __I  uint32_t  RESERVED0;

+  __O  uint32_t  TASKS_STOP;                        /*!< Stops PWM pulse generation on all channels at the end of current

+                                                         PWM period, and stops sequence playback                               */

+  __O  uint32_t  TASKS_SEQSTART[2];                 /*!< Description collection[0]: Loads the first PWM value on all

+                                                         enabled channels from sequence 0, and starts playing that sequence

+                                                          at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes

+                                                          PWM generation to start it was not running.                          */

+  __O  uint32_t  TASKS_NEXTSTEP;                    /*!< Steps by one value in the current sequence on all enabled channels

+                                                         if DECODER.MODE=NextStep. Does not cause PWM generation to start

+                                                          it was not running.                                                  */

+  __I  uint32_t  RESERVED1[60];

+  __IO uint32_t  EVENTS_STOPPED;                    /*!< Response to STOP task, emitted when PWM pulses are no longer

+                                                         generated                                                             */

+  __IO uint32_t  EVENTS_SEQSTARTED[2];              /*!< Description collection[0]: First PWM period started on sequence

+                                                         0                                                                     */

+  __IO uint32_t  EVENTS_SEQEND[2];                  /*!< Description collection[0]: Emitted at end of every sequence

+                                                         0, when last value from RAM has been applied to wave counter          */

+  __IO uint32_t  EVENTS_PWMPERIODEND;               /*!< Emitted at the end of each PWM period                                 */

+  __IO uint32_t  EVENTS_LOOPSDONE;                  /*!< Concatenated sequences have been played the amount of times

+                                                         defined in LOOP.CNT                                                   */

+  __I  uint32_t  RESERVED2[56];

+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */

+  __I  uint32_t  RESERVED3[63];

+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED4[125];

+  __IO uint32_t  ENABLE;                            /*!< PWM module enable register                                            */

+  __IO uint32_t  MODE;                              /*!< Selects operating mode of the wave counter                            */

+  __IO uint32_t  COUNTERTOP;                        /*!< Value up to which the pulse generator counter counts                  */

+  __IO uint32_t  PRESCALER;                         /*!< Configuration for PWM_CLK                                             */

+  __IO uint32_t  DECODER;                           /*!< Configuration of the decoder                                          */

+  __IO uint32_t  LOOP;                              /*!< Amount of playback of a loop                                          */

+  __I  uint32_t  RESERVED5[2];

+  PWM_SEQ_Type SEQ[2];                              /*!< Unspecified                                                           */

+  PWM_PSEL_Type PSEL;                               /*!< Unspecified                                                           */

+} NRF_PWM_Type;

+

+

+/* ================================================================================ */

+/* ================                       PDM                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM)

+  */

+

+typedef struct {                                    /*!< PDM Structure                                                         */

+  __O  uint32_t  TASKS_START;                       /*!< Starts continuous PDM transfer                                        */

+  __O  uint32_t  TASKS_STOP;                        /*!< Stops PDM transfer                                                    */

+  __I  uint32_t  RESERVED0[62];

+  __IO uint32_t  EVENTS_STARTED;                    /*!< PDM transfer has started                                              */

+  __IO uint32_t  EVENTS_STOPPED;                    /*!< PDM transfer has finished                                             */

+  __IO uint32_t  EVENTS_END;                        /*!< The PDM has written the last sample specified by SAMPLE.MAXCNT

+                                                         (or the last sample after a STOP task has been received) to

+                                                          Data RAM                                                             */

+  __I  uint32_t  RESERVED1[125];

+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED2[125];

+  __IO uint32_t  ENABLE;                            /*!< PDM module enable register                                            */

+  __IO uint32_t  PDMCLKCTRL;                        /*!< PDM clock generator control                                           */

+  __IO uint32_t  MODE;                              /*!< Defines the routing of the connected PDM microphones' signals         */

+  __I  uint32_t  RESERVED3[3];

+  __IO uint32_t  GAINL;                             /*!< Left output gain adjustment                                           */

+  __IO uint32_t  GAINR;                             /*!< Right output gain adjustment                                          */

+  __I  uint32_t  RESERVED4[8];

+  PDM_PSEL_Type PSEL;                               /*!< Unspecified                                                           */

+  __I  uint32_t  RESERVED5[6];

+  PDM_SAMPLE_Type SAMPLE;                           /*!< Unspecified                                                           */

+} NRF_PDM_Type;

+

+

+/* ================================================================================ */

+/* ================                      NVMC                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief Non Volatile Memory Controller (NVMC)

+  */

+

+typedef struct {                                    /*!< NVMC Structure                                                        */

+  __I  uint32_t  RESERVED0[256];

+  __I  uint32_t  READY;                             /*!< Ready flag                                                            */

+  __I  uint32_t  RESERVED1[64];

+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */

+  

+  union {

+    __IO uint32_t  ERASEPCR1;                       /*!< Deprecated register - Register for erasing a page in Code area.

+                                                         Equivalent to ERASEPAGE.                                              */

+    __IO uint32_t  ERASEPAGE;                       /*!< Register for erasing a page in Code area                              */

+  };

+  __IO uint32_t  ERASEALL;                          /*!< Register for erasing all non-volatile user memory                     */

+  __IO uint32_t  ERASEPCR0;                         /*!< Deprecated register - Register for erasing a page in Code area.

+                                                         Equivalent to ERASEPAGE.                                              */

+  __IO uint32_t  ERASEUICR;                         /*!< Register for erasing User Information Configuration Registers         */

+  __I  uint32_t  RESERVED2[10];

+  __IO uint32_t  ICACHECNF;                         /*!< I-Code cache configuration register.                                  */

+  __I  uint32_t  RESERVED3;

+  __IO uint32_t  IHIT;                              /*!< I-Code cache hit counter.                                             */

+  __IO uint32_t  IMISS;                             /*!< I-Code cache miss counter.                                            */

+} NRF_NVMC_Type;

+

+

+/* ================================================================================ */

+/* ================                       PPI                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief Programmable Peripheral Interconnect (PPI)

+  */

+

+typedef struct {                                    /*!< PPI Structure                                                         */

+  PPI_TASKS_CHG_Type TASKS_CHG[6];                  /*!< Channel group tasks                                                   */

+  __I  uint32_t  RESERVED0[308];

+  __IO uint32_t  CHEN;                              /*!< Channel enable register                                               */

+  __IO uint32_t  CHENSET;                           /*!< Channel enable set register                                           */

+  __IO uint32_t  CHENCLR;                           /*!< Channel enable clear register                                         */

+  __I  uint32_t  RESERVED1;

+  PPI_CH_Type CH[20];                               /*!< PPI Channel                                                           */

+  __I  uint32_t  RESERVED2[148];

+  __IO uint32_t  CHG[6];                            /*!< Description collection[0]: Channel group 0                            */

+  __I  uint32_t  RESERVED3[62];

+  PPI_FORK_Type FORK[32];                           /*!< Fork                                                                  */

+} NRF_PPI_Type;

+

+

+/* ================================================================================ */

+/* ================                       MWU                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief Memory Watch Unit (MWU)

+  */

+

+typedef struct {                                    /*!< MWU Structure                                                         */

+  __I  uint32_t  RESERVED0[64];

+  MWU_EVENTS_REGION_Type EVENTS_REGION[4];          /*!< Unspecified                                                           */

+  __I  uint32_t  RESERVED1[16];

+  MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];        /*!< Unspecified                                                           */

+  __I  uint32_t  RESERVED2[100];

+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED3[5];

+  __IO uint32_t  NMIEN;                             /*!< Enable or disable non-maskable interrupt                              */

+  __IO uint32_t  NMIENSET;                          /*!< Enable non-maskable interrupt                                         */

+  __IO uint32_t  NMIENCLR;                          /*!< Disable non-maskable interrupt                                        */

+  __I  uint32_t  RESERVED4[53];

+  MWU_PERREGION_Type PERREGION[2];                  /*!< Unspecified                                                           */

+  __I  uint32_t  RESERVED5[64];

+  __IO uint32_t  REGIONEN;                          /*!< Enable/disable regions watch                                          */

+  __IO uint32_t  REGIONENSET;                       /*!< Enable regions watch                                                  */

+  __IO uint32_t  REGIONENCLR;                       /*!< Disable regions watch                                                 */

+  __I  uint32_t  RESERVED6[57];

+  MWU_REGION_Type REGION[4];                        /*!< Unspecified                                                           */

+  __I  uint32_t  RESERVED7[32];

+  MWU_PREGION_Type PREGION[2];                      /*!< Unspecified                                                           */

+} NRF_MWU_Type;

+

+

+/* ================================================================================ */

+/* ================                       I2S                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief Inter-IC Sound (I2S)

+  */

+

+typedef struct {                                    /*!< I2S Structure                                                         */

+  __O  uint32_t  TASKS_START;                       /*!< Starts continuous I2S transfer. Also starts MCK generator when

+                                                         this is enabled.                                                      */

+  __O  uint32_t  TASKS_STOP;                        /*!< Stops I2S transfer. Also stops MCK generator. Triggering this

+                                                         task will cause the {event:STOPPED} event to be generated.            */

+  __I  uint32_t  RESERVED0[63];

+  __IO uint32_t  EVENTS_RXPTRUPD;                   /*!< The RXD.PTR register has been copied to internal double-buffers.

+                                                         When the I2S module is started and RX is enabled, this event

+                                                          will be generated for every RXTXD.MAXCNT words that are received

+                                                          on the SDIN pin.                                                     */

+  __IO uint32_t  EVENTS_STOPPED;                    /*!< I2S transfer stopped.                                                 */

+  __I  uint32_t  RESERVED1[2];

+  __IO uint32_t  EVENTS_TXPTRUPD;                   /*!< The TDX.PTR register has been copied to internal double-buffers.

+                                                         When the I2S module is started and TX is enabled, this event

+                                                          will be generated for every RXTXD.MAXCNT words that are sent

+                                                          on the SDOUT pin.                                                    */

+  __I  uint32_t  RESERVED2[122];

+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */

+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */

+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */

+  __I  uint32_t  RESERVED3[125];

+  __IO uint32_t  ENABLE;                            /*!< Enable I2S module.                                                    */

+  I2S_CONFIG_Type CONFIG;                           /*!< Unspecified                                                           */

+  __I  uint32_t  RESERVED4[3];

+  I2S_RXD_Type RXD;                                 /*!< Unspecified                                                           */

+  __I  uint32_t  RESERVED5;

+  I2S_TXD_Type TXD;                                 /*!< Unspecified                                                           */

+  __I  uint32_t  RESERVED6[3];

+  I2S_RXTXD_Type RXTXD;                             /*!< Unspecified                                                           */

+  __I  uint32_t  RESERVED7[3];

+  I2S_PSEL_Type PSEL;                               /*!< Unspecified                                                           */

+} NRF_I2S_Type;

+

+

+/* ================================================================================ */

+/* ================                       FPU                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief FPU (FPU)

+  */

+

+typedef struct {                                    /*!< FPU Structure                                                         */

+  __I  uint32_t  UNUSED;                            /*!< Unused.                                                               */

+} NRF_FPU_Type;

+

+

+/* ================================================================================ */

+/* ================                      GPIO                      ================ */

+/* ================================================================================ */

+

+

+/**

+  * @brief GPIO Port 1 (GPIO)

+  */

+

+typedef struct {                                    /*!< GPIO Structure                                                        */

+  __I  uint32_t  RESERVED0[321];

+  __IO uint32_t  OUT;                               /*!< Write GPIO port                                                       */

+  __IO uint32_t  OUTSET;                            /*!< Set individual bits in GPIO port                                      */

+  __IO uint32_t  OUTCLR;                            /*!< Clear individual bits in GPIO port                                    */

+  __I  uint32_t  IN;                                /*!< Read GPIO port                                                        */

+  __IO uint32_t  DIR;                               /*!< Direction of GPIO pins                                                */

+  __IO uint32_t  DIRSET;                            /*!< DIR set register                                                      */

+  __IO uint32_t  DIRCLR;                            /*!< DIR clear register                                                    */

+  __IO uint32_t  LATCH;                             /*!< Latch register indicating what GPIO pins that have met the criteria

+                                                         set in the PIN_CNF[n].SENSE registers                                 */

+  __IO uint32_t  DETECTMODE;                        /*!< Select between default DETECT signal behaviour and LDETECT mode       */

+  __I  uint32_t  RESERVED1[118];

+  __IO uint32_t  PIN_CNF[32];                       /*!< Description collection[0]: Configuration of GPIO pins                 */

+} NRF_GPIO_Type;

+

+

+/* --------------------  End of section using anonymous unions  ------------------- */

+#if defined(__CC_ARM)

+  #pragma pop

+#elif defined(__ICCARM__)

+  /* leave anonymous unions enabled */

+#elif defined(__GNUC__)

+  /* anonymous unions are enabled by default */

+#elif defined(__TMS470__)

+  /* anonymous unions are enabled by default */

+#elif defined(__TASKING__)

+  #pragma warning restore

+#else

+  #warning Not supported compiler type

+#endif

+

+

+

+

+/* ================================================================================ */

+/* ================              Peripheral memory map             ================ */

+/* ================================================================================ */

+

+#define NRF_FICR_BASE                   0x10000000UL

+#define NRF_UICR_BASE                   0x10001000UL

+#define NRF_BPROT_BASE                  0x40000000UL

+#define NRF_POWER_BASE                  0x40000000UL

+#define NRF_CLOCK_BASE                  0x40000000UL

+#define NRF_AMLI_BASE                   0x40000000UL

+#define NRF_RADIO_BASE                  0x40001000UL

+#define NRF_UARTE0_BASE                 0x40002000UL

+#define NRF_UART0_BASE                  0x40002000UL

+#define NRF_SPIM0_BASE                  0x40003000UL

+#define NRF_SPIS0_BASE                  0x40003000UL

+#define NRF_TWIM0_BASE                  0x40003000UL

+#define NRF_TWIS0_BASE                  0x40003000UL

+#define NRF_SPI0_BASE                   0x40003000UL

+#define NRF_TWI0_BASE                   0x40003000UL

+#define NRF_SPIM1_BASE                  0x40004000UL

+#define NRF_SPIS1_BASE                  0x40004000UL

+#define NRF_TWIM1_BASE                  0x40004000UL

+#define NRF_TWIS1_BASE                  0x40004000UL

+#define NRF_SPI1_BASE                   0x40004000UL

+#define NRF_TWI1_BASE                   0x40004000UL

+#define NRF_NFCT_BASE                   0x40005000UL

+#define NRF_GPIOTE_BASE                 0x40006000UL

+#define NRF_SAADC_BASE                  0x40007000UL

+#define NRF_TIMER0_BASE                 0x40008000UL

+#define NRF_TIMER1_BASE                 0x40009000UL

+#define NRF_TIMER2_BASE                 0x4000A000UL

+#define NRF_RTC0_BASE                   0x4000B000UL

+#define NRF_TEMP_BASE                   0x4000C000UL

+#define NRF_RNG_BASE                    0x4000D000UL

+#define NRF_ECB_BASE                    0x4000E000UL

+#define NRF_CCM_BASE                    0x4000F000UL

+#define NRF_AAR_BASE                    0x4000F000UL

+#define NRF_WDT_BASE                    0x40010000UL

+#define NRF_RTC1_BASE                   0x40011000UL

+#define NRF_QDEC_BASE                   0x40012000UL

+#define NRF_COMP_BASE                   0x40013000UL

+#define NRF_LPCOMP_BASE                 0x40013000UL

+#define NRF_SWI0_BASE                   0x40014000UL

+#define NRF_EGU0_BASE                   0x40014000UL

+#define NRF_SWI1_BASE                   0x40015000UL

+#define NRF_EGU1_BASE                   0x40015000UL

+#define NRF_SWI2_BASE                   0x40016000UL

+#define NRF_EGU2_BASE                   0x40016000UL

+#define NRF_SWI3_BASE                   0x40017000UL

+#define NRF_EGU3_BASE                   0x40017000UL

+#define NRF_SWI4_BASE                   0x40018000UL

+#define NRF_EGU4_BASE                   0x40018000UL

+#define NRF_SWI5_BASE                   0x40019000UL

+#define NRF_EGU5_BASE                   0x40019000UL

+#define NRF_TIMER3_BASE                 0x4001A000UL

+#define NRF_TIMER4_BASE                 0x4001B000UL

+#define NRF_PWM0_BASE                   0x4001C000UL

+#define NRF_PDM_BASE                    0x4001D000UL

+#define NRF_NVMC_BASE                   0x4001E000UL

+#define NRF_PPI_BASE                    0x4001F000UL

+#define NRF_MWU_BASE                    0x40020000UL

+#define NRF_PWM1_BASE                   0x40021000UL

+#define NRF_PWM2_BASE                   0x40022000UL

+#define NRF_SPIM2_BASE                  0x40023000UL

+#define NRF_SPIS2_BASE                  0x40023000UL

+#define NRF_SPI2_BASE                   0x40023000UL

+#define NRF_RTC2_BASE                   0x40024000UL

+#define NRF_I2S_BASE                    0x40025000UL

+#define NRF_FPU_BASE                    0x40026000UL

+#define NRF_P0_BASE                     0x50000000UL

+

+

+/* ================================================================================ */

+/* ================             Peripheral declaration             ================ */

+/* ================================================================================ */

+

+#define NRF_FICR                        ((NRF_FICR_Type           *) NRF_FICR_BASE)

+#define NRF_UICR                        ((NRF_UICR_Type           *) NRF_UICR_BASE)

+#define NRF_BPROT                       ((NRF_BPROT_Type          *) NRF_BPROT_BASE)

+#define NRF_POWER                       ((NRF_POWER_Type          *) NRF_POWER_BASE)

+#define NRF_CLOCK                       ((NRF_CLOCK_Type          *) NRF_CLOCK_BASE)

+#define NRF_AMLI                        ((NRF_AMLI_Type           *) NRF_AMLI_BASE)

+#define NRF_RADIO                       ((NRF_RADIO_Type          *) NRF_RADIO_BASE)

+#define NRF_UARTE0                      ((NRF_UARTE_Type          *) NRF_UARTE0_BASE)

+#define NRF_UART0                       ((NRF_UART_Type           *) NRF_UART0_BASE)

+#define NRF_SPIM0                       ((NRF_SPIM_Type           *) NRF_SPIM0_BASE)

+#define NRF_SPIS0                       ((NRF_SPIS_Type           *) NRF_SPIS0_BASE)

+#define NRF_TWIM0                       ((NRF_TWIM_Type           *) NRF_TWIM0_BASE)

+#define NRF_TWIS0                       ((NRF_TWIS_Type           *) NRF_TWIS0_BASE)

+#define NRF_SPI0                        ((NRF_SPI_Type            *) NRF_SPI0_BASE)

+#define NRF_TWI0                        ((NRF_TWI_Type            *) NRF_TWI0_BASE)

+#define NRF_SPIM1                       ((NRF_SPIM_Type           *) NRF_SPIM1_BASE)

+#define NRF_SPIS1                       ((NRF_SPIS_Type           *) NRF_SPIS1_BASE)

+#define NRF_TWIM1                       ((NRF_TWIM_Type           *) NRF_TWIM1_BASE)

+#define NRF_TWIS1                       ((NRF_TWIS_Type           *) NRF_TWIS1_BASE)

+#define NRF_SPI1                        ((NRF_SPI_Type            *) NRF_SPI1_BASE)

+#define NRF_TWI1                        ((NRF_TWI_Type            *) NRF_TWI1_BASE)

+#define NRF_NFCT                        ((NRF_NFCT_Type           *) NRF_NFCT_BASE)

+#define NRF_GPIOTE                      ((NRF_GPIOTE_Type         *) NRF_GPIOTE_BASE)

+#define NRF_SAADC                       ((NRF_SAADC_Type          *) NRF_SAADC_BASE)

+#define NRF_TIMER0                      ((NRF_TIMER_Type          *) NRF_TIMER0_BASE)

+#define NRF_TIMER1                      ((NRF_TIMER_Type          *) NRF_TIMER1_BASE)

+#define NRF_TIMER2                      ((NRF_TIMER_Type          *) NRF_TIMER2_BASE)

+#define NRF_RTC0                        ((NRF_RTC_Type            *) NRF_RTC0_BASE)

+#define NRF_TEMP                        ((NRF_TEMP_Type           *) NRF_TEMP_BASE)

+#define NRF_RNG                         ((NRF_RNG_Type            *) NRF_RNG_BASE)

+#define NRF_ECB                         ((NRF_ECB_Type            *) NRF_ECB_BASE)

+#define NRF_CCM                         ((NRF_CCM_Type            *) NRF_CCM_BASE)

+#define NRF_AAR                         ((NRF_AAR_Type            *) NRF_AAR_BASE)

+#define NRF_WDT                         ((NRF_WDT_Type            *) NRF_WDT_BASE)

+#define NRF_RTC1                        ((NRF_RTC_Type            *) NRF_RTC1_BASE)

+#define NRF_QDEC                        ((NRF_QDEC_Type           *) NRF_QDEC_BASE)

+#define NRF_COMP                        ((NRF_COMP_Type           *) NRF_COMP_BASE)

+#define NRF_LPCOMP                      ((NRF_LPCOMP_Type         *) NRF_LPCOMP_BASE)

+#define NRF_SWI0                        ((NRF_SWI_Type            *) NRF_SWI0_BASE)

+#define NRF_EGU0                        ((NRF_EGU_Type            *) NRF_EGU0_BASE)

+#define NRF_SWI1                        ((NRF_SWI_Type            *) NRF_SWI1_BASE)

+#define NRF_EGU1                        ((NRF_EGU_Type            *) NRF_EGU1_BASE)

+#define NRF_SWI2                        ((NRF_SWI_Type            *) NRF_SWI2_BASE)

+#define NRF_EGU2                        ((NRF_EGU_Type            *) NRF_EGU2_BASE)

+#define NRF_SWI3                        ((NRF_SWI_Type            *) NRF_SWI3_BASE)

+#define NRF_EGU3                        ((NRF_EGU_Type            *) NRF_EGU3_BASE)

+#define NRF_SWI4                        ((NRF_SWI_Type            *) NRF_SWI4_BASE)

+#define NRF_EGU4                        ((NRF_EGU_Type            *) NRF_EGU4_BASE)

+#define NRF_SWI5                        ((NRF_SWI_Type            *) NRF_SWI5_BASE)

+#define NRF_EGU5                        ((NRF_EGU_Type            *) NRF_EGU5_BASE)

+#define NRF_TIMER3                      ((NRF_TIMER_Type          *) NRF_TIMER3_BASE)

+#define NRF_TIMER4                      ((NRF_TIMER_Type          *) NRF_TIMER4_BASE)

+#define NRF_PWM0                        ((NRF_PWM_Type            *) NRF_PWM0_BASE)

+#define NRF_PDM                         ((NRF_PDM_Type            *) NRF_PDM_BASE)

+#define NRF_NVMC                        ((NRF_NVMC_Type           *) NRF_NVMC_BASE)

+#define NRF_PPI                         ((NRF_PPI_Type            *) NRF_PPI_BASE)

+#define NRF_MWU                         ((NRF_MWU_Type            *) NRF_MWU_BASE)

+#define NRF_PWM1                        ((NRF_PWM_Type            *) NRF_PWM1_BASE)

+#define NRF_PWM2                        ((NRF_PWM_Type            *) NRF_PWM2_BASE)

+#define NRF_SPIM2                       ((NRF_SPIM_Type           *) NRF_SPIM2_BASE)

+#define NRF_SPIS2                       ((NRF_SPIS_Type           *) NRF_SPIS2_BASE)

+#define NRF_SPI2                        ((NRF_SPI_Type            *) NRF_SPI2_BASE)

+#define NRF_RTC2                        ((NRF_RTC_Type            *) NRF_RTC2_BASE)

+#define NRF_I2S                         ((NRF_I2S_Type            *) NRF_I2S_BASE)

+#define NRF_FPU                         ((NRF_FPU_Type            *) NRF_FPU_BASE)

+#define NRF_P0                          ((NRF_GPIO_Type           *) NRF_P0_BASE)

+

+

+/** @} */ /* End of group Device_Peripheral_Registers */

+/** @} */ /* End of group nrf52 */

+/** @} */ /* End of group Nordic Semiconductor */

+

+#ifdef __cplusplus

+}

+#endif

+

+

+#endif  /* nrf52_H */

+

diff --git a/os/hal/ports/NRF5/NRF52832/nrf52_bitfields.h b/os/hal/ports/NRF5/NRF52832/nrf52_bitfields.h
new file mode 100644
index 0000000..ae959d4
--- /dev/null
+++ b/os/hal/ports/NRF5/NRF52832/nrf52_bitfields.h
@@ -0,0 +1,14861 @@
+/* Copyright (c) 2015, Nordic Semiconductor ASA

+ * All rights reserved.

+ *

+ * Redistribution and use in source and binary forms, with or without

+ * modification, are permitted provided that the following conditions are met:

+ *

+ *   * Redistributions of source code must retain the above copyright notice, this

+ *     list of conditions and the following disclaimer.

+ *

+ *   * Redistributions in binary form must reproduce the above copyright notice,

+ *     this list of conditions and the following disclaimer in the documentation

+ *     and/or other materials provided with the distribution.

+ *

+ *   * Neither the name of Nordic Semiconductor ASA nor the names of its

+ *     contributors may be used to endorse or promote products derived from

+ *     this software without specific prior written permission.

+ *

+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE

+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

+ *

+ */

+#ifndef __NRF52_BITS_H

+#define __NRF52_BITS_H

+

+/*lint ++flb "Enter library region" */

+

+/* Peripheral: AAR */

+/* Description: Accelerated Address Resolver */

+

+/* Register: AAR_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */

+#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */

+#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */

+#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */

+#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */

+#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */

+

+/* Bit 1 : Write '1' to Enable interrupt for RESOLVED event */

+#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */

+#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */

+#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */

+#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */

+#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */

+

+/* Bit 0 : Write '1' to Enable interrupt for END event */

+#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */

+#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */

+#define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */

+#define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */

+#define AAR_INTENSET_END_Set (1UL) /*!< Enable */

+

+/* Register: AAR_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */

+#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */

+#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */

+#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */

+#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */

+#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */

+

+/* Bit 1 : Write '1' to Disable interrupt for RESOLVED event */

+#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */

+#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */

+#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */

+#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */

+#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */

+

+/* Bit 0 : Write '1' to Disable interrupt for END event */

+#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */

+#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */

+#define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */

+#define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */

+#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */

+

+/* Register: AAR_STATUS */

+/* Description: Resolution status */

+

+/* Bits 3..0 : The IRK that was used last time an address was resolved */

+#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */

+#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */

+

+/* Register: AAR_ENABLE */

+/* Description: Enable AAR */

+

+/* Bits 1..0 : Enable or disable AAR */

+#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */

+#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */

+#define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */

+#define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */

+

+/* Register: AAR_NIRK */

+/* Description: Number of IRKs */

+

+/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */

+#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */

+#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */

+

+/* Register: AAR_IRKPTR */

+/* Description: Pointer to IRK data structure */

+

+/* Bits 31..0 : Pointer to the IRK data structure */

+#define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */

+#define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */

+

+/* Register: AAR_ADDRPTR */

+/* Description: Pointer to the resolvable address */

+

+/* Bits 31..0 : Pointer to the resolvable address (6-bytes) */

+#define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */

+#define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */

+

+/* Register: AAR_SCRATCHPTR */

+/* Description: Pointer to data area used for temporary storage */

+

+/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */

+#define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */

+#define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */

+

+

+/* Peripheral: AMLI */

+/* Description: AHB Multi-Layer Interface */

+

+/* Register: AMLI_RAMPRI_CPU0 */

+/* Description: AHB bus master priority register for CPU0 */

+

+/* Bits 31..28 : Priority register for RAM AHB slave 7 */

+#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */

+#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */

+#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_CPU0_RAM7_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_CPU0_RAM7_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_CPU0_RAM7_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_CPU0_RAM7_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_CPU0_RAM7_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_CPU0_RAM7_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_CPU0_RAM7_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_CPU0_RAM7_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 27..24 : Priority register for RAM AHB slave 6 */

+#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */

+#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */

+#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_CPU0_RAM6_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_CPU0_RAM6_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_CPU0_RAM6_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_CPU0_RAM6_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_CPU0_RAM6_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_CPU0_RAM6_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_CPU0_RAM6_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_CPU0_RAM6_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 23..20 : Priority register for RAM AHB slave 5 */

+#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */

+#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */

+#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_CPU0_RAM5_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_CPU0_RAM5_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_CPU0_RAM5_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_CPU0_RAM5_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_CPU0_RAM5_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_CPU0_RAM5_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_CPU0_RAM5_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_CPU0_RAM5_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 19..16 : Priority register for RAM AHB slave 4 */

+#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */

+#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */

+#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_CPU0_RAM4_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_CPU0_RAM4_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_CPU0_RAM4_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_CPU0_RAM4_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_CPU0_RAM4_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_CPU0_RAM4_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_CPU0_RAM4_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_CPU0_RAM4_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 15..12 : Priority register for RAM AHB slave 3 */

+#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */

+#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */

+#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_CPU0_RAM3_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_CPU0_RAM3_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_CPU0_RAM3_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_CPU0_RAM3_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_CPU0_RAM3_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_CPU0_RAM3_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_CPU0_RAM3_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_CPU0_RAM3_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 11..8 : Priority register for RAM AHB slave 2 */

+#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */

+#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */

+#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_CPU0_RAM2_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_CPU0_RAM2_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_CPU0_RAM2_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_CPU0_RAM2_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_CPU0_RAM2_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_CPU0_RAM2_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_CPU0_RAM2_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_CPU0_RAM2_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 7..4 : Priority register for RAM AHB slave 1 */

+#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */

+#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */

+#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_CPU0_RAM1_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_CPU0_RAM1_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_CPU0_RAM1_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_CPU0_RAM1_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_CPU0_RAM1_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_CPU0_RAM1_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_CPU0_RAM1_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_CPU0_RAM1_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 3..0 : Priority register for RAM AHB slave 0 */

+#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */

+#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */

+#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_CPU0_RAM0_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_CPU0_RAM0_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_CPU0_RAM0_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_CPU0_RAM0_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_CPU0_RAM0_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_CPU0_RAM0_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_CPU0_RAM0_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_CPU0_RAM0_Pri15 (15UL) /*!< Priority 15 */

+

+/* Register: AMLI_RAMPRI_SPIS1 */

+/* Description: AHB bus master priority register for SPIM1, SPIS1, TWIM1 and TWIS1 */

+

+/* Bits 31..28 : Priority register for RAM AHB slave 7 */

+#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */

+#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */

+#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SPIS1_RAM7_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SPIS1_RAM7_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SPIS1_RAM7_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SPIS1_RAM7_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SPIS1_RAM7_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SPIS1_RAM7_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SPIS1_RAM7_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SPIS1_RAM7_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 27..24 : Priority register for RAM AHB slave 6 */

+#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */

+#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */

+#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SPIS1_RAM6_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SPIS1_RAM6_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SPIS1_RAM6_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SPIS1_RAM6_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SPIS1_RAM6_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SPIS1_RAM6_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SPIS1_RAM6_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SPIS1_RAM6_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 23..20 : Priority register for RAM AHB slave 5 */

+#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */

+#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */

+#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SPIS1_RAM5_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SPIS1_RAM5_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SPIS1_RAM5_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SPIS1_RAM5_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SPIS1_RAM5_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SPIS1_RAM5_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SPIS1_RAM5_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SPIS1_RAM5_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 19..16 : Priority register for RAM AHB slave 4 */

+#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */

+#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */

+#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SPIS1_RAM4_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SPIS1_RAM4_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SPIS1_RAM4_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SPIS1_RAM4_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SPIS1_RAM4_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SPIS1_RAM4_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SPIS1_RAM4_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SPIS1_RAM4_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 15..12 : Priority register for RAM AHB slave 3 */

+#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */

+#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */

+#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SPIS1_RAM3_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SPIS1_RAM3_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SPIS1_RAM3_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SPIS1_RAM3_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SPIS1_RAM3_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SPIS1_RAM3_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SPIS1_RAM3_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SPIS1_RAM3_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 11..8 : Priority register for RAM AHB slave 2 */

+#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */

+#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */

+#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SPIS1_RAM2_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SPIS1_RAM2_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SPIS1_RAM2_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SPIS1_RAM2_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SPIS1_RAM2_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SPIS1_RAM2_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SPIS1_RAM2_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SPIS1_RAM2_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 7..4 : Priority register for RAM AHB slave 1 */

+#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */

+#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */

+#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SPIS1_RAM1_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SPIS1_RAM1_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SPIS1_RAM1_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SPIS1_RAM1_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SPIS1_RAM1_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SPIS1_RAM1_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SPIS1_RAM1_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SPIS1_RAM1_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 3..0 : Priority register for RAM AHB slave 0 */

+#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */

+#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */

+#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SPIS1_RAM0_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SPIS1_RAM0_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SPIS1_RAM0_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SPIS1_RAM0_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SPIS1_RAM0_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SPIS1_RAM0_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SPIS1_RAM0_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SPIS1_RAM0_Pri15 (15UL) /*!< Priority 15 */

+

+/* Register: AMLI_RAMPRI_RADIO */

+/* Description: AHB bus master priority register for RADIO */

+

+/* Bits 31..28 : Priority register for RAM AHB slave 7 */

+#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */

+#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */

+#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_RADIO_RAM7_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_RADIO_RAM7_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_RADIO_RAM7_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_RADIO_RAM7_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_RADIO_RAM7_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_RADIO_RAM7_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_RADIO_RAM7_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_RADIO_RAM7_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 27..24 : Priority register for RAM AHB slave 6 */

+#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */

+#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */

+#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_RADIO_RAM6_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_RADIO_RAM6_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_RADIO_RAM6_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_RADIO_RAM6_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_RADIO_RAM6_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_RADIO_RAM6_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_RADIO_RAM6_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_RADIO_RAM6_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 23..20 : Priority register for RAM AHB slave 5 */

+#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */

+#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */

+#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_RADIO_RAM5_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_RADIO_RAM5_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_RADIO_RAM5_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_RADIO_RAM5_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_RADIO_RAM5_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_RADIO_RAM5_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_RADIO_RAM5_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_RADIO_RAM5_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 19..16 : Priority register for RAM AHB slave 4 */

+#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */

+#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */

+#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_RADIO_RAM4_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_RADIO_RAM4_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_RADIO_RAM4_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_RADIO_RAM4_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_RADIO_RAM4_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_RADIO_RAM4_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_RADIO_RAM4_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_RADIO_RAM4_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 15..12 : Priority register for RAM AHB slave 3 */

+#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */

+#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */

+#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_RADIO_RAM3_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_RADIO_RAM3_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_RADIO_RAM3_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_RADIO_RAM3_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_RADIO_RAM3_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_RADIO_RAM3_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_RADIO_RAM3_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_RADIO_RAM3_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 11..8 : Priority register for RAM AHB slave 2 */

+#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */

+#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */

+#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_RADIO_RAM2_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_RADIO_RAM2_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_RADIO_RAM2_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_RADIO_RAM2_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_RADIO_RAM2_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_RADIO_RAM2_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_RADIO_RAM2_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_RADIO_RAM2_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 7..4 : Priority register for RAM AHB slave 1 */

+#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */

+#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */

+#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_RADIO_RAM1_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_RADIO_RAM1_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_RADIO_RAM1_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_RADIO_RAM1_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_RADIO_RAM1_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_RADIO_RAM1_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_RADIO_RAM1_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_RADIO_RAM1_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 3..0 : Priority register for RAM AHB slave 0 */

+#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */

+#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */

+#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_RADIO_RAM0_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_RADIO_RAM0_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_RADIO_RAM0_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_RADIO_RAM0_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_RADIO_RAM0_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_RADIO_RAM0_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_RADIO_RAM0_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_RADIO_RAM0_Pri15 (15UL) /*!< Priority 15 */

+

+/* Register: AMLI_RAMPRI_ECB */

+/* Description: AHB bus master priority register for ECB */

+

+/* Bits 31..28 : Priority register for RAM AHB slave 7 */

+#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */

+#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */

+#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_ECB_RAM7_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_ECB_RAM7_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_ECB_RAM7_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_ECB_RAM7_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_ECB_RAM7_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_ECB_RAM7_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_ECB_RAM7_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_ECB_RAM7_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_ECB_RAM7_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_ECB_RAM7_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_ECB_RAM7_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_ECB_RAM7_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_ECB_RAM7_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_ECB_RAM7_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_ECB_RAM7_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 27..24 : Priority register for RAM AHB slave 6 */

+#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */

+#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */

+#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_ECB_RAM6_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_ECB_RAM6_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_ECB_RAM6_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_ECB_RAM6_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_ECB_RAM6_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_ECB_RAM6_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_ECB_RAM6_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_ECB_RAM6_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_ECB_RAM6_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_ECB_RAM6_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_ECB_RAM6_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_ECB_RAM6_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_ECB_RAM6_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_ECB_RAM6_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_ECB_RAM6_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 23..20 : Priority register for RAM AHB slave 5 */

+#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */

+#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */

+#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_ECB_RAM5_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_ECB_RAM5_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_ECB_RAM5_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_ECB_RAM5_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_ECB_RAM5_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_ECB_RAM5_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_ECB_RAM5_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_ECB_RAM5_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_ECB_RAM5_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_ECB_RAM5_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_ECB_RAM5_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_ECB_RAM5_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_ECB_RAM5_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_ECB_RAM5_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_ECB_RAM5_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 19..16 : Priority register for RAM AHB slave 4 */

+#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */

+#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */

+#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_ECB_RAM4_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_ECB_RAM4_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_ECB_RAM4_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_ECB_RAM4_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_ECB_RAM4_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_ECB_RAM4_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_ECB_RAM4_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_ECB_RAM4_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_ECB_RAM4_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_ECB_RAM4_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_ECB_RAM4_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_ECB_RAM4_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_ECB_RAM4_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_ECB_RAM4_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_ECB_RAM4_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 15..12 : Priority register for RAM AHB slave 3 */

+#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */

+#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */

+#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_ECB_RAM3_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_ECB_RAM3_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_ECB_RAM3_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_ECB_RAM3_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_ECB_RAM3_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_ECB_RAM3_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_ECB_RAM3_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_ECB_RAM3_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_ECB_RAM3_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_ECB_RAM3_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_ECB_RAM3_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_ECB_RAM3_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_ECB_RAM3_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_ECB_RAM3_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_ECB_RAM3_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 11..8 : Priority register for RAM AHB slave 2 */

+#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */

+#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */

+#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_ECB_RAM2_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_ECB_RAM2_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_ECB_RAM2_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_ECB_RAM2_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_ECB_RAM2_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_ECB_RAM2_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_ECB_RAM2_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_ECB_RAM2_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_ECB_RAM2_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_ECB_RAM2_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_ECB_RAM2_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_ECB_RAM2_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_ECB_RAM2_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_ECB_RAM2_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_ECB_RAM2_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 7..4 : Priority register for RAM AHB slave 1 */

+#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */

+#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */

+#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_ECB_RAM1_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_ECB_RAM1_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_ECB_RAM1_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_ECB_RAM1_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_ECB_RAM1_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_ECB_RAM1_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_ECB_RAM1_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_ECB_RAM1_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_ECB_RAM1_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_ECB_RAM1_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_ECB_RAM1_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_ECB_RAM1_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_ECB_RAM1_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_ECB_RAM1_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_ECB_RAM1_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 3..0 : Priority register for RAM AHB slave 0 */

+#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */

+#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */

+#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_ECB_RAM0_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_ECB_RAM0_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_ECB_RAM0_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_ECB_RAM0_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_ECB_RAM0_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_ECB_RAM0_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_ECB_RAM0_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_ECB_RAM0_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_ECB_RAM0_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_ECB_RAM0_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_ECB_RAM0_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_ECB_RAM0_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_ECB_RAM0_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_ECB_RAM0_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_ECB_RAM0_Pri15 (15UL) /*!< Priority 15 */

+

+/* Register: AMLI_RAMPRI_CCM */

+/* Description: AHB bus master priority register for CCM */

+

+/* Bits 31..28 : Priority register for RAM AHB slave 7 */

+#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */

+#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */

+#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_CCM_RAM7_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_CCM_RAM7_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_CCM_RAM7_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_CCM_RAM7_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_CCM_RAM7_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_CCM_RAM7_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_CCM_RAM7_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_CCM_RAM7_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_CCM_RAM7_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_CCM_RAM7_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_CCM_RAM7_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_CCM_RAM7_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_CCM_RAM7_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_CCM_RAM7_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_CCM_RAM7_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 27..24 : Priority register for RAM AHB slave 6 */

+#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */

+#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */

+#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_CCM_RAM6_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_CCM_RAM6_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_CCM_RAM6_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_CCM_RAM6_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_CCM_RAM6_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_CCM_RAM6_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_CCM_RAM6_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_CCM_RAM6_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_CCM_RAM6_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_CCM_RAM6_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_CCM_RAM6_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_CCM_RAM6_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_CCM_RAM6_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_CCM_RAM6_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_CCM_RAM6_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 23..20 : Priority register for RAM AHB slave 5 */

+#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */

+#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */

+#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_CCM_RAM5_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_CCM_RAM5_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_CCM_RAM5_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_CCM_RAM5_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_CCM_RAM5_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_CCM_RAM5_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_CCM_RAM5_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_CCM_RAM5_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_CCM_RAM5_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_CCM_RAM5_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_CCM_RAM5_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_CCM_RAM5_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_CCM_RAM5_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_CCM_RAM5_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_CCM_RAM5_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 19..16 : Priority register for RAM AHB slave 4 */

+#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */

+#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */

+#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_CCM_RAM4_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_CCM_RAM4_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_CCM_RAM4_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_CCM_RAM4_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_CCM_RAM4_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_CCM_RAM4_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_CCM_RAM4_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_CCM_RAM4_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_CCM_RAM4_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_CCM_RAM4_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_CCM_RAM4_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_CCM_RAM4_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_CCM_RAM4_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_CCM_RAM4_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_CCM_RAM4_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 15..12 : Priority register for RAM AHB slave 3 */

+#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */

+#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */

+#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_CCM_RAM3_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_CCM_RAM3_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_CCM_RAM3_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_CCM_RAM3_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_CCM_RAM3_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_CCM_RAM3_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_CCM_RAM3_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_CCM_RAM3_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_CCM_RAM3_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_CCM_RAM3_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_CCM_RAM3_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_CCM_RAM3_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_CCM_RAM3_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_CCM_RAM3_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_CCM_RAM3_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 11..8 : Priority register for RAM AHB slave 2 */

+#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */

+#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */

+#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_CCM_RAM2_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_CCM_RAM2_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_CCM_RAM2_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_CCM_RAM2_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_CCM_RAM2_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_CCM_RAM2_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_CCM_RAM2_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_CCM_RAM2_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_CCM_RAM2_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_CCM_RAM2_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_CCM_RAM2_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_CCM_RAM2_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_CCM_RAM2_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_CCM_RAM2_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_CCM_RAM2_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 7..4 : Priority register for RAM AHB slave 1 */

+#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */

+#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */

+#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_CCM_RAM1_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_CCM_RAM1_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_CCM_RAM1_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_CCM_RAM1_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_CCM_RAM1_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_CCM_RAM1_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_CCM_RAM1_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_CCM_RAM1_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_CCM_RAM1_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_CCM_RAM1_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_CCM_RAM1_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_CCM_RAM1_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_CCM_RAM1_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_CCM_RAM1_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_CCM_RAM1_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 3..0 : Priority register for RAM AHB slave 0 */

+#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */

+#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */

+#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_CCM_RAM0_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_CCM_RAM0_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_CCM_RAM0_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_CCM_RAM0_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_CCM_RAM0_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_CCM_RAM0_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_CCM_RAM0_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_CCM_RAM0_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_CCM_RAM0_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_CCM_RAM0_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_CCM_RAM0_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_CCM_RAM0_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_CCM_RAM0_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_CCM_RAM0_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_CCM_RAM0_Pri15 (15UL) /*!< Priority 15 */

+

+/* Register: AMLI_RAMPRI_AAR */

+/* Description: AHB bus master priority register for AAR */

+

+/* Bits 31..28 : Priority register for RAM AHB slave 7 */

+#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */

+#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */

+#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_AAR_RAM7_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_AAR_RAM7_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_AAR_RAM7_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_AAR_RAM7_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_AAR_RAM7_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_AAR_RAM7_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_AAR_RAM7_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_AAR_RAM7_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_AAR_RAM7_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_AAR_RAM7_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_AAR_RAM7_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_AAR_RAM7_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_AAR_RAM7_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_AAR_RAM7_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_AAR_RAM7_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 27..24 : Priority register for RAM AHB slave 6 */

+#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */

+#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */

+#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_AAR_RAM6_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_AAR_RAM6_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_AAR_RAM6_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_AAR_RAM6_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_AAR_RAM6_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_AAR_RAM6_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_AAR_RAM6_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_AAR_RAM6_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_AAR_RAM6_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_AAR_RAM6_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_AAR_RAM6_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_AAR_RAM6_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_AAR_RAM6_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_AAR_RAM6_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_AAR_RAM6_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 23..20 : Priority register for RAM AHB slave 5 */

+#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */

+#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */

+#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_AAR_RAM5_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_AAR_RAM5_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_AAR_RAM5_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_AAR_RAM5_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_AAR_RAM5_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_AAR_RAM5_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_AAR_RAM5_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_AAR_RAM5_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_AAR_RAM5_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_AAR_RAM5_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_AAR_RAM5_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_AAR_RAM5_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_AAR_RAM5_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_AAR_RAM5_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_AAR_RAM5_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 19..16 : Priority register for RAM AHB slave 4 */

+#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */

+#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */

+#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_AAR_RAM4_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_AAR_RAM4_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_AAR_RAM4_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_AAR_RAM4_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_AAR_RAM4_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_AAR_RAM4_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_AAR_RAM4_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_AAR_RAM4_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_AAR_RAM4_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_AAR_RAM4_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_AAR_RAM4_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_AAR_RAM4_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_AAR_RAM4_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_AAR_RAM4_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_AAR_RAM4_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 15..12 : Priority register for RAM AHB slave 3 */

+#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */

+#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */

+#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_AAR_RAM3_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_AAR_RAM3_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_AAR_RAM3_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_AAR_RAM3_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_AAR_RAM3_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_AAR_RAM3_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_AAR_RAM3_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_AAR_RAM3_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_AAR_RAM3_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_AAR_RAM3_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_AAR_RAM3_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_AAR_RAM3_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_AAR_RAM3_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_AAR_RAM3_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_AAR_RAM3_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 11..8 : Priority register for RAM AHB slave 2 */

+#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */

+#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */

+#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_AAR_RAM2_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_AAR_RAM2_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_AAR_RAM2_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_AAR_RAM2_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_AAR_RAM2_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_AAR_RAM2_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_AAR_RAM2_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_AAR_RAM2_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_AAR_RAM2_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_AAR_RAM2_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_AAR_RAM2_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_AAR_RAM2_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_AAR_RAM2_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_AAR_RAM2_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_AAR_RAM2_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 7..4 : Priority register for RAM AHB slave 1 */

+#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */

+#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */

+#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_AAR_RAM1_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_AAR_RAM1_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_AAR_RAM1_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_AAR_RAM1_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_AAR_RAM1_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_AAR_RAM1_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_AAR_RAM1_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_AAR_RAM1_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_AAR_RAM1_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_AAR_RAM1_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_AAR_RAM1_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_AAR_RAM1_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_AAR_RAM1_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_AAR_RAM1_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_AAR_RAM1_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 3..0 : Priority register for RAM AHB slave 0 */

+#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */

+#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */

+#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_AAR_RAM0_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_AAR_RAM0_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_AAR_RAM0_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_AAR_RAM0_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_AAR_RAM0_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_AAR_RAM0_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_AAR_RAM0_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_AAR_RAM0_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_AAR_RAM0_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_AAR_RAM0_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_AAR_RAM0_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_AAR_RAM0_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_AAR_RAM0_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_AAR_RAM0_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_AAR_RAM0_Pri15 (15UL) /*!< Priority 15 */

+

+/* Register: AMLI_RAMPRI_SAADC */

+/* Description: AHB bus master priority register for SAADC */

+

+/* Bits 31..28 : Priority register for RAM AHB slave 7 */

+#define AMLI_RAMPRI_SAADC_RAM7_Pos (28UL) /*!< Position of RAM7 field. */

+#define AMLI_RAMPRI_SAADC_RAM7_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM7_Pos) /*!< Bit mask of RAM7 field. */

+#define AMLI_RAMPRI_SAADC_RAM7_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SAADC_RAM7_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SAADC_RAM7_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SAADC_RAM7_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SAADC_RAM7_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SAADC_RAM7_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SAADC_RAM7_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SAADC_RAM7_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SAADC_RAM7_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SAADC_RAM7_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SAADC_RAM7_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SAADC_RAM7_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SAADC_RAM7_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SAADC_RAM7_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SAADC_RAM7_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SAADC_RAM7_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 27..24 : Priority register for RAM AHB slave 6 */

+#define AMLI_RAMPRI_SAADC_RAM6_Pos (24UL) /*!< Position of RAM6 field. */

+#define AMLI_RAMPRI_SAADC_RAM6_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM6_Pos) /*!< Bit mask of RAM6 field. */

+#define AMLI_RAMPRI_SAADC_RAM6_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SAADC_RAM6_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SAADC_RAM6_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SAADC_RAM6_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SAADC_RAM6_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SAADC_RAM6_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SAADC_RAM6_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SAADC_RAM6_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SAADC_RAM6_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SAADC_RAM6_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SAADC_RAM6_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SAADC_RAM6_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SAADC_RAM6_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SAADC_RAM6_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SAADC_RAM6_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SAADC_RAM6_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 23..20 : Priority register for RAM AHB slave 5 */

+#define AMLI_RAMPRI_SAADC_RAM5_Pos (20UL) /*!< Position of RAM5 field. */

+#define AMLI_RAMPRI_SAADC_RAM5_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM5_Pos) /*!< Bit mask of RAM5 field. */

+#define AMLI_RAMPRI_SAADC_RAM5_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SAADC_RAM5_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SAADC_RAM5_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SAADC_RAM5_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SAADC_RAM5_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SAADC_RAM5_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SAADC_RAM5_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SAADC_RAM5_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SAADC_RAM5_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SAADC_RAM5_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SAADC_RAM5_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SAADC_RAM5_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SAADC_RAM5_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SAADC_RAM5_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SAADC_RAM5_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SAADC_RAM5_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 19..16 : Priority register for RAM AHB slave 4 */

+#define AMLI_RAMPRI_SAADC_RAM4_Pos (16UL) /*!< Position of RAM4 field. */

+#define AMLI_RAMPRI_SAADC_RAM4_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM4_Pos) /*!< Bit mask of RAM4 field. */

+#define AMLI_RAMPRI_SAADC_RAM4_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SAADC_RAM4_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SAADC_RAM4_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SAADC_RAM4_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SAADC_RAM4_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SAADC_RAM4_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SAADC_RAM4_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SAADC_RAM4_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SAADC_RAM4_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SAADC_RAM4_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SAADC_RAM4_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SAADC_RAM4_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SAADC_RAM4_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SAADC_RAM4_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SAADC_RAM4_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SAADC_RAM4_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 15..12 : Priority register for RAM AHB slave 3 */

+#define AMLI_RAMPRI_SAADC_RAM3_Pos (12UL) /*!< Position of RAM3 field. */

+#define AMLI_RAMPRI_SAADC_RAM3_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM3_Pos) /*!< Bit mask of RAM3 field. */

+#define AMLI_RAMPRI_SAADC_RAM3_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SAADC_RAM3_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SAADC_RAM3_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SAADC_RAM3_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SAADC_RAM3_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SAADC_RAM3_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SAADC_RAM3_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SAADC_RAM3_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SAADC_RAM3_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SAADC_RAM3_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SAADC_RAM3_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SAADC_RAM3_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SAADC_RAM3_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SAADC_RAM3_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SAADC_RAM3_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SAADC_RAM3_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 11..8 : Priority register for RAM AHB slave 2 */

+#define AMLI_RAMPRI_SAADC_RAM2_Pos (8UL) /*!< Position of RAM2 field. */

+#define AMLI_RAMPRI_SAADC_RAM2_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM2_Pos) /*!< Bit mask of RAM2 field. */

+#define AMLI_RAMPRI_SAADC_RAM2_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SAADC_RAM2_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SAADC_RAM2_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SAADC_RAM2_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SAADC_RAM2_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SAADC_RAM2_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SAADC_RAM2_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SAADC_RAM2_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SAADC_RAM2_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SAADC_RAM2_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SAADC_RAM2_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SAADC_RAM2_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SAADC_RAM2_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SAADC_RAM2_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SAADC_RAM2_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SAADC_RAM2_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 7..4 : Priority register for RAM AHB slave 1 */

+#define AMLI_RAMPRI_SAADC_RAM1_Pos (4UL) /*!< Position of RAM1 field. */

+#define AMLI_RAMPRI_SAADC_RAM1_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM1_Pos) /*!< Bit mask of RAM1 field. */

+#define AMLI_RAMPRI_SAADC_RAM1_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SAADC_RAM1_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SAADC_RAM1_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SAADC_RAM1_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SAADC_RAM1_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SAADC_RAM1_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SAADC_RAM1_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SAADC_RAM1_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SAADC_RAM1_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SAADC_RAM1_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SAADC_RAM1_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SAADC_RAM1_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SAADC_RAM1_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SAADC_RAM1_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SAADC_RAM1_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SAADC_RAM1_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 3..0 : Priority register for RAM AHB slave 0 */

+#define AMLI_RAMPRI_SAADC_RAM0_Pos (0UL) /*!< Position of RAM0 field. */

+#define AMLI_RAMPRI_SAADC_RAM0_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM0_Pos) /*!< Bit mask of RAM0 field. */

+#define AMLI_RAMPRI_SAADC_RAM0_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SAADC_RAM0_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SAADC_RAM0_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SAADC_RAM0_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SAADC_RAM0_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SAADC_RAM0_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SAADC_RAM0_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SAADC_RAM0_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SAADC_RAM0_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SAADC_RAM0_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SAADC_RAM0_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SAADC_RAM0_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SAADC_RAM0_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SAADC_RAM0_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SAADC_RAM0_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SAADC_RAM0_Pri15 (15UL) /*!< Priority 15 */

+

+/* Register: AMLI_RAMPRI_UARTE */

+/* Description: AHB bus master priority register for UARTE */

+

+/* Bits 31..28 : Priority register for RAM AHB slave 7 */

+#define AMLI_RAMPRI_UARTE_RAM7_Pos (28UL) /*!< Position of RAM7 field. */

+#define AMLI_RAMPRI_UARTE_RAM7_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM7_Pos) /*!< Bit mask of RAM7 field. */

+#define AMLI_RAMPRI_UARTE_RAM7_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_UARTE_RAM7_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_UARTE_RAM7_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_UARTE_RAM7_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_UARTE_RAM7_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_UARTE_RAM7_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_UARTE_RAM7_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_UARTE_RAM7_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_UARTE_RAM7_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_UARTE_RAM7_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_UARTE_RAM7_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_UARTE_RAM7_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_UARTE_RAM7_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_UARTE_RAM7_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_UARTE_RAM7_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_UARTE_RAM7_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 27..24 : Priority register for RAM AHB slave 6 */

+#define AMLI_RAMPRI_UARTE_RAM6_Pos (24UL) /*!< Position of RAM6 field. */

+#define AMLI_RAMPRI_UARTE_RAM6_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM6_Pos) /*!< Bit mask of RAM6 field. */

+#define AMLI_RAMPRI_UARTE_RAM6_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_UARTE_RAM6_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_UARTE_RAM6_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_UARTE_RAM6_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_UARTE_RAM6_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_UARTE_RAM6_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_UARTE_RAM6_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_UARTE_RAM6_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_UARTE_RAM6_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_UARTE_RAM6_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_UARTE_RAM6_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_UARTE_RAM6_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_UARTE_RAM6_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_UARTE_RAM6_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_UARTE_RAM6_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_UARTE_RAM6_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 23..20 : Priority register for RAM AHB slave 5 */

+#define AMLI_RAMPRI_UARTE_RAM5_Pos (20UL) /*!< Position of RAM5 field. */

+#define AMLI_RAMPRI_UARTE_RAM5_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM5_Pos) /*!< Bit mask of RAM5 field. */

+#define AMLI_RAMPRI_UARTE_RAM5_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_UARTE_RAM5_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_UARTE_RAM5_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_UARTE_RAM5_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_UARTE_RAM5_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_UARTE_RAM5_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_UARTE_RAM5_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_UARTE_RAM5_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_UARTE_RAM5_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_UARTE_RAM5_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_UARTE_RAM5_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_UARTE_RAM5_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_UARTE_RAM5_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_UARTE_RAM5_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_UARTE_RAM5_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_UARTE_RAM5_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 19..16 : Priority register for RAM AHB slave 4 */

+#define AMLI_RAMPRI_UARTE_RAM4_Pos (16UL) /*!< Position of RAM4 field. */

+#define AMLI_RAMPRI_UARTE_RAM4_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM4_Pos) /*!< Bit mask of RAM4 field. */

+#define AMLI_RAMPRI_UARTE_RAM4_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_UARTE_RAM4_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_UARTE_RAM4_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_UARTE_RAM4_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_UARTE_RAM4_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_UARTE_RAM4_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_UARTE_RAM4_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_UARTE_RAM4_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_UARTE_RAM4_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_UARTE_RAM4_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_UARTE_RAM4_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_UARTE_RAM4_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_UARTE_RAM4_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_UARTE_RAM4_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_UARTE_RAM4_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_UARTE_RAM4_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 15..12 : Priority register for RAM AHB slave 3 */

+#define AMLI_RAMPRI_UARTE_RAM3_Pos (12UL) /*!< Position of RAM3 field. */

+#define AMLI_RAMPRI_UARTE_RAM3_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM3_Pos) /*!< Bit mask of RAM3 field. */

+#define AMLI_RAMPRI_UARTE_RAM3_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_UARTE_RAM3_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_UARTE_RAM3_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_UARTE_RAM3_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_UARTE_RAM3_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_UARTE_RAM3_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_UARTE_RAM3_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_UARTE_RAM3_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_UARTE_RAM3_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_UARTE_RAM3_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_UARTE_RAM3_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_UARTE_RAM3_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_UARTE_RAM3_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_UARTE_RAM3_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_UARTE_RAM3_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_UARTE_RAM3_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 11..8 : Priority register for RAM AHB slave 2 */

+#define AMLI_RAMPRI_UARTE_RAM2_Pos (8UL) /*!< Position of RAM2 field. */

+#define AMLI_RAMPRI_UARTE_RAM2_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM2_Pos) /*!< Bit mask of RAM2 field. */

+#define AMLI_RAMPRI_UARTE_RAM2_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_UARTE_RAM2_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_UARTE_RAM2_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_UARTE_RAM2_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_UARTE_RAM2_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_UARTE_RAM2_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_UARTE_RAM2_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_UARTE_RAM2_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_UARTE_RAM2_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_UARTE_RAM2_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_UARTE_RAM2_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_UARTE_RAM2_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_UARTE_RAM2_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_UARTE_RAM2_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_UARTE_RAM2_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_UARTE_RAM2_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 7..4 : Priority register for RAM AHB slave 1 */

+#define AMLI_RAMPRI_UARTE_RAM1_Pos (4UL) /*!< Position of RAM1 field. */

+#define AMLI_RAMPRI_UARTE_RAM1_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM1_Pos) /*!< Bit mask of RAM1 field. */

+#define AMLI_RAMPRI_UARTE_RAM1_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_UARTE_RAM1_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_UARTE_RAM1_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_UARTE_RAM1_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_UARTE_RAM1_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_UARTE_RAM1_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_UARTE_RAM1_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_UARTE_RAM1_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_UARTE_RAM1_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_UARTE_RAM1_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_UARTE_RAM1_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_UARTE_RAM1_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_UARTE_RAM1_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_UARTE_RAM1_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_UARTE_RAM1_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_UARTE_RAM1_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 3..0 : Priority register for RAM AHB slave 0 */

+#define AMLI_RAMPRI_UARTE_RAM0_Pos (0UL) /*!< Position of RAM0 field. */

+#define AMLI_RAMPRI_UARTE_RAM0_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM0_Pos) /*!< Bit mask of RAM0 field. */

+#define AMLI_RAMPRI_UARTE_RAM0_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_UARTE_RAM0_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_UARTE_RAM0_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_UARTE_RAM0_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_UARTE_RAM0_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_UARTE_RAM0_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_UARTE_RAM0_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_UARTE_RAM0_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_UARTE_RAM0_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_UARTE_RAM0_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_UARTE_RAM0_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_UARTE_RAM0_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_UARTE_RAM0_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_UARTE_RAM0_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_UARTE_RAM0_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_UARTE_RAM0_Pri15 (15UL) /*!< Priority 15 */

+

+/* Register: AMLI_RAMPRI_SERIAL0 */

+/* Description: AHB bus master priority register for SPIM0, SPIS0, TWIM0 and TWIS0 */

+

+/* Bits 31..28 : Priority register for RAM AHB slave 7 */

+#define AMLI_RAMPRI_SERIAL0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */

+#define AMLI_RAMPRI_SERIAL0_RAM7_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM7_Pos) /*!< Bit mask of RAM7 field. */

+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 27..24 : Priority register for RAM AHB slave 6 */

+#define AMLI_RAMPRI_SERIAL0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */

+#define AMLI_RAMPRI_SERIAL0_RAM6_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM6_Pos) /*!< Bit mask of RAM6 field. */

+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 23..20 : Priority register for RAM AHB slave 5 */

+#define AMLI_RAMPRI_SERIAL0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */

+#define AMLI_RAMPRI_SERIAL0_RAM5_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM5_Pos) /*!< Bit mask of RAM5 field. */

+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 19..16 : Priority register for RAM AHB slave 4 */

+#define AMLI_RAMPRI_SERIAL0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */

+#define AMLI_RAMPRI_SERIAL0_RAM4_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM4_Pos) /*!< Bit mask of RAM4 field. */

+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 15..12 : Priority register for RAM AHB slave 3 */

+#define AMLI_RAMPRI_SERIAL0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */

+#define AMLI_RAMPRI_SERIAL0_RAM3_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM3_Pos) /*!< Bit mask of RAM3 field. */

+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 11..8 : Priority register for RAM AHB slave 2 */

+#define AMLI_RAMPRI_SERIAL0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */

+#define AMLI_RAMPRI_SERIAL0_RAM2_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM2_Pos) /*!< Bit mask of RAM2 field. */

+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 7..4 : Priority register for RAM AHB slave 1 */

+#define AMLI_RAMPRI_SERIAL0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */

+#define AMLI_RAMPRI_SERIAL0_RAM1_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM1_Pos) /*!< Bit mask of RAM1 field. */

+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 3..0 : Priority register for RAM AHB slave 0 */

+#define AMLI_RAMPRI_SERIAL0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */

+#define AMLI_RAMPRI_SERIAL0_RAM0_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM0_Pos) /*!< Bit mask of RAM0 field. */

+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri15 (15UL) /*!< Priority 15 */

+

+/* Register: AMLI_RAMPRI_SERIAL2 */

+/* Description: AHB bus master priority register for SPIM2 and SPIS2 */

+

+/* Bits 31..28 : Priority register for RAM AHB slave 7 */

+#define AMLI_RAMPRI_SERIAL2_RAM7_Pos (28UL) /*!< Position of RAM7 field. */

+#define AMLI_RAMPRI_SERIAL2_RAM7_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM7_Pos) /*!< Bit mask of RAM7 field. */

+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 27..24 : Priority register for RAM AHB slave 6 */

+#define AMLI_RAMPRI_SERIAL2_RAM6_Pos (24UL) /*!< Position of RAM6 field. */

+#define AMLI_RAMPRI_SERIAL2_RAM6_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM6_Pos) /*!< Bit mask of RAM6 field. */

+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 23..20 : Priority register for RAM AHB slave 5 */

+#define AMLI_RAMPRI_SERIAL2_RAM5_Pos (20UL) /*!< Position of RAM5 field. */

+#define AMLI_RAMPRI_SERIAL2_RAM5_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM5_Pos) /*!< Bit mask of RAM5 field. */

+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 19..16 : Priority register for RAM AHB slave 4 */

+#define AMLI_RAMPRI_SERIAL2_RAM4_Pos (16UL) /*!< Position of RAM4 field. */

+#define AMLI_RAMPRI_SERIAL2_RAM4_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM4_Pos) /*!< Bit mask of RAM4 field. */

+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 15..12 : Priority register for RAM AHB slave 3 */

+#define AMLI_RAMPRI_SERIAL2_RAM3_Pos (12UL) /*!< Position of RAM3 field. */

+#define AMLI_RAMPRI_SERIAL2_RAM3_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM3_Pos) /*!< Bit mask of RAM3 field. */

+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 11..8 : Priority register for RAM AHB slave 2 */

+#define AMLI_RAMPRI_SERIAL2_RAM2_Pos (8UL) /*!< Position of RAM2 field. */

+#define AMLI_RAMPRI_SERIAL2_RAM2_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM2_Pos) /*!< Bit mask of RAM2 field. */

+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 7..4 : Priority register for RAM AHB slave 1 */

+#define AMLI_RAMPRI_SERIAL2_RAM1_Pos (4UL) /*!< Position of RAM1 field. */

+#define AMLI_RAMPRI_SERIAL2_RAM1_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM1_Pos) /*!< Bit mask of RAM1 field. */

+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 3..0 : Priority register for RAM AHB slave 0 */

+#define AMLI_RAMPRI_SERIAL2_RAM0_Pos (0UL) /*!< Position of RAM0 field. */

+#define AMLI_RAMPRI_SERIAL2_RAM0_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM0_Pos) /*!< Bit mask of RAM0 field. */

+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri15 (15UL) /*!< Priority 15 */

+

+/* Register: AMLI_RAMPRI_NFCT */

+/* Description: AHB bus master priority register for NFCT */

+

+/* Bits 31..28 : Priority register for RAM AHB slave 7 */

+#define AMLI_RAMPRI_NFCT_RAM7_Pos (28UL) /*!< Position of RAM7 field. */

+#define AMLI_RAMPRI_NFCT_RAM7_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM7_Pos) /*!< Bit mask of RAM7 field. */

+#define AMLI_RAMPRI_NFCT_RAM7_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_NFCT_RAM7_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_NFCT_RAM7_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_NFCT_RAM7_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_NFCT_RAM7_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_NFCT_RAM7_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_NFCT_RAM7_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_NFCT_RAM7_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_NFCT_RAM7_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_NFCT_RAM7_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_NFCT_RAM7_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_NFCT_RAM7_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_NFCT_RAM7_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_NFCT_RAM7_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_NFCT_RAM7_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_NFCT_RAM7_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 27..24 : Priority register for RAM AHB slave 6 */

+#define AMLI_RAMPRI_NFCT_RAM6_Pos (24UL) /*!< Position of RAM6 field. */

+#define AMLI_RAMPRI_NFCT_RAM6_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM6_Pos) /*!< Bit mask of RAM6 field. */

+#define AMLI_RAMPRI_NFCT_RAM6_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_NFCT_RAM6_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_NFCT_RAM6_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_NFCT_RAM6_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_NFCT_RAM6_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_NFCT_RAM6_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_NFCT_RAM6_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_NFCT_RAM6_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_NFCT_RAM6_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_NFCT_RAM6_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_NFCT_RAM6_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_NFCT_RAM6_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_NFCT_RAM6_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_NFCT_RAM6_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_NFCT_RAM6_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_NFCT_RAM6_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 23..20 : Priority register for RAM AHB slave 5 */

+#define AMLI_RAMPRI_NFCT_RAM5_Pos (20UL) /*!< Position of RAM5 field. */

+#define AMLI_RAMPRI_NFCT_RAM5_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM5_Pos) /*!< Bit mask of RAM5 field. */

+#define AMLI_RAMPRI_NFCT_RAM5_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_NFCT_RAM5_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_NFCT_RAM5_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_NFCT_RAM5_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_NFCT_RAM5_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_NFCT_RAM5_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_NFCT_RAM5_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_NFCT_RAM5_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_NFCT_RAM5_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_NFCT_RAM5_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_NFCT_RAM5_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_NFCT_RAM5_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_NFCT_RAM5_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_NFCT_RAM5_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_NFCT_RAM5_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_NFCT_RAM5_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 19..16 : Priority register for RAM AHB slave 4 */

+#define AMLI_RAMPRI_NFCT_RAM4_Pos (16UL) /*!< Position of RAM4 field. */

+#define AMLI_RAMPRI_NFCT_RAM4_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM4_Pos) /*!< Bit mask of RAM4 field. */

+#define AMLI_RAMPRI_NFCT_RAM4_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_NFCT_RAM4_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_NFCT_RAM4_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_NFCT_RAM4_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_NFCT_RAM4_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_NFCT_RAM4_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_NFCT_RAM4_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_NFCT_RAM4_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_NFCT_RAM4_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_NFCT_RAM4_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_NFCT_RAM4_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_NFCT_RAM4_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_NFCT_RAM4_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_NFCT_RAM4_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_NFCT_RAM4_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_NFCT_RAM4_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 15..12 : Priority register for RAM AHB slave 3 */

+#define AMLI_RAMPRI_NFCT_RAM3_Pos (12UL) /*!< Position of RAM3 field. */

+#define AMLI_RAMPRI_NFCT_RAM3_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM3_Pos) /*!< Bit mask of RAM3 field. */

+#define AMLI_RAMPRI_NFCT_RAM3_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_NFCT_RAM3_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_NFCT_RAM3_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_NFCT_RAM3_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_NFCT_RAM3_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_NFCT_RAM3_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_NFCT_RAM3_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_NFCT_RAM3_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_NFCT_RAM3_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_NFCT_RAM3_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_NFCT_RAM3_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_NFCT_RAM3_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_NFCT_RAM3_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_NFCT_RAM3_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_NFCT_RAM3_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_NFCT_RAM3_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 11..8 : Priority register for RAM AHB slave 2 */

+#define AMLI_RAMPRI_NFCT_RAM2_Pos (8UL) /*!< Position of RAM2 field. */

+#define AMLI_RAMPRI_NFCT_RAM2_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM2_Pos) /*!< Bit mask of RAM2 field. */

+#define AMLI_RAMPRI_NFCT_RAM2_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_NFCT_RAM2_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_NFCT_RAM2_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_NFCT_RAM2_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_NFCT_RAM2_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_NFCT_RAM2_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_NFCT_RAM2_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_NFCT_RAM2_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_NFCT_RAM2_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_NFCT_RAM2_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_NFCT_RAM2_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_NFCT_RAM2_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_NFCT_RAM2_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_NFCT_RAM2_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_NFCT_RAM2_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_NFCT_RAM2_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 7..4 : Priority register for RAM AHB slave 1 */

+#define AMLI_RAMPRI_NFCT_RAM1_Pos (4UL) /*!< Position of RAM1 field. */

+#define AMLI_RAMPRI_NFCT_RAM1_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM1_Pos) /*!< Bit mask of RAM1 field. */

+#define AMLI_RAMPRI_NFCT_RAM1_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_NFCT_RAM1_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_NFCT_RAM1_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_NFCT_RAM1_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_NFCT_RAM1_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_NFCT_RAM1_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_NFCT_RAM1_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_NFCT_RAM1_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_NFCT_RAM1_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_NFCT_RAM1_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_NFCT_RAM1_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_NFCT_RAM1_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_NFCT_RAM1_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_NFCT_RAM1_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_NFCT_RAM1_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_NFCT_RAM1_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 3..0 : Priority register for RAM AHB slave 0 */

+#define AMLI_RAMPRI_NFCT_RAM0_Pos (0UL) /*!< Position of RAM0 field. */

+#define AMLI_RAMPRI_NFCT_RAM0_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM0_Pos) /*!< Bit mask of RAM0 field. */

+#define AMLI_RAMPRI_NFCT_RAM0_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_NFCT_RAM0_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_NFCT_RAM0_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_NFCT_RAM0_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_NFCT_RAM0_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_NFCT_RAM0_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_NFCT_RAM0_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_NFCT_RAM0_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_NFCT_RAM0_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_NFCT_RAM0_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_NFCT_RAM0_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_NFCT_RAM0_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_NFCT_RAM0_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_NFCT_RAM0_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_NFCT_RAM0_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_NFCT_RAM0_Pri15 (15UL) /*!< Priority 15 */

+

+/* Register: AMLI_RAMPRI_I2S */

+/* Description: AHB bus master priority register for I2S */

+

+/* Bits 31..28 : Priority register for RAM AHB slave 7 */

+#define AMLI_RAMPRI_I2S_RAM7_Pos (28UL) /*!< Position of RAM7 field. */

+#define AMLI_RAMPRI_I2S_RAM7_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM7_Pos) /*!< Bit mask of RAM7 field. */

+#define AMLI_RAMPRI_I2S_RAM7_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_I2S_RAM7_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_I2S_RAM7_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_I2S_RAM7_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_I2S_RAM7_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_I2S_RAM7_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_I2S_RAM7_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_I2S_RAM7_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_I2S_RAM7_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_I2S_RAM7_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_I2S_RAM7_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_I2S_RAM7_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_I2S_RAM7_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_I2S_RAM7_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_I2S_RAM7_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_I2S_RAM7_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 27..24 : Priority register for RAM AHB slave 6 */

+#define AMLI_RAMPRI_I2S_RAM6_Pos (24UL) /*!< Position of RAM6 field. */

+#define AMLI_RAMPRI_I2S_RAM6_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM6_Pos) /*!< Bit mask of RAM6 field. */

+#define AMLI_RAMPRI_I2S_RAM6_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_I2S_RAM6_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_I2S_RAM6_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_I2S_RAM6_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_I2S_RAM6_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_I2S_RAM6_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_I2S_RAM6_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_I2S_RAM6_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_I2S_RAM6_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_I2S_RAM6_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_I2S_RAM6_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_I2S_RAM6_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_I2S_RAM6_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_I2S_RAM6_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_I2S_RAM6_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_I2S_RAM6_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 23..20 : Priority register for RAM AHB slave 5 */

+#define AMLI_RAMPRI_I2S_RAM5_Pos (20UL) /*!< Position of RAM5 field. */

+#define AMLI_RAMPRI_I2S_RAM5_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM5_Pos) /*!< Bit mask of RAM5 field. */

+#define AMLI_RAMPRI_I2S_RAM5_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_I2S_RAM5_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_I2S_RAM5_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_I2S_RAM5_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_I2S_RAM5_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_I2S_RAM5_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_I2S_RAM5_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_I2S_RAM5_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_I2S_RAM5_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_I2S_RAM5_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_I2S_RAM5_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_I2S_RAM5_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_I2S_RAM5_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_I2S_RAM5_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_I2S_RAM5_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_I2S_RAM5_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 19..16 : Priority register for RAM AHB slave 4 */

+#define AMLI_RAMPRI_I2S_RAM4_Pos (16UL) /*!< Position of RAM4 field. */

+#define AMLI_RAMPRI_I2S_RAM4_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM4_Pos) /*!< Bit mask of RAM4 field. */

+#define AMLI_RAMPRI_I2S_RAM4_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_I2S_RAM4_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_I2S_RAM4_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_I2S_RAM4_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_I2S_RAM4_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_I2S_RAM4_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_I2S_RAM4_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_I2S_RAM4_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_I2S_RAM4_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_I2S_RAM4_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_I2S_RAM4_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_I2S_RAM4_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_I2S_RAM4_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_I2S_RAM4_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_I2S_RAM4_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_I2S_RAM4_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 15..12 : Priority register for RAM AHB slave 3 */

+#define AMLI_RAMPRI_I2S_RAM3_Pos (12UL) /*!< Position of RAM3 field. */

+#define AMLI_RAMPRI_I2S_RAM3_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM3_Pos) /*!< Bit mask of RAM3 field. */

+#define AMLI_RAMPRI_I2S_RAM3_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_I2S_RAM3_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_I2S_RAM3_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_I2S_RAM3_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_I2S_RAM3_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_I2S_RAM3_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_I2S_RAM3_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_I2S_RAM3_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_I2S_RAM3_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_I2S_RAM3_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_I2S_RAM3_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_I2S_RAM3_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_I2S_RAM3_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_I2S_RAM3_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_I2S_RAM3_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_I2S_RAM3_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 11..8 : Priority register for RAM AHB slave 2 */

+#define AMLI_RAMPRI_I2S_RAM2_Pos (8UL) /*!< Position of RAM2 field. */

+#define AMLI_RAMPRI_I2S_RAM2_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM2_Pos) /*!< Bit mask of RAM2 field. */

+#define AMLI_RAMPRI_I2S_RAM2_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_I2S_RAM2_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_I2S_RAM2_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_I2S_RAM2_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_I2S_RAM2_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_I2S_RAM2_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_I2S_RAM2_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_I2S_RAM2_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_I2S_RAM2_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_I2S_RAM2_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_I2S_RAM2_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_I2S_RAM2_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_I2S_RAM2_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_I2S_RAM2_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_I2S_RAM2_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_I2S_RAM2_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 7..4 : Priority register for RAM AHB slave 1 */

+#define AMLI_RAMPRI_I2S_RAM1_Pos (4UL) /*!< Position of RAM1 field. */

+#define AMLI_RAMPRI_I2S_RAM1_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM1_Pos) /*!< Bit mask of RAM1 field. */

+#define AMLI_RAMPRI_I2S_RAM1_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_I2S_RAM1_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_I2S_RAM1_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_I2S_RAM1_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_I2S_RAM1_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_I2S_RAM1_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_I2S_RAM1_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_I2S_RAM1_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_I2S_RAM1_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_I2S_RAM1_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_I2S_RAM1_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_I2S_RAM1_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_I2S_RAM1_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_I2S_RAM1_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_I2S_RAM1_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_I2S_RAM1_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 3..0 : Priority register for RAM AHB slave 0 */

+#define AMLI_RAMPRI_I2S_RAM0_Pos (0UL) /*!< Position of RAM0 field. */

+#define AMLI_RAMPRI_I2S_RAM0_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM0_Pos) /*!< Bit mask of RAM0 field. */

+#define AMLI_RAMPRI_I2S_RAM0_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_I2S_RAM0_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_I2S_RAM0_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_I2S_RAM0_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_I2S_RAM0_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_I2S_RAM0_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_I2S_RAM0_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_I2S_RAM0_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_I2S_RAM0_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_I2S_RAM0_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_I2S_RAM0_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_I2S_RAM0_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_I2S_RAM0_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_I2S_RAM0_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_I2S_RAM0_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_I2S_RAM0_Pri15 (15UL) /*!< Priority 15 */

+

+/* Register: AMLI_RAMPRI_PDM */

+/* Description: AHB bus master priority register for PDM */

+

+/* Bits 31..28 : Priority register for RAM AHB slave 7 */

+#define AMLI_RAMPRI_PDM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */

+#define AMLI_RAMPRI_PDM_RAM7_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM7_Pos) /*!< Bit mask of RAM7 field. */

+#define AMLI_RAMPRI_PDM_RAM7_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_PDM_RAM7_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_PDM_RAM7_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_PDM_RAM7_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_PDM_RAM7_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_PDM_RAM7_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_PDM_RAM7_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_PDM_RAM7_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_PDM_RAM7_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_PDM_RAM7_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_PDM_RAM7_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_PDM_RAM7_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_PDM_RAM7_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_PDM_RAM7_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_PDM_RAM7_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_PDM_RAM7_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 27..24 : Priority register for RAM AHB slave 6 */

+#define AMLI_RAMPRI_PDM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */

+#define AMLI_RAMPRI_PDM_RAM6_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM6_Pos) /*!< Bit mask of RAM6 field. */

+#define AMLI_RAMPRI_PDM_RAM6_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_PDM_RAM6_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_PDM_RAM6_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_PDM_RAM6_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_PDM_RAM6_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_PDM_RAM6_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_PDM_RAM6_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_PDM_RAM6_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_PDM_RAM6_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_PDM_RAM6_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_PDM_RAM6_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_PDM_RAM6_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_PDM_RAM6_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_PDM_RAM6_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_PDM_RAM6_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_PDM_RAM6_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 23..20 : Priority register for RAM AHB slave 5 */

+#define AMLI_RAMPRI_PDM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */

+#define AMLI_RAMPRI_PDM_RAM5_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM5_Pos) /*!< Bit mask of RAM5 field. */

+#define AMLI_RAMPRI_PDM_RAM5_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_PDM_RAM5_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_PDM_RAM5_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_PDM_RAM5_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_PDM_RAM5_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_PDM_RAM5_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_PDM_RAM5_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_PDM_RAM5_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_PDM_RAM5_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_PDM_RAM5_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_PDM_RAM5_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_PDM_RAM5_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_PDM_RAM5_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_PDM_RAM5_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_PDM_RAM5_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_PDM_RAM5_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 19..16 : Priority register for RAM AHB slave 4 */

+#define AMLI_RAMPRI_PDM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */

+#define AMLI_RAMPRI_PDM_RAM4_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM4_Pos) /*!< Bit mask of RAM4 field. */

+#define AMLI_RAMPRI_PDM_RAM4_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_PDM_RAM4_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_PDM_RAM4_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_PDM_RAM4_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_PDM_RAM4_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_PDM_RAM4_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_PDM_RAM4_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_PDM_RAM4_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_PDM_RAM4_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_PDM_RAM4_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_PDM_RAM4_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_PDM_RAM4_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_PDM_RAM4_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_PDM_RAM4_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_PDM_RAM4_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_PDM_RAM4_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 15..12 : Priority register for RAM AHB slave 3 */

+#define AMLI_RAMPRI_PDM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */

+#define AMLI_RAMPRI_PDM_RAM3_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM3_Pos) /*!< Bit mask of RAM3 field. */

+#define AMLI_RAMPRI_PDM_RAM3_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_PDM_RAM3_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_PDM_RAM3_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_PDM_RAM3_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_PDM_RAM3_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_PDM_RAM3_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_PDM_RAM3_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_PDM_RAM3_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_PDM_RAM3_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_PDM_RAM3_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_PDM_RAM3_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_PDM_RAM3_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_PDM_RAM3_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_PDM_RAM3_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_PDM_RAM3_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_PDM_RAM3_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 11..8 : Priority register for RAM AHB slave 2 */

+#define AMLI_RAMPRI_PDM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */

+#define AMLI_RAMPRI_PDM_RAM2_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM2_Pos) /*!< Bit mask of RAM2 field. */

+#define AMLI_RAMPRI_PDM_RAM2_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_PDM_RAM2_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_PDM_RAM2_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_PDM_RAM2_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_PDM_RAM2_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_PDM_RAM2_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_PDM_RAM2_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_PDM_RAM2_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_PDM_RAM2_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_PDM_RAM2_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_PDM_RAM2_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_PDM_RAM2_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_PDM_RAM2_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_PDM_RAM2_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_PDM_RAM2_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_PDM_RAM2_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 7..4 : Priority register for RAM AHB slave 1 */

+#define AMLI_RAMPRI_PDM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */

+#define AMLI_RAMPRI_PDM_RAM1_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM1_Pos) /*!< Bit mask of RAM1 field. */

+#define AMLI_RAMPRI_PDM_RAM1_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_PDM_RAM1_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_PDM_RAM1_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_PDM_RAM1_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_PDM_RAM1_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_PDM_RAM1_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_PDM_RAM1_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_PDM_RAM1_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_PDM_RAM1_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_PDM_RAM1_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_PDM_RAM1_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_PDM_RAM1_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_PDM_RAM1_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_PDM_RAM1_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_PDM_RAM1_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_PDM_RAM1_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 3..0 : Priority register for RAM AHB slave 0 */

+#define AMLI_RAMPRI_PDM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */

+#define AMLI_RAMPRI_PDM_RAM0_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM0_Pos) /*!< Bit mask of RAM0 field. */

+#define AMLI_RAMPRI_PDM_RAM0_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_PDM_RAM0_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_PDM_RAM0_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_PDM_RAM0_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_PDM_RAM0_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_PDM_RAM0_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_PDM_RAM0_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_PDM_RAM0_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_PDM_RAM0_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_PDM_RAM0_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_PDM_RAM0_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_PDM_RAM0_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_PDM_RAM0_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_PDM_RAM0_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_PDM_RAM0_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_PDM_RAM0_Pri15 (15UL) /*!< Priority 15 */

+

+/* Register: AMLI_RAMPRI_PWM */

+/* Description: AHB bus master priority register for PWM0, PWM1 and PWM2 */

+

+/* Bits 31..28 : Priority register for RAM AHB slave 7 */

+#define AMLI_RAMPRI_PWM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */

+#define AMLI_RAMPRI_PWM_RAM7_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM7_Pos) /*!< Bit mask of RAM7 field. */

+#define AMLI_RAMPRI_PWM_RAM7_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_PWM_RAM7_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_PWM_RAM7_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_PWM_RAM7_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_PWM_RAM7_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_PWM_RAM7_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_PWM_RAM7_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_PWM_RAM7_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_PWM_RAM7_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_PWM_RAM7_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_PWM_RAM7_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_PWM_RAM7_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_PWM_RAM7_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_PWM_RAM7_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_PWM_RAM7_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_PWM_RAM7_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 27..24 : Priority register for RAM AHB slave 6 */

+#define AMLI_RAMPRI_PWM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */

+#define AMLI_RAMPRI_PWM_RAM6_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM6_Pos) /*!< Bit mask of RAM6 field. */

+#define AMLI_RAMPRI_PWM_RAM6_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_PWM_RAM6_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_PWM_RAM6_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_PWM_RAM6_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_PWM_RAM6_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_PWM_RAM6_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_PWM_RAM6_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_PWM_RAM6_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_PWM_RAM6_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_PWM_RAM6_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_PWM_RAM6_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_PWM_RAM6_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_PWM_RAM6_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_PWM_RAM6_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_PWM_RAM6_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_PWM_RAM6_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 23..20 : Priority register for RAM AHB slave 5 */

+#define AMLI_RAMPRI_PWM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */

+#define AMLI_RAMPRI_PWM_RAM5_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM5_Pos) /*!< Bit mask of RAM5 field. */

+#define AMLI_RAMPRI_PWM_RAM5_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_PWM_RAM5_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_PWM_RAM5_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_PWM_RAM5_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_PWM_RAM5_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_PWM_RAM5_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_PWM_RAM5_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_PWM_RAM5_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_PWM_RAM5_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_PWM_RAM5_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_PWM_RAM5_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_PWM_RAM5_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_PWM_RAM5_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_PWM_RAM5_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_PWM_RAM5_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_PWM_RAM5_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 19..16 : Priority register for RAM AHB slave 4 */

+#define AMLI_RAMPRI_PWM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */

+#define AMLI_RAMPRI_PWM_RAM4_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM4_Pos) /*!< Bit mask of RAM4 field. */

+#define AMLI_RAMPRI_PWM_RAM4_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_PWM_RAM4_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_PWM_RAM4_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_PWM_RAM4_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_PWM_RAM4_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_PWM_RAM4_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_PWM_RAM4_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_PWM_RAM4_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_PWM_RAM4_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_PWM_RAM4_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_PWM_RAM4_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_PWM_RAM4_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_PWM_RAM4_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_PWM_RAM4_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_PWM_RAM4_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_PWM_RAM4_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 15..12 : Priority register for RAM AHB slave 3 */

+#define AMLI_RAMPRI_PWM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */

+#define AMLI_RAMPRI_PWM_RAM3_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM3_Pos) /*!< Bit mask of RAM3 field. */

+#define AMLI_RAMPRI_PWM_RAM3_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_PWM_RAM3_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_PWM_RAM3_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_PWM_RAM3_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_PWM_RAM3_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_PWM_RAM3_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_PWM_RAM3_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_PWM_RAM3_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_PWM_RAM3_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_PWM_RAM3_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_PWM_RAM3_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_PWM_RAM3_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_PWM_RAM3_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_PWM_RAM3_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_PWM_RAM3_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_PWM_RAM3_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 11..8 : Priority register for RAM AHB slave 2 */

+#define AMLI_RAMPRI_PWM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */

+#define AMLI_RAMPRI_PWM_RAM2_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM2_Pos) /*!< Bit mask of RAM2 field. */

+#define AMLI_RAMPRI_PWM_RAM2_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_PWM_RAM2_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_PWM_RAM2_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_PWM_RAM2_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_PWM_RAM2_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_PWM_RAM2_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_PWM_RAM2_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_PWM_RAM2_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_PWM_RAM2_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_PWM_RAM2_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_PWM_RAM2_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_PWM_RAM2_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_PWM_RAM2_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_PWM_RAM2_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_PWM_RAM2_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_PWM_RAM2_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 7..4 : Priority register for RAM AHB slave 1 */

+#define AMLI_RAMPRI_PWM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */

+#define AMLI_RAMPRI_PWM_RAM1_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM1_Pos) /*!< Bit mask of RAM1 field. */

+#define AMLI_RAMPRI_PWM_RAM1_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_PWM_RAM1_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_PWM_RAM1_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_PWM_RAM1_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_PWM_RAM1_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_PWM_RAM1_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_PWM_RAM1_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_PWM_RAM1_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_PWM_RAM1_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_PWM_RAM1_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_PWM_RAM1_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_PWM_RAM1_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_PWM_RAM1_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_PWM_RAM1_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_PWM_RAM1_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_PWM_RAM1_Pri15 (15UL) /*!< Priority 15 */

+

+/* Bits 3..0 : Priority register for RAM AHB slave 0 */

+#define AMLI_RAMPRI_PWM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */

+#define AMLI_RAMPRI_PWM_RAM0_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM0_Pos) /*!< Bit mask of RAM0 field. */

+#define AMLI_RAMPRI_PWM_RAM0_Pri0 (0UL) /*!< Priority 0 */

+#define AMLI_RAMPRI_PWM_RAM0_Pri1 (1UL) /*!< Priority 1 */

+#define AMLI_RAMPRI_PWM_RAM0_Pri2 (2UL) /*!< Priority 2 */

+#define AMLI_RAMPRI_PWM_RAM0_Pri3 (3UL) /*!< Priority 3 */

+#define AMLI_RAMPRI_PWM_RAM0_Pri4 (4UL) /*!< Priority 4 */

+#define AMLI_RAMPRI_PWM_RAM0_Pri5 (5UL) /*!< Priority 5 */

+#define AMLI_RAMPRI_PWM_RAM0_Pri6 (6UL) /*!< Priority 6 */

+#define AMLI_RAMPRI_PWM_RAM0_Pri7 (7UL) /*!< Priority 7 */

+#define AMLI_RAMPRI_PWM_RAM0_Pri8 (8UL) /*!< Priority 8 */

+#define AMLI_RAMPRI_PWM_RAM0_Pri9 (9UL) /*!< Priority 9 */

+#define AMLI_RAMPRI_PWM_RAM0_Pri10 (10UL) /*!< Priority 10 */

+#define AMLI_RAMPRI_PWM_RAM0_Pri11 (11UL) /*!< Priority 11 */

+#define AMLI_RAMPRI_PWM_RAM0_Pri12 (12UL) /*!< Priority 12 */

+#define AMLI_RAMPRI_PWM_RAM0_Pri13 (13UL) /*!< Priority 13 */

+#define AMLI_RAMPRI_PWM_RAM0_Pri14 (14UL) /*!< Priority 14 */

+#define AMLI_RAMPRI_PWM_RAM0_Pri15 (15UL) /*!< Priority 15 */

+

+

+/* Peripheral: BPROT */

+/* Description: Block Protect */

+

+/* Register: BPROT_CONFIG0 */

+/* Description: Block protect configuration register 0 */

+

+/* Bit 31 : Enable protection for region 31. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION31_Pos (31UL) /*!< Position of REGION31 field. */

+#define BPROT_CONFIG0_REGION31_Msk (0x1UL << BPROT_CONFIG0_REGION31_Pos) /*!< Bit mask of REGION31 field. */

+#define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 30 : Enable protection for region 30. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION30_Pos (30UL) /*!< Position of REGION30 field. */

+#define BPROT_CONFIG0_REGION30_Msk (0x1UL << BPROT_CONFIG0_REGION30_Pos) /*!< Bit mask of REGION30 field. */

+#define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 29 : Enable protection for region 29. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION29_Pos (29UL) /*!< Position of REGION29 field. */

+#define BPROT_CONFIG0_REGION29_Msk (0x1UL << BPROT_CONFIG0_REGION29_Pos) /*!< Bit mask of REGION29 field. */

+#define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 28 : Enable protection for region 28. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION28_Pos (28UL) /*!< Position of REGION28 field. */

+#define BPROT_CONFIG0_REGION28_Msk (0x1UL << BPROT_CONFIG0_REGION28_Pos) /*!< Bit mask of REGION28 field. */

+#define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 27 : Enable protection for region 27. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION27_Pos (27UL) /*!< Position of REGION27 field. */

+#define BPROT_CONFIG0_REGION27_Msk (0x1UL << BPROT_CONFIG0_REGION27_Pos) /*!< Bit mask of REGION27 field. */

+#define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 26 : Enable protection for region 26. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION26_Pos (26UL) /*!< Position of REGION26 field. */

+#define BPROT_CONFIG0_REGION26_Msk (0x1UL << BPROT_CONFIG0_REGION26_Pos) /*!< Bit mask of REGION26 field. */

+#define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 25 : Enable protection for region 25. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION25_Pos (25UL) /*!< Position of REGION25 field. */

+#define BPROT_CONFIG0_REGION25_Msk (0x1UL << BPROT_CONFIG0_REGION25_Pos) /*!< Bit mask of REGION25 field. */

+#define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 24 : Enable protection for region 24. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION24_Pos (24UL) /*!< Position of REGION24 field. */

+#define BPROT_CONFIG0_REGION24_Msk (0x1UL << BPROT_CONFIG0_REGION24_Pos) /*!< Bit mask of REGION24 field. */

+#define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 23 : Enable protection for region 23. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION23_Pos (23UL) /*!< Position of REGION23 field. */

+#define BPROT_CONFIG0_REGION23_Msk (0x1UL << BPROT_CONFIG0_REGION23_Pos) /*!< Bit mask of REGION23 field. */

+#define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 22 : Enable protection for region 22. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION22_Pos (22UL) /*!< Position of REGION22 field. */

+#define BPROT_CONFIG0_REGION22_Msk (0x1UL << BPROT_CONFIG0_REGION22_Pos) /*!< Bit mask of REGION22 field. */

+#define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 21 : Enable protection for region 21. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION21_Pos (21UL) /*!< Position of REGION21 field. */

+#define BPROT_CONFIG0_REGION21_Msk (0x1UL << BPROT_CONFIG0_REGION21_Pos) /*!< Bit mask of REGION21 field. */

+#define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 20 : Enable protection for region 20. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION20_Pos (20UL) /*!< Position of REGION20 field. */

+#define BPROT_CONFIG0_REGION20_Msk (0x1UL << BPROT_CONFIG0_REGION20_Pos) /*!< Bit mask of REGION20 field. */

+#define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 19 : Enable protection for region 19. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION19_Pos (19UL) /*!< Position of REGION19 field. */

+#define BPROT_CONFIG0_REGION19_Msk (0x1UL << BPROT_CONFIG0_REGION19_Pos) /*!< Bit mask of REGION19 field. */

+#define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 18 : Enable protection for region 18. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION18_Pos (18UL) /*!< Position of REGION18 field. */

+#define BPROT_CONFIG0_REGION18_Msk (0x1UL << BPROT_CONFIG0_REGION18_Pos) /*!< Bit mask of REGION18 field. */

+#define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 17 : Enable protection for region 17. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION17_Pos (17UL) /*!< Position of REGION17 field. */

+#define BPROT_CONFIG0_REGION17_Msk (0x1UL << BPROT_CONFIG0_REGION17_Pos) /*!< Bit mask of REGION17 field. */

+#define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 16 : Enable protection for region 16. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION16_Pos (16UL) /*!< Position of REGION16 field. */

+#define BPROT_CONFIG0_REGION16_Msk (0x1UL << BPROT_CONFIG0_REGION16_Pos) /*!< Bit mask of REGION16 field. */

+#define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 15 : Enable protection for region 15. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION15_Pos (15UL) /*!< Position of REGION15 field. */

+#define BPROT_CONFIG0_REGION15_Msk (0x1UL << BPROT_CONFIG0_REGION15_Pos) /*!< Bit mask of REGION15 field. */

+#define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 14 : Enable protection for region 14. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION14_Pos (14UL) /*!< Position of REGION14 field. */

+#define BPROT_CONFIG0_REGION14_Msk (0x1UL << BPROT_CONFIG0_REGION14_Pos) /*!< Bit mask of REGION14 field. */

+#define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 13 : Enable protection for region 13. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION13_Pos (13UL) /*!< Position of REGION13 field. */

+#define BPROT_CONFIG0_REGION13_Msk (0x1UL << BPROT_CONFIG0_REGION13_Pos) /*!< Bit mask of REGION13 field. */

+#define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 12 : Enable protection for region 12. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION12_Pos (12UL) /*!< Position of REGION12 field. */

+#define BPROT_CONFIG0_REGION12_Msk (0x1UL << BPROT_CONFIG0_REGION12_Pos) /*!< Bit mask of REGION12 field. */

+#define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 11 : Enable protection for region 11. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION11_Pos (11UL) /*!< Position of REGION11 field. */

+#define BPROT_CONFIG0_REGION11_Msk (0x1UL << BPROT_CONFIG0_REGION11_Pos) /*!< Bit mask of REGION11 field. */

+#define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 10 : Enable protection for region 10. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION10_Pos (10UL) /*!< Position of REGION10 field. */

+#define BPROT_CONFIG0_REGION10_Msk (0x1UL << BPROT_CONFIG0_REGION10_Pos) /*!< Bit mask of REGION10 field. */

+#define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 9 : Enable protection for region 9. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION9_Pos (9UL) /*!< Position of REGION9 field. */

+#define BPROT_CONFIG0_REGION9_Msk (0x1UL << BPROT_CONFIG0_REGION9_Pos) /*!< Bit mask of REGION9 field. */

+#define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 8 : Enable protection for region 8. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION8_Pos (8UL) /*!< Position of REGION8 field. */

+#define BPROT_CONFIG0_REGION8_Msk (0x1UL << BPROT_CONFIG0_REGION8_Pos) /*!< Bit mask of REGION8 field. */

+#define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 7 : Enable protection for region 7. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION7_Pos (7UL) /*!< Position of REGION7 field. */

+#define BPROT_CONFIG0_REGION7_Msk (0x1UL << BPROT_CONFIG0_REGION7_Pos) /*!< Bit mask of REGION7 field. */

+#define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 6 : Enable protection for region 6. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION6_Pos (6UL) /*!< Position of REGION6 field. */

+#define BPROT_CONFIG0_REGION6_Msk (0x1UL << BPROT_CONFIG0_REGION6_Pos) /*!< Bit mask of REGION6 field. */

+#define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 5 : Enable protection for region 5. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION5_Pos (5UL) /*!< Position of REGION5 field. */

+#define BPROT_CONFIG0_REGION5_Msk (0x1UL << BPROT_CONFIG0_REGION5_Pos) /*!< Bit mask of REGION5 field. */

+#define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 4 : Enable protection for region 4. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION4_Pos (4UL) /*!< Position of REGION4 field. */

+#define BPROT_CONFIG0_REGION4_Msk (0x1UL << BPROT_CONFIG0_REGION4_Pos) /*!< Bit mask of REGION4 field. */

+#define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 3 : Enable protection for region 3. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION3_Pos (3UL) /*!< Position of REGION3 field. */

+#define BPROT_CONFIG0_REGION3_Msk (0x1UL << BPROT_CONFIG0_REGION3_Pos) /*!< Bit mask of REGION3 field. */

+#define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 2 : Enable protection for region 2. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */

+#define BPROT_CONFIG0_REGION2_Msk (0x1UL << BPROT_CONFIG0_REGION2_Pos) /*!< Bit mask of REGION2 field. */

+#define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 1 : Enable protection for region 1. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION1_Pos (1UL) /*!< Position of REGION1 field. */

+#define BPROT_CONFIG0_REGION1_Msk (0x1UL << BPROT_CONFIG0_REGION1_Pos) /*!< Bit mask of REGION1 field. */

+#define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enable */

+

+/* Bit 0 : Enable protection for region 0. Write '0' has no effect. */

+#define BPROT_CONFIG0_REGION0_Pos (0UL) /*!< Position of REGION0 field. */

+#define BPROT_CONFIG0_REGION0_Msk (0x1UL << BPROT_CONFIG0_REGION0_Pos) /*!< Bit mask of REGION0 field. */

+#define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enable */

+

+/* Register: BPROT_CONFIG1 */

+/* Description: Block protect configuration register 1 */

+

+/* Bit 31 : Enable protection for region 63. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION63_Pos (31UL) /*!< Position of REGION63 field. */

+#define BPROT_CONFIG1_REGION63_Msk (0x1UL << BPROT_CONFIG1_REGION63_Pos) /*!< Bit mask of REGION63 field. */

+#define BPROT_CONFIG1_REGION63_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION63_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 30 : Enable protection for region 62. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION62_Pos (30UL) /*!< Position of REGION62 field. */

+#define BPROT_CONFIG1_REGION62_Msk (0x1UL << BPROT_CONFIG1_REGION62_Pos) /*!< Bit mask of REGION62 field. */

+#define BPROT_CONFIG1_REGION62_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION62_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 29 : Enable protection for region 61. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION61_Pos (29UL) /*!< Position of REGION61 field. */

+#define BPROT_CONFIG1_REGION61_Msk (0x1UL << BPROT_CONFIG1_REGION61_Pos) /*!< Bit mask of REGION61 field. */

+#define BPROT_CONFIG1_REGION61_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION61_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 28 : Enable protection for region 60. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION60_Pos (28UL) /*!< Position of REGION60 field. */

+#define BPROT_CONFIG1_REGION60_Msk (0x1UL << BPROT_CONFIG1_REGION60_Pos) /*!< Bit mask of REGION60 field. */

+#define BPROT_CONFIG1_REGION60_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION60_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 27 : Enable protection for region 59. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION59_Pos (27UL) /*!< Position of REGION59 field. */

+#define BPROT_CONFIG1_REGION59_Msk (0x1UL << BPROT_CONFIG1_REGION59_Pos) /*!< Bit mask of REGION59 field. */

+#define BPROT_CONFIG1_REGION59_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION59_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 26 : Enable protection for region 58. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION58_Pos (26UL) /*!< Position of REGION58 field. */

+#define BPROT_CONFIG1_REGION58_Msk (0x1UL << BPROT_CONFIG1_REGION58_Pos) /*!< Bit mask of REGION58 field. */

+#define BPROT_CONFIG1_REGION58_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION58_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 25 : Enable protection for region 57. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION57_Pos (25UL) /*!< Position of REGION57 field. */

+#define BPROT_CONFIG1_REGION57_Msk (0x1UL << BPROT_CONFIG1_REGION57_Pos) /*!< Bit mask of REGION57 field. */

+#define BPROT_CONFIG1_REGION57_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION57_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 24 : Enable protection for region 56. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION56_Pos (24UL) /*!< Position of REGION56 field. */

+#define BPROT_CONFIG1_REGION56_Msk (0x1UL << BPROT_CONFIG1_REGION56_Pos) /*!< Bit mask of REGION56 field. */

+#define BPROT_CONFIG1_REGION56_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION56_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 23 : Enable protection for region 55. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION55_Pos (23UL) /*!< Position of REGION55 field. */

+#define BPROT_CONFIG1_REGION55_Msk (0x1UL << BPROT_CONFIG1_REGION55_Pos) /*!< Bit mask of REGION55 field. */

+#define BPROT_CONFIG1_REGION55_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION55_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 22 : Enable protection for region 54. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION54_Pos (22UL) /*!< Position of REGION54 field. */

+#define BPROT_CONFIG1_REGION54_Msk (0x1UL << BPROT_CONFIG1_REGION54_Pos) /*!< Bit mask of REGION54 field. */

+#define BPROT_CONFIG1_REGION54_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION54_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 21 : Enable protection for region 53. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION53_Pos (21UL) /*!< Position of REGION53 field. */

+#define BPROT_CONFIG1_REGION53_Msk (0x1UL << BPROT_CONFIG1_REGION53_Pos) /*!< Bit mask of REGION53 field. */

+#define BPROT_CONFIG1_REGION53_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION53_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 20 : Enable protection for region 52. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION52_Pos (20UL) /*!< Position of REGION52 field. */

+#define BPROT_CONFIG1_REGION52_Msk (0x1UL << BPROT_CONFIG1_REGION52_Pos) /*!< Bit mask of REGION52 field. */

+#define BPROT_CONFIG1_REGION52_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION52_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 19 : Enable protection for region 51. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION51_Pos (19UL) /*!< Position of REGION51 field. */

+#define BPROT_CONFIG1_REGION51_Msk (0x1UL << BPROT_CONFIG1_REGION51_Pos) /*!< Bit mask of REGION51 field. */

+#define BPROT_CONFIG1_REGION51_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION51_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 18 : Enable protection for region 50. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION50_Pos (18UL) /*!< Position of REGION50 field. */

+#define BPROT_CONFIG1_REGION50_Msk (0x1UL << BPROT_CONFIG1_REGION50_Pos) /*!< Bit mask of REGION50 field. */

+#define BPROT_CONFIG1_REGION50_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION50_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 17 : Enable protection for region 49. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION49_Pos (17UL) /*!< Position of REGION49 field. */

+#define BPROT_CONFIG1_REGION49_Msk (0x1UL << BPROT_CONFIG1_REGION49_Pos) /*!< Bit mask of REGION49 field. */

+#define BPROT_CONFIG1_REGION49_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION49_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 16 : Enable protection for region 48. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION48_Pos (16UL) /*!< Position of REGION48 field. */

+#define BPROT_CONFIG1_REGION48_Msk (0x1UL << BPROT_CONFIG1_REGION48_Pos) /*!< Bit mask of REGION48 field. */

+#define BPROT_CONFIG1_REGION48_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION48_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 15 : Enable protection for region 47. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION47_Pos (15UL) /*!< Position of REGION47 field. */

+#define BPROT_CONFIG1_REGION47_Msk (0x1UL << BPROT_CONFIG1_REGION47_Pos) /*!< Bit mask of REGION47 field. */

+#define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 14 : Enable protection for region 46. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION46_Pos (14UL) /*!< Position of REGION46 field. */

+#define BPROT_CONFIG1_REGION46_Msk (0x1UL << BPROT_CONFIG1_REGION46_Pos) /*!< Bit mask of REGION46 field. */

+#define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 13 : Enable protection for region 45. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION45_Pos (13UL) /*!< Position of REGION45 field. */

+#define BPROT_CONFIG1_REGION45_Msk (0x1UL << BPROT_CONFIG1_REGION45_Pos) /*!< Bit mask of REGION45 field. */

+#define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 12 : Enable protection for region 44. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION44_Pos (12UL) /*!< Position of REGION44 field. */

+#define BPROT_CONFIG1_REGION44_Msk (0x1UL << BPROT_CONFIG1_REGION44_Pos) /*!< Bit mask of REGION44 field. */

+#define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 11 : Enable protection for region 43. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION43_Pos (11UL) /*!< Position of REGION43 field. */

+#define BPROT_CONFIG1_REGION43_Msk (0x1UL << BPROT_CONFIG1_REGION43_Pos) /*!< Bit mask of REGION43 field. */

+#define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 10 : Enable protection for region 42. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION42_Pos (10UL) /*!< Position of REGION42 field. */

+#define BPROT_CONFIG1_REGION42_Msk (0x1UL << BPROT_CONFIG1_REGION42_Pos) /*!< Bit mask of REGION42 field. */

+#define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 9 : Enable protection for region 41. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION41_Pos (9UL) /*!< Position of REGION41 field. */

+#define BPROT_CONFIG1_REGION41_Msk (0x1UL << BPROT_CONFIG1_REGION41_Pos) /*!< Bit mask of REGION41 field. */

+#define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 8 : Enable protection for region 40. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION40_Pos (8UL) /*!< Position of REGION40 field. */

+#define BPROT_CONFIG1_REGION40_Msk (0x1UL << BPROT_CONFIG1_REGION40_Pos) /*!< Bit mask of REGION40 field. */

+#define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 7 : Enable protection for region 39. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION39_Pos (7UL) /*!< Position of REGION39 field. */

+#define BPROT_CONFIG1_REGION39_Msk (0x1UL << BPROT_CONFIG1_REGION39_Pos) /*!< Bit mask of REGION39 field. */

+#define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 6 : Enable protection for region 38. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION38_Pos (6UL) /*!< Position of REGION38 field. */

+#define BPROT_CONFIG1_REGION38_Msk (0x1UL << BPROT_CONFIG1_REGION38_Pos) /*!< Bit mask of REGION38 field. */

+#define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 5 : Enable protection for region 37. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION37_Pos (5UL) /*!< Position of REGION37 field. */

+#define BPROT_CONFIG1_REGION37_Msk (0x1UL << BPROT_CONFIG1_REGION37_Pos) /*!< Bit mask of REGION37 field. */

+#define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 4 : Enable protection for region 36. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION36_Pos (4UL) /*!< Position of REGION36 field. */

+#define BPROT_CONFIG1_REGION36_Msk (0x1UL << BPROT_CONFIG1_REGION36_Pos) /*!< Bit mask of REGION36 field. */

+#define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 3 : Enable protection for region 35. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION35_Pos (3UL) /*!< Position of REGION35 field. */

+#define BPROT_CONFIG1_REGION35_Msk (0x1UL << BPROT_CONFIG1_REGION35_Pos) /*!< Bit mask of REGION35 field. */

+#define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 2 : Enable protection for region 34. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */

+#define BPROT_CONFIG1_REGION34_Msk (0x1UL << BPROT_CONFIG1_REGION34_Pos) /*!< Bit mask of REGION34 field. */

+#define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 1 : Enable protection for region 33. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION33_Pos (1UL) /*!< Position of REGION33 field. */

+#define BPROT_CONFIG1_REGION33_Msk (0x1UL << BPROT_CONFIG1_REGION33_Pos) /*!< Bit mask of REGION33 field. */

+#define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 0 : Enable protection for region 32. Write '0' has no effect. */

+#define BPROT_CONFIG1_REGION32_Pos (0UL) /*!< Position of REGION32 field. */

+#define BPROT_CONFIG1_REGION32_Msk (0x1UL << BPROT_CONFIG1_REGION32_Pos) /*!< Bit mask of REGION32 field. */

+#define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */

+

+/* Register: BPROT_DISABLEINDEBUG */

+/* Description: Disable protection mechanism in debug interface mode */

+

+/* Bit 0 : Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode. */

+#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */

+#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */

+#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enable in debug */

+#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disable in debug */

+

+/* Register: BPROT_CONFIG2 */

+/* Description: Block protect configuration register 2 */

+

+/* Bit 31 : Enable protection for region 95. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION95_Pos (31UL) /*!< Position of REGION95 field. */

+#define BPROT_CONFIG2_REGION95_Msk (0x1UL << BPROT_CONFIG2_REGION95_Pos) /*!< Bit mask of REGION95 field. */

+#define BPROT_CONFIG2_REGION95_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION95_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 30 : Enable protection for region 94. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION94_Pos (30UL) /*!< Position of REGION94 field. */

+#define BPROT_CONFIG2_REGION94_Msk (0x1UL << BPROT_CONFIG2_REGION94_Pos) /*!< Bit mask of REGION94 field. */

+#define BPROT_CONFIG2_REGION94_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION94_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 29 : Enable protection for region 93. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION93_Pos (29UL) /*!< Position of REGION93 field. */

+#define BPROT_CONFIG2_REGION93_Msk (0x1UL << BPROT_CONFIG2_REGION93_Pos) /*!< Bit mask of REGION93 field. */

+#define BPROT_CONFIG2_REGION93_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION93_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 28 : Enable protection for region 92. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION92_Pos (28UL) /*!< Position of REGION92 field. */

+#define BPROT_CONFIG2_REGION92_Msk (0x1UL << BPROT_CONFIG2_REGION92_Pos) /*!< Bit mask of REGION92 field. */

+#define BPROT_CONFIG2_REGION92_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION92_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 27 : Enable protection for region 91. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION91_Pos (27UL) /*!< Position of REGION91 field. */

+#define BPROT_CONFIG2_REGION91_Msk (0x1UL << BPROT_CONFIG2_REGION91_Pos) /*!< Bit mask of REGION91 field. */

+#define BPROT_CONFIG2_REGION91_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION91_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 26 : Enable protection for region 90. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION90_Pos (26UL) /*!< Position of REGION90 field. */

+#define BPROT_CONFIG2_REGION90_Msk (0x1UL << BPROT_CONFIG2_REGION90_Pos) /*!< Bit mask of REGION90 field. */

+#define BPROT_CONFIG2_REGION90_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION90_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 25 : Enable protection for region 89. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION89_Pos (25UL) /*!< Position of REGION89 field. */

+#define BPROT_CONFIG2_REGION89_Msk (0x1UL << BPROT_CONFIG2_REGION89_Pos) /*!< Bit mask of REGION89 field. */

+#define BPROT_CONFIG2_REGION89_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION89_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 24 : Enable protection for region 88. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION88_Pos (24UL) /*!< Position of REGION88 field. */

+#define BPROT_CONFIG2_REGION88_Msk (0x1UL << BPROT_CONFIG2_REGION88_Pos) /*!< Bit mask of REGION88 field. */

+#define BPROT_CONFIG2_REGION88_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION88_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 23 : Enable protection for region 87. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION87_Pos (23UL) /*!< Position of REGION87 field. */

+#define BPROT_CONFIG2_REGION87_Msk (0x1UL << BPROT_CONFIG2_REGION87_Pos) /*!< Bit mask of REGION87 field. */

+#define BPROT_CONFIG2_REGION87_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION87_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 22 : Enable protection for region 86. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION86_Pos (22UL) /*!< Position of REGION86 field. */

+#define BPROT_CONFIG2_REGION86_Msk (0x1UL << BPROT_CONFIG2_REGION86_Pos) /*!< Bit mask of REGION86 field. */

+#define BPROT_CONFIG2_REGION86_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION86_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 21 : Enable protection for region 85. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION85_Pos (21UL) /*!< Position of REGION85 field. */

+#define BPROT_CONFIG2_REGION85_Msk (0x1UL << BPROT_CONFIG2_REGION85_Pos) /*!< Bit mask of REGION85 field. */

+#define BPROT_CONFIG2_REGION85_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION85_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 20 : Enable protection for region 84. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION84_Pos (20UL) /*!< Position of REGION84 field. */

+#define BPROT_CONFIG2_REGION84_Msk (0x1UL << BPROT_CONFIG2_REGION84_Pos) /*!< Bit mask of REGION84 field. */

+#define BPROT_CONFIG2_REGION84_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION84_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 19 : Enable protection for region 83. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION83_Pos (19UL) /*!< Position of REGION83 field. */

+#define BPROT_CONFIG2_REGION83_Msk (0x1UL << BPROT_CONFIG2_REGION83_Pos) /*!< Bit mask of REGION83 field. */

+#define BPROT_CONFIG2_REGION83_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION83_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 18 : Enable protection for region 82. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION82_Pos (18UL) /*!< Position of REGION82 field. */

+#define BPROT_CONFIG2_REGION82_Msk (0x1UL << BPROT_CONFIG2_REGION82_Pos) /*!< Bit mask of REGION82 field. */

+#define BPROT_CONFIG2_REGION82_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION82_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 17 : Enable protection for region 81. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION81_Pos (17UL) /*!< Position of REGION81 field. */

+#define BPROT_CONFIG2_REGION81_Msk (0x1UL << BPROT_CONFIG2_REGION81_Pos) /*!< Bit mask of REGION81 field. */

+#define BPROT_CONFIG2_REGION81_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION81_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 16 : Enable protection for region 80. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION80_Pos (16UL) /*!< Position of REGION80 field. */

+#define BPROT_CONFIG2_REGION80_Msk (0x1UL << BPROT_CONFIG2_REGION80_Pos) /*!< Bit mask of REGION80 field. */

+#define BPROT_CONFIG2_REGION80_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION80_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 15 : Enable protection for region 79. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION79_Pos (15UL) /*!< Position of REGION79 field. */

+#define BPROT_CONFIG2_REGION79_Msk (0x1UL << BPROT_CONFIG2_REGION79_Pos) /*!< Bit mask of REGION79 field. */

+#define BPROT_CONFIG2_REGION79_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION79_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 14 : Enable protection for region 78. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION78_Pos (14UL) /*!< Position of REGION78 field. */

+#define BPROT_CONFIG2_REGION78_Msk (0x1UL << BPROT_CONFIG2_REGION78_Pos) /*!< Bit mask of REGION78 field. */

+#define BPROT_CONFIG2_REGION78_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION78_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 13 : Enable protection for region 77. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION77_Pos (13UL) /*!< Position of REGION77 field. */

+#define BPROT_CONFIG2_REGION77_Msk (0x1UL << BPROT_CONFIG2_REGION77_Pos) /*!< Bit mask of REGION77 field. */

+#define BPROT_CONFIG2_REGION77_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION77_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 12 : Enable protection for region 76. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION76_Pos (12UL) /*!< Position of REGION76 field. */

+#define BPROT_CONFIG2_REGION76_Msk (0x1UL << BPROT_CONFIG2_REGION76_Pos) /*!< Bit mask of REGION76 field. */

+#define BPROT_CONFIG2_REGION76_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION76_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 11 : Enable protection for region 75. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION75_Pos (11UL) /*!< Position of REGION75 field. */

+#define BPROT_CONFIG2_REGION75_Msk (0x1UL << BPROT_CONFIG2_REGION75_Pos) /*!< Bit mask of REGION75 field. */

+#define BPROT_CONFIG2_REGION75_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION75_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 10 : Enable protection for region 74. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION74_Pos (10UL) /*!< Position of REGION74 field. */

+#define BPROT_CONFIG2_REGION74_Msk (0x1UL << BPROT_CONFIG2_REGION74_Pos) /*!< Bit mask of REGION74 field. */

+#define BPROT_CONFIG2_REGION74_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION74_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 9 : Enable protection for region 73. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION73_Pos (9UL) /*!< Position of REGION73 field. */

+#define BPROT_CONFIG2_REGION73_Msk (0x1UL << BPROT_CONFIG2_REGION73_Pos) /*!< Bit mask of REGION73 field. */

+#define BPROT_CONFIG2_REGION73_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION73_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 8 : Enable protection for region 72. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION72_Pos (8UL) /*!< Position of REGION72 field. */

+#define BPROT_CONFIG2_REGION72_Msk (0x1UL << BPROT_CONFIG2_REGION72_Pos) /*!< Bit mask of REGION72 field. */

+#define BPROT_CONFIG2_REGION72_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION72_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 7 : Enable protection for region 71. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION71_Pos (7UL) /*!< Position of REGION71 field. */

+#define BPROT_CONFIG2_REGION71_Msk (0x1UL << BPROT_CONFIG2_REGION71_Pos) /*!< Bit mask of REGION71 field. */

+#define BPROT_CONFIG2_REGION71_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION71_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 6 : Enable protection for region 70. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION70_Pos (6UL) /*!< Position of REGION70 field. */

+#define BPROT_CONFIG2_REGION70_Msk (0x1UL << BPROT_CONFIG2_REGION70_Pos) /*!< Bit mask of REGION70 field. */

+#define BPROT_CONFIG2_REGION70_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION70_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 5 : Enable protection for region 69. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION69_Pos (5UL) /*!< Position of REGION69 field. */

+#define BPROT_CONFIG2_REGION69_Msk (0x1UL << BPROT_CONFIG2_REGION69_Pos) /*!< Bit mask of REGION69 field. */

+#define BPROT_CONFIG2_REGION69_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION69_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 4 : Enable protection for region 68. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION68_Pos (4UL) /*!< Position of REGION68 field. */

+#define BPROT_CONFIG2_REGION68_Msk (0x1UL << BPROT_CONFIG2_REGION68_Pos) /*!< Bit mask of REGION68 field. */

+#define BPROT_CONFIG2_REGION68_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION68_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 3 : Enable protection for region 67. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION67_Pos (3UL) /*!< Position of REGION67 field. */

+#define BPROT_CONFIG2_REGION67_Msk (0x1UL << BPROT_CONFIG2_REGION67_Pos) /*!< Bit mask of REGION67 field. */

+#define BPROT_CONFIG2_REGION67_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION67_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 2 : Enable protection for region 66. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION66_Pos (2UL) /*!< Position of REGION66 field. */

+#define BPROT_CONFIG2_REGION66_Msk (0x1UL << BPROT_CONFIG2_REGION66_Pos) /*!< Bit mask of REGION66 field. */

+#define BPROT_CONFIG2_REGION66_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION66_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 1 : Enable protection for region 65. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION65_Pos (1UL) /*!< Position of REGION65 field. */

+#define BPROT_CONFIG2_REGION65_Msk (0x1UL << BPROT_CONFIG2_REGION65_Pos) /*!< Bit mask of REGION65 field. */

+#define BPROT_CONFIG2_REGION65_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION65_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 0 : Enable protection for region 64. Write '0' has no effect. */

+#define BPROT_CONFIG2_REGION64_Pos (0UL) /*!< Position of REGION64 field. */

+#define BPROT_CONFIG2_REGION64_Msk (0x1UL << BPROT_CONFIG2_REGION64_Pos) /*!< Bit mask of REGION64 field. */

+#define BPROT_CONFIG2_REGION64_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG2_REGION64_Enabled (1UL) /*!< Protection enabled */

+

+/* Register: BPROT_CONFIG3 */

+/* Description: Block protect configuration register 3 */

+

+/* Bit 31 : Enable protection for region 127. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION127_Pos (31UL) /*!< Position of REGION127 field. */

+#define BPROT_CONFIG3_REGION127_Msk (0x1UL << BPROT_CONFIG3_REGION127_Pos) /*!< Bit mask of REGION127 field. */

+#define BPROT_CONFIG3_REGION127_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION127_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 30 : Enable protection for region 126. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION126_Pos (30UL) /*!< Position of REGION126 field. */

+#define BPROT_CONFIG3_REGION126_Msk (0x1UL << BPROT_CONFIG3_REGION126_Pos) /*!< Bit mask of REGION126 field. */

+#define BPROT_CONFIG3_REGION126_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION126_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 29 : Enable protection for region 125. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION125_Pos (29UL) /*!< Position of REGION125 field. */

+#define BPROT_CONFIG3_REGION125_Msk (0x1UL << BPROT_CONFIG3_REGION125_Pos) /*!< Bit mask of REGION125 field. */

+#define BPROT_CONFIG3_REGION125_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION125_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 28 : Enable protection for region 124. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION124_Pos (28UL) /*!< Position of REGION124 field. */

+#define BPROT_CONFIG3_REGION124_Msk (0x1UL << BPROT_CONFIG3_REGION124_Pos) /*!< Bit mask of REGION124 field. */

+#define BPROT_CONFIG3_REGION124_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION124_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 27 : Enable protection for region 123. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION123_Pos (27UL) /*!< Position of REGION123 field. */

+#define BPROT_CONFIG3_REGION123_Msk (0x1UL << BPROT_CONFIG3_REGION123_Pos) /*!< Bit mask of REGION123 field. */

+#define BPROT_CONFIG3_REGION123_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION123_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 26 : Enable protection for region 122. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION122_Pos (26UL) /*!< Position of REGION122 field. */

+#define BPROT_CONFIG3_REGION122_Msk (0x1UL << BPROT_CONFIG3_REGION122_Pos) /*!< Bit mask of REGION122 field. */

+#define BPROT_CONFIG3_REGION122_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION122_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 25 : Enable protection for region 121. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION121_Pos (25UL) /*!< Position of REGION121 field. */

+#define BPROT_CONFIG3_REGION121_Msk (0x1UL << BPROT_CONFIG3_REGION121_Pos) /*!< Bit mask of REGION121 field. */

+#define BPROT_CONFIG3_REGION121_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION121_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 24 : Enable protection for region 120. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION120_Pos (24UL) /*!< Position of REGION120 field. */

+#define BPROT_CONFIG3_REGION120_Msk (0x1UL << BPROT_CONFIG3_REGION120_Pos) /*!< Bit mask of REGION120 field. */

+#define BPROT_CONFIG3_REGION120_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION120_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 23 : Enable protection for region 119. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION119_Pos (23UL) /*!< Position of REGION119 field. */

+#define BPROT_CONFIG3_REGION119_Msk (0x1UL << BPROT_CONFIG3_REGION119_Pos) /*!< Bit mask of REGION119 field. */

+#define BPROT_CONFIG3_REGION119_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION119_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 22 : Enable protection for region 118. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION118_Pos (22UL) /*!< Position of REGION118 field. */

+#define BPROT_CONFIG3_REGION118_Msk (0x1UL << BPROT_CONFIG3_REGION118_Pos) /*!< Bit mask of REGION118 field. */

+#define BPROT_CONFIG3_REGION118_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION118_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 21 : Enable protection for region 117. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION117_Pos (21UL) /*!< Position of REGION117 field. */

+#define BPROT_CONFIG3_REGION117_Msk (0x1UL << BPROT_CONFIG3_REGION117_Pos) /*!< Bit mask of REGION117 field. */

+#define BPROT_CONFIG3_REGION117_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION117_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 20 : Enable protection for region 116. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION116_Pos (20UL) /*!< Position of REGION116 field. */

+#define BPROT_CONFIG3_REGION116_Msk (0x1UL << BPROT_CONFIG3_REGION116_Pos) /*!< Bit mask of REGION116 field. */

+#define BPROT_CONFIG3_REGION116_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION116_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 19 : Enable protection for region 115. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION115_Pos (19UL) /*!< Position of REGION115 field. */

+#define BPROT_CONFIG3_REGION115_Msk (0x1UL << BPROT_CONFIG3_REGION115_Pos) /*!< Bit mask of REGION115 field. */

+#define BPROT_CONFIG3_REGION115_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION115_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 18 : Enable protection for region 114. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION114_Pos (18UL) /*!< Position of REGION114 field. */

+#define BPROT_CONFIG3_REGION114_Msk (0x1UL << BPROT_CONFIG3_REGION114_Pos) /*!< Bit mask of REGION114 field. */

+#define BPROT_CONFIG3_REGION114_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION114_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 17 : Enable protection for region 113. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION113_Pos (17UL) /*!< Position of REGION113 field. */

+#define BPROT_CONFIG3_REGION113_Msk (0x1UL << BPROT_CONFIG3_REGION113_Pos) /*!< Bit mask of REGION113 field. */

+#define BPROT_CONFIG3_REGION113_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION113_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 16 : Enable protection for region 112. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION112_Pos (16UL) /*!< Position of REGION112 field. */

+#define BPROT_CONFIG3_REGION112_Msk (0x1UL << BPROT_CONFIG3_REGION112_Pos) /*!< Bit mask of REGION112 field. */

+#define BPROT_CONFIG3_REGION112_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION112_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 15 : Enable protection for region 111. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION111_Pos (15UL) /*!< Position of REGION111 field. */

+#define BPROT_CONFIG3_REGION111_Msk (0x1UL << BPROT_CONFIG3_REGION111_Pos) /*!< Bit mask of REGION111 field. */

+#define BPROT_CONFIG3_REGION111_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION111_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 14 : Enable protection for region 110. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION110_Pos (14UL) /*!< Position of REGION110 field. */

+#define BPROT_CONFIG3_REGION110_Msk (0x1UL << BPROT_CONFIG3_REGION110_Pos) /*!< Bit mask of REGION110 field. */

+#define BPROT_CONFIG3_REGION110_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION110_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 13 : Enable protection for region 109. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION109_Pos (13UL) /*!< Position of REGION109 field. */

+#define BPROT_CONFIG3_REGION109_Msk (0x1UL << BPROT_CONFIG3_REGION109_Pos) /*!< Bit mask of REGION109 field. */

+#define BPROT_CONFIG3_REGION109_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION109_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 12 : Enable protection for region 108. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION108_Pos (12UL) /*!< Position of REGION108 field. */

+#define BPROT_CONFIG3_REGION108_Msk (0x1UL << BPROT_CONFIG3_REGION108_Pos) /*!< Bit mask of REGION108 field. */

+#define BPROT_CONFIG3_REGION108_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION108_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 11 : Enable protection for region 107. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION107_Pos (11UL) /*!< Position of REGION107 field. */

+#define BPROT_CONFIG3_REGION107_Msk (0x1UL << BPROT_CONFIG3_REGION107_Pos) /*!< Bit mask of REGION107 field. */

+#define BPROT_CONFIG3_REGION107_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION107_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 10 : Enable protection for region 106. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION106_Pos (10UL) /*!< Position of REGION106 field. */

+#define BPROT_CONFIG3_REGION106_Msk (0x1UL << BPROT_CONFIG3_REGION106_Pos) /*!< Bit mask of REGION106 field. */

+#define BPROT_CONFIG3_REGION106_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION106_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 9 : Enable protection for region 105. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION105_Pos (9UL) /*!< Position of REGION105 field. */

+#define BPROT_CONFIG3_REGION105_Msk (0x1UL << BPROT_CONFIG3_REGION105_Pos) /*!< Bit mask of REGION105 field. */

+#define BPROT_CONFIG3_REGION105_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION105_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 8 : Enable protection for region 104. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION104_Pos (8UL) /*!< Position of REGION104 field. */

+#define BPROT_CONFIG3_REGION104_Msk (0x1UL << BPROT_CONFIG3_REGION104_Pos) /*!< Bit mask of REGION104 field. */

+#define BPROT_CONFIG3_REGION104_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION104_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 7 : Enable protection for region 103. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION103_Pos (7UL) /*!< Position of REGION103 field. */

+#define BPROT_CONFIG3_REGION103_Msk (0x1UL << BPROT_CONFIG3_REGION103_Pos) /*!< Bit mask of REGION103 field. */

+#define BPROT_CONFIG3_REGION103_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION103_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 6 : Enable protection for region 102. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION102_Pos (6UL) /*!< Position of REGION102 field. */

+#define BPROT_CONFIG3_REGION102_Msk (0x1UL << BPROT_CONFIG3_REGION102_Pos) /*!< Bit mask of REGION102 field. */

+#define BPROT_CONFIG3_REGION102_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION102_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 5 : Enable protection for region 101. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION101_Pos (5UL) /*!< Position of REGION101 field. */

+#define BPROT_CONFIG3_REGION101_Msk (0x1UL << BPROT_CONFIG3_REGION101_Pos) /*!< Bit mask of REGION101 field. */

+#define BPROT_CONFIG3_REGION101_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION101_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 4 : Enable protection for region 100. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION100_Pos (4UL) /*!< Position of REGION100 field. */

+#define BPROT_CONFIG3_REGION100_Msk (0x1UL << BPROT_CONFIG3_REGION100_Pos) /*!< Bit mask of REGION100 field. */

+#define BPROT_CONFIG3_REGION100_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION100_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 3 : Enable protection for region 99. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION99_Pos (3UL) /*!< Position of REGION99 field. */

+#define BPROT_CONFIG3_REGION99_Msk (0x1UL << BPROT_CONFIG3_REGION99_Pos) /*!< Bit mask of REGION99 field. */

+#define BPROT_CONFIG3_REGION99_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION99_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 2 : Enable protection for region 98. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION98_Pos (2UL) /*!< Position of REGION98 field. */

+#define BPROT_CONFIG3_REGION98_Msk (0x1UL << BPROT_CONFIG3_REGION98_Pos) /*!< Bit mask of REGION98 field. */

+#define BPROT_CONFIG3_REGION98_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION98_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 1 : Enable protection for region 97. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION97_Pos (1UL) /*!< Position of REGION97 field. */

+#define BPROT_CONFIG3_REGION97_Msk (0x1UL << BPROT_CONFIG3_REGION97_Pos) /*!< Bit mask of REGION97 field. */

+#define BPROT_CONFIG3_REGION97_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION97_Enabled (1UL) /*!< Protection enabled */

+

+/* Bit 0 : Enable protection for region 96. Write '0' has no effect. */

+#define BPROT_CONFIG3_REGION96_Pos (0UL) /*!< Position of REGION96 field. */

+#define BPROT_CONFIG3_REGION96_Msk (0x1UL << BPROT_CONFIG3_REGION96_Pos) /*!< Bit mask of REGION96 field. */

+#define BPROT_CONFIG3_REGION96_Disabled (0UL) /*!< Protection disabled */

+#define BPROT_CONFIG3_REGION96_Enabled (1UL) /*!< Protection enabled */

+

+

+/* Peripheral: CCM */

+/* Description: AES CCM Mode Encryption */

+

+/* Register: CCM_SHORTS */

+/* Description: Shortcut register */

+

+/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */

+#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */

+#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */

+#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */

+#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */

+

+/* Register: CCM_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 2 : Write '1' to Enable interrupt for ERROR event */

+#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */

+#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */

+#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */

+#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */

+#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */

+

+/* Bit 1 : Write '1' to Enable interrupt for ENDCRYPT event */

+#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */

+#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */

+#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */

+#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */

+#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */

+

+/* Bit 0 : Write '1' to Enable interrupt for ENDKSGEN event */

+#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */

+#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */

+#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */

+#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */

+#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */

+

+/* Register: CCM_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 2 : Write '1' to Disable interrupt for ERROR event */

+#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */

+#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */

+#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */

+#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */

+#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */

+

+/* Bit 1 : Write '1' to Disable interrupt for ENDCRYPT event */

+#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */

+#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */

+#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */

+#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */

+#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */

+

+/* Bit 0 : Write '1' to Disable interrupt for ENDKSGEN event */

+#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */

+#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */

+#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */

+#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */

+#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */

+

+/* Register: CCM_MICSTATUS */

+/* Description: MIC check result */

+

+/* Bit 0 : The result of the MIC check performed during the previous decryption operation */

+#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */

+#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */

+#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */

+#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */

+

+/* Register: CCM_ENABLE */

+/* Description: Enable */

+

+/* Bits 1..0 : Enable or disable CCM */

+#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */

+#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */

+#define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */

+#define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */

+

+/* Register: CCM_MODE */

+/* Description: Operation mode */

+

+/* Bit 24 : Packet length configuration */

+#define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */

+#define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */

+#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field is 5-bit */

+#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field is 8-bit */

+

+/* Bit 16 : Data rate that the CCM shall run in synch with */

+#define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */

+#define CCM_MODE_DATARATE_Msk (0x1UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */

+#define CCM_MODE_DATARATE_1Mbit (0UL) /*!< In synch with 1 Mbit data rate */

+#define CCM_MODE_DATARATE_2Mbit (1UL) /*!< In synch with 2 Mbit data rate */

+

+/* Bit 0 : The mode of operation to be used */

+#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */

+#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */

+#define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */

+#define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */

+

+/* Register: CCM_CNFPTR */

+/* Description: Pointer to data structure holding AES key and NONCE vector */

+

+/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */

+#define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */

+#define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */

+

+/* Register: CCM_INPTR */

+/* Description: Input pointer */

+

+/* Bits 31..0 : Input pointer */

+#define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */

+#define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */

+

+/* Register: CCM_OUTPTR */

+/* Description: Output pointer */

+

+/* Bits 31..0 : Output pointer */

+#define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */

+#define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */

+

+/* Register: CCM_SCRATCHPTR */

+/* Description: Pointer to data area used for temporary storage */

+

+/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. */

+#define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */

+#define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */

+

+

+/* Peripheral: CLOCK */

+/* Description: Clock control */

+

+/* Register: CLOCK_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 4 : Write '1' to Enable interrupt for CTTO event */

+#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */

+#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */

+#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */

+#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */

+#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */

+

+/* Bit 3 : Write '1' to Enable interrupt for DONE event */

+#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */

+#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */

+#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */

+#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */

+#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */

+

+/* Bit 1 : Write '1' to Enable interrupt for LFCLKSTARTED event */

+#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */

+#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */

+#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */

+#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */

+#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */

+

+/* Bit 0 : Write '1' to Enable interrupt for HFCLKSTARTED event */

+#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */

+#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */

+#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */

+#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */

+#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */

+

+/* Register: CLOCK_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 4 : Write '1' to Disable interrupt for CTTO event */

+#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */

+#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */

+#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */

+#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */

+#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */

+

+/* Bit 3 : Write '1' to Disable interrupt for DONE event */

+#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */

+#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */

+#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */

+#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */

+#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */

+

+/* Bit 1 : Write '1' to Disable interrupt for LFCLKSTARTED event */

+#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */

+#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */

+#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */

+#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */

+#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */

+

+/* Bit 0 : Write '1' to Disable interrupt for HFCLKSTARTED event */

+#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */

+#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */

+#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */

+#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */

+#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */

+

+/* Register: CLOCK_HFCLKRUN */

+/* Description: Status indicating that HFCLKSTART task has been triggered */

+

+/* Bit 0 : HFCLKSTART task triggered or not */

+#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */

+#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */

+#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */

+#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */

+

+/* Register: CLOCK_HFCLKSTAT */

+/* Description: HFCLK status */

+

+/* Bit 16 : HFCLK state */

+#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */

+#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */

+#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */

+#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */

+

+/* Bit 0 : Source of HFCLK */

+#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */

+#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */

+#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */

+#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */

+

+/* Register: CLOCK_LFCLKRUN */

+/* Description: Status indicating that LFCLKSTART task has been triggered */

+

+/* Bit 0 : LFCLKSTART task triggered or not */

+#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */

+#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */

+#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */

+#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */

+

+/* Register: CLOCK_LFCLKSTAT */

+/* Description: LFCLK status */

+

+/* Bit 16 : LFCLK state */

+#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */

+#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */

+#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */

+#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */

+

+/* Bits 1..0 : Source of LFCLK */

+#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */

+#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */

+#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */

+#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */

+#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */

+

+/* Register: CLOCK_LFCLKSRCCOPY */

+/* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */

+

+/* Bits 1..0 : Clock source */

+#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */

+#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */

+#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */

+#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */

+#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */

+

+/* Register: CLOCK_LFCLKSRC */

+/* Description: Clock source for the LFCLK */

+

+/* Bits 1..0 : Clock source */

+#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */

+#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */

+#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */

+#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */

+#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */

+

+/* Register: CLOCK_CTIV */

+/* Description: Calibration timer interval (retained register, same reset behaviour as RESETREAS) */

+

+/* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */

+#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */

+#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */

+

+/* Register: CLOCK_TRACECONFIG */

+/* Description: Clocking options for the Trace Port debug interface */

+

+/* Bits 17..16 : Pin multiplexing of trace signals. */

+#define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */

+#define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */

+#define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< GPIOs multiplexed onto all trace-pins */

+#define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins */

+#define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. */

+

+/* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */

+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */

+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */

+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */

+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */

+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */

+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */

+

+

+/* Peripheral: COMP */

+/* Description: Comparator */

+

+/* Register: COMP_SHORTS */

+/* Description: Shortcut register */

+

+/* Bit 4 : Shortcut between CROSS event and STOP task */

+#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */

+#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */

+#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */

+#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 3 : Shortcut between UP event and STOP task */

+#define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */

+#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */

+#define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */

+#define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 2 : Shortcut between DOWN event and STOP task */

+#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */

+#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */

+#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */

+#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 1 : Shortcut between READY event and STOP task */

+#define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */

+#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */

+#define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */

+#define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 0 : Shortcut between READY event and SAMPLE task */

+#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */

+#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */

+#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */

+#define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */

+

+/* Register: COMP_INTEN */

+/* Description: Enable or disable interrupt */

+

+/* Bit 3 : Enable or disable interrupt for CROSS event */

+#define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */

+#define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */

+#define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */

+#define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */

+

+/* Bit 2 : Enable or disable interrupt for UP event */

+#define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */

+#define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */

+#define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */

+#define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */

+

+/* Bit 1 : Enable or disable interrupt for DOWN event */

+#define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */

+#define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */

+#define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */

+#define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */

+

+/* Bit 0 : Enable or disable interrupt for READY event */

+#define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */

+#define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */

+#define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */

+#define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */

+

+/* Register: COMP_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 3 : Write '1' to Enable interrupt for CROSS event */

+#define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */

+#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */

+#define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */

+#define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */

+#define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */

+

+/* Bit 2 : Write '1' to Enable interrupt for UP event */

+#define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */

+#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */

+#define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */

+#define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */

+#define COMP_INTENSET_UP_Set (1UL) /*!< Enable */

+

+/* Bit 1 : Write '1' to Enable interrupt for DOWN event */

+#define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */

+#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */

+#define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */

+#define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */

+#define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */

+

+/* Bit 0 : Write '1' to Enable interrupt for READY event */

+#define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */

+#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */

+#define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */

+#define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */

+#define COMP_INTENSET_READY_Set (1UL) /*!< Enable */

+

+/* Register: COMP_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 3 : Write '1' to Disable interrupt for CROSS event */

+#define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */

+#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */

+#define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */

+#define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */

+#define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */

+

+/* Bit 2 : Write '1' to Disable interrupt for UP event */

+#define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */

+#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */

+#define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */

+#define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */

+#define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */

+

+/* Bit 1 : Write '1' to Disable interrupt for DOWN event */

+#define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */

+#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */

+#define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */

+#define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */

+#define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */

+

+/* Bit 0 : Write '1' to Disable interrupt for READY event */

+#define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */

+#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */

+#define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */

+#define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */

+#define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */

+

+/* Register: COMP_RESULT */

+/* Description: Compare result */

+

+/* Bit 0 : Result of last compare. Decision point SAMPLE task. */

+#define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */

+#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */

+#define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ &lt; VIN-) */

+#define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ &gt; VIN-) */

+

+/* Register: COMP_ENABLE */

+/* Description: COMP enable */

+

+/* Bits 1..0 : Enable or disable COMP */

+#define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */

+#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */

+#define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */

+#define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */

+

+/* Register: COMP_PSEL */

+/* Description: Pin select */

+

+/* Bits 2..0 : Analog pin select */

+#define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */

+#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */

+#define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */

+#define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */

+#define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */

+#define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */

+#define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */

+#define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */

+#define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */

+#define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */

+

+/* Register: COMP_REFSEL */

+/* Description: Reference source select */

+

+/* Bits 2..0 : Reference select */

+#define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */

+#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */

+#define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) */

+#define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) */

+#define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) */

+#define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */

+#define COMP_REFSEL_REFSEL_ARef (7UL) /*!< VREF = AREF (VDD &gt;= VREF &gt;= AREFMIN) */

+

+/* Register: COMP_EXTREFSEL */

+/* Description: External reference select */

+

+/* Bit 0 : External analog reference select */

+#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */

+#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */

+#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */

+#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */

+

+/* Register: COMP_TH */

+/* Description: Threshold configuration for hysteresis unit */

+

+/* Bits 13..8 : VUP = (THUP+1)/64*VREF */

+#define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */

+#define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */

+

+/* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */

+#define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */

+#define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */

+

+/* Register: COMP_MODE */

+/* Description: Mode configuration */

+

+/* Bit 8 : Main operation mode */

+#define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */

+#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */

+#define COMP_MODE_MAIN_SE (0UL) /*!< Single ended mode */

+#define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */

+

+/* Bits 1..0 : Speed and power mode */

+#define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */

+#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */

+#define COMP_MODE_SP_Low (0UL) /*!< Low power mode */

+#define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */

+#define COMP_MODE_SP_High (2UL) /*!< High speed mode */

+

+/* Register: COMP_HYST */

+/* Description: Comparator hysteresis enable */

+

+/* Bit 0 : Comparator hysteresis */

+#define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */

+#define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */

+#define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */

+#define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */

+

+/* Register: COMP_ISOURCE */

+/* Description: Current source select on analog input */

+

+/* Bits 1..0 : Comparator hysteresis */

+#define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */

+#define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */

+#define COMP_ISOURCE_ISOURCE_Off (0UL) /*!< Current source disabled */

+#define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL) /*!< Current source enabled (+/- 2.5 uA) */

+#define COMP_ISOURCE_ISOURCE_Ien5mA (2UL) /*!< Current source enabled (+/- 5 uA) */

+#define COMP_ISOURCE_ISOURCE_Ien10mA (3UL) /*!< Current source enabled (+/- 10 uA) */

+

+

+/* Peripheral: ECB */

+/* Description: AES ECB Mode Encryption */

+

+/* Register: ECB_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 1 : Write '1' to Enable interrupt for ERRORECB event */

+#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */

+#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */

+#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */

+#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */

+#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */

+

+/* Bit 0 : Write '1' to Enable interrupt for ENDECB event */

+#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */

+#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */

+#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */

+#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */

+#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */

+

+/* Register: ECB_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 1 : Write '1' to Disable interrupt for ERRORECB event */

+#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */

+#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */

+#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */

+#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */

+#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */

+

+/* Bit 0 : Write '1' to Disable interrupt for ENDECB event */

+#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */

+#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */

+#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */

+#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */

+#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */

+

+/* Register: ECB_ECBDATAPTR */

+/* Description: ECB block encrypt memory pointers */

+

+/* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */

+#define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */

+#define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */

+

+

+/* Peripheral: EGU */

+/* Description: Event Generator Unit 0 */

+

+/* Register: EGU_INTEN */

+/* Description: Enable or disable interrupt */

+

+/* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */

+#define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */

+#define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */

+#define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */

+#define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */

+

+/* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */

+#define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */

+#define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */

+#define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */

+#define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */

+

+/* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */

+#define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */

+#define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */

+#define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */

+#define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */

+

+/* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */

+#define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */

+#define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */

+#define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */

+#define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */

+

+/* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */

+#define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */

+#define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */

+#define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */

+#define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */

+

+/* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */

+#define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */

+#define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */

+#define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */

+#define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */

+

+/* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */

+#define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */

+#define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */

+#define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */

+#define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */

+

+/* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */

+#define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */

+#define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */

+#define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */

+#define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */

+

+/* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */

+#define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */

+#define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */

+#define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */

+#define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */

+

+/* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */

+#define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */

+#define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */

+#define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */

+#define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */

+

+/* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */

+#define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */

+#define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */

+#define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */

+#define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */

+

+/* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */

+#define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */

+#define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */

+#define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */

+#define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */

+

+/* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */

+#define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */

+#define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */

+#define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */

+#define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */

+

+/* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */

+#define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */

+#define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */

+#define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */

+#define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */

+

+/* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */

+#define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */

+#define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */

+#define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */

+#define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */

+

+/* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */

+#define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */

+#define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */

+#define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */

+#define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */

+

+/* Register: EGU_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 15 : Write '1' to Enable interrupt for TRIGGERED[15] event */

+#define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */

+#define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */

+#define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */

+

+/* Bit 14 : Write '1' to Enable interrupt for TRIGGERED[14] event */

+#define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */

+#define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */

+#define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */

+

+/* Bit 13 : Write '1' to Enable interrupt for TRIGGERED[13] event */

+#define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */

+#define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */

+#define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */

+

+/* Bit 12 : Write '1' to Enable interrupt for TRIGGERED[12] event */

+#define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */

+#define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */

+#define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */

+

+/* Bit 11 : Write '1' to Enable interrupt for TRIGGERED[11] event */

+#define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */

+#define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */

+#define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */

+

+/* Bit 10 : Write '1' to Enable interrupt for TRIGGERED[10] event */

+#define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */

+#define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */

+#define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */

+

+/* Bit 9 : Write '1' to Enable interrupt for TRIGGERED[9] event */

+#define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */

+#define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */

+#define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */

+

+/* Bit 8 : Write '1' to Enable interrupt for TRIGGERED[8] event */

+#define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */

+#define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */

+#define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */

+

+/* Bit 7 : Write '1' to Enable interrupt for TRIGGERED[7] event */

+#define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */

+#define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */

+#define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */

+

+/* Bit 6 : Write '1' to Enable interrupt for TRIGGERED[6] event */

+#define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */

+#define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */

+#define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */

+

+/* Bit 5 : Write '1' to Enable interrupt for TRIGGERED[5] event */

+#define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */

+#define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */

+#define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */

+

+/* Bit 4 : Write '1' to Enable interrupt for TRIGGERED[4] event */

+#define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */

+#define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */

+#define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */

+

+/* Bit 3 : Write '1' to Enable interrupt for TRIGGERED[3] event */

+#define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */

+#define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */

+#define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */

+

+/* Bit 2 : Write '1' to Enable interrupt for TRIGGERED[2] event */

+#define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */

+#define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */

+#define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */

+

+/* Bit 1 : Write '1' to Enable interrupt for TRIGGERED[1] event */

+#define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */

+#define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */

+#define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */

+

+/* Bit 0 : Write '1' to Enable interrupt for TRIGGERED[0] event */

+#define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */

+#define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */

+#define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */

+

+/* Register: EGU_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 15 : Write '1' to Disable interrupt for TRIGGERED[15] event */

+#define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */

+#define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */

+#define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */

+

+/* Bit 14 : Write '1' to Disable interrupt for TRIGGERED[14] event */

+#define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */

+#define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */

+#define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */

+

+/* Bit 13 : Write '1' to Disable interrupt for TRIGGERED[13] event */

+#define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */

+#define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */

+#define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */

+

+/* Bit 12 : Write '1' to Disable interrupt for TRIGGERED[12] event */

+#define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */

+#define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */

+#define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */

+

+/* Bit 11 : Write '1' to Disable interrupt for TRIGGERED[11] event */

+#define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */

+#define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */

+#define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */

+

+/* Bit 10 : Write '1' to Disable interrupt for TRIGGERED[10] event */

+#define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */

+#define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */

+#define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */

+

+/* Bit 9 : Write '1' to Disable interrupt for TRIGGERED[9] event */

+#define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */

+#define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */

+#define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */

+

+/* Bit 8 : Write '1' to Disable interrupt for TRIGGERED[8] event */

+#define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */

+#define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */

+#define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */

+

+/* Bit 7 : Write '1' to Disable interrupt for TRIGGERED[7] event */

+#define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */

+#define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */

+#define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */

+

+/* Bit 6 : Write '1' to Disable interrupt for TRIGGERED[6] event */

+#define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */

+#define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */

+#define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */

+

+/* Bit 5 : Write '1' to Disable interrupt for TRIGGERED[5] event */

+#define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */

+#define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */

+#define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */

+

+/* Bit 4 : Write '1' to Disable interrupt for TRIGGERED[4] event */

+#define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */

+#define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */

+#define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */

+

+/* Bit 3 : Write '1' to Disable interrupt for TRIGGERED[3] event */

+#define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */

+#define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */

+#define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */

+

+/* Bit 2 : Write '1' to Disable interrupt for TRIGGERED[2] event */

+#define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */

+#define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */

+#define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */

+

+/* Bit 1 : Write '1' to Disable interrupt for TRIGGERED[1] event */

+#define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */

+#define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */

+#define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */

+

+/* Bit 0 : Write '1' to Disable interrupt for TRIGGERED[0] event */

+#define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */

+#define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */

+#define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */

+#define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */

+#define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */

+

+

+/* Peripheral: FICR */

+/* Description: Factory Information Configuration Registers */

+

+/* Register: FICR_CODEPAGESIZE */

+/* Description: Code memory page size */

+

+/* Bits 31..0 : Code memory page size */

+#define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */

+#define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */

+

+/* Register: FICR_CODESIZE */

+/* Description: Code memory size */

+

+/* Bits 31..0 : Code memory size in number of pages */

+#define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */

+#define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */

+

+/* Register: FICR_DEVICEID */

+/* Description: Description collection[0]:  Device identifier */

+

+/* Bits 31..0 : 64 bit unique device identifier */

+#define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */

+#define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */

+

+/* Register: FICR_ER */

+/* Description: Description collection[0]:  Encryption Root, word 0 */

+

+/* Bits 31..0 : Encryption Root, word n */

+#define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */

+#define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */

+

+/* Register: FICR_IR */

+/* Description: Description collection[0]:  Identity Root, word 0 */

+

+/* Bits 31..0 : Identity Root, word n */

+#define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */

+#define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */

+

+/* Register: FICR_DEVICEADDRTYPE */

+/* Description: Device address type */

+

+/* Bit 0 : Device address type */

+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */

+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */

+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */

+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */

+

+/* Register: FICR_DEVICEADDR */

+/* Description: Description collection[0]:  Device address 0 */

+

+/* Bits 31..0 : 48 bit device address */

+#define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */

+#define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */

+

+/* Register: FICR_INFO_PART */

+/* Description: Part code */

+

+/* Bits 31..0 : Part code */

+#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */

+#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */

+#define FICR_INFO_PART_PART_N52832 (0x52832UL) /*!< nRF52832 */

+#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */

+

+/* Register: FICR_INFO_VARIANT */

+/* Description: Part Variant, Hardware version and Production configuration */

+

+/* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */

+#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */

+#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */

+#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */

+#define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */

+#define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */

+#define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */

+#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */

+

+/* Register: FICR_INFO_PACKAGE */

+/* Description: Package option */

+

+/* Bits 31..0 : Package option */

+#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */

+#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */

+#define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */

+#define FICR_INFO_PACKAGE_PACKAGE_CH (0x2001UL) /*!< CHxx - 7x8 WLCSP 56 balls */

+#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */

+

+/* Register: FICR_INFO_RAM */

+/* Description: RAM variant */

+

+/* Bits 31..0 : RAM variant */

+#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */

+#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */

+#define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */

+#define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */

+#define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */

+#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */

+

+/* Register: FICR_INFO_FLASH */

+/* Description: Flash variant */

+

+/* Bits 31..0 : Flash variant */

+#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */

+#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */

+#define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */

+#define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */

+#define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */

+#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */

+

+/* Register: FICR_TEMP_A0 */

+/* Description: Slope definition A0. */

+

+/* Bits 11..0 : A (slope definition) register. */

+#define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */

+#define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */

+

+/* Register: FICR_TEMP_A1 */

+/* Description: Slope definition A1. */

+

+/* Bits 11..0 : A (slope definition) register. */

+#define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */

+#define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */

+

+/* Register: FICR_TEMP_A2 */

+/* Description: Slope definition A2. */

+

+/* Bits 11..0 : A (slope definition) register. */

+#define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */

+#define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */

+

+/* Register: FICR_TEMP_A3 */

+/* Description: Slope definition A3. */

+

+/* Bits 11..0 : A (slope definition) register. */

+#define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */

+#define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */

+

+/* Register: FICR_TEMP_A4 */

+/* Description: Slope definition A4. */

+

+/* Bits 11..0 : A (slope definition) register. */

+#define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */

+#define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */

+

+/* Register: FICR_TEMP_A5 */

+/* Description: Slope definition A5. */

+

+/* Bits 11..0 : A (slope definition) register. */

+#define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */

+#define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */

+

+/* Register: FICR_TEMP_B0 */

+/* Description: y-intercept B0. */

+

+/* Bits 13..0 : B (y-intercept) */

+#define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */

+#define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */

+

+/* Register: FICR_TEMP_B1 */

+/* Description: y-intercept B1. */

+

+/* Bits 13..0 : B (y-intercept) */

+#define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */

+#define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */

+

+/* Register: FICR_TEMP_B2 */

+/* Description: y-intercept B2. */

+

+/* Bits 13..0 : B (y-intercept) */

+#define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */

+#define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */

+

+/* Register: FICR_TEMP_B3 */

+/* Description: y-intercept B3. */

+

+/* Bits 13..0 : B (y-intercept) */

+#define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */

+#define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */

+

+/* Register: FICR_TEMP_B4 */

+/* Description: y-intercept B4. */

+

+/* Bits 13..0 : B (y-intercept) */

+#define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */

+#define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */

+

+/* Register: FICR_TEMP_B5 */

+/* Description: y-intercept B5. */

+

+/* Bits 13..0 : B (y-intercept) */

+#define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */

+#define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */

+

+/* Register: FICR_TEMP_T0 */

+/* Description: Segment end T0. */

+

+/* Bits 7..0 : T (segment end)register. */

+#define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */

+#define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */

+

+/* Register: FICR_TEMP_T1 */

+/* Description: Segment end T1. */

+

+/* Bits 7..0 : T (segment end)register. */

+#define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */

+#define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */

+

+/* Register: FICR_TEMP_T2 */

+/* Description: Segment end T2. */

+

+/* Bits 7..0 : T (segment end)register. */

+#define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */

+#define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */

+

+/* Register: FICR_TEMP_T3 */

+/* Description: Segment end T3. */

+

+/* Bits 7..0 : T (segment end)register. */

+#define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */

+#define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */

+

+/* Register: FICR_TEMP_T4 */

+/* Description: Segment end T4. */

+

+/* Bits 7..0 : T (segment end)register. */

+#define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */

+#define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */

+

+/* Register: FICR_NFC_TAGHEADER0 */

+/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */

+

+/* Bits 31..24 : Unique identifier byte 3 */

+#define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */

+#define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */

+

+/* Bits 23..16 : Unique identifier byte 2 */

+#define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */

+#define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */

+

+/* Bits 15..8 : Unique identifier byte 1 */

+#define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */

+#define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */

+

+/* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */

+#define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */

+#define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */

+

+/* Register: FICR_NFC_TAGHEADER1 */

+/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */

+

+/* Bits 31..24 : Unique identifier byte 7 */

+#define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */

+#define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */

+

+/* Bits 23..16 : Unique identifier byte 6 */

+#define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */

+#define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */

+

+/* Bits 15..8 : Unique identifier byte 5 */

+#define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */

+#define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */

+

+/* Bits 7..0 : Unique identifier byte 4 */

+#define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */

+#define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */

+

+/* Register: FICR_NFC_TAGHEADER2 */

+/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */

+

+/* Bits 31..24 : Unique identifier byte 11 */

+#define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */

+#define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */

+

+/* Bits 23..16 : Unique identifier byte 10 */

+#define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */

+#define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */

+

+/* Bits 15..8 : Unique identifier byte 9 */

+#define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */

+#define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */

+

+/* Bits 7..0 : Unique identifier byte 8 */

+#define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */

+#define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */

+

+/* Register: FICR_NFC_TAGHEADER3 */

+/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */

+

+/* Bits 31..24 : Unique identifier byte 15 */

+#define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */

+#define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */

+

+/* Bits 23..16 : Unique identifier byte 14 */

+#define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */

+#define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */

+

+/* Bits 15..8 : Unique identifier byte 13 */

+#define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */

+#define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */

+

+/* Bits 7..0 : Unique identifier byte 12 */

+#define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */

+#define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */

+

+

+/* Peripheral: GPIOTE */

+/* Description: GPIO Tasks and Events */

+

+/* Register: GPIOTE_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 31 : Write '1' to Enable interrupt for PORT event */

+#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */

+#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */

+#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */

+#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */

+#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */

+

+/* Bit 7 : Write '1' to Enable interrupt for IN[7] event */

+#define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */

+#define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */

+#define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */

+#define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */

+#define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */

+

+/* Bit 6 : Write '1' to Enable interrupt for IN[6] event */

+#define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */

+#define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */

+#define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */

+#define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */

+#define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */

+

+/* Bit 5 : Write '1' to Enable interrupt for IN[5] event */

+#define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */

+#define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */

+#define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */

+#define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */

+#define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */

+

+/* Bit 4 : Write '1' to Enable interrupt for IN[4] event */

+#define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */

+#define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */

+#define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */

+#define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */

+#define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */

+

+/* Bit 3 : Write '1' to Enable interrupt for IN[3] event */

+#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */

+#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */

+#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */

+#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */

+#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */

+

+/* Bit 2 : Write '1' to Enable interrupt for IN[2] event */

+#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */

+#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */

+#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */

+#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */

+#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */

+

+/* Bit 1 : Write '1' to Enable interrupt for IN[1] event */

+#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */

+#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */

+#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */

+#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */

+#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */

+

+/* Bit 0 : Write '1' to Enable interrupt for IN[0] event */

+#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */

+#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */

+#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */

+#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */

+#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */

+

+/* Register: GPIOTE_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 31 : Write '1' to Disable interrupt for PORT event */

+#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */

+#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */

+#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */

+#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */

+#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */

+

+/* Bit 7 : Write '1' to Disable interrupt for IN[7] event */

+#define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */

+#define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */

+#define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */

+#define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */

+#define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */

+

+/* Bit 6 : Write '1' to Disable interrupt for IN[6] event */

+#define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */

+#define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */

+#define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */

+#define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */

+#define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */

+

+/* Bit 5 : Write '1' to Disable interrupt for IN[5] event */

+#define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */

+#define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */

+#define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */

+#define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */

+#define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */

+

+/* Bit 4 : Write '1' to Disable interrupt for IN[4] event */

+#define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */

+#define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */

+#define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */

+#define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */

+#define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */

+

+/* Bit 3 : Write '1' to Disable interrupt for IN[3] event */

+#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */

+#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */

+#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */

+#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */

+#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */

+

+/* Bit 2 : Write '1' to Disable interrupt for IN[2] event */

+#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */

+#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */

+#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */

+#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */

+#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */

+

+/* Bit 1 : Write '1' to Disable interrupt for IN[1] event */

+#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */

+#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */

+#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */

+#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */

+#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */

+

+/* Bit 0 : Write '1' to Disable interrupt for IN[0] event */

+#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */

+#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */

+#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */

+#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */

+#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */

+

+/* Register: GPIOTE_CONFIG */

+/* Description: Description collection[0]:  Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */

+

+/* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */

+#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */

+#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */

+#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */

+#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */

+

+/* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */

+#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */

+#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */

+#define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */

+#define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */

+#define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */

+#define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */

+

+/* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */

+#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */

+#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */

+

+/* Bits 1..0 : Mode */

+#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */

+#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */

+#define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */

+#define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */

+#define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */

+

+

+/* Peripheral: I2S */

+/* Description: Inter-IC Sound */

+

+/* Register: I2S_INTEN */

+/* Description: Enable or disable interrupt */

+

+/* Bit 5 : Enable or disable interrupt for TXPTRUPD event */

+#define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */

+#define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */

+#define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */

+#define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */

+

+/* Bit 2 : Enable or disable interrupt for STOPPED event */

+#define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */

+#define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */

+#define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */

+#define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */

+

+/* Bit 1 : Enable or disable interrupt for RXPTRUPD event */

+#define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */

+#define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */

+#define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */

+#define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */

+

+/* Register: I2S_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 5 : Write '1' to Enable interrupt for TXPTRUPD event */

+#define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */

+#define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */

+#define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */

+#define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */

+#define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */

+

+/* Bit 2 : Write '1' to Enable interrupt for STOPPED event */

+#define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */

+#define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */

+#define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */

+#define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */

+#define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */

+

+/* Bit 1 : Write '1' to Enable interrupt for RXPTRUPD event */

+#define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */

+#define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */

+#define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */

+#define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */

+#define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */

+

+/* Register: I2S_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 5 : Write '1' to Disable interrupt for TXPTRUPD event */

+#define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */

+#define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */

+#define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */

+#define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */

+#define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */

+

+/* Bit 2 : Write '1' to Disable interrupt for STOPPED event */

+#define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */

+#define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */

+#define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */

+#define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */

+#define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */

+

+/* Bit 1 : Write '1' to Disable interrupt for RXPTRUPD event */

+#define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */

+#define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */

+#define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */

+#define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */

+#define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */

+

+/* Register: I2S_ENABLE */

+/* Description: Enable I2S module. */

+

+/* Bit 0 : Enable I2S module. */

+#define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */

+#define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */

+#define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */

+#define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */

+

+/* Register: I2S_CONFIG_MODE */

+/* Description: I2S mode. */

+

+/* Bit 0 : I2S mode. */

+#define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */

+#define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */

+#define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */

+#define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */

+

+/* Register: I2S_CONFIG_RXEN */

+/* Description: Reception (RX) enable. */

+

+/* Bit 0 : Reception (RX) enable. */

+#define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */

+#define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */

+#define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */

+#define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */

+

+/* Register: I2S_CONFIG_TXEN */

+/* Description: Transmission (TX) enable. */

+

+/* Bit 0 : Transmission (TX) enable. */

+#define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */

+#define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */

+#define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */

+#define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */

+

+/* Register: I2S_CONFIG_MCKEN */

+/* Description: Master clock generator enable. */

+

+/* Bit 0 : Master clock generator enable. */

+#define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */

+#define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */

+#define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */

+#define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */

+

+/* Register: I2S_CONFIG_MCKFREQ */

+/* Description: Master clock generator frequency. */

+

+/* Bits 31..0 : Master clock generator frequency. */

+#define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */

+#define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */

+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */

+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */

+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */

+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */

+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */

+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */

+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */

+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */

+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */

+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */

+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */

+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */

+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */

+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz */

+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz */

+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz */

+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz */

+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */

+

+/* Register: I2S_CONFIG_RATIO */

+/* Description: MCK / LRCK ratio. */

+

+/* Bits 3..0 : MCK / LRCK ratio. */

+#define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */

+#define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */

+#define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */

+#define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */

+#define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */

+#define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */

+#define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */

+#define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */

+#define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */

+#define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */

+#define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */

+

+/* Register: I2S_CONFIG_SWIDTH */

+/* Description: Sample width. */

+

+/* Bits 1..0 : Sample width. */

+#define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */

+#define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */

+#define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */

+#define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */

+#define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */

+

+/* Register: I2S_CONFIG_ALIGN */

+/* Description: Alignment of sample within a frame. */

+

+/* Bit 0 : Alignment of sample within a frame. */

+#define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */

+#define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */

+#define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */

+#define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */

+

+/* Register: I2S_CONFIG_FORMAT */

+/* Description: Frame format. */

+

+/* Bit 0 : Frame format. */

+#define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */

+#define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */

+#define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */

+#define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */

+

+/* Register: I2S_CONFIG_CHANNELS */

+/* Description: Enable channels. */

+

+/* Bits 1..0 : Enable channels. */

+#define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */

+#define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */

+#define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */

+#define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */

+#define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */

+

+/* Register: I2S_RXD_PTR */

+/* Description: Receive buffer RAM start address. */

+

+/* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */

+#define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */

+#define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

+

+/* Register: I2S_TXD_PTR */

+/* Description: Transmit buffer RAM start address. */

+

+/* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */

+#define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */

+#define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

+

+/* Register: I2S_RXTXD_MAXCNT */

+/* Description: Size of RXD and TXD buffers. */

+

+/* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */

+#define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */

+#define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

+

+/* Register: I2S_PSEL_MCK */

+/* Description: Pin select for MCK signal. */

+

+/* Bit 31 : Connection */

+#define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */

+#define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */

+#define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */

+#define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */

+

+/* Bits 4..0 : Pin number */

+#define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */

+#define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */

+

+/* Register: I2S_PSEL_SCK */

+/* Description: Pin select for SCK signal. */

+

+/* Bit 31 : Connection */

+#define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */

+#define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */

+#define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */

+#define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */

+

+/* Bits 4..0 : Pin number */

+#define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */

+#define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */

+

+/* Register: I2S_PSEL_LRCK */

+/* Description: Pin select for LRCK signal. */

+

+/* Bit 31 : Connection */

+#define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */

+#define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */

+#define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */

+#define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */

+

+/* Bits 4..0 : Pin number */

+#define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */

+#define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */

+

+/* Register: I2S_PSEL_SDIN */

+/* Description: Pin select for SDIN signal. */

+

+/* Bit 31 : Connection */

+#define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */

+#define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */

+#define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */

+#define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */

+

+/* Bits 4..0 : Pin number */

+#define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */

+#define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */

+

+/* Register: I2S_PSEL_SDOUT */

+/* Description: Pin select for SDOUT signal. */

+

+/* Bit 31 : Connection */

+#define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */

+#define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */

+#define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */

+#define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */

+

+/* Bits 4..0 : Pin number */

+#define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */

+#define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */

+

+

+/* Peripheral: LPCOMP */

+/* Description: Low Power Comparator */

+

+/* Register: LPCOMP_SHORTS */

+/* Description: Shortcut register */

+

+/* Bit 4 : Shortcut between CROSS event and STOP task */

+#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */

+#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */

+#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */

+#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 3 : Shortcut between UP event and STOP task */

+#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */

+#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */

+#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */

+#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 2 : Shortcut between DOWN event and STOP task */

+#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */

+#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */

+#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */

+#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 1 : Shortcut between READY event and STOP task */

+#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */

+#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */

+#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */

+#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 0 : Shortcut between READY event and SAMPLE task */

+#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */

+#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */

+#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */

+#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */

+

+/* Register: LPCOMP_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 3 : Write '1' to Enable interrupt for CROSS event */

+#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */

+#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */

+#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */

+#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */

+#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */

+

+/* Bit 2 : Write '1' to Enable interrupt for UP event */

+#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */

+#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */

+#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */

+#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */

+#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */

+

+/* Bit 1 : Write '1' to Enable interrupt for DOWN event */

+#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */

+#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */

+#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */

+#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */

+#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */

+

+/* Bit 0 : Write '1' to Enable interrupt for READY event */

+#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */

+#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */

+#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */

+#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */

+#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */

+

+/* Register: LPCOMP_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 3 : Write '1' to Disable interrupt for CROSS event */

+#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */

+#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */

+#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */

+#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */

+#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */

+

+/* Bit 2 : Write '1' to Disable interrupt for UP event */

+#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */

+#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */

+#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */

+#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */

+#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */

+

+/* Bit 1 : Write '1' to Disable interrupt for DOWN event */

+#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */

+#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */

+#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */

+#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */

+#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */

+

+/* Bit 0 : Write '1' to Disable interrupt for READY event */

+#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */

+#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */

+#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */

+#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */

+#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */

+

+/* Register: LPCOMP_RESULT */

+/* Description: Compare result */

+

+/* Bit 0 : Result of last compare. Decision point SAMPLE task. */

+#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */

+#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */

+#define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is below the reference threshold (VIN+ &lt; VIN-). */

+#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ &gt; VIN-). */

+

+/* Register: LPCOMP_ENABLE */

+/* Description: Enable LPCOMP */

+

+/* Bits 1..0 : Enable or disable LPCOMP */

+#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */

+#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */

+#define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */

+#define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */

+

+/* Register: LPCOMP_PSEL */

+/* Description: Input pin select */

+

+/* Bits 2..0 : Analog pin select */

+#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */

+#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */

+#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */

+#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */

+#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */

+#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */

+#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */

+#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */

+#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */

+#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */

+

+/* Register: LPCOMP_REFSEL */

+/* Description: Reference select */

+

+/* Bits 3..0 : Reference select */

+#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */

+#define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */

+#define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */

+#define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */

+#define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */

+#define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */

+#define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */

+#define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */

+#define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */

+#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */

+#define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */

+#define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */

+#define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */

+#define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */

+#define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */

+#define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */

+#define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */

+#define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */

+

+/* Register: LPCOMP_EXTREFSEL */

+/* Description: External reference select */

+

+/* Bit 0 : External analog reference select */

+#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */

+#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */

+#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */

+#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */

+

+/* Register: LPCOMP_ANADETECT */

+/* Description: Analog detect configuration */

+

+/* Bits 1..0 : Analog detect configuration */

+#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */

+#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */

+#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */

+#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */

+#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */

+

+/* Register: LPCOMP_HYST */

+/* Description: Comparator hysteresis enable */

+

+/* Bit 0 : Comparator hysteresis enable */

+#define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */

+#define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */

+#define LPCOMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */

+#define LPCOMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis disabled (typ. 50 mV) */

+

+

+/* Peripheral: MWU */

+/* Description: Memory Watch Unit */

+

+/* Register: MWU_INTEN */

+/* Description: Enable or disable interrupt */

+

+/* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */

+#define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */

+#define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */

+#define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */

+#define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */

+

+/* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */

+#define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */

+#define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */

+#define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */

+#define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */

+

+/* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */

+#define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */

+#define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */

+#define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */

+#define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */

+

+/* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */

+#define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */

+#define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */

+#define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */

+#define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */

+

+/* Bit 7 : Enable or disable interrupt for REGION[3].RA event */

+#define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */

+#define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */

+#define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */

+#define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */

+

+/* Bit 6 : Enable or disable interrupt for REGION[3].WA event */

+#define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */

+#define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */

+#define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */

+#define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */

+

+/* Bit 5 : Enable or disable interrupt for REGION[2].RA event */

+#define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */

+#define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */

+#define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */

+#define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */

+

+/* Bit 4 : Enable or disable interrupt for REGION[2].WA event */

+#define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */

+#define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */

+#define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */

+#define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */

+

+/* Bit 3 : Enable or disable interrupt for REGION[1].RA event */

+#define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */

+#define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */

+#define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */

+#define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */

+

+/* Bit 2 : Enable or disable interrupt for REGION[1].WA event */

+#define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */

+#define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */

+#define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */

+#define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */

+

+/* Bit 1 : Enable or disable interrupt for REGION[0].RA event */

+#define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */

+#define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */

+#define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */

+#define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */

+

+/* Bit 0 : Enable or disable interrupt for REGION[0].WA event */

+#define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */

+#define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */

+#define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */

+#define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */

+

+/* Register: MWU_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 27 : Write '1' to Enable interrupt for PREGION[1].RA event */

+#define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */

+#define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */

+#define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */

+

+/* Bit 26 : Write '1' to Enable interrupt for PREGION[1].WA event */

+#define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */

+#define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */

+#define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */

+

+/* Bit 25 : Write '1' to Enable interrupt for PREGION[0].RA event */

+#define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */

+#define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */

+#define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */

+

+/* Bit 24 : Write '1' to Enable interrupt for PREGION[0].WA event */

+#define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */

+#define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */

+#define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */

+

+/* Bit 7 : Write '1' to Enable interrupt for REGION[3].RA event */

+#define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */

+#define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */

+#define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */

+

+/* Bit 6 : Write '1' to Enable interrupt for REGION[3].WA event */

+#define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */

+#define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */

+#define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */

+

+/* Bit 5 : Write '1' to Enable interrupt for REGION[2].RA event */

+#define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */

+#define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */

+#define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */

+

+/* Bit 4 : Write '1' to Enable interrupt for REGION[2].WA event */

+#define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */

+#define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */

+#define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */

+

+/* Bit 3 : Write '1' to Enable interrupt for REGION[1].RA event */

+#define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */

+#define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */

+#define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */

+

+/* Bit 2 : Write '1' to Enable interrupt for REGION[1].WA event */

+#define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */

+#define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */

+#define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */

+

+/* Bit 1 : Write '1' to Enable interrupt for REGION[0].RA event */

+#define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */

+#define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */

+#define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */

+

+/* Bit 0 : Write '1' to Enable interrupt for REGION[0].WA event */

+#define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */

+#define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */

+#define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */

+

+/* Register: MWU_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 27 : Write '1' to Disable interrupt for PREGION[1].RA event */

+#define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */

+#define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */

+#define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */

+

+/* Bit 26 : Write '1' to Disable interrupt for PREGION[1].WA event */

+#define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */

+#define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */

+#define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */

+

+/* Bit 25 : Write '1' to Disable interrupt for PREGION[0].RA event */

+#define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */

+#define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */

+#define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */

+

+/* Bit 24 : Write '1' to Disable interrupt for PREGION[0].WA event */

+#define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */

+#define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */

+#define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */

+

+/* Bit 7 : Write '1' to Disable interrupt for REGION[3].RA event */

+#define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */

+#define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */

+#define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */

+

+/* Bit 6 : Write '1' to Disable interrupt for REGION[3].WA event */

+#define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */

+#define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */

+#define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */

+

+/* Bit 5 : Write '1' to Disable interrupt for REGION[2].RA event */

+#define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */

+#define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */

+#define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */

+

+/* Bit 4 : Write '1' to Disable interrupt for REGION[2].WA event */

+#define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */

+#define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */

+#define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */

+

+/* Bit 3 : Write '1' to Disable interrupt for REGION[1].RA event */

+#define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */

+#define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */

+#define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */

+

+/* Bit 2 : Write '1' to Disable interrupt for REGION[1].WA event */

+#define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */

+#define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */

+#define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */

+

+/* Bit 1 : Write '1' to Disable interrupt for REGION[0].RA event */

+#define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */

+#define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */

+#define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */

+

+/* Bit 0 : Write '1' to Disable interrupt for REGION[0].WA event */

+#define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */

+#define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */

+#define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */

+

+/* Register: MWU_NMIEN */

+/* Description: Enable or disable non-maskable interrupt */

+

+/* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */

+#define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */

+#define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */

+#define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */

+#define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */

+

+/* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */

+#define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */

+#define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */

+#define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */

+#define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */

+

+/* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */

+#define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */

+#define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */

+#define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */

+#define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */

+

+/* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */

+#define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */

+#define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */

+#define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */

+#define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */

+

+/* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */

+#define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */

+#define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */

+#define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */

+#define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */

+

+/* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */

+#define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */

+#define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */

+#define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */

+#define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */

+

+/* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */

+#define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */

+#define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */

+#define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */

+#define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */

+

+/* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */

+#define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */

+#define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */

+#define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */

+#define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */

+

+/* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */

+#define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */

+#define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */

+#define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */

+#define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */

+

+/* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */

+#define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */

+#define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */

+#define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */

+#define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */

+

+/* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */

+#define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */

+#define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */

+#define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */

+#define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */

+

+/* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */

+#define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */

+#define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */

+#define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */

+#define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */

+

+/* Register: MWU_NMIENSET */

+/* Description: Enable non-maskable interrupt */

+

+/* Bit 27 : Write '1' to Enable non-maskable interrupt for PREGION[1].RA event */

+#define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */

+#define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */

+#define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */

+

+/* Bit 26 : Write '1' to Enable non-maskable interrupt for PREGION[1].WA event */

+#define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */

+#define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */

+#define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */

+

+/* Bit 25 : Write '1' to Enable non-maskable interrupt for PREGION[0].RA event */

+#define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */

+#define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */

+#define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */

+

+/* Bit 24 : Write '1' to Enable non-maskable interrupt for PREGION[0].WA event */

+#define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */

+#define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */

+#define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */

+

+/* Bit 7 : Write '1' to Enable non-maskable interrupt for REGION[3].RA event */

+#define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */

+#define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */

+#define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */

+

+/* Bit 6 : Write '1' to Enable non-maskable interrupt for REGION[3].WA event */

+#define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */

+#define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */

+#define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */

+

+/* Bit 5 : Write '1' to Enable non-maskable interrupt for REGION[2].RA event */

+#define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */

+#define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */

+#define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */

+

+/* Bit 4 : Write '1' to Enable non-maskable interrupt for REGION[2].WA event */

+#define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */

+#define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */

+#define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */

+

+/* Bit 3 : Write '1' to Enable non-maskable interrupt for REGION[1].RA event */

+#define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */

+#define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */

+#define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */

+

+/* Bit 2 : Write '1' to Enable non-maskable interrupt for REGION[1].WA event */

+#define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */

+#define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */

+#define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */

+

+/* Bit 1 : Write '1' to Enable non-maskable interrupt for REGION[0].RA event */

+#define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */

+#define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */

+#define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */

+

+/* Bit 0 : Write '1' to Enable non-maskable interrupt for REGION[0].WA event */

+#define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */

+#define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */

+#define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */

+

+/* Register: MWU_NMIENCLR */

+/* Description: Disable non-maskable interrupt */

+

+/* Bit 27 : Write '1' to Disable non-maskable interrupt for PREGION[1].RA event */

+#define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */

+#define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */

+#define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */

+

+/* Bit 26 : Write '1' to Disable non-maskable interrupt for PREGION[1].WA event */

+#define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */

+#define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */

+#define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */

+

+/* Bit 25 : Write '1' to Disable non-maskable interrupt for PREGION[0].RA event */

+#define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */

+#define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */

+#define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */

+

+/* Bit 24 : Write '1' to Disable non-maskable interrupt for PREGION[0].WA event */

+#define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */

+#define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */

+#define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */

+

+/* Bit 7 : Write '1' to Disable non-maskable interrupt for REGION[3].RA event */

+#define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */

+#define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */

+#define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */

+

+/* Bit 6 : Write '1' to Disable non-maskable interrupt for REGION[3].WA event */

+#define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */

+#define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */

+#define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */

+

+/* Bit 5 : Write '1' to Disable non-maskable interrupt for REGION[2].RA event */

+#define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */

+#define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */

+#define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */

+

+/* Bit 4 : Write '1' to Disable non-maskable interrupt for REGION[2].WA event */

+#define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */

+#define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */

+#define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */

+

+/* Bit 3 : Write '1' to Disable non-maskable interrupt for REGION[1].RA event */

+#define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */

+#define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */

+#define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */

+

+/* Bit 2 : Write '1' to Disable non-maskable interrupt for REGION[1].WA event */

+#define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */

+#define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */

+#define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */

+

+/* Bit 1 : Write '1' to Disable non-maskable interrupt for REGION[0].RA event */

+#define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */

+#define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */

+#define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */

+

+/* Bit 0 : Write '1' to Disable non-maskable interrupt for REGION[0].WA event */

+#define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */

+#define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */

+#define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */

+#define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */

+#define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */

+

+/* Register: MWU_PERREGION_SUBSTATWA */

+/* Description: Description cluster[0]:  Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching */

+

+/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */

+#define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */

+#define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */

+#define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */

+#define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */

+#define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */

+#define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */

+#define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */

+#define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */

+#define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */

+#define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */

+#define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */

+#define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */

+#define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */

+#define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */

+#define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */

+#define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */

+#define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */

+#define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */

+#define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */

+#define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */

+#define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */

+#define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */

+#define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */

+#define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */

+#define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */

+#define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */

+#define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */

+#define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */

+#define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */

+#define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */

+#define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */

+#define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */

+#define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */

+#define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */

+#define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */

+#define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */

+#define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */

+#define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */

+#define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */

+#define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */

+#define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */

+#define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */

+#define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */

+#define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */

+#define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */

+#define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */

+#define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */

+#define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */

+#define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */

+#define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */

+#define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */

+#define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */

+#define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */

+#define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */

+#define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */

+#define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */

+#define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */

+#define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */

+#define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */

+#define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */

+#define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */

+#define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */

+#define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */

+#define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */

+

+/* Register: MWU_PERREGION_SUBSTATRA */

+/* Description: Description cluster[0]:  Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching */

+

+/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */

+#define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */

+#define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */

+#define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */

+#define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */

+#define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */

+#define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */

+#define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */

+#define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */

+#define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */

+#define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */

+#define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */

+#define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */

+#define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */

+#define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */

+#define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */

+#define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */

+#define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */

+#define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */

+#define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */

+#define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */

+#define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */

+#define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */

+#define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */

+#define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */

+#define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */

+#define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */

+#define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */

+#define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */

+#define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */

+#define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */

+#define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */

+#define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */

+#define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */

+#define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */

+#define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */

+#define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */

+#define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */

+#define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */

+#define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */

+#define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */

+#define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */

+#define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */

+#define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */

+#define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */

+#define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */

+#define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */

+#define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */

+#define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */

+#define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */

+#define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */

+#define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */

+#define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */

+#define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */

+#define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */

+#define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */

+#define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */

+#define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */

+#define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */

+#define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */

+#define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */

+#define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */

+#define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */

+#define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */

+#define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */

+#define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */

+#define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */

+

+/* Register: MWU_REGIONEN */

+/* Description: Enable/disable regions watch */

+

+/* Bit 27 : Enable/disable read access watch in PREGION[1] */

+#define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */

+#define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */

+#define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */

+#define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */

+

+/* Bit 26 : Enable/disable write access watch in PREGION[1] */

+#define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */

+#define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */

+#define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */

+#define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */

+

+/* Bit 25 : Enable/disable read access watch in PREGION[0] */

+#define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */

+#define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */

+#define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */

+#define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */

+

+/* Bit 24 : Enable/disable write access watch in PREGION[0] */

+#define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */

+#define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */

+#define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */

+#define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */

+

+/* Bit 7 : Enable/disable read access watch in region[3] */

+#define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */

+#define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */

+#define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */

+#define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */

+

+/* Bit 6 : Enable/disable write access watch in region[3] */

+#define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */

+#define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */

+#define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */

+#define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */

+

+/* Bit 5 : Enable/disable read access watch in region[2] */

+#define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */

+#define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */

+#define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */

+#define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */

+

+/* Bit 4 : Enable/disable write access watch in region[2] */

+#define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */

+#define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */

+#define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */

+#define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */

+

+/* Bit 3 : Enable/disable read access watch in region[1] */

+#define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */

+#define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */

+#define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */

+#define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */

+

+/* Bit 2 : Enable/disable write access watch in region[1] */

+#define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */

+#define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */

+#define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */

+#define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */

+

+/* Bit 1 : Enable/disable read access watch in region[0] */

+#define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */

+#define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */

+#define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */

+#define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */

+

+/* Bit 0 : Enable/disable write access watch in region[0] */

+#define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */

+#define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */

+#define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */

+#define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */

+

+/* Register: MWU_REGIONENSET */

+/* Description: Enable regions watch */

+

+/* Bit 27 : Enable read access watch in PREGION[1] */

+#define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */

+#define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */

+#define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */

+#define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */

+#define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */

+

+/* Bit 26 : Enable write access watch in PREGION[1] */

+#define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */

+#define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */

+#define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */

+#define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */

+#define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */

+

+/* Bit 25 : Enable read access watch in PREGION[0] */

+#define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */

+#define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */

+#define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */

+#define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */

+#define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */

+

+/* Bit 24 : Enable write access watch in PREGION[0] */

+#define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */

+#define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */

+#define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */

+#define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */

+#define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */

+

+/* Bit 7 : Enable read access watch in region[3] */

+#define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */

+#define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */

+#define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */

+#define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */

+#define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */

+

+/* Bit 6 : Enable write access watch in region[3] */

+#define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */

+#define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */

+#define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */

+#define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */

+#define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */

+

+/* Bit 5 : Enable read access watch in region[2] */

+#define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */

+#define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */

+#define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */

+#define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */

+#define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */

+

+/* Bit 4 : Enable write access watch in region[2] */

+#define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */

+#define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */

+#define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */

+#define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */

+#define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */

+

+/* Bit 3 : Enable read access watch in region[1] */

+#define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */

+#define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */

+#define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */

+#define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */

+#define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */

+

+/* Bit 2 : Enable write access watch in region[1] */

+#define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */

+#define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */

+#define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */

+#define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */

+#define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */

+

+/* Bit 1 : Enable read access watch in region[0] */

+#define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */

+#define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */

+#define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */

+#define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */

+#define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */

+

+/* Bit 0 : Enable write access watch in region[0] */

+#define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */

+#define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */

+#define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */

+#define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */

+#define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */

+

+/* Register: MWU_REGIONENCLR */

+/* Description: Disable regions watch */

+

+/* Bit 27 : Disable read access watch in PREGION[1] */

+#define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */

+#define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */

+#define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */

+#define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */

+#define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */

+

+/* Bit 26 : Disable write access watch in PREGION[1] */

+#define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */

+#define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */

+#define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */

+#define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */

+#define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */

+

+/* Bit 25 : Disable read access watch in PREGION[0] */

+#define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */

+#define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */

+#define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */

+#define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */

+#define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */

+

+/* Bit 24 : Disable write access watch in PREGION[0] */

+#define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */

+#define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */

+#define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */

+#define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */

+#define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */

+

+/* Bit 7 : Disable read access watch in region[3] */

+#define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */

+#define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */

+#define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */

+#define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */

+#define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */

+

+/* Bit 6 : Disable write access watch in region[3] */

+#define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */

+#define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */

+#define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */

+#define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */

+#define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */

+

+/* Bit 5 : Disable read access watch in region[2] */

+#define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */

+#define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */

+#define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */

+#define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */

+#define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */

+

+/* Bit 4 : Disable write access watch in region[2] */

+#define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */

+#define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */

+#define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */

+#define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */

+#define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */

+

+/* Bit 3 : Disable read access watch in region[1] */

+#define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */

+#define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */

+#define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */

+#define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */

+#define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */

+

+/* Bit 2 : Disable write access watch in region[1] */

+#define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */

+#define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */

+#define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */

+#define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */

+#define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */

+

+/* Bit 1 : Disable read access watch in region[0] */

+#define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */

+#define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */

+#define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */

+#define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */

+#define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */

+

+/* Bit 0 : Disable write access watch in region[0] */

+#define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */

+#define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */

+#define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */

+#define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */

+#define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */

+

+/* Register: MWU_REGION_START */

+/* Description: Description cluster[0]:  Start address for region 0 */

+

+/* Bits 31..0 : Start address for region */

+#define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */

+#define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */

+

+/* Register: MWU_REGION_END */

+/* Description: Description cluster[0]:  End address of region 0 */

+

+/* Bits 31..0 : End address of region. */

+#define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */

+#define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */

+

+/* Register: MWU_PREGION_START */

+/* Description: Description cluster[0]:  Reserved for future use */

+

+/* Bits 31..0 : Reserved for future use */

+#define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */

+#define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */

+

+/* Register: MWU_PREGION_END */

+/* Description: Description cluster[0]:  Reserved for future use */

+

+/* Bits 31..0 : Reserved for future use */

+#define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */

+#define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */

+

+/* Register: MWU_PREGION_SUBS */

+/* Description: Description cluster[0]:  Subregions of region 0 */

+

+/* Bit 31 : Include or exclude subregion 31 in region */

+#define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */

+#define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */

+#define MWU_PREGION_SUBS_SR31_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */

+

+/* Bit 30 : Include or exclude subregion 30 in region */

+#define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */

+#define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */

+#define MWU_PREGION_SUBS_SR30_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */

+

+/* Bit 29 : Include or exclude subregion 29 in region */

+#define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */

+#define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */

+#define MWU_PREGION_SUBS_SR29_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */

+

+/* Bit 28 : Include or exclude subregion 28 in region */

+#define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */

+#define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */

+#define MWU_PREGION_SUBS_SR28_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */

+

+/* Bit 27 : Include or exclude subregion 27 in region */

+#define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */

+#define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */

+#define MWU_PREGION_SUBS_SR27_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */

+

+/* Bit 26 : Include or exclude subregion 26 in region */

+#define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */

+#define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */

+#define MWU_PREGION_SUBS_SR26_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */

+

+/* Bit 25 : Include or exclude subregion 25 in region */

+#define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */

+#define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */

+#define MWU_PREGION_SUBS_SR25_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */

+

+/* Bit 24 : Include or exclude subregion 24 in region */

+#define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */

+#define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */

+#define MWU_PREGION_SUBS_SR24_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */

+

+/* Bit 23 : Include or exclude subregion 23 in region */

+#define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */

+#define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */

+#define MWU_PREGION_SUBS_SR23_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */

+

+/* Bit 22 : Include or exclude subregion 22 in region */

+#define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */

+#define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */

+#define MWU_PREGION_SUBS_SR22_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */

+

+/* Bit 21 : Include or exclude subregion 21 in region */

+#define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */

+#define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */

+#define MWU_PREGION_SUBS_SR21_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */

+

+/* Bit 20 : Include or exclude subregion 20 in region */

+#define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */

+#define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */

+#define MWU_PREGION_SUBS_SR20_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */

+

+/* Bit 19 : Include or exclude subregion 19 in region */

+#define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */

+#define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */

+#define MWU_PREGION_SUBS_SR19_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */

+

+/* Bit 18 : Include or exclude subregion 18 in region */

+#define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */

+#define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */

+#define MWU_PREGION_SUBS_SR18_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */

+

+/* Bit 17 : Include or exclude subregion 17 in region */

+#define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */

+#define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */

+#define MWU_PREGION_SUBS_SR17_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */

+

+/* Bit 16 : Include or exclude subregion 16 in region */

+#define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */

+#define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */

+#define MWU_PREGION_SUBS_SR16_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */

+

+/* Bit 15 : Include or exclude subregion 15 in region */

+#define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */

+#define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */

+#define MWU_PREGION_SUBS_SR15_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */

+

+/* Bit 14 : Include or exclude subregion 14 in region */

+#define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */

+#define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */

+#define MWU_PREGION_SUBS_SR14_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */

+

+/* Bit 13 : Include or exclude subregion 13 in region */

+#define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */

+#define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */

+#define MWU_PREGION_SUBS_SR13_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */

+

+/* Bit 12 : Include or exclude subregion 12 in region */

+#define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */

+#define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */

+#define MWU_PREGION_SUBS_SR12_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */

+

+/* Bit 11 : Include or exclude subregion 11 in region */

+#define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */

+#define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */

+#define MWU_PREGION_SUBS_SR11_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */

+

+/* Bit 10 : Include or exclude subregion 10 in region */

+#define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */

+#define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */

+#define MWU_PREGION_SUBS_SR10_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */

+

+/* Bit 9 : Include or exclude subregion 9 in region */

+#define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */

+#define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */

+#define MWU_PREGION_SUBS_SR9_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */

+

+/* Bit 8 : Include or exclude subregion 8 in region */

+#define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */

+#define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */

+#define MWU_PREGION_SUBS_SR8_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */

+

+/* Bit 7 : Include or exclude subregion 7 in region */

+#define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */

+#define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */

+#define MWU_PREGION_SUBS_SR7_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */

+

+/* Bit 6 : Include or exclude subregion 6 in region */

+#define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */

+#define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */

+#define MWU_PREGION_SUBS_SR6_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */

+

+/* Bit 5 : Include or exclude subregion 5 in region */

+#define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */

+#define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */

+#define MWU_PREGION_SUBS_SR5_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */

+

+/* Bit 4 : Include or exclude subregion 4 in region */

+#define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */

+#define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */

+#define MWU_PREGION_SUBS_SR4_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */

+

+/* Bit 3 : Include or exclude subregion 3 in region */

+#define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */

+#define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */

+#define MWU_PREGION_SUBS_SR3_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */

+

+/* Bit 2 : Include or exclude subregion 2 in region */

+#define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */

+#define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */

+#define MWU_PREGION_SUBS_SR2_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */

+

+/* Bit 1 : Include or exclude subregion 1 in region */

+#define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */

+#define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */

+#define MWU_PREGION_SUBS_SR1_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */

+

+/* Bit 0 : Include or exclude subregion 0 in region */

+#define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */

+#define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */

+#define MWU_PREGION_SUBS_SR0_Exclude (0UL) /*!< Exclude */

+#define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */

+

+

+/* Peripheral: NFCT */

+/* Description: NFC-A compatible radio */

+

+/* Register: NFCT_SHORTS */

+/* Description: Shortcut register */

+

+/* Bit 1 : Shortcut between FIELDLOST event and SENSE task */

+#define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */

+#define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */

+#define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */

+#define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 0 : Shortcut between FIELDDETECTED event and ACTIVATE task */

+#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */

+#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */

+#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */

+#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */

+

+/* Register: NFCT_INTEN */

+/* Description: Enable or disable interrupt */

+

+/* Bit 20 : Enable or disable interrupt for STARTED event */

+#define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */

+#define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */

+#define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */

+#define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */

+

+/* Bit 19 : Enable or disable interrupt for SELECTED event */

+#define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */

+#define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */

+#define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */

+#define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */

+

+/* Bit 18 : Enable or disable interrupt for COLLISION event */

+#define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */

+#define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */

+#define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */

+#define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */

+

+/* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */

+#define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */

+#define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */

+#define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */

+#define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */

+

+/* Bit 12 : Enable or disable interrupt for ENDTX event */

+#define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */

+#define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */

+#define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */

+#define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */

+

+/* Bit 11 : Enable or disable interrupt for ENDRX event */

+#define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */

+#define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */

+#define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */

+#define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */

+

+/* Bit 10 : Enable or disable interrupt for RXERROR event */

+#define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */

+#define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */

+#define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */

+#define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */

+

+/* Bit 7 : Enable or disable interrupt for ERROR event */

+#define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */

+#define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */

+#define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */

+#define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */

+

+/* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */

+#define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */

+#define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */

+#define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */

+#define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */

+

+/* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */

+#define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */

+#define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */

+#define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */

+#define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */

+

+/* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */

+#define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */

+#define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */

+#define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */

+#define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */

+

+/* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */

+#define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */

+#define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */

+#define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */

+#define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */

+

+/* Bit 2 : Enable or disable interrupt for FIELDLOST event */

+#define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */

+#define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */

+#define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */

+#define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */

+

+/* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */

+#define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */

+#define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */

+#define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */

+#define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */

+

+/* Bit 0 : Enable or disable interrupt for READY event */

+#define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */

+#define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */

+#define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */

+#define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */

+

+/* Register: NFCT_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 20 : Write '1' to Enable interrupt for STARTED event */

+#define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */

+#define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */

+#define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */

+

+/* Bit 19 : Write '1' to Enable interrupt for SELECTED event */

+#define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */

+#define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */

+#define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */

+

+/* Bit 18 : Write '1' to Enable interrupt for COLLISION event */

+#define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */

+#define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */

+#define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */

+

+/* Bit 14 : Write '1' to Enable interrupt for AUTOCOLRESSTARTED event */

+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */

+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */

+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */

+

+/* Bit 12 : Write '1' to Enable interrupt for ENDTX event */

+#define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */

+#define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */

+#define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */

+

+/* Bit 11 : Write '1' to Enable interrupt for ENDRX event */

+#define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */

+#define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */

+#define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */

+

+/* Bit 10 : Write '1' to Enable interrupt for RXERROR event */

+#define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */

+#define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */

+#define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */

+

+/* Bit 7 : Write '1' to Enable interrupt for ERROR event */

+#define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */

+#define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */

+#define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */

+

+/* Bit 6 : Write '1' to Enable interrupt for RXFRAMEEND event */

+#define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */

+#define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */

+#define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */

+

+/* Bit 5 : Write '1' to Enable interrupt for RXFRAMESTART event */

+#define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */

+#define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */

+#define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */

+

+/* Bit 4 : Write '1' to Enable interrupt for TXFRAMEEND event */

+#define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */

+#define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */

+#define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */

+

+/* Bit 3 : Write '1' to Enable interrupt for TXFRAMESTART event */

+#define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */

+#define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */

+#define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */

+

+/* Bit 2 : Write '1' to Enable interrupt for FIELDLOST event */

+#define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */

+#define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */

+#define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */

+

+/* Bit 1 : Write '1' to Enable interrupt for FIELDDETECTED event */

+#define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */

+#define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */

+#define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */

+

+/* Bit 0 : Write '1' to Enable interrupt for READY event */

+#define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */

+#define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */

+#define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */

+

+/* Register: NFCT_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 20 : Write '1' to Disable interrupt for STARTED event */

+#define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */

+#define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */

+#define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */

+

+/* Bit 19 : Write '1' to Disable interrupt for SELECTED event */

+#define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */

+#define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */

+#define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */

+

+/* Bit 18 : Write '1' to Disable interrupt for COLLISION event */

+#define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */

+#define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */

+#define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */

+

+/* Bit 14 : Write '1' to Disable interrupt for AUTOCOLRESSTARTED event */

+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */

+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */

+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */

+

+/* Bit 12 : Write '1' to Disable interrupt for ENDTX event */

+#define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */

+#define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */

+#define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */

+

+/* Bit 11 : Write '1' to Disable interrupt for ENDRX event */

+#define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */

+#define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */

+#define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */

+

+/* Bit 10 : Write '1' to Disable interrupt for RXERROR event */

+#define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */

+#define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */

+#define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */

+

+/* Bit 7 : Write '1' to Disable interrupt for ERROR event */

+#define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */

+#define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */

+#define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */

+

+/* Bit 6 : Write '1' to Disable interrupt for RXFRAMEEND event */

+#define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */

+#define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */

+#define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */

+

+/* Bit 5 : Write '1' to Disable interrupt for RXFRAMESTART event */

+#define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */

+#define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */

+#define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */

+

+/* Bit 4 : Write '1' to Disable interrupt for TXFRAMEEND event */

+#define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */

+#define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */

+#define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */

+

+/* Bit 3 : Write '1' to Disable interrupt for TXFRAMESTART event */

+#define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */

+#define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */

+#define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */

+

+/* Bit 2 : Write '1' to Disable interrupt for FIELDLOST event */

+#define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */

+#define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */

+#define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */

+

+/* Bit 1 : Write '1' to Disable interrupt for FIELDDETECTED event */

+#define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */

+#define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */

+#define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */

+

+/* Bit 0 : Write '1' to Disable interrupt for READY event */

+#define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */

+#define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */

+#define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */

+#define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */

+#define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */

+

+/* Register: NFCT_ERRORSTATUS */

+/* Description: NFC Error Status register */

+

+/* Bit 3 : Field level is too low at min load resistance */

+#define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos (3UL) /*!< Position of NFCFIELDTOOWEAK field. */

+#define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos) /*!< Bit mask of NFCFIELDTOOWEAK field. */

+

+/* Bit 2 : Field level is too high at max load resistance */

+#define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos (2UL) /*!< Position of NFCFIELDTOOSTRONG field. */

+#define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos) /*!< Bit mask of NFCFIELDTOOSTRONG field. */

+

+/* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */

+#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */

+#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */

+

+/* Register: NFCT_FRAMESTATUS_RX */

+/* Description: Result of last incoming frames */

+

+/* Bit 3 : Overrun detected */

+#define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */

+#define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */

+#define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */

+#define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */

+

+/* Bit 2 : Parity status of received frame */

+#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */

+#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */

+#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */

+#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */

+

+/* Bit 0 : No valid End of Frame detected */

+#define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */

+#define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */

+#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */

+#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */

+

+/* Register: NFCT_CURRENTLOADCTRL */

+/* Description: Current value driven to the NFC Load Control */

+

+/* Bits 5..0 : Current value driven to the NFC Load Control */

+#define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos (0UL) /*!< Position of CURRENTLOADCTRL field. */

+#define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Msk (0x3FUL << NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos) /*!< Bit mask of CURRENTLOADCTRL field. */

+

+/* Register: NFCT_FIELDPRESENT */

+/* Description: Indicates the presence or not of a valid field */

+

+/* Bit 1 : Indicates if the low level has locked to the field */

+#define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */

+#define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */

+#define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */

+#define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */

+

+/* Bit 0 : Indicates the presence or not of a valid field. Available only in the activated state. */

+#define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */

+#define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */

+#define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */

+#define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */

+

+/* Register: NFCT_FRAMEDELAYMIN */

+/* Description: Minimum frame delay */

+

+/* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */

+#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */

+#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */

+

+/* Register: NFCT_FRAMEDELAYMAX */

+/* Description: Maximum frame delay */

+

+/* Bits 15..0 : Maximum frame delay in number of 13.56 MHz clocks */

+#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */

+#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */

+

+/* Register: NFCT_FRAMEDELAYMODE */

+/* Description: Configuration register for the Frame Delay Timer */

+

+/* Bits 1..0 : Configuration register for the Frame Delay Timer */

+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */

+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */

+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */

+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */

+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */

+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */

+

+/* Register: NFCT_PACKETPTR */

+/* Description: Packet pointer for TXD and RXD data storage in Data RAM */

+

+/* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address. */

+#define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */

+#define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */

+

+/* Register: NFCT_MAXLEN */

+/* Description: Size of allocated for TXD and RXD data storage buffer in Data RAM */

+

+/* Bits 8..0 : Size of allocated for TXD and RXD data storage buffer in Data RAM */

+#define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */

+#define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */

+

+/* Register: NFCT_TXD_FRAMECONFIG */

+/* Description: Configuration of outgoing frames */

+

+/* Bit 4 : CRC mode for outgoing frames */

+#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */

+#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */

+#define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */

+#define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */

+

+/* Bit 2 : Adding SoF or not in TX frames */

+#define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */

+#define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */

+#define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol not added */

+#define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol added */

+

+/* Bit 1 : Discarding unused bits in start or at end of a Frame */

+#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */

+#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */

+#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits is discarded at end of frame */

+#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits is discarded at start of frame */

+

+/* Bit 0 : Adding parity or not in the frame */

+#define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */

+#define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */

+#define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added in TX frames */

+#define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added TX frames */

+

+/* Register: NFCT_TXD_AMOUNT */

+/* Description: Size of outgoing frame */

+

+/* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */

+#define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */

+#define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */

+

+/* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */

+#define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */

+#define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */

+

+/* Register: NFCT_RXD_FRAMECONFIG */

+/* Description: Configuration of incoming frames */

+

+/* Bit 4 : CRC mode for incoming frames */

+#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */

+#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */

+#define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */

+#define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */

+

+/* Bit 2 : SoF expected or not in RX frames */

+#define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */

+#define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */

+#define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol is not expected in RX frames */

+#define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol is expected in RX frames */

+

+/* Bit 0 : Parity expected or not in RX frame */

+#define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */

+#define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */

+#define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */

+#define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */

+

+/* Register: NFCT_RXD_AMOUNT */

+/* Description: Size of last incoming frame */

+

+/* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */

+#define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */

+#define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */

+

+/* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */

+#define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */

+#define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */

+

+/* Register: NFCT_NFCID1_LAST */

+/* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */

+

+/* Bits 31..24 : NFCID1 byte W */

+#define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */

+#define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */

+

+/* Bits 23..16 : NFCID1 byte X */

+#define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */

+#define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */

+

+/* Bits 15..8 : NFCID1 byte Y */

+#define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */

+#define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */

+

+/* Bits 7..0 : NFCID1 byte Z (very last byte sent) */

+#define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */

+#define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */

+

+/* Register: NFCT_NFCID1_2ND_LAST */

+/* Description: Second last NFCID1 part (7 or 10 bytes ID) */

+

+/* Bits 23..16 : NFCID1 byte T */

+#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */

+#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */

+

+/* Bits 15..8 : NFCID1 byte U */

+#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */

+#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */

+

+/* Bits 7..0 : NFCID1 byte V */

+#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */

+#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */

+

+/* Register: NFCT_NFCID1_3RD_LAST */

+/* Description: Third last NFCID1 part (10 bytes ID) */

+

+/* Bits 23..16 : NFCID1 byte Q */

+#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */

+#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */

+

+/* Bits 15..8 : NFCID1 byte R */

+#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */

+#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */

+

+/* Bits 7..0 : NFCID1 byte S */

+#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */

+#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */

+

+/* Register: NFCT_SENSRES */

+/* Description: NFC-A SENS_RES auto-response settings */

+

+/* Bits 15..12 : Reserved for future use. Shall be 0. */

+#define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */

+#define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */

+

+/* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */

+#define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */

+#define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */

+

+/* Bits 7..6 : NFCID1 size. This value is used by the Auto collision resolution engine. */

+#define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */

+#define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */

+#define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */

+#define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */

+#define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */

+

+/* Bit 5 : Reserved for future use. Shall be 0. */

+#define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */

+#define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */

+

+/* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */

+#define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */

+#define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */

+#define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */

+#define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */

+#define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */

+#define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */

+#define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */

+#define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */

+

+/* Register: NFCT_SELRES */

+/* Description: NFC-A SEL_RES auto-response settings */

+

+/* Bit 7 : Reserved for future use. Shall be 0. */

+#define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */

+#define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */

+

+/* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */

+#define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */

+#define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */

+

+/* Bits 4..3 : Reserved for future use. Shall be 0. */

+#define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */

+#define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */

+

+/* Bit 2 : Cascade bit (controlled by hardware, write has no effect) */

+#define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */

+#define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */

+#define NFCT_SELRES_CASCADE_Complete (0UL) /*!< NFCID1 complete */

+#define NFCT_SELRES_CASCADE_NotComplete (1UL) /*!< NFCID1 not complete */

+

+/* Bits 1..0 : Reserved for future use. Shall be 0. */

+#define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */

+#define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */

+

+

+/* Peripheral: NVMC */

+/* Description: Non Volatile Memory Controller */

+

+/* Register: NVMC_READY */

+/* Description: Ready flag */

+

+/* Bit 0 : NVMC is ready or busy */

+#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */

+#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */

+#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */

+#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */

+

+/* Register: NVMC_CONFIG */

+/* Description: Configuration register */

+

+/* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */

+#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */

+#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */

+#define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */

+#define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write Enabled */

+#define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */

+

+/* Register: NVMC_ERASEPAGE */

+/* Description: Register for erasing a page in Code area */

+

+/* Bits 31..0 : Register for starting erase of a page in Code area */

+#define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */

+#define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */

+

+/* Register: NVMC_ERASEPCR1 */

+/* Description: Deprecated register -  Register for erasing a page in Code area. Equivalent to ERASEPAGE. */

+

+/* Bits 31..0 : Register for erasing a page in Code area. Equivalent to ERASEPAGE. */

+#define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */

+#define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */

+

+/* Register: NVMC_ERASEALL */

+/* Description: Register for erasing all non-volatile user memory */

+

+/* Bit 0 : Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */

+#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */

+#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */

+#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */

+#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */

+

+/* Register: NVMC_ERASEPCR0 */

+/* Description: Deprecated register -  Register for erasing a page in Code area. Equivalent to ERASEPAGE. */

+

+/* Bits 31..0 : Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. */

+#define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */

+#define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */

+

+/* Register: NVMC_ERASEUICR */

+/* Description: Register for erasing User Information Configuration Registers */

+

+/* Bit 0 : Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */

+#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */

+#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */

+#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */

+#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */

+

+/* Register: NVMC_ICACHECNF */

+/* Description: I-Code cache configuration register. */

+

+/* Bit 8 : Cache profiling enable */

+#define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */

+#define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */

+#define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */

+#define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */

+

+/* Bit 0 : Cache enable */

+#define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */

+#define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */

+#define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */

+#define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */

+

+/* Register: NVMC_IHIT */

+/* Description: I-Code cache hit counter. */

+

+/* Bits 31..0 : Number of cache hits */

+#define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */

+#define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */

+

+/* Register: NVMC_IMISS */

+/* Description: I-Code cache miss counter. */

+

+/* Bits 31..0 : Number of cache misses */

+#define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */

+#define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */

+

+

+/* Peripheral: GPIO */

+/* Description: GPIO Port 1 */

+

+/* Register: GPIO_OUT */

+/* Description: Write GPIO port */

+

+/* Bit 31 : P0.31 pin */

+#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */

+#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */

+#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */

+

+/* Bit 30 : P0.30 pin */

+#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */

+#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */

+#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */

+

+/* Bit 29 : P0.29 pin */

+#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */

+#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */

+#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */

+

+/* Bit 28 : P0.28 pin */

+#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */

+#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */

+#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */

+

+/* Bit 27 : P0.27 pin */

+#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */

+#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */

+#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */

+

+/* Bit 26 : P0.26 pin */

+#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */

+#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */

+#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */

+

+/* Bit 25 : P0.25 pin */

+#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */

+#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */

+#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */

+

+/* Bit 24 : P0.24 pin */

+#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */

+#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */

+#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */

+

+/* Bit 23 : P0.23 pin */

+#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */

+#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */

+#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */

+

+/* Bit 22 : P0.22 pin */

+#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */

+#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */

+#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */

+

+/* Bit 21 : P0.21 pin */

+#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */

+#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */

+#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */

+

+/* Bit 20 : P0.20 pin */

+#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */

+#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */

+#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */

+

+/* Bit 19 : P0.19 pin */

+#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */

+#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */

+#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */

+

+/* Bit 18 : P0.18 pin */

+#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */

+#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */

+#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */

+

+/* Bit 17 : P0.17 pin */

+#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */

+#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */

+#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */

+

+/* Bit 16 : P0.16 pin */

+#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */

+#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */

+#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */

+

+/* Bit 15 : P0.15 pin */

+#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */

+#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */

+#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */

+

+/* Bit 14 : P0.14 pin */

+#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */

+#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */

+#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */

+

+/* Bit 13 : P0.13 pin */

+#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */

+#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */

+#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */

+

+/* Bit 12 : P0.12 pin */

+#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */

+#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */

+#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */

+

+/* Bit 11 : P0.11 pin */

+#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */

+#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */

+#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */

+

+/* Bit 10 : P0.10 pin */

+#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */

+#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */

+#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */

+

+/* Bit 9 : P0.9 pin */

+#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */

+#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */

+#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */

+

+/* Bit 8 : P0.8 pin */

+#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */

+#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */

+#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */

+

+/* Bit 7 : P0.7 pin */

+#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */

+#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */

+#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */

+

+/* Bit 6 : P0.6 pin */

+#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */

+#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */

+#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */

+

+/* Bit 5 : P0.5 pin */

+#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */

+#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */

+#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */

+

+/* Bit 4 : P0.4 pin */

+#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */

+#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */

+#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */

+

+/* Bit 3 : P0.3 pin */

+#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */

+#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */

+#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */

+

+/* Bit 2 : P0.2 pin */

+#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */

+#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */

+#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */

+

+/* Bit 1 : P0.1 pin */

+#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */

+#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */

+#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */

+

+/* Bit 0 : P0.0 pin */

+#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */

+#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */

+#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */

+#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */

+

+/* Register: GPIO_OUTSET */

+/* Description: Set individual bits in GPIO port */

+

+/* Bit 31 : P0.31 pin */

+#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */

+#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */

+#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 30 : P0.30 pin */

+#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */

+#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */

+#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 29 : P0.29 pin */

+#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */

+#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */

+#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 28 : P0.28 pin */

+#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */

+#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */

+#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 27 : P0.27 pin */

+#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */

+#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */

+#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 26 : P0.26 pin */

+#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */

+#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */

+#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 25 : P0.25 pin */

+#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */

+#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */

+#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 24 : P0.24 pin */

+#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */

+#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */

+#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 23 : P0.23 pin */

+#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */

+#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */

+#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 22 : P0.22 pin */

+#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */

+#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */

+#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 21 : P0.21 pin */

+#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */

+#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */

+#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 20 : P0.20 pin */

+#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */

+#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */

+#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 19 : P0.19 pin */

+#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */

+#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */

+#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 18 : P0.18 pin */

+#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */

+#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */

+#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 17 : P0.17 pin */

+#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */

+#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */

+#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 16 : P0.16 pin */

+#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */

+#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */

+#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 15 : P0.15 pin */

+#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */

+#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */

+#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 14 : P0.14 pin */

+#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */

+#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */

+#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 13 : P0.13 pin */

+#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */

+#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */

+#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 12 : P0.12 pin */

+#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */

+#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */

+#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 11 : P0.11 pin */

+#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */

+#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */

+#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 10 : P0.10 pin */

+#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */

+#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */

+#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 9 : P0.9 pin */

+#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */

+#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */

+#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 8 : P0.8 pin */

+#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */

+#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */

+#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 7 : P0.7 pin */

+#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */

+#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */

+#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 6 : P0.6 pin */

+#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */

+#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */

+#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 5 : P0.5 pin */

+#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */

+#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */

+#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 4 : P0.4 pin */

+#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */

+#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */

+#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 3 : P0.3 pin */

+#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */

+#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */

+#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 2 : P0.2 pin */

+#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */

+#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */

+#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 1 : P0.1 pin */

+#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */

+#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */

+#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Bit 0 : P0.0 pin */

+#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */

+#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */

+#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

+

+/* Register: GPIO_OUTCLR */

+/* Description: Clear individual bits in GPIO port */

+

+/* Bit 31 : P0.31 pin */

+#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */

+#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */

+#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 30 : P0.30 pin */

+#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */

+#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */

+#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 29 : P0.29 pin */

+#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */

+#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */

+#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 28 : P0.28 pin */

+#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */

+#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */

+#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 27 : P0.27 pin */

+#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */

+#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */

+#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 26 : P0.26 pin */

+#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */

+#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */

+#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 25 : P0.25 pin */

+#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */

+#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */

+#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 24 : P0.24 pin */

+#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */

+#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */

+#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 23 : P0.23 pin */

+#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */

+#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */

+#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 22 : P0.22 pin */

+#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */

+#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */

+#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 21 : P0.21 pin */

+#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */

+#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */

+#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 20 : P0.20 pin */

+#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */

+#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */

+#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 19 : P0.19 pin */

+#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */

+#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */

+#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 18 : P0.18 pin */

+#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */

+#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */

+#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 17 : P0.17 pin */

+#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */

+#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */

+#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 16 : P0.16 pin */

+#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */

+#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */

+#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 15 : P0.15 pin */

+#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */

+#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */

+#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 14 : P0.14 pin */

+#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */

+#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */

+#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 13 : P0.13 pin */

+#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */

+#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */

+#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 12 : P0.12 pin */

+#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */

+#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */

+#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 11 : P0.11 pin */

+#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */

+#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */

+#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 10 : P0.10 pin */

+#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */

+#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */

+#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 9 : P0.9 pin */

+#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */

+#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */

+#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 8 : P0.8 pin */

+#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */

+#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */

+#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 7 : P0.7 pin */

+#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */

+#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */

+#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 6 : P0.6 pin */

+#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */

+#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */

+#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 5 : P0.5 pin */

+#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */

+#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */

+#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 4 : P0.4 pin */

+#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */

+#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */

+#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 3 : P0.3 pin */

+#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */

+#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */

+#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 2 : P0.2 pin */

+#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */

+#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */

+#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 1 : P0.1 pin */

+#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */

+#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */

+#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Bit 0 : P0.0 pin */

+#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */

+#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */

+#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */

+#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */

+#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

+

+/* Register: GPIO_IN */

+/* Description: Read GPIO port */

+

+/* Bit 31 : P0.31 pin */

+#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */

+#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */

+#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */

+

+/* Bit 30 : P0.30 pin */

+#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */

+#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */

+#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */

+

+/* Bit 29 : P0.29 pin */

+#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */

+#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */

+#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */

+

+/* Bit 28 : P0.28 pin */

+#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */

+#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */

+#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */

+

+/* Bit 27 : P0.27 pin */

+#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */

+#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */

+#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */

+

+/* Bit 26 : P0.26 pin */

+#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */

+#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */

+#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */

+

+/* Bit 25 : P0.25 pin */

+#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */

+#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */

+#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */

+

+/* Bit 24 : P0.24 pin */

+#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */

+#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */

+#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */

+

+/* Bit 23 : P0.23 pin */

+#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */

+#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */

+#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */

+

+/* Bit 22 : P0.22 pin */

+#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */

+#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */

+#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */

+

+/* Bit 21 : P0.21 pin */

+#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */

+#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */

+#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */

+

+/* Bit 20 : P0.20 pin */

+#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */

+#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */

+#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */

+

+/* Bit 19 : P0.19 pin */

+#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */

+#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */

+#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */

+

+/* Bit 18 : P0.18 pin */

+#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */

+#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */

+#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */

+

+/* Bit 17 : P0.17 pin */

+#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */

+#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */

+#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */

+

+/* Bit 16 : P0.16 pin */

+#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */

+#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */

+#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */

+

+/* Bit 15 : P0.15 pin */

+#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */

+#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */

+#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */

+

+/* Bit 14 : P0.14 pin */

+#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */

+#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */

+#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */

+

+/* Bit 13 : P0.13 pin */

+#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */

+#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */

+#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */

+

+/* Bit 12 : P0.12 pin */

+#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */

+#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */

+#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */

+

+/* Bit 11 : P0.11 pin */

+#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */

+#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */

+#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */

+

+/* Bit 10 : P0.10 pin */

+#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */

+#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */

+#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */

+

+/* Bit 9 : P0.9 pin */

+#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */

+#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */

+#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */

+

+/* Bit 8 : P0.8 pin */

+#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */

+#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */

+#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */

+

+/* Bit 7 : P0.7 pin */

+#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */

+#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */

+#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */

+

+/* Bit 6 : P0.6 pin */

+#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */

+#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */

+#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */

+

+/* Bit 5 : P0.5 pin */

+#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */

+#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */

+#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */

+

+/* Bit 4 : P0.4 pin */

+#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */

+#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */

+#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */

+

+/* Bit 3 : P0.3 pin */

+#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */

+#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */

+#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */

+

+/* Bit 2 : P0.2 pin */

+#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */

+#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */

+#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */

+

+/* Bit 1 : P0.1 pin */

+#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */

+#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */

+#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */

+

+/* Bit 0 : P0.0 pin */

+#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */

+#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */

+#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */

+#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */

+

+/* Register: GPIO_DIR */

+/* Description: Direction of GPIO pins */

+

+/* Bit 31 : P0.31 pin */

+#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */

+#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */

+#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */

+

+/* Bit 30 : P0.30 pin */

+#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */

+#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */

+#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */

+

+/* Bit 29 : P0.29 pin */

+#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */

+#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */

+#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */

+

+/* Bit 28 : P0.28 pin */

+#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */

+#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */

+#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */

+

+/* Bit 27 : P0.27 pin */

+#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */

+#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */

+#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */

+

+/* Bit 26 : P0.26 pin */

+#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */

+#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */

+#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */

+

+/* Bit 25 : P0.25 pin */

+#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */

+#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */

+#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */

+

+/* Bit 24 : P0.24 pin */

+#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */

+#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */

+#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */

+

+/* Bit 23 : P0.23 pin */

+#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */

+#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */

+#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */

+

+/* Bit 22 : P0.22 pin */

+#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */

+#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */

+#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */

+

+/* Bit 21 : P0.21 pin */

+#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */

+#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */

+#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */

+

+/* Bit 20 : P0.20 pin */

+#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */

+#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */

+#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */

+

+/* Bit 19 : P0.19 pin */

+#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */

+#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */

+#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */

+

+/* Bit 18 : P0.18 pin */

+#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */

+#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */

+#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */

+

+/* Bit 17 : P0.17 pin */

+#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */

+#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */

+#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */

+

+/* Bit 16 : P0.16 pin */

+#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */

+#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */

+#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */

+

+/* Bit 15 : P0.15 pin */

+#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */

+#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */

+#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */

+

+/* Bit 14 : P0.14 pin */

+#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */

+#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */

+#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */

+

+/* Bit 13 : P0.13 pin */

+#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */

+#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */

+#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */

+

+/* Bit 12 : P0.12 pin */

+#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */

+#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */

+#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */

+

+/* Bit 11 : P0.11 pin */

+#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */

+#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */

+#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */

+

+/* Bit 10 : P0.10 pin */

+#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */

+#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */

+#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */

+

+/* Bit 9 : P0.9 pin */

+#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */

+#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */

+#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */

+

+/* Bit 8 : P0.8 pin */

+#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */

+#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */

+#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */

+

+/* Bit 7 : P0.7 pin */

+#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */

+#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */

+#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */

+

+/* Bit 6 : P0.6 pin */

+#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */

+#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */

+#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */

+

+/* Bit 5 : P0.5 pin */

+#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */

+#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */

+#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */

+

+/* Bit 4 : P0.4 pin */

+#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */

+#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */

+#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */

+

+/* Bit 3 : P0.3 pin */

+#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */

+#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */

+#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */

+

+/* Bit 2 : P0.2 pin */

+#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */

+#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */

+#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */

+

+/* Bit 1 : P0.1 pin */

+#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */

+#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */

+#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */

+

+/* Bit 0 : P0.0 pin */

+#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */

+#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */

+#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */

+#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */

+

+/* Register: GPIO_DIRSET */

+/* Description: DIR set register */

+

+/* Bit 31 : Set as output pin 31 */

+#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */

+#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */

+#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 30 : Set as output pin 30 */

+#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */

+#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */

+#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 29 : Set as output pin 29 */

+#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */

+#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */

+#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 28 : Set as output pin 28 */

+#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */

+#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */

+#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 27 : Set as output pin 27 */

+#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */

+#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */

+#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 26 : Set as output pin 26 */

+#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */

+#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */

+#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 25 : Set as output pin 25 */

+#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */

+#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */

+#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 24 : Set as output pin 24 */

+#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */

+#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */

+#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 23 : Set as output pin 23 */

+#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */

+#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */

+#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 22 : Set as output pin 22 */

+#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */

+#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */

+#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 21 : Set as output pin 21 */

+#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */

+#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */

+#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 20 : Set as output pin 20 */

+#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */

+#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */

+#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 19 : Set as output pin 19 */

+#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */

+#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */

+#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 18 : Set as output pin 18 */

+#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */

+#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */

+#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 17 : Set as output pin 17 */

+#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */

+#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */

+#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 16 : Set as output pin 16 */

+#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */

+#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */

+#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 15 : Set as output pin 15 */

+#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */

+#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */

+#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 14 : Set as output pin 14 */

+#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */

+#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */

+#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 13 : Set as output pin 13 */

+#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */

+#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */

+#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 12 : Set as output pin 12 */

+#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */

+#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */

+#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 11 : Set as output pin 11 */

+#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */

+#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */

+#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 10 : Set as output pin 10 */

+#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */

+#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */

+#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 9 : Set as output pin 9 */

+#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */

+#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */

+#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 8 : Set as output pin 8 */

+#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */

+#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */

+#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 7 : Set as output pin 7 */

+#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */

+#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */

+#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 6 : Set as output pin 6 */

+#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */

+#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */

+#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 5 : Set as output pin 5 */

+#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */

+#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */

+#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 4 : Set as output pin 4 */

+#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */

+#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */

+#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 3 : Set as output pin 3 */

+#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */

+#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */

+#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 2 : Set as output pin 2 */

+#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */

+#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */

+#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 1 : Set as output pin 1 */

+#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */

+#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */

+#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Bit 0 : Set as output pin 0 */

+#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */

+#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */

+#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

+

+/* Register: GPIO_DIRCLR */

+/* Description: DIR clear register */

+

+/* Bit 31 : Set as input pin 31 */

+#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */

+#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */

+#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 30 : Set as input pin 30 */

+#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */

+#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */

+#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 29 : Set as input pin 29 */

+#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */

+#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */

+#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 28 : Set as input pin 28 */

+#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */

+#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */

+#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 27 : Set as input pin 27 */

+#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */

+#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */

+#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 26 : Set as input pin 26 */

+#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */

+#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */

+#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 25 : Set as input pin 25 */

+#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */

+#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */

+#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 24 : Set as input pin 24 */

+#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */

+#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */

+#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 23 : Set as input pin 23 */

+#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */

+#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */

+#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 22 : Set as input pin 22 */

+#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */

+#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */

+#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 21 : Set as input pin 21 */

+#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */

+#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */

+#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 20 : Set as input pin 20 */

+#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */

+#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */

+#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 19 : Set as input pin 19 */

+#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */

+#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */

+#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 18 : Set as input pin 18 */

+#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */

+#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */

+#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 17 : Set as input pin 17 */

+#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */

+#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */

+#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 16 : Set as input pin 16 */

+#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */

+#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */

+#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 15 : Set as input pin 15 */

+#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */

+#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */

+#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 14 : Set as input pin 14 */

+#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */

+#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */

+#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 13 : Set as input pin 13 */

+#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */

+#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */

+#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 12 : Set as input pin 12 */

+#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */

+#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */

+#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 11 : Set as input pin 11 */

+#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */

+#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */

+#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 10 : Set as input pin 10 */

+#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */

+#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */

+#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 9 : Set as input pin 9 */

+#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */

+#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */

+#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 8 : Set as input pin 8 */

+#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */

+#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */

+#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 7 : Set as input pin 7 */

+#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */

+#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */

+#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 6 : Set as input pin 6 */

+#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */

+#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */

+#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 5 : Set as input pin 5 */

+#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */

+#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */

+#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 4 : Set as input pin 4 */

+#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */

+#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */

+#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 3 : Set as input pin 3 */

+#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */

+#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */

+#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 2 : Set as input pin 2 */

+#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */

+#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */

+#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 1 : Set as input pin 1 */

+#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */

+#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */

+#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Bit 0 : Set as input pin 0 */

+#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */

+#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */

+#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */

+#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */

+#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

+

+/* Register: GPIO_LATCH */

+/* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */

+

+/* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */

+#define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */

+#define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */

+#define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */

+#define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */

+#define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */

+#define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */

+#define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */

+#define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */

+#define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */

+#define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */

+#define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */

+#define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */

+#define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */

+#define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */

+#define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */

+#define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */

+#define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */

+#define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */

+#define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */

+#define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */

+#define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */

+#define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */

+#define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */

+#define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */

+#define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */

+#define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */

+#define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */

+#define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */

+#define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */

+#define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */

+#define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */

+#define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */

+#define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */

+#define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */

+#define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */

+#define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */

+#define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */

+#define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */

+#define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */

+#define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */

+#define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */

+#define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */

+#define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */

+#define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */

+#define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */

+#define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */

+#define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */

+#define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */

+#define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */

+#define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */

+#define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */

+#define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */

+#define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */

+#define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */

+#define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */

+#define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */

+#define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */

+#define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */

+#define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */

+#define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */

+#define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */

+#define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */

+

+/* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */

+#define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */

+#define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */

+#define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */

+#define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */

+

+/* Register: GPIO_DETECTMODE */

+/* Description: Select between default DETECT signal behaviour and LDETECT mode */

+

+/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */

+#define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */

+#define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */

+#define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */

+#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */

+

+/* Register: GPIO_PIN_CNF */

+/* Description: Description collection[0]:  Configuration of GPIO pins */

+

+/* Bits 17..16 : Pin sensing mechanism */

+#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */

+#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */

+#define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */

+#define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */

+#define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */

+

+/* Bits 10..8 : Drive configuration */

+#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */

+#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */

+#define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */

+#define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */

+#define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */

+#define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */

+#define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */

+#define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */

+#define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */

+#define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */

+

+/* Bits 3..2 : Pull configuration */

+#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */

+#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */

+#define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */

+#define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */

+#define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */

+

+/* Bit 1 : Connect or disconnect input buffer */

+#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */

+#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */

+#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */

+#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */

+

+/* Bit 0 : Pin direction. Same physical register as DIR register */

+#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */

+#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */

+#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */

+#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */

+

+

+/* Peripheral: PDM */

+/* Description: Pulse Density Modulation (Digital Microphone) Interface */

+

+/* Register: PDM_INTEN */

+/* Description: Enable or disable interrupt */

+

+/* Bit 2 : Enable or disable interrupt for END event */

+#define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */

+#define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */

+#define PDM_INTEN_END_Disabled (0UL) /*!< Disable */

+#define PDM_INTEN_END_Enabled (1UL) /*!< Enable */

+

+/* Bit 1 : Enable or disable interrupt for STOPPED event */

+#define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */

+#define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */

+#define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */

+#define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */

+

+/* Bit 0 : Enable or disable interrupt for STARTED event */

+#define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */

+#define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */

+#define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */

+#define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */

+

+/* Register: PDM_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 2 : Write '1' to Enable interrupt for END event */

+#define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */

+#define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */

+#define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */

+#define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */

+#define PDM_INTENSET_END_Set (1UL) /*!< Enable */

+

+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */

+#define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */

+#define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */

+#define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */

+#define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */

+#define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */

+

+/* Bit 0 : Write '1' to Enable interrupt for STARTED event */

+#define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */

+#define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */

+#define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */

+#define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */

+#define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */

+

+/* Register: PDM_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 2 : Write '1' to Disable interrupt for END event */

+#define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */

+#define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */

+#define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */

+#define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */

+#define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */

+

+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */

+#define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */

+#define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */

+#define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */

+#define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */

+#define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */

+

+/* Bit 0 : Write '1' to Disable interrupt for STARTED event */

+#define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */

+#define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */

+#define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */

+#define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */

+#define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */

+

+/* Register: PDM_ENABLE */

+/* Description: PDM module enable register */

+

+/* Bit 0 : Enable or disable PDM module */

+#define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */

+#define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */

+#define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */

+#define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */

+

+/* Register: PDM_PDMCLKCTRL */

+/* Description: PDM clock generator control */

+

+/* Bits 31..0 : PDM_CLK frequency */

+#define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */

+#define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */

+#define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */

+#define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz */

+#define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */

+

+/* Register: PDM_MODE */

+/* Description: Defines the routing of the connected PDM microphones' signals */

+

+/* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */

+#define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */

+#define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */

+#define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */

+#define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */

+

+/* Bit 0 : Mono or stereo operation */

+#define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */

+#define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */

+#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */

+#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */

+

+/* Register: PDM_GAINL */

+/* Description: Left output gain adjustment */

+

+/* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00    -20 dB gain adjust 0x01  -19.5 dB gain adjust (...) 0x27   -0.5 dB gain adjust 0x28      0 dB gain adjust 0x29   +0.5 dB gain adjust (...) 0x4F  +19.5 dB gain adjust 0x50    +20 dB gain adjust */

+#define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */

+#define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */

+#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */

+#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */

+#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */

+

+/* Register: PDM_GAINR */

+/* Description: Right output gain adjustment */

+

+/* Bits 7..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */

+#define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */

+#define PDM_GAINR_GAINR_Msk (0xFFUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */

+#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */

+#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */

+#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */

+

+/* Register: PDM_PSEL_CLK */

+/* Description: Pin number configuration for PDM CLK signal */

+

+/* Bit 31 : Connection */

+#define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */

+#define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */

+#define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */

+#define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */

+

+/* Bits 4..0 : Pin number */

+#define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */

+#define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */

+

+/* Register: PDM_PSEL_DIN */

+/* Description: Pin number configuration for PDM DIN signal */

+

+/* Bit 31 : Connection */

+#define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */

+#define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */

+#define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */

+#define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */

+

+/* Bits 4..0 : Pin number */

+#define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */

+#define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */

+

+/* Register: PDM_SAMPLE_PTR */

+/* Description: RAM address pointer to write samples to with EasyDMA */

+

+/* Bits 31..0 : Address to write PDM samples to over DMA */

+#define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */

+#define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */

+

+/* Register: PDM_SAMPLE_MAXCNT */

+/* Description: Number of samples to allocate memory for in EasyDMA mode */

+

+/* Bits 14..0 : Length of DMA RAM allocation in number of samples */

+#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */

+#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */

+

+

+/* Peripheral: POWER */

+/* Description: Power control */

+

+/* Register: POWER_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 6 : Write '1' to Enable interrupt for SLEEPEXIT event */

+#define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */

+#define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */

+#define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */

+#define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */

+#define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */

+

+/* Bit 5 : Write '1' to Enable interrupt for SLEEPENTER event */

+#define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */

+#define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */

+#define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */

+#define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */

+#define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */

+

+/* Bit 2 : Write '1' to Enable interrupt for POFWARN event */

+#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */

+#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */

+#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */

+#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */

+#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */

+

+/* Register: POWER_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 6 : Write '1' to Disable interrupt for SLEEPEXIT event */

+#define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */

+#define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */

+#define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */

+#define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */

+#define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */

+

+/* Bit 5 : Write '1' to Disable interrupt for SLEEPENTER event */

+#define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */

+#define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */

+#define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */

+#define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */

+#define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */

+

+/* Bit 2 : Write '1' to Disable interrupt for POFWARN event */

+#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */

+#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */

+#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */

+#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */

+#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */

+

+/* Register: POWER_RESETREAS */

+/* Description: Reset reason */

+

+/* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */

+#define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */

+#define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */

+#define POWER_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */

+#define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */

+

+/* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */

+#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */

+#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */

+#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */

+#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */

+

+/* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */

+#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */

+#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */

+#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */

+#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */

+

+/* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */

+#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */

+#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */

+#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */

+#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */

+

+/* Bit 3 : Reset from CPU lock-up detected */

+#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */

+#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */

+#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */

+#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */

+

+/* Bit 2 : Reset from soft reset detected */

+#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */

+#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */

+#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */

+#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */

+

+/* Bit 1 : Reset from watchdog detected */

+#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */

+#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */

+#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */

+#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */

+

+/* Bit 0 : Reset from pin-reset detected */

+#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */

+#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */

+#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */

+#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */

+

+/* Register: POWER_RAMSTATUS */

+/* Description: Deprecated register -  RAM status register */

+

+/* Bit 3 : RAM block 3 is on or off/powering up */

+#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */

+#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */

+#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< Off */

+#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */

+

+/* Bit 2 : RAM block 2 is on or off/powering up */

+#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */

+#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */

+#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< Off */

+#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */

+

+/* Bit 1 : RAM block 1 is on or off/powering up */

+#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */

+#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */

+#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */

+#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */

+

+/* Bit 0 : RAM block 0 is on or off/powering up */

+#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */

+#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */

+#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */

+#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */

+

+/* Register: POWER_SYSTEMOFF */

+/* Description: System OFF register */

+

+/* Bit 0 : Enable System OFF mode */

+#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */

+#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */

+#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */

+

+/* Register: POWER_POFCON */

+/* Description: Power failure comparator configuration */

+

+/* Bits 4..1 : Power failure comparator threshold setting */

+#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */

+#define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */

+#define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */

+#define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */

+#define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */

+#define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */

+#define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */

+#define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */

+#define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */

+#define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */

+#define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */

+#define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */

+#define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */

+#define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */

+

+/* Bit 0 : Enable or disable power failure comparator */

+#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */

+#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */

+#define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */

+#define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */

+

+/* Register: POWER_GPREGRET */

+/* Description: General purpose retention register */

+

+/* Bits 7..0 : General purpose retention register */

+#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */

+#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */

+

+/* Register: POWER_GPREGRET2 */

+/* Description: General purpose retention register */

+

+/* Bits 7..0 : General purpose retention register */

+#define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */

+#define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */

+

+/* Register: POWER_RAMON */

+/* Description: Deprecated register -  RAM on/off register (this register is retained) */

+

+/* Bit 17 : Keep retention on RAM block 1 when RAM block is switched off */

+#define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */

+#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */

+#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< Off */

+#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< On */

+

+/* Bit 16 : Keep retention on RAM block 0 when RAM block is switched off */

+#define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */

+#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */

+#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< Off */

+#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< On */

+

+/* Bit 1 : Keep RAM block 1 on or off in system ON Mode */

+#define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */

+#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */

+#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< Off */

+#define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< On */

+

+/* Bit 0 : Keep RAM block 0 on or off in system ON Mode */

+#define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */

+#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */

+#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< Off */

+#define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< On */

+

+/* Register: POWER_RAMONB */

+/* Description: Deprecated register -  RAM on/off register (this register is retained) */

+

+/* Bit 17 : Keep retention on RAM block 3 when RAM block is switched off */

+#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */

+#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */

+#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< Off */

+#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< On */

+

+/* Bit 16 : Keep retention on RAM block 2 when RAM block is switched off */

+#define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */

+#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */

+#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< Off */

+#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< On */

+

+/* Bit 1 : Keep RAM block 3 on or off in system ON Mode */

+#define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */

+#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */

+#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< Off */

+#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< On */

+

+/* Bit 0 : Keep RAM block 2 on or off in system ON Mode */

+#define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */

+#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */

+#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< Off */

+#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< On */

+

+/* Register: POWER_DCDCEN */

+/* Description: DC/DC enable register */

+

+/* Bit 0 : Enable or disable DC/DC converter */

+#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */

+#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */

+#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */

+#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */

+

+/* Register: POWER_RAM_POWER */

+/* Description: Description cluster[0]:  RAM0 power control register */

+

+/* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */

+#define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */

+#define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */

+#define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */

+#define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */

+

+/* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */

+#define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */

+#define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */

+#define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */

+#define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */

+

+/* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */

+#define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */

+#define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */

+#define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */

+#define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */

+

+/* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */

+#define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */

+#define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */

+#define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */

+#define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */

+

+/* Register: POWER_RAM_POWERSET */

+/* Description: Description cluster[0]:  RAM0 power control set register */

+

+/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */

+#define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */

+#define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */

+#define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */

+

+/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */

+#define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */

+#define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */

+#define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */

+

+/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */

+#define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */

+#define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */

+#define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */

+

+/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */

+#define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */

+#define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */

+#define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */

+

+/* Register: POWER_RAM_POWERCLR */

+/* Description: Description cluster[0]:  RAM0 power control clear register */

+

+/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */

+#define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */

+#define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */

+#define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */

+

+/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */

+#define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */

+#define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */

+#define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */

+

+/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */

+#define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */

+#define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */

+#define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */

+

+/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */

+#define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */

+#define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */

+#define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */

+

+

+/* Peripheral: PPI */

+/* Description: Programmable Peripheral Interconnect */

+

+/* Register: PPI_CHEN */

+/* Description: Channel enable register */

+

+/* Bit 31 : Enable or disable channel 31 */

+#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */

+#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */

+#define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 30 : Enable or disable channel 30 */

+#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */

+#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */

+#define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 29 : Enable or disable channel 29 */

+#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */

+#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */

+#define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 28 : Enable or disable channel 28 */

+#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */

+#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */

+#define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 27 : Enable or disable channel 27 */

+#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */

+#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */

+#define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 26 : Enable or disable channel 26 */

+#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */

+#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */

+#define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 25 : Enable or disable channel 25 */

+#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */

+#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */

+#define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 24 : Enable or disable channel 24 */

+#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */

+#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */

+#define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 23 : Enable or disable channel 23 */

+#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */

+#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */

+#define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 22 : Enable or disable channel 22 */

+#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */

+#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */

+#define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 21 : Enable or disable channel 21 */

+#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */

+#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */

+#define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 20 : Enable or disable channel 20 */

+#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */

+#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */

+#define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 19 : Enable or disable channel 19 */

+#define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */

+#define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */

+#define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 18 : Enable or disable channel 18 */

+#define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */

+#define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */

+#define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 17 : Enable or disable channel 17 */

+#define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */

+#define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */

+#define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 16 : Enable or disable channel 16 */

+#define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */

+#define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */

+#define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 15 : Enable or disable channel 15 */

+#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */

+#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */

+#define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 14 : Enable or disable channel 14 */

+#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */

+#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */

+#define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 13 : Enable or disable channel 13 */

+#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */

+#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */

+#define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 12 : Enable or disable channel 12 */

+#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */

+#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */

+#define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 11 : Enable or disable channel 11 */

+#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */

+#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */

+#define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 10 : Enable or disable channel 10 */

+#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */

+#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */

+#define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 9 : Enable or disable channel 9 */

+#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */

+#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */

+#define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 8 : Enable or disable channel 8 */

+#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */

+#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */

+#define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 7 : Enable or disable channel 7 */

+#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */

+#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */

+#define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 6 : Enable or disable channel 6 */

+#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */

+#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */

+#define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 5 : Enable or disable channel 5 */

+#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */

+#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */

+#define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 4 : Enable or disable channel 4 */

+#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */

+#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */

+#define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 3 : Enable or disable channel 3 */

+#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */

+#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */

+#define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 2 : Enable or disable channel 2 */

+#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */

+#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */

+#define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 1 : Enable or disable channel 1 */

+#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */

+#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */

+#define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */

+

+/* Bit 0 : Enable or disable channel 0 */

+#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */

+#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */

+#define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */

+#define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */

+

+/* Register: PPI_CHENSET */

+/* Description: Channel enable set register */

+

+/* Bit 31 : Channel 31 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */

+#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */

+#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 30 : Channel 30 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */

+#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */

+#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 29 : Channel 29 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */

+#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */

+#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 28 : Channel 28 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */

+#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */

+#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 27 : Channel 27 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */

+#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */

+#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 26 : Channel 26 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */

+#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */

+#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 25 : Channel 25 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */

+#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */

+#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 24 : Channel 24 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */

+#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */

+#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 23 : Channel 23 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */

+#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */

+#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 22 : Channel 22 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */

+#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */

+#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 21 : Channel 21 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */

+#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */

+#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 20 : Channel 20 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */

+#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */

+#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 19 : Channel 19 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */

+#define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */

+#define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 18 : Channel 18 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */

+#define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */

+#define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 17 : Channel 17 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */

+#define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */

+#define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 16 : Channel 16 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */

+#define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */

+#define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 15 : Channel 15 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */

+#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */

+#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 14 : Channel 14 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */

+#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */

+#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 13 : Channel 13 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */

+#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */

+#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 12 : Channel 12 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */

+#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */

+#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 11 : Channel 11 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */

+#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */

+#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 10 : Channel 10 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */

+#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */

+#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 9 : Channel 9 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */

+#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */

+#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 8 : Channel 8 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */

+#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */

+#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 7 : Channel 7 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */

+#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */

+#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 6 : Channel 6 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */

+#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */

+#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 5 : Channel 5 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */

+#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */

+#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 4 : Channel 4 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */

+#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */

+#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 3 : Channel 3 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */

+#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */

+#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 2 : Channel 2 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */

+#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */

+#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 1 : Channel 1 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */

+#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */

+#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */

+

+/* Bit 0 : Channel 0 enable set register.  Writing '0' has no effect */

+#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */

+#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */

+#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */

+

+/* Register: PPI_CHENCLR */

+/* Description: Channel enable clear register */

+

+/* Bit 31 : Channel 31 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */

+#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */

+#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 30 : Channel 30 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */

+#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */

+#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 29 : Channel 29 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */

+#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */

+#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 28 : Channel 28 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */

+#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */

+#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 27 : Channel 27 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */

+#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */

+#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 26 : Channel 26 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */

+#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */

+#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 25 : Channel 25 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */

+#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */

+#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 24 : Channel 24 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */

+#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */

+#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 23 : Channel 23 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */

+#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */

+#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 22 : Channel 22 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */

+#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */

+#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 21 : Channel 21 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */

+#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */

+#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 20 : Channel 20 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */

+#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */

+#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 19 : Channel 19 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */

+#define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */

+#define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 18 : Channel 18 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */

+#define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */

+#define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 17 : Channel 17 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */

+#define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */

+#define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 16 : Channel 16 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */

+#define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */

+#define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 15 : Channel 15 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */

+#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */

+#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 14 : Channel 14 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */

+#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */

+#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 13 : Channel 13 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */

+#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */

+#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 12 : Channel 12 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */

+#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */

+#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 11 : Channel 11 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */

+#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */

+#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 10 : Channel 10 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */

+#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */

+#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 9 : Channel 9 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */

+#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */

+#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 8 : Channel 8 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */

+#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */

+#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 7 : Channel 7 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */

+#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */

+#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 6 : Channel 6 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */

+#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */

+#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 5 : Channel 5 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */

+#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */

+#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 4 : Channel 4 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */

+#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */

+#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 3 : Channel 3 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */

+#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */

+#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 2 : Channel 2 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */

+#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */

+#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 1 : Channel 1 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */

+#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */

+#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */

+

+/* Bit 0 : Channel 0 enable clear register.  Writing '0' has no effect */

+#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */

+#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */

+#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */

+#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */

+#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */

+

+/* Register: PPI_CH_EEP */

+/* Description: Description cluster[0]:  Channel 0 event end-point */

+

+/* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */

+#define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */

+#define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */

+

+/* Register: PPI_CH_TEP */

+/* Description: Description cluster[0]:  Channel 0 task end-point */

+

+/* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */

+#define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */

+#define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */

+

+/* Register: PPI_CHG */

+/* Description: Description collection[0]:  Channel group 0 */

+

+/* Bit 31 : Include or exclude channel 31 */

+#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */

+#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */

+#define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH31_Included (1UL) /*!< Include */

+

+/* Bit 30 : Include or exclude channel 30 */

+#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */

+#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */

+#define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH30_Included (1UL) /*!< Include */

+

+/* Bit 29 : Include or exclude channel 29 */

+#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */

+#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */

+#define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH29_Included (1UL) /*!< Include */

+

+/* Bit 28 : Include or exclude channel 28 */

+#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */

+#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */

+#define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH28_Included (1UL) /*!< Include */

+

+/* Bit 27 : Include or exclude channel 27 */

+#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */

+#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */

+#define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH27_Included (1UL) /*!< Include */

+

+/* Bit 26 : Include or exclude channel 26 */

+#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */

+#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */

+#define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH26_Included (1UL) /*!< Include */

+

+/* Bit 25 : Include or exclude channel 25 */

+#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */

+#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */

+#define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH25_Included (1UL) /*!< Include */

+

+/* Bit 24 : Include or exclude channel 24 */

+#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */

+#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */

+#define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH24_Included (1UL) /*!< Include */

+

+/* Bit 23 : Include or exclude channel 23 */

+#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */

+#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */

+#define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH23_Included (1UL) /*!< Include */

+

+/* Bit 22 : Include or exclude channel 22 */

+#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */

+#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */

+#define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH22_Included (1UL) /*!< Include */

+

+/* Bit 21 : Include or exclude channel 21 */

+#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */

+#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */

+#define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH21_Included (1UL) /*!< Include */

+

+/* Bit 20 : Include or exclude channel 20 */

+#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */

+#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */

+#define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH20_Included (1UL) /*!< Include */

+

+/* Bit 19 : Include or exclude channel 19 */

+#define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */

+#define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */

+#define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH19_Included (1UL) /*!< Include */

+

+/* Bit 18 : Include or exclude channel 18 */

+#define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */

+#define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */

+#define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH18_Included (1UL) /*!< Include */

+

+/* Bit 17 : Include or exclude channel 17 */

+#define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */

+#define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */

+#define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH17_Included (1UL) /*!< Include */

+

+/* Bit 16 : Include or exclude channel 16 */

+#define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */

+#define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */

+#define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH16_Included (1UL) /*!< Include */

+

+/* Bit 15 : Include or exclude channel 15 */

+#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */

+#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */

+#define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH15_Included (1UL) /*!< Include */

+

+/* Bit 14 : Include or exclude channel 14 */

+#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */

+#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */

+#define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH14_Included (1UL) /*!< Include */

+

+/* Bit 13 : Include or exclude channel 13 */

+#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */

+#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */

+#define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH13_Included (1UL) /*!< Include */

+

+/* Bit 12 : Include or exclude channel 12 */

+#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */

+#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */

+#define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH12_Included (1UL) /*!< Include */

+

+/* Bit 11 : Include or exclude channel 11 */

+#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */

+#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */

+#define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH11_Included (1UL) /*!< Include */

+

+/* Bit 10 : Include or exclude channel 10 */

+#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */

+#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */

+#define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH10_Included (1UL) /*!< Include */

+

+/* Bit 9 : Include or exclude channel 9 */

+#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */

+#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */

+#define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH9_Included (1UL) /*!< Include */

+

+/* Bit 8 : Include or exclude channel 8 */

+#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */

+#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */

+#define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH8_Included (1UL) /*!< Include */

+

+/* Bit 7 : Include or exclude channel 7 */

+#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */

+#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */

+#define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH7_Included (1UL) /*!< Include */

+

+/* Bit 6 : Include or exclude channel 6 */

+#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */

+#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */

+#define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH6_Included (1UL) /*!< Include */

+

+/* Bit 5 : Include or exclude channel 5 */

+#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */

+#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */

+#define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH5_Included (1UL) /*!< Include */

+

+/* Bit 4 : Include or exclude channel 4 */

+#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */

+#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */

+#define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH4_Included (1UL) /*!< Include */

+

+/* Bit 3 : Include or exclude channel 3 */

+#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */

+#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */

+#define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH3_Included (1UL) /*!< Include */

+

+/* Bit 2 : Include or exclude channel 2 */

+#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */

+#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */

+#define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH2_Included (1UL) /*!< Include */

+

+/* Bit 1 : Include or exclude channel 1 */

+#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */

+#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */

+#define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH1_Included (1UL) /*!< Include */

+

+/* Bit 0 : Include or exclude channel 0 */

+#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */

+#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */

+#define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */

+#define PPI_CHG_CH0_Included (1UL) /*!< Include */

+

+/* Register: PPI_FORK_TEP */

+/* Description: Description cluster[0]:  Channel 0 task end-point */

+

+/* Bits 31..0 : Pointer to task register */

+#define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */

+#define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */

+

+

+/* Peripheral: PWM */

+/* Description: Pulse Width Modulation Unit 0 */

+

+/* Register: PWM_SHORTS */

+/* Description: Shortcut register */

+

+/* Bit 4 : Shortcut between LOOPSDONE event and STOP task */

+#define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */

+#define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */

+#define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */

+#define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */

+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */

+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */

+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */

+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */

+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */

+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */

+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */

+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 1 : Shortcut between SEQEND[1] event and STOP task */

+#define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */

+#define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */

+#define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */

+#define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 0 : Shortcut between SEQEND[0] event and STOP task */

+#define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */

+#define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */

+#define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */

+#define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */

+

+/* Register: PWM_INTEN */

+/* Description: Enable or disable interrupt */

+

+/* Bit 7 : Enable or disable interrupt for LOOPSDONE event */

+#define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */

+#define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */

+#define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */

+#define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */

+

+/* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */

+#define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */

+#define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */

+#define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */

+#define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */

+

+/* Bit 5 : Enable or disable interrupt for SEQEND[1] event */

+#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */

+#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */

+#define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */

+#define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */

+

+/* Bit 4 : Enable or disable interrupt for SEQEND[0] event */

+#define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */

+#define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */

+#define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */

+#define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */

+

+/* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */

+#define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */

+#define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */

+#define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */

+#define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */

+

+/* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */

+#define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */

+#define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */

+#define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */

+#define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */

+

+/* Bit 1 : Enable or disable interrupt for STOPPED event */

+#define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */

+#define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */

+#define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */

+#define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */

+

+/* Register: PWM_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 7 : Write '1' to Enable interrupt for LOOPSDONE event */

+#define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */

+#define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */

+#define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */

+#define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */

+#define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */

+

+/* Bit 6 : Write '1' to Enable interrupt for PWMPERIODEND event */

+#define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */

+#define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */

+#define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */

+#define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */

+#define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */

+

+/* Bit 5 : Write '1' to Enable interrupt for SEQEND[1] event */

+#define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */

+#define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */

+#define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */

+#define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */

+#define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */

+

+/* Bit 4 : Write '1' to Enable interrupt for SEQEND[0] event */

+#define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */

+#define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */

+#define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */

+#define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */

+#define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */

+

+/* Bit 3 : Write '1' to Enable interrupt for SEQSTARTED[1] event */

+#define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */

+#define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */

+#define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */

+#define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */

+#define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */

+

+/* Bit 2 : Write '1' to Enable interrupt for SEQSTARTED[0] event */

+#define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */

+#define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */

+#define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */

+#define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */

+#define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */

+

+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */

+#define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */

+#define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */

+#define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */

+#define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */

+#define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */

+

+/* Register: PWM_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 7 : Write '1' to Disable interrupt for LOOPSDONE event */

+#define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */

+#define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */

+#define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */

+#define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */

+#define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */

+

+/* Bit 6 : Write '1' to Disable interrupt for PWMPERIODEND event */

+#define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */

+#define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */

+#define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */

+#define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */

+#define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */

+

+/* Bit 5 : Write '1' to Disable interrupt for SEQEND[1] event */

+#define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */

+#define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */

+#define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */

+#define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */

+#define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */

+

+/* Bit 4 : Write '1' to Disable interrupt for SEQEND[0] event */

+#define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */

+#define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */

+#define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */

+#define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */

+#define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */

+

+/* Bit 3 : Write '1' to Disable interrupt for SEQSTARTED[1] event */

+#define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */

+#define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */

+#define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */

+#define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */

+#define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */

+

+/* Bit 2 : Write '1' to Disable interrupt for SEQSTARTED[0] event */

+#define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */

+#define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */

+#define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */

+#define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */

+#define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */

+

+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */

+#define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */

+#define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */

+#define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */

+#define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */

+#define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */

+

+/* Register: PWM_ENABLE */

+/* Description: PWM module enable register */

+

+/* Bit 0 : Enable or disable PWM module */

+#define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */

+#define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */

+#define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */

+#define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */

+

+/* Register: PWM_MODE */

+/* Description: Selects operating mode of the wave counter */

+

+/* Bit 0 : Selects up or up and down as wave counter mode */

+#define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */

+#define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */

+#define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter - edge aligned PWM duty-cycle */

+#define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter - center aligned PWM duty cycle */

+

+/* Register: PWM_COUNTERTOP */

+/* Description: Value up to which the pulse generator counter counts */

+

+/* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used. */

+#define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */

+#define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */

+

+/* Register: PWM_PRESCALER */

+/* Description: Configuration for PWM_CLK */

+

+/* Bits 2..0 : Pre-scaler of PWM_CLK */

+#define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */

+#define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */

+#define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by   1 (16MHz) */

+#define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by   2 ( 8MHz) */

+#define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by   4 ( 4MHz) */

+#define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by   8 ( 2MHz) */

+#define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by  16 ( 1MHz) */

+#define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by  32 ( 500kHz) */

+#define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by  64 ( 250kHz) */

+#define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 ( 125kHz) */

+

+/* Register: PWM_DECODER */

+/* Description: Configuration of the decoder */

+

+/* Bit 8 : Selects source for advancing the active sequence */

+#define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */

+#define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */

+#define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */

+#define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */

+

+/* Bits 2..0 : How a sequence is read from RAM and spread to the compare register */

+#define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */

+#define PWM_DECODER_LOAD_Msk (0x7UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */

+#define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */

+#define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */

+#define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */

+#define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */

+

+/* Register: PWM_LOOP */

+/* Description: Amount of playback of a loop */

+

+/* Bits 15..0 : Amount of playback of pattern cycles */

+#define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */

+#define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */

+#define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */

+

+/* Register: PWM_SEQ_PTR */

+/* Description: Description cluster[0]:  Beginning address in Data RAM of sequence A */

+

+/* Bits 31..0 : Beginning address in Data RAM of sequence A */

+#define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */

+#define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

+

+/* Register: PWM_SEQ_CNT */

+/* Description: Description cluster[0]:  Amount of values (duty cycles) in sequence A */

+

+/* Bits 14..0 : Amount of values (duty cycles) in sequence A */

+#define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */

+#define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */

+#define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */

+

+/* Register: PWM_SEQ_REFRESH */

+/* Description: Description cluster[0]:  Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */

+

+/* Bits 23..0 : Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */

+#define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */

+#define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */

+#define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */

+

+/* Register: PWM_SEQ_ENDDELAY */

+/* Description: Description cluster[0]:  Time added after the sequence */

+

+/* Bits 23..0 : Time added after the sequence in PWM periods */

+#define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */

+#define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */

+

+/* Register: PWM_PSEL_OUT */

+/* Description: Description collection[0]:  Output pin select for PWM channel 0 */

+

+/* Bit 31 : Connection */

+#define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */

+#define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */

+#define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */

+#define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */

+

+/* Bits 4..0 : Pin number */

+#define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */

+#define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */

+

+

+/* Peripheral: QDEC */

+/* Description: Quadrature Decoder */

+

+/* Register: QDEC_SHORTS */

+/* Description: Shortcut register */

+

+/* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */

+#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */

+#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */

+#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */

+#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 5 : Shortcut between DBLRDY event and STOP task */

+#define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */

+#define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */

+#define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */

+#define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */

+#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */

+#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */

+#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */

+#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 3 : Shortcut between REPORTRDY event and STOP task */

+#define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */

+#define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */

+#define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */

+#define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */

+#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */

+#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */

+#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */

+#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 1 : Shortcut between SAMPLERDY event and STOP task */

+#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */

+#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */

+#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */

+#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */

+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */

+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */

+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */

+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */

+

+/* Register: QDEC_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 4 : Write '1' to Enable interrupt for STOPPED event */

+#define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */

+#define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */

+#define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */

+#define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */

+#define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */

+

+/* Bit 3 : Write '1' to Enable interrupt for DBLRDY event */

+#define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */

+#define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */

+#define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */

+#define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */

+#define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */

+

+/* Bit 2 : Write '1' to Enable interrupt for ACCOF event */

+#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */

+#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */

+#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */

+#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */

+#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */

+

+/* Bit 1 : Write '1' to Enable interrupt for REPORTRDY event */

+#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */

+#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */

+#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */

+#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */

+#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */

+

+/* Bit 0 : Write '1' to Enable interrupt for SAMPLERDY event */

+#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */

+#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */

+#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */

+#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */

+#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */

+

+/* Register: QDEC_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 4 : Write '1' to Disable interrupt for STOPPED event */

+#define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */

+#define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */

+#define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */

+#define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */

+#define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */

+

+/* Bit 3 : Write '1' to Disable interrupt for DBLRDY event */

+#define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */

+#define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */

+#define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */

+#define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */

+#define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */

+

+/* Bit 2 : Write '1' to Disable interrupt for ACCOF event */

+#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */

+#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */

+#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */

+#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */

+#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */

+

+/* Bit 1 : Write '1' to Disable interrupt for REPORTRDY event */

+#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */

+#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */

+#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */

+#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */

+#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */

+

+/* Bit 0 : Write '1' to Disable interrupt for SAMPLERDY event */

+#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */

+#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */

+#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */

+#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */

+#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */

+

+/* Register: QDEC_ENABLE */

+/* Description: Enable the quadrature decoder */

+

+/* Bit 0 : Enable or disable the quadrature decoder */

+#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */

+#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */

+#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */

+#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */

+

+/* Register: QDEC_LEDPOL */

+/* Description: LED output pin polarity */

+

+/* Bit 0 : LED output pin polarity */

+#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */

+#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */

+#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */

+#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */

+

+/* Register: QDEC_SAMPLEPER */

+/* Description: Sample period */

+

+/* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */

+#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */

+#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */

+#define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */

+#define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */

+#define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */

+#define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */

+#define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */

+#define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */

+#define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */

+#define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */

+#define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */

+#define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */

+#define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */

+

+/* Register: QDEC_SAMPLE */

+/* Description: Motion sample value */

+

+/* Bits 31..0 : Last motion sample */

+#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */

+#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */

+

+/* Register: QDEC_REPORTPER */

+/* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */

+

+/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */

+#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */

+#define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */

+#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */

+#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */

+#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */

+#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */

+#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */

+#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */

+#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */

+#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */

+#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */

+

+/* Register: QDEC_ACC */

+/* Description: Register accumulating the valid transitions */

+

+/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */

+#define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */

+#define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */

+

+/* Register: QDEC_ACCREAD */

+/* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */

+

+/* Bits 31..0 : Snapshot of the ACC register. */

+#define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */

+#define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */

+

+/* Register: QDEC_PSEL_LED */

+/* Description: Pin select for LED signal */

+

+/* Bit 31 : Connection */

+#define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */

+#define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */

+#define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */

+#define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */

+

+/* Bits 4..0 : Pin number */

+#define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */

+#define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */

+

+/* Register: QDEC_PSEL_A */

+/* Description: Pin select for A signal */

+

+/* Bit 31 : Connection */

+#define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */

+#define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */

+#define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */

+#define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */

+

+/* Bits 4..0 : Pin number */

+#define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */

+#define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */

+

+/* Register: QDEC_PSEL_B */

+/* Description: Pin select for B signal */

+

+/* Bit 31 : Connection */

+#define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */

+#define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */

+#define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */

+#define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */

+

+/* Bits 4..0 : Pin number */

+#define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */

+#define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */

+

+/* Register: QDEC_DBFEN */

+/* Description: Enable input debounce filters */

+

+/* Bit 0 : Enable input debounce filters */

+#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */

+#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */

+#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */

+#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */

+

+/* Register: QDEC_LEDPRE */

+/* Description: Time period the LED is switched ON prior to sampling */

+

+/* Bits 8..0 : Period in us the LED is switched on prior to sampling */

+#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */

+#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */

+

+/* Register: QDEC_ACCDBL */

+/* Description: Register accumulating the number of detected double transitions */

+

+/* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */

+#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */

+#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */

+

+/* Register: QDEC_ACCDBLREAD */

+/* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */

+

+/* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */

+#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */

+#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */

+

+

+/* Peripheral: RADIO */

+/* Description: 2.4 GHz Radio */

+

+/* Register: RADIO_SHORTS */

+/* Description: Shortcut register */

+

+/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */

+#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */

+#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */

+#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */

+#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 6 : Shortcut between ADDRESS event and BCSTART task */

+#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */

+#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */

+#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */

+#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 5 : Shortcut between END event and START task */

+#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */

+#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */

+#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */

+#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */

+#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */

+#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */

+#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */

+#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 3 : Shortcut between DISABLED event and RXEN task */

+#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */

+#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */

+#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */

+#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 2 : Shortcut between DISABLED event and TXEN task */

+#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */

+#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */

+#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */

+#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 1 : Shortcut between END event and DISABLE task */

+#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */

+#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */

+#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */

+#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 0 : Shortcut between READY event and START task */

+#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */

+#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */

+#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */

+#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */

+

+/* Register: RADIO_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 13 : Write '1' to Enable interrupt for CRCERROR event */

+#define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */

+#define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */

+#define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */

+#define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */

+#define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */

+

+/* Bit 12 : Write '1' to Enable interrupt for CRCOK event */

+#define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */

+#define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */

+#define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */

+#define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */

+#define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */

+

+/* Bit 10 : Write '1' to Enable interrupt for BCMATCH event */

+#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */

+#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */

+#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */

+#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */

+#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */

+

+/* Bit 7 : Write '1' to Enable interrupt for RSSIEND event */

+#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */

+#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */

+#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */

+#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */

+#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */

+

+/* Bit 6 : Write '1' to Enable interrupt for DEVMISS event */

+#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */

+#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */

+#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */

+#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */

+#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */

+

+/* Bit 5 : Write '1' to Enable interrupt for DEVMATCH event */

+#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */

+#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */

+#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */

+#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */

+#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */

+

+/* Bit 4 : Write '1' to Enable interrupt for DISABLED event */

+#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */

+#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */

+#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */

+#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */

+#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */

+

+/* Bit 3 : Write '1' to Enable interrupt for END event */

+#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */

+#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */

+#define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */

+#define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */

+#define RADIO_INTENSET_END_Set (1UL) /*!< Enable */

+

+/* Bit 2 : Write '1' to Enable interrupt for PAYLOAD event */

+#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */

+#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */

+#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */

+#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */

+#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */

+

+/* Bit 1 : Write '1' to Enable interrupt for ADDRESS event */

+#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */

+#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */

+#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */

+#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */

+#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */

+

+/* Bit 0 : Write '1' to Enable interrupt for READY event */

+#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */

+#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */

+#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */

+#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */

+#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */

+

+/* Register: RADIO_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 13 : Write '1' to Disable interrupt for CRCERROR event */

+#define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */

+#define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */

+#define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */

+#define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */

+#define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */

+

+/* Bit 12 : Write '1' to Disable interrupt for CRCOK event */

+#define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */

+#define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */

+#define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */

+#define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */

+#define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */

+

+/* Bit 10 : Write '1' to Disable interrupt for BCMATCH event */

+#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */

+#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */

+#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */

+#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */

+#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */

+

+/* Bit 7 : Write '1' to Disable interrupt for RSSIEND event */

+#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */

+#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */

+#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */

+#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */

+#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */

+

+/* Bit 6 : Write '1' to Disable interrupt for DEVMISS event */

+#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */

+#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */

+#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */

+#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */

+#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */

+

+/* Bit 5 : Write '1' to Disable interrupt for DEVMATCH event */

+#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */

+#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */

+#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */

+#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */

+#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */

+

+/* Bit 4 : Write '1' to Disable interrupt for DISABLED event */

+#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */

+#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */

+#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */

+#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */

+#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */

+

+/* Bit 3 : Write '1' to Disable interrupt for END event */

+#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */

+#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */

+#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */

+#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */

+#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */

+

+/* Bit 2 : Write '1' to Disable interrupt for PAYLOAD event */

+#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */

+#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */

+#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */

+#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */

+#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */

+

+/* Bit 1 : Write '1' to Disable interrupt for ADDRESS event */

+#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */

+#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */

+#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */

+#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */

+#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */

+

+/* Bit 0 : Write '1' to Disable interrupt for READY event */

+#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */

+#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */

+#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */

+#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */

+#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */

+

+/* Register: RADIO_CRCSTATUS */

+/* Description: CRC status */

+

+/* Bit 0 : CRC status of packet received */

+#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */

+#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */

+#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */

+#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */

+

+/* Register: RADIO_RXMATCH */

+/* Description: Received address */

+

+/* Bits 2..0 : Received address */

+#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */

+#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */

+

+/* Register: RADIO_RXCRC */

+/* Description: CRC field of previously received packet */

+

+/* Bits 23..0 : CRC field of previously received packet */

+#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */

+#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */

+

+/* Register: RADIO_DAI */

+/* Description: Device address match index */

+

+/* Bits 2..0 : Device address match index */

+#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */

+#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */

+

+/* Register: RADIO_PACKETPTR */

+/* Description: Packet pointer */

+

+/* Bits 31..0 : Packet pointer */

+#define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */

+#define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */

+

+/* Register: RADIO_FREQUENCY */

+/* Description: Frequency */

+

+/* Bit 8 : Channel map selection. */

+#define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */

+#define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */

+#define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */

+#define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */

+

+/* Bits 6..0 : Radio channel frequency */

+#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */

+#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */

+

+/* Register: RADIO_TXPOWER */

+/* Description: Output power */

+

+/* Bits 7..0 : RADIO output power. */

+#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */

+#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */

+#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0 dBm */

+#define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL) /*!< +3 dBm */

+#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4 dBm */

+#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< Deprecated enumerator -  -40 dBm */

+#define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */

+#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */

+#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */

+#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */

+#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */

+#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */

+

+/* Register: RADIO_MODE */

+/* Description: Data rate and modulation */

+

+/* Bits 3..0 : Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. */

+#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */

+#define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */

+#define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */

+#define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */

+#define RADIO_MODE_MODE_Nrf_250Kbit (2UL) /*!< Deprecated enumerator -  250 kbit/s Nordic proprietary radio mode */

+#define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */

+

+/* Register: RADIO_PCNF0 */

+/* Description: Packet configuration register 0 */

+

+/* Bit 24 : Length of preamble on air. Decision point: TASKS_START task */

+#define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */

+#define RADIO_PCNF0_PLEN_Msk (0x1UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */

+#define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */

+#define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */

+

+/* Bit 20 : Include or exclude S1 field in RAM */

+#define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */

+#define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */

+#define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN &gt; 0 */

+#define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */

+

+/* Bits 19..16 : Length on air of S1 field in number of bits. */

+#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */

+#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */

+

+/* Bit 8 : Length on air of S0 field in number of bytes. */

+#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */

+#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */

+

+/* Bits 3..0 : Length on air of LENGTH field in number of bits. */

+#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */

+#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */

+

+/* Register: RADIO_PCNF1 */

+/* Description: Packet configuration register 1 */

+

+/* Bit 25 : Enable or disable packet whitening */

+#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */

+#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */

+#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */

+#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */

+

+/* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */

+#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */

+#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */

+#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least Significant bit on air first */

+#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */

+

+/* Bits 18..16 : Base address length in number of bytes */

+#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */

+#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */

+

+/* Bits 15..8 : Static length in number of bytes */

+#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */

+#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */

+

+/* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */

+#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */

+#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */

+

+/* Register: RADIO_BASE0 */

+/* Description: Base address 0 */

+

+/* Bits 31..0 : Base address 0 */

+#define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */

+#define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */

+

+/* Register: RADIO_BASE1 */

+/* Description: Base address 1 */

+

+/* Bits 31..0 : Base address 1 */

+#define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */

+#define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */

+

+/* Register: RADIO_PREFIX0 */

+/* Description: Prefixes bytes for logical addresses 0-3 */

+

+/* Bits 31..24 : Address prefix 3. */

+#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */

+#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */

+

+/* Bits 23..16 : Address prefix 2. */

+#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */

+#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */

+

+/* Bits 15..8 : Address prefix 1. */

+#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */

+#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */

+

+/* Bits 7..0 : Address prefix 0. */

+#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */

+#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */

+

+/* Register: RADIO_PREFIX1 */

+/* Description: Prefixes bytes for logical addresses 4-7 */

+

+/* Bits 31..24 : Address prefix 7. */

+#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */

+#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */

+

+/* Bits 23..16 : Address prefix 6. */

+#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */

+#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */

+

+/* Bits 15..8 : Address prefix 5. */

+#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */

+#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */

+

+/* Bits 7..0 : Address prefix 4. */

+#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */

+#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */

+

+/* Register: RADIO_TXADDRESS */

+/* Description: Transmit address select */

+

+/* Bits 2..0 : Transmit address select */

+#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */

+#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */

+

+/* Register: RADIO_RXADDRESSES */

+/* Description: Receive address select */

+

+/* Bit 7 : Enable or disable reception on logical address 7. */

+#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */

+#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */

+#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */

+#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */

+

+/* Bit 6 : Enable or disable reception on logical address 6. */

+#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */

+#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */

+#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */

+#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */

+

+/* Bit 5 : Enable or disable reception on logical address 5. */

+#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */

+#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */

+#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */

+#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */

+

+/* Bit 4 : Enable or disable reception on logical address 4. */

+#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */

+#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */

+#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */

+#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */

+

+/* Bit 3 : Enable or disable reception on logical address 3. */

+#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */

+#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */

+#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */

+#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */

+

+/* Bit 2 : Enable or disable reception on logical address 2. */

+#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */

+#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */

+#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */

+#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */

+

+/* Bit 1 : Enable or disable reception on logical address 1. */

+#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */

+#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */

+#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */

+#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */

+

+/* Bit 0 : Enable or disable reception on logical address 0. */

+#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */

+#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */

+#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */

+#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */

+

+/* Register: RADIO_CRCCNF */

+/* Description: CRC configuration */

+

+/* Bit 8 : Include or exclude packet address field out of CRC calculation. */

+#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */

+#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */

+#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */

+#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */

+

+/* Bits 1..0 : CRC length in number of bytes. */

+#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */

+#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */

+#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */

+#define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */

+#define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */

+#define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */

+

+/* Register: RADIO_CRCPOLY */

+/* Description: CRC polynomial */

+

+/* Bits 23..0 : CRC polynomial */

+#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */

+#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */

+

+/* Register: RADIO_CRCINIT */

+/* Description: CRC initial value */

+

+/* Bits 23..0 : CRC initial value */

+#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */

+#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */

+

+/* Register: RADIO_TIFS */

+/* Description: Inter Frame Spacing in us */

+

+/* Bits 7..0 : Inter Frame Spacing in us */

+#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */

+#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */

+

+/* Register: RADIO_RSSISAMPLE */

+/* Description: RSSI sample */

+

+/* Bits 6..0 : RSSI sample */

+#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */

+#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */

+

+/* Register: RADIO_STATE */

+/* Description: Current radio state */

+

+/* Bits 3..0 : Current radio state */

+#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */

+#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */

+#define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */

+#define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */

+#define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */

+#define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */

+#define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */

+#define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */

+#define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */

+#define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */

+#define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */

+

+/* Register: RADIO_DATAWHITEIV */

+/* Description: Data whitening initial value */

+

+/* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */

+#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */

+#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */

+

+/* Register: RADIO_BCC */

+/* Description: Bit counter compare */

+

+/* Bits 31..0 : Bit counter compare */

+#define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */

+#define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */

+

+/* Register: RADIO_DAB */

+/* Description: Description collection[0]:  Device address base segment 0 */

+

+/* Bits 31..0 : Device address base segment 0 */

+#define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */

+#define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */

+

+/* Register: RADIO_DAP */

+/* Description: Description collection[0]:  Device address prefix 0 */

+

+/* Bits 15..0 : Device address prefix 0 */

+#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */

+#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */

+

+/* Register: RADIO_DACNF */

+/* Description: Device address match configuration */

+

+/* Bit 15 : TxAdd for device address 7 */

+#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */

+#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */

+

+/* Bit 14 : TxAdd for device address 6 */

+#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */

+#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */

+

+/* Bit 13 : TxAdd for device address 5 */

+#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */

+#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */

+

+/* Bit 12 : TxAdd for device address 4 */

+#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */

+#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */

+

+/* Bit 11 : TxAdd for device address 3 */

+#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */

+#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */

+

+/* Bit 10 : TxAdd for device address 2 */

+#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */

+#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */

+

+/* Bit 9 : TxAdd for device address 1 */

+#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */

+#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */

+

+/* Bit 8 : TxAdd for device address 0 */

+#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */

+#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */

+

+/* Bit 7 : Enable or disable device address matching using device address 7 */

+#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */

+#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */

+#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */

+#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */

+

+/* Bit 6 : Enable or disable device address matching using device address 6 */

+#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */

+#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */

+#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */

+#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */

+

+/* Bit 5 : Enable or disable device address matching using device address 5 */

+#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */

+#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */

+#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */

+#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */

+

+/* Bit 4 : Enable or disable device address matching using device address 4 */

+#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */

+#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */

+#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */

+#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */

+

+/* Bit 3 : Enable or disable device address matching using device address 3 */

+#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */

+#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */

+#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */

+#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */

+

+/* Bit 2 : Enable or disable device address matching using device address 2 */

+#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */

+#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */

+#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */

+#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */

+

+/* Bit 1 : Enable or disable device address matching using device address 1 */

+#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */

+#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */

+#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */

+#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */

+

+/* Bit 0 : Enable or disable device address matching using device address 0 */

+#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */

+#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */

+#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */

+#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */

+

+/* Register: RADIO_MODECNF0 */

+/* Description: Radio mode configuration register 0 */

+

+/* Bits 9..8 : Default TX value */

+#define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */

+#define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */

+#define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */

+#define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */

+#define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */

+

+/* Bit 0 : Radio ramp-up time */

+#define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */

+#define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */

+#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */

+#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */

+

+/* Register: RADIO_POWER */

+/* Description: Peripheral power control */

+

+/* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */

+#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */

+#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */

+#define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */

+#define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */

+

+

+/* Peripheral: RNG */

+/* Description: Random Number Generator */

+

+/* Register: RNG_SHORTS */

+/* Description: Shortcut register */

+

+/* Bit 0 : Shortcut between VALRDY event and STOP task */

+#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */

+#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */

+#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */

+#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */

+

+/* Register: RNG_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 0 : Write '1' to Enable interrupt for VALRDY event */

+#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */

+#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */

+#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */

+#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */

+#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */

+

+/* Register: RNG_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 0 : Write '1' to Disable interrupt for VALRDY event */

+#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */

+#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */

+#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */

+#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */

+#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */

+

+/* Register: RNG_CONFIG */

+/* Description: Configuration register */

+

+/* Bit 0 : Bias correction */

+#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */

+#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */

+#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */

+#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */

+

+/* Register: RNG_VALUE */

+/* Description: Output random number */

+

+/* Bits 7..0 : Generated random number */

+#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */

+#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */

+

+

+/* Peripheral: RTC */

+/* Description: Real time counter 0 */

+

+/* Register: RTC_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */

+#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */

+#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */

+#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */

+#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */

+#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */

+

+/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */

+#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */

+#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */

+#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */

+#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */

+#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */

+

+/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */

+#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */

+#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */

+#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */

+#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */

+#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */

+

+/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */

+#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */

+#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */

+#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */

+#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */

+#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */

+

+/* Bit 1 : Write '1' to Enable interrupt for OVRFLW event */

+#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */

+#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */

+#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */

+#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */

+#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */

+

+/* Bit 0 : Write '1' to Enable interrupt for TICK event */

+#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */

+#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */

+#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */

+#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */

+#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */

+

+/* Register: RTC_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */

+#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */

+#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */

+#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */

+#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */

+#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */

+

+/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */

+#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */

+#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */

+#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */

+#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */

+#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */

+

+/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */

+#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */

+#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */

+#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */

+#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */

+#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */

+

+/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */

+#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */

+#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */

+#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */

+#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */

+#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */

+

+/* Bit 1 : Write '1' to Disable interrupt for OVRFLW event */

+#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */

+#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */

+#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */

+#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */

+#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */

+

+/* Bit 0 : Write '1' to Disable interrupt for TICK event */

+#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */

+#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */

+#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */

+#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */

+#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */

+

+/* Register: RTC_EVTEN */

+/* Description: Enable or disable event routing */

+

+/* Bit 19 : Enable or disable event routing for COMPARE[3] event */

+#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */

+#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */

+#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */

+#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */

+

+/* Bit 18 : Enable or disable event routing for COMPARE[2] event */

+#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */

+#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */

+#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */

+#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */

+

+/* Bit 17 : Enable or disable event routing for COMPARE[1] event */

+#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */

+#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */

+#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */

+#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */

+

+/* Bit 16 : Enable or disable event routing for COMPARE[0] event */

+#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */

+#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */

+#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */

+#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */

+

+/* Bit 1 : Enable or disable event routing for OVRFLW event */

+#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */

+#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */

+#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */

+#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */

+

+/* Bit 0 : Enable or disable event routing for TICK event */

+#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */

+#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */

+#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */

+#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */

+

+/* Register: RTC_EVTENSET */

+/* Description: Enable event routing */

+

+/* Bit 19 : Write '1' to Enable event routing for COMPARE[3] event */

+#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */

+#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */

+#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */

+#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */

+#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */

+

+/* Bit 18 : Write '1' to Enable event routing for COMPARE[2] event */

+#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */

+#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */

+#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */

+#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */

+#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */

+

+/* Bit 17 : Write '1' to Enable event routing for COMPARE[1] event */

+#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */

+#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */

+#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */

+#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */

+#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */

+

+/* Bit 16 : Write '1' to Enable event routing for COMPARE[0] event */

+#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */

+#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */

+#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */

+#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */

+#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */

+

+/* Bit 1 : Write '1' to Enable event routing for OVRFLW event */

+#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */

+#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */

+#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */

+#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */

+#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */

+

+/* Bit 0 : Write '1' to Enable event routing for TICK event */

+#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */

+#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */

+#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */

+#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */

+#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */

+

+/* Register: RTC_EVTENCLR */

+/* Description: Disable event routing */

+

+/* Bit 19 : Write '1' to Disable event routing for COMPARE[3] event */

+#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */

+#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */

+#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */

+#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */

+#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */

+

+/* Bit 18 : Write '1' to Disable event routing for COMPARE[2] event */

+#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */

+#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */

+#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */

+#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */

+#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */

+

+/* Bit 17 : Write '1' to Disable event routing for COMPARE[1] event */

+#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */

+#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */

+#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */

+#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */

+#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */

+

+/* Bit 16 : Write '1' to Disable event routing for COMPARE[0] event */

+#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */

+#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */

+#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */

+#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */

+#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */

+

+/* Bit 1 : Write '1' to Disable event routing for OVRFLW event */

+#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */

+#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */

+#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */

+#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */

+#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */

+

+/* Bit 0 : Write '1' to Disable event routing for TICK event */

+#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */

+#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */

+#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */

+#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */

+#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */

+

+/* Register: RTC_COUNTER */

+/* Description: Current COUNTER value */

+

+/* Bits 23..0 : Counter value */

+#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */

+#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */

+

+/* Register: RTC_PRESCALER */

+/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */

+

+/* Bits 11..0 : Prescaler value */

+#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */

+#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */

+

+/* Register: RTC_CC */

+/* Description: Description collection[0]:  Compare register 0 */

+

+/* Bits 23..0 : Compare value */

+#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */

+#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */

+

+

+/* Peripheral: SAADC */

+/* Description: Analog to Digital Converter */

+

+/* Register: SAADC_INTEN */

+/* Description: Enable or disable interrupt */

+

+/* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */

+#define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */

+#define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */

+#define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */

+#define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */

+

+/* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */

+#define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */

+#define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */

+#define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */

+#define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */

+

+/* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */

+#define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */

+#define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */

+#define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */

+#define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */

+

+/* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */

+#define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */

+#define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */

+#define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */

+#define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */

+

+/* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */

+#define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */

+#define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */

+#define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */

+#define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */

+

+/* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */

+#define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */

+#define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */

+#define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */

+#define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */

+

+/* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */

+#define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */

+#define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */

+#define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */

+#define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */

+

+/* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */

+#define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */

+#define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */

+#define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */

+#define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */

+

+/* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */

+#define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */

+#define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */

+#define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */

+#define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */

+

+/* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */

+#define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */

+#define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */

+#define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */

+#define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */

+

+/* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */

+#define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */

+#define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */

+#define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */

+#define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */

+

+/* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */

+#define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */

+#define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */

+#define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */

+#define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */

+

+/* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */

+#define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */

+#define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */

+#define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */

+#define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */

+

+/* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */

+#define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */

+#define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */

+#define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */

+#define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */

+

+/* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */

+#define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */

+#define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */

+#define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */

+#define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */

+

+/* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */

+#define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */

+#define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */

+#define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */

+#define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */

+

+/* Bit 5 : Enable or disable interrupt for STOPPED event */

+#define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */

+#define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */

+#define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */

+#define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */

+

+/* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */

+#define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */

+#define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */

+#define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */

+#define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */

+

+/* Bit 3 : Enable or disable interrupt for RESULTDONE event */

+#define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */

+#define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */

+#define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */

+#define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */

+

+/* Bit 2 : Enable or disable interrupt for DONE event */

+#define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */

+#define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */

+#define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */

+#define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */

+

+/* Bit 1 : Enable or disable interrupt for END event */

+#define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */

+#define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */

+#define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */

+#define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */

+

+/* Bit 0 : Enable or disable interrupt for STARTED event */

+#define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */

+#define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */

+#define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */

+#define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */

+

+/* Register: SAADC_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 21 : Write '1' to Enable interrupt for CH[7].LIMITL event */

+#define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */

+#define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */

+#define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */

+

+/* Bit 20 : Write '1' to Enable interrupt for CH[7].LIMITH event */

+#define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */

+#define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */

+#define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */

+

+/* Bit 19 : Write '1' to Enable interrupt for CH[6].LIMITL event */

+#define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */

+#define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */

+#define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */

+

+/* Bit 18 : Write '1' to Enable interrupt for CH[6].LIMITH event */

+#define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */

+#define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */

+#define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */

+

+/* Bit 17 : Write '1' to Enable interrupt for CH[5].LIMITL event */

+#define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */

+#define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */

+#define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */

+

+/* Bit 16 : Write '1' to Enable interrupt for CH[5].LIMITH event */

+#define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */

+#define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */

+#define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */

+

+/* Bit 15 : Write '1' to Enable interrupt for CH[4].LIMITL event */

+#define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */

+#define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */

+#define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */

+

+/* Bit 14 : Write '1' to Enable interrupt for CH[4].LIMITH event */

+#define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */

+#define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */

+#define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */

+

+/* Bit 13 : Write '1' to Enable interrupt for CH[3].LIMITL event */

+#define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */

+#define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */

+#define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */

+

+/* Bit 12 : Write '1' to Enable interrupt for CH[3].LIMITH event */

+#define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */

+#define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */

+#define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */

+

+/* Bit 11 : Write '1' to Enable interrupt for CH[2].LIMITL event */

+#define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */

+#define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */

+#define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */

+

+/* Bit 10 : Write '1' to Enable interrupt for CH[2].LIMITH event */

+#define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */

+#define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */

+#define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */

+

+/* Bit 9 : Write '1' to Enable interrupt for CH[1].LIMITL event */

+#define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */

+#define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */

+#define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */

+

+/* Bit 8 : Write '1' to Enable interrupt for CH[1].LIMITH event */

+#define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */

+#define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */

+#define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */

+

+/* Bit 7 : Write '1' to Enable interrupt for CH[0].LIMITL event */

+#define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */

+#define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */

+#define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */

+

+/* Bit 6 : Write '1' to Enable interrupt for CH[0].LIMITH event */

+#define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */

+#define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */

+#define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */

+

+/* Bit 5 : Write '1' to Enable interrupt for STOPPED event */

+#define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */

+#define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */

+#define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */

+

+/* Bit 4 : Write '1' to Enable interrupt for CALIBRATEDONE event */

+#define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */

+#define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */

+#define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */

+

+/* Bit 3 : Write '1' to Enable interrupt for RESULTDONE event */

+#define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */

+#define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */

+#define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */

+

+/* Bit 2 : Write '1' to Enable interrupt for DONE event */

+#define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */

+#define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */

+#define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */

+

+/* Bit 1 : Write '1' to Enable interrupt for END event */

+#define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */

+#define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */

+#define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENSET_END_Set (1UL) /*!< Enable */

+

+/* Bit 0 : Write '1' to Enable interrupt for STARTED event */

+#define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */

+#define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */

+#define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */

+

+/* Register: SAADC_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 21 : Write '1' to Disable interrupt for CH[7].LIMITL event */

+#define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */

+#define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */

+#define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */

+

+/* Bit 20 : Write '1' to Disable interrupt for CH[7].LIMITH event */

+#define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */

+#define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */

+#define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */

+

+/* Bit 19 : Write '1' to Disable interrupt for CH[6].LIMITL event */

+#define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */

+#define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */

+#define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */

+

+/* Bit 18 : Write '1' to Disable interrupt for CH[6].LIMITH event */

+#define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */

+#define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */

+#define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */

+

+/* Bit 17 : Write '1' to Disable interrupt for CH[5].LIMITL event */

+#define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */

+#define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */

+#define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */

+

+/* Bit 16 : Write '1' to Disable interrupt for CH[5].LIMITH event */

+#define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */

+#define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */

+#define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */

+

+/* Bit 15 : Write '1' to Disable interrupt for CH[4].LIMITL event */

+#define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */

+#define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */

+#define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */

+

+/* Bit 14 : Write '1' to Disable interrupt for CH[4].LIMITH event */

+#define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */

+#define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */

+#define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */

+

+/* Bit 13 : Write '1' to Disable interrupt for CH[3].LIMITL event */

+#define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */

+#define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */

+#define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */

+

+/* Bit 12 : Write '1' to Disable interrupt for CH[3].LIMITH event */

+#define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */

+#define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */

+#define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */

+

+/* Bit 11 : Write '1' to Disable interrupt for CH[2].LIMITL event */

+#define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */

+#define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */

+#define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */

+

+/* Bit 10 : Write '1' to Disable interrupt for CH[2].LIMITH event */

+#define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */

+#define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */

+#define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */

+

+/* Bit 9 : Write '1' to Disable interrupt for CH[1].LIMITL event */

+#define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */

+#define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */

+#define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */

+

+/* Bit 8 : Write '1' to Disable interrupt for CH[1].LIMITH event */

+#define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */

+#define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */

+#define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */

+

+/* Bit 7 : Write '1' to Disable interrupt for CH[0].LIMITL event */

+#define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */

+#define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */

+#define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */

+

+/* Bit 6 : Write '1' to Disable interrupt for CH[0].LIMITH event */

+#define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */

+#define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */

+#define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */

+

+/* Bit 5 : Write '1' to Disable interrupt for STOPPED event */

+#define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */

+#define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */

+#define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */

+

+/* Bit 4 : Write '1' to Disable interrupt for CALIBRATEDONE event */

+#define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */

+#define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */

+#define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */

+

+/* Bit 3 : Write '1' to Disable interrupt for RESULTDONE event */

+#define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */

+#define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */

+#define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */

+

+/* Bit 2 : Write '1' to Disable interrupt for DONE event */

+#define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */

+#define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */

+#define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */

+

+/* Bit 1 : Write '1' to Disable interrupt for END event */

+#define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */

+#define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */

+#define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */

+

+/* Bit 0 : Write '1' to Disable interrupt for STARTED event */

+#define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */

+#define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */

+#define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */

+#define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */

+#define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */

+

+/* Register: SAADC_STATUS */

+/* Description: Status */

+

+/* Bit 0 : Status */

+#define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */

+#define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */

+#define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */

+#define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */

+

+/* Register: SAADC_ENABLE */

+/* Description: Enable or disable ADC */

+

+/* Bit 0 : Enable or disable ADC */

+#define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */

+#define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */

+#define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */

+#define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */

+

+/* Register: SAADC_CH_PSELP */

+/* Description: Description cluster[0]:  Input positive pin selection for CH[0] */

+

+/* Bits 4..0 : Analog positive input channel */

+#define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */

+#define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */

+#define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */

+#define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */

+#define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */

+#define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */

+#define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */

+#define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */

+#define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */

+#define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */

+#define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */

+#define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */

+

+/* Register: SAADC_CH_PSELN */

+/* Description: Description cluster[0]:  Input negative pin selection for CH[0] */

+

+/* Bits 4..0 : Analog negative input, enables differential channel */

+#define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */

+#define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */

+#define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */

+#define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */

+#define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */

+#define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */

+#define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */

+#define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */

+#define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */

+#define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */

+#define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */

+#define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */

+

+/* Register: SAADC_CH_CONFIG */

+/* Description: Description cluster[0]:  Input configuration for CH[0] */

+

+/* Bit 24 : Enable burst mode */

+#define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */

+#define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */

+#define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */

+#define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */

+

+/* Bit 20 : Enable differential mode */

+#define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */

+#define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */

+#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */

+#define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */

+

+/* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */

+#define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */

+#define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */

+#define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */

+#define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */

+#define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */

+#define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */

+#define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */

+#define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */

+

+/* Bit 12 : Reference control */

+#define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */

+#define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */

+#define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */

+#define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */

+

+/* Bits 10..8 : Gain control */

+#define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */

+#define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */

+#define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */

+#define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */

+#define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */

+#define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */

+#define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */

+#define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */

+#define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */

+#define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */

+

+/* Bits 5..4 : Negative channel resistor control */

+#define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */

+#define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */

+#define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */

+#define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */

+#define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */

+#define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */

+

+/* Bits 1..0 : Positive channel resistor control */

+#define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */

+#define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */

+#define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */

+#define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */

+#define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */

+#define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */

+

+/* Register: SAADC_CH_LIMIT */

+/* Description: Description cluster[0]:  High/low limits for event monitoring a channel */

+

+/* Bits 31..16 : High level limit */

+#define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */

+#define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */

+

+/* Bits 15..0 : Low level limit */

+#define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */

+#define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */

+

+/* Register: SAADC_RESOLUTION */

+/* Description: Resolution configuration */

+

+/* Bits 2..0 : Set the resolution */

+#define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */

+#define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */

+#define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */

+#define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */

+#define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */

+#define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */

+

+/* Register: SAADC_OVERSAMPLE */

+/* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */

+

+/* Bits 3..0 : Oversample control */

+#define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */

+#define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */

+#define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */

+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */

+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */

+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */

+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */

+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */

+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */

+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */

+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */

+

+/* Register: SAADC_SAMPLERATE */

+/* Description: Controls normal or continuous sample rate */

+

+/* Bit 12 : Select mode for sample rate control */

+#define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */

+#define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */

+#define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */

+#define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */

+

+/* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */

+#define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */

+#define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */

+

+/* Register: SAADC_RESULT_PTR */

+/* Description: Data pointer */

+

+/* Bits 31..0 : Data pointer */

+#define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */

+#define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

+

+/* Register: SAADC_RESULT_MAXCNT */

+/* Description: Maximum number of buffer words to transfer */

+

+/* Bits 14..0 : Maximum number of buffer words to transfer */

+#define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */

+#define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

+

+/* Register: SAADC_RESULT_AMOUNT */

+/* Description: Number of buffer words transferred since last START */

+

+/* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */

+#define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */

+#define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */

+

+

+/* Peripheral: SPI */

+/* Description: Serial Peripheral Interface 0 */

+

+/* Register: SPI_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 2 : Write '1' to Enable interrupt for READY event */

+#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */

+#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */

+#define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */

+#define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */

+#define SPI_INTENSET_READY_Set (1UL) /*!< Enable */

+

+/* Register: SPI_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 2 : Write '1' to Disable interrupt for READY event */

+#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */

+#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */

+#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */

+#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */

+#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */

+

+/* Register: SPI_ENABLE */

+/* Description: Enable SPI */

+

+/* Bits 3..0 : Enable or disable SPI */

+#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */

+#define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */

+#define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */

+#define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */

+

+/* Register: SPI_PSEL_SCK */

+/* Description: Pin select for SCK */

+

+/* Bits 31..0 : Pin number configuration for SPI SCK signal */

+#define SPI_PSEL_SCK_PSELSCK_Pos (0UL) /*!< Position of PSELSCK field. */

+#define SPI_PSEL_SCK_PSELSCK_Msk (0xFFFFFFFFUL << SPI_PSEL_SCK_PSELSCK_Pos) /*!< Bit mask of PSELSCK field. */

+#define SPI_PSEL_SCK_PSELSCK_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */

+

+/* Register: SPI_PSEL_MOSI */

+/* Description: Pin select for MOSI */

+

+/* Bits 31..0 : Pin number configuration for SPI MOSI signal */

+#define SPI_PSEL_MOSI_PSELMOSI_Pos (0UL) /*!< Position of PSELMOSI field. */

+#define SPI_PSEL_MOSI_PSELMOSI_Msk (0xFFFFFFFFUL << SPI_PSEL_MOSI_PSELMOSI_Pos) /*!< Bit mask of PSELMOSI field. */

+#define SPI_PSEL_MOSI_PSELMOSI_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */

+

+/* Register: SPI_PSEL_MISO */

+/* Description: Pin select for MISO */

+

+/* Bits 31..0 : Pin number configuration for SPI MISO signal */

+#define SPI_PSEL_MISO_PSELMISO_Pos (0UL) /*!< Position of PSELMISO field. */

+#define SPI_PSEL_MISO_PSELMISO_Msk (0xFFFFFFFFUL << SPI_PSEL_MISO_PSELMISO_Pos) /*!< Bit mask of PSELMISO field. */

+#define SPI_PSEL_MISO_PSELMISO_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */

+

+/* Register: SPI_RXD */

+/* Description: RXD register */

+

+/* Bits 7..0 : RX data received. Double buffered */

+#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */

+#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */

+

+/* Register: SPI_TXD */

+/* Description: TXD register */

+

+/* Bits 7..0 : TX data to send. Double buffered */

+#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */

+#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */

+

+/* Register: SPI_FREQUENCY */

+/* Description: SPI frequency */

+

+/* Bits 31..0 : SPI master data rate */

+#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */

+#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */

+#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */

+#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */

+#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */

+#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */

+#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */

+#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */

+#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */

+

+/* Register: SPI_CONFIG */

+/* Description: Configuration register */

+

+/* Bit 2 : Serial clock (SCK) polarity */

+#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */

+#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */

+#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */

+#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */

+

+/* Bit 1 : Serial clock (SCK) phase */

+#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */

+#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */

+#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */

+#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */

+

+/* Bit 0 : Bit order */

+#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */

+#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */

+#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */

+#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */

+

+

+/* Peripheral: SPIM */

+/* Description: Serial Peripheral Interface Master with EasyDMA 0 */

+

+/* Register: SPIM_SHORTS */

+/* Description: Shortcut register */

+

+/* Bit 17 : Shortcut between END event and START task */

+#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */

+#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */

+#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */

+#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */

+

+/* Register: SPIM_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 19 : Write '1' to Enable interrupt for STARTED event */

+#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */

+#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */

+#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */

+#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */

+#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */

+

+/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */

+#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */

+#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */

+#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */

+#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */

+#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */

+

+/* Bit 6 : Write '1' to Enable interrupt for END event */

+#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */

+#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */

+#define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */

+#define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */

+#define SPIM_INTENSET_END_Set (1UL) /*!< Enable */

+

+/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */

+#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */

+#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */

+#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */

+#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */

+#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */

+

+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */

+#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */

+#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */

+#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */

+#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */

+#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */

+

+/* Register: SPIM_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 19 : Write '1' to Disable interrupt for STARTED event */

+#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */

+#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */

+#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */

+#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */

+#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */

+

+/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */

+#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */

+#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */

+#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */

+#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */

+#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */

+

+/* Bit 6 : Write '1' to Disable interrupt for END event */

+#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */

+#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */

+#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */

+#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */

+#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */

+

+/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */

+#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */

+#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */

+#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */

+#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */

+#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */

+

+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */

+#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */

+#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */

+#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */

+#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */

+#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */

+

+/* Register: SPIM_ENABLE */

+/* Description: Enable SPIM */

+

+/* Bits 3..0 : Enable or disable SPIM */

+#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */

+#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */

+#define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */

+#define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */

+

+/* Register: SPIM_PSEL_SCK */

+/* Description: Pin select for SCK */

+

+/* Bit 31 : Connection */

+#define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */

+#define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */

+#define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */

+#define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */

+

+/* Bits 4..0 : Pin number */

+#define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */

+#define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */

+

+/* Register: SPIM_PSEL_MOSI */

+/* Description: Pin select for MOSI signal */

+

+/* Bit 31 : Connection */

+#define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */

+#define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */

+#define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */

+#define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */

+

+/* Bits 4..0 : Pin number */

+#define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */

+#define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */

+

+/* Register: SPIM_PSEL_MISO */

+/* Description: Pin select for MISO signal */

+

+/* Bit 31 : Connection */

+#define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */

+#define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */

+#define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */

+#define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */

+

+/* Bits 4..0 : Pin number */

+#define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */

+#define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */

+

+/* Register: SPIM_FREQUENCY */

+/* Description: SPI frequency */

+

+/* Bits 31..0 : SPI master data rate */

+#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */

+#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */

+#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */

+#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */

+#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */

+#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */

+#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */

+#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */

+#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */

+

+/* Register: SPIM_RXD_PTR */

+/* Description: Data pointer */

+

+/* Bits 31..0 : Data pointer */

+#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */

+#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

+

+/* Register: SPIM_RXD_MAXCNT */

+/* Description: Maximum number of bytes in receive buffer */

+

+/* Bits 7..0 : Maximum number of bytes in receive buffer */

+#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */

+#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

+

+/* Register: SPIM_RXD_AMOUNT */

+/* Description: Number of bytes transferred in the last transaction */

+

+/* Bits 7..0 : Number of bytes transferred in the last transaction */

+#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */

+#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */

+

+/* Register: SPIM_RXD_LIST */

+/* Description: EasyDMA list type */

+

+/* Bits 2..0 : List type */

+#define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */

+#define SPIM_RXD_LIST_LIST_Msk (0x7UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */

+#define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */

+#define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */

+

+/* Register: SPIM_TXD_PTR */

+/* Description: Data pointer */

+

+/* Bits 31..0 : Data pointer */

+#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */

+#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

+

+/* Register: SPIM_TXD_MAXCNT */

+/* Description: Maximum number of bytes in transmit buffer */

+

+/* Bits 7..0 : Maximum number of bytes in transmit buffer */

+#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */

+#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

+

+/* Register: SPIM_TXD_AMOUNT */

+/* Description: Number of bytes transferred in the last transaction */

+

+/* Bits 7..0 : Number of bytes transferred in the last transaction */

+#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */

+#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */

+

+/* Register: SPIM_TXD_LIST */

+/* Description: EasyDMA list type */

+

+/* Bits 2..0 : List type */

+#define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */

+#define SPIM_TXD_LIST_LIST_Msk (0x7UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */

+#define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */

+#define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */

+

+/* Register: SPIM_CONFIG */

+/* Description: Configuration register */

+

+/* Bit 2 : Serial clock (SCK) polarity */

+#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */

+#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */

+#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */

+#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */

+

+/* Bit 1 : Serial clock (SCK) phase */

+#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */

+#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */

+#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */

+#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */

+

+/* Bit 0 : Bit order */

+#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */

+#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */

+#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */

+#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */

+

+/* Register: SPIM_ORC */

+/* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer. */

+

+/* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. */

+#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */

+#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */

+

+

+/* Peripheral: SPIS */

+/* Description: SPI Slave 0 */

+

+/* Register: SPIS_SHORTS */

+/* Description: Shortcut register */

+

+/* Bit 2 : Shortcut between END event and ACQUIRE task */

+#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */

+#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */

+#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */

+#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */

+

+/* Register: SPIS_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 10 : Write '1' to Enable interrupt for ACQUIRED event */

+#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */

+#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */

+#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */

+#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */

+#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */

+

+/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */

+#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */

+#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */

+#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */

+#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */

+#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */

+

+/* Bit 1 : Write '1' to Enable interrupt for END event */

+#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */

+#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */

+#define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */

+#define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */

+#define SPIS_INTENSET_END_Set (1UL) /*!< Enable */

+

+/* Register: SPIS_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 10 : Write '1' to Disable interrupt for ACQUIRED event */

+#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */

+#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */

+#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */

+#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */

+#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */

+

+/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */

+#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */

+#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */

+#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */

+#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */

+#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */

+

+/* Bit 1 : Write '1' to Disable interrupt for END event */

+#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */

+#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */

+#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */

+#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */

+#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */

+

+/* Register: SPIS_SEMSTAT */

+/* Description: Semaphore status register */

+

+/* Bits 1..0 : Semaphore status */

+#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */

+#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */

+#define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */

+#define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */

+#define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */

+#define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */

+

+/* Register: SPIS_STATUS */

+/* Description: Status from last transaction */

+

+/* Bit 1 : RX buffer overflow detected, and prevented */

+#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */

+#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */

+#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */

+#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */

+#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */

+

+/* Bit 0 : TX buffer over-read detected, and prevented */

+#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */

+#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */

+#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */

+#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */

+#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */

+

+/* Register: SPIS_ENABLE */

+/* Description: Enable SPI slave */

+

+/* Bits 3..0 : Enable or disable SPI slave */

+#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */

+#define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */

+#define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */

+#define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */

+

+/* Register: SPIS_PSEL_SCK */

+/* Description: Pin select for SCK */

+

+/* Bit 31 : Connection */

+#define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */

+#define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */

+#define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */

+#define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */

+

+/* Bits 4..0 : Pin number */

+#define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */

+#define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */

+

+/* Register: SPIS_PSEL_MISO */

+/* Description: Pin select for MISO signal */

+

+/* Bit 31 : Connection */

+#define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */

+#define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */

+#define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */

+#define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */

+

+/* Bits 4..0 : Pin number */

+#define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */

+#define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */

+

+/* Register: SPIS_PSEL_MOSI */

+/* Description: Pin select for MOSI signal */

+

+/* Bit 31 : Connection */

+#define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */

+#define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */

+#define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */

+#define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */

+

+/* Bits 4..0 : Pin number */

+#define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */

+#define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */

+

+/* Register: SPIS_PSEL_CSN */

+/* Description: Pin select for CSN signal */

+

+/* Bit 31 : Connection */

+#define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */

+#define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */

+#define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */

+#define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */

+

+/* Bits 4..0 : Pin number */

+#define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */

+#define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */

+

+/* Register: SPIS_RXD_PTR */

+/* Description: RXD data pointer */

+

+/* Bits 31..0 : RXD data pointer */

+#define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */

+#define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

+

+/* Register: SPIS_RXD_MAXCNT */

+/* Description: Maximum number of bytes in receive buffer */

+

+/* Bits 7..0 : Maximum number of bytes in receive buffer */

+#define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */

+#define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

+

+/* Register: SPIS_RXD_AMOUNT */

+/* Description: Number of bytes received in last granted transaction */

+

+/* Bits 7..0 : Number of bytes received in the last granted transaction */

+#define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */

+#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */

+

+/* Register: SPIS_TXD_PTR */

+/* Description: TXD data pointer */

+

+/* Bits 31..0 : TXD data pointer */

+#define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */

+#define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

+

+/* Register: SPIS_TXD_MAXCNT */

+/* Description: Maximum number of bytes in transmit buffer */

+

+/* Bits 7..0 : Maximum number of bytes in transmit buffer */

+#define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */

+#define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

+

+/* Register: SPIS_TXD_AMOUNT */

+/* Description: Number of bytes transmitted in last granted transaction */

+

+/* Bits 7..0 : Number of bytes transmitted in last granted transaction */

+#define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */

+#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */

+

+/* Register: SPIS_CONFIG */

+/* Description: Configuration register */

+

+/* Bit 2 : Serial clock (SCK) polarity */

+#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */

+#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */

+#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */

+#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */

+

+/* Bit 1 : Serial clock (SCK) phase */

+#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */

+#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */

+#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */

+#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */

+

+/* Bit 0 : Bit order */

+#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */

+#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */

+#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */

+#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */

+

+/* Register: SPIS_DEF */

+/* Description: Default character. Character clocked out in case of an ignored transaction. */

+

+/* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */

+#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */

+#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */

+

+/* Register: SPIS_ORC */

+/* Description: Over-read character */

+

+/* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */

+#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */

+#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */

+

+

+/* Peripheral: TEMP */

+/* Description: Temperature Sensor */

+

+/* Register: TEMP_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 0 : Write '1' to Enable interrupt for DATARDY event */

+#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */

+#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */

+#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */

+#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */

+#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */

+

+/* Register: TEMP_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 0 : Write '1' to Disable interrupt for DATARDY event */

+#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */

+#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */

+#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */

+#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */

+#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */

+

+/* Register: TEMP_TEMP */

+/* Description: Temperature in degC (0.25deg steps) */

+

+/* Bits 31..0 : Temperature in degC (0.25deg steps) */

+#define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */

+#define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */

+

+/* Register: TEMP_A0 */

+/* Description: Slope of 1st piece wise linear function */

+

+/* Bits 11..0 : Slope of 1st piece wise linear function */

+#define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */

+#define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */

+

+/* Register: TEMP_A1 */

+/* Description: Slope of 2nd piece wise linear function */

+

+/* Bits 11..0 : Slope of 2nd piece wise linear function */

+#define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */

+#define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */

+

+/* Register: TEMP_A2 */

+/* Description: Slope of 3rd piece wise linear function */

+

+/* Bits 11..0 : Slope of 3rd piece wise linear function */

+#define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */

+#define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */

+

+/* Register: TEMP_A3 */

+/* Description: Slope of 4th piece wise linear function */

+

+/* Bits 11..0 : Slope of 4th piece wise linear function */

+#define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */

+#define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */

+

+/* Register: TEMP_A4 */

+/* Description: Slope of 5th piece wise linear function */

+

+/* Bits 11..0 : Slope of 5th piece wise linear function */

+#define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */

+#define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */

+

+/* Register: TEMP_A5 */

+/* Description: Slope of 6th piece wise linear function */

+

+/* Bits 11..0 : Slope of 6th piece wise linear function */

+#define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */

+#define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */

+

+/* Register: TEMP_B0 */

+/* Description: y-intercept of 1st piece wise linear function */

+

+/* Bits 13..0 : y-intercept of 1st piece wise linear function */

+#define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */

+#define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */

+

+/* Register: TEMP_B1 */

+/* Description: y-intercept of 2nd piece wise linear function */

+

+/* Bits 13..0 : y-intercept of 2nd piece wise linear function */

+#define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */

+#define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */

+

+/* Register: TEMP_B2 */

+/* Description: y-intercept of 3rd piece wise linear function */

+

+/* Bits 13..0 : y-intercept of 3rd piece wise linear function */

+#define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */

+#define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */

+

+/* Register: TEMP_B3 */

+/* Description: y-intercept of 4th piece wise linear function */

+

+/* Bits 13..0 : y-intercept of 4th piece wise linear function */

+#define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */

+#define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */

+

+/* Register: TEMP_B4 */

+/* Description: y-intercept of 5th piece wise linear function */

+

+/* Bits 13..0 : y-intercept of 5th piece wise linear function */

+#define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */

+#define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */

+

+/* Register: TEMP_B5 */

+/* Description: y-intercept of 6th piece wise linear function */

+

+/* Bits 13..0 : y-intercept of 6th piece wise linear function */

+#define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */

+#define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */

+

+/* Register: TEMP_T0 */

+/* Description: End point of 1st piece wise linear function */

+

+/* Bits 7..0 : End point of 1st piece wise linear function */

+#define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */

+#define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */

+

+/* Register: TEMP_T1 */

+/* Description: End point of 2nd piece wise linear function */

+

+/* Bits 7..0 : End point of 2nd piece wise linear function */

+#define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */

+#define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */

+

+/* Register: TEMP_T2 */

+/* Description: End point of 3rd piece wise linear function */

+

+/* Bits 7..0 : End point of 3rd piece wise linear function */

+#define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */

+#define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */

+

+/* Register: TEMP_T3 */

+/* Description: End point of 4th piece wise linear function */

+

+/* Bits 7..0 : End point of 4th piece wise linear function */

+#define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */

+#define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */

+

+/* Register: TEMP_T4 */

+/* Description: End point of 5th piece wise linear function */

+

+/* Bits 7..0 : End point of 5th piece wise linear function */

+#define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */

+#define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */

+

+

+/* Peripheral: TIMER */

+/* Description: Timer/Counter 0 */

+

+/* Register: TIMER_SHORTS */

+/* Description: Shortcut register */

+

+/* Bit 13 : Shortcut between COMPARE[5] event and STOP task */

+#define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */

+#define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */

+#define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */

+#define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 12 : Shortcut between COMPARE[4] event and STOP task */

+#define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */

+#define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */

+#define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */

+#define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 11 : Shortcut between COMPARE[3] event and STOP task */

+#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */

+#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */

+#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */

+#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 10 : Shortcut between COMPARE[2] event and STOP task */

+#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */

+#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */

+#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */

+#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 9 : Shortcut between COMPARE[1] event and STOP task */

+#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */

+#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */

+#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */

+#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 8 : Shortcut between COMPARE[0] event and STOP task */

+#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */

+#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */

+#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */

+#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */

+#define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */

+#define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */

+#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */

+#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */

+#define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */

+#define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */

+#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */

+#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */

+#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */

+#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */

+#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */

+#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */

+#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */

+#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */

+#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */

+#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */

+#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */

+#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */

+#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */

+#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */

+#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */

+#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */

+#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */

+#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */

+

+/* Register: TIMER_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 21 : Write '1' to Enable interrupt for COMPARE[5] event */

+#define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */

+#define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */

+#define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */

+#define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */

+#define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */

+

+/* Bit 20 : Write '1' to Enable interrupt for COMPARE[4] event */

+#define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */

+#define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */

+#define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */

+#define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */

+#define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */

+

+/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */

+#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */

+#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */

+#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */

+#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */

+#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */

+

+/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */

+#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */

+#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */

+#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */

+#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */

+#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */

+

+/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */

+#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */

+#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */

+#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */

+#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */

+#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */

+

+/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */

+#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */

+#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */

+#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */

+#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */

+#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */

+

+/* Register: TIMER_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 21 : Write '1' to Disable interrupt for COMPARE[5] event */

+#define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */

+#define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */

+#define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */

+#define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */

+#define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */

+

+/* Bit 20 : Write '1' to Disable interrupt for COMPARE[4] event */

+#define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */

+#define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */

+#define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */

+#define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */

+#define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */

+

+/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */

+#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */

+#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */

+#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */

+#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */

+#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */

+

+/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */

+#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */

+#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */

+#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */

+#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */

+#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */

+

+/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */

+#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */

+#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */

+#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */

+#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */

+#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */

+

+/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */

+#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */

+#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */

+#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */

+#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */

+#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */

+

+/* Register: TIMER_MODE */

+/* Description: Timer mode selection */

+

+/* Bits 1..0 : Timer mode */

+#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */

+#define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */

+#define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */

+#define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator -  Select Counter mode */

+#define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */

+

+/* Register: TIMER_BITMODE */

+/* Description: Configure the number of bits used by the TIMER */

+

+/* Bits 1..0 : Timer bit width */

+#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */

+#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */

+#define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */

+#define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */

+#define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */

+#define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */

+

+/* Register: TIMER_PRESCALER */

+/* Description: Timer prescaler register */

+

+/* Bits 3..0 : Prescaler value */

+#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */

+#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */

+

+/* Register: TIMER_CC */

+/* Description: Description collection[0]:  Capture/Compare register 0 */

+

+/* Bits 31..0 : Capture/Compare value */

+#define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */

+#define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */

+

+

+/* Peripheral: TWI */

+/* Description: I2C compatible Two-Wire Interface 0 */

+

+/* Register: TWI_SHORTS */

+/* Description: Shortcut register */

+

+/* Bit 1 : Shortcut between BB event and STOP task */

+#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */

+#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */

+#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */

+#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 0 : Shortcut between BB event and SUSPEND task */

+#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */

+#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */

+#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */

+#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */

+

+/* Register: TWI_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */

+#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */

+#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */

+#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */

+#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */

+#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */

+

+/* Bit 14 : Write '1' to Enable interrupt for BB event */

+#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */

+#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */

+#define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */

+#define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */

+#define TWI_INTENSET_BB_Set (1UL) /*!< Enable */

+

+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */

+#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */

+#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */

+#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */

+#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */

+#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */

+

+/* Bit 7 : Write '1' to Enable interrupt for TXDSENT event */

+#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */

+#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */

+#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */

+#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */

+#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */

+

+/* Bit 2 : Write '1' to Enable interrupt for RXDREADY event */

+#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */

+#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */

+#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */

+#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */

+#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */

+

+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */

+#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */

+#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */

+#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */

+#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */

+#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */

+

+/* Register: TWI_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */

+#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */

+#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */

+#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */

+#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */

+#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */

+

+/* Bit 14 : Write '1' to Disable interrupt for BB event */

+#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */

+#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */

+#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */

+#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */

+#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */

+

+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */

+#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */

+#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */

+#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */

+#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */

+#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */

+

+/* Bit 7 : Write '1' to Disable interrupt for TXDSENT event */

+#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */

+#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */

+#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */

+#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */

+#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */

+

+/* Bit 2 : Write '1' to Disable interrupt for RXDREADY event */

+#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */

+#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */

+#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */

+#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */

+#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */

+

+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */

+#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */

+#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */

+#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */

+#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */

+#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */

+

+/* Register: TWI_ERRORSRC */

+/* Description: Error source */

+

+/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */

+#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */

+#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */

+#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */

+#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */

+

+/* Bit 1 : NACK received after sending the address (write '1' to clear) */

+#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */

+#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */

+#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */

+#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */

+

+/* Bit 0 : Overrun error */

+#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */

+#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */

+#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */

+#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */

+

+/* Register: TWI_ENABLE */

+/* Description: Enable TWI */

+

+/* Bits 3..0 : Enable or disable TWI */

+#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */

+#define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */

+#define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */

+#define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */

+

+/* Register: TWI_PSELSCL */

+/* Description: Pin select for SCL */

+

+/* Bits 31..0 : Pin number configuration for TWI SCL signal */

+#define TWI_PSELSCL_PSELSCL_Pos (0UL) /*!< Position of PSELSCL field. */

+#define TWI_PSELSCL_PSELSCL_Msk (0xFFFFFFFFUL << TWI_PSELSCL_PSELSCL_Pos) /*!< Bit mask of PSELSCL field. */

+#define TWI_PSELSCL_PSELSCL_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */

+

+/* Register: TWI_PSELSDA */

+/* Description: Pin select for SDA */

+

+/* Bits 31..0 : Pin number configuration for TWI SDA signal */

+#define TWI_PSELSDA_PSELSDA_Pos (0UL) /*!< Position of PSELSDA field. */

+#define TWI_PSELSDA_PSELSDA_Msk (0xFFFFFFFFUL << TWI_PSELSDA_PSELSDA_Pos) /*!< Bit mask of PSELSDA field. */

+#define TWI_PSELSDA_PSELSDA_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */

+

+/* Register: TWI_RXD */

+/* Description: RXD register */

+

+/* Bits 7..0 : RXD register */

+#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */

+#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */

+

+/* Register: TWI_TXD */

+/* Description: TXD register */

+

+/* Bits 7..0 : TXD register */

+#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */

+#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */

+

+/* Register: TWI_FREQUENCY */

+/* Description: TWI frequency */

+

+/* Bits 31..0 : TWI master clock frequency */

+#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */

+#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */

+#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */

+#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */

+#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */

+

+/* Register: TWI_ADDRESS */

+/* Description: Address used in the TWI transfer */

+

+/* Bits 6..0 : Address used in the TWI transfer */

+#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */

+#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */

+

+

+/* Peripheral: TWIM */

+/* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */

+

+/* Register: TWIM_SHORTS */

+/* Description: Shortcut register */

+

+/* Bit 12 : Shortcut between LASTRX event and STOP task */

+#define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */

+#define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */

+#define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */

+#define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 10 : Shortcut between LASTRX event and STARTTX task */

+#define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */

+#define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */

+#define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */

+#define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 9 : Shortcut between LASTTX event and STOP task */

+#define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */

+#define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */

+#define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */

+#define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 8 : Shortcut between LASTTX event and SUSPEND task */

+#define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */

+#define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */

+#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */

+#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 7 : Shortcut between LASTTX event and STARTRX task */

+#define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */

+#define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */

+#define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */

+#define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */

+

+/* Register: TWIM_INTEN */

+/* Description: Enable or disable interrupt */

+

+/* Bit 24 : Enable or disable interrupt for LASTTX event */

+#define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */

+#define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */

+#define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */

+#define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */

+

+/* Bit 23 : Enable or disable interrupt for LASTRX event */

+#define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */

+#define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */

+#define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */

+#define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */

+

+/* Bit 20 : Enable or disable interrupt for TXSTARTED event */

+#define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */

+#define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */

+#define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */

+#define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */

+

+/* Bit 19 : Enable or disable interrupt for RXSTARTED event */

+#define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */

+#define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */

+#define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */

+#define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */

+

+/* Bit 18 : Enable or disable interrupt for SUSPENDED event */

+#define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */

+#define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */

+#define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */

+#define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */

+

+/* Bit 9 : Enable or disable interrupt for ERROR event */

+#define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */

+#define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */

+#define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */

+#define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */

+

+/* Bit 1 : Enable or disable interrupt for STOPPED event */

+#define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */

+#define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */

+#define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */

+#define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */

+

+/* Register: TWIM_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 24 : Write '1' to Enable interrupt for LASTTX event */

+#define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */

+#define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */

+#define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */

+#define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */

+#define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */

+

+/* Bit 23 : Write '1' to Enable interrupt for LASTRX event */

+#define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */

+#define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */

+#define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */

+#define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */

+#define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */

+

+/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */

+#define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */

+#define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */

+#define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */

+#define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */

+#define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */

+

+/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */

+#define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */

+#define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */

+#define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */

+#define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */

+#define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */

+

+/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */

+#define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */

+#define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */

+#define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */

+#define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */

+#define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */

+

+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */

+#define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */

+#define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */

+#define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */

+#define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */

+#define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */

+

+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */

+#define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */

+#define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */

+#define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */

+#define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */

+#define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */

+

+/* Register: TWIM_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 24 : Write '1' to Disable interrupt for LASTTX event */

+#define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */

+#define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */

+#define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */

+#define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */

+#define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */

+

+/* Bit 23 : Write '1' to Disable interrupt for LASTRX event */

+#define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */

+#define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */

+#define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */

+#define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */

+#define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */

+

+/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */

+#define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */

+#define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */

+#define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */

+#define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */

+#define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */

+

+/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */

+#define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */

+#define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */

+#define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */

+#define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */

+#define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */

+

+/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */

+#define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */

+#define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */

+#define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */

+#define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */

+#define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */

+

+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */

+#define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */

+#define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */

+#define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */

+#define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */

+#define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */

+

+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */

+#define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */

+#define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */

+#define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */

+#define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */

+#define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */

+

+/* Register: TWIM_ERRORSRC */

+/* Description: Error source */

+

+/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */

+#define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */

+#define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */

+#define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */

+#define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */

+

+/* Bit 1 : NACK received after sending the address (write '1' to clear) */

+#define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */

+#define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */

+#define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */

+#define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */

+

+/* Register: TWIM_ENABLE */

+/* Description: Enable TWIM */

+

+/* Bits 3..0 : Enable or disable TWIM */

+#define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */

+#define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */

+#define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */

+#define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */

+

+/* Register: TWIM_PSEL_SCL */

+/* Description: Pin select for SCL signal */

+

+/* Bit 31 : Connection */

+#define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */

+#define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */

+#define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */

+#define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */

+

+/* Bits 4..0 : Pin number */

+#define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */

+#define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */

+

+/* Register: TWIM_PSEL_SDA */

+/* Description: Pin select for SDA signal */

+

+/* Bit 31 : Connection */

+#define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */

+#define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */

+#define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */

+#define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */

+

+/* Bits 4..0 : Pin number */

+#define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */

+#define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */

+

+/* Register: TWIM_FREQUENCY */

+/* Description: TWI frequency */

+

+/* Bits 31..0 : TWI master clock frequency */

+#define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */

+#define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */

+#define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */

+#define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */

+#define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */

+

+/* Register: TWIM_RXD_PTR */

+/* Description: Data pointer */

+

+/* Bits 31..0 : Data pointer */

+#define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */

+#define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

+

+/* Register: TWIM_RXD_MAXCNT */

+/* Description: Maximum number of bytes in receive buffer */

+

+/* Bits 7..0 : Maximum number of bytes in receive buffer */

+#define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */

+#define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

+

+/* Register: TWIM_RXD_AMOUNT */

+/* Description: Number of bytes transferred in the last transaction */

+

+/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */

+#define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */

+#define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */

+

+/* Register: TWIM_RXD_LIST */

+/* Description: EasyDMA list type */

+

+/* Bits 2..0 : List type */

+#define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */

+#define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */

+#define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */

+#define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */

+

+/* Register: TWIM_TXD_PTR */

+/* Description: Data pointer */

+

+/* Bits 31..0 : Data pointer */

+#define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */

+#define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

+

+/* Register: TWIM_TXD_MAXCNT */

+/* Description: Maximum number of bytes in transmit buffer */

+

+/* Bits 7..0 : Maximum number of bytes in transmit buffer */

+#define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */

+#define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

+

+/* Register: TWIM_TXD_AMOUNT */

+/* Description: Number of bytes transferred in the last transaction */

+

+/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */

+#define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */

+#define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */

+

+/* Register: TWIM_TXD_LIST */

+/* Description: EasyDMA list type */

+

+/* Bits 2..0 : List type */

+#define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */

+#define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */

+#define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */

+#define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */

+

+/* Register: TWIM_ADDRESS */

+/* Description: Address used in the TWI transfer */

+

+/* Bits 6..0 : Address used in the TWI transfer */

+#define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */

+#define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */

+

+

+/* Peripheral: TWIS */

+/* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */

+

+/* Register: TWIS_SHORTS */

+/* Description: Shortcut register */

+

+/* Bit 14 : Shortcut between READ event and SUSPEND task */

+#define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */

+#define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */

+#define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */

+#define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 13 : Shortcut between WRITE event and SUSPEND task */

+#define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */

+#define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */

+#define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */

+#define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */

+

+/* Register: TWIS_INTEN */

+/* Description: Enable or disable interrupt */

+

+/* Bit 26 : Enable or disable interrupt for READ event */

+#define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */

+#define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */

+#define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */

+#define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */

+

+/* Bit 25 : Enable or disable interrupt for WRITE event */

+#define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */

+#define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */

+#define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */

+#define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */

+

+/* Bit 20 : Enable or disable interrupt for TXSTARTED event */

+#define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */

+#define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */

+#define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */

+#define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */

+

+/* Bit 19 : Enable or disable interrupt for RXSTARTED event */

+#define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */

+#define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */

+#define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */

+#define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */

+

+/* Bit 9 : Enable or disable interrupt for ERROR event */

+#define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */

+#define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */

+#define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */

+#define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */

+

+/* Bit 1 : Enable or disable interrupt for STOPPED event */

+#define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */

+#define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */

+#define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */

+#define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */

+

+/* Register: TWIS_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 26 : Write '1' to Enable interrupt for READ event */

+#define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */

+#define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */

+#define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */

+#define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */

+#define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */

+

+/* Bit 25 : Write '1' to Enable interrupt for WRITE event */

+#define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */

+#define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */

+#define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */

+#define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */

+#define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */

+

+/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */

+#define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */

+#define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */

+#define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */

+#define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */

+#define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */

+

+/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */

+#define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */

+#define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */

+#define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */

+#define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */

+#define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */

+

+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */

+#define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */

+#define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */

+#define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */

+#define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */

+#define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */

+

+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */

+#define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */

+#define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */

+#define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */

+#define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */

+#define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */

+

+/* Register: TWIS_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 26 : Write '1' to Disable interrupt for READ event */

+#define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */

+#define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */

+#define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */

+#define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */

+#define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */

+

+/* Bit 25 : Write '1' to Disable interrupt for WRITE event */

+#define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */

+#define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */

+#define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */

+#define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */

+#define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */

+

+/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */

+#define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */

+#define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */

+#define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */

+#define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */

+#define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */

+

+/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */

+#define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */

+#define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */

+#define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */

+#define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */

+#define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */

+

+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */

+#define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */

+#define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */

+#define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */

+#define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */

+#define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */

+

+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */

+#define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */

+#define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */

+#define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */

+#define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */

+#define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */

+

+/* Register: TWIS_ERRORSRC */

+/* Description: Error source */

+

+/* Bit 3 : TX buffer over-read detected, and prevented */

+#define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */

+#define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */

+#define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */

+#define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */

+

+/* Bit 2 : NACK sent after receiving a data byte */

+#define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */

+#define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */

+#define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */

+#define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */

+

+/* Bit 0 : RX buffer overflow detected, and prevented */

+#define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */

+#define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */

+#define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */

+#define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */

+

+/* Register: TWIS_MATCH */

+/* Description: Status register indicating which address had a match */

+

+/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */

+#define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */

+#define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */

+

+/* Register: TWIS_ENABLE */

+/* Description: Enable TWIS */

+

+/* Bits 3..0 : Enable or disable TWIS */

+#define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */

+#define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */

+#define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */

+#define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */

+

+/* Register: TWIS_PSEL_SCL */

+/* Description: Pin select for SCL signal */

+

+/* Bit 31 : Connection */

+#define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */

+#define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */

+#define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */

+#define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */

+

+/* Bits 4..0 : Pin number */

+#define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */

+#define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */

+

+/* Register: TWIS_PSEL_SDA */

+/* Description: Pin select for SDA signal */

+

+/* Bit 31 : Connection */

+#define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */

+#define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */

+#define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */

+#define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */

+

+/* Bits 4..0 : Pin number */

+#define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */

+#define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */

+

+/* Register: TWIS_RXD_PTR */

+/* Description: RXD Data pointer */

+

+/* Bits 31..0 : RXD Data pointer */

+#define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */

+#define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

+

+/* Register: TWIS_RXD_MAXCNT */

+/* Description: Maximum number of bytes in RXD buffer */

+

+/* Bits 7..0 : Maximum number of bytes in RXD buffer */

+#define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */

+#define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

+

+/* Register: TWIS_RXD_AMOUNT */

+/* Description: Number of bytes transferred in the last RXD transaction */

+

+/* Bits 7..0 : Number of bytes transferred in the last RXD transaction */

+#define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */

+#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */

+

+/* Register: TWIS_TXD_PTR */

+/* Description: TXD Data pointer */

+

+/* Bits 31..0 : TXD Data pointer */

+#define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */

+#define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

+

+/* Register: TWIS_TXD_MAXCNT */

+/* Description: Maximum number of bytes in TXD buffer */

+

+/* Bits 7..0 : Maximum number of bytes in TXD buffer */

+#define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */

+#define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

+

+/* Register: TWIS_TXD_AMOUNT */

+/* Description: Number of bytes transferred in the last TXD transaction */

+

+/* Bits 7..0 : Number of bytes transferred in the last TXD transaction */

+#define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */

+#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */

+

+/* Register: TWIS_ADDRESS */

+/* Description: Description collection[0]:  TWI slave address 0 */

+

+/* Bits 6..0 : TWI slave address */

+#define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */

+#define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */

+

+/* Register: TWIS_CONFIG */

+/* Description: Configuration register for the address match mechanism */

+

+/* Bit 1 : Enable or disable address matching on ADDRESS[1] */

+#define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */

+#define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */

+#define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */

+#define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */

+

+/* Bit 0 : Enable or disable address matching on ADDRESS[0] */

+#define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */

+#define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */

+#define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */

+#define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */

+

+/* Register: TWIS_ORC */

+/* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */

+

+/* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */

+#define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */

+#define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */

+

+

+/* Peripheral: UART */

+/* Description: Universal Asynchronous Receiver/Transmitter */

+

+/* Register: UART_SHORTS */

+/* Description: Shortcut register */

+

+/* Bit 4 : Shortcut between NCTS event and STOPRX task */

+#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */

+#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */

+#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */

+#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 3 : Shortcut between CTS event and STARTRX task */

+#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */

+#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */

+#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */

+#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */

+

+/* Register: UART_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 17 : Write '1' to Enable interrupt for RXTO event */

+#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */

+#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */

+#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */

+#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */

+#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */

+

+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */

+#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */

+#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */

+#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */

+#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */

+#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */

+

+/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */

+#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */

+#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */

+#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */

+#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */

+#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */

+

+/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */

+#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */

+#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */

+#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */

+#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */

+#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */

+

+/* Bit 1 : Write '1' to Enable interrupt for NCTS event */

+#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */

+#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */

+#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */

+#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */

+#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */

+

+/* Bit 0 : Write '1' to Enable interrupt for CTS event */

+#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */

+#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */

+#define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */

+#define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */

+#define UART_INTENSET_CTS_Set (1UL) /*!< Enable */

+

+/* Register: UART_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 17 : Write '1' to Disable interrupt for RXTO event */

+#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */

+#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */

+#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */

+#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */

+#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */

+

+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */

+#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */

+#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */

+#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */

+#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */

+#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */

+

+/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */

+#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */

+#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */

+#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */

+#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */

+#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */

+

+/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */

+#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */

+#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */

+#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */

+#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */

+#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */

+

+/* Bit 1 : Write '1' to Disable interrupt for NCTS event */

+#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */

+#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */

+#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */

+#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */

+#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */

+

+/* Bit 0 : Write '1' to Disable interrupt for CTS event */

+#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */

+#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */

+#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */

+#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */

+#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */

+

+/* Register: UART_ERRORSRC */

+/* Description: Error source */

+

+/* Bit 3 : Break condition */

+#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */

+#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */

+#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */

+#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */

+

+/* Bit 2 : Framing error occurred */

+#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */

+#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */

+#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */

+#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */

+

+/* Bit 1 : Parity error */

+#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */

+#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */

+#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */

+#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */

+

+/* Bit 0 : Overrun error */

+#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */

+#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */

+#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */

+#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */

+

+/* Register: UART_ENABLE */

+/* Description: Enable UART */

+

+/* Bits 3..0 : Enable or disable UART */

+#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */

+#define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */

+#define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */

+#define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */

+

+/* Register: UART_PSELRTS */

+/* Description: Pin select for RTS */

+

+/* Bits 31..0 : Pin number configuration for UART RTS signal */

+#define UART_PSELRTS_PSELRTS_Pos (0UL) /*!< Position of PSELRTS field. */

+#define UART_PSELRTS_PSELRTS_Msk (0xFFFFFFFFUL << UART_PSELRTS_PSELRTS_Pos) /*!< Bit mask of PSELRTS field. */

+#define UART_PSELRTS_PSELRTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */

+

+/* Register: UART_PSELTXD */

+/* Description: Pin select for TXD */

+

+/* Bits 31..0 : Pin number configuration for UART TXD signal */

+#define UART_PSELTXD_PSELTXD_Pos (0UL) /*!< Position of PSELTXD field. */

+#define UART_PSELTXD_PSELTXD_Msk (0xFFFFFFFFUL << UART_PSELTXD_PSELTXD_Pos) /*!< Bit mask of PSELTXD field. */

+#define UART_PSELTXD_PSELTXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */

+

+/* Register: UART_PSELCTS */

+/* Description: Pin select for CTS */

+

+/* Bits 31..0 : Pin number configuration for UART CTS signal */

+#define UART_PSELCTS_PSELCTS_Pos (0UL) /*!< Position of PSELCTS field. */

+#define UART_PSELCTS_PSELCTS_Msk (0xFFFFFFFFUL << UART_PSELCTS_PSELCTS_Pos) /*!< Bit mask of PSELCTS field. */

+#define UART_PSELCTS_PSELCTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */

+

+/* Register: UART_PSELRXD */

+/* Description: Pin select for RXD */

+

+/* Bits 31..0 : Pin number configuration for UART RXD signal */

+#define UART_PSELRXD_PSELRXD_Pos (0UL) /*!< Position of PSELRXD field. */

+#define UART_PSELRXD_PSELRXD_Msk (0xFFFFFFFFUL << UART_PSELRXD_PSELRXD_Pos) /*!< Bit mask of PSELRXD field. */

+#define UART_PSELRXD_PSELRXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */

+

+/* Register: UART_RXD */

+/* Description: RXD register */

+

+/* Bits 7..0 : RX data received in previous transfers, double buffered */

+#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */

+#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */

+

+/* Register: UART_TXD */

+/* Description: TXD register */

+

+/* Bits 7..0 : TX data to be transferred */

+#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */

+#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */

+

+/* Register: UART_BAUDRATE */

+/* Description: Baud rate */

+

+/* Bits 31..0 : Baud-rate */

+#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */

+#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */

+#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */

+#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */

+#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */

+#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */

+#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */

+#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */

+#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */

+#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */

+#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */

+#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */

+#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */

+#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */

+#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */

+#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */

+#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */

+#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */

+

+/* Register: UART_CONFIG */

+/* Description: Configuration of parity and hardware flow control */

+

+/* Bits 3..1 : Parity */

+#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */

+#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */

+#define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */

+#define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */

+

+/* Bit 0 : Hardware flow control */

+#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */

+#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */

+#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */

+#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */

+

+

+/* Peripheral: UARTE */

+/* Description: UART with EasyDMA */

+

+/* Register: UARTE_SHORTS */

+/* Description: Shortcut register */

+

+/* Bit 6 : Shortcut between ENDRX event and STOPRX task */

+#define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */

+#define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */

+#define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */

+#define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */

+

+/* Bit 5 : Shortcut between ENDRX event and STARTRX task */

+#define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */

+#define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */

+#define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */

+#define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */

+

+/* Register: UARTE_INTEN */

+/* Description: Enable or disable interrupt */

+

+/* Bit 22 : Enable or disable interrupt for TXSTOPPED event */

+#define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */

+#define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */

+#define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */

+#define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */

+

+/* Bit 20 : Enable or disable interrupt for TXSTARTED event */

+#define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */

+#define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */

+#define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */

+#define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */

+

+/* Bit 19 : Enable or disable interrupt for RXSTARTED event */

+#define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */

+#define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */

+#define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */

+#define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */

+

+/* Bit 17 : Enable or disable interrupt for RXTO event */

+#define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */

+#define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */

+#define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */

+#define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */

+

+/* Bit 9 : Enable or disable interrupt for ERROR event */

+#define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */

+#define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */

+#define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */

+#define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */

+

+/* Bit 8 : Enable or disable interrupt for ENDTX event */

+#define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */

+#define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */

+#define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */

+#define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */

+

+/* Bit 4 : Enable or disable interrupt for ENDRX event */

+#define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */

+#define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */

+#define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */

+#define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */

+

+/* Bit 1 : Enable or disable interrupt for NCTS event */

+#define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */

+#define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */

+#define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */

+#define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */

+

+/* Bit 0 : Enable or disable interrupt for CTS event */

+#define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */

+#define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */

+#define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */

+#define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */

+

+/* Register: UARTE_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 22 : Write '1' to Enable interrupt for TXSTOPPED event */

+#define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */

+#define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */

+#define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */

+#define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */

+#define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */

+

+/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */

+#define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */

+#define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */

+#define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */

+#define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */

+#define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */

+

+/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */

+#define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */

+#define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */

+#define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */

+#define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */

+#define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */

+

+/* Bit 17 : Write '1' to Enable interrupt for RXTO event */

+#define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */

+#define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */

+#define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */

+#define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */

+#define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */

+

+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */

+#define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */

+#define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */

+#define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */

+#define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */

+#define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */

+

+/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */

+#define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */

+#define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */

+#define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */

+#define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */

+#define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */

+

+/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */

+#define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */

+#define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */

+#define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */

+#define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */

+#define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */

+

+/* Bit 1 : Write '1' to Enable interrupt for NCTS event */

+#define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */

+#define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */

+#define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */

+#define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */

+#define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */

+

+/* Bit 0 : Write '1' to Enable interrupt for CTS event */

+#define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */

+#define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */

+#define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */

+#define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */

+#define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */

+

+/* Register: UARTE_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 22 : Write '1' to Disable interrupt for TXSTOPPED event */

+#define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */

+#define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */

+#define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */

+#define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */

+#define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */

+

+/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */

+#define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */

+#define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */

+#define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */

+#define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */

+#define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */

+

+/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */

+#define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */

+#define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */

+#define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */

+#define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */

+#define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */

+

+/* Bit 17 : Write '1' to Disable interrupt for RXTO event */

+#define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */

+#define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */

+#define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */

+#define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */

+#define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */

+

+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */

+#define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */

+#define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */

+#define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */

+#define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */

+#define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */

+

+/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */

+#define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */

+#define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */

+#define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */

+#define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */

+#define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */

+

+/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */

+#define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */

+#define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */

+#define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */

+#define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */

+#define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */

+

+/* Bit 1 : Write '1' to Disable interrupt for NCTS event */

+#define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */

+#define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */

+#define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */

+#define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */

+#define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */

+

+/* Bit 0 : Write '1' to Disable interrupt for CTS event */

+#define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */

+#define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */

+#define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */

+#define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */

+#define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */

+

+/* Register: UARTE_ERRORSRC */

+/* Description: Error source */

+

+/* Bit 3 : Break condition */

+#define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */

+#define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */

+#define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */

+#define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */

+

+/* Bit 2 : Framing error occurred */

+#define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */

+#define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */

+#define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */

+#define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */

+

+/* Bit 1 : Parity error */

+#define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */

+#define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */

+#define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */

+#define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */

+

+/* Bit 0 : Overrun error */

+#define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */

+#define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */

+#define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */

+#define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */

+

+/* Register: UARTE_ENABLE */

+/* Description: Enable UART */

+

+/* Bits 3..0 : Enable or disable UARTE */

+#define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */

+#define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */

+#define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */

+#define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */

+

+/* Register: UARTE_PSEL_RTS */

+/* Description: Pin select for RTS signal */

+

+/* Bit 31 : Connection */

+#define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */

+#define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */

+#define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */

+#define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */

+

+/* Bits 4..0 : Pin number */

+#define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */

+#define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */

+

+/* Register: UARTE_PSEL_TXD */

+/* Description: Pin select for TXD signal */

+

+/* Bit 31 : Connection */

+#define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */

+#define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */

+#define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */

+#define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */

+

+/* Bits 4..0 : Pin number */

+#define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */

+#define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */

+

+/* Register: UARTE_PSEL_CTS */

+/* Description: Pin select for CTS signal */

+

+/* Bit 31 : Connection */

+#define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */

+#define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */

+#define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */

+#define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */

+

+/* Bits 4..0 : Pin number */

+#define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */

+#define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */

+

+/* Register: UARTE_PSEL_RXD */

+/* Description: Pin select for RXD signal */

+

+/* Bit 31 : Connection */

+#define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */

+#define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */

+#define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */

+#define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */

+

+/* Bits 4..0 : Pin number */

+#define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */

+#define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */

+

+/* Register: UARTE_BAUDRATE */

+/* Description: Baud rate */

+

+/* Bits 31..0 : Baud-rate */

+#define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */

+#define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */

+#define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */

+#define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */

+#define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */

+#define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */

+#define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */

+#define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */

+#define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */

+#define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */

+#define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */

+#define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */

+#define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */

+#define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */

+#define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */

+#define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */

+#define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */

+#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */

+

+/* Register: UARTE_RXD_PTR */

+/* Description: Data pointer */

+

+/* Bits 31..0 : Data pointer */

+#define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */

+#define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

+

+/* Register: UARTE_RXD_MAXCNT */

+/* Description: Maximum number of bytes in receive buffer */

+

+/* Bits 7..0 : Maximum number of bytes in receive buffer */

+#define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */

+#define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

+

+/* Register: UARTE_RXD_AMOUNT */

+/* Description: Number of bytes transferred in the last transaction */

+

+/* Bits 7..0 : Number of bytes transferred in the last transaction */

+#define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */

+#define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */

+

+/* Register: UARTE_TXD_PTR */

+/* Description: Data pointer */

+

+/* Bits 31..0 : Data pointer */

+#define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */

+#define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

+

+/* Register: UARTE_TXD_MAXCNT */

+/* Description: Maximum number of bytes in transmit buffer */

+

+/* Bits 7..0 : Maximum number of bytes in transmit buffer */

+#define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */

+#define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

+

+/* Register: UARTE_TXD_AMOUNT */

+/* Description: Number of bytes transferred in the last transaction */

+

+/* Bits 7..0 : Number of bytes transferred in the last transaction */

+#define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */

+#define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */

+

+/* Register: UARTE_CONFIG */

+/* Description: Configuration of parity and hardware flow control */

+

+/* Bits 3..1 : Parity */

+#define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */

+#define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */

+#define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */

+#define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */

+

+/* Bit 0 : Hardware flow control */

+#define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */

+#define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */

+#define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */

+#define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */

+

+

+/* Peripheral: UICR */

+/* Description: User Information Configuration Registers */

+

+/* Register: UICR_NRFFW */

+/* Description: Description collection[0]:  Reserved for Nordic firmware design */

+

+/* Bits 31..0 : Reserved for Nordic firmware design */

+#define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */

+#define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */

+

+/* Register: UICR_NRFHW */

+/* Description: Description collection[0]:  Reserved for Nordic hardware design */

+

+/* Bits 31..0 : Reserved for Nordic hardware design */

+#define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */

+#define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */

+

+/* Register: UICR_CUSTOMER */

+/* Description: Description collection[0]:  Reserved for customer */

+

+/* Bits 31..0 : Reserved for customer */

+#define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */

+#define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */

+

+/* Register: UICR_PSELRESET */

+/* Description: Description collection[0]:  Mapping of the nRESET function (see POWER chapter for details) */

+

+/* Bit 31 : Connection */

+#define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */

+#define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */

+#define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */

+#define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */

+

+/* Bits 4..0 : GPIO number P0.n onto which Reset is exposed */

+#define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */

+#define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */

+

+/* Register: UICR_APPROTECT */

+/* Description: Access Port protection */

+

+/* Bits 7..0 : Enable or disable Access Port protection. */

+#define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */

+#define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */

+#define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */

+#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */

+

+/* Register: UICR_NFCPINS */

+/* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */

+

+/* Bit 0 : Setting of pins dedicated to NFC functionality */

+#define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */

+#define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */

+#define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */

+#define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */

+

+

+/* Peripheral: WDT */

+/* Description: Watchdog Timer */

+

+/* Register: WDT_INTENSET */

+/* Description: Enable interrupt */

+

+/* Bit 0 : Write '1' to Enable interrupt for TIMEOUT event */

+#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */

+#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */

+#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */

+#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */

+#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */

+

+/* Register: WDT_INTENCLR */

+/* Description: Disable interrupt */

+

+/* Bit 0 : Write '1' to Disable interrupt for TIMEOUT event */

+#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */

+#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */

+#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */

+#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */

+#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */

+

+/* Register: WDT_RUNSTATUS */

+/* Description: Run status */

+

+/* Bit 0 : Indicates whether or not the watchdog is running */

+#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */

+#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */

+#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */

+#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */

+

+/* Register: WDT_REQSTATUS */

+/* Description: Request status */

+

+/* Bit 7 : Request status for RR[7] register */

+#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */

+#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */

+#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */

+#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */

+

+/* Bit 6 : Request status for RR[6] register */

+#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */

+#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */

+#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */

+#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */

+

+/* Bit 5 : Request status for RR[5] register */

+#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */

+#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */

+#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */

+#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */

+

+/* Bit 4 : Request status for RR[4] register */

+#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */

+#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */

+#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */

+#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */

+

+/* Bit 3 : Request status for RR[3] register */

+#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */

+#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */

+#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */

+#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */

+

+/* Bit 2 : Request status for RR[2] register */

+#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */

+#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */

+#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */

+#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */

+

+/* Bit 1 : Request status for RR[1] register */

+#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */

+#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */

+#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */

+#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */

+

+/* Bit 0 : Request status for RR[0] register */

+#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */

+#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */

+#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */

+#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */

+

+/* Register: WDT_CRV */

+/* Description: Counter reload value */

+

+/* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */

+#define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */

+#define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */

+

+/* Register: WDT_RREN */

+/* Description: Enable register for reload request registers */

+

+/* Bit 7 : Enable or disable RR[7] register */

+#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */

+#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */

+#define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */

+#define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */

+

+/* Bit 6 : Enable or disable RR[6] register */

+#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */

+#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */

+#define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */

+#define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */

+

+/* Bit 5 : Enable or disable RR[5] register */

+#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */

+#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */

+#define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */

+#define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */

+

+/* Bit 4 : Enable or disable RR[4] register */

+#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */

+#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */

+#define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */

+#define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */

+

+/* Bit 3 : Enable or disable RR[3] register */

+#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */

+#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */

+#define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */

+#define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */

+

+/* Bit 2 : Enable or disable RR[2] register */

+#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */

+#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */

+#define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */

+#define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */

+

+/* Bit 1 : Enable or disable RR[1] register */

+#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */

+#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */

+#define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */

+#define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */

+

+/* Bit 0 : Enable or disable RR[0] register */

+#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */

+#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */

+#define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */

+#define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */

+

+/* Register: WDT_CONFIG */

+/* Description: Configuration register */

+

+/* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */

+#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */

+#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */

+#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */

+#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */

+

+/* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */

+#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */

+#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */

+#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */

+#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */

+

+/* Register: WDT_RR */

+/* Description: Description collection[0]:  Reload request 0 */

+

+/* Bits 31..0 : Reload request register */

+#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */

+#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */

+#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */

+

+

+/*lint --flb "Leave library region" */

+#endif

diff --git a/os/hal/ports/NRF5/NRF52832/nrf_delay.h b/os/hal/ports/NRF5/NRF52832/nrf_delay.h
new file mode 100644
index 0000000..9b5df64
--- /dev/null
+++ b/os/hal/ports/NRF5/NRF52832/nrf_delay.h
@@ -0,0 +1,97 @@
+/*
+    Copyright (C) 2015 Stephen Caudle
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    NRF5/NRF52832/nrf_delay.h
+ * @brief   NRF5 Delay routines
+ *
+ * @{
+ */
+
+#ifndef _NRF_DELAY_H
+#define _NRF_DELAY_H
+
+inline static void nrf_delay_us(uint32_t volatile number_of_us) __attribute__((always_inline));
+inline static void nrf_delay_us(uint32_t volatile number_of_us)
+{
+register uint32_t delay __asm ("r0") = number_of_us;
+__asm volatile (
+".syntax unified\n"
+    "1:\n"
+    " SUBS %0, %0, #1\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " BNE 1b\n"
+    ".syntax divided\n"
+    : "+r" (delay));
+}
+#endif //__NRF_DELAY_H
diff --git a/os/hal/ports/NRF5/NRF52832/platform.mk b/os/hal/ports/NRF5/NRF52832/platform.mk
new file mode 100644
index 0000000..248027b
--- /dev/null
+++ b/os/hal/ports/NRF5/NRF52832/platform.mk
@@ -0,0 +1,52 @@
+ifeq ($(USE_SMART_BUILD),yes)
+HALCONF := $(strip $(shell cat halconf.h halconf_community.h 2>/dev/null | egrep -e "define"))
+
+# List of all the NRF51x platform files.
+PLATFORMSRC  = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF52832/hal_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_st_lld.c
+
+ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_pal_lld.c
+endif
+ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_serial_lld.c
+endif
+ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_spi_lld.c
+endif
+ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_i2c_lld.c
+endif
+ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_gpt_lld.c
+endif
+ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_wdg_lld.c
+endif
+ifneq ($(findstring HAL_USE_RNG TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_rng_lld.c
+endif
+ifneq ($(findstring HAL_USE_QEI TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_qei_lld.c
+endif
+else
+PLATFORMSRC  = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF52832/hal_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_pal_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_serial_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_spi_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_i2c_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_st_lld.c \
+	       ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_gpt_lld.c \
+	       ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_wdg_lld.c \
+	       ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_rng_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_qei_lld.c
+endif
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF52832
+
+
diff --git a/os/hal/ports/NRF5/NRF52832/todo.txt b/os/hal/ports/NRF5/NRF52832/todo.txt
new file mode 100644
index 0000000..bc6423a
--- /dev/null
+++ b/os/hal/ports/NRF5/NRF52832/todo.txt
@@ -0,0 +1,7 @@
+* add extra RTC, TIMER
+* assert size constraints on TIMER
+* clarify write-buffer for events handling
+   https://devzone.nordicsemi.com/question/86564/nrf52-write-buffer/
+* implement pin-reset, swo trace, trace pin configuration
+* implement errata (see system_nrf52.c)
+* check GPIO DETECTMODE and LATCH
diff --git a/os/hal/ports/NRF51/NRF51822/platform.mk b/os/hal/ports/NRF51/NRF51822/platform.mk
deleted file mode 100644
index b937e39..0000000
--- a/os/hal/ports/NRF51/NRF51822/platform.mk
+++ /dev/null
@@ -1,61 +0,0 @@
-ifeq ($(USE_SMART_BUILD),yes)
-HALCONF := $(strip $(shell cat halconf.h halconf_community.h 2>/dev/null | egrep -e "define"))
-
-# List of all the NRF51x platform files.
-PLATFORMSRC  = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
-               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_lld.c \
-               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_st_lld.c
-
-ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)
-PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_pal_lld.c
-endif
-ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),)
-PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_serial_lld.c
-endif
-ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),)
-PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_spi_lld.c
-endif
-ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),)
-PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_ext_lld_isr.c \
-               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_ext_lld.c
-endif
-ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),)
-PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_i2c_lld.c
-endif
-ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)
-PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_adc_lld.c
-endif
-ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),)
-PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_gpt_lld.c
-endif
-ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),)
-PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_wdg_lld.c
-endif
-ifneq ($(findstring HAL_USE_RNG TRUE,$(HALCONF)),)
-PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_rng_lld.c
-endif
-ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),)
-PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_pwm_lld.c
-endif
-else
-PLATFORMSRC  = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
-               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_lld.c \
-               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_pal_lld.c \
-               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_serial_lld.c \
-               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_st_lld.c \
-               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_spi_lld.c \
-               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_ext_lld_isr.c \
-               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_ext_lld.c \
-               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_i2c_lld.c \
-               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_adc_lld.c \
-               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_gpt_lld.c \
-               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_wdg_lld.c \
-               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_rng_lld.c \
-               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_pwm_lld.c
-endif
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
-              ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822
-
-
diff --git a/os/hal/ports/STM32/LLD/COMPv1/hal_comp_lld.c b/os/hal/ports/STM32/LLD/COMPv1/hal_comp_lld.c
new file mode 100644
index 0000000..62d9f14
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/COMPv1/hal_comp_lld.c
@@ -0,0 +1,520 @@
+/*
+    ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio
+              Copyright (C) 2017 Fabien Poussin (fabien.poussin (at) google's mail)
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+
+/**
+ * @file    STM32/hal_comp_lld.c
+ * @brief   STM32 Comp subsystem low level driver header.
+ *
+ * @addtogroup COMP
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_COMP || defined(__DOXYGEN__)
+
+#include "hal_comp.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   COMPD1 driver identifier.
+ * @note    The driver COMPD1 allocates the comparator COMP1 when enabled.
+ */
+#if STM32_COMP_USE_COMP1 || defined(__DOXYGEN__)
+COMPDriver COMPD1;
+#endif
+
+/**
+ * @brief   COMPD2 driver identifier.
+ * @note    The driver COMPD2 allocates the comparator COMP2 when enabled.
+ */
+#if STM32_COMP_USE_COMP2 || defined(__DOXYGEN__)
+COMPDriver COMPD2;
+#endif
+
+/**
+ * @brief   COMPD3 driver identifier.
+ * @note    The driver COMPD3 allocates the comparator COMP3 when enabled.
+ */
+#if STM32_COMP_USE_COMP3 || defined(__DOXYGEN__)
+COMPDriver COMPD3;
+#endif
+
+/**
+ * @brief   COMPD4 driver identifier.
+ * @note    The driver COMPD4 allocates the comparator COMP4 when enabled.
+ */
+#if STM32_COMP_USE_COMP4 || defined(__DOXYGEN__)
+COMPDriver COMPD4;
+#endif
+
+/**
+ * @brief   COMPD5 driver identifier.
+ * @note    The driver COMPD5 allocates the comparator COMP5 when enabled.
+ */
+#if STM32_COMP_USE_COMP5 || defined(__DOXYGEN__)
+COMPDriver COMPD5;
+#endif
+
+/**
+ * @brief   COMPD6 driver identifier.
+ * @note    The driver COMPD6 allocates the comparator COMP6 when enabled.
+ */
+#if STM32_COMP_USE_COMP6 || defined(__DOXYGEN__)
+COMPDriver COMPD6;
+#endif
+
+/**
+ * @brief   COMPD7 driver identifier.
+ * @note    The driver COMPD7 allocates the comparator COMP7 when enabled.
+ */
+#if STM32_COMP_USE_COMP7 || defined(__DOXYGEN__)
+COMPDriver COMPD7;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level COMP driver initialization.
+ *
+ * @notapi
+ */
+void comp_lld_init(void) {
+
+#if STM32_COMP_USE_COMP1
+  /* Driver initialization.*/
+  compObjectInit(&COMPD1);
+  COMPD1.reg = COMP;
+  COMPD1.reg->CSR = 0;
+#if STM32_COMP_USE_INTERRUPTS
+  nvicEnableVector(COMP1_2_3_IRQn, STM32_COMP_1_2_3_IRQ_PRIORITY);
+#endif
+#endif
+
+#if STM32_COMP_USE_COMP2
+  /* Driver initialization.*/
+  compObjectInit(&COMPD2);
+  COMPD2.reg = COMP2;
+  COMPD2.reg->CSR = 0;
+#if STM32_COMP_USE_INTERRUPTS
+  nvicEnableVector(COMP1_2_3_IRQn, STM32_COMP_1_2_3_IRQ_PRIORITY);
+#endif
+#endif
+
+#if STM32_COMP_USE_COMP3
+  /* Driver initialization.*/
+  compObjectInit(&COMPD3);
+  COMPD3.reg = COMP3;
+  COMPD3.reg->CSR = 0;
+#if STM32_COMP_USE_INTERRUPTS
+  nvicEnableVector(COMP1_2_3_IRQn, STM32_COMP_1_2_3_IRQ_PRIORITY);
+#endif
+#endif
+
+#if STM32_COMP_USE_COMP4
+  /* Driver initialization.*/
+  compObjectInit(&COMPD4);
+  COMPD4.reg = COMP4;
+  COMPD4.reg->CSR = 0;
+#if STM32_COMP_USE_INTERRUPTS
+  nvicEnableVector(COMP4_5_6_IRQn, STM32_COMP_1_2_3_IRQ_PRIORITY);
+#endif
+#endif
+
+#if STM32_COMP_USE_COMP5
+  /* Driver initialization.*/
+  compObjectInit(&COMPD5);
+  COMPD5.reg = COMP5;
+  COMPD5.reg->CSR = 0;
+#if STM32_COMP_USE_INTERRUPTS
+  nvicEnableVector(COMP4_5_6_IRQn, STM32_COMP_1_2_3_IRQ_PRIORITY);
+#endif
+#endif
+
+#if STM32_COMP_USE_COMP6
+  /* Driver initialization.*/
+  compObjectInit(&COMPD6);
+  COMPD6.reg = COMP6;
+  COMPD6.reg->CSR = 0;
+#if STM32_COMP_USE_INTERRUPTS
+  nvicEnableVector(COMP4_5_6_IRQn, STM32_COMP_1_2_3_IRQ_PRIORITY);
+#endif
+#endif
+
+#if STM32_COMP_USE_COMP7
+  /* Driver initialization.*/
+  compObjectInit(&COMPD7);
+  COMPD7.reg = COMP7;
+  COMPD7.reg->CSR = 0;
+#if STM32_COMP_USE_INTERRUPTS
+  nvicEnableVector(COMP7_IRQn, STM32_COMP_7_IRQ_PRIORITY);
+#endif
+#endif
+
+}
+
+/**
+ * @brief  COMP1, COMP2, COMP3 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector140) {
+  uint32_t pr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  pr = EXTI->PR;
+  pr &= EXTI->IMR & ((1U << 21) | (1U << 22) | (1U << 29));
+  EXTI->PR = pr;
+#if STM32_COMP_USE_COMP1
+  if (pr & (1U << 21) && COMPD1.config->cb != NULL)
+    COMPD1.config->cb(&COMPD1);
+#endif
+#if STM32_COMP_USE_COMP2
+  if (pr & (1U << 22) && COMPD2.config->cb != NULL)
+    COMPD2.config->cb(&COMPD2);
+#endif
+#if STM32_COMP_USE_COMP3
+  if (pr & (1U << 29) && COMPD3.config->cb != NULL)
+    COMPD3.config->cb(&COMPD3);
+#endif
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   COMP4, COMP5, COMP6 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector144) {
+  uint32_t pr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  pr = EXTI->PR;
+  pr &= EXTI->IMR & ((1U << 30) | (1U << 31));
+  EXTI->PR = pr;
+#if STM32_COMP_USE_COMP4
+  if (pr & (1U << 30) && COMPD4.config->cb != NULL)
+    COMPD4.config->cb(&COMPD4);
+#endif
+#if STM32_COMP_USE_COMP5
+  if (pr & (1U << 31) && COMPD5.config->cb != NULL)
+    COMPD5.config->cb(&COMPD5);
+#endif
+
+#if STM32_COMP_USE_COMP6
+  pr = EXTI->PR2 & EXTI->IMR2 & (1U << 0);
+  EXTI->PR2 = pr;
+  if (pr & (1U << 0) && COMPD6.config->cb != NULL)
+    COMPD6.config->cb(&COMPD6);
+#endif
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   COMP7 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector148) {
+  uint32_t pr2;
+
+  OSAL_IRQ_PROLOGUE();
+
+  pr2 = EXTI->PR2;
+  pr2 = EXTI->IMR & (1U << 1);
+  EXTI->PR2 = pr2;
+#if STM32_COMP_USE_COMP7
+  if (pr2 & (1U << 1) && COMPD7.config->cb != NULL)
+    COMPD7.config->cb(&COMPD7);
+#endif
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   Configures and activates an EXT channel (used by comp)
+ *
+ * @param[in] compp      pointer to the @p COMPDriver object
+ * @param[in] channel    EXT channel
+ *
+ * @notapi
+ */
+void comp_ext_lld_channel_enable(COMPDriver *compp, uint32_t channel) {
+  uint32_t cmask = (1 << (channel & 0x1F));
+
+  /* Don't touch other channels */
+  if (channel < 21 || channel > 33) {
+      return;
+  }
+
+#if STM32_EXTI_NUM_LINES > 32
+  if (channel < 32) {
+#endif
+    /* Masked out lines must not be touched by this driver.*/
+    if ((cmask & STM32_EXTI_IMR_MASK) != 0U) {
+      return;
+    }
+
+    /* Programming edge registers.*/
+    if (compp->config->irq_mode == COMP_IRQ_RISING || compp->config->irq_mode == COMP_IRQ_BOTH)
+      EXTI->RTSR |= cmask;
+    else
+      EXTI->RTSR &= ~cmask;
+    if (compp->config->irq_mode == COMP_IRQ_FALLING || compp->config->irq_mode == COMP_IRQ_BOTH)
+      EXTI->FTSR |= cmask;
+    else
+      EXTI->FTSR &= ~cmask;
+
+    /* Programming interrupt and event registers.*/
+    EXTI->IMR |= cmask;
+    EXTI->EMR &= ~cmask;
+
+#if STM32_EXTI_NUM_LINES > 32
+  }
+  else {
+    /* Masked out lines must not be touched by this driver.*/
+    if ((cmask & STM32_EXTI_IMR2_MASK) != 0U) {
+      return;
+    }
+
+    /* Programming edge registers.*/
+    if (compp->config->irq_mode == COMP_IRQ_RISING || compp->config->irq_mode == COMP_IRQ_BOTH)
+      EXTI->RTSR2 |= cmask;
+    else
+      EXTI->RTSR2 &= ~cmask;
+    if (compp->config->irq_mode == COMP_IRQ_FALLING || compp->config->irq_mode == COMP_IRQ_BOTH)
+      EXTI->FTSR2 |= cmask;
+    else
+      EXTI->FTSR2 &= ~cmask;
+
+    /* Programming interrupt and event registers.*/
+    EXTI->IMR2 |= cmask;
+    EXTI->EMR2 &= ~cmask;
+  }
+#endif
+}
+
+/**
+ * @brief   Deactivate an EXT channel (used by comp)
+ *
+ * @param[in] compp      pointer to the @p COMPDriver object
+ * @param[in] channel    EXT channel
+ *
+ * @notapi
+ */
+void comp_ext_lld_channel_disable(COMPDriver *compp, uint32_t channel) {
+
+  (void) compp;
+  uint32_t cmask = (1 << (channel & 0x1F));
+
+#if STM32_EXTI_NUM_LINES > 32
+  if (channel < 32) {
+#endif
+    EXTI->IMR  &= ~cmask;
+    EXTI->EMR  &= ~cmask;
+    EXTI->RTSR &= ~cmask;
+    EXTI->FTSR &= ~cmask;
+    EXTI->PR    =  cmask;
+#if STM32_EXTI_NUM_LINES > 32
+  }
+  else {
+    EXTI->IMR2  &= ~cmask;
+    EXTI->EMR2  &= ~cmask;
+    EXTI->RTSR2 &= ~cmask;
+    EXTI->FTSR2 &= ~cmask;
+    EXTI->PR2    =  cmask;
+  }
+#endif
+}
+
+/**
+ * @brief   Configures and activates the COMP peripheral.
+ *
+ * @param[in] compp      pointer to the @p COMPDriver object
+ *
+ * @notapi
+ */
+void comp_lld_start(COMPDriver *compp) {
+
+  // Apply CSR Execpt the enable bit.
+  compp->reg->CSR = compp->config->csr & ~COMP_CSR_COMPxEN;
+
+  // Inverted output
+  if (compp->config->output_mode == COMP_OUTPUT_INVERTED)
+    compp->reg->CSR |= COMP_CSR_COMPxPOL;
+
+#if STM32_COMP_USE_INTERRUPTS
+#if STM32_COMP_USE_COMP1
+  if (compp == &COMPD1) {
+    comp_ext_lld_channel_enable(compp, 21);
+  }
+#endif
+
+#if STM32_COMP_USE_COMP2
+  if (compp == &COMPD2) {
+    comp_ext_lld_channel_enable(compp, 22);
+  }
+#endif
+
+#if STM32_COMP_USE_COMP3
+  if (compp == &COMPD3) {
+    comp_ext_lld_channel_enable(compp, 29);
+  }
+#endif
+
+#if STM32_COMP_USE_COMP4
+  if (compp == &COMPD4) {
+    comp_ext_lld_channel_enable(compp, 30);
+  }
+#endif
+
+#if STM32_COMP_USE_COMP5
+  if (compp == &COMPD5) {
+    comp_ext_lld_channel_enable(compp, 31);
+  }
+#endif
+
+#if STM32_COMP_USE_COMP6
+  if (compp == &COMPD6) {
+    comp_ext_lld_channel_enable(compp, 32);
+  }
+#endif
+
+#if STM32_COMP_USE_COMP7
+  if (compp == &COMPD7) {
+    comp_ext_lld_channel_enable(compp, 33);
+  }
+#endif
+#endif
+
+}
+
+/**
+ * @brief   Deactivates the comp peripheral.
+ *
+ * @param[in] compp      pointer to the @p COMPDriver object
+ *
+ * @notapi
+ */
+void comp_lld_stop(COMPDriver *compp) {
+
+  if (compp->state == COMP_READY) {
+
+    compp->reg->CSR = 0;
+  }
+
+#if STM32_COMP_USE_INTERRUPTS
+#if STM32_COMP_USE_COMP1
+  if (compp == &COMPD1) {
+    comp_ext_lld_channel_disable(compp, 21);
+  }
+#endif
+
+#if STM32_COMP_USE_COMP2
+  if (compp == &COMPD2) {
+    comp_ext_lld_channel_disable(compp, 22);
+  }
+#endif
+
+#if STM32_COMP_USE_COMP3
+  if (compp == &COMPD3) {
+    comp_ext_lld_channel_disable(compp, 29);
+  }
+#endif
+
+#if STM32_COMP_USE_COMP4
+  if (compp == &COMPD4) {
+    comp_ext_lld_channel_disable(compp, 30);
+  }
+#endif
+
+#if STM32_COMP_USE_COMP5
+  if (compp == &COMPD5) {
+    comp_ext_lld_channel_disable(compp, 31);
+  }
+#endif
+
+#if STM32_COMP_USE_COMP6
+  if (compp == &COMPD6) {
+    comp_ext_lld_channel_disable(compp, 32);
+  }
+#endif
+
+#if STM32_COMP_USE_COMP7
+  if (compp == &COMPD7) {
+    comp_ext_lld_channel_disable(compp, 33);
+  }
+#endif
+#endif
+
+}
+
+/**
+ * @brief   Enables the output.
+ *
+ * @param[in] compp      pointer to the @p COMPDriver object
+ *
+ * @notapi
+ */
+void comp_lld_enable(COMPDriver *compp) {
+
+   compp->reg->CSR |= COMP_CSR_COMPxEN; /* Enable */
+}
+
+/**
+ * @brief   Disables the output.
+ *
+ * @param[in] compp      pointer to the @p COMPDriver object
+ *
+ * @notapi
+ */
+void comp_lld_disable(COMPDriver *compp) {
+
+  compp->reg->CSR &= ~COMP_CSR_COMPxEN; /* Disable */
+}
+
+#endif /* HAL_USE_COMP */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/COMPv1/hal_comp_lld.h b/os/hal/ports/STM32/LLD/COMPv1/hal_comp_lld.h
new file mode 100644
index 0000000..bb40327
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/COMPv1/hal_comp_lld.h
@@ -0,0 +1,482 @@
+/*
+    ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio
+              Copyright (C) 2017 Fabien Poussin (fabien.poussin (at) google's mail)
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/comp_lld.h
+ * @brief   STM32 Comparator subsystem low level driver header.
+ *
+ * @addtogroup COMP
+ * @{
+ */
+
+#ifndef HAL_COMP_LLD_H_
+#define HAL_COMP_LLD_H_
+
+#include "hal.h"
+
+#if HAL_USE_COMP || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+
+#define STM32_COMP_InvertingInput_1_4VREFINT          ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */
+#define STM32_COMP_InvertingInput_1_2VREFINT          COMP_CSR_COMPxINSEL_0  /*!< 1/2 VREFINT connected to comparator inverting input */
+#define STM32_COMP_InvertingInput_3_4VREFINT          COMP_CSR_COMPxINSEL_1  /*!< 3/4 VREFINT connected to comparator inverting input */
+#define STM32_COMP_InvertingInput_VREFINT             ((uint32_t)0x00000030) /*!< VREFINT connected to comparator inverting input */
+#define STM32_COMP_InvertingInput_DAC1OUT1            COMP_CSR_COMPxINSEL_2  /*!< DAC1_OUT1 (PA4) connected to comparator inverting input */
+#define STM32_COMP_InvertingInput_DAC1OUT2            ((uint32_t)0x00000050) /*!< DAC1_OUT2 (PA5) connected to comparator inverting input */
+
+#define STM32_COMP_InvertingInput_IO1                 ((uint32_t)0x00000060) /*!< I/O1 (PA0 for COMP1, PA2 for COMP2, PD15 for COMP3,
+                                                                            PE8 for COMP4, PD13 for COMP5, PD10 for COMP6,
+                                                                            PC0 for COMP7) connected to comparator inverting input */
+
+#define STM32_COMP_InvertingInput_IO2                 COMP_CSR_COMPxINSEL    /*!< I/O2 (PB12 for COMP3, PB2 for COMP4, PB10 for COMP5,
+                                                                            PB15 for COMP6) connected to comparator inverting input.
+                                                                            It is valid only for STM32F303xC devices */
+
+#define STM32_COMP_InvertingInput_DAC2OUT1            COMP_CSR_COMPxINSEL_3  /*!< DAC2_OUT1 (PA6) connected to comparator inverting input */
+
+
+#define STM32_COMP_NonInvertingInput_IO1                 ((uint32_t)0x00000000) /*!< I/O1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3,
+                                                                               PB0 for COMP4, PD12 for COMP5, PD11 for COMP6,
+                                                                               PA0 for COMP7) connected to comparator non inverting input */
+
+#define STM32_COMP_NonInvertingInput_IO2                 COMP_CSR_COMPxNONINSEL /*!< I/O2 (PA3 for COMP2, PD14 for COMP3, PE7 for COMP4, PB13 for COMP5,
+                                                                               PB11 for COMP6, PC1 for COMP7) connected to comparator non inverting input */
+
+
+#define STM32_COMP_Output_None                            ((uint32_t)0x00000000)   /*!< COMP output isn't connected to other peripherals */
+
+/* Output Redirection common for all comparators COMP1...COMP7 */
+#define STM32_COMP_Output_TIM1BKIN                        COMP_CSR_COMPxOUTSEL_0   /*!< COMP output connected to TIM1 Break Input (BKIN) */
+#define STM32_COMP_Output_TIM1BKIN2                       ((uint32_t)0x00000800)   /*!< COMP output connected to TIM1 Break Input 2 (BKIN2) */
+#define STM32_COMP_Output_TIM8BKIN                        ((uint32_t)0x00000C00)   /*!< COMP output connected to TIM8 Break Input (BKIN) */
+#define STM32_COMP_Output_TIM8BKIN2                       ((uint32_t)0x00001000)   /*!< COMP output connected to TIM8 Break Input 2 (BKIN2) */
+#define STM32_COMP_Output_TIM1BKIN2_TIM8BKIN2             ((uint32_t)0x00001400)   /*!< COMP output connected to TIM1 Break Input 2 and TIM8 Break Input 2 */
+#define STM32_COMP_Output_TIM20BKIN                       ((uint32_t)0x00003000)   /*!< COMP output connected to TIM20 Break Input (BKIN) */
+#define STM32_COMP_Output_TIM20BKIN2                      ((uint32_t)0x00003400)  /*!< COMP output connected to TIM20 Break Input 2 (BKIN2) */
+#define STM32_COMP_Output_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2  ((uint32_t)0x00001400)   /*!< COMP output connected to TIM1 Break Input 2, TIM8 Break Input 2 and TIM20 Break Input2 */
+
+/* Output Redirection common for COMP1 and COMP2 */
+#define STM32_COMP_Output_TIM1OCREFCLR                    ((uint32_t)0x00001800)   /*!< COMP output connected to TIM1 OCREF Clear */
+#define STM32_COMP_Output_TIM1IC1                         ((uint32_t)0x00001C00)   /*!< COMP output connected to TIM1 Input Capture 1 */
+#define STM32_COMP_Output_TIM2IC4                         ((uint32_t)0x00002000)   /*!< COMP output connected to TIM2 Input Capture 4 */
+#define STM32_COMP_Output_TIM2OCREFCLR                    ((uint32_t)0x00002400)   /*!< COMP output connected to TIM2 OCREF Clear */
+#define STM32_COMP_Output_TIM3IC1                         ((uint32_t)0x00002800)   /*!< COMP output connected to TIM3 Input Capture 1 */
+#define STM32_COMP_Output_TIM3OCREFCLR                    ((uint32_t)0x00002C00)   /*!< COMP output connected to TIM3 OCREF Clear */
+
+/* Output Redirection specific to COMP2 */
+#define STM32_COMP_Output_HRTIM1_FLT6                     ((uint32_t)0x00003000)   /*!< COMP output connected to HRTIM1 FLT6 */
+#define STM32_COMP_Output_HRTIM1_EE1_2                    ((uint32_t)0x00003400)   /*!< COMP output connected to HRTIM1 EE1_2*/
+#define STM32_COMP_Output_HRTIM1_EE6_2                    ((uint32_t)0x00003800)   /*!< COMP output connected to HRTIM1 EE6_2 */
+#define STM32_COMP_Output_TIM20OCREFCLR                   ((uint32_t)0x00003C00)   /*!< COMP output connected to TIM20 OCREF Clear */
+
+/* Output Redirection specific to COMP3 */
+#define STM32_COMP_Output_TIM4IC1                         ((uint32_t)0x00001C00)   /*!< COMP output connected to TIM4 Input Capture 1 */
+#define STM32_COMP_Output_TIM3IC2                         ((uint32_t)0x00002000)   /*!< COMP output connected to TIM3 Input Capture 2 */
+#define STM32_COMP_Output_TIM15IC1                        ((uint32_t)0x00002800)   /*!< COMP output connected to TIM15 Input Capture 1 */
+#define STM32_COMP_Output_TIM15BKIN                       ((uint32_t)0x00002C00)   /*!< COMP output connected to TIM15 Break Input (BKIN) */
+
+/* Output Redirection specific to COMP4 */
+#define STM32_COMP_Output_TIM3IC3                         ((uint32_t)0x00001800)   /*!< COMP output connected to TIM3 Input Capture 3 */
+#define STM32_COMP_Output_TIM8OCREFCLR                    ((uint32_t)0x00001C00)   /*!< COMP output connected to TIM8 OCREF Clear */
+#define STM32_COMP_Output_TIM15IC2                        ((uint32_t)0x00002000)   /*!< COMP output connected to TIM15 Input Capture 2 */
+#define STM32_COMP_Output_TIM4IC2                         ((uint32_t)0x00002400)   /*!< COMP output connected to TIM4 Input Capture 2 */
+#define STM32_COMP_Output_TIM15OCREFCLR                   ((uint32_t)0x00002800)   /*!< COMP output connected to TIM15 OCREF Clear */
+
+#define STM32_COMP_Output_HRTIM1_FLT7                     ((uint32_t)0x00003000)   /*!< COMP output connected to HRTIM1 FLT7 */
+#define STM32_COMP_Output_HRTIM1_EE2_2                    ((uint32_t)0x00003400)   /*!< COMP output connected to HRTIM1 EE2_2*/
+#define STM32_COMP_Output_HRTIM1_EE7_2                    ((uint32_t)0x00003800)   /*!< COMP output connected to HRTIM1 EE7_2 */
+
+/* Output Redirection specific to COMP5 */
+#define STM32_COMP_Output_TIM2IC1                         ((uint32_t)0x00001800)   /*!< COMP output connected to TIM2 Input Capture 1 */
+#define STM32_COMP_Output_TIM17IC1                        ((uint32_t)0x00002000)   /*!< COMP output connected to TIM17 Input Capture 1 */
+#define STM32_COMP_Output_TIM4IC3                         ((uint32_t)0x00002400)   /*!< COMP output connected to TIM4 Input Capture 3 */
+#define STM32_COMP_Output_TIM16BKIN                       ((uint32_t)0x00002800)   /*!< COMP output connected to TIM16 Break Input (BKIN) */
+
+/* Output Redirection specific to COMP6 */
+#define STM32_COMP_Output_TIM2IC2                         ((uint32_t)0x00001800)   /*!< COMP output connected to TIM2 Input Capture 2 */
+#define STM32_COMP_Output_COMP6TIM2OCREFCLR               ((uint32_t)0x00002000)   /*!< COMP output connected to TIM2 OCREF Clear */
+#define STM32_COMP_Output_TIM16OCREFCLR                   ((uint32_t)0x00002400)   /*!< COMP output connected to TIM16 OCREF Clear */
+#define STM32_COMP_Output_TIM16IC1                        ((uint32_t)0x00002800)   /*!< COMP output connected to TIM16 Input Capture 1 */
+#define STM32_COMP_Output_TIM4IC4                         ((uint32_t)0x00002C00)   /*!< COMP output connected to TIM4 Input Capture 4 */
+
+#define STM32_COMP_Output_HRTIM1_FLT8                     ((uint32_t)0x00003000)   /*!< COMP output connected to HRTIM1 FLT8 */
+#define STM32_COMP_Output_HRTIM1_EE3_2                    ((uint32_t)0x00003400)   /*!< COMP output connected to HRTIM1 EE3_2*/
+#define STM32_COMP_Output_HRTIM1_EE8_2                    ((uint32_t)0x00003800)   /*!< COMP output connected to HRTIM1 EE8_2 */
+
+/* Output Redirection specific to COMP7 */
+#define STM32_COMP_Output_TIM2IC3                         ((uint32_t)0x00002000)   /*!< COMP output connected to TIM2 Input Capture 3 */
+#define STM32_COMP_Output_TIM1IC2                         ((uint32_t)0x00002400)   /*!< COMP output connected to TIM1 Input Capture 2 */
+#define STM32_COMP_Output_TIM17OCREFCLR                   ((uint32_t)0x00002800)   /*!< COMP output connected to TIM16 OCREF Clear */
+#define STM32_COMP_Output_TIM17BKIN                       ((uint32_t)0x00002C00)   /*!< COMP output connected to TIM16 Break Input (BKIN) */
+
+/* No blanking source can be selected for all comparators */
+#define STM32_COMP_BlankingSrce_None                   ((uint32_t)0x00000000)    /*!< No blanking source */
+
+/* Blanking source common for COMP1, COMP2, COMP3 and COMP7 */
+#define STM32_COMP_BlankingSrce_TIM1OC5                COMP_CSR_COMPxBLANKING_0  /*!< TIM1 OC5 selected as blanking source for compartor */
+
+/* Blanking source common for COMP1 and COMP2 */
+#define STM32_COMP_BlankingSrce_TIM2OC3                COMP_CSR_COMPxBLANKING_1  /*!< TIM2 OC5 selected as blanking source for compartor */
+
+/* Blanking source common for COMP1, COMP2 and COMP5 */
+#define STM32_COMP_BlankingSrce_TIM3OC3                ((uint32_t)0x000C0000)    /*!< TIM2 OC3 selected as blanking source for compartor */
+
+/* Blanking source common for COMP3 and COMP6 */
+#define STM32_COMP_BlankingSrce_TIM2OC4                ((uint32_t)0x000C0000)  /*!< TIM2 OC4 selected as blanking source for compartor */
+
+/* Blanking source common for COMP4, COMP5, COMP6 and COMP7 */
+#define STM32_COMP_BlankingSrce_TIM8OC5                COMP_CSR_COMPxBLANKING_1  /*!< TIM8 OC5 selected as blanking source for compartor */
+
+/* Blanking source for COMP4 */
+#define STM32_COMP_BlankingSrce_TIM3OC4                COMP_CSR_COMPxBLANKING_0  /*!< TIM3 OC4 selected as blanking source for compartor */
+#define STM32_COMP_BlankingSrce_TIM15OC1               ((uint32_t)0x000C0000)    /*!< TIM15 OC1 selected as blanking source for compartor */
+
+/* Blanking source common for COMP6 and COMP7 */
+#define STM32_COMP_BlankingSrce_TIM15OC2               COMP_CSR_COMPxBLANKING_2    /*!< TIM15 OC2 selected as blanking source for compartor */
+
+#define STM32_COMP_OutputPol_NonInverted              ((uint32_t)0x00000000)  /*!< COMP output on GPIO isn't inverted */
+#define STM32_COMP_OutputPol_Inverted                 COMP_CSR_COMPxPOL       /*!< COMP output on GPIO is inverted */
+
+#define STM32_COMP_Hysteresis_No                      0x00000000           /*!< No hysteresis */
+#define STM32_COMP_Hysteresis_Low                     COMP_CSR_COMPxHYST_0 /*!< Hysteresis level low */
+#define STM32_COMP_Hysteresis_Medium                  COMP_CSR_COMPxHYST_1 /*!< Hysteresis level medium */
+#define STM32_COMP_Hysteresis_High                    COMP_CSR_COMPxHYST   /*!< Hysteresis level high */
+
+#define STM32_COMP_Mode_HighSpeed                     0x00000000            /*!< High Speed */
+#define STM32_COMP_Mode_MediumSpeed                   COMP_CSR_COMPxMODE_0  /*!< Medium Speed */
+#define STM32_COMP_Mode_LowPower                      COMP_CSR_COMPxMODE_1  /*!< Low power mode */
+#define STM32_COMP_Mode_UltraLowPower                 COMP_CSR_COMPxMODE    /*!< Ultra-low power mode */
+
+/* When output polarity is not inverted, comparator output is high when
+   the non-inverting input is at a higher voltage than the inverting input */
+#define STM32_COMP_OutputLevel_High                   COMP_CSR_COMPxOUT
+/* When output polarity is not inverted, comparator output is low when
+   the non-inverting input is at a lower voltage than the inverting input*/
+#define STM32_COMP_OutputLevel_Low                    ((uint32_t)0x00000000)
+
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F303x8) \
+|| defined(STM32F318xx) || defined(STM32F328xx) || defined(STM32F334x8)
+#define STM32_HAS_COMP1 FALSE
+#define STM32_HAS_COMP2 TRUE
+#define STM32_HAS_COMP3 FALSE
+#define STM32_HAS_COMP4 TRUE
+#define STM32_HAS_COMP5 FALSE
+#define STM32_HAS_COMP6 TRUE
+#define STM32_HAS_COMP7 FALSE
+
+#elif defined(STM32F302xc) || defined(STM32F302xe)
+#define STM32_HAS_COMP1 TRUE
+#define STM32_HAS_COMP2 TRUE
+#define STM32_HAS_COMP3 FALSE
+#define STM32_HAS_COMP4 TRUE
+#define STM32_HAS_COMP5 FALSE
+#define STM32_HAS_COMP6 TRUE
+#define STM32_HAS_COMP7 FALSE
+
+#elif defined(STM32F303xC) || defined(STM32F303xE) || defined(STM32F358xx) || defined(STM32F398xx)
+#define STM32_HAS_COMP1 TRUE
+#define STM32_HAS_COMP2 TRUE
+#define STM32_HAS_COMP3 TRUE
+#define STM32_HAS_COMP4 TRUE
+#define STM32_HAS_COMP5 TRUE
+#define STM32_HAS_COMP6 TRUE
+#define STM32_HAS_COMP7 TRUE
+
+#elif defined(STM32F373xx) || defined(STM32F378xx) || defined(STM32L0XX) || defined(STM32L1XX) \
+  || defined(STM32F051x8) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F078xx) \
+  || defined(STM32F072xb) || defined(STM32F071xb)
+#define STM32_HAS_COMP1 TRUE
+#define STM32_HAS_COMP2 TRUE
+#define STM32_HAS_COMP3 FALSE
+#define STM32_HAS_COMP4 FALSE
+#define STM32_HAS_COMP5 FALSE
+#define STM32_HAS_COMP6 FALSE
+#define STM32_HAS_COMP7 FALSE
+
+#else
+#define STM32_HAS_COMP1 FALSE
+#define STM32_HAS_COMP2 FALSE
+#define STM32_HAS_COMP3 FALSE
+#define STM32_HAS_COMP4 FALSE
+#define STM32_HAS_COMP5 FALSE
+#define STM32_HAS_COMP6 FALSE
+#define STM32_HAS_COMP7 FALSE
+
+#endif
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+
+/**
+ * @brief   COMP INTERRUPTS.
+ * @details If set to @p TRUE the support for COMPD1 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_COMP_USE_INTERRUPTS) || defined(__DOXYGEN__)
+#define STM32_COMP_USE_INTERRUPTS             FALSE
+#endif
+
+/**
+ * @brief   COMPD1 driver enable switch.
+ * @details If set to @p TRUE the support for COMPD1 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_COMP_USE_COMP1) || defined(__DOXYGEN__)
+#define STM32_COMP_USE_COMP1                  FALSE
+#endif
+
+/**
+ * @brief   COMPD2 driver enable switch.
+ * @details If set to @p TRUE the support for COMPD2 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_COMP_USE_COMP2) || defined(__DOXYGEN__)
+#define STM32_COMP_USE_COMP2                  FALSE
+#endif
+
+/**
+ * @brief   COMPD3 driver enable switch.
+ * @details If set to @p TRUE the support for COMPD3 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_COMP_USE_COMP3) || defined(__DOXYGEN__)
+#define STM32_COMP_USE_COMP3                  FALSE
+#endif
+
+/**
+ * @brief   COMPD4 driver enable switch.
+ * @details If set to @p TRUE the support for COMPD4 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_COMP_USE_COMP4) || defined(__DOXYGEN__)
+#define STM32_COMP_USE_COMP4                  FALSE
+#endif
+
+/**
+ * @brief   COMPD5 driver enable switch.
+ * @details If set to @p TRUE the support for COMPD4 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_COMP_USE_COMP5) || defined(__DOXYGEN__)
+#define STM32_COMP_USE_COMP5                  FALSE
+#endif
+
+/**
+ * @brief   COMPD6 driver enable switch.
+ * @details If set to @p TRUE the support for COMPD4 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_COMP_USE_COMP6) || defined(__DOXYGEN__)
+#define STM32_COMP_USE_COMP6                  FALSE
+#endif
+
+/**
+ * @brief   COMPD7 driver enable switch.
+ * @details If set to @p TRUE the support for COMPD4 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_COMP_USE_COMP7) || defined(__DOXYGEN__)
+#define STM32_COMP_USE_COMP7                  FALSE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if STM32_COMP_USE_INTERRUPTS && defined(STM32F0XX)
+#error "Interrupts are shared with EXTI on F0s (lines 21-22)"
+#endif
+
+#if STM32_COMP_USE_INTERRUPTS
+#if !defined(STM32_DISABLE_EXTI21_22_29_HANDLER) || !defined(STM32_DISABLE_EXTI30_32_HANDLER) || !defined(STM32_DISABLE_EXTI33_HANDLER)
+#error "COMP needs these defines in mcuconf to use interrupts: STM32_DISABLE_EXTI21_22_29_HANDLER STM32_DISABLE_EXTI30_32_HANDLER STM32_DISABLE_EXTI33_HANDLER"
+#endif
+#endif
+
+#if STM32_COMP_USE_COMP1 && !STM32_HAS_COMP1
+#error "COMP1 not present in the selected device"
+#endif
+
+#if STM32_COMP_USE_COMP2 && !STM32_HAS_COMP2
+#error "COMP2 not present in the selected device"
+#endif
+
+#if STM32_COMP_USE_COMP3 && !STM32_HAS_COMP3
+#error "COMP3 not present in the selected device"
+#endif
+
+#if STM32_COMP_USE_COMP4 && !STM32_HAS_COMP4
+#error "COMP4 not present in the selected device"
+#endif
+
+#if STM32_COMP_USE_COMP5 && !STM32_HAS_COMP5
+#error "COMP5 not present in the selected device"
+#endif
+
+#if STM32_COMP_USE_COMP6 && !STM32_HAS_COMP6
+#error "COMP6 not present in the selected device"
+#endif
+
+#if STM32_COMP_USE_COMP7 && !STM32_HAS_COMP7
+#error "COMP7 not present in the selected device"
+#endif
+
+#if !STM32_COMP_USE_COMP1 && !STM32_COMP_USE_COMP2 &&                         \
+    !STM32_COMP_USE_COMP3 && !STM32_COMP_USE_COMP4 &&                         \
+    !STM32_COMP_USE_COMP6 && !STM32_COMP_USE_COMP6 &&                         \
+    !STM32_COMP_USE_COMP7
+#error "COMP driver activated but no COMP peripheral assigned"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   COMP output mode.
+ */
+typedef enum {
+  COMP_OUTPUT_NORMAL = 0,
+  COMP_OUTPUT_INVERTED = 1
+} comp_output_mode_t;
+
+/**
+ * @brief   COMP interrupt mode.
+ */
+typedef enum {
+  COMP_IRQ_RISING = 0,
+  COMP_IRQ_FALLING = 1,
+  COMP_IRQ_BOTH = 2
+} comp_irq_mode_t;
+
+/**
+ * @brief   Driver configuration structure.
+ * @note    It could be empty on some architectures.
+ */
+typedef struct {
+  /**
+   * @brief   Ouput mode.
+   */
+  comp_output_mode_t        output_mode;
+
+  /**
+   * @brief   Ouput mode.
+   */
+  comp_irq_mode_t           irq_mode;
+
+  /**
+   * @brief   Callback.
+   */
+  compcallback_t             cb;
+
+  /* End of the mandatory fields.*/
+
+  /**
+   * @brief COMP CSR register initialization data.
+   * @note  The value of this field should normally be equal to zero.
+   */
+  uint32_t                  csr;
+} COMPConfig;
+
+/**
+ * @brief   Structure representing an COMP driver.
+ */
+struct COMPDriver {
+  /**
+   * @brief Driver state.
+   */
+  compstate_t                state;
+  /**
+   * @brief Current configuration data.
+   */
+  const COMPConfig           *config;
+#if defined(COMP_DRIVER_EXT_FIELDS)
+  COMP_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Pointer to the COMPx registers block.
+   */
+  COMP_TypeDef               *reg;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if STM32_COMP_USE_COMP1 && !defined(__DOXYGEN__)
+extern COMPDriver COMPD1;
+#endif
+
+#if STM32_COMP_USE_COMP2 && !defined(__DOXYGEN__)
+extern COMPDriver COMPD2;
+#endif
+
+#if STM32_COMP_USE_COMP3 && !defined(__DOXYGEN__)
+extern COMPDriver COMPD3;
+#endif
+
+#if STM32_COMP_USE_COMP4 && !defined(__DOXYGEN__)
+extern COMPDriver COMPD4;
+#endif
+
+#if STM32_COMP_USE_COMP5 && !defined(__DOXYGEN__)
+extern COMPDriver COMPD5;
+#endif
+
+#if STM32_COMP_USE_COMP6 && !defined(__DOXYGEN__)
+extern COMPDriver COMPD6;
+#endif
+
+#if STM32_COMP_USE_COMP7 && !defined(__DOXYGEN__)
+extern COMPDriver COMPD7;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void comp_lld_init(void);
+  void comp_lld_start(COMPDriver *compp);
+  void comp_lld_stop(COMPDriver *compp);
+  void comp_lld_enable(COMPDriver *compp);
+  void comp_lld_disable(COMPDriver *compp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_COMP */
+
+#endif /* _comp_lld_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c
index 601deca..701b87d 100644..100755
--- a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c
+++ b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c
@@ -15,7 +15,7 @@
 */
 
 /**
- * @file    STM32/CRCv1/crc_lld.c
+ * @file    STM32/CRCv1/hal_crc_lld.c
  * @brief   STM32 CRC subsystem low level driver source.
  *
  * @addtogroup CRC
@@ -155,7 +155,7 @@ void crc_lld_start(CRCDriver *crcp) {
   if (crcp->config == NULL)
     crcp->config = &default_config;
 
-  rccEnableCRC(FALSE);
+  rccEnableCRC();
 
 #if STM32_CRC_PROGRAMMABLE == TRUE
   crcp->crc->INIT = crcp->config->initial_val;
@@ -185,15 +185,15 @@ void crc_lld_start(CRCDriver *crcp) {
     crcp->crc->CR |= CRC_CR_REV_OUT;
   }
 #else
-  osalDbgAssert(crcp->config->initial_val != default_config.initial_val,
+  osalDbgAssert(crcp->config->initial_val == default_config.initial_val,
       "hardware doesn't support programmable initial value");
-  osalDbgAssert(crcp->config->poly_size != default_config.poly_size,
+  osalDbgAssert(crcp->config->poly_size == default_config.poly_size,
       "hardware doesn't support programmable polynomial size");
-  osalDbgAssert(crcp->config->poly != default_config.poly,
+  osalDbgAssert(crcp->config->poly == default_config.poly,
       "hardware doesn't support programmable polynomial");
-  osalDbgAssert(crcp->config->reflect_data != default_config.reflect_data,
+  osalDbgAssert(crcp->config->reflect_data == default_config.reflect_data,
       "hardware doesn't support reflect of input data");
-  osalDbgAssert(crcp->config->reflect_remainder != default_config.reflect_remainder,
+  osalDbgAssert(crcp->config->reflect_remainder == default_config.reflect_remainder,
       "hardware doesn't support reflect of output remainder");
 #endif
 
@@ -234,7 +234,7 @@ void crc_lld_stop(CRCDriver *crcp) {
 #else
   (void)crcp;
 #endif
-  rccDisableCRC(FALSE);
+  rccDisableCRC();
 }
 
 /**
@@ -299,7 +299,7 @@ uint32_t crc_lld_calc(CRCDriver *crcp, size_t n, const void *buf) {
     n--;
   }
 #else
-  osalDbgAssert(n != 0, "STM32 CRC Unit only supports WORD accesses");
+  osalDbgAssert(n == 0, "STM32 CRC Unit only supports WORD accesses");
 #endif
 
 #endif
diff --git a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h
index ecdaf81..213d346 100644
--- a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h
+++ b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h
@@ -15,15 +15,15 @@
 */
 
 /**
- * @file    STM32/CRCv1/crc_lld.h
+ * @file    STM32/CRCv1/hal_crc_lld.h
  * @brief   STM32 CRC subsystem low level driver header.
  *
  * @addtogroup CRC
  * @{
  */
 
-#ifndef _CRC_LLD_H_
-#define _CRC_LLD_H_
+#ifndef HAL_CRC_LLD_H_
+#define HAL_CRC_LLD_H_
 
 #if (HAL_USE_CRC == TRUE) || defined(__DOXYGEN__)
 
@@ -244,6 +244,6 @@ extern "C" {
 
 #endif /* HAL_USE_CRC */
 
-#endif /* _CRC_LLD_H_ */
+#endif /* HAL_CRC_LLD_H_ */
 
 /** @} */
diff --git a/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c b/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c
index aba029f..b7c9b49 100644
--- a/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c
+++ b/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c
@@ -15,11 +15,10 @@
 */
 
 /**
- * @file    stm32_dma2d.c
+ * @file    hal_stm32_dma2d.c
  * @brief   DMA2D/Chrom-ART driver.
  */
 
-#include "ch.h"
 #include "hal.h"
 
 #include "hal_stm32_dma2d.h"
diff --git a/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.h b/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.h
index 01f0941..c06ab62 100644
--- a/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.h
+++ b/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.h
@@ -15,15 +15,15 @@
 */
 
 /**
- * @file    stm32_dma2d.h
+ * @file    hal_stm32_dma2d.h
  * @brief   DMA2D/Chrom-ART driver.
  *
  * @addtogroup dma2d
  * @{
  */
 
-#ifndef _STM32_DMA2D_H_
-#define _STM32_DMA2D_H_
+#ifndef HAL_STM32_DMA2D_H_
+#define HAL_STM32_DMA2D_H_
 
 /**
  * @brief   Using the DMA2D driver.
@@ -659,6 +659,6 @@ extern "C" {
 
 #endif  /* STM32_DMA2D_USE_DMA2D */
 
-#endif  /* _STM32_DMA2D_H_ */
+#endif  /* HAL_STM32_DMA2D_H_ */
 
 /** @} */
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c
index 8b1082c..71c6ada 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c
@@ -15,7 +15,7 @@
 */
 
 /**
- * @file    fsmc.c
+ * @file    hal_fsmc.c
  * @brief   FSMC Driver subsystem low level driver source template.
  *
  * @addtogroup FSMC
@@ -96,7 +96,11 @@ void fsmc_init(void) {
 #endif
 
 #if (defined(STM32F427xx) || defined(STM32F437xx) || \
-     defined(STM32F429xx) || defined(STM32F439xx))
+     defined(STM32F429xx) || defined(STM32F439xx) || \
+     defined(STM32F745xx) || defined(STM32F746xx) || \
+     defined(STM32F756xx) || defined(STM32F767xx) || \
+     defined(STM32F769xx) || defined(STM32F777xx) || \
+     defined(STM32F779xx))
   #if STM32_USE_FSMC_SDRAM
     FSMCD1.sdram = (FSMC_SDRAM_TypeDef *)FSMC_Bank5_6_R_BASE;
   #endif
@@ -124,7 +128,7 @@ void fsmc_start(FSMCDriver *fsmcp) {
       rccResetFSMC();
 #endif
       rccEnableFSMC(FALSE);
-#if (!STM32_NAND_USE_EXT_INT && HAL_USE_NAND)
+#if HAL_USE_NAND
       nvicEnableVector(STM32_FSMC_NUMBER, STM32_FSMC_FSMC1_IRQ_PRIORITY);
 #endif
     }
@@ -152,10 +156,10 @@ void fsmc_stop(FSMCDriver *fsmcp) {
     /* Disables the peripheral.*/
 #if STM32_FSMC_USE_FSMC1
     if (&FSMCD1 == fsmcp) {
-#if (!STM32_NAND_USE_EXT_INT && HAL_USE_NAND)
+#if HAL_USE_NAND
       nvicDisableVector(STM32_FSMC_NUMBER);
 #endif
-      rccDisableFSMC(FALSE);
+      rccDisableFSMC();
     }
 #endif /* STM32_FSMC_USE_FSMC1 */
 
@@ -163,7 +167,6 @@ void fsmc_stop(FSMCDriver *fsmcp) {
   }
 }
 
-#if !STM32_NAND_USE_EXT_INT
 /**
  * @brief   FSMC shared interrupt handler.
  *
@@ -184,7 +187,6 @@ CH_IRQ_HANDLER(STM32_FSMC_HANDLER) {
 #endif
   CH_IRQ_EPILOGUE();
 }
-#endif /* !STM32_NAND_USE_EXT_INT */
 
 #endif /* HAL_USE_FSMC */
 
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h
index 7889b01..80c5d26 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h
@@ -15,15 +15,15 @@
 */
 
 /**
- * @file    fsmc.h
+ * @file    hal_fsmc.h
  * @brief   FSMC Driver subsystem low level driver header.
  *
  * @addtogroup FSMC
  * @{
  */
 
-#ifndef _FSMC_H_
-#define _FSMC_H_
+#ifndef HAL_FSMC_H_
+#define HAL_FSMC_H_
 
 #if (HAL_USE_FSMC == TRUE) || defined(__DOXYGEN__)
 
@@ -35,7 +35,11 @@
  * (Re)define if needed base address constants supplied in ST's CMSIS
  */
 #if (defined(STM32F427xx) || defined(STM32F437xx) || \
-     defined(STM32F429xx) || defined(STM32F439xx))
+     defined(STM32F429xx) || defined(STM32F439xx) || \
+     defined(STM32F745xx) || defined(STM32F746xx) || \
+     defined(STM32F756xx) || defined(STM32F767xx) || \
+     defined(STM32F769xx) || defined(STM32F777xx) || \
+     defined(STM32F779xx))
   #if !defined(FSMC_Bank1_R_BASE)
   #define FSMC_Bank1_R_BASE               (FMC_R_BASE + 0x0000)
   #endif
@@ -80,7 +84,8 @@
 #define FSMC_Bank3_MAP_BASE               ((uint32_t) 0x80000000)
 #define FSMC_Bank4_MAP_BASE               ((uint32_t) 0x90000000)
 #if (defined(STM32F427xx) || defined(STM32F437xx) || \
-     defined(STM32F429xx) || defined(STM32F439xx))
+     defined(STM32F429xx) || defined(STM32F439xx) || \
+     defined(STM32F7))
   #define FSMC_Bank5_MAP_BASE             ((uint32_t) 0xC0000000)
   #define FSMC_Bank6_MAP_BASE             ((uint32_t) 0xD0000000)
 #endif
@@ -157,7 +162,8 @@ typedef struct {
 } FSMC_SRAM_NOR_TypeDef;
 
 #if (defined(STM32F427xx) || defined(STM32F437xx) || \
-     defined(STM32F429xx) || defined(STM32F439xx))
+     defined(STM32F429xx) || defined(STM32F439xx) || \
+     defined(STM32F7))
 
 typedef struct {
   __IO uint32_t SDCR1;              /**< SDRAM control register (bank 1) */
@@ -174,10 +180,15 @@ typedef struct {
 /**
  * @brief   PCR register
  */
-#define  FSMC_PCR_PWAITEN         ((uint32_t)0x00000002)
-#define  FSMC_PCR_PBKEN           ((uint32_t)0x00000004)
-#define  FSMC_PCR_PTYP            ((uint32_t)0x00000008)
-#define  FSMC_PCR_ECCEN           ((uint32_t)0x00000040)
+#define  FSMC_PCR_PWAITEN         ((uint32_t)1 << 1)
+#define  FSMC_PCR_PBKEN           ((uint32_t)1 << 2)
+#define  FSMC_PCR_PTYP            ((uint32_t)1 << 3)
+#define  FSMC_PCR_PWID_8          ((uint32_t)0 << 4)
+#define  FSMC_PCR_PWID_16         ((uint32_t)1 << 4)
+#define  FSMC_PCR_PWID_RESERVED1  ((uint32_t)2 << 4)
+#define  FSMC_PCR_PWID_RESERVED2  ((uint32_t)3 << 4)
+#define  FSMC_PCR_PWID_MASK       ((uint32_t)3 << 4)
+#define  FSMC_PCR_ECCEN           ((uint32_t)1 << 6)
 #define  FSMC_PCR_PTYP_PCCARD     0
 #define  FSMC_PCR_PTYP_NAND       FSMC_PCR_PTYP
 
@@ -205,7 +216,8 @@ typedef struct {
 #define  FSMC_BCR_MWID_8          ((uint32_t)0 << 4)
 #define  FSMC_BCR_MWID_16         ((uint32_t)1 << 4)
 #if (defined(STM32F427xx) || defined(STM32F437xx) || \
-     defined(STM32F429xx) || defined(STM32F439xx))
+     defined(STM32F429xx) || defined(STM32F439xx) || \
+     defined(STM32F7))
 #define  FSMC_BCR_MWID_32         ((uint32_t)2 << 4)
 #else
 #define  FSMC_BCR_MWID_RESERVED1  ((uint32_t)2 << 4)
@@ -221,6 +233,14 @@ typedef struct {
 #define  FSMC_BCR_EXTMOD          ((uint32_t)1 << 14)
 #define  FSMC_BCR_ASYNCWAIT       ((uint32_t)1 << 15)
 #define  FSMC_BCR_CBURSTRW        ((uint32_t)1 << 19)
+#if (defined(STM32F427xx) || defined(STM32F437xx) || \
+     defined(STM32F429xx) || defined(STM32F439xx) || \
+     defined(STM32F7))
+#define  FSMC_BCR_CCLKEN          ((uint32_t)1 << 20)
+#endif
+#if (defined(STM32F7))
+#define FSMC_BCR_WFDIS            ((uint32_t)1 << 21)
+#endif
 
 /*===========================================================================*/
 /* Driver pre-compile time settings.                                         */
@@ -238,15 +258,6 @@ typedef struct {
 #define STM32_FSMC_USE_FSMC1             FALSE
 #endif
 
-/**
- * @brief   Internal FSMC interrupt enable switch
- * @details MCUs in 100-pin package has no dedicated interrupt pin for FSMC.
- *          You have to use EXTI module instead to workaround this issue.
- */
-#if !defined(STM32_NAND_USE_EXT_INT) || defined(__DOXYGEN__)
-#define STM32_NAND_USE_EXT_INT          FALSE
-#endif
-
 /** @} */
 
 /*===========================================================================*/
@@ -303,7 +314,8 @@ struct FSMCDriver {
   FSMC_NAND_TypeDef         *nand2;
 #endif
 #if (defined(STM32F427xx) || defined(STM32F437xx) || \
-     defined(STM32F429xx) || defined(STM32F439xx))
+     defined(STM32F429xx) || defined(STM32F439xx) || \
+     defined(STM32F7))
   #if STM32_USE_FSMC_SDRAM
     FSMC_SDRAM_TypeDef       *sdram;
   #endif
@@ -334,6 +346,6 @@ extern "C" {
 
 #endif /* HAL_USE_FSMC */
 
-#endif /* _FSMC_H_ */
+#endif /* HAL_FSMC_H_ */
 
 /** @} */
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c
index 95f47d5..6d727c8 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c
@@ -18,7 +18,7 @@
  */
 
 /**
- * @file    fsmc_sdram.c
+ * @file    hal_fsmc_sdram.c
  * @brief   SDRAM Driver subsystem low level driver source.
  *
  * @addtogroup SDRAM
@@ -28,7 +28,11 @@
 #include "hal.h"
 
 #if (defined(STM32F427xx) || defined(STM32F437xx) || \
-     defined(STM32F429xx) || defined(STM32F439xx))
+     defined(STM32F429xx) || defined(STM32F439xx) || \
+     defined(STM32F745xx) || defined(STM32F746xx) || \
+     defined(STM32F756xx) || defined(STM32F767xx) || \
+     defined(STM32F769xx) || defined(STM32F777xx) || \
+     defined(STM32F779xx))
 
 #if (STM32_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__)
 
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h
index cef6772..c9f9de0 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h
@@ -18,18 +18,22 @@
  */
 
 /**
- * @file    fsmc_sdram.h
+ * @file    hal_fsmc_sdram.h
  * @brief   SDRAM Driver subsystem low level driver header.
  *
  * @addtogroup SDRAM
  * @{
  */
 
-#ifndef _FMC_SDRAM_H_
-#define _FMC_SDRAM_H_
+#ifndef HAL_FMC_SDRAM_H_
+#define HAL_FMC_SDRAM_H_
 
 #if (defined(STM32F427xx) || defined(STM32F437xx) || \
-     defined(STM32F429xx) || defined(STM32F439xx))
+     defined(STM32F429xx) || defined(STM32F439xx) || \
+     defined(STM32F745xx) || defined(STM32F746xx) || \
+     defined(STM32F756xx) || defined(STM32F767xx) || \
+     defined(STM32F769xx) || defined(STM32F777xx) || \
+     defined(STM32F779xx))
 
 #include "hal_fsmc.h"
 
@@ -166,6 +170,6 @@ extern "C" {
 
 #endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */
 
-#endif /* _FMC_SDRAM_H_ */
+#endif /* HAL_FMC_SDRAM_H_ */
 
 /** @} */
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c
index 6f710d4..da13ca5 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c
@@ -15,7 +15,7 @@
 */
 
 /**
- * @file    fsmc_sram.c
+ * @file    hal_fsmc_sram.c
  * @brief   SRAM Driver subsystem low level driver source.
  *
  * @addtogroup SRAM
@@ -128,9 +128,9 @@ void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp) {
               "invalid state");
 
   if (sramp->state == SRAM_STOP) {
-    sramp->sram->BCR  = cfgp->bcr | FSMC_BCR_MBKEN;
     sramp->sram->BTR  = cfgp->btr;
     sramp->sram->BWTR = cfgp->bwtr;
+    sramp->sram->BCR  = cfgp->bcr | FSMC_BCR_MBKEN;
     sramp->state = SRAM_READY;
   }
 }
@@ -145,7 +145,16 @@ void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp) {
 void fsmcSramStop(SRAMDriver *sramp) {
 
   if (sramp->state == SRAM_READY) {
-    sramp->sram->BCR &= ~FSMC_BCR_MBKEN;
+    uint32_t mask = FSMC_BCR_MBKEN;
+#if (defined(STM32F427xx) || defined(STM32F437xx) || \
+     defined(STM32F429xx) || defined(STM32F439xx) || \
+     defined(STM32F745xx) || defined(STM32F746xx) || \
+     defined(STM32F756xx) || defined(STM32F767xx) || \
+     defined(STM32F769xx) || defined(STM32F777xx) || \
+     defined(STM32F779xx))
+    mask |= FSMC_BCR_CCLKEN;
+#endif
+    sramp->sram->BCR &= ~mask;
     sramp->state = SRAM_STOP;
   }
 }
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h
index 529bdc7..5e749a8 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h
@@ -15,15 +15,15 @@
 */
 
 /**
- * @file    fsmc_sram.h
+ * @file    hal_fsmc_sram.h
  * @brief   SRAM Driver subsystem low level driver header.
  *
  * @addtogroup SRAM
  * @{
  */
 
-#ifndef _FSMC_SRAM_H_
-#define _FSMC_SRAM_H_
+#ifndef HAL_FSMC_SRAM_H_
+#define HAL_FSMC_SRAM_H_
 
 #include "hal_fsmc.h"
 
@@ -167,6 +167,6 @@ extern "C" {
 
 #endif /* STM32_USE_FSMC_SRAM */
 
-#endif /* _FSMC_SRAM_H_ */
+#endif /* HAL_FSMC_SRAM_H_ */
 
 /** @} */
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c
index b37c026..5729f92 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c
@@ -15,7 +15,7 @@
 */
 
 /**
- * @file    nand_lld.c
+ * @file    hal_nand_lld.c
  * @brief   NAND Driver subsystem low level driver source.
  *
  * @addtogroup NAND
@@ -33,6 +33,19 @@
   STM32_DMA_GETCHANNEL(STM32_NAND_DMA_STREAM,                             \
                        STM32_FSMC_DMA_CHN)
 
+/**
+ * @brief   Bus width of NAND IC.
+ * @details Must be 8 or 16
+ */
+#if ! defined(STM32_NAND_BUS_WIDTH) || defined(__DOXYGEN__)
+#define STM32_NAND_BUS_WIDTH        8
+#endif
+
+/**
+ * @brief   DMA transaction width on AHB bus in bytes
+ */
+#define AHB_TRANSACTION_WIDTH       2
+
 /*===========================================================================*/
 /* Driver exported variables.                                                */
 /*===========================================================================*/
@@ -62,6 +75,47 @@ NANDDriver NANDD2;
 /*===========================================================================*/
 /* Driver local functions.                                                   */
 /*===========================================================================*/
+
+/**
+ * @brief   Helper function.
+ *
+ * @notapi
+ */
+static void align_check(const void *ptr, uint32_t len) {
+  osalDbgCheck((((uint32_t)ptr % AHB_TRANSACTION_WIDTH) == 0) &&
+                         ((len % AHB_TRANSACTION_WIDTH) == 0) &&
+                         (len >= AHB_TRANSACTION_WIDTH));
+  (void)ptr;
+  (void)len;
+}
+
+/**
+ * @brief   Work around errata in STM32's FSMC core.
+ * @details Constant output clock (if enabled) disappears when CLKDIV value
+ *          sets to 1 (FMC_CLK period = 2 × HCLK periods) AND 8-bit async
+ *          transaction generated on AHB. This workaround eliminates 8-bit
+ *          transactions on bus when you use 8-bit memory. It suitable only
+ *          for 8-bit memory (i.e. PWID bits in PCR register must be set
+ *          to 8-bit mode).
+ *
+ * @notapi
+ */
+static void set_16bit_bus(NANDDriver *nandp) {
+#if STM32_NAND_BUS_WIDTH
+  nandp->nand->PCR |= FSMC_PCR_PWID_16;
+#else
+  (void)nandp;
+#endif
+}
+
+static void set_8bit_bus(NANDDriver *nandp) {
+#if STM32_NAND_BUS_WIDTH
+  nandp->nand->PCR &= ~FSMC_PCR_PWID_16;
+#else
+  (void)nandp;
+#endif
+}
+
 /**
  * @brief   Wakes up the waiting thread.
  *
@@ -117,13 +171,10 @@ static uint32_t calc_eccps(NANDDriver *nandp) {
  * @notapi
  */
 static void nand_ready_isr_enable(NANDDriver *nandp) {
-#if STM32_NAND_USE_EXT_INT
-  nandp->config->ext_nand_isr_enable();
-#else
+
   nandp->nand->SR &= ~(FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS |
-                                          FSMC_SR_ILEN | FSMC_SR_IFEN);
+                                    FSMC_SR_ILEN | FSMC_SR_IFEN);
   nandp->nand->SR |= FSMC_SR_IREN;
-#endif
 }
 
 /**
@@ -134,11 +185,8 @@ static void nand_ready_isr_enable(NANDDriver *nandp) {
  * @notapi
  */
 static void nand_ready_isr_disable(NANDDriver *nandp) {
-#if STM32_NAND_USE_EXT_INT
-  nandp->config->ext_nand_isr_disable();
-#else
+
   nandp->nand->SR &= ~FSMC_SR_IREN;
-#endif
 }
 
 /**
@@ -148,31 +196,24 @@ static void nand_ready_isr_disable(NANDDriver *nandp) {
  *
  * @notapi
  */
-static void nand_isr_handler (NANDDriver *nandp) {
+static void nand_isr_handler(NANDDriver *nandp) {
 
   osalSysLockFromISR();
 
-#if !STM32_NAND_USE_EXT_INT
   osalDbgCheck(nandp->nand->SR & FSMC_SR_IRS); /* spurious interrupt happened */
   nandp->nand->SR &= ~FSMC_SR_IRS;
-#endif
 
   switch (nandp->state){
   case NAND_READ:
     nandp->state = NAND_DMA_RX;
-    dmaStartMemCopy(nandp->dma, nandp->dmamode,
-                    nandp->map_data, nandp->rxdata, nandp->datalen);
+    dmaStartMemCopy(nandp->dma, nandp->dmamode, nandp->map_data, nandp->rxdata,
+                    nandp->datalen/AHB_TRANSACTION_WIDTH);
     /* thread will be waked up from DMA ISR */
     break;
 
-  case NAND_ERASE:
-    /* NAND reports about erase finish */
-    nandp->state = NAND_READY;
-    wakeup_isr(nandp);
-    break;
-
-  case NAND_PROGRAM:
-    /* NAND reports about page programming finish */
+  case NAND_ERASE:      /* NAND reports about erase finish */
+  case NAND_PROGRAM:    /* NAND reports about page programming finish */
+  case NAND_RESET:      /* NAND reports about finished reset recover */
     nandp->state = NAND_READY;
     wakeup_isr(nandp);
     break;
@@ -210,7 +251,7 @@ static void nand_lld_serve_transfer_end_irq(NANDDriver *nandp, uint32_t flags) {
   case NAND_DMA_TX:
     nandp->state = NAND_PROGRAM;
     nandp->map_cmd[0] = NAND_CMD_PAGEPROG;
-    /* thread will be woken from ready_isr() */
+    /* thread will be woken up from ready_isr() */
     break;
 
   case NAND_DMA_RX:
@@ -249,9 +290,9 @@ void nand_lld_init(void) {
   NANDD1.thread   = NULL;
   NANDD1.dma      = STM32_DMA_STREAM(STM32_NAND_DMA_STREAM);
   NANDD1.nand     = FSMCD1.nand1;
-  NANDD1.map_data = (uint8_t*)FSMC_Bank2_MAP_COMMON_DATA;
-  NANDD1.map_cmd  = (uint8_t*)FSMC_Bank2_MAP_COMMON_CMD;
-  NANDD1.map_addr = (uint8_t*)FSMC_Bank2_MAP_COMMON_ADDR;
+  NANDD1.map_data = (void *)FSMC_Bank2_MAP_COMMON_DATA;
+  NANDD1.map_cmd  = (uint16_t *)FSMC_Bank2_MAP_COMMON_CMD;
+  NANDD1.map_addr = (uint16_t *)FSMC_Bank2_MAP_COMMON_ADDR;
   NANDD1.bb_map   = NULL;
 #endif /* STM32_NAND_USE_FSMC_NAND1 */
 
@@ -263,9 +304,9 @@ void nand_lld_init(void) {
   NANDD2.thread   = NULL;
   NANDD2.dma      = STM32_DMA_STREAM(STM32_NAND_DMA_STREAM);
   NANDD2.nand     = FSMCD1.nand2;
-  NANDD2.map_data = (uint8_t*)FSMC_Bank3_MAP_COMMON_DATA;
-  NANDD2.map_cmd  = (uint8_t*)FSMC_Bank3_MAP_COMMON_CMD;
-  NANDD2.map_addr = (uint8_t*)FSMC_Bank3_MAP_COMMON_ADDR;
+  NANDD2.map_data = (void *)FSMC_Bank3_MAP_COMMON_DATA;
+  NANDD2.map_cmd  = (uint16_t *)FSMC_Bank3_MAP_COMMON_CMD;
+  NANDD2.map_addr = (uint16_t *)FSMC_Bank3_MAP_COMMON_ADDR;
   NANDD2.bb_map   = NULL;
 #endif /* STM32_NAND_USE_FSMC_NAND2 */
 }
@@ -280,6 +321,8 @@ void nand_lld_init(void) {
 void nand_lld_start(NANDDriver *nandp) {
 
   bool b;
+  uint32_t dmasize;
+  uint32_t pcr_bus_width;
 
   if (FSMCD1.state == FSMC_STOP)
     fsmc_start(&FSMCD1);
@@ -290,16 +333,33 @@ void nand_lld_start(NANDDriver *nandp) {
                           (stm32_dmaisr_t)nand_lld_serve_transfer_end_irq,
                           (void *)nandp);
     osalDbgAssert(!b, "stream already allocated");
+
+#if AHB_TRANSACTION_WIDTH == 4
+    dmasize = STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD;
+#elif AHB_TRANSACTION_WIDTH == 2
+    dmasize = STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
+#elif AHB_TRANSACTION_WIDTH == 1
+    dmasize = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
+#else
+#error "Incorrect AHB_TRANSACTION_WIDTH"
+#endif
+
     nandp->dmamode = STM32_DMA_CR_CHSEL(NAND_DMA_CHANNEL) |
                      STM32_DMA_CR_PL(STM32_NAND_NAND1_DMA_PRIORITY) |
-                     STM32_DMA_CR_PSIZE_BYTE |
-                     STM32_DMA_CR_MSIZE_BYTE |
+                     dmasize |
                      STM32_DMA_CR_DMEIE |
                      STM32_DMA_CR_TEIE |
                      STM32_DMA_CR_TCIE;
-    /* dmaStreamSetFIFO(nandp->dma,
-                    STM32_DMA_FCR_DMDIS | NAND_STM32_DMA_FCR_FTH_LVL); */
-    nandp->nand->PCR = calc_eccps(nandp) | FSMC_PCR_PTYP | FSMC_PCR_PBKEN;
+
+#if STM32_NAND_BUS_WIDTH == 8
+    pcr_bus_width = FSMC_PCR_PWID_8;
+#elif STM32_NAND_BUS_WIDTH == 16
+    pcr_bus_width = FSMC_PCR_PWID_16;
+#else
+#error "Bus width must be 8 or 16 bits"
+#endif
+    nandp->nand->PCR = pcr_bus_width | calc_eccps(nandp) |
+                       FSMC_PCR_PTYP_NAND | FSMC_PCR_PBKEN;
     nandp->nand->PMEM = nandp->config->pmem;
     nandp->nand->PATT = nandp->config->pmem;
     nandp->isr_handler = nand_isr_handler;
@@ -329,24 +389,28 @@ void nand_lld_stop(NANDDriver *nandp) {
  *
  * @param[in] nandp         pointer to the @p NANDDriver object
  * @param[out] data         pointer to data buffer
- * @param[in] datalen       size of data buffer
+ * @param[in] datalen       size of data buffer in bytes
  * @param[in] addr          pointer to address buffer
  * @param[in] addrlen       length of address
  * @param[out] ecc          pointer to store computed ECC. Ignored when NULL.
  *
  * @notapi
  */
-void nand_lld_read_data(NANDDriver *nandp, uint8_t *data, size_t datalen,
+void nand_lld_read_data(NANDDriver *nandp, uint16_t *data, size_t datalen,
                         uint8_t *addr, size_t addrlen, uint32_t *ecc){
 
+  align_check(data, datalen);
+
   nandp->state = NAND_READ;
   nandp->rxdata = data;
   nandp->datalen = datalen;
 
-  nand_lld_write_cmd (nandp, NAND_CMD_READ0);
+  set_16bit_bus(nandp);
+  nand_lld_write_cmd(nandp, NAND_CMD_READ0);
   nand_lld_write_addr(nandp, addr, addrlen);
   osalSysLock();
-  nand_lld_write_cmd (nandp, NAND_CMD_READ0_CONFIRM);
+  nand_lld_write_cmd(nandp, NAND_CMD_READ0_CONFIRM);
+  set_8bit_bus(nandp);
 
   /* Here NAND asserts busy signal and starts transferring from memory
      array to page buffer. After the end of transmission ready_isr functions
@@ -375,7 +439,7 @@ void nand_lld_read_data(NANDDriver *nandp, uint8_t *data, size_t datalen,
  *
  * @param[in] nandp         pointer to the @p NANDDriver object
  * @param[in] data          buffer with data to be written
- * @param[in] datalen       size of data buffer
+ * @param[in] datalen       size of data buffer in bytes
  * @param[in] addr          pointer to address buffer
  * @param[in] addrlen       length of address
  * @param[out] ecc          pointer to store computed ECC. Ignored when NULL.
@@ -384,14 +448,18 @@ void nand_lld_read_data(NANDDriver *nandp, uint8_t *data, size_t datalen,
  *
  * @notapi
  */
-uint8_t nand_lld_write_data(NANDDriver *nandp, const uint8_t *data,
+uint8_t nand_lld_write_data(NANDDriver *nandp, const uint16_t *data,
                 size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc) {
 
+  align_check(data, datalen);
+
   nandp->state = NAND_WRITE;
 
-  nand_lld_write_cmd (nandp, NAND_CMD_WRITE);
+  set_16bit_bus(nandp);
+  nand_lld_write_cmd(nandp, NAND_CMD_WRITE);
   osalSysLock();
   nand_lld_write_addr(nandp, addr, addrlen);
+  set_8bit_bus(nandp);
 
   /* Now start DMA transfer to NAND buffer and put thread in sleep state.
      Tread will be woken up from ready ISR. */
@@ -403,7 +471,8 @@ uint8_t nand_lld_write_data(NANDDriver *nandp, const uint8_t *data,
     nandp->nand->PCR |= FSMC_PCR_ECCEN;
   }
 
-  dmaStartMemCopy(nandp->dma, nandp->dmamode, data, nandp->map_data, datalen);
+  dmaStartMemCopy(nandp->dma, nandp->dmamode, data, nandp->map_data,
+                  datalen/AHB_TRANSACTION_WIDTH);
 
   nand_lld_suspend_thread(nandp);
   osalSysUnlock();
@@ -419,6 +488,26 @@ uint8_t nand_lld_write_data(NANDDriver *nandp, const uint8_t *data,
 }
 
 /**
+ * @brief   Soft reset NAND device.
+ *
+ * @param[in] nandp         pointer to the @p NANDDriver object
+ *
+ * @notapi
+ */
+void nand_lld_reset(NANDDriver *nandp) {
+
+  nandp->state = NAND_RESET;
+
+  set_16bit_bus(nandp);
+  nand_lld_write_cmd(nandp, NAND_CMD_RESET);
+  set_8bit_bus(nandp);
+
+  osalSysLock();
+  nand_lld_suspend_thread(nandp);
+  osalSysUnlock();
+}
+
+/**
  * @brief   Erase block.
  *
  * @param[in] nandp         pointer to the @p NANDDriver object
@@ -433,10 +522,13 @@ uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen) {
 
   nandp->state = NAND_ERASE;
 
-  nand_lld_write_cmd (nandp, NAND_CMD_ERASE);
+  set_16bit_bus(nandp);
+  nand_lld_write_cmd(nandp, NAND_CMD_ERASE);
   nand_lld_write_addr(nandp, addr, addrlen);
   osalSysLock();
-  nand_lld_write_cmd (nandp, NAND_CMD_ERASE_CONFIRM);
+  nand_lld_write_cmd(nandp, NAND_CMD_ERASE_CONFIRM);
+  set_8bit_bus(nandp);
+
   nand_lld_suspend_thread(nandp);
   osalSysUnlock();
 
@@ -444,25 +536,6 @@ uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen) {
 }
 
 /**
- * @brief     Read data from NAND using polling approach.
- *
- * @detatils  Use this function to read data when no waiting expected. For
- *            Example read status word after 0x70 command
- *
- * @param[in] nandp         pointer to the @p NANDDriver object
- * @param[out] data         pointer to output buffer
- * @param[in] len           length of data to be read
- *
- * @notapi
- */
-void nand_lld_polled_read_data(NANDDriver *nandp, uint8_t *data, size_t len) {
-  size_t i = 0;
-
-  for (i=0; i<len; i++)
-    data[i] = nandp->map_data[i];
-}
-
-/**
  * @brief   Send addres to NAND.
  *
  * @param[in] nandp         pointer to the @p NANDDriver object
@@ -501,12 +574,14 @@ void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd) {
  */
 uint8_t nand_lld_read_status(NANDDriver *nandp) {
 
-  uint8_t status[1] = {0x01}; /* presume worse */
+  uint16_t status;
 
+  set_16bit_bus(nandp);
   nand_lld_write_cmd(nandp, NAND_CMD_STATUS);
-  nand_lld_polled_read_data(nandp, status, 1);
+  set_8bit_bus(nandp);
+  status = nandp->map_data[0];
 
-  return status[0];
+  return status & 0xFF;
 }
 
 #endif /* HAL_USE_NAND */
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h
index 8dca42f..5266138 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h
@@ -15,15 +15,15 @@
 */
 
 /**
- * @file    nand_lld.h
+ * @file    hal_nand_lld.h
  * @brief   NAND Driver subsystem low level driver header.
  *
  * @addtogroup NAND
  * @{
  */
 
-#ifndef _NAND_LLD_H_
-#define _NAND_LLD_H_
+#ifndef HAL_NAND_LLD_H_
+#define HAL_NAND_LLD_H_
 
 #include "hal_fsmc.h"
 #include "bitmap.h"
@@ -120,10 +120,6 @@
 #error "FSMC not present in the selected device"
 #endif
 
-#if STM32_NAND_USE_EXT_INT && !HAL_USE_EXT
-#error "External interrupt controller must be enabled to use this feature"
-#endif
-
 #if !defined(STM32_DMA_REQUIRED)
 #define STM32_DMA_REQUIRED
 #endif
@@ -133,37 +129,21 @@
 /*===========================================================================*/
 
 /**
- * @brief   NAND driver condition flags type.
- */
-typedef uint32_t nandflags_t;
-
-/**
  * @brief   Type of a structure representing an NAND driver.
  */
 typedef struct NANDDriver NANDDriver;
 
 /**
- * @brief   Type of interrupt handler function
+ * @brief   Type of interrupt handler function.
  */
 typedef void (*nandisrhandler_t)(NANDDriver *nandp);
 
-#if STM32_NAND_USE_EXT_INT
-/**
- * @brief   Type of function switching external interrupts on and off.
- */
-typedef void (*nandisrswitch_t)(void);
-#endif /* STM32_NAND_USE_EXT_INT */
-
 /**
  * @brief   Driver configuration structure.
  * @note    It could be empty on some architectures.
  */
 typedef struct {
   /**
-   * @brief   Pointer to lower level driver.
-   */
-  //const FSMCDriver                *fsmcp;
-  /**
    * @brief   Number of erase blocks in NAND device.
    */
   uint32_t                  blocks;
@@ -197,16 +177,6 @@ typedef struct {
    *          from STMicroelectronics.
    */
   uint32_t                  pmem;
-#if STM32_NAND_USE_EXT_INT
-  /**
-   * @brief   Function enabling interrupts from EXTI
-   */
-  nandisrswitch_t           ext_nand_isr_enable;
-  /**
-   * @brief   Function disabling interrupts from EXTI
-   */
-  nandisrswitch_t           ext_nand_isr_disable;
-#endif /* STM32_NAND_USE_EXT_INT */
 } NANDConfig;
 
 /**
@@ -236,15 +206,15 @@ struct NANDDriver {
 #endif /* NAND_USE_MUTUAL_EXCLUSION */
   /* End of the mandatory fields.*/
   /**
-   * @brief   Function enabling interrupts from FSMC
+   * @brief   Function enabling interrupts from FSMC.
    */
   nandisrhandler_t          isr_handler;
   /**
-   * @brief   Pointer to current transaction buffer
+   * @brief   Pointer to current transaction buffer.
    */
-  uint8_t                   *rxdata;
+  void                      *rxdata;
   /**
-   * @brief   Current transaction length
+   * @brief   Current transaction length in bytes.
    */
   size_t                    datalen;
   /**
@@ -266,15 +236,15 @@ struct NANDDriver {
   /**
    * @brief     Memory mapping for data.
    */
-  uint8_t                   *map_data;
+  uint16_t                  *map_data;
   /**
    * @brief     Memory mapping for commands.
    */
-  uint8_t                   *map_cmd;
+  uint16_t                  *map_cmd;
   /**
    * @brief     Memory mapping for addresses.
    */
-  uint8_t                   *map_addr;
+  uint16_t                  *map_addr;
   /**
    * @brief   Pointer to bad block map.
    * @details One bit per block. All memory allocation is user's responsibility.
@@ -304,21 +274,21 @@ extern "C" {
   void nand_lld_init(void);
   void nand_lld_start(NANDDriver *nandp);
   void nand_lld_stop(NANDDriver *nandp);
-  void nand_lld_read_data(NANDDriver *nandp, uint8_t *data,
+  uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen);
+  void nand_lld_read_data(NANDDriver *nandp, uint16_t *data,
                 size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc);
-  void nand_lld_polled_read_data(NANDDriver *nandp, uint8_t *data, size_t len);
   void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len);
   void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd);
-  uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen);
-  uint8_t nand_lld_write_data(NANDDriver *nandp, const uint8_t *data,
+  uint8_t nand_lld_write_data(NANDDriver *nandp, const uint16_t *data,
                 size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc);
   uint8_t nand_lld_read_status(NANDDriver *nandp);
+  void nand_lld_reset(NANDDriver *nandp);
 #ifdef __cplusplus
 }
 #endif
 
 #endif /* HAL_USE_NAND */
 
-#endif /* _NAND_LLD_H_ */
+#endif /* HAL_NAND_LLD_H_ */
 
 /** @} */
diff --git a/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c b/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c
index e5f9a09..bffa472 100644
--- a/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c
+++ b/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c
@@ -15,11 +15,10 @@
 */
 
 /**
- * @file    stm32_ltdc.c
+ * @file    hal_stm32_ltdc.c
  * @brief   LCD-TFT Controller Driver.
  */
 
-#include "ch.h"
 #include "hal.h"
 
 #include "hal_stm32_ltdc.h"
diff --git a/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.h b/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.h
index 16b38ca..5db89e2 100644
--- a/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.h
+++ b/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.h
@@ -15,15 +15,15 @@
 */
 
 /**
- * @file    stm32_ltdc.h
+ * @file    hal_stm32_ltdc.h
  * @brief   LCD-TFT Controller Driver.
  *
  * @addtogroup ltdc
  * @{
  */
 
-#ifndef _STM32_LTDC_H_
-#define _STM32_LTDC_H_
+#ifndef HAL_STM32_LTDC_H_
+#define HAL_STM32_LTDC_H_
 
 /**
  * @brief   Using the LTDC driver.
@@ -731,6 +731,6 @@ extern "C" {
 
 #endif  /* STM32_LTDC_USE_LTDC */
 
-#endif  /* _STM32_LTDC_H_ */
+#endif  /* HAL_STM32_LTDC_H_ */
 
 /** @} */
diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c
index c04278e..ed4c5b8 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c
+++ b/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c
@@ -1057,75 +1057,75 @@ void eicu_lld_stop(EICUDriver *eicup) {
     if (&EICUD1 == eicup) {
       nvicDisableVector(STM32_TIM1_UP_NUMBER);
       nvicDisableVector(STM32_TIM1_CC_NUMBER);
-      rccDisableTIM1(FALSE);
+      rccDisableTIM1();
     }
 #endif
 #if STM32_EICU_USE_TIM2
     if (&EICUD2 == eicup) {
       nvicDisableVector(STM32_TIM2_NUMBER);
-      rccDisableTIM2(FALSE);
+      rccDisableTIM2();
     }
 #endif
 #if STM32_EICU_USE_TIM3
     if (&EICUD3 == eicup) {
       nvicDisableVector(STM32_TIM3_NUMBER);
-      rccDisableTIM3(FALSE);
+      rccDisableTIM3();
     }
 #endif
 #if STM32_EICU_USE_TIM4
     if (&EICUD4 == eicup) {
       nvicDisableVector(STM32_TIM4_NUMBER);
-      rccDisableTIM4(FALSE);
+      rccDisableTIM4();
     }
 #endif
 #if STM32_EICU_USE_TIM5
     if (&EICUD5 == eicup) {
       nvicDisableVector(STM32_TIM5_NUMBER);
-      rccDisableTIM5(FALSE);
+      rccDisableTIM5();
     }
 #endif
 #if STM32_EICU_USE_TIM8
     if (&EICUD8 == eicup) {
       nvicDisableVector(STM32_TIM8_UP_NUMBER);
       nvicDisableVector(STM32_TIM8_CC_NUMBER);
-      rccDisableTIM8(FALSE);
+      rccDisableTIM8();
     }
 #endif
 #if STM32_EICU_USE_TIM9
     if (&EICUD9 == eicup) {
       nvicDisableVector(STM32_TIM9_NUMBER);
-      rccDisableTIM9(FALSE);
+      rccDisableTIM9();
     }
 #endif
 #if STM32_EICU_USE_TIM12
     if (&EICUD12 == eicup) {
       nvicDisableVector(STM32_TIM12_NUMBER);
-      rccDisableTIM12(FALSE);
+      rccDisableTIM12();
     }
 #endif
   }
 #if STM32_EICU_USE_TIM10
     if (&EICUD10 == eicup) {
       nvicDisableVector(STM32_TIM10_NUMBER);
-      rccDisableTIM10(FALSE);
+      rccDisableTIM10();
     }
 #endif
 #if STM32_EICU_USE_TIM11
     if (&EICUD11 == eicup) {
       nvicDisableVector(STM32_TIM11_NUMBER);
-      rccDisableTIM11(FALSE);
+      rccDisableTIM11();
     }
 #endif
 #if STM32_EICU_USE_TIM13
     if (&EICUD13 == eicup) {
       nvicDisableVector(STM32_TIM13_NUMBER);
-      rccDisableTIM13(FALSE);
+      rccDisableTIM13();
     }
 #endif
 #if STM32_EICU_USE_TIM14
     if (&EICUD14 == eicup) {
       nvicDisableVector(STM32_TIM14_NUMBER);
-      rccDisableTIM14(FALSE);
+      rccDisableTIM14();
     }
 #endif
 }
diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.h b/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.h
index 927eb6f..e72098e 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.h
+++ b/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.h
@@ -22,8 +22,8 @@
    32-bit timers and timers with single capture/compare channels.
 */
 
-#ifndef __EICU_LLD_H
-#define __EICU_LLD_H
+#ifndef HAL_EICU_LLD_H
+#define HAL_EICU_LLD_H
 
 #include "stm32_tim.h"
 
@@ -551,4 +551,4 @@ extern "C" {
 
 #endif /* HAL_USE_EICU */
 
-#endif /* __EICU_LLD_H */
+#endif /* HAL_EICU_LLD_H */
diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
index ea051f7..e07b946 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
+++ b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
@@ -150,6 +150,8 @@ void qei_lld_init(void) {
  * @notapi

  */

 void qei_lld_start(QEIDriver *qeip) {

+  osalDbgAssert((qeip->config->min == 0) || (qeip->config->max == 0),

+		"only min/max set to 0 is supported");

 

   if (qeip->state == QEI_STOP) {

     /* Clock activation and timer reset.*/

@@ -192,24 +194,24 @@ void qei_lld_start(QEIDriver *qeip) {
 #endif

   }

    /* Timer configuration.*/

-  qeip->tim->CR1  = 0;                      /* Initially stopped.           */

+  qeip->tim->CR1  = 0;                      /* Initially stopped. */

   qeip->tim->CR2  = 0;

   qeip->tim->PSC  = 0;

   qeip->tim->DIER = 0;

-  qeip->tim->ARR   = 0xFFFF;

+  qeip->tim->ARR  = 0xFFFF;

 

   /* Set Capture Compare 1 and Capture Compare 2 as input. */

    qeip->tim->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;

 

   if (qeip->config->mode == QEI_MODE_QUADRATURE) {

     if (qeip->config->resolution == QEI_BOTH_EDGES)

-      qeip->tim->SMCR  = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0;

+      qeip->tim->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0;

     else

-      qeip->tim->SMCR  = TIM_SMCR_SMS_0;

+      qeip->tim->SMCR = TIM_SMCR_SMS_0;

   } else {

     /* Direction/Clock mode.

      * Direction input on TI1, Clock input on TI2. */

-    qeip->tim->SMCR  = TIM_SMCR_SMS_0;

+    qeip->tim->SMCR = TIM_SMCR_SMS_0;

   }

 

   if (qeip->config->dirinv == QEI_DIRINV_TRUE)

@@ -228,38 +230,38 @@ void qei_lld_start(QEIDriver *qeip) {
 void qei_lld_stop(QEIDriver *qeip) {

 

   if (qeip->state == QEI_READY) {

-    qeip->tim->CR1  = 0;                    /* Timer disabled.              */

+    qeip->tim->CR1 = 0;                    /* Timer disabled. */

 

     /* Clock deactivation.*/

 #if STM32_QEI_USE_TIM1

     if (&QEID1 == qeip) {

-      rccDisableTIM1(FALSE);

+      rccDisableTIM1();

     }

 #endif

 #if STM32_QEI_USE_TIM2

     if (&QEID2 == qeip) {

-      rccDisableTIM2(FALSE);

+      rccDisableTIM2();

     }

 #endif

 #if STM32_QEI_USE_TIM3

     if (&QEID3 == qeip) {

-      rccDisableTIM3(FALSE);

+      rccDisableTIM3();

     }

 #endif

 #if STM32_QEI_USE_TIM4

     if (&QEID4 == qeip) {

-      rccDisableTIM4(FALSE);

+      rccDisableTIM4();

     }

 #endif

 #if STM32_QEI_USE_TIM5

     if (&QEID5 == qeip) {

-      rccDisableTIM5(FALSE);

+      rccDisableTIM5();

     }

 #endif

   }

 #if STM32_QEI_USE_TIM8

     if (&QEID8 == qeip) {

-      rccDisableTIM8(FALSE);

+      rccDisableTIM8();

     }

 #endif

 }

@@ -273,7 +275,7 @@ void qei_lld_stop(QEIDriver *qeip) {
  */

 void qei_lld_enable(QEIDriver *qeip) {

 

-  qeip->tim->CR1 = TIM_CR1_CEN;            /* Timer enabled.               */

+  qeip->tim->CR1 = TIM_CR1_CEN;            /* Timer enabled. */

 }

 

 /**

@@ -285,7 +287,7 @@ void qei_lld_enable(QEIDriver *qeip) {
  */

 void qei_lld_disable(QEIDriver *qeip) {

 

-  qeip->tim->CR1 = 0;                    /* Timer disabled.              */

+  qeip->tim->CR1 = 0;                    /* Timer disabled. */

 }

 

 #endif /* HAL_USE_QEI */

diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h
index d0cb683..73468f5 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h
+++ b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h
@@ -33,6 +33,16 @@
 /* Driver constants.                                                         */

 /*===========================================================================*/

 

+/**

+ * @brief Mininum usable value for defining counter underflow

+ */

+#define QEI_COUNT_MIN (0)

+

+/**

+ * @brief Maximum usable value for defining counter overflow

+ */

+#define QEI_COUNT_MAX (65535)

+

 /*===========================================================================*/

 /* Driver pre-compile time settings.                                         */

 /*===========================================================================*/

@@ -172,6 +182,56 @@
 #error "QEI driver activated but no TIM peripheral assigned"

 #endif

 

+/* Checks on allocation of TIMx units.*/

+#if STM32_QEI_USE_TIM1

+#if defined(STM32_TIM1_IS_USED)

+#error "QEID1 requires TIM1 but the timer is already used"

+#else

+#define STM32_TIM1_IS_USED

+#endif

+#endif

+

+#if STM32_QEI_USE_TIM2

+#if defined(STM32_TIM2_IS_USED)

+#error "QEID2 requires TIM2 but the timer is already used"

+#else

+#define STM32_TIM2_IS_USED

+#endif

+#endif

+

+#if STM32_QEI_USE_TIM3

+#if defined(STM32_TIM3_IS_USED)

+#error "QEID3 requires TIM3 but the timer is already used"

+#else

+#define STM32_TIM3_IS_USED

+#endif

+#endif

+

+#if STM32_QEI_USE_TIM4

+#if defined(STM32_TIM4_IS_USED)

+#error "QEID4 requires TIM4 but the timer is already used"

+#else

+#define STM32_TIM4_IS_USED

+#endif

+#endif

+

+#if STM32_QEI_USE_TIM5

+#if defined(STM32_TIM5_IS_USED)

+#error "QEID5 requires TIM5 but the timer is already used"

+#else

+#define STM32_TIM5_IS_USED

+#endif

+#endif

+

+#if STM32_QEI_USE_TIM8

+#if defined(STM32_TIM8_IS_USED)

+#error "QEID8 requires TIM8 but the timer is already used"

+#else

+#define STM32_TIM8_IS_USED

+#endif

+#endif

+

+/* IRQ priority checks.*/

 #if STM32_QEI_USE_TIM1 &&                                                   \

     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QEI_TIM1_IRQ_PRIORITY)

 #error "Invalid IRQ priority assigned to TIM1"

@@ -202,6 +262,14 @@
 #error "Invalid IRQ priority assigned to TIM8"

 #endif

 

+#if QEI_USE_OVERFLOW_DISCARD

+#error "QEI_USE_OVERFLOW_DISCARD not supported by this driver"

+#endif

+

+#if QEI_USE_OVERFLOW_MINMAX

+#error "QEI_USE_OVERFLOW_MINMAX not supported by this driver"

+#endif

+

 /*===========================================================================*/

 /* Driver data structures and types.                                         */

 /*===========================================================================*/

@@ -233,7 +301,7 @@ typedef enum {
 /**

  * @brief   QEI counter type.

  */

-typedef uint16_t qeicnt_t;

+typedef int16_t qeicnt_t;

 

 /**

  * @brief   QEI delta type.

@@ -257,6 +325,45 @@ typedef struct {
    * @brief   Direction inversion.

    */

   qeidirinv_t               dirinv;

+  /**

+   * @brief   Handling of counter overflow/underflow

+   *

+   * @details When overflow occurs, the counter value is updated

+   *          according to:

+   *            - QEI_OVERFLOW_DISCARD:

+   *                discard the update value, counter doesn't change

+   */

+  qeioverflow_t             overflow;

+  /**

+   * @brief   Min count value.

+   *

+   * @note    If min == max, then QEI_COUNT_MIN is used.

+   *

+   * @note    Only min set to 0 / QEI_COUNT_MIN is supported.

+   */

+  qeicnt_t                  min;

+  /**

+   * @brief   Max count value.

+   *

+   * @note    If min == max, then QEI_COUNT_MAX is used.

+   *

+   * @note    Only max set to 0 / QEI_COUNT_MAX is supported.

+   */

+  qeicnt_t                  max;

+  /**

+    * @brief  Notify of value change

+    *

+    * @note   Called from ISR context.

+    */

+  qeicallback_t             notify_cb;

+  /**

+   * @brief   Notify of overflow

+   *

+   * @note    Overflow notification is performed after

+   *          value changed notification.

+   * @note    Called from ISR context.

+   */

+  void (*overflow_cb)(QEIDriver *qeip, qeidelta_t delta);

   /* End of the mandatory fields.*/

 } QEIConfig;

 

@@ -300,6 +407,16 @@ struct QEIDriver {
  */

 #define qei_lld_get_count(qeip) ((qeip)->tim->CNT)

 

+/**

+ * @brief   Set the counter value.

+ *

+ * @param[in] qeip      pointer to the @p QEIDriver object

+ * @param[in] qeip      counter value

+ *

+ * @notapi

+ */

+#define qei_lld_set_count(qeip, value)

+

 /*===========================================================================*/

 /* External declarations.                                                    */

 /*===========================================================================*/

diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c
index 8ab6176..d95c6a3 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c
+++ b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c
@@ -24,14 +24,13 @@
 
 
 /**
- * @file    STM32/timcap_lld.c
+ * @file    STM32/hal_timcap_lld.c
  * @brief   STM32 TIMCAP subsystem low level driver header.
  *
  * @addtogroup TIMCAP
  * @{
  */
 
-#include "ch.h"
 #include "hal.h"
 
 #if HAL_USE_TIMCAP || defined(__DOXYGEN__)
@@ -714,44 +713,44 @@ void timcap_lld_stop(TIMCAPDriver *timcapp) {
     if (&TIMCAPD1 == timcapp) {
       nvicDisableVector(STM32_TIM1_UP_NUMBER);
       nvicDisableVector(STM32_TIM1_CC_NUMBER);
-      rccDisableTIM1(FALSE);
+      rccDisableTIM1();
     }
 #endif
 #if STM32_TIMCAP_USE_TIM2
     if (&TIMCAPD2 == timcapp) {
       nvicDisableVector(STM32_TIM2_NUMBER);
-      rccDisableTIM2(FALSE);
+      rccDisableTIM2();
     }
 #endif
 #if STM32_TIMCAP_USE_TIM3
     if (&TIMCAPD3 == timcapp) {
       nvicDisableVector(STM32_TIM3_NUMBER);
-      rccDisableTIM3(FALSE);
+      rccDisableTIM3();
     }
 #endif
 #if STM32_TIMCAP_USE_TIM4
     if (&TIMCAPD4 == timcapp) {
       nvicDisableVector(STM32_TIM4_NUMBER);
-      rccDisableTIM4(FALSE);
+      rccDisableTIM4();
     }
 #endif
 #if STM32_TIMCAP_USE_TIM5
     if (&TIMCAPD5 == timcapp) {
       nvicDisableVector(STM32_TIM5_NUMBER);
-      rccDisableTIM5(FALSE);
+      rccDisableTIM5();
     }
 #endif
 #if STM32_TIMCAP_USE_TIM8
     if (&TIMCAPD8 == timcapp) {
       nvicDisableVector(STM32_TIM8_UP_NUMBER);
       nvicDisableVector(STM32_TIM8_CC_NUMBER);
-      rccDisableTIM8(FALSE);
+      rccDisableTIM8();
     }
 #endif
 #if STM32_TIMCAP_USE_TIM9
     if (&TIMCAPD9 == timcapp) {
       nvicDisableVector(STM32_TIM9_NUMBER);
-      rccDisableTIM9(FALSE);
+      rccDisableTIM9();
     }
 #endif
   }
diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.h b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.h
index d39c438..621313a 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.h
+++ b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.h
@@ -22,10 +22,9 @@
  * @{
  */
 
-#ifndef _TIMCAP_LLD_H_
-#define _TIMCAP_LLD_H_
+#ifndef HAL_TIMCAP_LLD_H_
+#define HAL_TIMCAP_LLD_H_
 
-#include "ch.h"
 #include "hal.h"
 #include "stm32_tim.h"
 
diff --git a/os/hal/ports/STM32/LLD/USBHv1/hal_stm32_otg.h b/os/hal/ports/STM32/LLD/USBHv1/hal_stm32_otg.h
deleted file mode 100644
index ca2dc49..0000000
--- a/os/hal/ports/STM32/LLD/USBHv1/hal_stm32_otg.h
+++ /dev/null
@@ -1,929 +0,0 @@
-/*
-    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    stm32_otg.h
- * @brief   STM32 OTG registers layout header.
- *
- * @addtogroup USB
- * @{
- */
-
-
-#ifndef _STM32_OTG_H_
-#define _STM32_OTG_H_
-
-/**
- * @brief   Number of the implemented endpoints in OTG_FS.
- * @details This value does not include the endpoint 0 that is always present.
- */
-#define STM32_OTG1_ENDOPOINTS_NUMBER    3
-
-/**
- * @brief   Number of the implemented endpoints in OTG_HS.
- * @details This value does not include the endpoint 0 that is always present.
- */
-#define STM32_OTG2_ENDOPOINTS_NUMBER    5
-
-/**
- * @brief   OTG_FS FIFO memory size in words.
- */
-#define STM32_OTG1_FIFO_MEM_SIZE        320
-
-/**
- * @brief   OTG_HS FIFO memory size in words.
- */
-#define STM32_OTG2_FIFO_MEM_SIZE        1024
-
-/**
- * @brief   Host channel registers group.
- */
-typedef struct {
-  volatile uint32_t HCCHAR;     /**< @brief Host channel characteristics
-                                            register.                       */
-  volatile uint32_t resvd8;
-  volatile uint32_t HCINT;      /**< @brief Host channel interrupt register.*/
-  volatile uint32_t HCINTMSK;   /**< @brief Host channel interrupt mask
-                                            register.                       */
-  volatile uint32_t HCTSIZ;     /**< @brief Host channel transfer size
-                                            register.                       */
-  volatile uint32_t resvd14;
-  volatile uint32_t resvd18;
-  volatile uint32_t resvd1c;
-} stm32_otg_host_chn_t;
-
-/**
- * @brief   Device input endpoint registers group.
- */
-typedef struct {
-  volatile uint32_t DIEPCTL;    /**< @brief Device control IN endpoint
-                                            control register.               */
-  volatile uint32_t resvd4;
-  volatile uint32_t DIEPINT;    /**< @brief Device IN endpoint interrupt
-                                            register.                       */
-  volatile uint32_t resvdC;
-  volatile uint32_t DIEPTSIZ;   /**< @brief Device IN endpoint transfer size
-                                            register.                       */
-  volatile uint32_t resvd14;
-  volatile uint32_t DTXFSTS;    /**< @brief Device IN endpoint transmit FIFO
-                                            status register.                */
-  volatile uint32_t resvd1C;
-} stm32_otg_in_ep_t;
-
-/**
- * @brief   Device output endpoint registers group.
- */
-typedef struct {
-  volatile uint32_t DOEPCTL;    /**< @brief Device control OUT endpoint
-                                            control register.               */
-  volatile uint32_t resvd4;
-  volatile uint32_t DOEPINT;    /**< @brief Device OUT endpoint interrupt
-                                            register.                       */
-  volatile uint32_t resvdC;
-  volatile uint32_t DOEPTSIZ;   /**< @brief Device OUT endpoint transfer
-                                            size register.                  */
-  volatile uint32_t resvd14;
-  volatile uint32_t resvd18;
-  volatile uint32_t resvd1C;
-} stm32_otg_out_ep_t;
-
-/**
- * @brief   USB registers memory map.
- */
-typedef struct {
-  volatile uint32_t GOTGCTL;    /**< @brief OTG control and status register.*/
-  volatile uint32_t GOTGINT;    /**< @brief OTG interrupt register.         */
-  volatile uint32_t GAHBCFG;    /**< @brief AHB configuration register.     */
-  volatile uint32_t GUSBCFG;    /**< @brief USB configuration register.     */
-  volatile uint32_t GRSTCTL;    /**< @brief Reset register size.            */
-  volatile uint32_t GINTSTS;    /**< @brief Interrupt register.             */
-  volatile uint32_t GINTMSK;    /**< @brief Interrupt mask register.        */
-  volatile uint32_t GRXSTSR;    /**< @brief Receive status debug read
-                                            register.                       */
-  volatile uint32_t GRXSTSP;    /**< @brief Receive status read/pop
-                                            register.                       */
-  volatile uint32_t GRXFSIZ;    /**< @brief Receive FIFO size register.     */
-  volatile uint32_t DIEPTXF0;   /**< @brief Endpoint 0 transmit FIFO size
-                                            register.                       */
-  volatile uint32_t HNPTXSTS;   /**< @brief Non-periodic transmit FIFO/queue
-                                            status register.                */
-  volatile uint32_t resvd30;
-  volatile uint32_t resvd34;
-  volatile uint32_t GCCFG;      /**< @brief General core configuration.     */
-  volatile uint32_t CID;        /**< @brief Core ID register.               */
-  volatile uint32_t resvd58[48];
-  volatile uint32_t HPTXFSIZ;   /**< @brief Host periodic transmit FIFO size
-                                            register.                       */
-  volatile uint32_t DIEPTXF[15];/**< @brief Device IN endpoint transmit FIFO
-                                            size registers.                 */
-  volatile uint32_t resvd140[176];
-  volatile uint32_t HCFG;       /**< @brief Host configuration register.    */
-  volatile uint32_t HFIR;       /**< @brief Host frame interval register.   */
-  volatile uint32_t HFNUM;      /**< @brief Host frame number/frame time
-                                            Remaining register.             */
-  volatile uint32_t resvd40C;
-  volatile uint32_t HPTXSTS;    /**< @brief Host periodic transmit FIFO/queue
-                                            status register.                */
-  volatile uint32_t HAINT;      /**< @brief Host all channels interrupt
-                                            register.                       */
-  volatile uint32_t HAINTMSK;   /**< @brief Host all channels interrupt mask
-                                            register.                       */
-  volatile uint32_t resvd41C[9];
-  volatile uint32_t HPRT;       /**< @brief Host port control and status
-                                            register.                       */
-  volatile uint32_t resvd444[47];
-  stm32_otg_host_chn_t hc[16];  /**< @brief Host channels array.            */
-  volatile uint32_t resvd700[64];
-  volatile uint32_t DCFG;       /**< @brief Device configuration register.  */
-  volatile uint32_t DCTL;       /**< @brief Device control register.        */
-  volatile uint32_t DSTS;       /**< @brief Device status register.         */
-  volatile uint32_t resvd80C;
-  volatile uint32_t DIEPMSK;    /**< @brief Device IN endpoint common
-                                            interrupt mask register.        */
-  volatile uint32_t DOEPMSK;    /**< @brief Device OUT endpoint common
-                                            interrupt mask register.        */
-  volatile uint32_t DAINT;      /**< @brief Device all endpoints interrupt
-                                            register.                       */
-  volatile uint32_t DAINTMSK;   /**< @brief Device all endpoints interrupt
-                                            mask register.                  */
-  volatile uint32_t resvd820;
-  volatile uint32_t resvd824;
-  volatile uint32_t DVBUSDIS;   /**< @brief Device VBUS discharge time
-                                            register.                       */
-  volatile uint32_t DVBUSPULSE; /**< @brief Device VBUS pulsing time
-                                            register.                       */
-  volatile uint32_t resvd830;
-  volatile uint32_t DIEPEMPMSK; /**< @brief Device IN endpoint FIFO empty
-                                            interrupt mask register.        */
-  volatile uint32_t resvd838;
-  volatile uint32_t resvd83C;
-  volatile uint32_t resvd840[16];
-  volatile uint32_t resvd880[16];
-  volatile uint32_t resvd8C0[16];
-  stm32_otg_in_ep_t ie[16];     /**< @brief Input endpoints.                */
-  stm32_otg_out_ep_t oe[16];    /**< @brief Output endpoints.               */
-  volatile uint32_t resvdD00[64];
-  volatile uint32_t PCGCCTL;    /**< @brief Power and clock gating control
-                                            register.                       */
-  volatile uint32_t resvdE04[127];
-  volatile uint32_t FIFO[16][1024];
-} stm32_otg_t;
-
-/**
- * @name GOTGCTL register bit definitions
- * @{
- */
-#define GOTGCTL_BSVLD           (1U<<19)    /**< B-Session Valid.           */
-#define GOTGCTL_ASVLD           (1U<<18)    /**< A-Session Valid.           */
-#define GOTGCTL_DBCT            (1U<<17)    /**< Long/Short debounce time.  */
-#define GOTGCTL_CIDSTS          (1U<<16)    /**< Connector ID status.       */
-#define GOTGCTL_EHEN            (1U<<12)
-#define GOTGCTL_DHNPEN          (1U<<11)    /**< Device HNP enabled.        */
-#define GOTGCTL_HSHNPEN         (1U<<10)    /**< Host Set HNP enable.       */
-#define GOTGCTL_HNPRQ           (1U<<9)     /**< HNP request.               */
-#define GOTGCTL_HNGSCS          (1U<<8)     /**< Host negotiation success.  */
-#define GOTGCTL_BVALOVAL        (1U<<7)
-#define GOTGCTL_BVALOEN         (1U<<6)
-#define GOTGCTL_AVALOVAL        (1U<<5)
-#define GOTGCTL_AVALOEN         (1U<<4)
-#define GOTGCTL_VBVALOVAL       (1U<<3)
-#define GOTGCTL_VBVALOEN        (1U<<2)
-#define GOTGCTL_SRQ             (1U<<1)     /**< Session request.           */
-#define GOTGCTL_SRQSCS          (1U<<0)     /**< Session request success.   */
-/** @} */
-
-/**
- * @name GOTGINT register bit definitions
- * @{
- */
-#define GOTGINT_DBCDNE          (1U<<19)    /**< Debounce done.             */
-#define GOTGINT_ADTOCHG         (1U<<18)    /**< A-Device timeout change.   */
-#define GOTGINT_HNGDET          (1U<<17)    /**< Host negotiation detected. */
-#define GOTGINT_HNSSCHG         (1U<<9)     /**< Host negotiation success
-                                                 status change.             */
-#define GOTGINT_SRSSCHG         (1U<<8)     /**< Session request success
-                                                 status change.             */
-#define GOTGINT_SEDET           (1U<<2)     /**< Session end detected.      */
-/** @} */
-
-/**
- * @name GAHBCFG register bit definitions
- * @{
- */
-#define GAHBCFG_PTXFELVL        (1U<<8)     /**< Periodic TxFIFO empty
-                                                 level.                     */
-#define GAHBCFG_TXFELVL         (1U<<7)     /**< Non-periodic TxFIFO empty
-                                                 level.                     */
-#define GAHBCFG_DMAEN           (1U<<5)     /**< DMA enable (HS only).      */
-#define GAHBCFG_HBSTLEN_MASK    (15U<<1)    /**< Burst length/type mask (HS
-                                                 only).                     */
-#define GAHBCFG_HBSTLEN(n)      ((n)<<1)    /**< Burst length/type (HS
-                                                 only).                     */
-#define GAHBCFG_GINTMSK         (1U<<0)     /**< Global interrupt mask.     */
-/** @} */
-
-/**
- * @name GUSBCFG register bit definitions
- * @{
- */
-#define GUSBCFG_CTXPKT          (1U<<31)    /**< Corrupt Tx packet.         */
-#define GUSBCFG_FDMOD           (1U<<30)    /**< Force Device Mode.         */
-#define GUSBCFG_FHMOD           (1U<<29)    /**< Force Host Mode.           */
-#define GUSBCFG_TRDT_MASK       (15U<<10)   /**< USB Turnaround time field
-                                                 mask.                      */
-#define GUSBCFG_TRDT(n)         ((n)<<10)   /**< USB Turnaround time field
-                                                 value.                     */
-#define GUSBCFG_HNPCAP          (1U<<9)     /**< HNP-Capable.               */
-#define GUSBCFG_SRPCAP          (1U<<8)     /**< SRP-Capable.               */
-#define GUSBCFG_PHYSEL          (1U<<6)     /**< USB 2.0 High-Speed PHY or
-                                                 USB 1.1 Full-Speed serial
-                                                 transceiver Select.        */
-#define GUSBCFG_TOCAL_MASK      (7U<<0)     /**< HS/FS timeout calibration
-                                                 field mask.                */
-#define GUSBCFG_TOCAL(n)        ((n)<<0)    /**< HS/FS timeout calibration
-                                                 field value.               */
-/** @} */
-
-/**
- * @name GRSTCTL register bit definitions
- * @{
- */
-#define GRSTCTL_AHBIDL          (1U<<31)    /**< AHB Master Idle.           */
-#define GRSTCTL_TXFNUM_MASK     (31U<<6)    /**< TxFIFO number field mask.  */
-#define GRSTCTL_TXFNUM(n)       ((n)<<6)    /**< TxFIFO number field value. */
-#define GRSTCTL_TXFFLSH         (1U<<5)     /**< TxFIFO flush.              */
-#define GRSTCTL_RXFFLSH         (1U<<4)     /**< RxFIFO flush.              */
-#define GRSTCTL_FCRST           (1U<<2)     /**< Host frame counter reset.  */
-#define GRSTCTL_HSRST           (1U<<1)     /**< HClk soft reset.           */
-#define GRSTCTL_CSRST           (1U<<0)     /**< Core soft reset.           */
-/** @} */
-
-/**
- * @name GINTSTS register bit definitions
- * @{
- */
-#define GINTSTS_WKUPINT         (1U<<31)    /**< Resume/Remote wakeup
-                                                 detected interrupt.        */
-#define GINTSTS_SRQINT          (1U<<30)    /**< Session request/New session
-                                                 detected interrupt.        */
-#define GINTSTS_DISCINT         (1U<<29)    /**< Disconnect detected
-                                                 interrupt.                 */
-#define GINTSTS_CIDSCHG         (1U<<28)    /**< Connector ID status change.*/
-#define GINTSTS_PTXFE           (1U<<26)    /**< Periodic TxFIFO empty.     */
-#define GINTSTS_HCINT           (1U<<25)    /**< Host channels interrupt.   */
-#define GINTSTS_HPRTINT         (1U<<24)    /**< Host port interrupt.       */
-#define GINTSTS_IPXFR           (1U<<21)    /**< Incomplete periodic
-                                                 transfer.                  */
-#define GINTSTS_IISOOXFR        (1U<<21)    /**< Incomplete isochronous OUT
-                                                 transfer.                  */
-#define GINTSTS_IISOIXFR        (1U<<20)    /**< Incomplete isochronous IN
-                                                 transfer.                  */
-#define GINTSTS_OEPINT          (1U<<19)    /**< OUT endpoints interrupt.   */
-#define GINTSTS_IEPINT          (1U<<18)    /**< IN endpoints interrupt.    */
-#define GINTSTS_EOPF            (1U<<15)    /**< End of periodic frame
-                                                 interrupt.                 */
-#define GINTSTS_ISOODRP         (1U<<14)    /**< Isochronous OUT packet
-                                                 dropped interrupt.         */
-#define GINTSTS_ENUMDNE         (1U<<13)    /**< Enumeration done.          */
-#define GINTSTS_USBRST          (1U<<12)    /**< USB reset.                 */
-#define GINTSTS_USBSUSP         (1U<<11)    /**< USB suspend.               */
-#define GINTSTS_ESUSP           (1U<<10)    /**< Early suspend.             */
-#define GINTSTS_GONAKEFF        (1U<<7)     /**< Global OUT NAK effective.  */
-#define GINTSTS_GINAKEFF        (1U<<6)     /**< Global IN non-periodic NAK
-                                                 effective.                 */
-#define GINTSTS_NPTXFE          (1U<<5)     /**< Non-periodic TxFIFO empty. */
-#define GINTSTS_RXFLVL          (1U<<4)     /**< RxFIFO non-empty.          */
-#define GINTSTS_SOF             (1U<<3)     /**< Start of frame.            */
-#define GINTSTS_OTGINT          (1U<<2)     /**< OTG interrupt.             */
-#define GINTSTS_MMIS            (1U<<1)     /**< Mode Mismatch interrupt.   */
-#define GINTSTS_CMOD            (1U<<0)     /**< Current mode of operation. */
-/** @} */
-
-/**
- * @name GINTMSK register bit definitions
- * @{
- */
-#define GINTMSK_WKUM            (1U<<31)    /**< Resume/remote wakeup
-                                                 detected interrupt mask.   */
-#define GINTMSK_SRQM            (1U<<30)    /**< Session request/New session
-                                                 detected interrupt mask.   */
-#define GINTMSK_DISCM           (1U<<29)    /**< Disconnect detected
-                                                 interrupt mask.            */
-#define GINTMSK_CIDSCHGM        (1U<<28)    /**< Connector ID status change
-                                                 mask.                      */
-#define GINTMSK_PTXFEM          (1U<<26)    /**< Periodic TxFIFO empty mask.*/
-#define GINTMSK_HCM             (1U<<25)    /**< Host channels interrupt
-                                                 mask.                      */
-#define GINTMSK_HPRTM           (1U<<24)    /**< Host port interrupt mask.  */
-#define GINTMSK_IPXFRM          (1U<<21)    /**< Incomplete periodic
-                                                 transfer mask.             */
-#define GINTMSK_IISOOXFRM       (1U<<21)    /**< Incomplete isochronous OUT
-                                                 transfer mask.             */
-#define GINTMSK_IISOIXFRM       (1U<<20)    /**< Incomplete isochronous IN
-                                                 transfer mask.             */
-#define GINTMSK_OEPM            (1U<<19)    /**< OUT endpoints interrupt
-                                                 mask.                      */
-#define GINTMSK_IEPM            (1U<<18)    /**< IN endpoints interrupt
-                                                 mask.                      */
-#define GINTMSK_EOPFM           (1U<<15)    /**< End of periodic frame
-                                                 interrupt mask.            */
-#define GINTMSK_ISOODRPM        (1U<<14)    /**< Isochronous OUT packet
-                                                 dropped interrupt mask.    */
-#define GINTMSK_ENUMDNEM        (1U<<13)    /**< Enumeration done mask.     */
-#define GINTMSK_USBRSTM         (1U<<12)    /**< USB reset mask.            */
-#define GINTMSK_USBSUSPM        (1U<<11)    /**< USB suspend mask.          */
-#define GINTMSK_ESUSPM          (1U<<10)    /**< Early suspend mask.        */
-#define GINTMSK_GONAKEFFM       (1U<<7)     /**< Global OUT NAK effective
-                                                 mask.                      */
-#define GINTMSK_GINAKEFFM       (1U<<6)     /**< Global non-periodic IN NAK
-                                                 effective mask.            */
-#define GINTMSK_NPTXFEM         (1U<<5)     /**< Non-periodic TxFIFO empty
-                                                 mask.                      */
-#define GINTMSK_RXFLVLM         (1U<<4)     /**< Receive FIFO non-empty
-                                                 mask.                      */
-#define GINTMSK_SOFM            (1U<<3)     /**< Start of (micro)frame mask.*/
-#define GINTMSK_OTGM            (1U<<2)     /**< OTG interrupt mask.        */
-#define GINTMSK_MMISM           (1U<<1)     /**< Mode Mismatch interrupt
-                                                 mask.                      */
-/** @} */
-
-/**
- * @name GRXSTSR register bit definitions
- * @{
- */
-#define GRXSTSR_PKTSTS_MASK     (15U<<17)   /**< Packet status mask.        */
-#define GRXSTSR_PKTSTS(n)       ((n)<<17)   /**< Packet status value.       */
-#define GRXSTSR_OUT_GLOBAL_NAK  GRXSTSR_PKTSTS(1)
-#define GRXSTSR_OUT_DATA        GRXSTSR_PKTSTS(2)
-#define GRXSTSR_OUT_COMP        GRXSTSR_PKTSTS(3)
-#define GRXSTSR_SETUP_COMP      GRXSTSR_PKTSTS(4)
-#define GRXSTSR_SETUP_DATA      GRXSTSR_PKTSTS(6)
-#define GRXSTSR_DPID_MASK       (3U<<15)    /**< Data PID mask.             */
-#define GRXSTSR_DPID(n)         ((n)<<15)   /**< Data PID value.            */
-#define GRXSTSR_BCNT_MASK       (0x7FF<<4)  /**< Byte count mask.           */
-#define GRXSTSR_BCNT(n)         ((n)<<4)    /**< Byte count value.          */
-#define GRXSTSR_CHNUM_MASK      (15U<<0)    /**< Channel number mask.       */
-#define GRXSTSR_CHNUM(n)        ((n)<<0)    /**< Channel number value.      */
-#define GRXSTSR_EPNUM_MASK      (15U<<0)    /**< Endpoint number mask.      */
-#define GRXSTSR_EPNUM(n)        ((n)<<0)    /**< Endpoint number value.     */
-/** @} */
-
-/**
- * @name GRXSTSP register bit definitions
- * @{
- */
-#define GRXSTSP_PKTSTS_MASK     (15<<17)    /**< Packet status mask.        */
-#define GRXSTSP_PKTSTS(n)       ((n)<<17)   /**< Packet status value.       */
-#define GRXSTSP_OUT_GLOBAL_NAK  GRXSTSP_PKTSTS(1)
-#define GRXSTSP_OUT_DATA        GRXSTSP_PKTSTS(2)
-#define GRXSTSP_OUT_COMP        GRXSTSP_PKTSTS(3)
-#define GRXSTSP_SETUP_COMP      GRXSTSP_PKTSTS(4)
-#define GRXSTSP_SETUP_DATA      GRXSTSP_PKTSTS(6)
-#define GRXSTSP_DPID_MASK       (3U<<15)    /**< Data PID mask.             */
-#define GRXSTSP_DPID(n)         ((n)<<15)   /**< Data PID value.            */
-#define GRXSTSP_BCNT_MASK       (0x7FF<<4)  /**< Byte count mask.           */
-#define GRXSTSP_BCNT_OFF        4           /**< Byte count offset.         */
-#define GRXSTSP_BCNT(n)         ((n)<<4)    /**< Byte count value.          */
-#define GRXSTSP_CHNUM_MASK      (15U<<0)    /**< Channel number mask.       */
-#define GRXSTSP_CHNUM(n)        ((n)<<0)    /**< Channel number value.      */
-#define GRXSTSP_EPNUM_MASK      (15U<<0)    /**< Endpoint number mask.      */
-#define GRXSTSP_EPNUM_OFF       0           /**< Endpoint number offset.    */
-#define GRXSTSP_EPNUM(n)        ((n)<<0)    /**< Endpoint number value.     */
-/** @} */
-
-/**
- * @name GRXFSIZ register bit definitions
- * @{
- */
-#define GRXFSIZ_RXFD_MASK       (0xFFFF<<0) /**< RxFIFO depth mask.         */
-#define GRXFSIZ_RXFD(n)         ((n)<<0)    /**< RxFIFO depth value.        */
-/** @} */
-
-/**
- * @name DIEPTXFx register bit definitions
- * @{
- */
-#define DIEPTXF_INEPTXFD_MASK   (0xFFFFU<<16)/**< IN endpoint TxFIFO depth
-                                                 mask.                      */
-#define DIEPTXF_INEPTXFD(n)     ((n)<<16)   /**< IN endpoint TxFIFO depth
-                                                 value.                     */
-#define DIEPTXF_INEPTXSA_MASK   (0xFFFF<<0) /**< IN endpoint FIFOx transmit
-                                                 RAM start address mask.    */
-#define DIEPTXF_INEPTXSA(n)     ((n)<<0)    /**< IN endpoint FIFOx transmit
-                                                 RAM start address value.   */
-/** @} */
-
-/**
- * @name GCCFG register bit definitions
- * @{
- */
-#define GCCFG_NOVBUSSENS        (1U<<21)    /**< VBUS sensing disable.      */
-#define GCCFG_SOFOUTEN          (1U<<20)    /**< SOF output enable.         */
-#define GCCFG_VBUSBSEN          (1U<<19)    /**< Enable the VBUS sensing "B"
-                                                 device.                    */
-#define GCCFG_VBUSASEN          (1U<<18)    /**< Enable the VBUS sensing "A"
-                                                 device.                    */
-#define GCCFG_PWRDWN            (1U<<16)    /**< Power down.                */
-/** @} */
-
-/**
- * @name HPTXFSIZ register bit definitions
- * @{
- */
-#define HPTXFSIZ_PTXFD_MASK     (0xFFFFU<<16)/**< Host periodic TxFIFO
-                                                 depth mask.                */
-#define HPTXFSIZ_PTXFD(n)       ((n)<<16)   /**< Host periodic TxFIFO
-                                                 depth value.               */
-#define HPTXFSIZ_PTXSA_MASK     (0xFFFFU<<0)/**< Host periodic TxFIFO
-                                                 Start address mask.        */
-#define HPTXFSIZ_PTXSA(n)       ((n)<<0)    /**< Host periodic TxFIFO
-                                                 start address value.       */
-/** @} */
-
-/**
- * @name HCFG register bit definitions
- * @{
- */
-#define HCFG_FSLSS              (1U<<2)     /**< FS- and LS-only support.   */
-#define HCFG_FSLSPCS_MASK       (3U<<0)     /**< FS/LS PHY clock select
-                                                 mask.                      */
-#define HCFG_FSLSPCS_48         (1U<<0)     /**< PHY clock is running at
-                                                 48 MHz.                    */
-#define HCFG_FSLSPCS_6          (2U<<0)     /**< PHY clock is running at
-                                                 6 MHz.                     */
-/** @} */
-
-/**
- * @name HFIR register bit definitions
- * @{
- */
-#define HFIR_FRIVL_MASK         (0xFFFFU<<0)/**< Frame interval mask.       */
-#define HFIR_FRIVL(n)           ((n)<<0)    /**< Frame interval value.      */
-/** @} */
-
-/**
- * @name HFNUM register bit definitions
- * @{
- */
-#define HFNUM_FTREM_MASK        (0xFFFFU<<16)/**< Frame time Remaining mask.*/
-#define HFNUM_FTREM(n)          ((n)<<16)   /**< Frame time Remaining value.*/
-#define HFNUM_FRNUM_MASK        (0xFFFFU<<0)/**< Frame number mask.         */
-#define HFNUM_FRNUM(n)          ((n)<<0)    /**< Frame number value.        */
-/** @} */
-
-/**
- * @name HPTXSTS register bit definitions
- * @{
- */
-#define HPTXSTS_PTXQTOP_MASK    (0xFFU<<24) /**< Top of the periodic
-                                                 transmit request queue
-                                                 mask.                      */
-#define HPTXSTS_PTXQTOP(n)      ((n)<<24)   /**< Top of the periodic
-                                                 transmit request queue
-                                                 value.                     */
-#define HPTXSTS_PTXQSAV_MASK    (0xFF<<16)  /**< Periodic transmit request
-                                                 queue Space Available
-                                                 mask.                      */
-#define HPTXSTS_PTXQSAV(n)      ((n)<<16)   /**< Periodic transmit request
-                                                 queue Space Available
-                                                 value.                     */
-#define HPTXSTS_PTXFSAVL_MASK   (0xFFFF<<0) /**< Periodic transmit Data
-                                                 FIFO Space Available
-                                                 mask.                      */
-#define HPTXSTS_PTXFSAVL(n)     ((n)<<0)    /**< Periodic transmit Data
-                                                 FIFO Space Available
-                                                 value.                     */
-/** @} */
-
-/**
- * @name HAINT register bit definitions
- * @{
- */
-#define HAINT_HAINT_MASK        (0xFFFFU<<0)/**< Channel interrupts mask.   */
-#define HAINT_HAINT(n)          ((n)<<0)    /**< Channel interrupts value.  */
-/** @} */
-
-/**
- * @name HAINTMSK register bit definitions
- * @{
- */
-#define HAINTMSK_HAINTM_MASK    (0xFFFFU<<0)/**< Channel interrupt mask
-                                                 mask.                      */
-#define HAINTMSK_HAINTM(n)      ((n)<<0)    /**< Channel interrupt mask
-                                                 value.                     */
-/** @} */
-
-/**
- * @name HPRT register bit definitions
- * @{
- */
-#define HPRT_PSPD_MASK          (3U<<17)    /**< Port speed mask.           */
-#define HPRT_PSPD_FS            (1U<<17)    /**< Full speed value.          */
-#define HPRT_PSPD_LS            (2U<<17)    /**< Low speed value.           */
-#define HPRT_PTCTL_MASK         (15<<13)    /**< Port Test control mask.    */
-#define HPRT_PTCTL(n)           ((n)<<13)   /**< Port Test control value.   */
-#define HPRT_PPWR               (1U<<12)    /**< Port power.                */
-#define HPRT_PLSTS_MASK         (3U<<11)    /**< Port Line status mask.     */
-#define HPRT_PLSTS_DM           (1U<<11)    /**< Logic level of D-.         */
-#define HPRT_PLSTS_DP           (1U<<10)    /**< Logic level of D+.         */
-#define HPRT_PRST               (1U<<8)     /**< Port reset.                */
-#define HPRT_PSUSP              (1U<<7)     /**< Port suspend.              */
-#define HPRT_PRES               (1U<<6)     /**< Port Resume.               */
-#define HPRT_POCCHNG            (1U<<5)     /**< Port overcurrent change.   */
-#define HPRT_POCA               (1U<<4)     /**< Port overcurrent active.   */
-#define HPRT_PENCHNG            (1U<<3)     /**< Port enable/disable change.*/
-#define HPRT_PENA               (1U<<2)     /**< Port enable.               */
-#define HPRT_PCDET              (1U<<1)     /**< Port Connect detected.     */
-#define HPRT_PCSTS              (1U<<0)     /**< Port connect status.       */
-/** @} */
-
-/**
- * @name HCCHAR register bit definitions
- * @{
- */
-#define HCCHAR_CHENA            (1U<<31)    /**< Channel enable.            */
-#define HCCHAR_CHDIS            (1U<<30)    /**< Channel Disable.           */
-#define HCCHAR_ODDFRM           (1U<<29)    /**< Odd frame.                 */
-#define HCCHAR_DAD_MASK         (0x7FU<<22) /**< Device Address mask.       */
-#define HCCHAR_DAD(n)           ((n)<<22)   /**< Device Address value.      */
-#define HCCHAR_MCNT_MASK        (3U<<20)    /**< Multicount mask.           */
-#define HCCHAR_MCNT(n)          ((n)<<20)   /**< Multicount value.          */
-#define HCCHAR_EPTYP_MASK       (3U<<18)    /**< Endpoint type mask.        */
-#define HCCHAR_EPTYP(n)         ((n)<<18)   /**< Endpoint type value.       */
-#define HCCHAR_EPTYP_CTL        (0U<<18)    /**< Control endpoint value.    */
-#define HCCHAR_EPTYP_ISO        (1U<<18)    /**< Isochronous endpoint value.*/
-#define HCCHAR_EPTYP_BULK       (2U<<18)    /**< Bulk endpoint value.       */
-#define HCCHAR_EPTYP_INTR       (3U<<18)    /**< Interrupt endpoint value.  */
-#define HCCHAR_LSDEV            (1U<<17)    /**< Low-Speed device.          */
-#define HCCHAR_EPDIR            (1U<<15)    /**< Endpoint direction.        */
-#define HCCHAR_EPNUM_MASK       (15U<<11)   /**< Endpoint number mask.      */
-#define HCCHAR_EPNUM(n)         ((n)<<11)   /**< Endpoint number value.     */
-#define HCCHAR_MPS_MASK         (0x7FFU<<0)    /**< Maximum packet size mask.  */
-#define HCCHAR_MPS(n)           ((n)<<0)    /**< Maximum packet size value. */
-/** @} */
-
-/**
- * @name HCINT register bit definitions
- * @{
- */
-#define HCINT_DTERR             (1U<<10)    /**< Data toggle error.         */
-#define HCINT_FRMOR             (1U<<9)     /**< Frame overrun.             */
-#define HCINT_BBERR             (1U<<8)     /**< Babble error.              */
-#define HCINT_TRERR             (1U<<7)     /**< Transaction Error.         */
-#define HCINT_ACK               (1U<<5)     /**< ACK response
-                                                 received/transmitted
-                                                 interrupt.                 */
-#define HCINT_NAK               (1U<<4)     /**< NAK response received
-                                                 interrupt.                 */
-#define HCINT_STALL             (1U<<3)     /**< STALL response received
-                                                 interrupt.                 */
-#define HCINT_CHH               (1U<<1)     /**< Channel halted.            */
-#define HCINT_XFRC              (1U<<0)     /**< Transfer completed.        */
-/** @} */
-
-/**
- * @name HCINTMSK register bit definitions
- * @{
- */
-#define HCINTMSK_DTERRM         (1U<<10)    /**< Data toggle error mask.    */
-#define HCINTMSK_FRMORM         (1U<<9)     /**< Frame overrun mask.        */
-#define HCINTMSK_BBERRM         (1U<<8)     /**< Babble error mask.         */
-#define HCINTMSK_TRERRM         (1U<<7)     /**< Transaction error mask.    */
-#define HCINTMSK_NYET           (1U<<6)     /**< NYET response received
-                                                 interrupt mask.            */
-#define HCINTMSK_ACKM           (1U<<5)     /**< ACK Response
-                                                 received/transmitted
-                                                 interrupt mask.            */
-#define HCINTMSK_NAKM           (1U<<4)     /**< NAK response received
-                                                 interrupt mask.            */
-#define HCINTMSK_STALLM         (1U<<3)     /**< STALL response received
-                                                 interrupt mask.            */
-#define HCINTMSK_AHBERRM        (1U<<2)
-#define HCINTMSK_CHHM           (1U<<1)     /**< Channel halted mask.       */
-#define HCINTMSK_XFRCM          (1U<<0)     /**< Transfer completed mask.   */
-/** @} */
-
-/**
- * @name HCTSIZ register bit definitions
- * @{
- */
-#define HCTSIZ_DPID_MASK        (3U<<29)    /**< PID mask.                  */
-#define HCTSIZ_DPID_DATA0       (0U<<29)    /**< DATA0.                     */
-#define HCTSIZ_DPID_DATA2       (1U<<29)    /**< DATA2.                     */
-#define HCTSIZ_DPID_DATA1       (2U<<29)    /**< DATA1.                     */
-#define HCTSIZ_DPID_MDATA       (3U<<29)    /**< MDATA.                     */
-#define HCTSIZ_DPID_SETUP       (3U<<29)    /**< SETUP.                     */
-#define HCTSIZ_PKTCNT_MASK      (0x3FFU<<19)/**< Packet count mask.         */
-#define HCTSIZ_PKTCNT(n)        ((n)<<19)   /**< Packet count value.        */
-#define HCTSIZ_XFRSIZ_MASK      (0x7FFFF<<0)/**< Transfer size mask.        */
-#define HCTSIZ_XFRSIZ(n)        ((n)<<0)    /**< Transfer size value.       */
-/** @} */
-
-/**
- * @name DCFG register bit definitions
- * @{
- */
-#define DCFG_PFIVL_MASK         (3U<<11)    /**< Periodic frame interval
-                                                 mask.                      */
-#define DCFG_PFIVL(n)           ((n)<<11)   /**< Periodic frame interval
-                                                 value.                     */
-#define DCFG_DAD_MASK           (0x7FU<<4)  /**< Device address mask.       */
-#define DCFG_DAD(n)             ((n)<<4)    /**< Device address value.      */
-#define DCFG_NZLSOHSK           (1U<<2)     /**< Non-Zero-Length status
-                                                 OUT handshake.             */
-#define DCFG_DSPD_MASK          (3U<<0)     /**< Device speed mask.         */
-#define DCFG_DSPD_HS            (0U<<0)     /**< High speed (USB 2.0).      */
-#define DCFG_DSPD_HS_FS         (1U<<0)     /**< High speed (USB 2.0) in FS
-                                                 mode.                      */
-#define DCFG_DSPD_FS11          (3U<<0)     /**< Full speed (USB 1.1
-                                                 transceiver clock is 48
-                                                 MHz).                      */
-/** @} */
-
-/**
- * @name DCTL register bit definitions
- * @{
- */
-#define DCTL_POPRGDNE           (1U<<11)    /**< Power-on programming done. */
-#define DCTL_CGONAK             (1U<<10)    /**< Clear global OUT NAK.      */
-#define DCTL_SGONAK             (1U<<9)     /**< Set global OUT NAK.        */
-#define DCTL_CGINAK             (1U<<8)     /**< Clear global non-periodic
-                                                 IN NAK.                    */
-#define DCTL_SGINAK             (1U<<7)     /**< Set global non-periodic
-                                                 IN NAK.                    */
-#define DCTL_TCTL_MASK          (7U<<4)     /**< Test control mask.         */
-#define DCTL_TCTL(n)            ((n)<<4     /**< Test control value.        */
-#define DCTL_GONSTS             (1U<<3)     /**< Global OUT NAK status.     */
-#define DCTL_GINSTS             (1U<<2)     /**< Global non-periodic IN
-                                                 NAK status.                */
-#define DCTL_SDIS               (1U<<1)     /**< Soft disconnect.           */
-#define DCTL_RWUSIG             (1U<<0)     /**< Remote wakeup signaling.   */
-/** @} */
-
-/**
- * @name DSTS register bit definitions
- * @{
- */
-#define DSTS_FNSOF_MASK         (0x3FFU<<8) /**< Frame number of the received
-                                                 SOF mask.                  */
-#define DSTS_FNSOF(n)           ((n)<<8)    /**< Frame number of the received
-                                                 SOF value.                 */
-#define DSTS_FNSOF_ODD          (1U<<8)     /**< Frame parity of the received
-                                                 SOF value.                 */
-#define DSTS_EERR               (1U<<3)     /**< Erratic error.             */
-#define DSTS_ENUMSPD_MASK       (3U<<1)     /**< Enumerated speed mask.     */
-#define DSTS_ENUMSPD_FS_48      (3U<<1)     /**< Full speed (PHY clock is
-                                                 running at 48 MHz).        */
-#define DSTS_ENUMSPD_HS_480     (0U<<1)     /**< High speed.                */
-#define DSTS_SUSPSTS            (1U<<0)     /**< Suspend status.            */
-/** @} */
-
-/**
- * @name DIEPMSK register bit definitions
- * @{
- */
-#define DIEPMSK_TXFEM           (1U<<6)     /**< Transmit FIFO empty mask.  */
-#define DIEPMSK_INEPNEM         (1U<<6)     /**< IN endpoint NAK effective
-                                                 mask.                      */
-#define DIEPMSK_ITTXFEMSK       (1U<<4)     /**< IN token received when
-                                                 TxFIFO empty mask.         */
-#define DIEPMSK_TOCM            (1U<<3)     /**< Timeout condition mask.    */
-#define DIEPMSK_EPDM            (1U<<1)     /**< Endpoint disabled
-                                                 interrupt mask.            */
-#define DIEPMSK_XFRCM           (1U<<0)     /**< Transfer completed
-                                                 interrupt mask.            */
-/** @} */
-
-/**
- * @name DOEPMSK register bit definitions
- * @{
- */
-#define DOEPMSK_OTEPDM          (1U<<4)     /**< OUT token received when
-                                                 endpoint disabled mask.    */
-#define DOEPMSK_STUPM           (1U<<3)     /**< SETUP phase done mask.     */
-#define DOEPMSK_EPDM            (1U<<1)     /**< Endpoint disabled
-                                                 interrupt mask.            */
-#define DOEPMSK_XFRCM           (1U<<0)     /**< Transfer completed
-                                                 interrupt mask.            */
-/** @} */
-
-/**
- * @name DAINT register bit definitions
- * @{
- */
-#define DAINT_OEPINT_MASK       (0xFFFFU<<16)/**< OUT endpoint interrupt
-                                                 bits mask.                 */
-#define DAINT_OEPINT(n)         ((n)<<16)   /**< OUT endpoint interrupt
-                                                 bits value.                */
-#define DAINT_IEPINT_MASK       (0xFFFFU<<0)/**< IN endpoint interrupt
-                                                 bits mask.                 */
-#define DAINT_IEPINT(n)         ((n)<<0)    /**< IN endpoint interrupt
-                                                 bits value.                */
-/** @} */
-
-/**
- * @name DAINTMSK register bit definitions
- * @{
- */
-#define DAINTMSK_OEPM_MASK      (0xFFFFU<<16)/**< OUT EP interrupt mask
-                                                 bits mask.                 */
-#define DAINTMSK_OEPM(n)        (1U<<(16+(n)))/**< OUT EP interrupt mask
-                                                 bits value.                */
-#define DAINTMSK_IEPM_MASK      (0xFFFFU<<0)/**< IN EP interrupt mask
-                                                 bits mask.                 */
-#define DAINTMSK_IEPM(n)        (1U<<(n))   /**< IN EP interrupt mask
-                                                 bits value.                */
-/** @} */
-
-/**
- * @name DVBUSDIS register bit definitions
- * @{
- */
-#define DVBUSDIS_VBUSDT_MASK    (0xFFFFU<<0)/**< Device VBUS discharge
-                                                 time mask.                 */
-#define DVBUSDIS_VBUSDT(n)      ((n)<<0)    /**< Device VBUS discharge
-                                                 time value.                */
-/** @} */
-
-/**
- * @name DVBUSPULSE register bit definitions
- * @{
- */
-#define DVBUSPULSE_DVBUSP_MASK  (0xFFFU<<0) /**< Device VBUSpulsing time
-                                                 mask.                      */
-#define DVBUSPULSE_DVBUSP(n)    ((n)<<0)    /**< Device VBUS pulsing time
-                                                 value.                     */
-/** @} */
-
-/**
- * @name DIEPEMPMSK register bit definitions
- * @{
- */
-#define DIEPEMPMSK_INEPTXFEM(n) (1U<<(n))   /**< IN EP Tx FIFO empty
-                                                 interrupt mask bit.        */
-/** @} */
-
-/**
- * @name DIEPCTL register bit definitions
- * @{
- */
-#define DIEPCTL_EPENA           (1U<<31)    /**< Endpoint enable.           */
-#define DIEPCTL_EPDIS           (1U<<30)    /**< Endpoint disable.          */
-#define DIEPCTL_SD1PID          (1U<<29)    /**< Set DATA1 PID.             */
-#define DIEPCTL_SODDFRM         (1U<<29)    /**< Set odd frame.             */
-#define DIEPCTL_SD0PID          (1U<<28)    /**< Set DATA0 PID.             */
-#define DIEPCTL_SEVNFRM         (1U<<28)    /**< Set even frame.            */
-#define DIEPCTL_SNAK            (1U<<27)    /**< Set NAK.                   */
-#define DIEPCTL_CNAK            (1U<<26)    /**< Clear NAK.                 */
-#define DIEPCTL_TXFNUM_MASK     (15U<<22)   /**< TxFIFO number mask.        */
-#define DIEPCTL_TXFNUM(n)       ((n)<<22)   /**< TxFIFO number value.       */
-#define DIEPCTL_STALL           (1U<<21)    /**< STALL handshake.           */
-#define DIEPCTL_SNPM            (1U<<20)    /**< Snoop mode.                */
-#define DIEPCTL_EPTYP_MASK      (3<<18)     /**< Endpoint type mask.        */
-#define DIEPCTL_EPTYP_CTRL      (0U<<18)    /**< Control.                   */
-#define DIEPCTL_EPTYP_ISO       (1U<<18)    /**< Isochronous.               */
-#define DIEPCTL_EPTYP_BULK      (2U<<18)    /**< Bulk.                      */
-#define DIEPCTL_EPTYP_INTR      (3U<<18)    /**< Interrupt.                 */
-#define DIEPCTL_NAKSTS          (1U<<17)    /**< NAK status.                */
-#define DIEPCTL_EONUM           (1U<<16)    /**< Even/odd frame.            */
-#define DIEPCTL_DPID            (1U<<16)    /**< Endpoint data PID.         */
-#define DIEPCTL_USBAEP          (1U<<15)    /**< USB active endpoint.       */
-#define DIEPCTL_MPSIZ_MASK      (0x3FFU<<0) /**< Maximum Packet size mask.  */
-#define DIEPCTL_MPSIZ(n)        ((n)<<0)    /**< Maximum Packet size value. */
-/** @} */
-
-/**
- * @name DIEPINT register bit definitions
- * @{
- */
-#define DIEPINT_TXFE            (1U<<7)     /**< Transmit FIFO empty.       */
-#define DIEPINT_INEPNE          (1U<<6)     /**< IN endpoint NAK effective. */
-#define DIEPINT_ITTXFE          (1U<<4)     /**< IN Token received when
-                                                 TxFIFO is empty.           */
-#define DIEPINT_TOC             (1U<<3)     /**< Timeout condition.         */
-#define DIEPINT_EPDISD          (1U<<1)     /**< Endpoint disabled
-                                                 interrupt.                 */
-#define DIEPINT_XFRC            (1U<<0)     /**< Transfer completed.        */
-/** @} */
-
-/**
- * @name DIEPTSIZ register bit definitions
- * @{
- */
-#define DIEPTSIZ_MCNT_MASK      (3U<<29)    /**< Multi count mask.          */
-#define DIEPTSIZ_MCNT(n)        ((n)<<29)   /**< Multi count value.         */
-#define DIEPTSIZ_PKTCNT_MASK    (0x3FF<<19) /**< Packet count mask.         */
-#define DIEPTSIZ_PKTCNT(n)      ((n)<<19)   /**< Packet count value.        */
-#define DIEPTSIZ_XFRSIZ_MASK    (0x7FFFFU<<0)/**< Transfer size mask.       */
-#define DIEPTSIZ_XFRSIZ(n)      ((n)<<0)    /**< Transfer size value.       */
-/** @} */
-
-/**
- * @name DTXFSTS register bit definitions.
- * @{
- */
-#define DTXFSTS_INEPTFSAV_MASK  (0xFFFF<<0) /**< IN endpoint TxFIFO space
-                                                 available.                 */
-/** @} */
-
-/**
- * @name DOEPCTL register bit definitions.
- * @{
- */
-#define DOEPCTL_EPENA           (1U<<31)    /**< Endpoint enable.           */
-#define DOEPCTL_EPDIS           (1U<<30)    /**< Endpoint disable.          */
-#define DOEPCTL_SD1PID          (1U<<29)    /**< Set DATA1 PID.             */
-#define DOEPCTL_SODDFRM         (1U<<29)    /**< Set odd frame.             */
-#define DOEPCTL_SD0PID          (1U<<28)    /**< Set DATA0 PID.             */
-#define DOEPCTL_SEVNFRM         (1U<<28)    /**< Set even frame.            */
-#define DOEPCTL_SNAK            (1U<<27)    /**< Set NAK.                   */
-#define DOEPCTL_CNAK            (1U<<26)    /**< Clear NAK.                 */
-#define DOEPCTL_STALL           (1U<<21)    /**< STALL handshake.           */
-#define DOEPCTL_SNPM            (1U<<20)    /**< Snoop mode.                */
-#define DOEPCTL_EPTYP_MASK      (3U<<18)    /**< Endpoint type mask.        */
-#define DOEPCTL_EPTYP_CTRL      (0U<<18)    /**< Control.                   */
-#define DOEPCTL_EPTYP_ISO       (1U<<18)    /**< Isochronous.               */
-#define DOEPCTL_EPTYP_BULK      (2U<<18)    /**< Bulk.                      */
-#define DOEPCTL_EPTYP_INTR      (3U<<18)    /**< Interrupt.                 */
-#define DOEPCTL_NAKSTS          (1U<<17)    /**< NAK status.                */
-#define DOEPCTL_EONUM           (1U<<16)    /**< Even/odd frame.            */
-#define DOEPCTL_DPID            (1U<<16)    /**< Endpoint data PID.         */
-#define DOEPCTL_USBAEP          (1U<<15)    /**< USB active endpoint.       */
-#define DOEPCTL_MPSIZ_MASK      (0x3FFU<<0) /**< Maximum Packet size mask.  */
-#define DOEPCTL_MPSIZ(n)        ((n)<<0)    /**< Maximum Packet size value. */
-/** @} */
-
-/**
- * @name DOEPINT register bit definitions
- * @{
- */
-#define DOEPINT_B2BSTUP         (1U<<6)     /**< Back-to-back SETUP packets
-                                                 received.                  */
-#define DOEPINT_OTEPDIS         (1U<<4)     /**< OUT token received when
-                                                 endpoint disabled.         */
-#define DOEPINT_STUP            (1U<<3)     /**< SETUP phase done.          */
-#define DOEPINT_EPDISD          (1U<<1)     /**< Endpoint disabled
-                                                 interrupt.                 */
-#define DOEPINT_XFRC            (1U<<0)     /**< Transfer completed
-                                                 interrupt.                 */
-/** @} */
-
-/**
- * @name DOEPTSIZ register bit definitions
- * @{
- */
-#define DOEPTSIZ_RXDPID_MASK    (3U<<29)    /**< Received data PID mask.    */
-#define DOEPTSIZ_RXDPID(n)      ((n)<<29)   /**< Received data PID value.   */
-#define DOEPTSIZ_STUPCNT_MASK   (3U<<29)    /**< SETUP packet count mask.   */
-#define DOEPTSIZ_STUPCNT(n)     ((n)<<29)   /**< SETUP packet count value.  */
-#define DOEPTSIZ_PKTCNT_MASK    (0x3FFU<<19)/**< Packet count mask.         */
-#define DOEPTSIZ_PKTCNT(n)      ((n)<<19)   /**< Packet count value.        */
-#define DOEPTSIZ_XFRSIZ_MASK    (0x7FFFFU<<0)/**< Transfer size mask.       */
-#define DOEPTSIZ_XFRSIZ(n)      ((n)<<0)    /**< Transfer size value.       */
-/** @} */
-
-/**
- * @name PCGCCTL register bit definitions
- * @{
- */
-#define PCGCCTL_PHYSUSP         (1U<<4)     /**< PHY Suspended.             */
-#define PCGCCTL_GATEHCLK        (1U<<1)     /**< Gate HCLK.                 */
-#define PCGCCTL_STPPCLK         (1U<<0)     /**< Stop PCLK.                 */
-/** @} */
-
-/**
- * @brief   OTG_FS registers block memory address.
- */
-#define OTG_FS_ADDR                 0x50000000
-
-/**
- * @brief   OTG_HS registers block memory address.
- */
-#define OTG_HS_ADDR                 0x40040000
-
-/**
- * @brief   Accesses to the OTG_FS registers block.
- */
-#define OTG_FS                      ((stm32_otg_t *)OTG_FS_ADDR)
-
-/**
- * @brief   Accesses to the OTG_HS registers block.
- */
-#define OTG_HS                      ((stm32_otg_t *)OTG_HS_ADDR)
-
-#endif /* _STM32_OTG_H_ */
-
-/** @} */
diff --git a/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c b/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c
index 3abab1c..2894907 100644
--- a/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c
+++ b/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c
@@ -1,6 +1,6 @@
 /*
-    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
-              Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail)
+    ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio
+              Copyright (C) 2015..2017 Diego Ismirlian, (dismirlian (at) google's mail)
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -21,6 +21,53 @@
 #include "usbh/internal.h"
 #include <string.h>
 
+#if STM32_USBH_USE_OTG1
+#if !defined(STM32_OTG1_CHANNELS_NUMBER)
+#error "STM32_OTG1_CHANNELS_NUMBER must be defined"
+#endif
+#if !defined(STM32_OTG1_RXFIFO_SIZE)
+#define STM32_OTG1_RXFIFO_SIZE		1024
+#endif
+#if !defined(STM32_OTG1_PTXFIFO_SIZE)
+#define STM32_OTG1_PTXFIFO_SIZE		128
+#endif
+#if !defined(STM32_OTG1_NPTXFIFO_SIZE)
+#define STM32_OTG1_NPTXFIFO_SIZE	128
+#endif
+#if (STM32_OTG1_RXFIFO_SIZE + STM32_OTG1_PTXFIFO_SIZE + STM32_OTG1_NPTXFIFO_SIZE) > (STM32_OTG1_FIFO_MEM_SIZE * 4)
+#error "Not enough memory in OTG1 implementation"
+#elif (STM32_OTG1_RXFIFO_SIZE + STM32_OTG1_PTXFIFO_SIZE + STM32_OTG1_NPTXFIFO_SIZE) < (STM32_OTG1_FIFO_MEM_SIZE * 4)
+#warning "Spare memory in OTG1; could enlarge RX, PTX or NPTX FIFO sizes"
+#endif
+#if (STM32_OTG1_RXFIFO_SIZE % 4) || (STM32_OTG1_PTXFIFO_SIZE % 4) || (STM32_OTG1_NPTXFIFO_SIZE % 4)
+#error "FIFO sizes must be a multiple of 32-bit words"
+#endif
+#endif
+
+#if STM32_USBH_USE_OTG2
+#if !defined(STM32_OTG2_CHANNELS_NUMBER)
+#error "STM32_OTG2_CHANNELS_NUMBER must be defined"
+#endif
+#if !defined(STM32_OTG2_RXFIFO_SIZE)
+#define STM32_OTG2_RXFIFO_SIZE		2048
+#endif
+#if !defined(STM32_OTG2_PTXFIFO_SIZE)
+#define STM32_OTG2_PTXFIFO_SIZE		1024
+#endif
+#if !defined(STM32_OTG2_NPTXFIFO_SIZE)
+#define STM32_OTG2_NPTXFIFO_SIZE	1024
+#endif
+#if (STM32_OTG2_RXFIFO_SIZE + STM32_OTG2_PTXFIFO_SIZE + STM32_OTG2_NPTXFIFO_SIZE) > (STM32_OTG2_FIFO_MEM_SIZE * 4)
+#error "Not enough memory in OTG2 implementation"
+#elif (STM32_OTG2_RXFIFO_SIZE + STM32_OTG2_PTXFIFO_SIZE + STM32_OTG2_NPTXFIFO_SIZE) < (STM32_OTG2_FIFO_MEM_SIZE * 4)
+#warning "Spare memory in OTG2; could enlarge RX, PTX or NPTX FIFO sizes"
+#endif
+#if (STM32_OTG2_RXFIFO_SIZE % 4) || (STM32_OTG2_PTXFIFO_SIZE % 4) || (STM32_OTG2_NPTXFIFO_SIZE % 4)
+#error "FIFO sizes must be a multiple of 32-bit words"
+#endif
+#endif
+
+
 #if USBH_LLD_DEBUG_ENABLE_TRACE
 #define udbgf(f, ...)  usbDbgPrintf(f, ##__VA_ARGS__)
 #define udbg(f, ...)  usbDbgPuts(f, ##__VA_ARGS__)
@@ -58,8 +105,15 @@ static void _try_commit_np(USBHDriver *host);
 static void otg_rxfifo_flush(USBHDriver *usbp);
 static void otg_txfifo_flush(USBHDriver *usbp, uint32_t fifo);
 
+#if STM32_USBH_USE_OTG1
+USBHDriver USBHD1;
+#endif
+#if STM32_USBH_USE_OTG2
+USBHDriver USBHD2;
+#endif
+
 /*===========================================================================*/
-/* Little helper functions.	    	                                 		 */
+/* Little helper functions.                                                  */
 /*===========================================================================*/
 static inline void _move_to_pending_queue(usbh_ep_t *ep) {
 	list_move_tail(&ep->node, ep->pending_list);
@@ -73,18 +127,8 @@ static inline void _save_dt_mask(usbh_ep_t *ep, uint32_t hctsiz) {
 	ep->dt_mask = hctsiz & HCTSIZ_DPID_MASK;
 }
 
-#if 1
-#define _transfer_completed _transfer_completedI
-#else
-static inline void _transfer_completed(usbh_ep_t *ep, usbh_urb_t *urb, usbh_urbstatus_t status) {
-	osalSysLockFromISR();
-	_transfer_completedI(ep, urb, status);
-	osalSysUnlockFromISR();
-}
-#endif
-
 /*===========================================================================*/
-/* Functions called from many places.                                 		 */
+/* Functions called from many places.                                        */
 /*===========================================================================*/
 static void _transfer_completedI(usbh_ep_t *ep, usbh_urb_t *urb, usbh_urbstatus_t status) {
 	osalDbgCheckClassI();
@@ -200,7 +244,6 @@ static bool _activate_ep(USBHDriver *host, usbh_ep_t *ep) {
 			ep->xfer.buf = urb->buff;
 		}
 		ep->xfer.error_count = 0;
-		//urb->status = USBH_URBSTATUS_QUEUED;
 	} else {
 		osalDbgCheck(urb->requestedLength >= urb->actualLength);
 
@@ -340,7 +383,7 @@ static bool _update_urb(usbh_ep_t *ep, uint32_t hctsiz, usbh_urb_t *urb, bool co
 		osalDbgCheck(len == ep->xfer.partial);	//TODO: if len == ep->xfer.partial, use this instead of the above code
 	}
 
-#if 1
+#if 0
 	osalDbgAssert(urb->actualLength + len <= urb->requestedLength, "what happened?");
 #else
 	if (urb->actualLength + len > urb->requestedLength) {
@@ -412,7 +455,7 @@ static void _purge_queue(USBHDriver *host, struct list_head *list) {
 			_release_channel(host, hcm);
 			_update_urb(ep, hcm->hc->HCTSIZ, urb, FALSE);
 		}
-		_transfer_completed(ep, urb, USBH_URBSTATUS_DISCONNECTED);
+		_transfer_completedI(ep, urb, USBH_URBSTATUS_DISCONNECTED);
 	}
 }
 
@@ -487,12 +530,12 @@ static uint32_t _write_packet(struct list_head *list, uint32_t space_available)
 
 
 /*===========================================================================*/
-/* API.					   	    	                                 		 */
+/* API.                                                                      */
 /*===========================================================================*/
 
 void usbh_lld_ep_object_init(usbh_ep_t *ep) {
 /*			CTRL(IN)	CTRL(OUT)	INT(IN)		INT(OUT)	BULK(IN)	BULK(OUT)	ISO(IN)		ISO(OUT)
- * STALL		si		sólo DAT/STAT	si			si			si			si			no			no		ep->type != ISO && (ep->type != CTRL || ctrlphase != SETUP)
+ * STALL		si		solo DAT/STAT	si			si			si			si			no			no		ep->type != ISO && (ep->type != CTRL || ctrlphase != SETUP)
  * ACK			si			si			si			si			si			si			no			no		ep->type != ISO
  * NAK			si			si			si			si			si			si			no			no		ep->type != ISO
  * BBERR		si			no			si			no			si			no			si			no		ep->in
@@ -548,7 +591,6 @@ void usbh_lld_ep_object_init(usbh_ep_t *ep) {
 void usbh_lld_ep_open(usbh_ep_t *ep) {
 	uinfof("\t%s: Open EP", ep->name);
 	ep->status = USBH_EPSTATUS_OPEN;
-	osalOsRescheduleS();
 }
 
 void usbh_lld_ep_close(usbh_ep_t *ep) {
@@ -560,11 +602,22 @@ void usbh_lld_ep_close(usbh_ep_t *ep) {
 	}
 	uinfof("\t%s: Closed", ep->name);
 	ep->status = USBH_EPSTATUS_CLOSED;
-	osalOsRescheduleS();
+}
+
+bool usbh_lld_ep_reset(usbh_ep_t *ep) {
+	ep->dt_mask = HCTSIZ_DPID_DATA0;
+	return TRUE;
 }
 
 void usbh_lld_urb_submit(usbh_urb_t *urb) {
 	usbh_ep_t *const ep = urb->ep;
+	USBHDriver *const host = ep->device->host;
+
+	if (!(host->otg->HPRT & HPRT_PENA)) {
+		uwarnf("\t%s: Can't submit URB, port disabled", ep->name);
+		_usbh_urb_completeI(urb, USBH_URBSTATUS_DISCONNECTED);
+		return;
+	}
 
 	/* add the URB to the EP's queue */
 	list_add_tail(&urb->node, &ep->urb_list);
@@ -576,7 +629,7 @@ void usbh_lld_urb_submit(usbh_urb_t *urb) {
 		_move_to_pending_queue(ep);
 
 		if (usbhEPIsPeriodic(ep)) {
-			ep->device->host->otg->GINTMSK |= GINTMSK_SOFM;
+			host->otg->GINTMSK |= GINTMSK_SOFM;
 		} else {
 			/* try to queue non-periodic transfers */
 			_try_commit_np(ep->device->host);
@@ -584,6 +637,7 @@ void usbh_lld_urb_submit(usbh_urb_t *urb) {
 	}
 }
 
+/* usbh_lld_urb_abort may require a reschedule if called from a S-locked state */
 bool usbh_lld_urb_abort(usbh_urb_t *urb, usbh_urbstatus_t status) {
 	osalDbgCheck(usbhURBIsBusy(urb));
 
@@ -596,17 +650,20 @@ bool usbh_lld_urb_abort(usbh_urb_t *urb, usbh_urbstatus_t status) {
 
 		if (hcm->halt_reason == USBH_LLD_HALTREASON_NONE) {
 			/* The channel is not being halted */
+			uinfof("\t%s: usbh_lld_urb_abort: channel is not being halted", hcm->ep->name);
 			urb->status = status;
 			_halt_channel(ep->device->host, hcm, USBH_LLD_HALTREASON_ABORT);
 		} else {
 			/* The channel is being halted, so we can't re-halt it. The CHH interrupt will
 			 * be in charge of completing the transfer, but the URB will not have the specified status.
 			 */
+			uinfof("\t%s: usbh_lld_urb_abort: channel is being halted", hcm->ep->name);
 		}
 		return FALSE;
 	}
 
-	/* This URB is active, we can cancel it now */
+	/* This URB is inactive, we can cancel it now */
+	uinfof("\t%s: usbh_lld_urb_abort: URB is not active", ep->name);
 	_transfer_completedI(ep, urb, status);
 
 	return TRUE;
@@ -614,7 +671,7 @@ bool usbh_lld_urb_abort(usbh_urb_t *urb, usbh_urbstatus_t status) {
 
 
 /*===========================================================================*/
-/* Channel Interrupts.   	    	                                 		 */
+/* Channel Interrupts.                                                       */
 /*===========================================================================*/
 
 //CTRL(IN)	CTRL(OUT)	INT(IN)		INT(OUT)	BULK(IN)	BULK(OUT)	ISO(IN)		ISO(OUT)
@@ -705,7 +762,7 @@ static void _complete_bulk_int(USBHDriver *host, stm32_hc_management_t *hcm, usb
 	_save_dt_mask(ep, hctsiz);
 	if (_update_urb(ep, hctsiz, urb, TRUE)) {
 		udbgf("\t%s: done", ep->name);
-		_transfer_completed(ep, urb, USBH_URBSTATUS_OK);
+		_transfer_completedI(ep, urb, USBH_URBSTATUS_OK);
 	} else {
 		osalDbgCheck(urb->requestedLength > 0x7FFFF);
 		uwarnf("\t%s: incomplete", ep->name);
@@ -736,7 +793,7 @@ static void _complete_control(USBHDriver *host, stm32_hc_management_t *hcm, usbh
 	} else {
 		osalDbgCheck(ep->xfer.u.ctrl_phase == USBH_LLD_CTRLPHASE_STATUS);
 		udbgf("\t%s: STATUS done", ep->name);
-		_transfer_completed(ep, urb, USBH_URBSTATUS_OK);
+		_transfer_completedI(ep, urb, USBH_URBSTATUS_OK);
 	}
 	_try_commit_np(host);
 }
@@ -762,7 +819,7 @@ static void _complete_iso(USBHDriver *host, stm32_hc_management_t *hcm, usbh_ep_
 	udbgf("\t%s: done", hcm->ep->name);
 	_release_channel(host, hcm);
 	_update_urb(ep, hctsiz, urb, TRUE);
-	_transfer_completed(ep, urb, USBH_URBSTATUS_OK);
+	_transfer_completedI(ep, urb, USBH_URBSTATUS_OK);
 	_try_commit_p(host, FALSE);
 }
 
@@ -847,7 +904,7 @@ static inline void _chh_int(USBHDriver *host, stm32_hc_management_t *hcm, stm32_
 		switch (reason) {
 		case USBH_LLD_HALTREASON_NAK:
 			if ((ep->type == USBH_EPTYPE_INT) && ep->in) {
-				_transfer_completed(ep, urb, USBH_URBSTATUS_TIMEOUT);
+				_transfer_completedI(ep, urb, USBH_URBSTATUS_TIMEOUT);
 			} else {
 				ep->xfer.error_count = 0;
 				_move_to_pending_queue(ep);
@@ -855,15 +912,19 @@ static inline void _chh_int(USBHDriver *host, stm32_hc_management_t *hcm, stm32_
 			break;
 
 		case USBH_LLD_HALTREASON_STALL:
-			if ((ep->type == USBH_EPTYPE_CTRL) && (ep->xfer.u.ctrl_phase == USBH_LLD_CTRLPHASE_SETUP)) {
-				uerrf("\t%s: Faulty device: STALLed SETUP phase", ep->name);
+			if (ep->type == USBH_EPTYPE_CTRL) {
+				if (ep->xfer.u.ctrl_phase == USBH_LLD_CTRLPHASE_SETUP) {
+					uerrf("\t%s: Faulty device: STALLed SETUP phase", ep->name);
+				}
+			} else {
+				ep->status = USBH_EPSTATUS_HALTED;
 			}
-			_transfer_completed(ep, urb, USBH_URBSTATUS_STALL);
+			_transfer_completedI(ep, urb, USBH_URBSTATUS_STALL);
 			break;
 
 		case USBH_LLD_HALTREASON_ERROR:
 			if ((ep->type == USBH_EPTYPE_ISO) || done || (ep->xfer.error_count >= 3)) {
-				_transfer_completed(ep, urb, USBH_URBSTATUS_ERROR);
+				_transfer_completedI(ep, urb, USBH_URBSTATUS_ERROR);
 			} else {
 				uerrf("\t%s: err=%d, done=%d, retry", ep->name, ep->xfer.error_count, done);
 				_move_to_pending_queue(ep);
@@ -872,7 +933,7 @@ static inline void _chh_int(USBHDriver *host, stm32_hc_management_t *hcm, stm32_
 
 		case USBH_LLD_HALTREASON_ABORT:
 			uwarnf("\t%s: Abort", ep->name);
-			_transfer_completed(ep, urb, urb->status);
+			_transfer_completedI(ep, urb, urb->status);
 			break;
 
 		default:
@@ -926,10 +987,15 @@ static inline void _hcint_int(USBHDriver *host) {
 	haint = host->otg->HAINT;
 	haint &= host->otg->HAINTMSK;
 
+#if USBH_LLD_DEBUG_ENABLE_ERRORS
 	if (!haint) {
-		uerrf("HAINT=%08x, HAINTMSK=%08x", host->otg->HAINT, host->otg->HAINTMSK);
+		uint32_t a, b;
+		a = host->otg->HAINT;
+		b = host->otg->HAINTMSK;
+		uerrf("HAINT=%08x, HAINTMSK=%08x", a, b);
 		return;
 	}
+#endif
 
 #if 1	//channel lookup loop
 	uint8_t i;
@@ -951,9 +1017,50 @@ static inline void _hcint_int(USBHDriver *host) {
 
 
 /*===========================================================================*/
-/* Host interrupts.			   	                                     		 */
+/* Host interrupts.                                                          */
 /*===========================================================================*/
 static inline void _sof_int(USBHDriver *host) {
+
+	/* this is part of the workaround to the LS bug in the OTG core */
+#undef HPRT_PLSTS_MASK
+#define HPRT_PLSTS_MASK (3U<<10)
+	if (host->check_ls_activity) {
+		stm32_otg_t *const otg = host->otg;
+		uint16_t remaining = otg->HFNUM >> 16;
+		if (remaining < 5975) {
+			uwarnf("LS: ISR called too late (time=%d)", 6000 - remaining);
+			return;
+		}
+		/* 15us loop during which we check if the core generates an actual keep-alive
+		 * (or activity other than idle) on the DP/DM lines. After 15us, we abort
+		 * the loop and wait for the next SOF. If no activity is detected, the upper
+		 * layer will time-out waiting for the reset to happen, and the port will remain
+		 * enabled (though in a dumb state). This will be detected on the next port reset
+		 * request and the OTG core will be reset. */
+		for (;;) {
+			uint32_t line_status = otg->HPRT & HPRT_PLSTS_MASK;
+			remaining = otg->HFNUM >> 16;
+			if (!(otg->HPRT & HPRT_PENA)) {
+				uwarn("LS: Port disabled");
+				return;
+			}
+			if (line_status != HPRT_PLSTS_DM) {
+				/* success; report that the port is enabled */
+				uinfof("LS: activity detected, line=%d, time=%d", line_status >> 10,  6000 - remaining);
+				host->check_ls_activity = FALSE;
+				otg->GINTMSK = (otg->GINTMSK & ~GINTMSK_SOFM) | (GINTMSK_HCM | GINTMSK_RXFLVLM);
+				host->rootport.lld_status |= USBH_PORTSTATUS_ENABLE;
+				host->rootport.lld_c_status |= USBH_PORTSTATUS_C_ENABLE;
+				return;
+			}
+			if (remaining < 5910) {
+				udbg("LS: No activity detected");
+				return;
+			}
+		}
+	}
+
+	/* real SOF interrupt */
 	udbg("SOF");
 	_try_commit_p(host, TRUE);
 }
@@ -1059,9 +1166,6 @@ static inline void _nptxfe_int(USBHDriver *host) {
 	rem += _write_packet(&host->ep_active_lists[USBH_EPTYPE_BULK],
 			otg->HNPTXSTS & HPTXSTS_PTXFSAVL_MASK);
 
-//	if (rem)
-//		otg->GINTMSK |= GINTMSK_NPTXFEM;
-
 	if (!rem)
 		otg->GINTMSK &= ~GINTMSK_NPTXFEM;
 
@@ -1073,17 +1177,19 @@ static inline void _ptxfe_int(USBHDriver *host) {
 	uinfo("PTXFE");
 }
 
-static inline void _discint_int(USBHDriver *host) {
-	uint32_t hprt = host->otg->HPRT;
-
-	uwarn("\tDISCINT");
+static void _disable(USBHDriver *host) {
+	host->rootport.lld_status &= ~(USBH_PORTSTATUS_CONNECTION | USBH_PORTSTATUS_ENABLE);
+	host->rootport.lld_c_status |= USBH_PORTSTATUS_C_CONNECTION | USBH_PORTSTATUS_C_ENABLE;
 
-	if (!(hprt & HPRT_PCSTS)) {
-		host->rootport.lld_status &= ~(USBH_PORTSTATUS_CONNECTION | USBH_PORTSTATUS_ENABLE);
-		host->rootport.lld_c_status |= USBH_PORTSTATUS_C_CONNECTION | USBH_PORTSTATUS_C_ENABLE;
-	}
 	_purge_active(host);
 	_purge_pending(host);
+
+	host->otg->GINTMSK &= ~(GINTMSK_HCM | GINTMSK_RXFLVLM);
+}
+
+static inline void _discint_int(USBHDriver *host) {
+	uinfo("DISCINT: Port disconnection detected");
+	_disable(host);
 }
 
 static inline void _hprtint_int(USBHDriver *host) {
@@ -1099,8 +1205,6 @@ static inline void _hprtint_int(USBHDriver *host) {
 			uinfo("\tHPRT: Port connection detected");
 			host->rootport.lld_status |= USBH_PORTSTATUS_CONNECTION;
 			host->rootport.lld_c_status |= USBH_PORTSTATUS_C_CONNECTION;
-		} else {
-			uinfo("\tHPRT: Port disconnection detected");
 		}
 	}
 
@@ -1108,9 +1212,32 @@ static inline void _hprtint_int(USBHDriver *host) {
 		hprt_clr |= HPRT_PENCHNG;
 		if (hprt & HPRT_PENA) {
 			uinfo("\tHPRT: Port enabled");
-			host->rootport.lld_status |= USBH_PORTSTATUS_ENABLE;
 			host->rootport.lld_status &= ~(USBH_PORTSTATUS_HIGH_SPEED | USBH_PORTSTATUS_LOW_SPEED);
 
+			/* configure FIFOs */
+#define HNPTXFSIZ						DIEPTXF0
+#if STM32_USBH_USE_OTG1
+#if STM32_USBH_USE_OTG2
+			if (&USBHD1 == host)
+#endif
+			{
+				otg->GRXFSIZ = GRXFSIZ_RXFD(STM32_OTG1_RXFIFO_SIZE / 4);
+				otg->HNPTXFSIZ = HPTXFSIZ_PTXSA(STM32_OTG1_RXFIFO_SIZE / 4) | HPTXFSIZ_PTXFD(STM32_OTG1_NPTXFIFO_SIZE / 4);
+				otg->HPTXFSIZ = HPTXFSIZ_PTXSA((STM32_OTG1_RXFIFO_SIZE / 4) + (STM32_OTG1_NPTXFIFO_SIZE / 4)) | HPTXFSIZ_PTXFD(STM32_OTG1_PTXFIFO_SIZE / 4);
+			}
+#endif
+#if STM32_USBH_USE_OTG2
+#if STM32_USBH_USE_OTG1
+			if (&USBHD2 == host)
+#endif
+			{
+				otg->GRXFSIZ = GRXFSIZ_RXFD(STM32_OTG2_RXFIFO_SIZE / 4);
+				otg->HNPTXFSIZ = HPTXFSIZ_PTXSA(STM32_OTG2_RXFIFO_SIZE / 4) | HPTXFSIZ_PTXFD(STM32_OTG2_NPTXFIFO_SIZE / 4);
+				otg->HPTXFSIZ = HPTXFSIZ_PTXSA((STM32_OTG2_RXFIFO_SIZE / 4) + (STM32_OTG2_NPTXFIFO_SIZE / 4)) | HPTXFSIZ_PTXFD(STM32_OTG2_PTXFIFO_SIZE / 4);
+			}
+#endif
+#undef HNPTXFSIZ
+
 			/* Make sure the FIFOs are flushed. */
 		    otg_txfifo_flush(host, 0x10);
 		    otg_rxfifo_flush(host);
@@ -1127,9 +1254,23 @@ static inline void _hprtint_int(USBHDriver *host) {
 				host->rootport.lld_status |= USBH_PORTSTATUS_LOW_SPEED;
 				otg->HFIR = 6000;
 				otg->HCFG = (otg->HCFG & ~HCFG_FSLSPCS_MASK) | HCFG_FSLSPCS_6;
+
+				/* Low speed devices connected to the STM32's internal transceiver sometimes
+				 * don't behave correctly. Although HPRT reports a port enable, really
+				 * no traffic is generated, and the core is non-functional. To avoid
+				 * this we won't report the port enable until we are sure that the
+				 * port is working. */
+				host->check_ls_activity = TRUE;
+				otg->GINTMSK |= GINTMSK_SOFM;
 			} else {
 				otg->HFIR = 48000;
 				otg->HCFG = (otg->HCFG & ~HCFG_FSLSPCS_MASK) | HCFG_FSLSPCS_48;
+				host->check_ls_activity = FALSE;
+
+				/* enable channel and rx interrupts */
+				otg->GINTMSK |= GINTMSK_HCM | GINTMSK_RXFLVLM;
+				host->rootport.lld_status |= USBH_PORTSTATUS_ENABLE;
+				host->rootport.lld_c_status |= USBH_PORTSTATUS_C_ENABLE;
 			}
 		} else {
 			if (hprt & HPRT_PCSTS) {
@@ -1141,13 +1282,8 @@ static inline void _hprtint_int(USBHDriver *host) {
 			} else {
 				uerr("\tHPRT: Port disabled due to disconnect");
 			}
-
-			_purge_active(host);
-			_purge_pending(host);
-
-			host->rootport.lld_status &= ~USBH_PORTSTATUS_ENABLE;
+			_disable(host);
 		}
-		host->rootport.lld_c_status |= USBH_PORTSTATUS_C_ENABLE;
 	}
 
 	if (hprt & HPRT_POCCHNG) {
@@ -1179,18 +1315,19 @@ static void usb_lld_serve_interrupt(USBHDriver *host) {
 	}
 
 	/* check mismatch */
-	if (gintsts & GINTSTS_MMIS) {
-		uerr("Mode Mismatch");
-		otg->GINTSTS = gintsts;
-		return;
-	}
+	osalDbgAssert((gintsts & GINTSTS_MMIS) == 0, "mode mismatch");
 
 	gintsts &= otg->GINTMSK;
 	if (!gintsts) {
-		uwarnf("GINTSTS=%08x, GINTMSK=%08x", otg->GINTSTS, otg->GINTMSK);
+#if USBH_DEBUG_ENABLE_WARNINGS
+		uint32_t a, b;
+		a = otg->GINTSTS;
+		b = otg->GINTMSK;
+		uwarnf("Masked bits caused an ISR: GINTSTS=%08x, GINTMSK=%08x (unhandled bits=%08x)", a, b, a & ~b);
+#endif
 		return;
 	}
-//	otg->GINTMSK &= ~(GINTMSK_NPTXFEM | GINTMSK_PTXFEM);
+
 	otg->GINTSTS = gintsts;
 
 	if (gintsts & GINTSTS_SOF)
@@ -1214,7 +1351,7 @@ static void usb_lld_serve_interrupt(USBHDriver *host) {
 
 
 /*===========================================================================*/
-/* Interrupt handlers.   	    	                                 		 */
+/* Interrupt handlers.                                                       */
 /*===========================================================================*/
 
 #if STM32_USBH_USE_OTG1
@@ -1239,7 +1376,7 @@ OSAL_IRQ_HANDLER(STM32_OTG2_HANDLER) {
 
 
 /*===========================================================================*/
-/* Initialization functions.   	                                     		 */
+/* Initialization functions.                                                 */
 /*===========================================================================*/
 static void otg_core_reset(USBHDriver *usbp) {
   stm32_otg_t *const otgp = usbp->otg;
@@ -1289,25 +1426,23 @@ static void _init(USBHDriver *host) {
 
 #if STM32_USBH_USE_OTG1
 #if STM32_USBH_USE_OTG2
-	if (&USBHD1 == host) {
+	if (&USBHD1 == host)
 #endif
+	{
 		host->otg = OTG_FS;
 		host->channels_number = STM32_OTG1_CHANNELS_NUMBER;
-#if STM32_USBH_USE_OTG2
 	}
 #endif
-#endif
 
 #if STM32_USBH_USE_OTG2
 #if STM32_USBH_USE_OTG1
-	if (&USBHD2 == host) {
+	if (&USBHD2 == host)
 #endif
+	{
 		host->otg = OTG_HS;
 		host->channels_number = STM32_OTG2_CHANNELS_NUMBER;
-#if STM32_USBH_USE_OTG1
 	}
 #endif
-#endif
 	INIT_LIST_HEAD(&host->ch_free[0]);
 	INIT_LIST_HEAD(&host->ch_free[1]);
 	for (i = 0; i < host->channels_number; i++) {
@@ -1341,8 +1476,9 @@ static void _usbh_start(USBHDriver *usbh) {
 	/* Clock activation.*/
 #if STM32_USBH_USE_OTG1
 #if STM32_USBH_USE_OTG2
-	if (&USBHD1 == usbh) {
+	if (&USBHD1 == usbh)
 #endif
+	{
 		/* OTG FS clock enable and reset.*/
 		rccEnableOTG_FS(FALSE);
 		rccResetOTG_FS();
@@ -1351,27 +1487,25 @@ static void _usbh_start(USBHDriver *usbh) {
 
 		/* Enables IRQ vector.*/
 		nvicEnableVector(STM32_OTG1_NUMBER, STM32_USB_OTG1_IRQ_PRIORITY);
-#if STM32_USBH_USE_OTG2
 	}
 #endif
-#endif
 
 #if STM32_USBH_USE_OTG2
 #if STM32_USBH_USE_OTG1
-	if (&USBHD2 == usbh) {
+	if (&USBHD2 == usbh)
 #endif
+	{
 		/* OTG HS clock enable and reset.*/
-		rccEnableOTG_HS(FALSE);
+		rccEnableOTG_HS(TRUE); // Enable HS clock when cpu is in sleep mode
+		rccDisableOTG_HSULPI(TRUE); // Disable HS ULPI clock when cpu is in sleep mode
 		rccResetOTG_HS();
 
 		otgp->GINTMSK = 0;
 
 		/* Enables IRQ vector.*/
 		nvicEnableVector(STM32_OTG2_NUMBER, STM32_USB_OTG2_IRQ_PRIORITY);
-#if STM32_USBH_USE_OTG1
 	}
 #endif
-#endif
 
 	otgp->GUSBCFG = GUSBCFG_PHYSEL | GUSBCFG_TRDT(5);
 
@@ -1386,12 +1520,20 @@ static void _usbh_start(USBHDriver *usbh) {
 	otgp->PCGCCTL = 0;
 
 	/* Internal FS PHY activation.*/
+#if STM32_OTG_STEPPING == 1
 #if defined(BOARD_OTG_NOVBUSSENS)
 	otgp->GCCFG = GCCFG_NOVBUSSENS | GCCFG_PWRDWN;
 #else
 	otgp->GCCFG = GCCFG_PWRDWN;
 #endif
+#elif STM32_OTG_STEPPING == 2
+#if defined(BOARD_OTG_NOVBUSSENS)
+	otgp->GCCFG = GCCFG_PWRDWN;
+#else
+	otgp->GCCFG = (GCCFG_VBDEN | GCCFG_PWRDWN);
+#endif
 
+#endif
 	/* 48MHz 1.1 PHY.*/
 	otgp->HCFG = HCFG_FSLSS | HCFG_FSLSPCS_48;
 
@@ -1402,40 +1544,11 @@ static void _usbh_start(USBHDriver *usbh) {
 
 	otgp->HPRT |= HPRT_PPWR;
 
-	/* without this delay, the FIFO sizes are set INcorrectly */
-	osalThreadSleepS(MS2ST(200));
-
-#define HNPTXFSIZ						DIEPTXF0
-#if STM32_USBH_USE_OTG1
-#if STM32_USBH_USE_OTG2
-	if (&USBHD1 == usbh) {
-#endif
-		otgp->GRXFSIZ = GRXFSIZ_RXFD(STM32_OTG1_RXFIFO_SIZE / 4);
-		otgp->HNPTXFSIZ = HPTXFSIZ_PTXSA((STM32_OTG1_RXFIFO_SIZE / 4)) | HPTXFSIZ_PTXFD(STM32_OTG1_NPTXFIFO_SIZE / 4);
-		otgp->HPTXFSIZ = HPTXFSIZ_PTXSA((STM32_OTG1_RXFIFO_SIZE / 4) + (STM32_OTG1_NPTXFIFO_SIZE / 4)) | HPTXFSIZ_PTXFD(STM32_OTG1_PTXFIFO_SIZE / 4);
-#if STM32_USBH_USE_OTG2
-	}
-#endif
-#endif
-#if STM32_USBH_USE_OTG2
-#if STM32_USBH_USE_OTG1
-	if (&USBHD2 == usbh) {
-#endif
-		otgp->GRXFSIZ = GRXFSIZ_RXFD(STM32_OTG2_RXFIFO_SIZE / 4);
-		otgp->HNPTXFSIZ = HPTXFSIZ_PTXSA((STM32_OTG2_RXFIFO_SIZE / 4)) | HPTXFSIZ_PTXFD(STM32_OTG2_NPTXFIFO_SIZE / 4);
-		otgp->HPTXFSIZ = HPTXFSIZ_PTXSA((STM32_OTG2_RXFIFO_SIZE / 4) + (STM32_OTG2_NPTXFIFO_SIZE / 4)) | HPTXFSIZ_PTXFD(STM32_OTG2_PTXFIFO_SIZE / 4);
-#if STM32_USBH_USE_OTG1
-	}
-#endif
-#endif
-
 	otg_txfifo_flush(usbh, 0x10);
 	otg_rxfifo_flush(usbh);
 
 	otgp->GINTSTS = 0xffffffff;
-	otgp->GINTMSK = GINTMSK_DISCM /*| GINTMSK_PTXFEM*/ | GINTMSK_HCM | GINTMSK_HPRTM
-					/*| GINTMSK_IPXFRM | GINTMSK_NPTXFEM*/ | GINTMSK_RXFLVLM
-					/*| GINTMSK_SOFM */ | GINTMSK_MMISM;
+	otgp->GINTMSK = GINTMSK_DISCM | GINTMSK_HPRTM | GINTMSK_MMISM;
 
 	usbh->rootport.lld_status = USBH_PORTSTATUS_POWER;
 	usbh->rootport.lld_c_status = 0;
@@ -1450,7 +1563,7 @@ void usbh_lld_start(USBHDriver *usbh) {
 }
 
 /*===========================================================================*/
-/* Root Hub request handler.   	                                     		 */
+/* Root Hub request handler.                                                 */
 /*===========================================================================*/
 usbh_urbstatus_t usbh_lld_root_hub_request(USBHDriver *usbh, uint8_t bmRequestType, uint8_t bRequest,
 		uint16_t wvalue, uint16_t windex, uint16_t wlength, uint8_t *buf) {
@@ -1469,18 +1582,18 @@ usbh_urbstatus_t usbh_lld_root_hub_request(USBHDriver *usbh, uint8_t bmRequestTy
 		break;
 
 	case ClearPortFeature:
-		chDbgAssert(windex == 1, "invalid windex");
+		osalDbgAssert(windex == 1, "invalid windex");
 
 		osalSysLock();
 		switch (wvalue) {
 		case USBH_PORT_FEAT_ENABLE:
 		case USBH_PORT_FEAT_SUSPEND:
 		case USBH_PORT_FEAT_POWER:
-			chDbgAssert(0, "unimplemented");	/* TODO */
+			osalDbgAssert(0, "unimplemented");	/* TODO */
 			break;
 
 		case USBH_PORT_FEAT_INDICATOR:
-			chDbgAssert(0, "unsupported");
+			osalDbgAssert(0, "unsupported");
 			break;
 
 		case USBH_PORT_FEAT_C_CONNECTION:
@@ -1500,30 +1613,18 @@ usbh_urbstatus_t usbh_lld_root_hub_request(USBHDriver *usbh, uint8_t bmRequestTy
 			break;
 
 		case USBH_PORT_FEAT_C_OVERCURRENT:
-			usbh->rootport.lld_c_status &= USBH_PORTSTATUS_C_OVERCURRENT;
+			usbh->rootport.lld_c_status &= ~USBH_PORTSTATUS_C_OVERCURRENT;
 			break;
 
 		default:
 			osalDbgAssert(0, "invalid wvalue");
 			break;
 		}
-		osalOsRescheduleS();
 		osalSysUnlock();
 		break;
 
 	case GetHubDescriptor:
-		/*dev_dbg(hsotg->dev, "GetHubDescriptor\n");
-		hub_desc = (struct usb_hub_descriptor *)buf;
-		hub_desc->bDescLength = 9;
-		hub_desc->bDescriptorType = USB_DT_HUB;
-		hub_desc->bNbrPorts = 1;
-		hub_desc->wHubCharacteristics =
-			cpu_to_le16(HUB_CHAR_COMMON_LPSM |
-					HUB_CHAR_INDV_PORT_OCPM);
-		hub_desc->bPwrOn2PwrGood = 1;
-		hub_desc->bHubContrCurrent = 0;
-		hub_desc->u.hs.DeviceRemovable[0] = 0;
-		hub_desc->u.hs.DeviceRemovable[1] = 0xff;*/
+		osalDbgAssert(0, "unsupported");
 		break;
 
 	case GetHubStatus:
@@ -1532,26 +1633,25 @@ usbh_urbstatus_t usbh_lld_root_hub_request(USBHDriver *usbh, uint8_t bmRequestTy
 		break;
 
 	case GetPortStatus:
-		chDbgAssert(windex == 1, "invalid windex");
+		osalDbgAssert(windex == 1, "invalid windex");
 		osalDbgCheck(wlength >= 4);
 		osalSysLock();
 		*(uint32_t *)buf = usbh->rootport.lld_status | (usbh->rootport.lld_c_status << 16);
-		osalOsRescheduleS();
 		osalSysUnlock();
 		break;
 
 	case SetHubFeature:
-		chDbgAssert(0, "unsupported");
+		osalDbgAssert(0, "unsupported");
 		break;
 
 	case SetPortFeature:
-		chDbgAssert(windex == 1, "invalid windex");
+		osalDbgAssert(windex == 1, "invalid windex");
 
 		switch (wvalue) {
 		case USBH_PORT_FEAT_TEST:
 		case USBH_PORT_FEAT_SUSPEND:
 		case USBH_PORT_FEAT_POWER:
-			chDbgAssert(0, "unimplemented");	/* TODO */
+			osalDbgAssert(0, "unimplemented");	/* TODO */
 			break;
 
 		case USBH_PORT_FEAT_RESET: {
@@ -1560,18 +1660,35 @@ usbh_urbstatus_t usbh_lld_root_hub_request(USBHDriver *usbh, uint8_t bmRequestTy
 			uint32_t hprt;
 			otg->PCGCCTL = 0;
 			hprt = otg->HPRT;
+			if (hprt & HPRT_PENA) {
+				/* This can occur when the OTG core doesn't generate traffic
+				 * despite reporting a successful por enable. */
+				uerr("Detected enabled port; resetting OTG core");
+				otg->GAHBCFG = 0;
+				osalThreadSleepS(OSAL_MS2I(20));
+				_usbh_start(usbh);				/* this effectively resets the core */
+				osalThreadSleepS(OSAL_MS2I(100));	/* during this delay, the core generates connect ISR */
+				uinfo("OTG reset ended");
+				if (otg->HPRT & HPRT_PCSTS) {
+					/* if the device is still connected, don't report a C_CONNECTION flag, which would cause
+					 * the upper layer to abort enumeration */
+					uinfo("Clear connection change flag");
+					usbh->rootport.lld_c_status &= ~USBH_PORTSTATUS_C_CONNECTION;
+				}
+			}
 			/* note: writing PENA = 1 actually disables the port */
-			hprt &= ~(HPRT_PSUSP | HPRT_PENA | HPRT_PCDET | HPRT_PENCHNG | HPRT_POCCHNG );
+			hprt &= ~(HPRT_PSUSP | HPRT_PENA | HPRT_PCDET | HPRT_PENCHNG | HPRT_POCCHNG);
+			while ((otg->GRSTCTL & GRSTCTL_AHBIDL) == 0);
 			otg->HPRT = hprt | HPRT_PRST;
-			osalThreadSleepS(MS2ST(60));
+			osalThreadSleepS(OSAL_MS2I(15));
 			otg->HPRT = hprt;
+			osalThreadSleepS(OSAL_MS2I(10));
 			usbh->rootport.lld_c_status |= USBH_PORTSTATUS_C_RESET;
-			osalOsRescheduleS();
 			osalSysUnlock();
 		} 	break;
 
 		case USBH_PORT_FEAT_INDICATOR:
-			chDbgAssert(0, "unsupported");
+			osalDbgAssert(0, "unsupported");
 			break;
 
 		default:
@@ -1589,16 +1706,7 @@ usbh_urbstatus_t usbh_lld_root_hub_request(USBHDriver *usbh, uint8_t bmRequestTy
 }
 
 uint8_t usbh_lld_roothub_get_statuschange_bitmap(USBHDriver *usbh) {
-	osalSysLock();
-	if (usbh->rootport.lld_c_status) {
-		osalOsRescheduleS();
-		osalSysUnlock();
-		return 1 << 1;
-	}
-	osalOsRescheduleS();
-	osalSysUnlock();
-	return 0;
+	return usbh->rootport.lld_c_status ? (1 << 1) : 0;
 }
 
-
 #endif
diff --git a/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.h b/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.h
index e8df749..fd7f4e0 100644
--- a/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.h
+++ b/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.h
@@ -1,6 +1,6 @@
 /*
-    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
-              Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail)
+    ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio
+              Copyright (C) 2015..2017 Diego Ismirlian, (dismirlian (at) google's mail)
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -15,8 +15,8 @@
     limitations under the License.
 */
 
-#ifndef USBH_LLD_H_
-#define USBH_LLD_H_
+#ifndef HAL_USBH_LLD_H
+#define HAL_USBH_LLD_H
 
 #include "hal.h"
 
@@ -63,6 +63,8 @@ typedef struct stm32_hc_management {
 
 #define _usbhdriver_ll_data											\
 	stm32_otg_t *otg;												\
+	/* low-speed port reset bug */									\
+	bool check_ls_activity;											\
 	/* channels */													\
 	uint8_t channels_number;										\
 	stm32_hc_management_t channels[STM32_OTG2_CHANNELS_NUMBER];		\
@@ -127,27 +129,37 @@ typedef struct stm32_hc_management {
 				"use USBH_DEFINE_BUFFER() to declare the IO buffers"); 	\
 		} while (0)
 
-
-
 void usbh_lld_init(void);
 void usbh_lld_start(USBHDriver *usbh);
 void usbh_lld_ep_object_init(usbh_ep_t *ep);
 void usbh_lld_ep_open(usbh_ep_t *ep);
 void usbh_lld_ep_close(usbh_ep_t *ep);
+bool usbh_lld_ep_reset(usbh_ep_t *ep);
 void usbh_lld_urb_submit(usbh_urb_t *urb);
 bool usbh_lld_urb_abort(usbh_urb_t *urb, usbh_urbstatus_t status);
 usbh_urbstatus_t usbh_lld_root_hub_request(USBHDriver *usbh, uint8_t bmRequestType, uint8_t bRequest,
 		uint16_t wvalue, uint16_t windex, uint16_t wlength, uint8_t *buf);
 uint8_t usbh_lld_roothub_get_statuschange_bitmap(USBHDriver *usbh);
 
-#define usbh_lld_epreset(ep) do {(ep)->dt_mask = HCTSIZ_DPID_DATA0;} while (0);
-
 #ifdef __IAR_SYSTEMS_ICC__
-#define USBH_LLD_DEFINE_BUFFER(type, name) type name
+#define USBH_LLD_DEFINE_BUFFER(var) _Pragma("data_alignment=4") var
+#define USBH_LLD_DECLARE_STRUCT_MEMBER_H1(x, y) x ## y
+#define USBH_LLD_DECLARE_STRUCT_MEMBER_H2(x, y) USBH_LLD_DECLARE_STRUCT_MEMBER_H1(x, y)
+#define USBH_LLD_DECLARE_STRUCT_MEMBER(member)  unsigned int USBH_LLD_DECLARE_STRUCT_MEMBER_H2(dummy_align_, __COUNTER__); member
 #else
-#define USBH_LLD_DEFINE_BUFFER(type, name) type name __attribute__((aligned(4)))
+#define USBH_LLD_DEFINE_BUFFER(var) var __attribute__((aligned(4)))
+#define USBH_LLD_DECLARE_STRUCT_MEMBER(member) member __attribute__((aligned(4)))
+#endif
+
+
+#if STM32_USBH_USE_OTG1
+extern USBHDriver USBHD1;
+#endif
+
+#if STM32_USBH_USE_OTG2
+extern USBHDriver USBHD2;
 #endif
 
 #endif
 
-#endif /* USBH_LLD_H_ */
+#endif /* HAL_USBH_LLD_H */
diff --git a/os/hal/ports/STM32/STM32F0xx/platform.mk b/os/hal/ports/STM32/STM32F0xx/platform.mk
index 377acdf..0102162 100644
--- a/os/hal/ports/STM32/STM32F0xx/platform.mk
+++ b/os/hal/ports/STM32/STM32F0xx/platform.mk
@@ -2,7 +2,7 @@ include ${CHIBIOS}/os/hal/ports/STM32/STM32F0xx/platform.mk
 
 PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \
                ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \
-               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
 
 PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \
                ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \
diff --git a/os/hal/ports/STM32/STM32F3xx/platform.mk b/os/hal/ports/STM32/STM32F3xx/platform.mk
index 92f033c..910fb1f 100644
--- a/os/hal/ports/STM32/STM32F3xx/platform.mk
+++ b/os/hal/ports/STM32/STM32F3xx/platform.mk
@@ -4,7 +4,9 @@ PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \
                ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c \
                ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \
                ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/COMPv1/hal_comp_lld.c \
 
 PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \
                ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/COMPv1 \
                ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD
diff --git a/os/hal/ports/STM32/STM32F7xx/platform.mk b/os/hal/ports/STM32/STM32F7xx/platform.mk
new file mode 100644
index 0000000..2f9392f
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F7xx/platform.mk
@@ -0,0 +1,9 @@
+include ${CHIBIOS}/os/hal/ports/STM32/STM32F7xx/platform.mk
+
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \
+               ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc_sdram.c
+
+PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1 \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD
diff --git a/os/hal/ports/STM32/STM32L4xx/platform.mk b/os/hal/ports/STM32/STM32L4xx/platform.mk
new file mode 100644
index 0000000..b9bbfea
--- /dev/null
+++ b/os/hal/ports/STM32/STM32L4xx/platform.mk
@@ -0,0 +1,21 @@
+include ${CHIBIOS}/os/hal/ports/STM32/STM32L4xx/platform.mk

+

+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \

+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c \

+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c \

+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c \

+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \

+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c \

+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c \

+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \

+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \

+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c \

+               ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc_sdram.c

+

+PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \

+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/DMA2Dv1 \

+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1 \

+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/LTDCv1 \

+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \

+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1 \

+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD

diff --git a/os/hal/ports/TIVA/LLD/ADC/driver.mk b/os/hal/ports/TIVA/LLD/ADC/driver.mk
new file mode 100644
index 0000000..5a1c80b
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/ADC/driver.mk
@@ -0,0 +1,9 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/ADC/hal_adc_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/ADC/hal_adc_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/ADC
diff --git a/os/hal/ports/TIVA/LLD/ADC/hal_adc_lld.c b/os/hal/ports/TIVA/LLD/ADC/hal_adc_lld.c
new file mode 100644
index 0000000..6c1be30
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/ADC/hal_adc_lld.c
@@ -0,0 +1,351 @@
+/*
+    Copyright (C) 2014..2017 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    hal_adc_lld.c
+ * @brief   PLATFORM ADC subsystem low level driver source.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#include "hal.h"
+
+#if (HAL_USE_ADC == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief   ADC0 driver identifier.*/
+#if TIVA_ADC_USE_ADC0 || defined(__DOXYGEN__)
+ADCDriver ADCD1;
+#endif
+
+/** @brief   ADC1 driver identifier.*/
+#if TIVA_ADC_USE_ADC1 || defined(__DOXYGEN__)
+ADCDriver ADCD2;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Common IRQ handler.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ */
+static void serve_interrupt(ADCDriver *adcp)
+{
+  tiva_udma_table_entry_t *pri = &udmaControlTable.primary[adcp->dmanr];
+  tiva_udma_table_entry_t *alt = &udmaControlTable.alternate[adcp->dmanr];
+
+  if ((pri->chctl & UDMA_CHCTL_XFERMODE_M) == UDMA_CHCTL_XFERMODE_STOP) {
+    /* Primary is used only for circular transfers */
+    if (adcp->grpp->circular) {
+      if (adcp->depth > 1) {
+        _adc_isr_half_code(adcp);
+      }
+
+      /* Reconfigure DMA for new lower half transfer */
+      pri->chctl = adcp->prictl;
+    }
+  }
+
+  if ((alt->chctl & UDMA_CHCTL_XFERMODE_M) == UDMA_CHCTL_XFERMODE_STOP) {
+    /* Alternate is used for both linear and circular transfers */
+    _adc_isr_full_code(adcp);
+
+    if (adcp->grpp->circular) {
+      /* Reconfigure DMA for new upper half transfer */
+      alt->chctl = adcp->altctl;
+    }
+  }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if TIVA_ADC_USE_ADC0
+/**
+ * @brief   ADC0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_ADC0_SEQ0_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  serve_interrupt(&ADCD1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_ADC_USE_ADC1
+/**
+ * @brief   ADC1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_ADC1_SEQ0_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  serve_interrupt(&ADCD2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level ADC driver initialization.
+ *
+ * @notapi
+ */
+void adc_lld_init(void)
+{
+#if TIVA_ADC_USE_ADC0
+  /* Driver initialization.*/
+  adcObjectInit(&ADCD1);
+  ADCD1.adc = ADC0_BASE;
+  ADCD1.dmanr = TIVA_ADC_ADC0_SS0_UDMA_CHANNEL;
+  ADCD1.chnmap = TIVA_ADC_ADC0_SS0_UDMA_MAPPING;
+#endif
+
+#if TIVA_ADC_USE_ADC1
+  /* Driver initialization.*/
+  adcObjectInit(&ADCD2);
+  ADCD2.adc = ADC1_BASE;
+  ADCD2.dmanr = TIVA_ADC_ADC1_SS0_UDMA_CHANNEL;
+  ADCD2.chnmap = TIVA_ADC_ADC1_SS0_UDMA_MAPPING;
+#endif
+}
+
+/**
+ * @brief   Configures and activates the ADC peripheral.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start(ADCDriver *adcp)
+{
+  if (adcp->state == ADC_STOP) {
+    /* Enables the peripheral.*/
+#if TIVA_ADC_USE_ADC0
+    if (&ADCD1 == adcp) {
+      bool b;
+      b = udmaChannelAllocate(adcp->dmanr);
+      osalDbgAssert(!b, "channel already allocated");
+
+      HWREG(SYSCTL_RCGCADC) |= (1 << 0);
+
+      while (!(HWREG(SYSCTL_PRADC) & (1 << 0)))
+        ;
+
+      /* Only sequencer 0 is supported */
+      nvicEnableVector(TIVA_ADC0_SEQ0_NUMBER, TIVA_ADC0_SEQ0_PRIORITY);
+    }
+#endif
+
+#if TIVA_ADC_USE_ADC1
+    if (&ADCD2 == adcp) {
+      bool b;
+      b = udmaChannelAllocate(adcp->dmanr);
+      osalDbgAssert(!b, "channel already allocated");
+
+      HWREG(SYSCTL_RCGCADC) |= (1 << 1);
+
+      while (!(HWREG(SYSCTL_PRADC) & (1 << 1)))
+        ;
+
+      /* Only sequencer 0 is supported */
+      nvicEnableVector(TIVA_ADC1_SEQ0_NUMBER, TIVA_ADC1_SEQ0_PRIORITY);
+    }
+#endif
+
+    HWREG(UDMA_CHMAP0 + (adcp->dmanr / 8) * 4) |= (adcp->chnmap << (adcp->dmanr % 8));
+  }
+}
+
+/**
+ * @brief   Deactivates the ADC peripheral.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop(ADCDriver *adcp)
+{
+  if (adcp->state == ADC_READY) {
+    /* Resets the peripheral.*/
+
+    udmaChannelRelease(adcp->dmanr);
+
+    /* Disables the peripheral.*/
+#if TIVA_ADC_USE_ADC0
+    if (&ADCD1 == adcp) {
+      nvicDisableVector(TIVA_ADC0_SEQ0_NUMBER);
+    }
+#endif
+
+#if TIVA_ADC_USE_ADC1
+    if (&ADCD2 == adcp) {
+      nvicDisableVector(TIVA_ADC1_SEQ0_NUMBER);
+    }
+#endif
+  }
+}
+
+/**
+ * @brief   Starts an ADC conversion.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start_conversion(ADCDriver *adcp)
+{
+  uint32_t adc = adcp->adc;
+  tiva_udma_table_entry_t *primary = &udmaControlTable.primary[adcp->dmanr];
+  tiva_udma_table_entry_t *alternate = &udmaControlTable.alternate[adcp->dmanr];
+
+  /* Disable sample sequencer 0 */
+  HWREG(adc + ADC_O_ACTSS) &= (1 << 0);
+
+  /* Configure the sample sequencer 0 trigger */
+  HWREG(adc + ADC_O_EMUX) = adcp->grpp->emux & 0xff;
+
+  /* If pwm is used as trigger, select in which block the pwm generator is
+     located */
+  if (adcp->grpp->emux >= 6 && adcp->grpp->emux <= 9) {
+    HWREG(adc + ADC_O_TSSEL) = 0;
+  }
+
+  /* For each sample in the sample sequencer, select the input source */
+  HWREG(adc + ADC_O_SSMUX0) = adcp->grpp->ssmux;
+
+  /* Configure the sample control bits */
+  HWREG(adc + ADC_O_SSCTL0) = adcp->grpp->ssctl | 0x44444444; /* Enforce IEn bits */
+
+  /* Alternate source endpoint is the same for all transfers */
+  alternate->srcendp = (void *)(adcp->adc + ADC_O_SSFIFO0);
+
+  /* Configure DMA */
+  if ((adcp->grpp->circular) && (adcp->depth > 1)) {
+    /* Configure DMA in ping-pong mode.
+       Ping (1st half) is configured in the primary control structure.
+       Pong (2nd half) is configured in the alternate control structure. */
+
+    uint32_t ctl;
+
+    /* configure the primary source endpoint */
+    primary->srcendp = (void *)(adcp->adc + ADC_O_SSFIFO0);
+
+    /* sample buffer is split in half, the upper half is used here */
+    primary->dstendp = (void *)(adcp->samples +
+                               (adcp->grpp->num_channels * adcp->depth / 2) - 1);
+    /* the lower half is used here */
+    alternate->dstendp = (void *)(adcp->samples +
+                                 (adcp->grpp->num_channels * adcp->depth) - 1);
+
+    ctl = UDMA_CHCTL_DSTSIZE_32 | UDMA_CHCTL_DSTINC_32 |
+          UDMA_CHCTL_SRCSIZE_32 | UDMA_CHCTL_SRCINC_NONE |
+          UDMA_CHCTL_ARBSIZE_1 |
+          UDMA_CHCTL_XFERSIZE(adcp->grpp->num_channels * adcp->depth / 2) |
+          UDMA_CHCTL_XFERMODE_PINGPONG;
+
+    adcp->prictl = ctl;
+    adcp->altctl = ctl;
+
+    dmaChannelPrimary(adcp->dmanr);
+  }
+  else {
+    /* Configure the DMA in basic mode.
+       This is used for both circular buffers with a depth of 1 and linear
+       buffers.*/
+    alternate->dstendp = (void *)(adcp->samples +
+                                 (adcp->grpp->num_channels * adcp->depth) - 1);
+    adcp->prictl = UDMA_CHCTL_XFERMODE_STOP;
+    adcp->altctl = UDMA_CHCTL_DSTSIZE_32 | UDMA_CHCTL_DSTINC_32 |
+                   UDMA_CHCTL_SRCSIZE_32 | UDMA_CHCTL_SRCINC_NONE |
+                   UDMA_CHCTL_ARBSIZE_1 |
+                   UDMA_CHCTL_XFERSIZE(adcp->grpp->num_channels * adcp->depth) |
+                   UDMA_CHCTL_XFERMODE_BASIC;
+
+    dmaChannelAlternate(adcp->dmanr);
+  }
+
+  /* Configure primary and alternate channel control fields */
+  primary->chctl = adcp->prictl;
+  alternate->chctl = adcp->altctl;
+
+  /* Configure DMA channel */
+  dmaChannelBurstOnly(adcp->dmanr);
+  dmaChannelPriorityDefault(adcp->dmanr);
+  dmaChannelEnableRequest(adcp->dmanr);
+
+  /* Enable DMA channel */
+  dmaChannelEnable(adcp->dmanr);
+
+  /* Enable the sample sequencer */
+  HWREG(adc + ADC_O_ACTSS) |= (1 << 0);
+
+  /* Enable DMA on the sample sequencer, is this for 129x only?*/
+  //HWREG(adc + ADC_O_ACTSS) |= (1 << 8);
+
+  /* Start conversion if configured for CPU trigger */
+  if ((adcp->grpp->emux & 0xff) == 0) {
+    HWREG(adc + ADC_O_PSSI) = ADC_PSSI_SS0;
+  }
+}
+
+/**
+ * @brief   Stops an ongoing conversion.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop_conversion(ADCDriver *adcp)
+{
+  uint32_t adc = adcp->adc;
+
+  /* Stop ongoing DMA transfer */
+  dmaChannelDisable(adcp->dmanr);
+
+  /* Stop ongoing ADC conversion by disabling the active sample sequencer */
+  HWREG(adc + ADC_O_ACTSS) &= ~(1 << 0);
+}
+
+#endif /* HAL_USE_ADC == TRUE */
+
+/** @} */
diff --git a/os/hal/ports/TIVA/LLD/ADC/hal_adc_lld.h b/os/hal/ports/TIVA/LLD/ADC/hal_adc_lld.h
new file mode 100644
index 0000000..81916b8
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/ADC/hal_adc_lld.h
@@ -0,0 +1,230 @@
+/*
+    Copyright (C) 2014..2017 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    hal_adc_lld.h
+ * @brief   PLATFORM ADC subsystem low level driver header.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#ifndef HAL_ADC_LLD_H
+#define HAL_ADC_LLD_H
+
+#if (HAL_USE_ADC == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    PLATFORM configuration options
+ * @{
+ */
+/**
+ * @brief   ADC1 driver enable switch.
+ * @details If set to @p TRUE the support for ADC1 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(PLATFORM_ADC_USE_ADC1) || defined(__DOXYGEN__)
+#define PLATFORM_ADC_USE_ADC1                  FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if !defined(TIVA_UDMA_REQUIRED)
+#define TIVA_UDMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   ADC sample data type.
+ */
+typedef uint32_t adcsample_t;
+
+/**
+ * @brief   Channels number in a conversion group.
+ */
+typedef uint16_t adc_channels_num_t;
+
+/**
+ * @brief   Possible ADC failure causes.
+ * @note    Error codes are architecture dependent and should not relied
+ *          upon.
+ */
+typedef enum {
+  ADC_ERR_DMAFAILURE = 0,                   /**< DMA operations failure.    */
+  ADC_ERR_OVERFLOW = 1,                     /**< ADC overflow condition.    */
+  ADC_ERR_AWD = 2                           /**< Analog watchdog triggered. */
+} adcerror_t;
+
+/**
+ * @brief   Type of a structure representing an ADC driver.
+ */
+typedef struct ADCDriver ADCDriver;
+
+/**
+ * @brief   ADC notification callback type.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object triggering the
+ *                      callback
+ * @param[in] buffer    pointer to the most recent samples data
+ * @param[in] n         number of buffer rows available starting from @p buffer
+ */
+typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
+
+/**
+ * @brief   ADC error callback type.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object triggering the
+ *                      callback
+ * @param[in] err       ADC error code
+ */
+typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
+
+/**
+ * @brief   Conversion group configuration structure.
+ * @details This implementation-dependent structure describes a conversion
+ *          operation.
+ * @note    The use of this configuration structure requires knowledge of
+ *          PLATFORM ADC cell registers interface, please refer to the PLATFORM
+ *          reference manual for details.
+ */
+typedef struct {
+  /**
+   * @brief   Enables the circular buffer mode for the group.
+   */
+  bool                      circular;
+  /**
+   * @brief   Number of the analog channels belonging to the conversion group.
+   */
+  adc_channels_num_t        num_channels;
+  /**
+   * @brief   Callback function associated to the group or @p NULL.
+   */
+  adccallback_t             end_cb;
+  /**
+   * @brief   Error callback or @p NULL.
+   */
+  adcerrorcallback_t        error_cb;
+  /* End of the mandatory fields.*/
+  uint32_t                  emux;
+  uint32_t                  ssmux;
+  uint32_t                  ssctl;
+} ADCConversionGroup;
+
+/**
+ * @brief   Driver configuration structure.
+ * @note    It could be empty on some architectures.
+ */
+typedef struct {
+  uint32_t                  dummy;
+} ADCConfig;
+
+/**
+ * @brief   Structure representing an ADC driver.
+ */
+struct ADCDriver {
+  /**
+   * @brief Driver state.
+   */
+  adcstate_t                state;
+  /**
+   * @brief Current configuration data.
+   */
+  const ADCConfig           *config;
+  /**
+   * @brief Current samples buffer pointer or @p NULL.
+   */
+  adcsample_t               *samples;
+  /**
+   * @brief Current samples buffer depth or @p 0.
+   */
+  size_t                    depth;
+  /**
+   * @brief Current conversion group pointer or @p NULL.
+   */
+  const ADCConversionGroup  *grpp;
+#if (ADC_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+  /**
+   * @brief Waiting thread.
+   */
+  thread_reference_t        thread;
+#endif
+#if (ADC_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__)
+  /**
+   * @brief Mutex protecting the peripheral.
+   */
+  mutex_t                   mutex;
+#endif
+#if defined(ADC_DRIVER_EXT_FIELDS)
+  ADC_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Pointer to the ADC registers block.
+   */
+  uint32_t                  adc;
+  uint8_t                   dmanr;
+  uint8_t                   chnmap;
+  uint32_t                  prictl;
+  uint32_t                  altctl;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if TIVA_ADC_USE_ADC0 && !defined(__DOXYGEN__)
+extern ADCDriver ADCD1;
+#endif
+
+#if TIVA_ADC_USE_ADC1 && !defined(__DOXYGEN__)
+extern ADCDriver ADCD2;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void adc_lld_init(void);
+  void adc_lld_start(ADCDriver *adcp);
+  void adc_lld_stop(ADCDriver *adcp);
+  void adc_lld_start_conversion(ADCDriver *adcp);
+  void adc_lld_stop_conversion(ADCDriver *adcp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_ADC == TRUE */
+
+#endif /* HAL_ADC_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/TIVA/LLD/GPIO/driver.mk b/os/hal/ports/TIVA/LLD/GPIO/driver.mk
new file mode 100644
index 0000000..486fe73
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/GPIO/driver.mk
@@ -0,0 +1,9 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPIO
diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c
new file mode 100644
index 0000000..7a222e4
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c
@@ -0,0 +1,1135 @@
+/*
+    Copyright (C) 2014..2017 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    GPIO/hal_pal_lld.c
+ * @brief   TM4C123x/TM4C129x PAL subsystem low level driver.
+ *
+ * @addtogroup PAL
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#if TIVA_HAS_GPIOA || defined(__DOXYGEN__)
+#define GPIOA_BIT       (1 << 0)
+#else
+#define GPIOA_BIT       0
+#endif
+
+#if TIVA_HAS_GPIOB || defined(__DOXYGEN__)
+#define GPIOB_BIT       (1 << 1)
+#else
+#define GPIOB_BIT       0
+#endif
+
+#if TIVA_HAS_GPIOC || defined(__DOXYGEN__)
+#define GPIOC_BIT       (1 << 2)
+#else
+#define GPIOC_BIT       0
+#endif
+
+#if TIVA_HAS_GPIOD || defined(__DOXYGEN__)
+#define GPIOD_BIT       (1 << 3)
+#else
+#define GPIOD_BIT       0
+#endif
+
+#if TIVA_HAS_GPIOE || defined(__DOXYGEN__)
+#define GPIOE_BIT       (1 << 4)
+#else
+#define GPIOE_BIT       0
+#endif
+
+#if TIVA_HAS_GPIOF || defined(__DOXYGEN__)
+#define GPIOF_BIT       (1 << 5)
+#else
+#define GPIOF_BIT       0
+#endif
+
+#if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
+#define GPIOG_BIT       (1 << 6)
+#else
+#define GPIOG_BIT       0
+#endif
+
+#if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
+#define GPIOH_BIT       (1 << 7)
+#else
+#define GPIOH_BIT       0
+#endif
+
+#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
+#define GPIOJ_BIT       (1 << 8)
+#else
+#define GPIOJ_BIT       0
+#endif
+
+#if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
+#define GPIOK_BIT       (1 << 9)
+#else
+#define GPIOK_BIT       0
+#endif
+
+#if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
+#define GPIOL_BIT       (1 << 10)
+#else
+#define GPIOL_BIT       0
+#endif
+
+#if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
+#define GPIOM_BIT       (1 << 11)
+#else
+#define GPIOM_BIT       0
+#endif
+
+#if TIVA_HAS_GPION || defined(__DOXYGEN__)
+#define GPION_BIT       (1 << 12)
+#else
+#define GPION_BIT       0
+#endif
+
+#if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
+#define GPIOP_BIT       (1 << 13)
+#else
+#define GPIOP_BIT       0
+#endif
+
+#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
+#define GPIOQ_BIT       (1 << 14)
+#else
+#define GPIOQ_BIT       0
+#endif
+
+#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
+#define GPIOR_BIT       (1 << 15)
+#else
+#define GPIOR_BIT       0
+#endif
+
+#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
+#define GPIOS_BIT       (1 << 16)
+#else
+#define GPIOS_BIT       0
+#endif
+
+#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
+#define GPIOT_BIT       (1 << 17)
+#else
+#define GPIOT_BIT       0
+#endif
+
+#define RCGCGPIO_MASK   (GPIOA_BIT | GPIOB_BIT | GPIOC_BIT | GPIOD_BIT |      \
+                         GPIOE_BIT | GPIOF_BIT | GPIOG_BIT | GPIOH_BIT |      \
+                         GPIOJ_BIT | GPIOK_BIT | GPIOL_BIT | GPIOM_BIT |      \
+                         GPION_BIT | GPIOP_BIT | GPIOQ_BIT | GPIOR_BIT |      \
+                         GPIOS_BIT | GPIOT_BIT)
+
+#define GPIOHBCTL_MASK  (GPIOA_BIT | GPIOB_BIT | GPIOC_BIT | GPIOD_BIT |      \
+                         GPIOE_BIT | GPIOF_BIT | GPIOG_BIT | GPIOH_BIT |      \
+                         GPIOJ_BIT)
+
+#define GPIOC_JTAG_MASK     (0x0F)
+#define GPIOD_NMI_MASK      (0x80)
+#define GPIOF_NMI_MASK      (0x01)
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Event records for all GPIO channels.
+ */
+palevent_t _pal_events[TIVA_GPIO_PINS];
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Initializes the port with the port configuration.
+ *
+ * @param[in] port      the port identifier
+ * @param[in] config    the port configuration
+ */
+static void gpio_init(ioportid_t port, const tiva_gpio_setup_t *config)
+{
+  HWREG(port + GPIO_O_DATA)  = config->data;
+  HWREG(port + GPIO_O_DIR)   = config->dir;
+  HWREG(port + GPIO_O_AFSEL) = config->afsel;
+  HWREG(port + GPIO_O_DR2R)  = config->dr2r;
+  HWREG(port + GPIO_O_DR4R)  = config->dr4r;
+  HWREG(port + GPIO_O_DR8R)  = config->dr8r;
+  HWREG(port + GPIO_O_ODR)   = config->odr;
+  HWREG(port + GPIO_O_PUR)   = config->pur;
+  HWREG(port + GPIO_O_PDR)   = config->pdr;
+  HWREG(port + GPIO_O_SLR)   = config->slr;
+  HWREG(port + GPIO_O_DEN)   = config->den;
+  HWREG(port + GPIO_O_AMSEL) = config->amsel;
+  HWREG(port + GPIO_O_PCTL)  = config->pctl;
+}
+
+/**
+ * @brief   Unlocks the masked pins of the GPIO peripheral.
+ * @note    This function is only useful for PORTC0-3, PORTD7 and PORTF0.
+ *
+ * @param[in] port      the port identifier
+ * @param[in] mask      the pin mask
+ */
+static void gpio_unlock(ioportid_t port, ioportmask_t mask)
+{
+
+  HWREG(port + GPIO_O_LOCK) = GPIO_LOCK_KEY;
+  HWREG(port + GPIO_O_CR) = mask;
+}
+
+#if PAL_USE_CALLBACKS || PAL_USE_WAIT
+/**
+ * @brief   Enables GPIO IRQ sources.
+ */
+static void gpio_irq_enable(void)
+{
+#if TIVA_HAS_GPIOA
+  nvicEnableVector(TIVA_GPIOA_NUMBER, TIVA_PAL_GPIOA_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOB
+  nvicEnableVector(TIVA_GPIOB_NUMBER, TIVA_PAL_GPIOB_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOC
+  nvicEnableVector(TIVA_GPIOC_NUMBER, TIVA_PAL_GPIOC_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOD
+  nvicEnableVector(TIVA_GPIOD_NUMBER, TIVA_PAL_GPIOD_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOE
+  nvicEnableVector(TIVA_GPIOE_NUMBER, TIVA_PAL_GPIOE_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOF
+  nvicEnableVector(TIVA_GPIOF_NUMBER, TIVA_PAL_GPIOF_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOG
+  nvicEnableVector(TIVA_GPIOG_NUMBER, TIVA_PAL_GPIOG_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOH
+  nvicEnableVector(TIVA_GPIOH_NUMBER, TIVA_PAL_GPIOH_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOJ
+  nvicEnableVector(TIVA_GPIOJ_NUMBER, TIVA_PAL_GPIOJ_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOK
+  nvicEnableVector(TIVA_GPIOK_NUMBER, TIVA_PAL_GPIOK_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOL
+  nvicEnableVector(TIVA_GPIOL_NUMBER, TIVA_PAL_GPIOL_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOM
+  nvicEnableVector(TIVA_GPIOM_NUMBER, TIVA_PAL_GPIOM_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPION
+  nvicEnableVector(TIVA_GPION_NUMBER, TIVA_PAL_GPION_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOP
+  nvicEnableVector(TIVA_GPIOP0_NUMBER, TIVA_PAL_GPIOP0_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP1_NUMBER, TIVA_PAL_GPIOP1_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP2_NUMBER, TIVA_PAL_GPIOP2_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP3_NUMBER, TIVA_PAL_GPIOP3_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP4_NUMBER, TIVA_PAL_GPIOP4_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP5_NUMBER, TIVA_PAL_GPIOP5_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP6_NUMBER, TIVA_PAL_GPIOP6_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP7_NUMBER, TIVA_PAL_GPIOP7_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOQ
+  nvicEnableVector(TIVA_GPIOQ0_NUMBER, TIVA_PAL_GPIOQ0_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ1_NUMBER, TIVA_PAL_GPIOQ1_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ2_NUMBER, TIVA_PAL_GPIOQ2_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ3_NUMBER, TIVA_PAL_GPIOQ3_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ4_NUMBER, TIVA_PAL_GPIOQ4_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ5_NUMBER, TIVA_PAL_GPIOQ5_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ6_NUMBER, TIVA_PAL_GPIOQ6_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ7_NUMBER, TIVA_PAL_GPIOQ7_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOR
+  nvicEnableVector(TIVA_GPIOR_NUMBER, TIVA_PAL_GPIOR_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOS
+  nvicEnableVector(TIVA_GPIOS_NUMBER, TIVA_PAL_GPIOS_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOT
+  nvicEnableVector(TIVA_GPIOT_NUMBER, TIVA_PAL_GPIOT_IRQ_PRIORITY);
+#endif
+}
+#endif
+
+#define gpio_serve_irq(mask, pin, channel) {                                \
+                                                                            \
+  if ((mask) & (1U << (pin))) {                                         \
+    _pal_isr_code(channel);                                                 \
+  }                                                                         \
+}
+
+/**
+ * @brief   Generic interrupt serving code for multiple pins per interrupt
+ *          handler.
+ */
+#define ext_lld_serve_port_interrupt(gpio, start)                             \
+  do {                                                                        \
+    uint32_t mis = HWREG(gpio + GPIO_O_MIS);                                  \
+                                                                              \
+    HWREG(gpio + GPIO_O_ICR) = mis;                                           \
+                                                                              \
+    gpio_serve_irq(mis, 0, start + 0);                                        \
+    gpio_serve_irq(mis, 1, start + 1);                                        \
+    gpio_serve_irq(mis, 2, start + 2);                                        \
+    gpio_serve_irq(mis, 3, start + 3);                                        \
+    gpio_serve_irq(mis, 4, start + 4);                                        \
+    gpio_serve_irq(mis, 5, start + 5);                                        \
+    gpio_serve_irq(mis, 6, start + 6);                                        \
+    gpio_serve_irq(mis, 7, start + 7);                                        \
+  } while (0);
+
+/**
+ * @brief   Generic interrupt serving code for single pin per interrupt
+ *          handler.
+ */
+#define ext_lld_serve_pin_interrupt(gpio, start, pin)                         \
+  do {                                                                        \
+    HWREG(gpio + GPIO_O_ICR) = (1 << pin);                                    \
+    gpio_serve_irq((1 << pin), pin, start)                                    \
+  } while (0);
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if TIVA_HAS_GPIOA || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOA interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOA_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOA, 0);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOB || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOB interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOB_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOB, 8);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOC || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOC interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOC_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOC, 16);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOD || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOD interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOD_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOD, 24);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOE || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOE interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOE_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOE, 32);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOF || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOF interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOF_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOF, 40);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOG interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOG_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOG, 48);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOH interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOH_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOH, 56);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOJ interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOJ_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOJ, 64);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOK interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOK_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOK, 72);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOL interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOL_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOL, 80);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOM interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOM_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOM, 88);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPION || defined(__DOXYGEN__)
+/**
+ * @brief   GPION interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPION_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPION, 96);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOP0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOP0_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOP, 104, 0);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOP1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOP1_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOP, 105, 1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOP2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOP2_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOP, 106, 2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOP3 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOP3_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOP, 107, 3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOP4 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOP4_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOP, 108, 4);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOP5 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOP5_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOP, 109, 5);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOP6 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOP6_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOP, 110, 6);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOP7 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOP7_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOP, 111, 7);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOQ0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOQ0_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOQ, 112, 0);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOQ1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOQ1_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOQ, 113, 1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOQ2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOQ2_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOQ, 114, 2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOQ3 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOQ3_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOQ, 115, 3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOQ4 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOQ4_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOQ, 116, 4);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOQ5 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOQ5_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOQ, 117, 5);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOQ6 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOQ6_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOQ, 118, 6);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOQ7 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOQ7_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOQ, 119, 7);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOR interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOR_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOR, 120);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOS interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOS_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOS, 128);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOT interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOT_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOT, 132);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Tiva I/O ports configuration.
+ * @details Ports A-F (G, H, J, K, L, M, N, P, Q, R, S, T) clocks enabled.
+ *
+ * @param[in] config    the Tiva ports configuration
+ *
+ * @notapi
+ */
+void _pal_lld_init(const PALConfig *config)
+{
+#if PAL_USE_CALLBACKS || PAL_USE_WAIT || defined(__DOXYGEN__)
+  unsigned i;
+
+  for (i = 0; i < TIVA_GPIO_PINS; i++) {
+    _pal_init_event(i);
+  }
+#endif
+
+  /*
+   * Enables all GPIO clocks.
+   */
+  HWREG(SYSCTL_RCGCGPIO) = RCGCGPIO_MASK;
+#if defined(TM4C123x)
+  HWREG(SYSCTL_GPIOHBCTL) = GPIOHBCTL_MASK;
+#endif
+
+  /* Wait until all GPIO modules are ready */
+  while (!((HWREG(SYSCTL_PRGPIO) & RCGCGPIO_MASK) == RCGCGPIO_MASK))
+    ;
+  
+#if TIVA_HAS_GPIOA
+  gpio_init(GPIOA, &config->PAData);
+#endif
+#if TIVA_HAS_GPIOB
+  gpio_init(GPIOB, &config->PBData);
+#endif
+#if TIVA_HAS_GPIOC
+  /* Unlock JTAG pins.*/
+  gpio_unlock(GPIOC, GPIOC_JTAG_MASK);
+  gpio_init(GPIOC, &config->PCData);
+#endif
+#if TIVA_HAS_GPIOD
+  /* Unlock NMI pin.*/
+  gpio_unlock(GPIOD, GPIOD_NMI_MASK);
+  gpio_init(GPIOD, &config->PDData);
+#endif
+#if TIVA_HAS_GPIOE
+  gpio_init(GPIOE, &config->PEData);
+#endif
+#if TIVA_HAS_GPIOF
+  /* Unlock NMI pin.*/
+  gpio_unlock(GPIOF, GPIOF_NMI_MASK);
+  gpio_init(GPIOF, &config->PFData);
+#endif
+#if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
+  gpio_init(GPIOG, &config->PGData);
+#endif
+#if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
+  gpio_init(GPIOH, &config->PHData);
+#endif
+#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
+  gpio_init(GPIOJ, &config->PJData);
+#endif
+#if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
+  gpio_init(GPIOK, &config->PKData);
+#endif
+#if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
+  gpio_init(GPIOL, &config->PLData);
+#endif
+#if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
+  gpio_init(GPIOM, &config->PMData);
+#endif
+#if TIVA_HAS_GPION || defined(__DOXYGEN__)
+  gpio_init(GPION, &config->PNData);
+#endif
+#if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
+  gpio_init(GPIOP, &config->PPData);
+#endif
+#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
+  gpio_init(GPIOQ, &config->PQData);
+#endif
+#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
+  gpio_init(GPIOR, &config->PRData);
+#endif
+#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
+  gpio_init(GPIOS, &config->PSData);
+#endif
+#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
+  gpio_init(GPIOT, &config->PTData);
+#endif
+#if PAL_USE_CALLBACKS || PAL_USE_WAIT
+  gpio_irq_enable();
+#endif
+}
+
+/**
+ * @brief   Pads mode setup.
+ * @details This function programs a pads group belonging to the same port
+ *          with the specified mode.
+ *
+ * @param[in] port      the port identifier
+ * @param[in] mask      the group mask
+ * @param[in] mode      the mode
+ *
+ * @notapi
+ */
+void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, iomode_t mode)
+{
+  uint32_t dir   = (mode & PAL_TIVA_DIR_MASK)   >> 0;
+  uint32_t afsel = (mode & PAL_TIVA_AFSEL_MASK) >> 1;
+  uint32_t dr2r  = (mode & PAL_TIVA_DR2R_MASK)  >> 2;
+  uint32_t dr4r  = (mode & PAL_TIVA_DR4R_MASK)  >> 3;
+  uint32_t dr8r  = (mode & PAL_TIVA_DR8R_MASK)  >> 4;
+  uint32_t odr   = (mode & PAL_TIVA_ODR_MASK)   >> 5;
+  uint32_t pur   = (mode & PAL_TIVA_PUR_MASK)   >> 6;
+  uint32_t pdr   = (mode & PAL_TIVA_PDR_MASK)   >> 7;
+  uint32_t slr   = (mode & PAL_TIVA_SLR_MASK)   >> 8;
+  uint32_t den   = (mode & PAL_TIVA_DEN_MASK)   >> 9;
+  uint32_t amsel = (mode & PAL_TIVA_AMSEL_MASK) >> 10;
+  uint32_t pctl  = (mode & PAL_TIVA_PCTL_MASK)  >> 11;
+  uint32_t bit   = 0;
+
+  while(TRUE) {
+    uint32_t pctl_mask = (7 << (4 * bit));
+    uint32_t bit_mask = (1 << bit);
+
+    if ((mask & 1) != 0) {
+      HWREG(port + GPIO_O_DIR)   = (HWREG(port + GPIO_O_DIR)   & ~bit_mask)  | dir;
+      HWREG(port + GPIO_O_AFSEL) = (HWREG(port + GPIO_O_AFSEL) & ~bit_mask)  | afsel;
+      HWREG(port + GPIO_O_DR2R)  = (HWREG(port + GPIO_O_DR2R)  & ~bit_mask)  | dr2r;
+      HWREG(port + GPIO_O_DR4R)  = (HWREG(port + GPIO_O_DR4R)  & ~bit_mask)  | dr4r;
+      HWREG(port + GPIO_O_DR8R)  = (HWREG(port + GPIO_O_DR8R)  & ~bit_mask)  | dr8r;
+      HWREG(port + GPIO_O_ODR)   = (HWREG(port + GPIO_O_ODR)   & ~bit_mask)  | odr;
+      HWREG(port + GPIO_O_PUR)   = (HWREG(port + GPIO_O_PUR)   & ~bit_mask)  | pur;
+      HWREG(port + GPIO_O_PDR)   = (HWREG(port + GPIO_O_PDR)   & ~bit_mask)  | pdr;
+      HWREG(port + GPIO_O_SLR)   = (HWREG(port + GPIO_O_SLR)   & ~bit_mask)  | slr;
+      HWREG(port + GPIO_O_DEN)   = (HWREG(port + GPIO_O_DEN)   & ~bit_mask)  | den;
+      HWREG(port + GPIO_O_AMSEL) = (HWREG(port + GPIO_O_AMSEL) & ~bit_mask)  | amsel;
+      HWREG(port + GPIO_O_PCTL)  = (HWREG(port + GPIO_O_PCTL)  & ~pctl_mask) | pctl;
+    }
+
+    mask >>= 1;
+    if (!mask) {
+      return;
+    }
+
+    dir   <<= 1;
+    afsel <<= 1;
+    dr2r  <<= 1;
+    dr4r  <<= 1;
+    dr8r  <<= 1;
+    odr   <<= 1;
+    pur   <<= 1;
+    pdr   <<= 1;
+    slr   <<= 1;
+    den   <<= 1;
+    amsel <<= 1;
+    pctl  <<= 4;
+
+    bit++;
+  }
+}
+
+#if PAL_USE_CALLBACKS || PAL_USE_WAIT || defined(__DOXYGEN__)
+/**
+ * @brief   Pad event enable.
+ * @note    Programming an unknown or unsupported mode is silently ignored.
+ *
+ * @param[in] port      port identifier
+ * @param[in] pad       pad number within the port
+ * @param[in] mode      pad event mode
+ *
+ * @notapi
+ */
+void _pal_lld_enablepadevent(ioportid_t port,
+                             iopadid_t pad,
+                             ioeventmode_t mode)
+{
+  //uint8_t portidx;
+  uint32_t padmask;
+
+  //portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 12) & 0x1FU;
+  padmask = (1 << pad);
+
+  /* Disable interrupt before changing edge configuration.*/
+  HWREG(port + GPIO_O_IM) &= ~padmask;
+
+  /* Configure pin to be edge-sensitive.*/
+  HWREG(port + GPIO_O_IS) &= ~(1 << pad);
+
+  /* Configure edges */
+  switch(mode & PAL_EVENT_MODE_EDGES_MASK) {
+  case PAL_EVENT_MODE_BOTH_EDGES:
+    HWREG(port + GPIO_O_IBE) |= padmask;
+    break;
+  case PAL_EVENT_MODE_RISING_EDGE:
+    HWREG(port + GPIO_O_IBE) &= ~padmask;
+    HWREG(port + GPIO_O_IEV) &= ~padmask;
+    break;
+  case PAL_EVENT_MODE_FALLING_EDGE:
+    HWREG(port + GPIO_O_IBE) &= ~padmask;
+    HWREG(port + GPIO_O_IEV) |= padmask;
+    break;
+  default:
+    /* Interrupt is already disabled */
+    break;
+  }
+
+  if (mode & PAL_EVENT_MODE_EDGES_MASK) {
+    /* Enable interrupt for this pad */
+    HWREG(port + GPIO_O_IM) |= padmask;
+  }
+}
+
+/**
+ * @brief   Pad event disable.
+ * @details This function disables previously programmed event callbacks.
+ *
+ * @param[in] port      port identifier
+ * @param[in] pad       pad number within the port
+ *
+ * @notapi
+ */
+void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad)
+{
+  uint8_t portidx;
+  uint8_t eventidx;
+
+  portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 12) & 0x1FU;
+
+  eventidx = portidx * 8 + pad;
+
+  HWREG(port + GPIO_O_IM) &= ~(1 << pad);
+
+#if PAL_USE_CALLBACKS || PAL_USE_WAIT
+  /* Callback cleared and/or thread reset.*/
+  _pal_clear_event(eventidx);
+#endif
+}
+
+/**
+ * @brief   Disables GPIO IRQ sources.
+ */
+void pal_lld_disable_irqs(void)
+{
+#if TIVA_HAS_GPIOA
+  nvicDisableVector(TIVA_GPIOA_NUMBER);
+#endif
+#if TIVA_HAS_GPIOB
+  nvicDisableVector(TIVA_GPIOB_NUMBER);
+#endif
+#if TIVA_HAS_GPIOC
+  nvicDisableVector(TIVA_GPIOC_NUMBER);
+#endif
+#if TIVA_HAS_GPIOD
+  nvicDisableVector(TIVA_GPIOD_NUMBER);
+#endif
+#if TIVA_HAS_GPIOE
+  nvicDisableVector(TIVA_GPIOE_NUMBER);
+#endif
+#if TIVA_HAS_GPIOF
+  nvicDisableVector(TIVA_GPIOF_NUMBER);
+#endif
+#if TIVA_HAS_GPIOG
+  nvicDisableVector(TIVA_GPIOG_NUMBER);
+#endif
+#if TIVA_HAS_GPIOH
+  nvicDisableVector(TIVA_GPIOH_NUMBER);
+#endif
+#if TIVA_HAS_GPIOJ
+  nvicDisableVector(TIVA_GPIOJ_NUMBER);
+#endif
+#if TIVA_HAS_GPIOK
+  nvicDisableVector(TIVA_GPIOK_NUMBER);
+#endif
+#if TIVA_HAS_GPIOL
+  nvicDisableVector(TIVA_GPIOL_NUMBER);
+#endif
+#if TIVA_HAS_GPIOM
+  nvicDisableVector(TIVA_GPIOM_NUMBER);
+#endif
+#if TIVA_HAS_GPION
+  nvicDisableVector(TIVA_GPION_NUMBER);
+#endif
+#if TIVA_HAS_GPIOP
+  nvicDisableVector(TIVA_GPIOP0_NUMBER);
+  nvicDisableVector(TIVA_GPIOP1_NUMBER);
+  nvicDisableVector(TIVA_GPIOP2_NUMBER);
+  nvicDisableVector(TIVA_GPIOP3_NUMBER);
+  nvicDisableVector(TIVA_GPIOP4_NUMBER);
+  nvicDisableVector(TIVA_GPIOP5_NUMBER);
+  nvicDisableVector(TIVA_GPIOP6_NUMBER);
+  nvicDisableVector(TIVA_GPIOP7_NUMBER);
+#endif
+#if TIVA_HAS_GPIOQ
+  nvicDisableVector(TIVA_GPIOQ0_NUMBER);
+  nvicDisableVector(TIVA_GPIOQ1_NUMBER);
+  nvicDisableVector(TIVA_GPIOQ2_NUMBER);
+  nvicDisableVector(TIVA_GPIOQ3_NUMBER);
+  nvicDisableVector(TIVA_GPIOQ4_NUMBER);
+  nvicDisableVector(TIVA_GPIOQ5_NUMBER);
+  nvicDisableVector(TIVA_GPIOQ6_NUMBER);
+  nvicDisableVector(TIVA_GPIOQ7_NUMBER);
+#endif
+#if TIVA_HAS_GPIOR
+  nvicDisableVector(TIVA_GPIOR_NUMBER);
+#endif
+#if TIVA_HAS_GPIOS
+  nvicDisableVector(TIVA_GPIOS_NUMBER);
+#endif
+#if TIVA_HAS_GPIOT
+  nvicDisableVector(TIVA_GPIOT_NUMBER);
+#endif
+}
+#endif /* PAL_USE_CALLBACKS || PAL_USE_WAIT */
+
+#endif /* HAL_USE_PAL */
+
+/**
+ * @}
+ */
diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
new file mode 100644
index 0000000..e884a92
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
@@ -0,0 +1,1141 @@
+/*
+    Copyright (C) 2014..2017 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    GPIO/hal_pal_lld.h
+ * @brief   TM4C123x/TM4C129x PAL subsystem low level driver header.
+ *
+ * @addtogroup PAL
+ * @{
+ */
+
+#ifndef HAL_PAL_LLD_H
+#define HAL_PAL_LLD_H
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Unsupported modes and specific modes                                      */
+/*===========================================================================*/
+
+#undef PAL_MODE_RESET
+#undef PAL_MODE_UNCONNECTED
+#undef PAL_MODE_INPUT
+#undef PAL_MODE_INPUT_PULLUP
+#undef PAL_MODE_INPUT_PULLDOWN
+#undef PAL_MODE_INPUT_ANALOG
+#undef PAL_MODE_OUTPUT_PUSHPULL
+#undef PAL_MODE_OUTPUT_OPENDRAIN
+
+/**
+ * @name    TIVA-specific I/O mode flags
+ * @{
+ */
+#define PAL_TIVA_DIR_MASK           (1 << 0)
+#define PAL_TIVA_DIR_INPUT          (0 << 0)
+#define PAL_TIVA_DIR_OUTPUT         (1 << 0)
+
+#define PAL_TIVA_AFSEL_MASK         (1 << 1)
+#define PAL_TIVA_AFSEL_GPIO         (0 << 1)
+#define PAL_TIVA_AFSEL_ALTERNATE    (1 << 1)
+
+#define PAL_TIVA_DR2R_MASK          (1 << 2)
+#define PAL_TIVA_DR2R_DISABLE       (0 << 2)
+#define PAL_TIVA_DR2R_ENABLE        (1 << 2)
+
+#define PAL_TIVA_DR4R_MASK          (1 << 3)
+#define PAL_TIVA_DR4R_DISABLE       (0 << 3)
+#define PAL_TIVA_DR4R_ENABLE        (1 << 3)
+
+#define PAL_TIVA_DR8R_MASK          (1 << 4)
+#define PAL_TIVA_DR8R_DISABLE       (0 << 4)
+#define PAL_TIVA_DR8R_ENABLE        (1 << 4)
+
+#define PAL_TIVA_ODR_MASK           (1 << 5)
+#define PAL_TIVA_ODR_PUSHPULL       (0 << 5)
+#define PAL_TIVA_ODR_OPENDRAIN      (1 << 5)
+
+#define PAL_TIVA_PUR_MASK           (1 << 6)
+#define PAL_TIVA_PUR_DISABLE        (0 << 6)
+#define PAL_TIVA_PUR_ENABLE         (1 << 6)
+
+#define PAL_TIVA_PDR_MASK           (1 << 7)
+#define PAL_TIVA_PDR_DISABLE        (0 << 7)
+#define PAL_TIVA_PDR_ENABLE         (1 << 7)
+
+#define PAL_TIVA_SLR_MASK           (1 << 8)
+#define PAL_TIVA_SLR_DISABLE        (0 << 8)
+#define PAL_TIVA_SLR_ENABLE         (1 << 8)
+
+#define PAL_TIVA_DEN_MASK           (1 << 9)
+#define PAL_TIVA_DEN_DISABLE        (0 << 9)
+#define PAL_TIVA_DEN_ENABLE         (1 << 9)
+
+#define PAL_TIVA_AMSEL_MASK         (1 << 10)
+#define PAL_TIVA_AMSEL_DISABLE      (0 << 10)
+#define PAL_TIVA_AMSEL_ENABLE       (1 << 10)
+
+#define PAL_TIVA_PCTL_MASK          (7 << 11)
+#define PAL_TIVA_PCTL(n)            ((n) << 11)
+
+/**
+ * @brief   Alternate function.
+ *
+ * @param[in] n         alternate function selector
+ */
+#define PAL_MODE_ALTERNATE(n)       (PAL_TIVA_AFSEL_ALTERNATE |               \
+                                     PAL_TIVA_PCTL(n))
+/** @} */
+
+/**
+ * @name    Standard I/O mode flags
+ * @{
+ */
+/**
+ * @brief   This mode is implemented as input.
+ */
+#define PAL_MODE_RESET                  PAL_MODE_INPUT
+
+/**
+ * @brief   This mode is implemented as input with pull-up.
+ */
+#define PAL_MODE_UNCONNECTED            PAL_MODE_INPUT_PULLUP
+
+/**
+ * @brief   Regular input high-Z pad.
+ */
+#define PAL_MODE_INPUT                  (PAL_TIVA_DEN_ENABLE |                \
+                                         PAL_TIVA_DIR_INPUT)
+
+/**
+ * @brief   Input pad with weak pull up resistor.
+ */
+#define PAL_MODE_INPUT_PULLUP           (PAL_TIVA_DIR_INPUT |                 \
+                                         PAL_TIVA_PUR_ENABLE |                \
+                                         PAL_TIVA_DEN_ENABLE)
+
+/**
+ * @brief   Input pad with weak pull down resistor.
+ */
+#define PAL_MODE_INPUT_PULLDOWN         (PAL_TIVA_DIR_INPUT |                 \
+                                         PAL_TIVA_PDR_ENABLE |                \
+                                         PAL_TIVA_DEN_ENABLE)
+
+/**
+ * @brief   Analog input mode.
+ */
+#define PAL_MODE_INPUT_ANALOG           (PAL_TIVA_DEN_DISABLE |               \
+                                         PAL_TIVA_AMSEL_ENABLE)
+
+/**
+ * @brief   Push-pull output pad.
+ */
+#define PAL_MODE_OUTPUT_PUSHPULL        (PAL_TIVA_DIR_OUTPUT |                \
+                                         PAL_TIVA_DR2R_ENABLE |               \
+                                         PAL_TIVA_ODR_PUSHPULL |              \
+                                         PAL_TIVA_DEN_ENABLE)
+
+/**
+ * @brief   Open-drain output pad.
+ */
+#define PAL_MODE_OUTPUT_OPENDRAIN       (PAL_TIVA_DIR_OUTPUT |                \
+                                         PAL_TIVA_DR2R_ENABLE |               \
+                                         PAL_TIVA_ODR_OPENDRAIN |             \
+                                         PAL_TIVA_DEN_ENABLE)
+/** @} */
+
+/*===========================================================================*/
+/* I/O Ports Types and constants.                                            */
+/*===========================================================================*/
+
+/**
+ * @name    Port related definitions
+ * @{
+ */
+/**
+ * @brief   Width, in bits, of an I/O port.
+ */
+#define PAL_IOPORTS_WIDTH 8
+
+/**
+ * @brief   Whole port mask.
+ * @brief   This macro specifies all the valid bits into a port.
+ */
+#define PAL_WHOLE_PORT ((ioportmask_t)0xFF)
+/** @} */
+
+/**
+ * @name    Line handling macros
+ * @{
+ */
+/**
+ * @brief   Forms a line identifier.
+ * @details A port/pad pair are encoded into an @p ioline_t type. The encoding
+ *          of this type is platform-dependent.
+ * @note    In this driver the pad number is encoded in the lower 4 bits of
+ *          the GPIO address which are guaranteed to be zero.
+ */
+#define PAL_LINE(port, pad)                                                 \
+  ((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad)))
+
+/**
+ * @brief   Decodes a port identifier from a line identifier.
+ */
+#define PAL_PORT(line)                                                      \
+  ((ioportid_t)(((uint32_t)(line)) & 0xFFFFFFF0U))
+
+/**
+ * @brief   Decodes a pad identifier from a line identifier.
+ */
+#define PAL_PAD(line)                                                       \
+  ((uint32_t)((uint32_t)(line) & 0x0000000FU))
+
+/**
+ * @brief   Value identifying an invalid line.
+ */
+#define PAL_NOLINE                      0U
+/** @} */
+
+/**
+ * @brief   GPIO port setup info.
+ */
+typedef struct
+{
+  /** @brief Initial value for DATA register.*/
+  uint32_t data;
+  /** @brief Initial value for DIR register.*/
+  uint32_t dir;
+  /** @brief Initial value for AFSEL register.*/
+  uint32_t afsel;
+  /** @brief Initial value for DR2R register.*/
+  uint32_t dr2r;
+  /** @brief Initial value for DR4R register.*/
+  uint32_t dr4r;
+  /** @brief Initial value for DR8R register.*/
+  uint32_t dr8r;
+  /** @brief Initial value for ODR register.*/
+  uint32_t odr;
+  /** @brief Initial value for PUR register.*/
+  uint32_t pur;
+  /** @brief Initial value for PDR register.*/
+  uint32_t pdr;
+  /** @brief Initial value for SLR register.*/
+  uint32_t slr;
+  /** @brief Initial value for DEN register.*/
+  uint32_t den;
+  /** @brief Initial value for AMSEL register.*/
+  uint32_t amsel;
+  /** @brief Initial value for PCTL register.*/
+  uint32_t pctl;
+} tiva_gpio_setup_t;
+
+/**
+ * @brief   Tiva GPIO static initializer.
+ * @details An instance of this structure must be passed to @p palInit() at
+ *          system startup time in order to initialized the digital I/O
+ *          subsystem. This represents only the initial setup, specific pads
+ *          or whole ports can be reprogrammed at later time.
+ */
+typedef struct
+{
+  /** @brief GPIO port A setup data.*/
+  tiva_gpio_setup_t     PAData;
+  /** @brief GPIO port B setup data.*/
+  tiva_gpio_setup_t     PBData;
+  /** @brief GPIO port C setup data.*/
+  tiva_gpio_setup_t     PCData;
+  /** @brief GPIO port D setup data.*/
+  tiva_gpio_setup_t     PDData;
+  /** @brief GPIO port E setup data.*/
+  tiva_gpio_setup_t     PEData;
+  /** @brief GPIO port F setup data.*/
+  tiva_gpio_setup_t     PFData;
+#if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
+  /** @brief GPIO port G setup data.*/
+  tiva_gpio_setup_t     PGData;
+#endif
+#if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
+  /** @brief GPIO port H setup data.*/
+  tiva_gpio_setup_t     PHData;
+#endif
+#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
+  /** @brief GPIO port J setup data.*/
+  tiva_gpio_setup_t     PJData;
+#endif
+#if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
+  /** @brief GPIO port K setup data.*/
+  tiva_gpio_setup_t     PKData;
+#endif
+#if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
+  /** @brief GPIO port L setup data.*/
+  tiva_gpio_setup_t     PLData;
+#endif
+#if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
+  /** @brief GPIO port M setup data.*/
+  tiva_gpio_setup_t     PMData;
+#endif
+#if TIVA_HAS_GPION || defined(__DOXYGEN__)
+  /** @brief GPIO port N setup data.*/
+  tiva_gpio_setup_t     PNData;
+#endif
+#if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
+  /** @brief GPIO port P setup data.*/
+  tiva_gpio_setup_t     PPData;
+#endif
+#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
+  /** @brief GPIO port Q setup data.*/
+  tiva_gpio_setup_t     PQData;
+#endif
+#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
+  /** @brief GPIO port R setup data.*/
+  tiva_gpio_setup_t     PRData;
+#endif
+#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
+  /** @brief GPIO port S setup data.*/
+  tiva_gpio_setup_t     PSData;
+#endif
+#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
+  /** @brief GPIO port T setup data.*/
+  tiva_gpio_setup_t     PTData;
+#endif
+} PALConfig;
+
+/**
+ * @brief   Digital I/O port sized unsigned type.
+ */
+typedef uint32_t ioportmask_t;
+
+/**
+ * @brief   Digital I/O modes.
+ */
+typedef uint32_t iomode_t;
+
+/**
+ * @brief   Type of an I/O line.
+ */
+typedef uint32_t ioline_t;
+
+/**
+ * @brief   Type of an event mode.
+ */
+typedef uint32_t ioeventmode_t;
+
+/**
+ * @brief   Port Identifier.
+ */
+typedef uint32_t ioportid_t;
+
+/**
+ * @brief   Type of an pad identifier.
+ */
+typedef uint32_t iopadid_t;
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   GPIOA interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOA_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOB interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOB_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOB_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOC interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOC_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOC_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOD interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOD_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOD_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOE interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOE_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOE_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOF interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOF_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOF_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOG interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOG_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOG_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOH interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOH_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOH_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOJ interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOJ_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOJ_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOK interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOK_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOK_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOL interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOL_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOL_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOM interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOM_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOM_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPION interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPION_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPION_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOP0 interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOP0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOP0_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOP1 interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOP1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOP1_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOP2 interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOP2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOP2_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOP3 interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOP3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOP3_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOP4 interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOP4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOP4_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOP5 interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOP5_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOP5_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOP6 interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOP6_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOP6_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOP7 interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOP7_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOP7_IRQ_PRIORITY        3
+#endif
+/** @} */
+
+/**
+ * @brief   GPIOQ0 interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOQ0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOQ0_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOQ1 interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOQ1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOQ1_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOQ2 interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOQ2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOQ2_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOQ3 interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOQ3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOQ3_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOQ4 interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOQ4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOQ4_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOQ5 interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOQ5_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOQ5_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOQ6 interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOQ6_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOQ6_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOQ7 interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOQ7_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOQ7_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOR interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOR_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOR_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOS interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOS_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOS_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOT interrupt priority level setting.
+ */
+#if !defined(TIVA_PAL_GPIOT_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOT_IRQ_PRIORITY         3
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#define GPIOA                               GPIO_PORTA_AHB_BASE
+#define GPIOB                               GPIO_PORTB_AHB_BASE
+#define GPIOC                               GPIO_PORTC_AHB_BASE
+#define GPIOD                               GPIO_PORTD_AHB_BASE
+#define GPIOE                               GPIO_PORTE_AHB_BASE
+#define GPIOF                               GPIO_PORTF_AHB_BASE
+#define GPIOG                               GPIO_PORTG_AHB_BASE
+#define GPIOH                               GPIO_PORTH_AHB_BASE
+#define GPIOJ                               GPIO_PORTJ_AHB_BASE
+#define GPIOK                               GPIO_PORTK_BASE
+#define GPIOL                               GPIO_PORTL_BASE
+#define GPIOM                               GPIO_PORTM_BASE
+#define GPION                               GPIO_PORTN_BASE
+#define GPIOP                               GPIO_PORTP_BASE
+#define GPIOQ                               GPIO_PORTQ_BASE
+#define GPIOR                               GPIO_PORTR_BASE
+#define GPIOS                               GPIO_PORTS_BASE
+#define GPIOT                               GPIO_PORTT_BASE
+
+#if TIVA_HAS_GPIOA &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOA_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOA"
+#endif
+
+#if TIVA_HAS_GPIOB &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOB_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOB"
+#endif
+
+#if TIVA_HAS_GPIOC &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOC_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOC"
+#endif
+
+#if TIVA_HAS_GPIOD &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOD_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOD"
+#endif
+
+#if TIVA_HAS_GPIOE &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOE_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOE"
+#endif
+
+#if TIVA_HAS_GPIOF &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOF_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOF"
+#endif
+
+#if TIVA_HAS_GPIOG &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOG_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOG"
+#endif
+
+#if TIVA_HAS_GPIOH &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOH_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOH"
+#endif
+
+#if TIVA_HAS_GPIOJ &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOJ_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOJ"
+#endif
+
+#if TIVA_HAS_GPIOK &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOK_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOK"
+#endif
+
+#if TIVA_HAS_GPIOL &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOL_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOL"
+#endif
+
+#if TIVA_HAS_GPIOM &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOM_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOM"
+#endif
+
+#if TIVA_HAS_GPION &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPION_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPION"
+#endif
+
+#if TIVA_HAS_GPIOP &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP0_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOP0"
+#endif
+
+#if TIVA_HAS_GPIOP &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOP1"
+#endif
+
+#if TIVA_HAS_GPIOP &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOP2"
+#endif
+
+#if TIVA_HAS_GPIOP &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOP3"
+#endif
+
+#if TIVA_HAS_GPIOP &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP4_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOP4"
+#endif
+
+#if TIVA_HAS_GPIOP &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP5_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOP5"
+#endif
+
+#if TIVA_HAS_GPIOP &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP6_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOP6"
+#endif
+
+#if TIVA_HAS_GPIOP &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP7_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOP7"
+#endif
+
+#if TIVA_HAS_GPIOQ &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ0_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOQ0"
+#endif
+
+#if TIVA_HAS_GPIOQ &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOQ1"
+#endif
+
+#if TIVA_HAS_GPIOQ &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOQ2"
+#endif
+
+#if TIVA_HAS_GPIOQ &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOQ3"
+#endif
+
+#if TIVA_HAS_GPIOQ &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ4_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOQ4"
+#endif
+
+#if TIVA_HAS_GPIOQ &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ5_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOQ5"
+#endif
+
+#if TIVA_HAS_GPIOQ &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ6_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOQ6"
+#endif
+
+#if TIVA_HAS_GPIOQ &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ7_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOQ7"
+#endif
+
+#if TIVA_HAS_GPIOR &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOR_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOR"
+#endif
+
+#if TIVA_HAS_GPIOS &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOS_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOS"
+#endif
+
+#if TIVA_HAS_GPIOT &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOT_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOT"
+#endif
+
+/*===========================================================================*/
+/* I/O Ports Identifiers.                                                    */
+/*===========================================================================*/
+
+/**
+ * @brief   GPIO port A identifier.
+ */
+#define IOPORT1         GPIOA
+
+/**
+ * @brief   GPIO port B identifier.
+ */
+#define IOPORT2         GPIOB
+
+/**
+ * @brief   GPIO port C identifier.
+ */
+#define IOPORT3         GPIOC
+
+/**
+ * @brief   GPIO port D identifier.
+ */
+#define IOPORT4         GPIOD
+
+/**
+ * @brief   GPIO port E identifier.
+ */
+#define IOPORT5         GPIOE
+
+/**
+ * @brief   GPIO port F identifier.
+ */
+#define IOPORT6         GPIOF
+
+/**
+ * @brief   GPIO port G identifier.
+ */
+#if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
+#define IOPORT7         GPIOG
+#endif
+
+/**
+ * @brief   GPIO port H identifier.
+ */
+#if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
+#define IOPORT8         GPIOH
+#endif
+
+/**
+ * @brief   GPIO port J identifier.
+ */
+#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
+#define IOPORT9         GPIOJ
+#endif
+
+/**
+ * @brief   GPIO port K identifier.
+ */
+#if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
+#define IOPORT10        GPIOK
+#endif
+
+/**
+ * @brief   GPIO port L identifier.
+ */
+#if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
+#define IOPORT11        GPIOL
+#endif
+
+/**
+ * @brief   GPIO port M identifier.
+ */
+#if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
+#define IOPORT12        GPIOM
+#endif
+
+/**
+ * @brief   GPIO port N identifier.
+ */
+#if TIVA_HAS_GPION || defined(__DOXYGEN__)
+#define IOPORT13        GPION
+#endif
+
+/**
+ * @brief   GPIO port P identifier.
+ */
+#if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
+#define IOPORT14        GPIOP
+#endif
+
+/**
+ * @brief   GPIO port Q identifier.
+ */
+#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
+#define IOPORT15        GPIOQ
+#endif
+
+/**
+ * @brief   GPIO port R identifier.
+ */
+#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
+#define IOPORT16        GPIOR
+#endif
+
+/**
+ * @brief   GPIO port S identifier.
+ */
+#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
+#define IOPORT17        GPIOS
+#endif
+
+/**
+ * @brief   GPIO port T identifier.
+ */
+#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
+#define IOPORT18        GPIOT
+#endif
+
+/*===========================================================================*/
+/* Implementation, some of the following macros could be implemented as      */
+/* functions, if so please put them in pal_lld.c.                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level PAL subsystem initialization.
+ *
+ * @param[in] config    architecture-dependent ports configuration
+ *
+ * @notapi
+ */
+#define pal_lld_init(config) _pal_lld_init(config)
+
+/**
+ * @brief   Reads the physical I/O port states.
+ *
+ * @param[in] port      port identifier
+ * @return              The port bits.
+ *
+ * @notapi
+ */
+#define pal_lld_readport(port) (HWREG((port) + GPIO_O_DATA + (0xff << 2)))
+
+/**
+ * @brief   Reads the output latch.
+ * @details The purpose of this function is to read back the latched output
+ *          value.
+ *
+ * @param[in] port      port identifier
+ * @return              The latched logical states.
+ *
+ * @notapi
+ */
+#define pal_lld_readlatch(port) pal_lld_readport(port)
+
+/**
+ * @brief   Writes a bits mask on a I/O port.
+ *
+ * @param[in] port      port identifier
+ * @param[in] bits      bits to be written on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_writeport(port, bits) (HWREG((port) + GPIO_O_DATA + (0xff << 2)) = (bits))
+
+/**
+ * @brief   Sets a bits mask on a I/O port.
+ * @note    The @ref PAL provides a default software implementation of this
+ *          functionality, implement this function if can optimize it by using
+ *          special hardware functionalities or special coding.
+ *
+ * @param[in] port      port identifier
+ * @param[in] bits      bits to be ORed on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_setport(port, bits) (HWREG((port) + (GPIO_O_DATA + (bits << 2))) = 0xFF)
+
+/**
+ * @brief   Clears a bits mask on a I/O port.
+ * @note    The @ref PAL provides a default software implementation of this
+ *          functionality, implement this function if can optimize it by using
+ *          special hardware functionalities or special coding.
+ *
+ * @param[in] port      port identifier
+ * @param[in] bits      bits to be cleared on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_clearport(port, bits) (HWREG((port) + (GPIO_O_DATA + (bits << 2))) = 0)
+
+/**
+ * @brief   Reads a group of bits.
+ * @note    The @ref PAL provides a default software implementation of this
+ *          functionality, implement this function if can optimize it by using
+ *          special hardware functionalities or special coding.
+ *
+ * @param[in] port      port identifier
+ * @param[in] mask      group mask
+ * @param[in] offset    group bit offset within the port
+ * @return              The group logical states.
+ *
+ * @notapi
+ */
+#define pal_lld_readgroup(port, mask, offset)   \
+  (HWREG((port) + (GPIO_O_DATA + (((mask) << (offset)) << 2))))
+
+/**
+ * @brief   Writes a group of bits.
+ * @note    The @ref PAL provides a default software implementation of this
+ *          functionality, implement this function if can optimize it by using
+ *          special hardware functionalities or special coding.
+ *
+ * @param[in] port      port identifier
+ * @param[in] mask      group mask
+ * @param[in] offset    group bit offset within the port
+ * @param[in] bits      bits to be written. Values exceeding the group width
+ *                      are masked.
+ *
+ * @notapi
+ */
+#define pal_lld_writegroup(port, mask, offset, bits)    \
+  (HWREG((port) + (GPIO_O_DATA + (((mask) << (offset)) << 2))) = (bits))
+
+/**
+ * @brief   Pads group mode setup.
+ * @details This function programs a pads group belonging to the same port
+ *          with the specified mode.
+ * @note    Programming an unknown or unsupported mode is silently ignored.
+ *
+ * @param[in] port      port identifier
+ * @param[in] mask      group mask
+ * @param[in] offset    group bit offset within the port
+ * @param[in] mode      group mode
+ *
+ * @notapi
+ */
+#define pal_lld_setgroupmode(port, mask, offset, mode)                      \
+  _pal_lld_setgroupmode(port, mask << offset, mode)
+
+/**
+ * @brief   Reads a logical state from an I/O pad.
+ * @note    The @ref PAL provides a default software implementation of this
+ *          functionality, implement this function if can optimize it by using
+ *          special hardware functionalities or special coding.
+ *
+ * @param[in] port      port identifier
+ * @param[in] pad       pad number within the port
+ * @return              The logical state.
+ * @retval PAL_LOW      low logical state.
+ * @retval PAL_HIGH     high logical state.
+ *
+ * @notapi
+ */
+#define pal_lld_readpad(port, pad) (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2))))
+
+/**
+ * @brief   Writes a logical state on an output pad.
+ * @note    This function is not meant to be invoked directly by the
+ *          application  code.
+ * @note    The @ref PAL provides a default software implementation of this
+ *          functionality, implement this function if can optimize it by using
+ *          special hardware functionalities or special coding.
+ *
+ * @param[in] port      port identifier
+ * @param[in] pad       pad number within the port
+ * @param[in] bit       logical value, the value must be @p PAL_LOW or
+ *                      @p PAL_HIGH
+ *
+ * @notapi
+ */
+#define pal_lld_writepad(port, pad, bit)    \
+  (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2))) = 1 << (bit))
+
+/**
+ * @brief   Sets a pad logical state to @p PAL_HIGH.
+ * @note    The @ref PAL provides a default software implementation of this
+ *          functionality, implement this function if can optimize it by using
+ *          special hardware functionalities or special coding.
+ *
+ * @param[in] port      port identifier
+ * @param[in] pad       pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_setpad(port, pad)   \
+  (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2))) = 1 << (pad))
+
+/**
+ * @brief   Clears a pad logical state to @p PAL_LOW.
+ * @note    The @ref PAL provides a default software implementation of this
+ *          functionality, implement this function if can optimize it by using
+ *          special hardware functionalities or special coding.
+ *
+ * @param[in] port      port identifier
+ * @param[in] pad       pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_clearpad(port, pad) \
+  (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2))) = 0)
+
+/**
+ * @brief   Pad event enable.
+ * @note    Programming an unknown or unsupported mode is silently ignored.
+ *
+ * @param[in] port      port identifier
+ * @param[in] pad       pad number within the port
+ * @param[in] mode      pad event mode
+ *
+ * @notapi
+ */
+#define pal_lld_enablepadevent(port, pad, mode)                             \
+  _pal_lld_enablepadevent(port, pad, mode)
+
+/**
+ * @brief   Pad event disable.
+ * @details This function disables previously programmed event callbacks.
+ *
+ * @param[in] port      port identifier
+ * @param[in] pad       pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_disablepadevent(port, pad)                                  \
+  _pal_lld_disablepadevent(port, pad)
+
+/**
+ * @brief   Returns a PAL event structure associated to a pad.
+ *
+ * @param[in] port      port identifier
+ * @param[in] pad       pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_get_pad_event(port, pad)                                    \
+  &_pal_events[((((((uint32_t)port - (uint32_t)GPIOA) >> 12) & 0x1FU) * 8) + pad)];
+
+/**
+ * @brief   Returns a PAL event structure associated to a line.
+ *
+ * @param[in] line      line identifier
+ *
+ * @notapi
+ */
+#define pal_lld_get_line_event(line)                                        \
+  &_pal_events[((((((uint32_t)PAL_PORT(line) - (uint32_t)GPIOA) >> 12) & 0x1FU) * 8) + PAL_PAD(line))]
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+extern const PALConfig pal_default_config;
+extern palevent_t _pal_events[TIVA_GPIO_PINS];
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void _pal_lld_init(const PALConfig *config);
+  void _pal_lld_setgroupmode(ioportid_t port,
+                             ioportmask_t mask,
+                             iomode_t mode);
+#if PAL_USE_CALLBACKS || PAL_USE_WAIT
+  void _pal_lld_enablepadevent(ioportid_t port,
+                               iopadid_t pad,
+                               ioeventmode_t mode);
+  void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad);
+  void pal_lld_disable_irqs(void);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_PAL */
+
+#endif /* HAL_PAL_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/TIVA/LLD/GPTM/driver.mk b/os/hal/ports/TIVA/LLD/GPTM/driver.mk
new file mode 100644
index 0000000..f003ce4
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/GPTM/driver.mk
@@ -0,0 +1,11 @@
+PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c
+
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPTM
diff --git a/os/hal/ports/TIVA/LLD/hal_gpt_lld.c b/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c
index 86f2303..8fb02f5 100644
--- a/os/hal/ports/TIVA/LLD/hal_gpt_lld.c
+++ b/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -15,7 +15,7 @@
 */
 
 /**
- * @file    TIVA/gpt_lld.c
+ * @file    GPTM/hal_gpt_lld.c
  * @brief   TM4C123x/TM4C129x GPT subsystem low level driver source.
  *
  * @addtogroup GPT
@@ -133,7 +133,7 @@ GPTDriver GPTD12;
  */
 static void gpt_lld_serve_interrupt(GPTDriver *gptp)
 {
-  gptp->gpt->ICR = 0xffffffff;
+  HWREG(gptp->gpt + TIMER_O_ICR) = 0xffffffff;
 
   if (gptp->state == GPT_ONESHOT) {
     gptp->state = GPT_READY;
@@ -388,62 +388,62 @@ void gpt_lld_init(void)
 {
   /* Driver initialization.*/
 #if TIVA_GPT_USE_GPT0
-  GPTD1.gpt = GPT0;
+  GPTD1.gpt = TIMER0_BASE;
   gptObjectInit(&GPTD1);
 #endif
 
 #if TIVA_GPT_USE_GPT1
-  GPTD2.gpt = GPT1;
+  GPTD2.gpt = TIMER1_BASE;
   gptObjectInit(&GPTD2);
 #endif
 
 #if TIVA_GPT_USE_GPT2
-  GPTD3.gpt = GPT2;
+  GPTD3.gpt = TIMER2_BASE;
   gptObjectInit(&GPTD3);
 #endif
 
 #if TIVA_GPT_USE_GPT3
-  GPTD4.gpt = GPT3;
+  GPTD4.gpt = TIMER3_BASE;
   gptObjectInit(&GPTD4);
 #endif
 
 #if TIVA_GPT_USE_GPT4
-  GPTD5.gpt = GPT4;
+  GPTD5.gpt = TIMER4_BASE;
   gptObjectInit(&GPTD5);
 #endif
 
 #if TIVA_GPT_USE_GPT5
-  GPTD6.gpt = GPT5;
+  GPTD6.gpt = TIMER5_BASE;
   gptObjectInit(&GPTD6);
 #endif
 
 #if TIVA_GPT_USE_WGPT0
-  GPTD7.gpt = WGPT0;
+  GPTD7.gpt = WTIMER0_BASE;
   gptObjectInit(&GPTD7);
 #endif
 
 #if TIVA_GPT_USE_WGPT1
-  GPTD8.gpt = WGPT1;
+  GPTD8.gpt = WTIMER1_BASE;
   gptObjectInit(&GPTD8);
 #endif
 
 #if TIVA_GPT_USE_WGPT2
-  GPTD9.gpt = WGPT2;
+  GPTD9.gpt = WTIMER2_BASE;
   gptObjectInit(&GPTD9);
 #endif
 
 #if TIVA_GPT_USE_WGPT3
-  GPTD10.gpt = WGPT3;
+  GPTD10.gpt = WTIMER3_BASE;
   gptObjectInit(&GPTD10);
 #endif
 
 #if TIVA_GPT_USE_WGPT4
-  GPTD11.gpt = WGPT4;
+  GPTD11.gpt = WTIMER4_BASE;
   gptObjectInit(&GPTD11);
 #endif
 
 #if TIVA_GPT_USE_WGPT5
-  GPTD12.gpt = WGPT5;
+  GPTD12.gpt = WTIMER5_BASE;
   gptObjectInit(&GPTD12);
 #endif
 }
@@ -461,93 +461,141 @@ void gpt_lld_start(GPTDriver *gptp)
     /* Clock activation.*/
 #if TIVA_GPT_USE_GPT0
     if (&GPTD1 == gptp) {
-      SYSCTL->RCGCTIMER |= (1 << 0);
+      HWREG(SYSCTL_RCGCTIMER) |= (1 << 0);
+
+      while (!(HWREG(SYSCTL_PRTIMER) & (1 << 0)))
+        ;
+
       nvicEnableVector(TIVA_GPT0A_NUMBER, TIVA_GPT_GPT0A_IRQ_PRIORITY);
     }
 #endif
 
 #if TIVA_GPT_USE_GPT1
     if (&GPTD2 == gptp) {
-      SYSCTL->RCGCTIMER |= (1 << 1);
+      HWREG(SYSCTL_RCGCTIMER) |= (1 << 1);
+
+      while (!(HWREG(SYSCTL_PRTIMER) & (1 << 1)))
+        ;
+
       nvicEnableVector(TIVA_GPT1A_NUMBER, TIVA_GPT_GPT1A_IRQ_PRIORITY);
     }
 #endif
 
 #if TIVA_GPT_USE_GPT2
     if (&GPTD3 == gptp) {
-      SYSCTL->RCGCTIMER |= (1 << 2);
+      HWREG(SYSCTL_RCGCTIMER) |= (1 << 2);
+
+      while (!(HWREG(SYSCTL_PRTIMER) & (1 << 2)))
+        ;
+
       nvicEnableVector(TIVA_GPT2A_NUMBER, TIVA_GPT_GPT2A_IRQ_PRIORITY);
     }
 #endif
 
 #if TIVA_GPT_USE_GPT3
     if (&GPTD4 == gptp) {
-      SYSCTL->RCGCTIMER |= (1 << 3);
+      HWREG(SYSCTL_RCGCTIMER) |= (1 << 3);
+
+      while (!(HWREG(SYSCTL_PRTIMER) & (1 << 3)))
+        ;
+
       nvicEnableVector(TIVA_GPT3A_NUMBER, TIVA_GPT_GPT3A_IRQ_PRIORITY);
     }
 #endif
 
 #if TIVA_GPT_USE_GPT4
     if (&GPTD5 == gptp) {
-      SYSCTL->RCGCTIMER |= (1 << 4);
+      HWREG(SYSCTL_RCGCTIMER) |= (1 << 4);
+
+      while (!(HWREG(SYSCTL_PRTIMER) & (1 << 4)))
+        ;
+
       nvicEnableVector(TIVA_GPT4A_NUMBER, TIVA_GPT_GPT4A_IRQ_PRIORITY);
     }
 #endif
 
 #if TIVA_GPT_USE_GPT5
     if (&GPTD6 == gptp) {
-      SYSCTL->RCGCTIMER |= (1 << 5);
+      HWREG(SYSCTL_RCGCTIMER) |= (1 << 5);
+
+      while (!(HWREG(SYSCTL_PRTIMER) & (1 << 5)))
+        ;
+
       nvicEnableVector(TIVA_GPT5A_NUMBER, TIVA_GPT_GPT5A_IRQ_PRIORITY);
     }
 #endif
 
 #if TIVA_GPT_USE_WGPT0
     if (&GPTD7 == gptp) {
-      SYSCTL->RCGCWTIMER |= (1 << 0);
+      HWREG(SYSCTL_RCGCWTIMER) |= (1 << 0);
+
+      while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 0)))
+        ;
+
       nvicEnableVector(TIVA_WGPT0A_NUMBER, TIVA_GPT_WGPT0A_IRQ_PRIORITY);
     }
 #endif
 
 #if TIVA_GPT_USE_WGPT1
     if (&GPTD8 == gptp) {
-      SYSCTL->RCGCWTIMER |= (1 << 1);
+      HWREG(SYSCTL_RCGCWTIMER) |= (1 << 1);
+
+      while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 1)))
+        ;
+
       nvicEnableVector(TIVA_WGPT1A_NUMBER, TIVA_GPT_WGPT1A_IRQ_PRIORITY);
     }
 #endif
 
 #if TIVA_GPT_USE_WGPT2
     if (&GPTD9 == gptp) {
-      SYSCTL->RCGCWTIMER |= (1 << 2);
+      HWREG(SYSCTL_RCGCWTIMER) |= (1 << 2);
+
+      while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 2)))
+        ;
+
       nvicEnableVector(TIVA_WGPT2A_NUMBER, TIVA_GPT_WGPT2A_IRQ_PRIORITY);
     }
 #endif
 
 #if TIVA_GPT_USE_WGPT3
     if (&GPTD10 == gptp) {
-      SYSCTL->RCGCWTIMER |= (1 << 3);
+      HWREG(SYSCTL_RCGCWTIMER) |= (1 << 3);
+
+      while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 3)))
+        ;
+
       nvicEnableVector(TIVA_WGPT3A_NUMBER, TIVA_GPT_WGPT3A_IRQ_PRIORITY);
     }
 #endif
 
 #if TIVA_GPT_USE_WGPT4
     if (&GPTD11 == gptp) {
-      SYSCTL->RCGCWTIMER |= (1 << 4);
+      HWREG(SYSCTL_RCGCWTIMER) |= (1 << 4);
+
+      while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 4)))
+        ;
+
       nvicEnableVector(TIVA_WGPT4A_NUMBER, TIVA_GPT_WGPT4A_IRQ_PRIORITY);
     }
 #endif
 
 #if TIVA_GPT_USE_WGPT5
     if (&GPTD12 == gptp) {
-      SYSCTL->RCGCWTIMER |= (1 << 5);
+      HWREG(SYSCTL_RCGCWTIMER) |= (1 << 5);
+
+      while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 5)))
+        ;
+
       nvicEnableVector(TIVA_WGPT5A_NUMBER, TIVA_GPT_WGPT5A_IRQ_PRIORITY);
     }
 #endif
   }
 
   /* Timer configuration.*/
-  gptp->gpt->CTL = 0;
-  gptp->gpt->CFG = GPTM_CFG_CFG_SPLIT;
-  gptp->gpt->TAPR = ((TIVA_SYSCLK / gptp->config->frequency) - 1);
+  HWREG(gptp->gpt + TIMER_O_CTL) = 0;
+  HWREG(gptp->gpt + TIMER_O_CFG) = TIMER_CFG_16_BIT;
+  HWREG(gptp->gpt + TIMER_O_TAPR) = ((TIVA_SYSCLK / gptp->config->frequency) - 1);
 }
 
 /**
@@ -560,91 +608,91 @@ void gpt_lld_start(GPTDriver *gptp)
 void gpt_lld_stop(GPTDriver *gptp)
 {
   if (gptp->state == GPT_READY) {
-    gptp->gpt->IMR = 0;
-    gptp->gpt->TAILR = 0;
-    gptp->gpt->CTL = 0;
+    HWREG(gptp->gpt + TIMER_O_IMR) = 0;
+    HWREG(gptp->gpt + TIMER_O_TAILR) = 0;
+    HWREG(gptp->gpt + TIMER_O_CTL) = 0;
 
 #if TIVA_GPT_USE_GPT0
     if (&GPTD1 == gptp) {
       nvicDisableVector(TIVA_GPT0A_NUMBER);
-      SYSCTL->RCGCTIMER &= ~(1 << 0);
+      HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 0);
     }
 #endif
 
 #if TIVA_GPT_USE_GPT1
     if (&GPTD2 == gptp) {
       nvicDisableVector(TIVA_GPT1A_NUMBER);
-      SYSCTL->RCGCTIMER &= ~(1 << 1);
+      HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 1);
     }
 #endif
 
 #if TIVA_GPT_USE_GPT2
     if (&GPTD3 == gptp) {
       nvicDisableVector(TIVA_GPT2A_NUMBER);
-      SYSCTL->RCGCTIMER &= ~(1 << 2);
+      HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 2);
     }
 #endif
 
 #if TIVA_GPT_USE_GPT3
     if (&GPTD4 == gptp) {
       nvicDisableVector(TIVA_GPT3A_NUMBER);
-      SYSCTL->RCGCTIMER &= ~(1 << 3);
+      HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 3);
     }
 #endif
 
 #if TIVA_GPT_USE_GPT4
     if (&GPTD5 == gptp) {
       nvicDisableVector(TIVA_GPT4A_NUMBER);
-      SYSCTL->RCGCTIMER &= ~(1 << 4);
+      HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 4);
     }
 #endif
 
 #if TIVA_GPT_USE_GPT5
     if (&GPTD6 == gptp) {
       nvicDisableVector(TIVA_GPT5A_NUMBER);
-      SYSCTL->RCGCTIMER &= ~(1 << 5);
+      HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 5);
     }
 #endif
 
 #if TIVA_GPT_USE_WGPT0
     if (&GPTD7 == gptp) {
       nvicDisableVector(TIVA_WGPT0A_NUMBER);
-      SYSCTL->RCGCWTIMER &= ~(1 << 0);
+      HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 0);
     }
 #endif
 
 #if TIVA_GPT_USE_WGPT1
     if (&GPTD8 == gptp) {
       nvicDisableVector(TIVA_WGPT1A_NUMBER);
-      SYSCTL->RCGCWTIMER &= ~(1 << 1);
+      HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 1);
     }
 #endif
 
 #if TIVA_GPT_USE_WGPT2
     if (&GPTD9 == gptp) {
       nvicDisableVector(TIVA_WGPT2A_NUMBER);
-      SYSCTL->RCGCWTIMER &= ~(1 << 2);
+      HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 2);
     }
 #endif
 
 #if TIVA_GPT_USE_WGPT3
     if (&GPTD10 == gptp) {
       nvicDisableVector(TIVA_WGPT3A_NUMBER);
-      SYSCTL->RCGCWTIMER &= ~(1 << 3);
+      HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 3);
     }
 #endif
 
 #if TIVA_GPT_USE_WGPT4
     if (&GPTD11 == gptp) {
       nvicDisableVector(TIVA_WGPT4A_NUMBER);
-      SYSCTL->RCGCWTIMER &= ~(1 << 4);
+      HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 4);
     }
 #endif
 
 #if TIVA_GPT_USE_WGPT5
     if (&GPTD12 == gptp) {
       nvicDisableVector(TIVA_WGPT5A_NUMBER);
-      SYSCTL->RCGCWTIMER &= ~(1 << 5);
+      HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 5);
     }
 #endif
   }
@@ -660,11 +708,11 @@ void gpt_lld_stop(GPTDriver *gptp)
  */
 void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval)
 {
-  gptp->gpt->TAILR = interval - 1;
-  gptp->gpt->ICR = 0xfffffff;
-  gptp->gpt->IMR = GPTM_IMR_TATOIM;
-  gptp->gpt->TAMR = GPTM_TAMR_TAMR_PERIODIC | GPTM_TAMR_TAILD | GPTM_TAMR_TASNAPS;
-  gptp->gpt->CTL = GPTM_CTL_TAEN | GPTM_CTL_TASTALL;
+  HWREG(gptp->gpt + TIMER_O_TAILR) = interval - 1;
+  HWREG(gptp->gpt + TIMER_O_ICR) = 0xfffffff;
+  HWREG(gptp->gpt + TIMER_O_IMR) = TIMER_IMR_TATOIM;
+  HWREG(gptp->gpt + TIMER_O_TAMR) = TIMER_TAMR_TAMR_PERIOD | TIMER_TAMR_TAILD | TIMER_TAMR_TASNAPS;
+  HWREG(gptp->gpt + TIMER_O_CTL) = TIMER_CTL_TAEN | TIMER_CTL_TASTALL;
 }
 
 /**
@@ -676,9 +724,9 @@ void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval)
  */
 void gpt_lld_stop_timer(GPTDriver *gptp)
 {
-  gptp->gpt->IMR = 0;
-  gptp->gpt->TAILR = 0;
-  gptp->gpt->CTL &= ~GPTM_CTL_TAEN;
+  HWREG(gptp->gpt + TIMER_O_IMR) = 0;
+  HWREG(gptp->gpt + TIMER_O_TAILR) = 0;
+  HWREG(gptp->gpt + TIMER_O_CTL) &= ~TIMER_CTL_TAEN;
 }
 
 /**
@@ -694,13 +742,13 @@ void gpt_lld_stop_timer(GPTDriver *gptp)
  */
 void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval)
 {
-  gptp->gpt->TAMR = GPTM_TAMR_TAMR_ONESHOT | GPTM_TAMR_TAILD | GPTM_TAMR_TASNAPS;
-  gptp->gpt->TAILR = interval - 1;
-  gptp->gpt->ICR = 0xffffffff;
-  gptp->gpt->CTL = GPTM_CTL_TAEN | GPTM_CTL_TASTALL;
-  while (!(gptp->gpt->RIS & GPTM_IMR_TATOIM))
+  HWREG(gptp->gpt + TIMER_O_TAMR) = TIMER_TAMR_TAMR_1_SHOT | TIMER_TAMR_TAILD | TIMER_TAMR_TASNAPS;
+  HWREG(gptp->gpt + TIMER_O_TAILR) = interval - 1;
+  HWREG(gptp->gpt + TIMER_O_ICR) = 0xffffffff;
+  HWREG(gptp->gpt + TIMER_O_CTL) = TIMER_CTL_TAEN | TIMER_CTL_TASTALL;
+  while (!(HWREG(gptp->gpt + TIMER_O_RIS) & TIMER_IMR_TATOIM))
     ;
-  gptp->gpt->ICR = 0xffffffff;
+  HWREG(gptp->gpt + TIMER_O_ICR) = 0xffffffff;
 }
 
 #endif /* HAL_USE_GPT */
diff --git a/os/hal/ports/TIVA/LLD/hal_gpt_lld.h b/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.h
index e518e58..6b4196f 100644
--- a/os/hal/ports/TIVA/LLD/hal_gpt_lld.h
+++ b/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.h
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -15,7 +15,7 @@
 */
 
 /**
- * @file    TIVA/gpt_lld.h
+ * @file    GPTM/hal_gpt_lld.h
  * @brief   TM4C123x/TM4C129x GPT subsystem low level driver header.
  *
  * @addtogroup GPT
@@ -405,7 +405,7 @@ struct GPTDriver {
   /**
    * @brief Pointer to the GPT registers block.
    */
-  GPT_TypeDef               *gpt;
+  uint32_t                   gpt;
 };
 
 /*===========================================================================*/
@@ -426,7 +426,7 @@ struct GPTDriver {
  * @notapi
  */
 #define gpt_lld_change_interval(gptp, interval) {                           \
-  gptp->gpt->TAILR = interval - 1;                                          \
+  HWREG(gptp->gpt + TIMER_O_TAILR) = interval - 1;                                          \
 }
 
 /*===========================================================================*/
diff --git a/os/hal/ports/TIVA/LLD/hal_st_lld.c b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c
index 30fdb8a..0f9576a 100644
--- a/os/hal/ports/TIVA/LLD/hal_st_lld.c
+++ b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -15,7 +15,7 @@
 */
 
 /**
- * @file    Tiva/LLD/st_lld.c
+ * @file    GPTM/hal_st_lld.c
  * @brief   ST Driver subsystem low level driver code.
  *
  * @addtogroup ST
@@ -37,44 +37,44 @@
 #if TIVA_ST_TIMER_NUMBER == 0
 #define ST_HANDLER                          TIVA_WGPT0A_HANDLER
 #define ST_NUMBER                           TIVA_WGPT0A_NUMBER
-#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCWTIMER |= (1 << 0))
-#define ST_WAIT_CLOCK()                     while (!(SYSCTL->PRWTIMER & (1 << 0)))
+#define ST_ENABLE_CLOCK()                   (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 0))
+#define ST_WAIT_CLOCK()                     while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 0)))
 
 #elif TIVA_ST_TIMER_NUMBER == 1
 #define ST_HANDLER                          TIVA_WGPT1A_HANDLER
 #define ST_NUMBER                           TIVA_WGPT1A_NUMBER
-#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCWTIMER |= (1 << 1))
-#define ST_WAIT_CLOCK()                     while (!(SYSCTL->PRWTIMER & (1 << 1)))
+#define ST_ENABLE_CLOCK()                   (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 1))
+#define ST_WAIT_CLOCK()                     while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 1)))
 
 #elif TIVA_ST_TIMER_NUMBER == 2
 #define ST_HANDLER                          TIVA_WGPT2A_HANDLER
 #define ST_NUMBER                           TIVA_WGPT2A_NUMBER
-#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCWTIMER |= (1 << 2))
-#define ST_WAIT_CLOCK()                     while (!(SYSCTL->PRWTIMER & (1 << 2)))
+#define ST_ENABLE_CLOCK()                   (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 2))
+#define ST_WAIT_CLOCK()                     while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 2)))
 
 #elif TIVA_ST_TIMER_NUMBER == 3
 #define ST_HANDLER                          TIVA_WGPT3A_HANDLER
 #define ST_NUMBER                           TIVA_WGPT3A_NUMBER
-#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCWTIMER |= (1 << 3))
-#define ST_WAIT_CLOCK()                     while (!(SYSCTL->PRWTIMER & (1 << 3)))
+#define ST_ENABLE_CLOCK()                   (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 3))
+#define ST_WAIT_CLOCK()                     while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 3)))
 
 #elif TIVA_ST_TIMER_NUMBER == 4
 #define ST_HANDLER                          TIVA_WGPT4A_HANDLER
 #define ST_NUMBER                           TIVA_WGPT4A_NUMBER
-#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCWTIMER |= (1 << 4))
-#define ST_WAIT_CLOCK()                     while (!(SYSCTL->PRWTIMER & (1 << 4)))
+#define ST_ENABLE_CLOCK()                   (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 4))
+#define ST_WAIT_CLOCK()                     while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 4)))
 
 #elif TIVA_ST_TIMER_NUMBER == 5
 #define ST_HANDLER                          TIVA_WGPT5A_HANDLER
 #define ST_NUMBER                           TIVA_WGPT5A_NUMBER
-#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCWTIMER |= (1 << 5))
-#define ST_WAIT_CLOCK()                     while (!(SYSCTL->PRWTIMER & (1 << 5)))
+#define ST_ENABLE_CLOCK()                   (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 5))
+#define ST_WAIT_CLOCK()                     while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 5)))
 
 #else
 #error "TIVA_ST_USE_TIMER specifies an unsupported timer"
 #endif
 
-#if (ST_CLOCK_SRC / OSAL_ST_FREQUENCY) - 1 > 0xFFFF
+#if (TIVA_SYSCLK / OSAL_ST_FREQUENCY) - 1 > 0xFFFF
 #error "the selected ST frequency is not obtainable because TIM timer prescaler limits"
 #endif
 
@@ -83,38 +83,38 @@
 #if TIVA_ST_TIMER_NUMBER == 0
 #define ST_HANDLER                          TIVA_GPT0A_HANDLER
 #define ST_NUMBER                           TIVA_GPT0A_NUMBER
-#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCTIMER |= (1 << 0))
-#define ST_WAIT_CLOCK()                     while (!(SYSCTL->PRTIMER & (1 << 0)))
+#define ST_ENABLE_CLOCK()                   (HWREG(SYSCTL_RCGCTIMER) |= (1 << 0))
+#define ST_WAIT_CLOCK()                     while (!(HWREG(SYSCTL_PRTIMER) & (1 << 0)))
 
 #elif TIVA_ST_TIMER_NUMBER == 1
 #define ST_HANDLER                          TIVA_GPT1A_HANDLER
 #define ST_NUMBER                           TIVA_GPT1A_NUMBER
-#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCTIMER |= (1 << 1))
-#define ST_WAIT_CLOCK()                     while (!(SYSCTL->PRTIMER & (1 << 1)))
+#define ST_ENABLE_CLOCK()                   (HWREG(SYSCTL_RCGCTIMER) |= (1 << 1))
+#define ST_WAIT_CLOCK()                     while (!(HWREG(SYSCTL_PRTIMER) & (1 << 1)))
 
 #elif TIVA_ST_TIMER_NUMBER == 2
 #define ST_HANDLER                          TIVA_GPT2A_HANDLER
 #define ST_NUMBER                           TIVA_GPT2A_NUMBER
-#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCTIMER |= (1 << 2))
-#define ST_WAIT_CLOCK()                     while (!(SYSCTL->PRTIMER & (1 << 2)))
+#define ST_ENABLE_CLOCK()                   (HWREG(SYSCTL_RCGCTIMER) |= (1 << 2))
+#define ST_WAIT_CLOCK()                     while (!(HWREG(SYSCTL_PRTIMER) & (1 << 2)))
 
 #elif TIVA_ST_TIMER_NUMBER == 3
 #define ST_HANDLER                          TIVA_GPT3A_HANDLER
 #define ST_NUMBER                           TIVA_GPT3A_NUMBER
-#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCTIMER |= (1 << 3))
-#define ST_WAIT_CLOCK()                     while (!(SYSCTL->PRTIMER & (1 << 3)))
+#define ST_ENABLE_CLOCK()                   (HWREG(SYSCTL_RCGCTIMER) |= (1 << 3))
+#define ST_WAIT_CLOCK()                     while (!(HWREG(SYSCTL_PRTIMER) & (1 << 3)))
 
 #elif TIVA_ST_TIMER_NUMBER == 4
 #define ST_HANDLER                          TIVA_GPT4A_HANDLER
 #define ST_NUMBER                           TIVA_GPT4A_NUMBER
-#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCTIMER |= (1 << 4))
-#define ST_WAIT_CLOCK()                     while (!(SYSCTL->PRTIMER & (1 << 4)))
+#define ST_ENABLE_CLOCK()                   (HWREG(SYSCTL_RCGCTIMER) |= (1 << 4))
+#define ST_WAIT_CLOCK()                     while (!(HWREG(SYSCTL_PRTIMER) & (1 << 4)))
 
 #elif TIVA_ST_TIMER_NUMBER == 5
 #define ST_HANDLER                          TIVA_GPT5A_HANDLER
 #define ST_NUMBER                           TIVA_GPT5A_NUMBER
-#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCTIMER |= (1 << 5))
-#define ST_WAIT_CLOCK()                     while (!(SYSCTL->PRTIMER & (1 << 5)))
+#define ST_ENABLE_CLOCK()                   (HWREG(SYSCTL_RCGCTIMER) |= (1 << 5))
+#define ST_WAIT_CLOCK()                     while (!(HWREG(SYSCTL_PRTIMER) & (1 << 5)))
 
 #else
 #error "TIVA_ST_USE_TIMER specifies an unsupported timer"
@@ -184,10 +184,10 @@ OSAL_IRQ_HANDLER(ST_HANDLER)
 
   OSAL_IRQ_PROLOGUE();
 
-  mis = TIVA_ST_TIM->MIS;
-  TIVA_ST_TIM->ICR = mis;
+  mis = HWREG(TIVA_ST_TIM + TIMER_O_MIS);
+  HWREG(TIVA_ST_TIM + TIMER_O_ICR) = mis;
 
-  if (mis & GPTM_IMR_TAMIM) {
+  if (mis & TIMER_IMR_TAMIM) {
     osalSysLockFromISR();
     osalOsTimerHandlerI();
     osalSysUnlockFromISR();
@@ -218,15 +218,17 @@ void st_lld_init(void)
   ST_WAIT_CLOCK();
 
   /* Initializing the counter in free running down mode.*/
-  TIVA_ST_TIM->CTL  = 0;
-  TIVA_ST_TIM->CFG  = GPTM_CFG_CFG_SPLIT;       /* Timer split mode */
-  TIVA_ST_TIM->TAMR = (GPTM_TAMR_TAMR_PERIODIC |/* Periodic mode */
-                       GPTM_TAMR_TAMIE |        /* Match interrupt enable */
-                       GPTM_TAMR_TASNAPS);      /* Snapshot mode */
-
-  TIVA_ST_TIM->TAPR = (TIVA_SYSCLK / OSAL_ST_FREQUENCY) - 1;
-  TIVA_ST_TIM->CTL  = (GPTM_CTL_TAEN |          /* Timer A enable */
-                       GPTM_CTL_TASTALL);       /* Timer A stall when paused */
+  HWREG(TIVA_ST_TIM + TIMER_O_CTL)  = 0;
+  HWREG(TIVA_ST_TIM + TIMER_O_CFG)  = TIMER_CFG_16_BIT; /* Timer split mode */
+  HWREG(TIVA_ST_TIM + TIMER_O_TAMR) = (
+      TIMER_TAMR_TAMR_PERIOD |  /* Periodic mode */
+      TIMER_TAMR_TAMIE |        /* Match interrupt enable */
+      TIMER_TAMR_TASNAPS);      /* Snapshot mode */
+
+  HWREG(TIVA_ST_TIM + TIMER_O_TAPR) = (TIVA_SYSCLK / OSAL_ST_FREQUENCY) - 1;
+  HWREG(TIVA_ST_TIM + TIMER_O_CTL)  = (
+      TIMER_CTL_TAEN |          /* Timer A enable */
+      TIMER_CTL_TASTALL);       /* Timer A stall when paused */
 
   /* IRQ enabled.*/
   nvicEnableVector(ST_NUMBER, TIVA_ST_IRQ_PRIORITY);
diff --git a/os/hal/ports/TIVA/LLD/hal_st_lld.h b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.h
index 35bf008..a0b4dfc 100644
--- a/os/hal/ports/TIVA/LLD/hal_st_lld.h
+++ b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.h
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -15,7 +15,7 @@
 */
 
 /**
- * @file    Tiva/LLD/st_lld.h
+ * @file    GPTM/hal_st_lld.h
  * @brief   ST Driver subsystem low level driver header.
  * @details This header is designed to be include-able without having to
  *          include other files from the HAL.
@@ -29,7 +29,6 @@
 
 #include "mcuconf.h"
 #include "tiva_registry.h"
-#include "tiva_gpt.h"
 
 /*===========================================================================*/
 /* Driver constants.                                                         */
@@ -82,37 +81,37 @@
 #if !TIVA_HAS_WGPT0
 #error "WGPT0 not present"
 #endif
-#define TIVA_ST_TIM                         WGPT0
+#define TIVA_ST_TIM                         WTIMER0_BASE
 
 #elif TIVA_ST_TIMER_NUMBER == 1
 #if !TIVA_HAS_WGPT1
 #error "WGPT1 not present"
 #endif
-#define TIVA_ST_TIM                         WGPT1
+#define TIVA_ST_TIM                         WTIMER1_BASE
 
 #elif TIVA_ST_TIMER_NUMBER == 2
 #if !TIVA_HAS_WGPT2
 #error "WGPT2 not present"
 #endif
-#define TIVA_ST_TIM                         WGPT2
+#define TIVA_ST_TIM                         WTIMER2_BASE
 
 #elif TIVA_ST_TIMER_NUMBER == 3
 #if !TIVA_HAS_WGPT3
 #error "WGPT3 not present"
 #endif
-#define TIVA_ST_TIM                         WGPT3
+#define TIVA_ST_TIM                         WTIMER3_BASE
 
 #elif TIVA_ST_TIMER_NUMBER == 4
 #if !TIVA_HAS_WGPT4
 #error "WGPT4 not present"
 #endif
-#define TIVA_ST_TIM                         WGPT4
+#define TIVA_ST_TIM                         WTIMER4_BASE
 
 #elif TIVA_ST_TIMER_NUMBER == 5
 #if !TIVA_HAS_WGPT5
 #error "WGPT5 not present"
 #endif
-#define TIVA_ST_TIM                         WGPT5
+#define TIVA_ST_TIM                         WTIMER5_BASE
 
 #else
 #error "TIVA_ST_USE_TIMER specifies an unsupported timer"
@@ -124,37 +123,37 @@
 #if !TIVA_HAS_GPT0
 #error "GPT0 not present"
 #endif
-#define TIVA_ST_TIM                         GPT0
+#define TIVA_ST_TIM                         TIMER0_BASE
 
 #elif TIVA_ST_TIMER_NUMBER == 1
 #if !TIVA_HAS_GPT1
 #error "GPT1 not present"
 #endif
-#define TIVA_ST_TIM                         GPT1
+#define TIVA_ST_TIM                         TIMER1_BASE
 
 #elif TIVA_ST_TIMER_NUMBER == 2
 #if !TIVA_HAS_GPT2
 #error "GPT2 not present"
 #endif
-#define TIVA_ST_TIM                         GPT2
+#define TIVA_ST_TIM                         TIMER2_BASE
 
 #elif TIVA_ST_TIMER_NUMBER == 3
 #if !TIVA_HAS_GPT3
 #error "GPT3 not present"
 #endif
-#define TIVA_ST_TIM                         GPT3
+#define TIVA_ST_TIM                         TIMER3_BASE
 
 #elif TIVA_ST_TIMER_NUMBER == 4
 #if !TIVA_HAS_GPT4
 #error "GPT4 not present"
 #endif
-#define TIVA_ST_TIM                         GPT4
+#define TIVA_ST_TIM                         TIMER4_BASE
 
 #elif TIVA_ST_TIMER_NUMBER == 5
 #if !TIVA_HAS_GPT5
 #error "GPT5 not present"
 #endif
-#define TIVA_ST_TIM                         GPT5
+#define TIVA_ST_TIM                         TIMER5_BASE
 
 #else
 #error "TIVA_ST_TIMER_NUMBER specifies an unsupported timer"
@@ -164,11 +163,6 @@
 #error "wrong value defined for TIVA_ST_USE_WIDE_TIMER"
 #endif
 
-#if OSAL_ST_MODE != OSAL_ST_MODE_NONE && \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_ST_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to ST"
-#endif
-
 /*===========================================================================*/
 /* Driver data structures and types.                                         */
 /*===========================================================================*/
@@ -202,7 +196,7 @@ extern "C" {
  */
 static inline systime_t st_lld_get_counter(void)
 {
-  return (systime_t) (((systime_t) 0xffffffff) - TIVA_ST_TIM->TAR);
+  return (systime_t) (((systime_t) 0xffffffff) - HWREG(TIVA_ST_TIM + TIMER_O_TAV));
 }
 
 /**
@@ -216,9 +210,9 @@ static inline systime_t st_lld_get_counter(void)
  */
 static inline void st_lld_start_alarm(systime_t time)
 {
-  TIVA_ST_TIM->TAMATCHR = (systime_t) (((systime_t) 0xffffffff) - time);
-  TIVA_ST_TIM->ICR = TIVA_ST_TIM->MIS;
-  TIVA_ST_TIM->IMR = GPTM_IMR_TAMIM;
+  HWREG(TIVA_ST_TIM + TIMER_O_TAMATCHR) = (systime_t) (((systime_t) 0xffffffff) - time);
+  HWREG(TIVA_ST_TIM + TIMER_O_ICR) = HWREG(TIVA_ST_TIM + TIMER_O_MIS);
+  HWREG(TIVA_ST_TIM + TIMER_O_IMR) = TIMER_IMR_TAMIM;
 }
 
 /**
@@ -228,7 +222,7 @@ static inline void st_lld_start_alarm(systime_t time)
  */
 static inline void st_lld_stop_alarm(void)
 {
-  TIVA_ST_TIM->IMR = 0;
+  HWREG(TIVA_ST_TIM + TIMER_O_IMR) = 0;
 }
 
 /**
@@ -240,7 +234,7 @@ static inline void st_lld_stop_alarm(void)
  */
 static inline void st_lld_set_alarm(systime_t time)
 {
-  TIVA_ST_TIM->TAMATCHR = (systime_t) (((systime_t) 0xffffffff) - time);
+  HWREG(TIVA_ST_TIM + TIMER_O_TAMATCHR) = (systime_t) (((systime_t) 0xffffffff) - time);
 }
 
 /**
@@ -252,7 +246,7 @@ static inline void st_lld_set_alarm(systime_t time)
  */
 static inline systime_t st_lld_get_alarm(void)
 {
-  return (systime_t) (((systime_t)0xffffffff) - TIVA_ST_TIM->TAMATCHR);
+  return (systime_t) (((systime_t)0xffffffff) - HWREG(TIVA_ST_TIM + TIMER_O_TAMATCHR));
 }
 
 /**
@@ -266,7 +260,7 @@ static inline systime_t st_lld_get_alarm(void)
  */
 static inline bool st_lld_is_alarm_active(void)
 {
-  return (bool) ((TIVA_ST_TIM->IMR & GPTM_IMR_TAMIM) !=0);
+  return (bool) ((HWREG(TIVA_ST_TIM + TIMER_O_IMR) & TIMER_IMR_TAMIM) !=0);
 }
 
 #endif /* HAL_ST_LLD_H */
diff --git a/os/hal/ports/TIVA/LLD/I2C/driver.mk b/os/hal/ports/TIVA/LLD/I2C/driver.mk
new file mode 100644
index 0000000..d327a19
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/I2C/driver.mk
@@ -0,0 +1,9 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/I2C
diff --git a/os/hal/ports/TIVA/LLD/hal_i2c_lld.c b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c
index 5d80633..7ba7bad 100644
--- a/os/hal/ports/TIVA/LLD/hal_i2c_lld.c
+++ b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -15,7 +15,7 @@
 */
 
 /**
- * @file    TIVA/LLD/i2c_lld.c
+ * @file    I2C/hal_i2c_lld.c
  * @brief   TM4C123x/TM4C129x I2C subsystem low level driver source.
  *
  * @addtogroup I2C
@@ -30,6 +30,33 @@
 /* Driver local definitions.                                                 */
 /*===========================================================================*/
 
+// interrupt states
+#define STATE_IDLE          0
+#define STATE_WRITE_NEXT    1
+#define STATE_WRITE_FINAL   2
+#define STATE_WAIT_ACK      3
+#define STATE_SEND_ACK      4
+#define STATE_READ_ONE      5
+#define STATE_READ_FIRST    6
+#define STATE_READ_NEXT     7
+#define STATE_READ_FINAL    8
+#define STATE_READ_WAIT     9
+
+#define TIVA_I2C_SIGNLE_SEND                (I2C_MCS_RUN | I2C_MCS_START | I2C_MCS_STOP)
+#define TIVA_I2C_BURST_SEND_START           (I2C_MCS_RUN | I2C_MCS_START)
+#define TIVA_I2C_BURST_SEND_CONTINUE        (I2C_MCS_RUN)
+#define TIVA_I2C_BURST_SEND_FINISH          (I2C_MCS_RUN | I2C_MCS_STOP)
+#define TIVA_I2C_BURST_SEND_STOP            (I2C_MCS_STOP)
+#define TIVA_I2C_BURST_SEND_ERROR_STOP      (I2C_MCS_STOP)
+
+#define TIVA_I2C_SINGLE_RECEIVE             (I2C_MCS_RUN | I2C_MCS_START | I2C_MCS_STOP)
+#define TIVA_I2C_BURST_RECEIVE_START        (I2C_MCS_RUN | I2C_MCS_START | I2C_MCS_ACK)
+#define TIVA_I2C_BURST_RECEIVE_CONTINUE     (I2C_MCS_RUN | I2C_MCS_ACK)
+#define TIVA_I2C_BURST_RECEIVE_FINISH       (I2C_MCS_RUN | I2C_MCS_STOP)
+#define TIVA_I2C_BURST_RECEIVE_ERROR_STOP   (I2C_MCS_STOP)
+
+#define MTPR_VALUE          ((TIVA_SYSCLK/(2*(6+4)*i2cp->config->clock_speed))-1)
+
 /*===========================================================================*/
 /* Driver constants.                                                         */
 /*===========================================================================*/
@@ -125,19 +152,19 @@ I2CDriver I2CD10;
  */
 static void i2c_lld_serve_interrupt(I2CDriver *i2cp)
 {
-  I2C_TypeDef *dp = i2cp->i2c;
+  uint32_t i2c = i2cp->i2c;
   uint32_t status;
 
   // clear MIS bit in MICR by writing 1
-  dp->MICR = 1;
+  HWREG(i2c + I2C_O_MICR) = 1;
 
   // read interrupt status
-  status = dp->MCS;
+  status = HWREG(i2c + I2C_O_MCS);
 
-  if (status & TIVA_MCS_ERROR) {
+  if (status & I2C_MCS_ERROR) {
     i2cp->errors |= I2C_BUS_ERROR;
   }
-  if (status & TIVA_MCS_ARBLST) {
+  if (status & I2C_MCS_ARBLST) {
     i2cp->errors |= I2C_ARBITRATION_LOST;
   }
 
@@ -152,11 +179,11 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp)
         if (i2cp->txbytes == 1) {
           i2cp->intstate = STATE_WRITE_FINAL;
         }
-        dp->MDR = *(i2cp->txbuf);
+        HWREG(i2c + I2C_O_MDR) = *(i2cp->txbuf);
         i2cp->txbuf++;
         i2cp->txbytes--;
         // start transmission
-        dp->MCS = TIVA_I2C_BURST_SEND_CONTINUE;
+        HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_SEND_CONTINUE;
         break;
       }
       case STATE_WRITE_FINAL: {
@@ -169,12 +196,12 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp)
         else {
           i2cp->intstate = STATE_READ_FIRST;
         }
-        dp->MDR = *(i2cp->txbuf);
+        HWREG(i2c + I2C_O_MDR) = *(i2cp->txbuf);
         i2cp->txbuf++;
         // txbytes - 1
         i2cp->txbytes--;
         // start transmission
-        dp->MCS = TIVA_I2C_BURST_SEND_FINISH;
+        HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_SEND_FINISH;
         break;
       }
       case STATE_WAIT_ACK: {
@@ -189,10 +216,10 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp)
          i2cp->addr |= 1;
 
          // set slave address
-         dp->MSA = i2cp->addr;
-          i2cp->rxbytes--;
+         HWREG(i2c + I2C_O_MSA) = i2cp->addr;
+         i2cp->rxbytes--;
          //start receiving
-         dp->MCS = TIVA_I2C_SINGLE_RECEIVE;
+         HWREG(i2c + I2C_O_MCS) = TIVA_I2C_SINGLE_RECEIVE;
 
         break;
       }
@@ -208,10 +235,10 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp)
          i2cp->addr |= 1;
 
          // set slave address
-         dp->MSA = i2cp->addr;
-          i2cp->rxbytes--;
+         HWREG(i2c + I2C_O_MSA) = i2cp->addr;
+         i2cp->rxbytes--;
          //start receiving
-         dp->MCS = TIVA_I2C_BURST_RECEIVE_START;
+         HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_RECEIVE_START;
 
         break;
       }
@@ -219,27 +246,27 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp)
         if(i2cp->rxbytes == 2) {
           i2cp->intstate = STATE_READ_FINAL;
         }
-        *(i2cp->rxbuf) = dp->MDR;
+        *(i2cp->rxbuf) = HWREG(i2c + I2C_O_MDR);
         i2cp->rxbuf++;
         i2cp->rxbytes--;
         //start receiving
-        dp->MCS = TIVA_I2C_BURST_RECEIVE_CONTINUE;
+        HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_RECEIVE_CONTINUE;
 
         break;
       }
       case STATE_READ_FINAL: {
         i2cp->intstate = STATE_READ_WAIT;
-        *(i2cp->rxbuf) = dp->MDR;
+        *(i2cp->rxbuf) = HWREG(i2c + I2C_O_MDR);
         i2cp->rxbuf++;
-          i2cp->rxbytes--;
+        i2cp->rxbytes--;
         //start receiving
-        dp->MCS = TIVA_I2C_BURST_RECEIVE_FINISH;
+        HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_RECEIVE_FINISH;
 
         break;
       }
       case STATE_READ_WAIT: {
         i2cp->intstate = STATE_IDLE;
-        *(i2cp->rxbuf) = dp->MDR;
+        *(i2cp->rxbuf) = HWREG(i2c + I2C_O_MDR);
         i2cp->rxbuf++;
         _i2c_wakeup_isr(i2cp);
         break;
@@ -430,61 +457,61 @@ void i2c_lld_init(void) {
 #if TIVA_I2C_USE_I2C0
   i2cObjectInit(&I2CD1);
   I2CD1.thread = NULL;
-  I2CD1.i2c    = I2C0;
+  I2CD1.i2c    = I2C0_BASE;
 #endif /* TIVA_I2C_USE_I2C0 */
 
 #if TIVA_I2C_USE_I2C1
   i2cObjectInit(&I2CD2);
   I2CD2.thread = NULL;
-  I2CD2.i2c    = I2C1;
+  I2CD2.i2c    = I2C1_BASE;
 #endif /* TIVA_I2C_USE_I2C1 */
 
 #if TIVA_I2C_USE_I2C2
   i2cObjectInit(&I2CD3);
   I2CD3.thread = NULL;
-  I2CD3.i2c    = I2C2;
+  I2CD3.i2c    = I2C2_BASE;
 #endif /* TIVA_I2C_USE_I2C2 */
 
 #if TIVA_I2C_USE_I2C3
   i2cObjectInit(&I2CD4);
   I2CD4.thread = NULL;
-  I2CD4.i2c    = I2C3;
+  I2CD4.i2c    = I2C3_BASE;
 #endif /* TIVA_I2C_USE_I2C3 */
 
 #if TIVA_I2C_USE_I2C4
   i2cObjectInit(&I2CD5);
   I2CD5.thread = NULL;
-  I2CD5.i2c    = I2C4;
+  I2CD5.i2c    = I2C4_BASE;
 #endif /* TIVA_I2C_USE_I2C4 */
 
 #if TIVA_I2C_USE_I2C5
   i2cObjectInit(&I2CD6);
   I2CD6.thread = NULL;
-  I2CD6.i2c    = I2C5;
+  I2CD6.i2c    = I2C5_BASE;
 #endif /* TIVA_I2C_USE_I2C5 */
 
 #if TIVA_I2C_USE_I2C6
   i2cObjectInit(&I2CD7);
   I2CD7.thread = NULL;
-  I2CD7.i2c    = I2C6;
+  I2CD7.i2c    = I2C6_BASE;
 #endif /* TIVA_I2C_USE_I2C6 */
 
 #if TIVA_I2C_USE_I2C7
   i2cObjectInit(&I2CD8);
   I2CD8.thread = NULL;
-  I2CD8.i2c    = I2C7;
+  I2CD8.i2c    = I2C7_BASE;
 #endif /* TIVA_I2C_USE_I2C7 */
 
 #if TIVA_I2C_USE_I2C8
   i2cObjectInit(&I2CD9);
   I2CD9.thread = NULL;
-  I2CD9.i2c    = I2C8;
+  I2CD9.i2c    = I2C8_BASE;
 #endif /* TIVA_I2C_USE_I2C8 */
 
 #if TIVA_I2C_USE_I2C9
   i2cObjectInit(&I2CD10);
   I2CD10.thread = NULL;
-  I2CD10.i2c    = I2C9;
+  I2CD10.i2c    = I2C9_BASE;
 #endif /* TIVA_I2C_USE_I2C9 */
 }
 
@@ -497,83 +524,123 @@ void i2c_lld_init(void) {
  */
 void i2c_lld_start(I2CDriver *i2cp)
 {
-  I2C_TypeDef *dp = i2cp->i2c;
+  uint32_t i2c = i2cp->i2c;
 
   /* If in stopped state then enables the I2C clocks.*/
   if (i2cp->state == I2C_STOP) {
 #if TIVA_I2C_USE_I2C0
     if (&I2CD1 == i2cp) {
-      SYSCTL->RCGCI2C |= (1 << 0);
+      HWREG(SYSCTL_RCGCI2C) |= (1 << 0);
+
+      while (!(HWREG(SYSCTL_PRI2C) & (1 << 0)))
+        ;
+
       nvicEnableVector(TIVA_I2C0_NUMBER, TIVA_I2C_I2C0_IRQ_PRIORITY);
     }
 #endif /* TIVA_I2C_USE_I2C0 */
 
 #if TIVA_I2C_USE_I2C1
     if (&I2CD2 == i2cp) {
-      SYSCTL->RCGCI2C |= (1 << 1);
+      HWREG(SYSCTL_RCGCI2C) |= (1 << 1);
+
+      while (!(HWREG(SYSCTL_PRI2C) & (1 << 1)))
+        ;
+
       nvicEnableVector(TIVA_I2C1_NUMBER, TIVA_I2C_I2C1_IRQ_PRIORITY);
     }
 #endif /* TIVA_I2C_USE_I2C1 */
 
 #if TIVA_I2C_USE_I2C2
     if (&I2CD3 == i2cp) {
-      SYSCTL->RCGCI2C |= (1 << 2);
+      HWREG(SYSCTL_RCGCI2C) |= (1 << 2);
+
+      while (!(HWREG(SYSCTL_PRI2C) & (1 << 2)))
+        ;
+
       nvicEnableVector(TIVA_I2C2_NUMBER, TIVA_I2C_I2C2_IRQ_PRIORITY);
     }
 #endif /* TIVA_I2C_USE_I2C2 */
 
 #if TIVA_I2C_USE_I2C3
     if (&I2CD4 == i2cp) {
-      SYSCTL->RCGCI2C |= (1 << 3);
+      HWREG(SYSCTL_RCGCI2C) |= (1 << 3);
+
+      while (!(HWREG(SYSCTL_PRI2C) & (1 << 3)))
+        ;
+
       nvicEnableVector(TIVA_I2C3_NUMBER, TIVA_I2C_I2C3_IRQ_PRIORITY);
     }
 #endif /* TIVA_I2C_USE_I2C3 */
 
 #if TIVA_I2C_USE_I2C4
     if (&I2CD5 == i2cp) {
-      SYSCTL->RCGCI2C |= (1 << 4);
+      HWREG(SYSCTL_RCGCI2C) |= (1 << 4);
+
+      while (!(HWREG(SYSCTL_PRI2C) & (1 << 4)))
+        ;
+
       nvicEnableVector(TIVA_I2C4_NUMBER, TIVA_I2C_I2C4_IRQ_PRIORITY);
     }
 #endif /* TIVA_I2C_USE_I2C4 */
 
 #if TIVA_I2C_USE_I2C5
     if (&I2CD6 == i2cp) {
-      SYSCTL->RCGCI2C |= (1 << 5);
+      HWREG(SYSCTL_RCGCI2C) |= (1 << 5);
+
+      while (!(HWREG(SYSCTL_PRI2C) & (1 << 5)))
+        ;
+
       nvicEnableVector(TIVA_I2C5_NUMBER, TIVA_I2C_I2C5_IRQ_PRIORITY);
     }
 #endif /* TIVA_I2C_USE_I2C5 */
 
 #if TIVA_I2C_USE_I2C6
     if (&I2CD7 == i2cp) {
-      SYSCTL->RCGCI2C |= (1 << 6);
+      HWREG(SYSCTL_RCGCI2C) |= (1 << 6);
+
+      while (!(HWREG(SYSCTL_PRI2C) & (1 << 6)))
+        ;
+
       nvicEnableVector(TIVA_I2C6_NUMBER, TIVA_I2C_I2C6_IRQ_PRIORITY);
     }
 #endif /* TIVA_I2C_USE_I2C6 */
 
 #if TIVA_I2C_USE_I2C7
     if (&I2CD8 == i2cp) {
-      SYSCTL->RCGCI2C |= (1 << 7);
+      HWREG(SYSCTL_RCGCI2C) |= (1 << 7);
+
+      while (!(HWREG(SYSCTL_PRI2C) & (1 << 7)))
+        ;
+
       nvicEnableVector(TIVA_I2C7_NUMBER, TIVA_I2C_I2C7_IRQ_PRIORITY);
     }
 #endif /* TIVA_I2C_USE_I2C7 */
 
 #if TIVA_I2C_USE_I2C8
     if (&I2CD9 == i2cp) {
-      SYSCTL->RCGCI2C |= (1 << 8);
+      HWREG(SYSCTL_RCGCI2C) |= (1 << 8);
+
+      while (!(HWREG(SYSCTL_PRI2C) & (1 << 8)))
+        ;
+
       nvicEnableVector(TIVA_I2C8_NUMBER, TIVA_I2C_I2C8_IRQ_PRIORITY);
     }
 #endif /* TIVA_I2C_USE_I2C7 */
 
 #if TIVA_I2C_USE_I2C9
     if (&I2CD10 == i2cp) {
-      SYSCTL->RCGCI2C |= (1 << 9);
+      HWREG(SYSCTL_RCGCI2C) |= (1 << 9);
+
+      while (!(HWREG(SYSCTL_PRI2C) & (1 << 9)))
+        ;
+
       nvicEnableVector(TIVA_I2C9_NUMBER, TIVA_I2C_I2C9_IRQ_PRIORITY);
     }
 #endif /* TIVA_I2C_USE_I2C7 */
   }
 
-  dp->MCR = 0x10;
-  dp->MTPR = MTPR_VALUE;
+  HWREG(i2c + I2C_O_MCR) = 0x10;
+  HWREG(i2c + I2C_O_MTPR) = MTPR_VALUE;
 }
 
 /**
@@ -585,7 +652,8 @@ void i2c_lld_start(I2CDriver *i2cp)
  */
 void i2c_lld_stop(I2CDriver *i2cp)
 {
-  I2C_TypeDef *dp = i2cp->i2c;
+  uint32_t i2c = i2cp->i2c;
+
   /* If not in stopped state then disables the I2C clock.*/
   if (i2cp->state != I2C_STOP) {
 
@@ -595,76 +663,76 @@ void i2c_lld_stop(I2CDriver *i2cp)
 
 #if TIVA_I2C_USE_I2C0
     if (&I2CD1 == i2cp) {
-      SYSCTL->RCGCI2C &= ~(1 << 0);
+      HWREG(SYSCTL_RCGCI2C) &= ~(1 << 0);
       nvicDisableVector(TIVA_I2C0_NUMBER);
     }
 #endif /* TIVA_I2C_USE_I2C0 */
 
 #if TIVA_I2C_USE_I2C1
     if (&I2CD2 == i2cp) {
-      SYSCTL->RCGCI2C &= ~(1 << 1);
+      HWREG(SYSCTL_RCGCI2C) &= ~(1 << 1);
       nvicDisableVector(TIVA_I2C1_NUMBER);
     }
 #endif /* TIVA_I2C_USE_I2C1 */
 
 #if TIVA_I2C_USE_I2C2
     if (&I2CD3 == i2cp) {
-      SYSCTL->RCGCI2C &= ~(1 << 2);
+      HWREG(SYSCTL_RCGCI2C) &= ~(1 << 2);
       nvicDisableVector(TIVA_I2C2_NUMBER);
     }
 #endif /* TIVA_I2C_USE_I2C2 */
 
 #if TIVA_I2C_USE_I2C3
     if (&I2CD4 == i2cp) {
-      SYSCTL->RCGCI2C &= ~(1 << 3);
+      HWREG(SYSCTL_RCGCI2C) &= ~(1 << 3);
       nvicDisableVector(TIVA_I2C3_NUMBER);
     }
 #endif /* TIVA_I2C_USE_I2C3 */
 
 #if TIVA_I2C_USE_I2C4
     if (&I2CD5 == i2cp) {
-      SYSCTL->RCGCI2C &= ~(1 << 4);
+      HWREG(SYSCTL_RCGCI2C) &= ~(1 << 4);
       nvicDisableVector(TIVA_I2C4_NUMBER);
     }
 #endif /* TIVA_I2C_USE_I2C4 */
 
 #if TIVA_I2C_USE_I2C5
     if (&I2CD6 == i2cp) {
-      SYSCTL->RCGCI2C &= ~(1 << 5);
+      HWREG(SYSCTL_RCGCI2C) &= ~(1 << 5);
       nvicDisableVector(TIVA_I2C5_NUMBER);
     }
 #endif /* TIVA_I2C_USE_I2C5 */
 
 #if TIVA_I2C_USE_I2C6
     if (&I2CD7 == i2cp) {
-      SYSCTL->RCGCI2C &= ~(1 << 6);
+      HWREG(SYSCTL_RCGCI2C) &= ~(1 << 6);
       nvicDisableVector(TIVA_I2C6_NUMBER);
     }
 #endif /* TIVA_I2C_USE_I2C6 */
 
 #if TIVA_I2C_USE_I2C7
     if (&I2CD8 == i2cp) {
-      SYSCTL->RCGCI2C &= ~(1 << 7);
+      HWREG(SYSCTL_RCGCI2C) &= ~(1 << 7);
       nvicDisableVector(TIVA_I2C7_NUMBER);
     }
 #endif /* TIVA_I2C_USE_I2C7 */
 
 #if TIVA_I2C_USE_I2C8
     if (&I2CD9 == i2cp) {
-      SYSCTL->RCGCI2C &= ~(1 << 8);
+      HWREG(SYSCTL_RCGCI2C) &= ~(1 << 8);
       nvicDisableVector(TIVA_I2C8_NUMBER);
     }
 #endif /* TIVA_I2C_USE_I2C8 */
 
 #if TIVA_I2C_USE_I2C9
     if (&I2CD10 == i2cp) {
-      SYSCTL->RCGCI2C &= ~(1 << 9);
+      HWREG(SYSCTL_RCGCI2C) &= ~(1 << 9);
       nvicDisableVector(TIVA_I2C9_NUMBER);
     }
 #endif /* TIVA_I2C_USE_I2C9 */
 
-  dp->MCR = 0;
-  dp->MTPR = 0;
+  HWREG(i2c + I2C_O_MCR) = 0;
+  HWREG(i2c + I2C_O_MTPR) = 0;
   }
 }
 
@@ -693,7 +761,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
                                      uint8_t *rxbuf, size_t rxbytes,
                                      systime_t timeout)
 {
-  I2C_TypeDef *dp = i2cp->i2c;
+  uint32_t i2c = i2cp->i2c;
   systime_t start, end;
 
   i2cp->rxbuf = rxbuf;
@@ -710,7 +778,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
 
   /* Calculating the time window for the timeout on the busy bus condition.*/
   start = osalOsGetSystemTimeX();
-  end = start + OSAL_MS2ST(TIVA_I2C_BUSY_TIMEOUT);
+  end = start + OSAL_MS2I(TIVA_I2C_BUSY_TIMEOUT);
 
   /* Waits until BUSY flag is reset or, alternatively, for a timeout
      condition.*/
@@ -719,22 +787,22 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
 
     /* If the bus is not busy then the operation can continue, note, the
        loop is exited in the locked state.*/
-    if ((dp->MCS & TIVA_MCS_BUSY) == 0)
+    if ((HWREG(i2c + I2C_O_MCS) & I2C_MCS_BUSY) == 0)
       break;
 
     /* If the system time went outside the allowed window then a timeout
        condition is returned.*/
-    if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end))
+    if (!osalTimeIsInRangeX(osalOsGetSystemTimeX(), start, end))
       return MSG_TIMEOUT;
 
     osalSysUnlock();
   }
 
   /* set slave address */
-  dp->MSA = addr;
+  HWREG(i2c + I2C_O_MSA) = addr;
 
   /* Starts the operation.*/
-  dp->MCS = TIVA_I2C_SINGLE_RECEIVE;
+  HWREG(i2c + I2C_O_MCS) = TIVA_I2C_SINGLE_RECEIVE;
 
   /* Waits for the operation completion or a timeout.*/
   return osalThreadSuspendTimeoutS(&i2cp->thread, timeout);
@@ -768,7 +836,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
                                       uint8_t *rxbuf, size_t rxbytes,
                                       systime_t timeout)
 {
-  I2C_TypeDef *dp = i2cp->i2c;
+  uint32_t i2c = i2cp->i2c;
   systime_t start, end;
 
   i2cp->rxbuf = rxbuf;
@@ -784,7 +852,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
 
   /* Calculating the time window for the timeout on the busy bus condition.*/
   start = osalOsGetSystemTimeX();
-  end = start + OSAL_MS2ST(TIVA_I2C_BUSY_TIMEOUT);
+  end = start + OSAL_MS2I(TIVA_I2C_BUSY_TIMEOUT);
 
   /* Waits until BUSY flag is reset or, alternatively, for a timeout
      condition.*/
@@ -793,12 +861,13 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
 
     /* If the bus is not busy then the operation can continue, note, the
        loop is exited in the locked state.*/
-    if ((dp->MCS & TIVA_MCS_BUSY) == 0)
+    if ((HWREG(i2c + I2C_O_MCS) & I2C_MCS_BUSY) == 0)
       break;
 
     /* If the system time went outside the allowed window then a timeout
        condition is returned.*/
-    if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end))
+    if (!osalTimeIsInRangeX(osalOsGetSystemTimeX(), start, end))
+
       return MSG_TIMEOUT;
 
     osalSysUnlock();
@@ -808,13 +877,13 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
   i2cp->addr = addr << 1 | 0;
 
   /* set slave address */
-  dp->MSA = i2cp->addr;
+  HWREG(i2c + I2C_O_MSA) = i2cp->addr;
 
   /* enable interrupts */
-  dp->MIMR = TIVA_MIMR_IM;
+  HWREG(i2c + I2C_O_MIMR) = I2C_MIMR_IM;
 
   /* put data in register */
-  dp->MDR = *(i2cp->txbuf);
+  HWREG(i2c + I2C_O_MDR) = *(i2cp->txbuf);
 
   /* check if 1 or more bytes */
   if (i2cp->txbytes == 1) {
@@ -827,7 +896,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
       i2cp->intstate = STATE_READ_FIRST;
     }
     // single byte send
-    dp->MCS = TIVA_I2C_SIGNLE_SEND;
+    HWREG(i2c + I2C_O_MCS) = TIVA_I2C_SIGNLE_SEND;
   }
   else {
     if (i2cp->txbytes == 2) {
@@ -839,7 +908,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
       i2cp->intstate = STATE_WRITE_NEXT;
     }
     // multiple bytes start send
-    dp->MCS = TIVA_I2C_BURST_SEND_START;
+    HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_SEND_START;
   }
 
   i2cp->txbuf++;
diff --git a/os/hal/ports/TIVA/LLD/hal_i2c_lld.h b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.h
index 460d231..66669f1 100644
--- a/os/hal/ports/TIVA/LLD/hal_i2c_lld.h
+++ b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.h
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -15,7 +15,7 @@
 */
 
 /**
- * @file    TIVA/LLD/i2c_lld.h
+ * @file    I2C/hal_i2c_lld.h
  * @brief   TM4C123x/TM4C129x I2C subsystem low level driver header.
  *
  * @addtogroup I2C
@@ -31,80 +31,6 @@
 /* Driver constants.                                                         */
 /*===========================================================================*/
 
-#define MTPR_VALUE          ((TIVA_SYSCLK/(2*(6+4)*i2cp->config->clock_speed))-1)
-
-#define TIVA_MSA_RS         (1 << 0)
-#define TIVA_MSA_SA         (127 << 1)
-
-#define TIVA_MCS_BUSY       (1 << 0)
-#define TIVA_MCS_ERROR      (1 << 1)
-#define TIVA_MCS_ADRACK     (1 << 2)
-#define TIVA_MCS_DATACK     (1 << 3)
-#define TIVA_MCS_ARBLST     (1 << 4)
-#define TIVA_MCS_IDLE       (1 << 5)
-#define TIVA_MCS_BUSBSY     (1 << 6)
-#define TIVA_MCS_CLKTO      (1 << 7)
-
-#define TIVA_MCS_RUN        (1 << 0)
-#define TIVA_MCS_START      (1 << 1)
-#define TIVA_MCS_STOP       (1 << 2)
-#define TIVA_MCS_ACK        (1 << 3)
-#define TIVA_MCS_HS         (1 << 4)
-
-#define TIVA_I2C_SIGNLE_SEND                (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_STOP)
-#define TIVA_I2C_BURST_SEND_START           (TIVA_MCS_RUN | TIVA_MCS_START)
-#define TIVA_I2C_BURST_SEND_CONTINUE        (TIVA_MCS_RUN)
-#define TIVA_I2C_BURST_SEND_FINISH          (TIVA_MCS_RUN | TIVA_MCS_STOP)
-#define TIVA_I2C_BURST_SEND_STOP            (TIVA_MCS_STOP)
-#define TIVA_I2C_BURST_SEND_ERROR_STOP      (TIVA_MCS_STOP)
-
-#define TIVA_I2C_SINGLE_RECEIVE             (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_STOP)
-#define TIVA_I2C_BURST_RECEIVE_START        (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_ACK)
-#define TIVA_I2C_BURST_RECEIVE_CONTINUE     (TIVA_MCS_RUN | TIVA_MCS_ACK)
-#define TIVA_I2C_BURST_RECEIVE_FINISH       (TIVA_MCS_RUN | TIVA_MCS_STOP)
-#define TIVA_I2C_BURST_RECEIVE_ERROR_STOP   (TIVA_MCS_STOP)
-
-#define TIVA_MDR_DATA       (255 << 0)
-
-#define TIVA_MTPR_TPR       (127 << 0)
-#define TIVA_MTPR_HS        (1 << 7)
-
-#define TIVA_MIMR_IM        (1 << 0)
-#define TIVA_MIMR_CLKIM     (1 << 1)
-
-#define TIVA_MRIS_RIS       (1 << 0)
-#define TIVA_MRIS_CLKRIS    (1 << 1)
-
-#define TIVA_MMIS_MIS       (1 << 0)
-#define TIVA_MMIS_CLKMIS    (1 << 1)
-
-#define TIVA_MICR_IC        (1 << 0)
-#define TIVA_MICR_CLKIC     (1 << 1)
-
-#define TIVA_MCR_LPBK       (1 << 0)
-#define TIVA_MCR_MFE        (1 << 4)
-#define TIVA_MCR_SFE        (1 << 5)
-#define TIVA_MCR_GFE        (1 << 6)
-
-#define TIVA_MCLKOCNT_CNTL  (255 << 0)
-
-#define TIVA_MBMON_SCL      (1 << 0)
-#define TIVA_MBMON_SDA      (1 << 1)
-
-#define TIVA_MCR2_GFPW      (7 << 4)
-
-// interrupt states
-#define STATE_IDLE          0
-#define STATE_WRITE_NEXT    1
-#define STATE_WRITE_FINAL   2
-#define STATE_WAIT_ACK      3
-#define STATE_SEND_ACK      4
-#define STATE_READ_ONE      5
-#define STATE_READ_FIRST    6
-#define STATE_READ_NEXT     7
-#define STATE_READ_FINAL    8
-#define STATE_READ_WAIT     9
-
 /*===========================================================================*/
 /* Driver pre-compile time settings.                                         */
 /*===========================================================================*/
@@ -440,7 +366,7 @@ struct I2CDriver {
   /**
    * @brief     Pointer to the I2Cx registers block.
    */
-  I2C_TypeDef               *i2c;
+  uint32_t                  i2c;
 };
 
 /*===========================================================================*/
diff --git a/os/hal/ports/TIVA/LLD/MAC/driver.mk b/os/hal/ports/TIVA/LLD/MAC/driver.mk
new file mode 100644
index 0000000..3847ce8
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/MAC/driver.mk
@@ -0,0 +1,9 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_MAC TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/MAC
diff --git a/os/hal/ports/TIVA/LLD/hal_mac_lld.c b/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c
index 04177b6..1f1f220 100644
--- a/os/hal/ports/TIVA/LLD/hal_mac_lld.c
+++ b/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -15,7 +15,7 @@
 */
 
 /**
- * @file    TIVA/mac_lld.c
+ * @file    MAC/hal_mac_lld.c
  * @brief   MAC Driver subsystem low level driver source.
  *
  * @addtogroup MAC
@@ -89,10 +89,10 @@ static uint32_t tb[TIVA_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE];
  */
 static void mii_write(MACDriver *macp, uint32_t reg, uint32_t value)
 {
-  ETH->MIIDATA = value;
-  ETH->MIIADDR = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIW | EMAC_MIIADDR_MIIB;
+  HWREG(EMAC0_BASE + EMAC_O_MIIDATA) = value;
+  HWREG(EMAC0_BASE + EMAC_O_MIIADDR) = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIW | EMAC_MIIADDR_MIIB;
 
-  while ((ETH->MIIADDR & EMAC_MIIADDR_MIIB) != 0)
+  while ((HWREG(EMAC0_BASE + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) != 0)
     ;
 }
 
@@ -126,12 +126,12 @@ static void mii_write_extended(MACDriver *macp, uint32_t reg, uint32_t value)
  */
 static uint32_t mii_read(MACDriver *macp, uint32_t reg)
 {
-  ETH->MIIADDR = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIB;
+  HWREG(EMAC0_BASE + EMAC_O_MIIADDR) = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIB;
 
-  while ((ETH->MIIADDR & EMAC_MIIADDR_MIIB) != 0)
+  while ((HWREG(EMAC0_BASE + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) != 0)
     ;
 
-  return ETH->MIIDATA;
+  return HWREG(EMAC0_BASE + EMAC_O_MIIDATA);
 }
 
 /**
@@ -171,7 +171,7 @@ static void mii_find_phy(MACDriver *macp)
 #endif
     for (i = 0; i < 31; i++) {
       macp->phyaddr = i << 11;
-      ETH->MIIDATA = (i << 6) | MACMIIADDR_CR;
+      HWREG(EMAC0_BASE + EMAC_O_MIIDATA) = (i << 6) | MACMIIADDR_CR;
       if ((mii_read(macp, TIVA_ID1) == (BOARD_PHY_ID >> 16)) &&
           ((mii_read(macp, TIVA_ID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) {
         return;
@@ -196,20 +196,20 @@ static void mac_lld_set_address(const uint8_t *p)
 {
   /* MAC address configuration, only a single address comparator is used,
      hash table not used.*/
-  ETH->ADDR0H   = ((uint32_t)p[5] << 8) |
+  HWREG(EMAC0_BASE + EMAC_O_ADDR0H)   = ((uint32_t)p[5] << 8) |
                   ((uint32_t)p[4] << 0);
-  ETH->ADDR0L   = ((uint32_t)p[3] << 24) |
+  HWREG(EMAC0_BASE + EMAC_O_ADDR0L)   = ((uint32_t)p[3] << 24) |
                   ((uint32_t)p[2] << 16) |
                   ((uint32_t)p[1] << 8) |
                   ((uint32_t)p[0] << 0);
-  ETH->ADDR1H   = 0x0000FFFF;
-  ETH->ADDR1L   = 0xFFFFFFFF;
-  ETH->ADDR2H   = 0x0000FFFF;
-  ETH->ADDR2L   = 0xFFFFFFFF;
-  ETH->ADDR3H   = 0x0000FFFF;
-  ETH->ADDR3L   = 0xFFFFFFFF;
-  ETH->HASHTBLH = 0;
-  ETH->HASHTBLL = 0;
+  HWREG(EMAC0_BASE + EMAC_O_ADDR1H)   = 0x0000FFFF;
+  HWREG(EMAC0_BASE + EMAC_O_ADDR1L)   = 0xFFFFFFFF;
+  HWREG(EMAC0_BASE + EMAC_O_ADDR2H)   = 0x0000FFFF;
+  HWREG(EMAC0_BASE + EMAC_O_ADDR2L)   = 0xFFFFFFFF;
+  HWREG(EMAC0_BASE + EMAC_O_ADDR3H)   = 0x0000FFFF;
+  HWREG(EMAC0_BASE + EMAC_O_ADDR3L)   = 0xFFFFFFFF;
+  HWREG(EMAC0_BASE + EMAC_O_HASHTBLH) = 0;
+  HWREG(EMAC0_BASE + EMAC_O_HASHTBLL) = 0;
 }
 
 /*===========================================================================*/
@@ -222,8 +222,8 @@ CH_IRQ_HANDLER(TIVA_MAC_HANDLER)
 
   CH_IRQ_PROLOGUE();
 
-  dmaris = ETH->DMARIS;
-  ETH->DMARIS = dmaris & 0x0001FFFF; /* Clear status bits.*/
+  dmaris = HWREG(EMAC0_BASE + EMAC_O_DMARIS);
+  HWREG(EMAC0_BASE + EMAC_O_DMARIS) = dmaris & 0x0001FFFF; /* Clear status bits.*/
 
   if (dmaris & (1 << 6)) {
     /* Data Received.*/
@@ -275,26 +275,26 @@ void mac_lld_init(void)
   }
 
   /* Enable MAC clock */
-  SYSCTL->RCGCEMAC = 1;
-  while (SYSCTL->PREMAC != 0x01)
+  HWREG(SYSCTL_RCGCEMAC) = 1;
+  while (HWREG(SYSCTL_PREMAC) != 0x01)
     ;
 
   /* Set PHYHOLD bit */
-  ETH->PC |= 1;
+  HWREG(EMAC0_BASE + EMAC_O_PC) |= 1;
 
   /* Enable PHY clock */
-  SYSCTL->RCGCEPHY = 1;
-  while (SYSCTL->PREPHY != 0x01)
+  HWREG(SYSCTL_RCGCEPHY) = 1;
+  while (HWREG(SYSCTL_PREPHY) != 0x01)
     ;
 
   /* Enable power to PHY */
-  SYSCTL->PCEPHY |= 1;
-  while (SYSCTL->PREPHY != 0x01)
+  HWREG(SYSCTL_PCEPHY) |= 1;
+  while (HWREG(SYSCTL_PREPHY) != 0x01)
     ;
 #if BOARD_PHY_RMII
-  ETH->PC = EMAC_PHY_CONFIG | (0x04 << 28);
+  HWREG(EMAC0_BASE + EMAC_O_PC) = EMAC_PHY_CONFIG | (0x04 << 28);
 #else
-  ETH->PC = EMAC_PHY_CONFIG;
+  HWREG(EMAC0_BASE + EMAC_O_PC) = EMAC_PHY_CONFIG;
 #endif
 
   /*
@@ -310,12 +310,12 @@ void mac_lld_init(void)
   /* Set done bit after writing EMACPC register */
   mii_write(&ETHD1, TIVA_CFG1, (1 << 15) | mii_read(&ETHD1, TIVA_CFG1));
 
-  while(ETH->DMABUSMOD & 1)
+  while(HWREG(EMAC0_BASE + EMAC_O_DMABUSMOD) & 1)
     ;
 
   /* Reset MAC */
-  ETH->DMABUSMOD |= 1;
-  while (ETH->DMABUSMOD & 1)
+  HWREG(EMAC0_BASE + EMAC_O_DMABUSMOD) |= 1;
+  while (HWREG(EMAC0_BASE + EMAC_O_DMABUSMOD) & 1)
     ;
 
   /* PHY address setup.*/
@@ -344,10 +344,10 @@ void mac_lld_init(void)
 #endif
 
   /* Disable MAC clock */
-  SYSCTL->RCGCEMAC = 0;
+  HWREG(SYSCTL_RCGCEMAC) = 0;
 
   /* Disable PHY clock */
-  SYSCTL->RCGCEPHY = 0;
+  HWREG(SYSCTL_RCGCEPHY) = 0;
 }
 
 /**
@@ -374,13 +374,13 @@ void mac_lld_start(MACDriver *macp)
   macp->txptr = (tiva_eth_tx_descriptor_t *)td;
 
   /* Enable MAC clock */
-  SYSCTL->RCGCEMAC = 1;
-  while (SYSCTL->PREMAC != 0x01)
+  HWREG(SYSCTL_RCGCEMAC) = 1;
+  while (HWREG(SYSCTL_PREMAC) != 0x01)
     ;
 
   /* Enable PHY clock */
-  SYSCTL->RCGCEPHY = 1;
-  while (!SYSCTL->PREPHY)
+  HWREG(SYSCTL_RCGCEPHY) = 1;
+  while (!HWREG(SYSCTL_PREPHY))
     ;
 
   /* ISR vector enabled.*/
@@ -392,9 +392,9 @@ void mac_lld_start(MACDriver *macp)
 #endif
 
   /* MAC configuration.*/
-  ETH->FRAMEFLTR = 0;
-  ETH->FLOWCTL = 0;
-  ETH->VLANTG = 0;
+  HWREG(EMAC0_BASE + EMAC_O_FRAMEFLTR) = 0;
+  HWREG(EMAC0_BASE + EMAC_O_FLOWCTL) = 0;
+  HWREG(EMAC0_BASE + EMAC_O_VLANTG) = 0;
 
   /* MAC address setup.*/
   if (macp->config->mac_address == NULL)
@@ -406,30 +406,30 @@ void mac_lld_start(MACDriver *macp)
      Note that the complete setup of the MAC is performed when the link
      status is detected.*/
 #if TIVA_MAC_IP_CHECKSUM_OFFLOAD
-  ETH->CFG = (1 << 10) | (1 << 3) | (1 << 2);
+  HWREG(EMAC0_BASE + EMAC_O_CFG) = (1 << 10) | (1 << 3) | (1 << 2);
 #else
-  ETH->CFG =             (1 << 3) | (1 << 2);
+  HWREG(EMAC0_BASE + EMAC_O_CFG) =             (1 << 3) | (1 << 2);
 #endif
 
   /* DMA configuration:
      Descriptor chains pointers.*/
-  ETH->RXDLADDR = (uint32_t)rd;
-  ETH->TXDLADDR = (uint32_t)td;
+  HWREG(EMAC0_BASE + EMAC_O_RXDLADDR) = (uint32_t)rd;
+  HWREG(EMAC0_BASE + EMAC_O_TXDLADDR) = (uint32_t)td;
 
   /* Enabling required interrupt sources.*/
-  ETH->DMARIS &= 0xFFFF;
-  ETH->DMAIM = (1 << 16) | (1 << 6) | (1 << 0);
+  HWREG(EMAC0_BASE + EMAC_O_DMARIS) &= 0xFFFF;
+  HWREG(EMAC0_BASE + EMAC_O_DMAIM) = (1 << 16) | (1 << 6) | (1 << 0);
 
   /* DMA general settings.*/
-  ETH->DMABUSMOD = (1 << 25) | (1 << 17) | (1 << 8);
+  HWREG(EMAC0_BASE + EMAC_O_DMABUSMOD) = (1 << 25) | (1 << 17) | (1 << 8);
 
   /* Transmit FIFO flush.*/
-  ETH->DMAOPMODE = (1 << 20);
-  while (ETH->DMAOPMODE & (1 << 20))
+  HWREG(EMAC0_BASE + EMAC_O_DMAOPMODE) = (1 << 20);
+  while (HWREG(EMAC0_BASE + EMAC_O_DMAOPMODE) & (1 << 20))
     ;
 
   /* DMA final configuration and start.*/
-  ETH->DMAOPMODE = (1 << 26) | (1 << 25) | (1 << 21) |
+  HWREG(EMAC0_BASE + EMAC_O_DMAOPMODE) = (1 << 26) | (1 << 25) | (1 << 21) |
                         (1 << 13) | (1 << 1);
 }
 
@@ -449,16 +449,16 @@ void mac_lld_stop(MACDriver *macp)
 #endif
 
     /* MAC and DMA stopped.*/
-    ETH->CFG = 0;
-    ETH->DMAOPMODE = 0;
-    ETH->DMAIM = 0;
-    ETH->DMARIS &= 0xFFFF;
+    HWREG(EMAC0_BASE + EMAC_O_CFG) = 0;
+    HWREG(EMAC0_BASE + EMAC_O_DMAOPMODE) = 0;
+    HWREG(EMAC0_BASE + EMAC_O_DMAIM) = 0;
+    HWREG(EMAC0_BASE + EMAC_O_DMARIS) &= 0xFFFF;
 
     /* MAC clocks stopped.*/
-    SYSCTL->RCGCEMAC = 0;
+    HWREG(SYSCTL_RCGCEMAC) = 0;
 
     /* PHY clock stopped.*/
-    SYSCTL->RCGCEPHY = 0;
+    HWREG(SYSCTL_RCGCEPHY) = 0;
 
     /* ISR vector disabled.*/
     nvicDisableVector(TIVA_MAC_NUMBER);
@@ -537,9 +537,9 @@ void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp)
   tdp->physdesc->locked = 0;
 
   /* If the DMA engine is stalled then a restart request is issued.*/
-  if ((ETH->DMARIS & (0x7 << 20)) == (6 << 20)) {
-    ETH->DMARIS   = (1 << 2);
-    ETH->TXPOLLD = 1; /* Any value is OK.*/
+  if ((HWREG(EMAC0_BASE + EMAC_O_DMARIS) & (0x7 << 20)) == (6 << 20)) {
+    HWREG(EMAC0_BASE + EMAC_O_DMARIS)   = (1 << 2);
+    HWREG(EMAC0_BASE + EMAC_O_TXPOLLD) = 1; /* Any value is OK.*/
   }
 
   osalSysUnlock();
@@ -616,9 +616,9 @@ void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp)
   rdp->physdesc->rdes0 = TIVA_RDES0_OWN;
 
   /* If the DMA engine is stalled then a restart request is issued.*/
-  if ((ETH->STATUS & (0xf << 17)) == (4 << 17)) {
-    ETH->DMARIS   = (1 << 7);
-    ETH->TXPOLLD = 1; /* Any value is OK.*/
+  if ((HWREG(EMAC0_BASE + EMAC_O_STATUS) & (0xf << 17)) == (4 << 17)) {
+    HWREG(EMAC0_BASE + EMAC_O_DMARIS)   = (1 << 7);
+    HWREG(EMAC0_BASE + EMAC_O_TXPOLLD) = 1; /* Any value is OK.*/
   }
 
   osalSysUnlock();
@@ -638,7 +638,7 @@ bool mac_lld_poll_link_status(MACDriver *macp)
 {
   uint32_t maccfg, bmsr, bmcr;
 
-  maccfg = ETH->CFG;
+  maccfg = HWREG(EMAC0_BASE + EMAC_O_CFG);
 
   /* PHY CR and SR registers read.*/
   (void)mii_read(macp, MII_BMSR);
@@ -688,7 +688,7 @@ bool mac_lld_poll_link_status(MACDriver *macp)
   }
 
   /* Changes the mode in the MAC.*/
-  ETH->CFG = maccfg;
+  HWREG(EMAC0_BASE + EMAC_O_CFG) = maccfg;
 
   /* Returns the link status.*/
   return macp->link_up = true;
diff --git a/os/hal/ports/TIVA/LLD/hal_mac_lld.h b/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.h
index 98036bb..407bf6c 100644
--- a/os/hal/ports/TIVA/LLD/hal_mac_lld.h
+++ b/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.h
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -15,7 +15,7 @@
 */
 
 /**
- * @file    TIVA/mac_lld.h
+ * @file    MAC/hal_mac_lld.h
  * @brief   MAC Driver subsystem low level driver header.
  *
  * @addtogroup MAC
diff --git a/os/hal/ports/TIVA/LLD/PWM/driver.mk b/os/hal/ports/TIVA/LLD/PWM/driver.mk
new file mode 100644
index 0000000..0c82d6f
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/PWM/driver.mk
@@ -0,0 +1,9 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/PWM
diff --git a/os/hal/ports/TIVA/LLD/hal_pwm_lld.c b/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c
index b223a9c..6f4535c 100644
--- a/os/hal/ports/TIVA/LLD/hal_pwm_lld.c
+++ b/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -15,7 +15,7 @@
 */
 
 /**
- * @file    TIVA/LLD/pwm_lld.c
+ * @file    PWM/hal_pwm_lld.c
  * @brief   TM4C123x/TM4C129x PWM subsystem low level driver.
  *
  * @addtogroup PWM
@@ -30,13 +30,6 @@
 /* Driver local definitions.                                                 */
 /*===========================================================================*/
 
-#define PWM_INT_CMPBD       (1 << 5)
-#define PWM_INT_CMPBU       (1 << 4)
-#define PWM_INT_CMPAD       (1 << 3)
-#define PWM_INT_CMPAU       (1 << 2)
-#define PWM_INT_CNTLOAD     (1 << 1)
-#define PWM_INT_CNTZERO     (1 << 0)
-
 /*===========================================================================*/
 /* Driver exported variables.                                                */
 /*===========================================================================*/
@@ -59,6 +52,8 @@ PWMDriver PWMD2;
 /* Driver local variables and types.                                         */
 /*===========================================================================*/
 
+static uint32_t pwm_generator_offsets[] = { PWM_GEN_0_OFFSET, PWM_GEN_1_OFFSET, PWM_GEN_2_OFFSET, PWM_GEN_3_OFFSET};
+
 /*===========================================================================*/
 /* Driver local functions.                                                   */
 /*===========================================================================*/
@@ -75,35 +70,36 @@ PWMDriver PWMD2;
 static void pwm_lld_serve_generator_interrupt (PWMDriver *pwmp, uint8_t i)
 {
   uint32_t isc;
+  uint32_t pwm = pwmp->pwm;
 
-  isc = pwmp->pwm->PWM[i].ISC;
-  pwmp->pwm->PWM[i].ISC = isc;
+  isc = HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_ISC);
+  HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_ISC) = isc;
 
-  if (((isc & PWM_INT_CMPAD) != 0) &&
+  if (((isc & PWM_X_ISC_INTCMPAD) != 0) &&
       (pwmp->config->channels[i * 2 + 0].callback != NULL)) {
     pwmp->config->channels[i * 2 + 0].callback(pwmp);
   }
 
-  if (((isc & PWM_INT_CMPAU) != 0) &&
+  if (((isc & PWM_X_ISC_INTCMPAU) != 0) &&
       (pwmp->config->channels[i * 2 + 0].callback != NULL)) {
     pwmp->config->channels[i * 2 + 0].callback(pwmp);
   }
 
-  if (((isc & PWM_INT_CMPBD) != 0) &&
+  if (((isc & PWM_X_ISC_INTCMPBD) != 0) &&
       (pwmp->config->channels[i * 2 + 1].callback != NULL)) {
     pwmp->config->channels[i * 2 + 1].callback(pwmp);
   }
 
-  if (((isc & PWM_INT_CMPBU) != 0) &&
+  if (((isc & PWM_X_ISC_INTCMPBU) != 0) &&
       (pwmp->config->channels[i * 2 + 1].callback != NULL)) {
     pwmp->config->channels[i * 2 + 1].callback(pwmp);
   }
 
-  if (((isc & PWM_INT_CNTLOAD) != 0) && (pwmp->config->callback != NULL)) {
+  if (((isc & PWM_X_ISC_INTCNTLOAD) != 0) && (pwmp->config->callback != NULL)) {
     pwmp->config->callback(pwmp);
   }
 
-  if (((isc & PWM_INT_CNTZERO) != 0) && (pwmp->config->callback != NULL)) {
+  if (((isc & PWM_X_ISC_INTCNTZERO) != 0) && (pwmp->config->callback != NULL)) {
     pwmp->config->callback(pwmp);
   }
 }
@@ -311,13 +307,13 @@ void pwm_lld_init(void)
 #if TIVA_PWM_USE_PWM0
   pwmObjectInit(&PWMD1);
   PWMD1.channels = PWM_CHANNELS;
-  PWMD1.pwm = PWM0;
+  PWMD1.pwm = PWM0_BASE;
 #endif
 
 #if TIVA_PWM_USE_PWM1
   pwmObjectInit(&PWMD2);
   PWMD2.channels = PWM_CHANNELS;
-  PWMD2.pwm = PWM1;
+  PWMD2.pwm = PWM1_BASE;
 #endif
 }
 
@@ -335,12 +331,17 @@ void pwm_lld_start(PWMDriver *pwmp)
   uint8_t i;
   uint32_t invert = 0;
   uint32_t enable = 0;
+  uint32_t pwm = pwmp->pwm;
 
   if (pwmp->state == PWM_STOP) {
     /* Clock activation.*/
 #if TIVA_PWM_USE_PWM0
     if (&PWMD1 == pwmp) {
-      SYSCTL->RCGCPWM |= (1 << 0);
+      HWREG(SYSCTL_RCGCPWM) |= (1 << 0);
+
+      while (!(HWREG(SYSCTL_PRPWM) & (1 << 0)))
+        ;
+
       nvicEnableVector(TIVA_PWM0FAULT_NUMBER,
                        TIVA_PWM_PWM0_FAULT_IRQ_PRIORITY);
       nvicEnableVector(TIVA_PWM0GEN0_NUMBER, TIVA_PWM_PWM0_0_IRQ_PRIORITY);
@@ -352,7 +353,11 @@ void pwm_lld_start(PWMDriver *pwmp)
 
 #if TIVA_PWM_USE_PWM1
     if (&PWMD2 == pwmp) {
-      SYSCTL->RCGCPWM |= (1 << 1);
+      HWREG(SYSCTL_RCGCPWM) |= (1 << 1);
+
+      while (!(HWREG(SYSCTL_PRPWM) & (1 << 1)))
+        ;
+
       nvicEnableVector(TIVA_PWM1FAULT_NUMBER,
                        TIVA_PWM_PWM1_FAULT_IRQ_PRIORITY);
       nvicEnableVector(TIVA_PWM1GEN0_NUMBER, TIVA_PWM_PWM1_0_IRQ_PRIORITY);
@@ -364,20 +369,20 @@ void pwm_lld_start(PWMDriver *pwmp)
   }
   else {
     /* Driver re-configuration scenario, it must be stopped first.*/
-    pwmp->pwm->PWM[0].CTL = 0;
-    pwmp->pwm->PWM[1].CTL = 0;
-    pwmp->pwm->PWM[2].CTL = 0;
-    pwmp->pwm->PWM[3].CTL = 0;
+    HWREG(pwm + PWM_O_0_CTL) = 0;
+    HWREG(pwm + PWM_O_1_CTL) = 0;
+    HWREG(pwm + PWM_O_2_CTL) = 0;
+    HWREG(pwm + PWM_O_3_CTL) = 0;
   }
 
   /* Timer configuration.*/
   for (i = 0; i  < (PWM_CHANNELS >> 1); i++) {
-    pwmp->pwm->PWM[i].CTL = 0;
-    pwmp->pwm->PWM[i].GEN[0] = 0x08C;
-    pwmp->pwm->PWM[i].GEN[1] = 0x80C;
-    pwmp->pwm->PWM[i].LOAD = (uint16_t)(pwmp->config->frequency - 1);
-    pwmp->pwm->PWM[i].CMP[0] = (uint16_t)(pwmp->period - 1);
-    pwmp->pwm->PWM[i].CMP[1] = (uint16_t)(pwmp->period - 1);
+    HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_CTL) = 0;
+    HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_GENA) = 0x08C;
+    HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_GENB) = 0x80C;
+    HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_LOAD) = (uint16_t)(pwmp->config->frequency - 1);
+    HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_CMPA) = (uint16_t)(pwmp->period - 1);
+    HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_CMPB) = (uint16_t)(pwmp->period - 1);
   }
 
   /* Output enables and polarities setup.*/
@@ -399,9 +404,9 @@ void pwm_lld_start(PWMDriver *pwmp)
     }
   }
 
-  pwmp->pwm->INVERT = invert;
-  pwmp->pwm->ENABLE = enable;
-  pwmp->pwm->ISC = 0xFFFFFFFF;
+  HWREG(pwm + PWM_O_INVERT) = invert;
+  HWREG(pwm + PWM_O_ENABLE) = enable;
+  HWREG(pwm + PWM_O_ISC) = 0xFFFFFFFF;
 }
 
 /**
@@ -413,12 +418,14 @@ void pwm_lld_start(PWMDriver *pwmp)
  */
 void pwm_lld_stop(PWMDriver *pwmp)
 {
+  uint32_t pwm = pwmp->pwm;
+
   /* If in ready state then disables the PWM clock.*/
   if (pwmp->state == PWM_READY) {
-    pwmp->pwm->PWM[0].CTL = 0;
-    pwmp->pwm->PWM[1].CTL = 0;
-    pwmp->pwm->PWM[2].CTL = 0;
-    pwmp->pwm->PWM[3].CTL = 0;
+    HWREG(pwm + PWM_O_0_CTL) = 0;
+    HWREG(pwm + PWM_O_1_CTL) = 0;
+    HWREG(pwm + PWM_O_2_CTL) = 0;
+    HWREG(pwm + PWM_O_3_CTL) = 0;
 
 #if TIVA_PWM_USE_PWM0
     if (&PWMD1 == pwmp) {
@@ -427,7 +434,7 @@ void pwm_lld_stop(PWMDriver *pwmp)
       nvicDisableVector(TIVA_PWM0GEN1_NUMBER);
       nvicDisableVector(TIVA_PWM0GEN2_NUMBER);
       nvicDisableVector(TIVA_PWM0GEN3_NUMBER);
-      SYSCTL->RCGCPWM &= ~(1 << 0);
+      HWREG(SYSCTL_RCGCPWM) &= ~(1 << 0);
     }
 #endif
 
@@ -438,7 +445,7 @@ void pwm_lld_stop(PWMDriver *pwmp)
       nvicDisableVector(TIVA_PWM1GEN1_NUMBER);
       nvicDisableVector(TIVA_PWM1GEN2_NUMBER);
       nvicDisableVector(TIVA_PWM1GEN3_NUMBER);
-      SYSCTL->RCGCPWM &= ~(1 << 1);
+      HWREG(SYSCTL_RCGCPWM) &= ~(1 << 1);
     }
 #endif
   }
@@ -461,9 +468,16 @@ void pwm_lld_enable_channel(PWMDriver *pwmp,
                             pwmchannel_t channel,
                             pwmcnt_t width)
 {
+  uint32_t pwm = pwmp->pwm;
+
   /* Changing channel duty cycle on the fly.*/
-  pwmp->pwm->PWM[channel >> 1].CMP[channel & 1] = width;
-  pwmp->pwm->PWM[channel >> 1].CTL |= (1 << 0);
+  if (channel & 1)
+    HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CMPB) = width;
+  else
+    HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CMPA) = width;
+
+
+  HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CTL) = (1 << 0);
 }
 
 /**
@@ -480,8 +494,14 @@ void pwm_lld_enable_channel(PWMDriver *pwmp,
  */
 void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel)
 {
-  pwmp->pwm->PWM[channel >> 1].CMP[channel & 1] = 0;
-  pwmp->pwm->PWM[channel >> 1].CTL &= ~(1 << 0);
+  uint32_t pwm = pwmp->pwm;
+
+  if (channel & 1)
+    HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CMPB) = 0;
+  else
+    HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CMPA) = 0;
+
+  HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CTL) = (1 << 0);
 }
 
 /**
@@ -497,18 +517,19 @@ void pwm_lld_enable_periodic_notification(PWMDriver *pwmp)
 {
   uint32_t inten;
   uint8_t i;
+  uint32_t pwm = pwmp->pwm;
 
   /* If the IRQ is not already enabled care must be taken to clear it,
      it is probably already pending because the timer is running.*/
   for(i = 0; i < (PWM_CHANNELS >> 1); i++) {
-    inten = pwmp->pwm->PWM[i].INTEN;
+    inten = HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_INTEN);
     if ((inten & 0x03) == 0) {
-      pwmp->pwm->PWM[i].INTEN |= 0x03;
-      pwmp->pwm->PWM[i].ISC = 0x03;
+      HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_INTEN) |= 0x03;
+      HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_ISC) = 0x03;
     }
   }
 
-  pwmp->pwm->INTEN = 0x3f;
+  HWREG(pwm + PWM_O_INTEN) = 0x3f;
 }
 
 /**
@@ -522,11 +543,14 @@ void pwm_lld_enable_periodic_notification(PWMDriver *pwmp)
  */
 void pwm_lld_disable_periodic_notification(PWMDriver *pwmp)
 {
-  pwmp->pwm->PWM[0].INTEN &= ~(0x03);
-  pwmp->pwm->PWM[1].INTEN &= ~(0x03);
-  pwmp->pwm->PWM[2].INTEN &= ~(0x03);
-  pwmp->pwm->PWM[3].INTEN &= ~(0x03);
-  pwmp->pwm->INTEN &= ~(0x3F);
+  uint32_t pwm = pwmp->pwm;
+
+  HWREG(pwm + PWM_O_0_INTEN) = ~(0x03);
+  HWREG(pwm + PWM_O_1_INTEN) = ~(0x03);
+  HWREG(pwm + PWM_O_2_INTEN) = ~(0x03);
+  HWREG(pwm + PWM_O_3_INTEN) = ~(0x03);
+
+  HWREG(pwm + PWM_O_INTEN) &= ~(0x3F);
 }
 
 /**
@@ -543,13 +567,14 @@ void pwm_lld_disable_periodic_notification(PWMDriver *pwmp)
 void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
                                          pwmchannel_t channel)
 {
-  uint32_t inten = pwmp->pwm->PWM[channel >> 1].INTEN;
+  uint32_t pwm = pwmp->pwm;
+  uint32_t inten = HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_ISC);
 
   /* If the IRQ is not already enabled care must be taken to clear it,
      it is probably already pending because the timer is running.*/
   if ((inten & (0x03 << (((channel & 1) * 2) + 2))) == 0) {
-    pwmp->pwm->PWM[channel >> 1].INTEN |= (0x03 << (((channel & 1) * 2) + 2));
-    pwmp->pwm->PWM[channel >> 1].ISC = (0x03 << (((channel & 1) * 2) + 2));
+    HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_INTEN) |= (0x03 << (((channel & 1) * 2) + 2));
+    HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_ISC) = (0x03 << (((channel & 1) * 2) + 2));
   }
 }
 
@@ -567,7 +592,9 @@ void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
 void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
                                           pwmchannel_t channel)
 {
-  pwmp->pwm->PWM[channel >> 1].INTEN &= ~(0x03 << (((channel & 1) * 2) + 2));
+  uint32_t pwm = pwmp->pwm;
+
+  HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_INTEN) = ~(0x03 << (((channel & 1) * 2) + 2));
 }
 
 #endif /* HAL_USE_PWM */
diff --git a/os/hal/ports/TIVA/LLD/hal_pwm_lld.h b/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.h
index ac64fe1..3fca631 100644
--- a/os/hal/ports/TIVA/LLD/hal_pwm_lld.h
+++ b/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.h
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -15,7 +15,7 @@
 */
 
 /**
- * @file    TIVA/LLD/pwm_lld.c
+ * @file    PWM/hal_pwm_lld.c
  * @brief   TM4C123x/TM4C129x PWM subsystem low level driver header.
  *
  * @addtogroup PWM
@@ -304,7 +304,7 @@ struct PWMDriver {
   /**
    * @brief Pointer to the PWMx registers block.
    */
-  PWM_TypeDef               *pwm;
+  uint32_t                  pwm;
 };
 
 /*===========================================================================*/
@@ -328,10 +328,10 @@ struct PWMDriver {
  * @notapi
  */
 #define pwm_lld_change_period(pwmp, period)                                  \
-  ((pwmp)->pwm->PWM[0].LOAD = (uint16_t)((period) - 1));                     \
-  ((pwmp)->pwm->PWM[1].LOAD = (uint16_t)((period) - 1));                     \
-  ((pwmp)->pwm->PWM[2].LOAD = (uint16_t)((period) - 1));                     \
-  ((pwmp)->pwm->PWM[3].LOAD = (uint16_t)((period) - 1))
+  HWREG((pwmp)->pwm + PWM_O_0_LOAD) = (uint16_t)((period) - 1);             \
+  HWREG((pwmp)->pwm + PWM_O_1_LOAD) = (uint16_t)((period) - 1);             \
+  HWREG((pwmp)->pwm + PWM_O_2_LOAD) = (uint16_t)((period) - 1);             \
+  HWREG((pwmp)->pwm + PWM_O_3_LOAD) = (uint16_t)((period) - 1)
 
 /*===========================================================================*/
 /* External declarations.                                                    */
diff --git a/os/hal/ports/TIVA/LLD/SSI/driver.mk b/os/hal/ports/TIVA/LLD/SSI/driver.mk
new file mode 100644
index 0000000..6f71487
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/SSI/driver.mk
@@ -0,0 +1,9 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/SSI
diff --git a/os/hal/ports/TIVA/LLD/hal_spi_lld.c b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c
index ded2b99..2255110 100644
--- a/os/hal/ports/TIVA/LLD/hal_spi_lld.c
+++ b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -15,7 +15,7 @@
 */
 
 /**
- * @file    TIVA/LLD/spi_lld.c
+ * @file    SSI/hal_spi_lld.c
  * @brief   TM4C123x/TM4C129x SPI subsystem low level driver.
  *
  * @addtogroup SPI
@@ -77,19 +77,19 @@ static uint16_t dummyrx;
  */
 static void spi_serve_interrupt(SPIDriver *spip)
 {
-  SSI_TypeDef *ssi = spip->ssi;
-  uint32_t mis = ssi->MIS;
-  uint32_t dmachis = UDMA->CHIS;
+  uint32_t ssi = spip->ssi;
+  uint32_t mis = HWREG(ssi + SSI_O_MIS);
+  uint32_t dmachis = HWREG(UDMA_CHIS);
 
   /* SPI error handling.*/
-  if ((mis & (TIVA_MIS_RORMIS | TIVA_MIS_RTMIS)) != 0) {
+  if ((mis & (SSI_MIS_RORMIS | SSI_MIS_RTMIS)) != 0) {
     TIVA_SPI_SSI_ERROR_HOOK(spip);
   }
 
-  if ( (dmachis & ( (1 << spip->dmarxnr) | (1 << spip->dmatxnr) ) ) ==
-      ( (1 << spip->dmarxnr) | (1 << spip->dmatxnr) ) ) {
+  if ((dmachis & ((1 << spip->dmarxnr) | (1 << spip->dmatxnr))) ==
+      (uint32_t)((1 << spip->dmarxnr) | (1 << spip->dmatxnr))) {
     /* Clear DMA Channel interrupts.*/
-    UDMA->CHIS = (1 << spip->dmarxnr) | (1 << spip->dmatxnr);
+    HWREG(UDMA_CHIS) = (1 << spip->dmarxnr) | (1 << spip->dmatxnr);
 
     /* Portable SPI ISR code defined in the high level driver, note, it is a
        macro.*/
@@ -180,7 +180,7 @@ void spi_lld_init(void)
 
 #if TIVA_SPI_USE_SSI0
   spiObjectInit(&SPID1);
-  SPID1.ssi = SSI0;
+  SPID1.ssi = SSI0_BASE;
   SPID1.dmarxnr = TIVA_SPI_SSI0_RX_UDMA_CHANNEL;
   SPID1.dmatxnr = TIVA_SPI_SSI0_TX_UDMA_CHANNEL;
   SPID1.rxchnmap = TIVA_SPI_SSI0_RX_UDMA_MAPPING;
@@ -189,7 +189,7 @@ void spi_lld_init(void)
 
 #if TIVA_SPI_USE_SSI1
   spiObjectInit(&SPID2);
-  SPID2.ssi = SSI1;
+  SPID2.ssi = SSI1_BASE;
   SPID2.dmarxnr = TIVA_SPI_SSI1_RX_UDMA_CHANNEL;
   SPID2.dmatxnr = TIVA_SPI_SSI1_TX_UDMA_CHANNEL;
   SPID2.rxchnmap = TIVA_SPI_SSI1_RX_UDMA_MAPPING;
@@ -198,7 +198,7 @@ void spi_lld_init(void)
 
 #if TIVA_SPI_USE_SSI2
   spiObjectInit(&SPID3);
-  SPID3.ssi = SSI2;
+  SPID3.ssi = SSI2_BASE;
   SPID3.dmarxnr = TIVA_SPI_SSI2_RX_UDMA_CHANNEL;
   SPID3.dmatxnr = TIVA_SPI_SSI2_TX_UDMA_CHANNEL;
   SPID3.rxchnmap = TIVA_SPI_SSI2_RX_UDMA_MAPPING;
@@ -207,7 +207,7 @@ void spi_lld_init(void)
 
 #if TIVA_SPI_USE_SSI3
   spiObjectInit(&SPID4);
-  SPID4.ssi = SSI3;
+  SPID4.ssi = SSI3_BASE;
   SPID4.dmarxnr = TIVA_SPI_SSI3_RX_UDMA_CHANNEL;
   SPID4.dmatxnr = TIVA_SPI_SSI3_TX_UDMA_CHANNEL;
   SPID4.rxchnmap = TIVA_SPI_SSI3_RX_UDMA_MAPPING;
@@ -235,8 +235,8 @@ void spi_lld_start(SPIDriver *spip)
       osalDbgAssert(!b, "channel already allocated");
 
       /* Enable SSI0 module.*/
-      SYSCTL->RCGCSSI |= (1 << 0);
-      while (!(SYSCTL->PRSSI & (1 << 0)))
+      HWREG(SYSCTL_RCGCSSI) |= (1 << 0);
+      while (!(HWREG(SYSCTL_PRSSI) & (1 << 0)))
         ;
 
       nvicEnableVector(TIVA_SSI0_NUMBER, TIVA_SPI_SSI0_IRQ_PRIORITY);
@@ -251,14 +251,14 @@ void spi_lld_start(SPIDriver *spip)
       osalDbgAssert(!b, "channel already allocated");
 
       /* Enable SSI0 module.*/
-      SYSCTL->RCGCSSI |= (1 << 1);
-      while (!(SYSCTL->PRSSI & (1 << 1)))
+      HWREG(SYSCTL_RCGCSSI) |= (1 << 1);
+      while (!(HWREG(SYSCTL_PRSSI) & (1 << 1)))
         ;
 
       nvicEnableVector(TIVA_SSI1_NUMBER, TIVA_SPI_SSI1_IRQ_PRIORITY);
     }
 #endif
-#if TIVASPI_USE_SSI2
+#if TIVA_SPI_USE_SSI2
     if (&SPID2 == spip) {
       bool b;
       b = udmaChannelAllocate(spip->dmarxnr);
@@ -267,8 +267,8 @@ void spi_lld_start(SPIDriver *spip)
       osalDbgAssert(!b, "channel already allocated");
 
       /* Enable SSI0 module.*/
-      SYSCTL->RCGCSSI |= (1 << 2);
-      while (!(SYSCTL->PRSSI & (1 << 2)))
+      HWREG(SYSCTL_RCGCSSI) |= (1 << 2);
+      while (!(HWREG(SYSCTL_PRSSI) & (1 << 2)))
         ;
 
       nvicEnableVector(TIVA_SSI2_NUMBER, TIVA_SPI_SSI2_IRQ_PRIORITY);
@@ -283,40 +283,40 @@ void spi_lld_start(SPIDriver *spip)
       osalDbgAssert(!b, "channel already allocated");
 
       /* Enable SSI0 module.*/
-      SYSCTL->RCGCSSI |= (1 << 3);
-      while (!(SYSCTL->PRSSI & (1 << 3)))
+      HWREG(SYSCTL_RCGCSSI) |= (1 << 3);
+      while (!(HWREG(SYSCTL_PRSSI) & (1 << 3)))
         ;
 
       nvicEnableVector(TIVA_SSI3_NUMBER, TIVA_SPI_SSI3_IRQ_PRIORITY);
     }
 #endif
 
-    UDMA->CHMAP[spip->dmarxnr / 8] |= (spip->rxchnmap << (spip->dmarxnr % 8));
-    UDMA->CHMAP[spip->dmatxnr / 8] |= (spip->txchnmap << (spip->dmatxnr % 8));
+    HWREG(UDMA_CHMAP0 + (spip->dmarxnr / 8) * 4) |= (spip->rxchnmap << (spip->dmarxnr % 8));
+    HWREG(UDMA_CHMAP0 + (spip->dmatxnr / 8) * 4) |= (spip->txchnmap << (spip->dmatxnr % 8));
   }
   /* Set master operation mode.*/
-  spip->ssi->CR1 = 0;
+  HWREG(spip->ssi + SSI_O_CR1) = 0;
 
   /* Clock configuration - System Clock.*/
-  spip->ssi->CC = 0;
+  HWREG(spip->ssi + SSI_O_CC) = 0;
 
   /* Clear pending interrupts.*/
-  spip->ssi->ICR = TIVA_ICR_RTIC | TIVA_ICR_RORIC;
+  HWREG(spip->ssi + SSI_O_ICR) = SSI_ICR_RTIC | SSI_ICR_RORIC;
 
   /* Enable Receive Time-Out and Receive Overrun Interrupts.*/
-  spip->ssi->IM = TIVA_IM_RTIM | TIVA_IM_RORIM;
+  HWREG(spip->ssi + SSI_O_IM) = SSI_IM_RTIM | SSI_IM_RORIM;
 
   /* Configure the clock prescale divisor.*/
-  spip->ssi->CPSR = spip->config->cpsr;
+  HWREG(spip->ssi + SSI_O_CPSR) = spip->config->cpsr;
 
   /* Serial clock rate, phase/polarity, data size, fixed SPI frame format.*/
-  spip->ssi->CR0 = (spip->config->cr0 & ~TIVA_CR0_FRF_MASK) | TIVA_CR0_FRF(0);
+  HWREG(spip->ssi + SSI_O_CR0) = (spip->config->cr0 & ~SSI_CR0_FRF_M) | SSI_CR0_FRF_MOTO;
 
   /* Enable SSI.*/
-  spip->ssi->CR1 |= TIVA_CR1_SSE;
+  HWREG(spip->ssi + SSI_O_CR1) |= SSI_CR1_SSE;
 
   /* Enable RX and TX DMA channels.*/
-  spip->ssi->DMACTL = (TIVA_DMACTL_TXDMAE | TIVA_DMACTL_RXDMAE);
+  HWREG(spip->ssi + SSI_O_DMACTL) = (SSI_DMACTL_TXDMAE | SSI_DMACTL_RXDMAE);
 }
 
 /**
@@ -329,9 +329,9 @@ void spi_lld_start(SPIDriver *spip)
 void spi_lld_stop(SPIDriver *spip)
 {
   if (spip->state != SPI_STOP) {
-    spip->ssi->CR1 = 0;
-    spip->ssi->CR0 = 0;
-    spip->ssi->CPSR = 0;
+    HWREG(spip->ssi + SSI_O_CR1) = 0;
+    HWREG(spip->ssi + SSI_O_CR0) = 0;
+    HWREG(spip->ssi + SSI_O_CPSR) = 0;
 
     udmaChannelRelease(spip->dmarxnr);
     udmaChannelRelease(spip->dmatxnr);
@@ -359,6 +359,7 @@ void spi_lld_stop(SPIDriver *spip)
   }
 }
 
+#if (SPI_SELECT_MODE == SPI_SELECT_MODE_LLD) || defined(__DOXYGEN__)
 /**
  * @brief   Asserts the slave select signal and prepares for transfers.
  *
@@ -368,7 +369,7 @@ void spi_lld_stop(SPIDriver *spip)
  */
 void spi_lld_select(SPIDriver *spip)
 {
-  palClearPad(spip->config->ssport, spip->config->sspad);
+  /* No implementation on Tiva.*/
 }
 
 /**
@@ -381,8 +382,9 @@ void spi_lld_select(SPIDriver *spip)
  */
 void spi_lld_unselect(SPIDriver *spip)
 {
-  palSetPad(spip->config->ssport, spip->config->sspad);
+  /* No implementation on Tiva.*/
 }
+#endif
 
 /**
  * @brief   Ignores data on the SPI bus.
@@ -399,20 +401,20 @@ void spi_lld_ignore(SPIDriver *spip, size_t n)
 {
   tiva_udma_table_entry_t *primary = udmaControlTable.primary;
 
-  if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) {
+  if ((spip->config->cr0 & SSI_CR0_DSS_M) < 8) {
     /* Configure for 8-bit transfers.*/
     primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx;
-    primary[spip->dmatxnr].dstendp = &spip->ssi->DR;
-    primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 |
-                                   UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 |
+    primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR);
+    primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE |
+                                   UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE |
                                    UDMA_CHCTL_ARBSIZE_4 |
                                    UDMA_CHCTL_XFERSIZE(n) |
                                    UDMA_CHCTL_XFERMODE_BASIC;
 
-    primary[spip->dmarxnr].srcendp = &spip->ssi->DR;
+    primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR);
     primary[spip->dmarxnr].dstendp = &dummyrx;
-    primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 |
-                                   UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 |
+    primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE |
+                                   UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE |
                                    UDMA_CHCTL_ARBSIZE_4 |
                                    UDMA_CHCTL_XFERSIZE(n) |
                                    UDMA_CHCTL_XFERMODE_BASIC;
@@ -420,17 +422,17 @@ void spi_lld_ignore(SPIDriver *spip, size_t n)
   else {
     /* Configure for 16-bit transfers.*/
     primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx;
-    primary[spip->dmatxnr].dstendp = &spip->ssi->DR;
-    primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 |
-                                   UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 |
+    primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR);
+    primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE |
+                                   UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE |
                                    UDMA_CHCTL_ARBSIZE_4 |
                                    UDMA_CHCTL_XFERSIZE(n) |
                                    UDMA_CHCTL_XFERMODE_BASIC;
 
-    primary[spip->dmarxnr].srcendp = &spip->ssi->DR;
+    primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR);
     primary[spip->dmarxnr].dstendp = &dummyrx;
-    primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 |
-                                   UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 |
+    primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE |
+                                   UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE |
                                    UDMA_CHCTL_ARBSIZE_4 |
                                    UDMA_CHCTL_XFERSIZE(n) |
                                    UDMA_CHCTL_XFERMODE_BASIC;
@@ -470,20 +472,20 @@ void spi_lld_exchange(SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf)
 {
   tiva_udma_table_entry_t *primary = udmaControlTable.primary;
 
-  if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) {
+  if ((spip->config->cr0 & SSI_CR0_DSS_M) < 8) {
     /* Configure for 8-bit transfers.*/
     primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+n-1;
-    primary[spip->dmatxnr].dstendp = &spip->ssi->DR;
-    primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 |
+    primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR);
+    primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE |
                                    UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_8 |
                                    UDMA_CHCTL_ARBSIZE_4 |
                                    UDMA_CHCTL_XFERSIZE(n) |
                                    UDMA_CHCTL_XFERMODE_BASIC;
 
-    primary[spip->dmarxnr].srcendp = &spip->ssi->DR;
+    primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR);
     primary[spip->dmarxnr].dstendp = rxbuf+n-1;
     primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 |
-                                   UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 |
+                                   UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE |
                                    UDMA_CHCTL_ARBSIZE_4 |
                                    UDMA_CHCTL_XFERSIZE(n) |
                                    UDMA_CHCTL_XFERMODE_BASIC;
@@ -491,17 +493,17 @@ void spi_lld_exchange(SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf)
   else {
     /* Configure for 16-bit transfers.*/
     primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+(n*2)-1;
-    primary[spip->dmatxnr].dstendp = &spip->ssi->DR;
-    primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 |
+    primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR);
+    primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE |
                                    UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_16 |
                                    UDMA_CHCTL_ARBSIZE_4 |
                                    UDMA_CHCTL_XFERSIZE(n) |
                                    UDMA_CHCTL_XFERMODE_BASIC;
 
-    primary[spip->dmarxnr].srcendp = &spip->ssi->DR;
+    primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR);
     primary[spip->dmarxnr].dstendp = rxbuf+(n*2)-1;
     primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_16 |
-                                   UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 |
+                                   UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE |
                                    UDMA_CHCTL_ARBSIZE_4 |
                                    UDMA_CHCTL_XFERSIZE(n) |
                                    UDMA_CHCTL_XFERMODE_BASIC;
@@ -539,20 +541,20 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf)
 {
   tiva_udma_table_entry_t *primary = udmaControlTable.primary;
 
-  if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) {
+  if ((spip->config->cr0 & SSI_CR0_DSS_M) < 8) {
     /* Configure for 8-bit transfers.*/
     primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+n-1;
-    primary[spip->dmatxnr].dstendp = &spip->ssi->DR;
-    primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 |
+    primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR);
+    primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE |
                                    UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_8 |
                                    UDMA_CHCTL_ARBSIZE_4 |
                                    UDMA_CHCTL_XFERSIZE(n) |
                                    UDMA_CHCTL_XFERMODE_BASIC;
 
-    primary[spip->dmarxnr].dstendp = &spip->ssi->DR;
+    primary[spip->dmarxnr].dstendp = (void *)(spip->ssi + SSI_O_DR);
     primary[spip->dmarxnr].srcendp = &dummyrx;
-    primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 |
-                                   UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 |
+    primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE |
+                                   UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE |
                                    UDMA_CHCTL_ARBSIZE_4 |
                                    UDMA_CHCTL_XFERSIZE(n) |
                                    UDMA_CHCTL_XFERMODE_BASIC;
@@ -560,17 +562,17 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf)
   else {
     /* Configure for 16-bit transfers.*/
     primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+(n*2)-1;
-    primary[spip->dmatxnr].dstendp = &spip->ssi->DR;
-    primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 |
+    primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR);
+    primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE |
                                    UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_16 |
                                    UDMA_CHCTL_ARBSIZE_4 |
                                    UDMA_CHCTL_XFERSIZE(n) |
                                    UDMA_CHCTL_XFERMODE_BASIC;
 
-    primary[spip->dmarxnr].dstendp = &spip->ssi->DR;
+    primary[spip->dmarxnr].dstendp = (void *)(spip->ssi + SSI_O_DR);
     primary[spip->dmarxnr].srcendp = &dummyrx;
-    primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 |
-                                   UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 |
+    primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE |
+                                   UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE |
                                    UDMA_CHCTL_ARBSIZE_4 |
                                    UDMA_CHCTL_XFERSIZE(n) |
                                    UDMA_CHCTL_XFERMODE_BASIC;
@@ -608,20 +610,20 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf)
 {
   tiva_udma_table_entry_t *primary = udmaControlTable.primary;
 
-  if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) {
+  if ((spip->config->cr0 & SSI_CR0_DSS_M) < 8) {
     /* Configure for 8-bit transfers.*/
     primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx;
-    primary[spip->dmatxnr].dstendp = &spip->ssi->DR;
-    primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 |
-                                   UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 |
+    primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR);
+    primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE |
+                                   UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE |
                                    UDMA_CHCTL_ARBSIZE_4 |
                                    UDMA_CHCTL_XFERSIZE(n) |
                                    UDMA_CHCTL_XFERMODE_BASIC;
 
-    primary[spip->dmarxnr].srcendp = &spip->ssi->DR;
+    primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR);
     primary[spip->dmarxnr].dstendp = rxbuf+n-1;
     primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 |
-                                   UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 |
+                                   UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE |
                                    UDMA_CHCTL_ARBSIZE_4 |
                                    UDMA_CHCTL_XFERSIZE(n) |
                                    UDMA_CHCTL_XFERMODE_BASIC;
@@ -629,17 +631,17 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf)
   else {
     /* Configure for 16-bit transfers.*/
     primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx;
-    primary[spip->dmatxnr].dstendp = &spip->ssi->DR;
-    primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 |
-                                   UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 |
+    primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR);
+    primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE |
+                                   UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE |
                                    UDMA_CHCTL_ARBSIZE_4 |
                                    UDMA_CHCTL_XFERSIZE(n) |
                                    UDMA_CHCTL_XFERMODE_BASIC;
 
-    primary[spip->dmarxnr].srcendp = &spip->ssi->DR;
+    primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR);
     primary[spip->dmarxnr].dstendp = rxbuf+(n*2)-1;
     primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_16 |
-                                   UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 |
+                                   UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE |
                                    UDMA_CHCTL_ARBSIZE_4 |
                                    UDMA_CHCTL_XFERSIZE(n) |
                                    UDMA_CHCTL_XFERMODE_BASIC;
@@ -674,10 +676,10 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf)
  */
 uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame)
 {
-  spip->ssi->DR = (uint32_t)frame;
-  while ((spip->ssi->SR & TIVA_SR_RNE) == 0)
+  HWREG(spip->ssi + SSI_O_DR) = (uint32_t)frame;
+  while ((HWREG(spip->ssi + SSI_O_SR) & SSI_SR_RNE) == 0)
     ;
-  return (uint16_t)spip->ssi->DR;
+  return (uint16_t)HWREG(spip->ssi + SSI_O_DR);
 }
 
 #endif /* HAL_USE_SPI */
diff --git a/os/hal/ports/TIVA/LLD/hal_spi_lld.h b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h
index 2adc9ed..c93c189 100644
--- a/os/hal/ports/TIVA/LLD/hal_spi_lld.h
+++ b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -15,7 +15,7 @@
 */
 
 /**
- * @file    TIVA/LLD/spi_lld.h
+ * @file    SSI/hal_spi_lld.h
  * @brief   TM4C123x/TM4C129x SPI subsystem low level driver.
  *
  * @addtogroup SPI
@@ -32,89 +32,9 @@
 /*===========================================================================*/
 
 /**
- * @name    Control 0
- * @{
- */
-#define TIVA_CR0_DSS_MASK       0x0F
-#define TIVA_CR0_DSS(n)         ((n-1) << 0)
-
-#define TIVA_CR0_FRF_MASK       (3 << 4)
-#define TIVA_CR0_FRF(n)         ((n) << 4)
-
-#define TIVA_CR0_SPO            (1 << 6)
-#define TIVA_CR0_SPH            (1 << 7)
-
-#define TIVA_CR0_SRC_MASK       (0xFF << 8)
-#define TIVA_CR0_SRC(n)         ((n) << 8)
-/** @} */
-
-/**
- * @name    Control 1
- * @{
- */
-#define TIVA_CR1_LBM            (1 << 0)
-#define TIVA_CR1_SSE            (1 << 1)
-#define TIVA_CR1_MS             (1 << 2)
-#define TIVA_CR1_SOD            (1 << 3)
-#define TIVA_CR1_EOT            (1 << 4)
-/** @} */
-
-/**
- * @name    Status
- * @{
- */
-#define TIVA_SR_TFE             (1 << 0)
-#define TIVA_SR_TNF             (1 << 1)
-#define TIVA_SR_RNE             (1 << 2)
-#define TIVA_SR_RFF             (1 << 3)
-#define TIVA_SR_BSY             (1 << 4)
-/** @} */
-
-/**
- * @name    Interrupt Mask
- * @{
- */
-#define TIVA_IM_RORIM           (1 << 0)
-#define TIVA_IM_RTIM            (1 << 1)
-#define TIVA_IM_RXIM            (1 << 2)
-#define TIVA_IM_TXIM            (1 << 3)
-/** @} */
-
-/**
- * @name    Interrupt Status
- * @{
- */
-#define TIVA_IS_RORIS           (1 << 0)
-#define TIVA_IS_RTIS            (1 << 1)
-#define TIVA_IS_RXIS            (1 << 2)
-#define TIVA_IS_TXIS            (1 << 3)
-/** @} */
-
-/**
- * @name    Masked Interrupt Status
- * @{
- */
-#define TIVA_MIS_RORMIS         (1 << 0)
-#define TIVA_MIS_RTMIS          (1 << 1)
-#define TIVA_MIS_RXMIS          (1 << 2)
-#define TIVA_MIS_TXMIS          (1 << 3)
-/** @} */
-
-/**
- * @name    Interrupt Clear
- * @{
+ * @brief   CR0 Serial Clock Rate helper.
  */
-#define TIVA_ICR_RORIC          (1 << 0)
-#define TIVA_ICR_RTIC           (1 << 1)
-/** @} */
-
-/**
- * @name    DMA Control
- * @{
- */
-#define TIVA_DMACTL_RXDMAE      (1 << 0)
-#define TIVA_DMACTL_TXDMAE      (1 << 1)
-/** @} */
+#define SSI_CR0_SCR(n)         ((n) << 8)
 
 /*===========================================================================*/
 /* Driver pre-compile time settings.                                         */
@@ -236,7 +156,7 @@
 #error "Invalid IRQ priority assigned to SSI2"
 #endif
 
-#if TM4C123x_SPI_USE_SSI3 && \
+#if TIVA_SPI_USE_SSI3 && \
     !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SPI_SSI3_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to SSI3"
 #endif
@@ -245,6 +165,10 @@
 #define TIVA_UDMA_REQUIRED
 #endif
 
+#if SPI_SELECT_MODE == SPI_SELECT_MODE_LLD
+#error "SPI_SELECT_MODE_LLD not supported by this driver"
+#endif
+
 /*===========================================================================*/
 /* Driver data structures and types.                                         */
 /*===========================================================================*/
@@ -269,16 +193,34 @@ typedef struct {
   /**
    * @brief Operation complete callback or @p NULL.
    */
-  spicallback_t         end_cb;
-  /* End of the mandatory fields.*/
+  spicallback_t             end_cb;
+#if (SPI_SELECT_MODE == SPI_SELECT_MODE_LINE) || defined(__DOXYGEN__)
   /**
-   * @brief The chip select line port.
+   * @brief The chip select line.
    */
-  ioportid_t            ssport;
+  ioline_t                  ssline;
+#endif
+#if (SPI_SELECT_MODE == SPI_SELECT_MODE_PORT) || defined(__DOXYGEN__)
   /**
-   * @brief The chip select line pad number.
+   * @brief The chip select port.
    */
-  uint16_t              sspad;
+  ioportid_t                ssport;
+  /**
+   * @brief The chip select port mask.
+   */
+  uint8fast_t               ssmask;
+#endif
+#if (SPI_SELECT_MODE == SPI_SELECT_MODE_PAD) || defined(__DOXYGEN__)
+  /**
+   * @brief The chip select port.
+   */
+  ioportid_t                ssport;
+  /**
+   * @brief The chip select pad number.
+   */
+  uint_fast8_t              sspad;
+#endif
+  /* End of the mandatory fields.*/
   /**
    * @brief SSI CR0 initialization data.
    */
@@ -320,7 +262,7 @@ struct SPIDriver {
   /**
    * @brief Pointer to the SSI registers block.
    */
-  SSI_TypeDef           *ssi;
+  uint32_t              ssi;
   /**
    * @brief Receive DMA channel number.
    */
@@ -369,8 +311,10 @@ extern "C" {
   void spi_lld_init(void);
   void spi_lld_start(SPIDriver *spip);
   void spi_lld_stop(SPIDriver *spip);
+#if (SPI_SELECT_MODE == SPI_SELECT_MODE_LLD) || defined(__DOXYGEN__)
   void spi_lld_select(SPIDriver *spip);
   void spi_lld_unselect(SPIDriver *spip);
+#endif
   void spi_lld_ignore(SPIDriver *spip, size_t n);
   void spi_lld_exchange(SPIDriver *spip, size_t n,
                         const void *txbuf, void *rxbuf);
diff --git a/os/hal/ports/TIVA/LLD/UART/driver.mk b/os/hal/ports/TIVA/LLD/UART/driver.mk
new file mode 100644
index 0000000..e42f34a
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/UART/driver.mk
@@ -0,0 +1,13 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c
+endif
+ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c
+PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART
diff --git a/os/hal/ports/TIVA/LLD/hal_serial_lld.c b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c
index bd1b81e..f1bda8d 100644
--- a/os/hal/ports/TIVA/LLD/hal_serial_lld.c
+++ b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -15,7 +15,7 @@
 */
 
 /**
- * @file    TIVA/LLD/serial_lld.c
+ * @file    UART/hal_serial_lld.c
  * @brief   Tiva low level serial driver code.
  *
  * @addtogroup SERIAL
@@ -34,58 +34,42 @@
 /* Driver exported variables.                                                */
 /*===========================================================================*/
 
-/**
- * @brief UART0 serial driver identifier.
- */
+/** @brief UART0 serial driver identifier.*/
 #if TIVA_SERIAL_USE_UART0 || defined(__DOXYGEN__)
 SerialDriver SD1;
 #endif
 
-/**
- * @brief UART1 serial driver identifier.
- */
+/** @brief UART1 serial driver identifier.*/
 #if TIVA_SERIAL_USE_UART1 || defined(__DOXYGEN__)
 SerialDriver SD2;
 #endif
 
-/**
- * @brief UART2 serial driver identifier.
- */
+/** @brief UART2 serial driver identifier.*/
 #if TIVA_SERIAL_USE_UART2 || defined(__DOXYGEN__)
 SerialDriver SD3;
 #endif
 
-/**
- * @brief UART3 serial driver identifier.
- */
+/** @brief UART3 serial driver identifier.*/
 #if TIVA_SERIAL_USE_UART3 || defined(__DOXYGEN__)
 SerialDriver SD4;
 #endif
 
-/**
- * @brief UART4 serial driver identifier.
- */
+/** @brief UART4 serial driver identifier.*/
 #if TIVA_SERIAL_USE_UART4 || defined(__DOXYGEN__)
 SerialDriver SD5;
 #endif
 
-/**
- * @brief UART5 serial driver identifier.
- */
+/** @brief UART5 serial driver identifier.*/
 #if TIVA_SERIAL_USE_UART5 || defined(__DOXYGEN__)
 SerialDriver SD6;
 #endif
 
-/**
- * @brief UART6 serial driver identifier.
- */
+/** @brief UART6 serial driver identifier.*/
 #if TIVA_SERIAL_USE_UART6 || defined(__DOXYGEN__)
 SerialDriver SD7;
 #endif
 
-/**
- * @brief UART7 serial driver identifier.
- */
+/** @brief UART7 serial driver identifier.*/
 #if TIVA_SERIAL_USE_UART7 || defined(__DOXYGEN__)
 SerialDriver SD8;
 #endif
@@ -94,16 +78,80 @@ SerialDriver SD8;
 /* Driver local variables.                                                   */
 /*===========================================================================*/
 
-/**
- * @brief Driver default configuration.
- */
+/** @brief Driver default configuration.*/
 static const SerialConfig sd_default_config =
 {
   SERIAL_DEFAULT_BITRATE,
-  TIVA_LCRH_FEN | TIVA_LCRH_WLEN_8,
-  TIVA_IFLS_TXIFLSEL_1_8_F | TIVA_IFLS_RXIFLSEL_1_8_E
+  0,
+  UART_LCRH_FEN | UART_LCRH_WLEN_8,
+  UART_IFLS_TX4_8 | UART_IFLS_RX7_8,
+  UART_CC_CS_SYSCLK
 };
 
+#if TIVA_SERIAL_USE_UART0 || defined(__DOXYGEN__)
+/** @brief Input buffer for SD1.*/
+static uint8_t sd_in_buf1[TIVA_SERIAL_UART0_IN_BUF_SIZE];
+
+/** @brief Output buffer for SD1.*/
+static uint8_t sd_out_buf1[TIVA_SERIAL_UART0_OUT_BUF_SIZE];
+#endif
+
+#if TIVA_SERIAL_USE_UART1 || defined(__DOXYGEN__)
+/** @brief Input buffer for SD2.*/
+static uint8_t sd_in_buf2[TIVA_SERIAL_UART1_IN_BUF_SIZE];
+
+/** @brief Output buffer for SD2.*/
+static uint8_t sd_out_buf2[TIVA_SERIAL_UART1_OUT_BUF_SIZE];
+#endif
+
+#if TIVA_SERIAL_USE_UART2 || defined(__DOXYGEN__)
+/** @brief Input buffer for SD3.*/
+static uint8_t sd_in_buf3[TIVA_SERIAL_UART2_IN_BUF_SIZE];
+
+/** @brief Output buffer for SD3.*/
+static uint8_t sd_out_buf3[TIVA_SERIAL_UART2_OUT_BUF_SIZE];
+#endif
+
+#if TIVA_SERIAL_USE_UART3 || defined(__DOXYGEN__)
+/** @brief Input buffer for SD4.*/
+static uint8_t sd_in_buf4[TIVA_SERIAL_UART3_IN_BUF_SIZE];
+
+/** @brief Output buffer for SD4.*/
+static uint8_t sd_out_buf4[TIVA_SERIAL_UART3_OUT_BUF_SIZE];
+#endif
+
+#if TIVA_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+/** @brief Input buffer for SD5.*/
+static uint8_t sd_in_buf5[TIVA_SERIAL_UART4_IN_BUF_SIZE];
+
+/** @brief Output buffer for SD5.*/
+static uint8_t sd_out_buf5[TIVA_SERIAL_UART4_OUT_BUF_SIZE];
+#endif
+
+#if TIVA_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+/** @brief Input buffer for SD6.*/
+static uint8_t sd_in_buf6[TIVA_SERIAL_UART5_IN_BUF_SIZE];
+
+/** @brief Output buffer for SD6.*/
+static uint8_t sd_out_buf6[TIVA_SERIAL_UART5_OUT_BUF_SIZE];
+#endif
+
+#if TIVA_SERIAL_USE_UART6 || defined(__DOXYGEN__)
+/** @brief Input buffer for SD7.*/
+static uint8_t sd_in_buf7[TIVA_SERIAL_UART6_IN_BUF_SIZE];
+
+/** @brief Output buffer for SD7.*/
+static uint8_t sd_out_buf7[TIVA_SERIAL_UART6_OUT_BUF_SIZE];
+#endif
+
+#if TIVA_SERIAL_USE_UART7 || defined(__DOXYGEN__)
+/** @brief Input buffer for SD8.*/
+static uint8_t sd_in_buf8[TIVA_SERIAL_UART7_IN_BUF_SIZE];
+
+/** @brief Output buffer for SD8.*/
+static uint8_t sd_out_buf8[TIVA_SERIAL_UART7_OUT_BUF_SIZE];
+#endif
+
 /*===========================================================================*/
 /* Driver local functions.                                                   */
 /*===========================================================================*/
@@ -111,23 +159,55 @@ static const SerialConfig sd_default_config =
 /**
  * @brief   UART initialization.
  *
- * @param[in] sdp       communication channel associated to the UART
+ * @param[in] sdp       pointer to a @p SerialDriver object
  * @param[in] config    the architecture-dependent serial driver configuration
  */
 static void uart_init(SerialDriver *sdp, const SerialConfig *config)
 {
-  UART_TypeDef *u = sdp->uart;
-  uint32_t div;  /* baud rate divisor */
-
-  /* disable the UART before any of the control registers are reprogrammed */
-  u->CTL &= ~TIVA_CTL_UARTEN;
-  div = (((TIVA_SYSCLK * 8) / config->sc_speed) + 1) / 2;
-  u->IBRD = div / 64;   /* integer portion of the baud rate divisor */
-  u->FBRD = div % 64;   /* fractional portion of the baud rate divisor */
-  u->LCRH = config->sc_lcrh;   /* set data format */
-  u->IFLS = config->sc_ifls;
-  u->CTL |= TIVA_CTL_TXE | TIVA_CTL_RXE | TIVA_CTL_UARTEN;
-  u->IM |= TIVA_IM_RXIM | TIVA_IM_TXIM | TIVA_IM_RTIM;   /* interrupts enable */
+  uint32_t u = sdp->uart;
+  uint32_t brd;
+  uint32_t speed = config->speed;
+  uint32_t clock_source;
+
+  if (config->ctl & UART_CTL_HSE) {
+    /* High speed mode is enabled, half the baud rate to compensate
+     * for high speed mode.*/
+    speed = (speed + 1) / 2;
+  }
+
+  if ((config->cc & UART_CC_CS_SYSCLK) == UART_CC_CS_SYSCLK) {
+    /* UART is clocked using the SYSCLK.*/
+    clock_source = TIVA_SYSCLK * 8;
+  }
+  else {
+    /* UART is clocked using the PIOSC.*/
+    clock_source = 16000000 * 8;
+  }
+
+  /* Calculate the baud rate divisor */
+  brd = ((clock_source / speed) + 1) / 2;
+
+  /* Disable UART.*/
+  HWREG(u + UART_O_CTL) &= ~UART_CTL_UARTEN;
+
+  /* Set baud rate.*/
+  HWREG(u + UART_O_IBRD) = brd / 64;
+  HWREG(u + UART_O_FBRD) = brd % 64;
+
+  /* Line control/*/
+  HWREG(u + UART_O_LCRH) = config->lcrh;
+
+  /* Select clock source.*/
+  HWREG(u + UART_O_CC) = config->cc & UART_CC_CS_M;
+
+  /* FIFO configuration.*/
+  HWREG(u + UART_O_IFLS) = config->ifls & (UART_IFLS_RX_M | UART_IFLS_TX_M);
+
+  /* Note that some bits are enforced.*/
+  HWREG(u + UART_O_CTL)  = config->ctl | UART_CTL_RXE | UART_CTL_TXE | UART_CTL_UARTEN;
+
+  /* Enable interrupts.*/
+  HWREG(u + UART_O_IM)   = UART_IM_RXIM | UART_IM_TXIM | UART_IM_RTIM;
 }
 
 /**
@@ -135,9 +215,9 @@ static void uart_init(SerialDriver *sdp, const SerialConfig *config)
  *
  * @param[in] u         pointer to an UART I/O block
  */
-static void uart_deinit(UART_TypeDef *u)
+static void uart_deinit(uint32_t u)
 {
-  u->CTL &= ~TIVA_CTL_UARTEN;
+  HWREG(u + UART_O_CTL) &= ~UART_CTL_UARTEN;
 }
 
 /**
@@ -150,13 +230,13 @@ static void set_error(SerialDriver *sdp, uint16_t err)
 {
   eventflags_t sts = 0;
   
-  if (err & TIVA_MIS_FEMIS)
+  if (err & UART_MIS_FEMIS)
     sts |= SD_FRAMING_ERROR;
-  if (err & TIVA_MIS_PEMIS)
+  if (err & UART_MIS_PEMIS)
     sts |= SD_PARITY_ERROR;
-  if (err & TIVA_MIS_BEMIS)
+  if (err & UART_MIS_BEMIS)
     sts |= SD_BREAK_DETECTED;
-  if (err & TIVA_MIS_OEMIS)
+  if (err & UART_MIS_OEMIS)
     sts |= SD_OVERRUN_ERROR;
   osalSysLockFromISR();
   chnAddFlagsI(sdp, sts);
@@ -174,64 +254,67 @@ static void set_error(SerialDriver *sdp, uint16_t err)
  */
 static void serial_serve_interrupt(SerialDriver *sdp) 
 {
-  UART_TypeDef *u = sdp->uart;
-  uint16_t mis = u->MIS;
+  uint32_t u = sdp->uart;
+  uint16_t mis = HWREG(u + UART_O_MIS);
   
-  u->ICR = mis;		/* clear interrupts */
+  HWREG(u + UART_O_ICR) = mis;		/* clear interrupts */
 
-  if (mis & (TIVA_MIS_FEMIS | TIVA_MIS_PEMIS | TIVA_MIS_BEMIS | TIVA_MIS_OEMIS)) {
+  if (mis & (UART_MIS_FEMIS | UART_MIS_PEMIS | UART_MIS_BEMIS | UART_MIS_OEMIS)) {
     set_error(sdp, mis);
   }
 
-  if ((mis & TIVA_MIS_RXMIS) || (mis &  TIVA_MIS_RTMIS)) {
+  if ((mis & UART_MIS_RXMIS) || (mis &  UART_MIS_RTMIS)) {
     osalSysLockFromISR();
     if (iqIsEmptyI(&sdp->iqueue)) {
       chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE);
     }
     osalSysUnlockFromISR();
-    while ((u->FR & TIVA_FR_RXFE) == 0) {
+    while ((HWREG(u + UART_O_FR) & UART_FR_RXFE) == 0) {
       osalSysLockFromISR();
-      if (iqPutI(&sdp->iqueue, u->DR) < Q_OK) {
-        chnAddFlagsI(sdp, SD_OVERRUN_ERROR);
+      if (iqPutI(&sdp->iqueue, HWREG(u + UART_O_DR)) < Q_OK) {
+        chnAddFlagsI(sdp, SD_QUEUE_FULL_ERROR);
       }
       osalSysUnlockFromISR();
     }
   }
 
-  if (mis & TIVA_MIS_TXMIS) {
-    while ((u->FR & TIVA_FR_TXFF) == 0) {
+  if (mis & UART_MIS_TXMIS) {
+    while ((HWREG(u + UART_O_FR) & UART_FR_TXFF) == 0) {
       msg_t b;
       osalSysLockFromISR();
       b = oqGetI(&sdp->oqueue);
       osalSysUnlockFromISR();
       if (b < Q_OK) {
-        u->IM &= ~TIVA_IM_TXIM;
+        HWREG(u + UART_O_IM) &= ~UART_IM_TXIM;
         osalSysLockFromISR();
         chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
         osalSysUnlockFromISR();
         break;
       }
-      u->DR = b;
+      HWREG(u + UART_O_DR) = b;
     }
   }
+
+  /* TODO: Physical transmission end. */
 }
 
 /**
- * @brief
+ * @brief   Fill the hardware FIFO of a UART.
  */
 static void fifo_load(SerialDriver *sdp)
 {
-  UART_TypeDef *u = sdp->uart;
+  uint32_t u = sdp->uart;
 
-  while ((u->FR & TIVA_FR_TXFF) == 0) {
+  while ((HWREG(u + UART_O_FR) & UART_FR_TXFF) == 0) {
     msg_t b = oqGetI(&sdp->oqueue);
     if (b < Q_OK) {
       chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
       return;
     }
-    u->DR = b;
+    HWREG(u + UART_O_DR) = b;
   }
-  u->IM |= TIVA_IM_TXIM;   /* transmit interrupt enable */
+
+  HWREG(u + UART_O_IM) |= UART_IM_TXIM;   /* transmit interrupt enable */
 }
 
 /**
@@ -326,13 +409,15 @@ static void notify8(io_queue_t *qp)
 /* Driver interrupt handlers.                                                */
 /*===========================================================================*/
 
-/**
- * @brief   UART0 IRQ handler.
- */
 #if TIVA_SERIAL_USE_UART0 || defined(__DOXYGEN__)
 #if !defined(TIVA_UART0_HANDLER)
 #error "TIVA_UART0_HANDLER not defined"
 #endif
+/**
+ * @brief   UART0 interrupt handler.
+ *
+ * @isr
+ */
 CH_IRQ_HANDLER(TIVA_UART0_HANDLER)
 {
   CH_IRQ_PROLOGUE();
@@ -343,10 +428,16 @@ CH_IRQ_HANDLER(TIVA_UART0_HANDLER)
 }
 #endif
 
+
+#if TIVA_SERIAL_USE_UART1 || defined(__DOXYGEN__)
+#if !defined(TIVA_UART1_HANDLER)
+#error "TIVA_UART1_HANDLER not defined"
+#endif
 /**
- * @brief   UART1 IRQ handler.
+ * @brief   UART1 interrupt handler.
+ *
+ * @isr
  */
-#if TIVA_SERIAL_USE_UART1 || defined(__DOXYGEN__)
 CH_IRQ_HANDLER(TIVA_UART1_HANDLER)
 {
   CH_IRQ_PROLOGUE();
@@ -357,10 +448,15 @@ CH_IRQ_HANDLER(TIVA_UART1_HANDLER)
 }
 #endif
 
+#if TIVA_SERIAL_USE_UART2 || defined(__DOXYGEN__)
+#if !defined(TIVA_UART2_HANDLER)
+#error "TIVA_UART2_HANDLER not defined"
+#endif
 /**
- * @brief   UART2 IRQ handler.
+ * @brief   UART2 interrupt handler.
+ *
+ * @isr
  */
-#if TIVA_SERIAL_USE_UART2 || defined(__DOXYGEN__)
 CH_IRQ_HANDLER(TIVA_UART2_HANDLER)
 {
   CH_IRQ_PROLOGUE();
@@ -371,10 +467,15 @@ CH_IRQ_HANDLER(TIVA_UART2_HANDLER)
 }
 #endif
 
+#if TIVA_SERIAL_USE_UART3 || defined(__DOXYGEN__)
+#if !defined(TIVA_UART3_HANDLER)
+#error "TIVA_UART3_HANDLER not defined"
+#endif
 /**
- * @brief   UART3 IRQ handler.
+ * @brief   UART3 interrupt handler.
+ *
+ * @isr
  */
-#if TIVA_SERIAL_USE_UART3 || defined(__DOXYGEN__)
 CH_IRQ_HANDLER(TIVA_UART3_HANDLER)
 {
   CH_IRQ_PROLOGUE();
@@ -385,10 +486,15 @@ CH_IRQ_HANDLER(TIVA_UART3_HANDLER)
 }
 #endif
 
+#if TIVA_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+#if !defined(TIVA_UART4_HANDLER)
+#error "TIVA_UART4_HANDLER not defined"
+#endif
 /**
- * @brief   UART4 IRQ handler.
+ * @brief   UART4 interrupt handler.
+ *
+ * @isr
  */
-#if TIVA_SERIAL_USE_UART4 || defined(__DOXYGEN__)
 CH_IRQ_HANDLER(TIVA_UART4_HANDLER)
 {
   CH_IRQ_PROLOGUE();
@@ -399,10 +505,15 @@ CH_IRQ_HANDLER(TIVA_UART4_HANDLER)
 }
 #endif
 
+#if TIVA_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+#if !defined(TIVA_UART5_HANDLER)
+#error "TIVA_UART5_HANDLER not defined"
+#endif
 /**
- * @brief   UART5 IRQ handler.
+ * @brief   UART5 interrupt handler.
+ *
+ * @isr
  */
-#if TIVA_SERIAL_USE_UART5 || defined(__DOXYGEN__)
 CH_IRQ_HANDLER(TIVA_UART5_HANDLER)
 {
   CH_IRQ_PROLOGUE();
@@ -413,10 +524,15 @@ CH_IRQ_HANDLER(TIVA_UART5_HANDLER)
 }
 #endif
 
+#if TIVA_SERIAL_USE_UART6 || defined(__DOXYGEN__)
+#if !defined(TIVA_UART6_HANDLER)
+#error "TIVA_UART6_HANDLER not defined"
+#endif
 /**
- * @brief   UART6 IRQ handler.
+ * @brief   UART6 interrupt handler.
+ *
+ * @isr
  */
-#if TIVA_SERIAL_USE_UART6 || defined(__DOXYGEN__)
 CH_IRQ_HANDLER(TIVA_UART6_HANDLER)
 {
   CH_IRQ_PROLOGUE();
@@ -427,10 +543,15 @@ CH_IRQ_HANDLER(TIVA_UART6_HANDLER)
 }
 #endif
 
+#if TIVA_SERIAL_USE_UART7 || defined(__DOXYGEN__)
+#if !defined(TIVA_UART7_HANDLER)
+#error "TIVA_UART7_HANDLER not defined"
+#endif
 /**
- * @brief   UART7 IRQ handler.
+ * @brief   UART7 interrupt handler.
+ *
+ * @isr
  */
-#if TIVA_SERIAL_USE_UART7 || defined(__DOXYGEN__)
 CH_IRQ_HANDLER(TIVA_UART7_HANDLER)
 {
   CH_IRQ_PROLOGUE();
@@ -447,47 +568,65 @@ CH_IRQ_HANDLER(TIVA_UART7_HANDLER)
 
 /**
  * @brief   Low level serial driver initialization.
+ *
+ * @notapi
  */
 void sd_lld_init(void)
 {
 #if TIVA_SERIAL_USE_UART0
-  sdObjectInit(&SD1, NULL, notify1);
-  SD1.uart = UART0;
+  sdObjectInit(&SD1);
+  iqObjectInit(&SD1.iqueue, sd_in_buf1, sizeof sd_in_buf1, NULL, &SD1);
+  oqObjectInit(&SD1.oqueue, sd_out_buf1, sizeof sd_out_buf1, notify1, &SD1);
+  SD1.uart = UART0_BASE;
 #endif
 
 #if TIVA_SERIAL_USE_UART1
-  sdObjectInit(&SD2, NULL, notify2);
-  SD2.uart = UART1;
+  sdObjectInit(&SD2);
+  iqObjectInit(&SD2.iqueue, sd_in_buf2, sizeof sd_in_buf2, NULL, &SD2);
+  oqObjectInit(&SD2.oqueue, sd_out_buf2, sizeof sd_out_buf2, notify2, &SD2);
+  SD2.uart = UART1_BASE;
 #endif
 
 #if TIVA_SERIAL_USE_UART2
-  sdObjectInit(&SD3, NULL, notify3);
-  SD3.uart = UART2;
+  sdObjectInit(&SD3);
+  iqObjectInit(&SD3.iqueue, sd_in_buf3, sizeof sd_in_buf3, NULL, &SD3);
+  oqObjectInit(&SD3.oqueue, sd_out_buf3, sizeof sd_out_buf3, notify3, &SD3);
+  SD3.uart = UART2_BASE;
 #endif
 
 #if TIVA_SERIAL_USE_UART3
-  sdObjectInit(&SD4, NULL, notify4);
-  SD4.uart = UART3;
+  sdObjectInit(&SD4);
+  iqObjectInit(&SD4.iqueue, sd_in_buf4, sizeof sd_in_buf4, NULL, &SD4);
+  oqObjectInit(&SD4.oqueue, sd_out_buf4, sizeof sd_out_buf4, notify4, &SD4);
+  SD4.uart = UART3_BASE;
 #endif
 
 #if TIVA_SERIAL_USE_UART4
-  sdObjectInit(&SD5, NULL, notify5);
-  SD5.uart = UART4;
+  sdObjectInit(&SD5);
+  iqObjectInit(&SD5.iqueue, sd_in_buf5, sizeof sd_in_buf5, NULL, &SD5);
+  oqObjectInit(&SD5.oqueue, sd_out_buf5, sizeof sd_out_buf5, notify5, &SD5);
+  SD5.uart = UART4_BASE;
 #endif
 
 #if TIVA_SERIAL_USE_UART5
-  sdObjectInit(&SD6, NULL, notify6);
-  SD6.uart = UART5;
+  sdObjectInit(&SD6);
+  iqObjectInit(&SD6.iqueue, sd_in_buf6, sizeof sd_in_buf6, NULL, &SD6);
+  oqObjectInit(&SD6.oqueue, sd_out_buf6, sizeof sd_out_buf6, notify6, &SD6);
+  SD6.uart = UART5_BASE;
 #endif
 
 #if TIVA_SERIAL_USE_UART6
-  sdObjectInit(&SD7, NULL, notify7);
-  SD7.uart = UART6;
+  sdObjectInit(&SD7);
+  iqObjectInit(&SD7.iqueue, sd_in_buf7, sizeof sd_in_buf7, NULL, &SD7);
+  oqObjectInit(&SD7.oqueue, sd_out_buf7, sizeof sd_out_buf7, notify7, &SD7);
+  SD7.uart = UART6_BASE;
 #endif
 
 #if TIVA_SERIAL_USE_UART7
-  sdObjectInit(&SD8, NULL, notify8);
-  SD8.uart = UART7;
+  sdObjectInit(&SD8);
+  iqObjectInit(&SD8.iqueue, sd_in_buf8, sizeof sd_in_buf8, NULL, &SD8);
+  oqObjectInit(&SD8.oqueue, sd_out_buf8, sizeof sd_out_buf8, notify8, &SD8);
+  SD8.uart = UART7_BASE;
 #endif
 }
 
@@ -498,6 +637,8 @@ void sd_lld_init(void)
  * @param[in] config    the architecture-dependent serial driver configuration.
  *                      If this parameter is set to @p NULL then a default
  *                      configuration is used.
+ *
+ * @notapi
  */
 void sd_lld_start(SerialDriver *sdp, const SerialConfig *config)
 {
@@ -507,49 +648,81 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config)
   if (sdp->state == SD_STOP) {
 #if TIVA_SERIAL_USE_UART0
     if (&SD1 == sdp) {
-      SYSCTL->RCGCUART |= (1 << 0);
+      HWREG(SYSCTL_RCGCUART) |= (1 << 0);
+
+      while (!(HWREG(SYSCTL_PRUART) & (1 << 0)))
+        ;
+
       nvicEnableVector(TIVA_UART0_NUMBER, TIVA_SERIAL_UART0_PRIORITY);
     }
 #endif
 #if TIVA_SERIAL_USE_UART1
     if (&SD2 == sdp) {
-      SYSCTL->RCGC.UART |= (1 << 1);
+      HWREG(SYSCTL_RCGCUART) |= (1 << 1);
+
+      while (!(HWREG(SYSCTL_PRUART) & (1 << 1)))
+        ;
+
       nvicEnableVector(TIVA_UART1_NUMBER, TIVA_SERIAL_UART1_PRIORITY);
     }
 #endif
 #if TIVA_SERIAL_USE_UART2
     if (&SD3 == sdp) {
-      SYSCTL->RCGC.UART |= (1 << 2);  /* enable UART2 module */
+      HWREG(SYSCTL_RCGCUART) |= (1 << 2);
+
+      while (!(HWREG(SYSCTL_PRUART) & (1 << 2)))
+        ;
+
       nvicEnableVector(TIVA_UART2_NUMBER, TIVA_SERIAL_UART2_PRIORITY);
     }
 #endif
 #if TIVA_SERIAL_USE_UART3
     if (&SD4 == sdp) {
-      SYSCTL->RCGC.UART |= (1 << 3);  /* enable UART3 module */
+      HWREG(SYSCTL_RCGCUART) |= (1 << 3);
+
+      while (!(HWREG(SYSCTL_PRUART) & (1 << 3)))
+        ;
+
       nvicEnableVector(TIVA_UART3_NUMBER, TIVA_SERIAL_UART3_PRIORITY);
     }
 #endif
 #if TIVA_SERIAL_USE_UART4
     if (&SD5 == sdp) {
-      SYSCTL->RCGC.UART |= (1 << 4);  /* enable UART4 module */
+      HWREG(SYSCTL_RCGCUART) |= (1 << 4);
+
+      while (!(HWREG(SYSCTL_PRUART) & (1 << 4)))
+        ;
+
       nvicEnableVector(TIVA_UART4_NUMBER, TIVA_SERIAL_UART4_PRIORITY);
     }
 #endif
 #if TIVA_SERIAL_USE_UART5
     if (&SD6 == sdp) {
-      SYSCTL->RCGC.UART |= (1 << 5);  /* enable UART5 module */
+      HWREG(SYSCTL_RCGCUART) |= (1 << 5);
+
+      while (!(HWREG(SYSCTL_PRUART) & (1 << 5)))
+        ;
+
       nvicEnableVector(TIVA_UART5_NUMBER, TIVA_SERIAL_UART5_PRIORITY);
     }
 #endif
 #if TIVA_SERIAL_USE_UART6
     if (&SD7 == sdp) {
-      SYSCTL->RCGC.UART |= (1 << 6);  /* enable UART6 module */
+      HWREG(SYSCTL_RCGCUART) |= (1 << 6);
+
+      while (!(HWREG(SYSCTL_PRUART) & (1 << 6)))
+        ;
+
       nvicEnableVector(TIVA_UART6_NUMBER, TIVA_SERIAL_UART6_PRIORITY);
     }
 #endif
 #if TIVA_SERIAL_USE_UART7
     if (&SD8 == sdp) {
-      SYSCTL->RCGC.UART |= (1 << 7);  /* enable UART7 module */
+      HWREG(SYSCTL_RCGCUART) |= (1 << 7);
+
+      while (!(HWREG(SYSCTL_PRUART) & (1 << 7)))
+        ;
+
       nvicEnableVector(TIVA_UART7_NUMBER, TIVA_SERIAL_UART7_PRIORITY);
     }
 #endif
@@ -563,6 +736,8 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config)
  *          interrupt vector.
  *
  * @param[in] sdp       pointer to a @p SerialDriver object
+ *
+ * @notapi
  */
 void sd_lld_stop(SerialDriver *sdp)
 {
@@ -570,56 +745,56 @@ void sd_lld_stop(SerialDriver *sdp)
     uart_deinit(sdp->uart);
 #if TIVA_SERIAL_USE_UART0
     if (&SD1 == sdp) {
-      SYSCTL->RCGCUART &= ~(1 << 0);  /* disable UART0 module */
+      HWREG(SYSCTL_RCGCUART) &= ~(1 << 0);  /* disable UART0 module */
       nvicDisableVector(TIVA_UART0_NUMBER);
       return;
     }
 #endif
 #if TIVA_SERIAL_USE_UART1
     if (&SD2 == sdp) {
-      SYSCTL->RCGC.UART &= ~(1 << 1);  /* disable UART1 module */
+      HWREG(SYSCTL_RCGCUART) &= ~(1 << 1);  /* disable UART1 module */
       nvicDisableVector(TIVA_UART1_NUMBER);
       return;
     }
 #endif
 #if TIVA_SERIAL_USE_UART2
     if (&SD3 == sdp) {
-      SYSCTL->RCGC.UART &= ~(1 << 2);  /* disable UART2 module */
+      HWREG(SYSCTL_RCGCUART) &= ~(1 << 2);  /* disable UART2 module */
       nvicDisableVector(TIVA_UART2_NUMBER);
       return;
     }
 #endif
 #if TIVA_SERIAL_USE_UART3
     if (&SD4 == sdp) {
-      SYSCTL->RCGC.UART &= ~(1 << 3);  /* disable UART3 module */
+      HWREG(SYSCTL_RCGCUART) &= ~(1 << 3);  /* disable UART3 module */
       nvicDisableVector(TIVA_UART3_NUMBER);
       return;
     }
 #endif
 #if TIVA_SERIAL_USE_UART4
     if (&SD5 == sdp) {
-      SYSCTL->RCGC.UART &= ~(1 << 4);  /* disable UART4 module */
+      HWREG(SYSCTL_RCGCUART) &= ~(1 << 4);  /* disable UART4 module */
       nvicDisableVector(TIVA_UART4_NUMBER);
       return;
     }
 #endif
 #if TIVA_SERIAL_USE_UART5
     if (&SD6 == sdp) {
-      SYSCTL->RCGC.UART &= ~(1 << 5);  /* disable UART5 module */
+      HWREG(SYSCTL_RCGCUART) &= ~(1 << 5);  /* disable UART5 module */
       nvicDisableVector(TIVA_UART5_NUMBER);
       return;
     }
 #endif
 #if TIVA_SERIAL_USE_UART6
     if (&SD7 == sdp) {
-      SYSCTL->RCGC.UART &= ~(1 << 6);  /* disable UART6 module */
+      HWREG(SYSCTL_RCGCUART) &= ~(1 << 6);  /* disable UART6 module */
       nvicDisableVector(TIVA_UART6_NUMBER);
       return;
     }
 #endif
 #if TIVA_SERIAL_USE_UART7
     if (&SD8 == sdp) {
-      SYSCTL->RCGC.UART &= ~(1 << 7);  /* disable UART7 module */
+      HWREG(SYSCTL_RCGCUART) &= ~(1 << 7);  /* disable UART7 module */
       nvicDisableVector(TIVA_UART7_NUMBER);
       return;
     }
diff --git a/os/hal/ports/TIVA/LLD/hal_serial_lld.h b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.h
index 203ef6a..bde999e 100644
--- a/os/hal/ports/TIVA/LLD/hal_serial_lld.h
+++ b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.h
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -15,7 +15,7 @@
 */
 
 /**
- * @file    TIVA/LLD/serial_lld.h
+ * @file    UART/hal_serial_lld.h
  * @brief   Tiva low level serial driver header.
  *
  * @addtogroup SERIAL
@@ -32,162 +32,14 @@
 /*===========================================================================*/
 
 /**
- * @name    FR register bits definitions
- * @{
- */
-
-#define TIVA_FR_CTS         (1 << 0)
-
-#define TIVA_FR_BUSY        (1 << 3)
-
-#define TIVA_FR_RXFE        (1 << 4)
-
-#define TIVA_FR_TXFF        (1 << 5)
-
-#define TIVA_FR_RXFF        (1 << 6)
-
-#define TIVA_FR_TXFE        (1 << 7)
-
-/**
- * @}
- */
-
-/**
- * @name    LCRH register bits definitions
- * @{
- */
-
-#define TIVA_LCRH_BRK       (1 << 0)
-
-#define TIVA_LCRH_PEN       (1 << 1)
-
-#define TIVA_LCRH_EPS       (1 << 2)
-
-#define TIVA_LCRH_STP2      (1 << 3)
-
-#define TIVA_LCRH_FEN       (1 << 4)
-
-#define TIVA_LCRH_WLEN_MASK (3 << 5)
-#define TIVA_LCRH_WLEN_5    (0 << 5)
-#define TIVA_LCRH_WLEN_6    (1 << 5)
-#define TIVA_LCRH_WLEN_7    (2 << 5)
-#define TIVA_LCRH_WLEN_8    (3 << 5)
-
-#define TIVA_LCRH_SPS       (1 << 7)
-
-/**
- * @}
+ * @brief   Advanced buffering support switch.
+ * @details This constants enables the advanced buffering support in the
+ *          low level driver, the queue buffer is no more part of the
+ *          @p SerialDriver structure, each driver can have a different
+ *          queue size.
  */
- 
-/**
- * @name    CTL register bits definitions
- * @{
- */
-
-#define TIVA_CTL_UARTEN     (1 << 0)
-
-#define TIVA_CTL_SIREN      (1 << 1)
-
-#define TIVA_CTL_SIRLP      (1 << 2)
-
-#define TIVA_CTL_SMART      (1 << 3)
-
-#define TIVA_CTL_EOT        (1 << 4)
-
-#define TIVA_CTL_HSE        (1 << 5)
-
-#define TIVA_CTL_LBE        (1 << 7)
-
-#define TIVA_CTL_TXE        (1 << 8)
-
-#define TIVA_CTL_RXE        (1 << 9)
-
-#define TIVA_CTL_RTS        (1 << 11)
-
-#define TIVA_CTL_RTSEN      (1 << 14)
-
-#define TIVA_CTL_CTSEN      (1 << 15)
-
-/**
- * @}
- */
-
-/**
- * @name    IFLS register bits definitions
- * @{
- */
-
-#define TIVA_IFLS_TXIFLSEL_MASK     (7 << 0)
-#define TIVA_IFLS_TXIFLSEL_1_8_F    (0 << 0)
-#define TIVA_IFLS_TXIFLSEL_1_4_F    (1 << 0)
-#define TIVA_IFLS_TXIFLSEL_1_2_F    (2 << 0)
-#define TIVA_IFLS_TXIFLSEL_3_4_F    (3 << 0)
-#define TIVA_IFLS_TXIFLSEL_7_8_F    (4 << 0)
-
-#define TIVA_IFLS_RXIFLSEL_MASK     (7 << 3)
-#define TIVA_IFLS_RXIFLSEL_7_8_E    (0 << 3)
-#define TIVA_IFLS_RXIFLSEL_3_4_E    (1 << 3)
-#define TIVA_IFLS_RXIFLSEL_1_2_E    (2 << 3)
-#define TIVA_IFLS_RXIFLSEL_1_4_E    (3 << 3)
-#define TIVA_IFLS_RXIFLSEL_1_8_E    (4 << 3)
-
-/**
- * @}
- */
-
-/**
- * @name    MIS register bits definitions
- * @{
- */
-
-#define TIVA_MIS_CTSMIS             (1 << 1)
-
-#define TIVA_MIS_RXMIS              (1 << 4)
-
-#define TIVA_MIS_TXMIS              (1 << 5)
-
-#define TIVA_MIS_RTMIS              (1 << 6)
-
-#define TIVA_MIS_FEMIS              (1 << 7)
-
-#define TIVA_MIS_PEMIS              (1 << 8)
-
-#define TIVA_MIS_BEMIS              (1 << 9)
-
-#define TIVA_MIS_OEMIS              (1 << 10)
-
-#define TIVA_MIS_9BITMIS            (1 << 12)
-
-/**
- * @}
- */
-
-/**
- * @name    IM register bits definitions
- * @{
- */
-
-#define TIVA_IM_CTSIM               (1 << 1)
-
-#define TIVA_IM_RXIM                (1 << 4)
-
-#define TIVA_IM_TXIM                (1 << 5)
-
-#define TIVA_IM_RTIM                (1 << 6)
+#define SERIAL_ADVANCED_BUFFERING_SUPPORT   TRUE
 
-#define TIVA_IM_FEIM                (1 << 7)
-
-#define TIVA_IM_PEIM                (1 << 8)
-
-#define TIVA_IM_BEIM                (1 << 9)
-
-#define TIVA_IM_OEIM                (1 << 10)
-
-#define TIVA_IM_9BITIM              (1 << 12)
-
-/**
- * @}
- */
 /*===========================================================================*/
 /* Driver pre-compile time settings.                                         */
 /*===========================================================================*/
@@ -196,7 +48,6 @@
  * @name    Configuration options
  * @{
  */
-
 /**
  * @brief   UART0 driver enable switch.
  * @details If set to @p TRUE the support for UART0 is included.
@@ -326,8 +177,117 @@
 #endif
 
 /**
- * @}
+ * @brief   Input buffer size for UART0.
+ */
+#if !defined(TIVA_SERIAL_UART0_IN_BUF_SIZE) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_UART0_IN_BUF_SIZE   SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief   Output buffer size for UART0.
+ */
+#if !defined(TIVA_SERIAL_UART0_OUT_BUF_SIZE) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_UART0_OUT_BUF_SIZE  SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief   Input buffer size for UART1.
+ */
+#if !defined(TIVA_SERIAL_UART1_IN_BUF_SIZE) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_UART1_IN_BUF_SIZE   SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief   Output buffer size for UART1.
+ */
+#if !defined(TIVA_SERIAL_UART1_OUT_BUF_SIZE) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_UART1_OUT_BUF_SIZE  SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief   Input buffer size for UART2.
+ */
+#if !defined(TIVA_SERIAL_UART2_IN_BUF_SIZE) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_UART2_IN_BUF_SIZE   SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief   Output buffer size for UART2.
+ */
+#if !defined(TIVA_SERIAL_UART2_OUT_BUF_SIZE) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_UART2_OUT_BUF_SIZE  SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief   Input buffer size for UART3.
+ */
+#if !defined(TIVA_SERIAL_UART3_IN_BUF_SIZE) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_UART3_IN_BUF_SIZE   SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief   Output buffer size for UART3.
+ */
+#if !defined(TIVA_SERIAL_UART3_OUT_BUF_SIZE) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_UART3_OUT_BUF_SIZE  SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief   Input buffer size for UART4.
+ */
+#if !defined(TIVA_SERIAL_UART4_IN_BUF_SIZE) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_UART4_IN_BUF_SIZE   SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief   Output buffer size for UART4.
  */
+#if !defined(TIVA_SERIAL_UART4_OUT_BUF_SIZE) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_UART4_OUT_BUF_SIZE  SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief   Input buffer size for UART5.
+ */
+#if !defined(TIVA_SERIAL_UART5_IN_BUF_SIZE) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_UART5_IN_BUF_SIZE   SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief   Output buffer size for UART5.
+ */
+#if !defined(TIVA_SERIAL_UART5_OUT_BUF_SIZE) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_UART5_OUT_BUF_SIZE  SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief   Input buffer size for UART6.
+ */
+#if !defined(TIVA_SERIAL_UART6_IN_BUF_SIZE) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_UART6_IN_BUF_SIZE   SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief   Output buffer size for UART6.
+ */
+#if !defined(TIVA_SERIAL_UART6_OUT_BUF_SIZE) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_UART6_OUT_BUF_SIZE  SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief   Input buffer size for UART7.
+ */
+#if !defined(TIVA_SERIAL_UART7_IN_BUF_SIZE) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_UART7_IN_BUF_SIZE   SERIAL_BUFFERS_SIZE
+#endif
+
+/**
+ * @brief   Output buffer size for UART7.
+ */
+#if !defined(TIVA_SERIAL_UART7_OUT_BUF_SIZE) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_UART7_OUT_BUF_SIZE  SERIAL_BUFFERS_SIZE
+#endif
+/** @} */
 
 /*===========================================================================*/
 /* Derived constants and error checks.                                       */
@@ -388,22 +348,32 @@
  * @brief   Tiva Serial Driver configuration structure.
  * @details An instance of this structure must be passed to @p sdStart()
  *          in order to configure and start a serial driver operations.
+ * @note    This structure content is architecture dependent, each driver
+ *          implementation defines its own version and the custom static
+ *          initializers.
  */
 typedef struct {
   /**
    * @brief Bit rate.
    */
-  uint32_t                  sc_speed;
+  uint32_t                  speed;
   /* End of the mandatory fields. */
   /**
-   * @brief Initialization value for the LCRH (Line Control) register.
+   * @brief Initialization value for the CTL register.
+   */
+  uint16_t                  ctl;
+  /**
+   * @brief Initialization value for the LCRH register.
+   */
+  uint8_t                   lcrh;
+  /**
+   * @brief Initialization value for the IFLS register.
    */
-  uint32_t                  sc_lcrh;
+  uint8_t                   ifls;
   /**
-   * @brief Initialization value for the IFLS (Interrupt FIFO Level Select)
-   * register.
+   * @brief Initialization value for the CC register.
    */
-  uint32_t                  sc_ifls;
+  uint8_t                   cc;
 } SerialConfig;
 
 /**
@@ -417,13 +387,9 @@ typedef struct {
   input_queue_t             iqueue;                                         \
   /* Output queue.*/                                                        \
   output_queue_t            oqueue;                                         \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
   /* End of the mandatory fields.*/                                         \
   /* Pointer to the USART registers block.*/                                \
-  UART_TypeDef              *uart;
+  uint32_t                  uart;
 
 /*===========================================================================*/
 /* Driver macros.                                                            */
diff --git a/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.c b/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.c
new file mode 100644
index 0000000..374ea6d
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.c
@@ -0,0 +1,826 @@
+/*
+    Copyright (C) 2014..2017 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    UART/hal_uart_lld.c
+ * @brief   Tiva low level UART driver code.
+ *
+ * @addtogroup UART
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_UART || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief UART0 UART driver identifier.*/
+#if TIVA_UART_USE_UART0 || defined(__DOXYGEN__)
+UARTDriver UARTD1;
+#endif
+
+/** @brief UART1 UART driver identifier.*/
+#if TIVA_UART_USE_UART1 || defined(__DOXYGEN__)
+UARTDriver UARTD2;
+#endif
+
+/** @brief UART2 UART driver identifier.*/
+#if TIVA_UART_USE_UART2 || defined(__DOXYGEN__)
+UARTDriver UARTD3;
+#endif
+
+/** @brief UART3 UART driver identifier.*/
+#if TIVA_UART_USE_UART3 || defined(__DOXYGEN__)
+UARTDriver UARTD4;
+#endif
+
+/** @brief UART4 UART driver identifier.*/
+#if TIVA_UART_USE_UART4 || defined(__DOXYGEN__)
+UARTDriver UARTD5;
+#endif
+
+/** @brief UART5 UART driver identifier.*/
+#if TIVA_UART_USE_UART5 || defined(__DOXYGEN__)
+UARTDriver UARTD6;
+#endif
+
+/** @brief UART6 UART driver identifier.*/
+#if TIVA_UART_USE_UART6 || defined(__DOXYGEN__)
+UARTDriver UARTD7;
+#endif
+
+/** @brief UART7 UART driver identifier.*/
+#if TIVA_UART_USE_UART7 || defined(__DOXYGEN__)
+UARTDriver UARTD8;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Status bits translation.
+ *
+ * @param[in] err       UART LSR register value
+ *
+ * @return  The error flags.
+ */
+static uartflags_t translate_errors(uint32_t err)
+{
+  uartflags_t sts = 0;
+
+  if (err & UART_MIS_FEMIS)
+    sts |= UART_FRAMING_ERROR;
+  if (err & UART_MIS_PEMIS)
+    sts |= UART_PARITY_ERROR;
+  if (err & UART_MIS_BEMIS)
+    sts |= UART_BREAK_DETECTED;
+  if (err & UART_MIS_OEMIS)
+    sts |= UART_OVERRUN_ERROR;
+
+  return sts;
+}
+
+/**
+ * @brief   Puts the receiver in the UART_RX_IDLE state.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ */
+static void uart_enter_rx_idle_loop(UARTDriver *uartp)
+{
+  tiva_udma_table_entry_t *primary = udmaControlTable.primary;
+
+  dmaChannelDisable(uartp->dmarxnr);
+
+  /* Configure for 8-bit transfers.*/
+  primary[uartp->dmarxnr].srcendp = (void *)(uartp->uart + UART_O_DR);
+  primary[uartp->dmarxnr].dstendp = (volatile void *)&uartp->rxbuf;
+  primary[uartp->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 |
+                                  UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE |
+                                  UDMA_CHCTL_ARBSIZE_4 |
+                                  UDMA_CHCTL_XFERSIZE(1) |
+                                  UDMA_CHCTL_XFERMODE_BASIC;
+
+  dmaChannelSingleBurst(uartp->dmarxnr);
+  dmaChannelPrimary(uartp->dmarxnr);
+  dmaChannelPriorityDefault(uartp->dmarxnr);
+  dmaChannelEnableRequest(uartp->dmarxnr);
+
+  /* Enable DMA channel, transfer starts immediately.*/
+  dmaChannelEnable(uartp->dmarxnr);
+}
+
+/**
+ * @brief   UART de-initialization.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ */
+static void uart_stop(UARTDriver *uartp)
+{
+  /* Stops RX and TX DMA channels.*/
+  dmaChannelDisable(uartp->dmarxnr);
+  dmaChannelDisable(uartp->dmatxnr);
+
+  /* Stops USART operations.*/
+  HWREG(uartp->uart + UART_O_CTL) &= ~UART_CTL_UARTEN;
+}
+
+/**
+ * @brief   UART initialization.
+ *
+ * @param[in] uartp     pointer to a @p UARTDriver object
+ */
+static void uart_init(UARTDriver *uartp)
+{
+  uint32_t u = uartp->uart;
+  const UARTConfig *config = uartp->config;
+  uint32_t brd;
+  uint32_t speed = config->speed;
+  uint32_t clock_source;
+
+  if (uartp->config->ctl & UART_CTL_HSE) {
+    /* High speed mode is enabled, half the baud rate to compensate
+     * for high speed mode.*/
+    speed = (speed + 1) / 2;
+  }
+
+  if ((config->cc & UART_CC_CS_M) == UART_CC_CS_SYSCLK) {
+    /* UART is clocked using the SYSCLK.*/
+    clock_source = TIVA_SYSCLK * 8;
+  }
+  else {
+    /* UART is clocked using the PIOSC.*/
+    clock_source = 16000000 * 8;
+  }
+
+  /* Calculate the baud rate divisor */
+  brd = ((clock_source / speed) + 1) / 2;
+
+  /* Disable UART.*/
+  HWREG(u + UART_O_CTL) &= ~UART_CTL_UARTEN;
+
+  /* Set baud rate.*/
+  HWREG(u + UART_O_IBRD) = brd / 64;
+  HWREG(u + UART_O_FBRD) = brd % 64;
+
+  /* Line control/*/
+  HWREG(u + UART_O_LCRH) = config->lcrh;
+
+  /* Select clock source.*/
+  HWREG(u + UART_O_CC) = config->cc & UART_CC_CS_M;
+
+  /* FIFO configuration.*/
+  HWREG(u + UART_O_IFLS) = config->ifls & (UART_IFLS_RX_M | UART_IFLS_TX_M);
+
+  /* Enable interrupts.*/
+  HWREG(u + UART_O_IM) = UART_IM_TXIM | UART_IM_OEIM | UART_IM_BEIM | UART_IM_PEIM | UART_IM_FEIM;
+
+  /* Enable DMA for the UART */
+  HWREG(u + UART_O_DMACTL) = UART_DMACTL_TXDMAE | UART_DMACTL_RXDMAE | UART_DMACTL_DMAERR;
+
+  /* Note that some bits are enforced.*/
+  HWREG(u + UART_O_CTL)  = config->ctl | UART_CTL_RXE | UART_CTL_TXE | UART_CTL_UARTEN | UART_CTL_EOT;
+
+  /* Starting the receiver idle loop.*/
+  uart_enter_rx_idle_loop(uartp);
+}
+
+/**
+ * @brief   UART common service routine.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ */
+static void uart_serve_interrupt(UARTDriver *uartp)
+{
+  uint32_t dmachis = HWREG(UDMA_CHIS);
+  uint32_t mis = HWREG(uartp->uart + UART_O_MIS);
+
+  if (mis & UART_MIS_TXMIS) {
+    /* End of transfer */
+    _uart_tx2_isr_code(uartp);
+  }
+
+  if (mis & (UART_MIS_OEMIS | UART_MIS_BEMIS | UART_MIS_PEMIS | UART_MIS_FEMIS)) {
+    /* Error occurred */
+    _uart_rx_error_isr_code(uartp, translate_errors(mis));
+  }
+
+  if (dmachis & (1 << uartp->dmarxnr)) {
+    if (uartp->rxstate == UART_RX_IDLE) {
+      /* Receiver in idle state, a callback is generated, if enabled, for each
+         received character and then the driver stays in the same state.*/
+      _uart_rx_idle_code(uartp);
+      uart_enter_rx_idle_loop(uartp);
+    }
+    else {
+      /* Receiver in active state, a callback is generated, if enabled, after
+         a completed transfer.*/
+      _uart_rx_complete_isr_code(uartp);
+    }
+  }
+
+  if (dmachis & (1 << uartp->dmatxnr)) {
+    /* A callback is generated, if enabled, after a completed transfer.*/
+    _uart_tx1_isr_code(uartp);
+  }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if TIVA_UART_USE_UART0 || defined(__DOXYGEN__)
+#if !defined(TIVA_UART0_HANDLER)
+#error "TIVA_UART0_HANDLER not defined"
+#endif
+/**
+ * @brief   UART0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_UART0_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  uart_serve_interrupt(&UARTD1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_UART_USE_UART1 || defined(__DOXYGEN__)
+#if !defined(TIVA_UART1_HANDLER)
+#error "TIVA_UART1_HANDLER not defined"
+#endif
+/**
+ * @brief   UART1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_UART1_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  uart_serve_interrupt(&UARTD2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_UART_USE_UART2 || defined(__DOXYGEN__)
+#if !defined(TIVA_UART2_HANDLER)
+#error "TIVA_UART2_HANDLER not defined"
+#endif
+/**
+ * @brief   UART2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_UART2_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  uart_serve_interrupt(&UARTD3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_UART_USE_UART3 || defined(__DOXYGEN__)
+#if !defined(TIVA_UART3_HANDLER)
+#error "TIVA_UART3_HANDLER not defined"
+#endif
+/**
+ * @brief   UART3 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_UART3_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  uart_serve_interrupt(&UARTD4);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_UART_USE_UART4 || defined(__DOXYGEN__)
+#if !defined(TIVA_UART4_HANDLER)
+#error "TIVA_UART4_HANDLER not defined"
+#endif
+/**
+ * @brief   UART4 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_UART4_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  uart_serve_interrupt(&UARTD5);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_UART_USE_UART5 || defined(__DOXYGEN__)
+#if !defined(TIVA_UART5_HANDLER)
+#error "TIVA_UART5_HANDLER not defined"
+#endif
+/**
+ * @brief   UART5 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_UART5_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  uart_serve_interrupt(&UARTD6);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_UART_USE_UART6 || defined(__DOXYGEN__)
+#if !defined(TIVA_UART6_HANDLER)
+#error "TIVA_UART6_HANDLER not defined"
+#endif
+/**
+ * @brief   UART6 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_UART6_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  uart_serve_interrupt(&UARTD7);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_UART_USE_UART7 || defined(__DOXYGEN__)
+#if !defined(TIVA_UART7_HANDLER)
+#error "TIVA_UART7_HANDLER not defined"
+#endif
+/**
+ * @brief   UART7 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_UART7_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  uart_serve_interrupt(&UARTD8);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level UART driver initialization.
+ *
+ * @notapi
+ */
+void uart_lld_init(void)
+{
+#if TIVA_UART_USE_UART0
+  uartObjectInit(&UARTD1);
+  UARTD1.uart    = UART0_BASE;
+  UARTD1.dmarxnr = TIVA_UART_UART0_RX_UDMA_CHANNEL;
+  UARTD1.dmatxnr = TIVA_UART_UART0_TX_UDMA_CHANNEL;
+  UARTD1.rxchnmap = TIVA_UART_UART0_RX_UDMA_MAPPING;
+  UARTD1.txchnmap = TIVA_UART_UART0_TX_UDMA_MAPPING;
+#endif
+#if TIVA_UART_USE_UART1
+  uartObjectInit(&UARTD2);
+  UARTD2.uart    = UART1_BASE;
+  UARTD2.dmarxnr = TIVA_UART_UART1_RX_UDMA_CHANNEL;
+  UARTD2.dmatxnr = TIVA_UART_UART1_TX_UDMA_CHANNEL;
+  UARTD2.rxchnmap = TIVA_UART_UART1_RX_UDMA_MAPPING;
+  UARTD2.txchnmap = TIVA_UART_UART1_TX_UDMA_MAPPING;
+#endif
+#if TIVA_UART_USE_UART2
+  uartObjectInit(&UARTD3);
+  UARTD2.uart    = UART2_BASE;
+  UARTD2.dmarxnr = TIVA_UART_UART2_RX_UDMA_CHANNEL;
+  UARTD2.dmatxnr = TIVA_UART_UART2_TX_UDMA_CHANNEL;
+  UARTD2.rxchnmap = TIVA_UART_UART2_RX_UDMA_MAPPING;
+  UARTD2.txchnmap = TIVA_UART_UART2_TX_UDMA_MAPPING;
+#endif
+#if TIVA_UART_USE_UART3
+  uartObjectInit(&UARTD4);
+  UARTD4.uart    = UART3_BASE;
+  UARTD4.dmarxnr = TIVA_UART_UART3_RX_UDMA_CHANNEL;
+  UARTD4.dmatxnr = TIVA_UART_UART3_TX_UDMA_CHANNEL;
+  UARTD4.rxchnmap = TIVA_UART_UART3_RX_UDMA_MAPPING;
+  UARTD4.txchnmap = TIVA_UART_UART3_TX_UDMA_MAPPING;
+#endif
+#if TIVA_UART_USE_UART4
+  uartObjectInit(&UARTD5);
+  UARTD5.uart    = UART4_BASE;
+  UARTD5.dmarxnr = TIVA_UART_UART4_RX_UDMA_CHANNEL;
+  UARTD5.dmatxnr = TIVA_UART_UART4_TX_UDMA_CHANNEL;
+  UARTD5.rxchnmap = TIVA_UART_UART4_RX_UDMA_MAPPING;
+  UARTD5.txchnmap = TIVA_UART_UART4_TX_UDMA_MAPPING;
+#endif
+#if TIVA_UART_USE_UART5
+  uartObjectInit(&UARTD6);
+  UARTD6.uart    = UART5_BASE;
+  UARTD6.dmarxnr = TIVA_UART_UART5_RX_UDMA_CHANNEL;
+  UARTD6.dmatxnr = TIVA_UART_UART5_TX_UDMA_CHANNEL;
+  UARTD6.rxchnmap = TIVA_UART_UART5_RX_UDMA_MAPPING;
+  UARTD6.txchnmap = TIVA_UART_UART5_TX_UDMA_MAPPING;
+#endif
+#if TIVA_UART_USE_UART6
+  uartObjectInit(&UARTD7);
+  UARTD7.uart    = UART6_BASE;
+  UARTD7.dmarxnr = TIVA_UART_UART6_RX_UDMA_CHANNEL;
+  UARTD7.dmatxnr = TIVA_UART_UART6_TX_UDMA_CHANNEL;
+  UARTD7.rxchnmap = TIVA_UART_UART6_RX_UDMA_MAPPING;
+  UARTD7.txchnmap = TIVA_UART_UART6_TX_UDMA_MAPPING;
+#endif
+#if TIVA_UART_USE_UART7
+  uartObjectInit(&UARTD8);
+  UARTD8.uart    = UART7_BASE;
+  UARTD8.dmarxnr = TIVA_UART_UART7_RX_UDMA_CHANNEL;
+  UARTD8.dmatxnr = TIVA_UART_UART7_TX_UDMA_CHANNEL;
+  UARTD8.rxchnmap = TIVA_UART_UART7_RX_UDMA_MAPPING;
+  UARTD8.txchnmap = TIVA_UART_UART7_TX_UDMA_MAPPING;
+#endif
+}
+
+/**
+ * @brief   Configures and activates the UART peripheral.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ *
+ * @notapi
+ */
+void uart_lld_start(UARTDriver *uartp) {
+
+  if (uartp->state == UART_STOP) {
+#if TIVA_UART_USE_UART0
+    if (&UARTD1 == uartp) {
+      bool b;
+      b = udmaChannelAllocate(uartp->dmarxnr);
+      osalDbgAssert(!b, "channel already allocated");
+      b = udmaChannelAllocate(uartp->dmatxnr);
+      osalDbgAssert(!b, "channel already allocated");
+
+      HWREG(SYSCTL_RCGCUART) |= (1 << 0);
+
+      while (!(HWREG(SYSCTL_PRUART) & (1 << 0)))
+        ;
+
+      nvicEnableVector(TIVA_UART0_NUMBER, TIVA_UART_UART0_PRIORITY);
+    }
+#endif
+#if TIVA_UART_USE_UART1
+    if (&UARTD2 == uartp) {
+      bool b;
+      b = udmaChannelAllocate(uartp->dmarxnr);
+      osalDbgAssert(!b, "channel already allocated");
+      b = udmaChannelAllocate(uartp->dmatxnr);
+      osalDbgAssert(!b, "channel already allocated");
+
+      HWREG(SYSCTL_RCGCUART) |= (1 << 1);
+
+      while (!(HWREG(SYSCTL_PRUART) & (1 << 1)))
+        ;
+
+      nvicEnableVector(TIVA_UART1_NUMBER, TIVA_UART_UART1_PRIORITY);
+    }
+#endif
+#if TIVA_UART_USE_UART2
+    if (&UARTD3 == uartp) {
+      bool b;
+      b = udmaChannelAllocate(uartp->dmarxnr);
+      osalDbgAssert(!b, "channel already allocated");
+      b = udmaChannelAllocate(uartp->dmatxnr);
+      osalDbgAssert(!b, "channel already allocated");
+
+      HWREG(SYSCTL_RCGCUART) |= (1 << 2);
+
+      while (!(HWREG(SYSCTL_PRUART) & (1 << 2)))
+        ;
+
+      nvicEnableVector(TIVA_UART2_NUMBER, TIVA_UART_UART2_PRIORITY);
+    }
+#endif
+#if TIVA_UART_USE_UART3
+    if (&UARTD4 == uartp) {
+      bool b;
+      b = udmaChannelAllocate(uartp->dmarxnr);
+      osalDbgAssert(!b, "channel already allocated");
+      b = udmaChannelAllocate(uartp->dmatxnr);
+      osalDbgAssert(!b, "channel already allocated");
+
+      HWREG(SYSCTL_RCGCUART) |= (1 << 3);
+
+      while (!(HWREG(SYSCTL_PRUART) & (1 << 3)))
+        ;
+
+      nvicEnableVector(TIVA_UART3_NUMBER, TIVA_UART_UART3_PRIORITY);
+    }
+#endif
+#if TIVA_UART_USE_UART4
+    if (&UARTD5 == uartp) {
+      bool b;
+      b = udmaChannelAllocate(uartp->dmarxnr);
+      osalDbgAssert(!b, "channel already allocated");
+      b = udmaChannelAllocate(uartp->dmatxnr);
+      osalDbgAssert(!b, "channel already allocated");
+
+      HWREG(SYSCTL_RCGCUART) |= (1 << 4);
+
+      while (!(HWREG(SYSCTL_PRUART) & (1 << 4)))
+        ;
+
+      nvicEnableVector(TIVA_UART4_NUMBER, TIVA_UART_UART4_PRIORITY);
+    }
+#endif
+#if TIVA_UART_USE_UART5
+    if (&UARTD6 == uartp) {
+      bool b;
+      b = udmaChannelAllocate(uartp->dmarxnr);
+      osalDbgAssert(!b, "channel already allocated");
+      b = udmaChannelAllocate(uartp->dmatxnr);
+      osalDbgAssert(!b, "channel already allocated");
+
+      HWREG(SYSCTL_RCGCUART) |= (1 << 5);
+
+      while (!(HWREG(SYSCTL_PRUART) & (1 << 5)))
+        ;
+
+      nvicEnableVector(TIVA_UART5_NUMBER, TIVA_UART_UART5_PRIORITY);
+    }
+#endif
+#if TIVA_UART_USE_UART6
+    if (&UARTD7 == uartp) {
+      bool b;
+      b = udmaChannelAllocate(uartp->dmarxnr);
+      osalDbgAssert(!b, "channel already allocated");
+      b = udmaChannelAllocate(uartp->dmatxnr);
+      osalDbgAssert(!b, "channel already allocated");
+
+      HWREG(SYSCTL_RCGCUART) |= (1 << 6);
+
+      while (!(HWREG(SYSCTL_PRUART) & (1 << 6)))
+        ;
+
+      nvicEnableVector(TIVA_UART6_NUMBER, TIVA_UART_UART6_PRIORITY);
+    }
+#endif
+#if TIVA_UART_USE_UART7
+    if (&UARTD8 == uartp) {
+      bool b;
+      b = udmaChannelAllocate(uartp->dmarxnr);
+      osalDbgAssert(!b, "channel already allocated");
+      b = udmaChannelAllocate(uartp->dmatxnr);
+      osalDbgAssert(!b, "channel already allocated");
+
+      HWREG(SYSCTL_RCGCUART) |= (1 << 7);
+
+      while (!(HWREG(SYSCTL_PRUART) & (1 << 7)))
+        ;
+
+      nvicEnableVector(TIVA_UART7_NUMBER, TIVA_UART_UART7_PRIORITY);
+    }
+#endif
+
+    uartp->rxbuf = 0;
+
+    HWREG(UDMA_CHMAP0 + (uartp->dmarxnr / 8) * 4) |= (uartp->rxchnmap << (uartp->dmarxnr % 8));
+    HWREG(UDMA_CHMAP0 + (uartp->dmatxnr / 8) * 4) |= (uartp->txchnmap << (uartp->dmatxnr % 8));
+  }
+
+  uartp->rxstate = UART_RX_IDLE;
+  uartp->txstate = UART_TX_IDLE;
+  uart_init(uartp);
+}
+
+/**
+ * @brief   Deactivates the UART peripheral.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ *
+ * @notapi
+ */
+void uart_lld_stop(UARTDriver *uartp) {
+
+  if (uartp->state == UART_READY) {
+    uart_stop(uartp);
+    udmaChannelRelease(uartp->dmarxnr);
+    udmaChannelRelease(uartp->dmatxnr);
+
+#if TIVA_UART_USE_UART0
+    if (&UARTD1 == uartp) {
+      HWREG(SYSCTL_RCGCUART) &= ~(1 << 0);
+      return;
+    }
+#endif
+#if TIVA_UART_USE_UART1
+    if (&UARTD2 == uartp) {
+      HWREG(SYSCTL_RCGCUART) &= ~(1 << 1);
+      return;
+    }
+#endif
+#if TIVA_UART_USE_UART2
+    if (&UARTD3 == uartp) {
+      HWREG(SYSCTL_RCGCUART) &= ~(1 << 2);
+      return;
+    }
+#endif
+#if TIVA_UART_USE_UART3
+    if (&UARTD4 == uartp) {
+      HWREG(SYSCTL_RCGCUART) &= ~(1 << 3);
+      return;
+    }
+#endif
+#if TIVA_UART_USE_UART4
+    if (&UARTD5 == uartp) {
+      HWREG(SYSCTL_RCGCUART) &= ~(1 << 4);
+      return;
+    }
+#endif
+#if TIVA_UART_USE_UART5
+    if (&UARTD6 == uartp) {
+      HWREG(SYSCTL_RCGCUART) &= ~(1 << 5);
+      return;
+    }
+#endif
+#if TIVA_UART_USE_UART6
+    if (&UARTD7 == uartp) {
+      HWREG(SYSCTL_RCGCUART) &= ~(1 << 6);
+      return;
+    }
+#endif
+#if TIVA_UART_USE_UART7
+    if (&UARTD8 == uartp) {
+      HWREG(SYSCTL_RCGCUART) &= ~(1 << 7);
+      return;
+    }
+#endif
+  }
+}
+
+/**
+ * @brief   Starts a transmission on the UART peripheral.
+ * @note    The buffers are organized as uint8_t arrays for data sizes below
+ *          or equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ * @param[in] n         number of data frames to send
+ * @param[in] txbuf     the pointer to the transmit buffer
+ *
+ * @notapi
+ */
+void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf)
+{
+  tiva_udma_table_entry_t *primary = udmaControlTable.primary;
+
+  /* TODO: This assert should be moved to the dma helper driver */
+  osalDbgAssert((uint32_t)txbuf >= SRAM_BASE, "txbuf should be in SRAM region.");
+
+  dmaChannelDisable(uartp->dmatxnr);
+
+  /* Configure for 8-bit transfers.*/
+  primary[uartp->dmatxnr].srcendp = (volatile void *)txbuf+n-1;
+  primary[uartp->dmatxnr].dstendp = (void *)(uartp->uart + UART_O_DR);
+  primary[uartp->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE |
+                                  UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_8 |
+                                  UDMA_CHCTL_ARBSIZE_4 |
+                                  UDMA_CHCTL_XFERSIZE(n) |
+                                  UDMA_CHCTL_XFERMODE_BASIC;
+
+  dmaChannelSingleBurst(uartp->dmatxnr);
+  dmaChannelPrimary(uartp->dmatxnr);
+  dmaChannelPriorityDefault(uartp->dmatxnr);
+  dmaChannelEnableRequest(uartp->dmatxnr);
+
+  /* Enable DMA channel, transfer starts immediately.*/
+  dmaChannelEnable(uartp->dmatxnr);
+}
+
+/**
+ * @brief   Stops any ongoing transmission.
+ * @note    Stopping a transmission also suppresses the transmission callbacks.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ *
+ * @return              The number of data frames not transmitted by the
+ *                      stopped transmit operation.
+ *
+ * @notapi
+ */
+size_t uart_lld_stop_send(UARTDriver *uartp)
+{
+  tiva_udma_table_entry_t *primary = udmaControlTable.primary;
+  uint16_t left;
+
+  dmaChannelDisable(uartp->dmatxnr);
+
+  left = ((primary[uartp->dmatxnr].chctl & UDMA_CHCTL_XFERSIZE_M) + 1) >> 4;
+
+  return left;
+}
+
+/**
+ * @brief   Starts a receive operation on the UART peripheral.
+ * @note    The buffers are organized as uint8_t arrays for data sizes below
+ *          or equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ * @param[in] n         number of data frames to send
+ * @param[out] rxbuf    the pointer to the receive buffer
+ *
+ * @notapi
+ */
+void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf)
+{
+  tiva_udma_table_entry_t *primary = udmaControlTable.primary;
+
+  /* TODO: This assert should be moved to the dma helper driver */
+  osalDbgAssert((uint32_t)rxbuf >= SRAM_BASE, "rxbuf should be in SRAM region.");
+
+  dmaChannelDisable(uartp->dmarxnr);
+
+  /* Configure for 8-bit transfers.*/
+  primary[uartp->dmarxnr].srcendp = (void *)(uartp->uart + UART_O_DR);
+  primary[uartp->dmarxnr].dstendp = (volatile void *)rxbuf+n-1;
+  primary[uartp->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 |
+                                  UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE |
+                                  UDMA_CHCTL_ARBSIZE_4 |
+                                  UDMA_CHCTL_XFERSIZE(n) |
+                                  UDMA_CHCTL_XFERMODE_BASIC;
+
+  dmaChannelSingleBurst(uartp->dmarxnr);
+  dmaChannelPrimary(uartp->dmarxnr);
+  dmaChannelPriorityDefault(uartp->dmarxnr);
+  dmaChannelEnableRequest(uartp->dmarxnr);
+
+  /* Enable DMA channel, transfer starts immediately.*/
+  dmaChannelEnable(uartp->dmarxnr);
+}
+
+/**
+ * @brief   Stops any ongoing receive operation.
+ * @note    Stopping a receive operation also suppresses the receive callbacks.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ *
+ * @return              The number of data frames not received by the
+ *                      stopped receive operation.
+ *
+ * @notapi
+ */
+size_t uart_lld_stop_receive(UARTDriver *uartp)
+{
+  tiva_udma_table_entry_t *primary = udmaControlTable.primary;
+  uint16_t left;
+
+  dmaChannelDisable(uartp->dmatxnr);
+
+  left = ((primary[uartp->dmatxnr].chctl & UDMA_CHCTL_XFERSIZE_M) + 1) >> 4;
+
+  uart_enter_rx_idle_loop(uartp);
+
+  return left;
+}
+
+#endif /* HAL_USE_UART */
+
+/** @} */
diff --git a/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.h b/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.h
new file mode 100644
index 0000000..1dc743b
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.h
@@ -0,0 +1,471 @@
+/*
+    Copyright (C) 2014..2017 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    UART/hal_uart_lld.h
+ * @brief   Tiva low level UART driver header.
+ *
+ * @addtogroup UART
+ * @{
+ */
+
+#ifndef HAL_UART_LLD_H
+#define HAL_UART_LLD_H
+
+#if HAL_USE_UART || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   UART driver on UART0 enable switch.
+ * @details If set to @p TRUE the support for UART0 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_UART_USE_UART0) || defined(__DOXYGEN__)
+#define TIVA_UART_USE_UART0               FALSE
+#endif
+
+/**
+ * @brief   UART driver on UART1 enable switch.
+ * @details If set to @p TRUE the support for UART1 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_UART_USE_UART1) || defined(__DOXYGEN__)
+#define TIVA_UART_USE_UART1               FALSE
+#endif
+
+/**
+ * @brief   UART driver on UART2 enable switch.
+ * @details If set to @p TRUE the support for UART2 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_UART_USE_UART2) || defined(__DOXYGEN__)
+#define TIVA_UART_USE_UART2               FALSE
+#endif
+
+/**
+ * @brief   UART driver on UART3 enable switch.
+ * @details If set to @p TRUE the support for UART3 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_UART_USE_UART3) || defined(__DOXYGEN__)
+#define TIVA_UART_USE_UART3               FALSE
+#endif
+
+/**
+ * @brief   UART driver on UART4 enable switch.
+ * @details If set to @p TRUE the support for UART4 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_UART_USE_UART4) || defined(__DOXYGEN__)
+#define TIVA_UART_USE_UART4               FALSE
+#endif
+
+/**
+ * @brief   UART driver on UART5 enable switch.
+ * @details If set to @p TRUE the support for UART5 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_UART_USE_UART5) || defined(__DOXYGEN__)
+#define TIVA_UART_USE_UART5               FALSE
+#endif
+
+/**
+ * @brief   UART driver on UART6 enable switch.
+ * @details If set to @p TRUE the support for UART6 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_UART_USE_UART6) || defined(__DOXYGEN__)
+#define TIVA_UART_USE_UART6               FALSE
+#endif
+
+/**
+ * @brief   UART driver on UART7 enable switch.
+ * @details If set to @p TRUE the support for UART7 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_UART_USE_UART7) || defined(__DOXYGEN__)
+#define TIVA_UART_USE_UART7               FALSE
+#endif
+
+/**
+ * @brief   UART0 interrupt priority level setting.
+ */
+#if !defined(TIVA_UART_UART0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_UART_UART0_IRQ_PRIORITY      5
+#endif
+
+/**
+ * @brief   UART1 interrupt priority level setting.
+ */
+#if !defined(TIVA_UART_UART1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_UART_UART1_IRQ_PRIORITY      5
+#endif
+
+/**
+ * @brief   UART2 interrupt priority level setting.
+ */
+#if !defined(TIVA_UART_UART2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_UART_UART2_IRQ_PRIORITY      5
+#endif
+
+/**
+ * @brief   UART3 interrupt priority level setting.
+ */
+#if !defined(TIVA_UART_UART3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_UART_UART3_IRQ_PRIORITY      5
+#endif
+
+/**
+ * @brief   UART4 interrupt priority level setting.
+ */
+#if !defined(TIVA_UART_UART4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_UART_UART4_IRQ_PRIORITY      5
+#endif
+
+/**
+ * @brief   UART5 interrupt priority level setting.
+ */
+#if !defined(TIVA_UART_UART5_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_UART_UART5_IRQ_PRIORITY      5
+#endif
+
+/**
+ * @brief   UART6 interrupt priority level setting.
+ */
+#if !defined(TIVA_UART_UART6_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_UART_UART6_IRQ_PRIORITY      5
+#endif
+
+/**
+ * @brief   UART7 interrupt priority level setting.
+ */
+#if !defined(TIVA_UART_UART7_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_UART_UART7_IRQ_PRIORITY      5
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if TIVA_UART_USE_UART0 && !TIVA_HAS_UART0
+#error "UART0 not present in the selected device"
+#endif
+
+#if TIVA_UART_USE_UART1 && !TIVA_HAS_UART1
+#error "UART1 not present in the selected device"
+#endif
+
+#if TIVA_UART_USE_UART2 && !TIVA_HAS_UART2
+#error "UART2 not present in the selected device"
+#endif
+
+#if TIVA_UART_USE_UART3 && !TIVA_HAS_UART3
+#error "UART3 not present in the selected device"
+#endif
+
+#if TIVA_UART_USE_UART4 && !TIVA_HAS_UART4
+#error "UART4 not present in the selected device"
+#endif
+
+#if TIVA_UART_USE_UART5 && !TIVA_HAS_UART5
+#error "UART5 not present in the selected device"
+#endif
+
+#if TIVA_UART_USE_UART6 && !TIVA_HAS_UART6
+#error "UART6 not present in the selected device"
+#endif
+
+#if TIVA_UART_USE_UART7 && !TIVA_HAS_UART7
+#error "UART7 not present in the selected device"
+#endif
+
+#if !TIVA_UART_USE_UART0 && !TIVA_UART_USE_UART1 && !TIVA_UART_USE_UART2 && \
+    !TIVA_UART_USE_UART3 && !TIVA_UART_USE_UART4 && !TIVA_UART_USE_UART5 && \
+    !TIVA_UART_USE_UART6 && !TIVA_UART_USE_UART7
+#error "UART driver activated but no UART peripheral assigned"
+#endif
+
+#if TIVA_UART_USE_UART0 &&                                                \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART0_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to UART0"
+#endif
+
+#if TIVA_UART_USE_UART1 &&                                                \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to UART1"
+#endif
+
+#if TIVA_UART_USE_UART2 &&                                                \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to UART2"
+#endif
+
+#if TIVA_UART_USE_UART3 &&                                                \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to UART3"
+#endif
+
+#if TIVA_UART_USE_UART4 &&                                                \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART4_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to UART4"
+#endif
+
+#if TIVA_UART_USE_UART5 &&                                                \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART5_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to UART5"
+#endif
+
+#if TIVA_UART_USE_UART6 &&                                                \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART6_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to UART6"
+#endif
+
+#if TIVA_UART_USE_UART7 &&                                                \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART7_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to UART7"
+#endif
+
+#if !defined(TIVA_UDMA_REQUIRED)
+#define TIVA_UDMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   UART driver condition flags type.
+ */
+typedef uint32_t uartflags_t;
+
+/**
+ * @brief   Structure representing an UART driver.
+ */
+typedef struct UARTDriver UARTDriver;
+
+/**
+ * @brief   Generic UART notification callback type.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ */
+typedef void (*uartcb_t)(UARTDriver *uartp);
+
+/**
+ * @brief   Character received UART notification callback type.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ * @param[in] c         received character
+ */
+typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c);
+
+/**
+ * @brief   Receive error UART notification callback type.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ * @param[in] e         receive error mask
+ */
+typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e);
+
+/**
+ * @brief   Driver configuration structure.
+ * @note    It could be empty on some architectures.
+ */
+typedef struct {
+  /**
+   * @brief   End of transmission buffer callback.
+   */
+  uartcb_t                  txend1_cb;
+  /**
+   * @brief   Physical end of transmission callback.
+   */
+  uartcb_t                  txend2_cb;
+  /**
+   * @brief   Receive buffer filled callback.
+   */
+  uartcb_t                  rxend_cb;
+  /**
+   * @brief   Character received while out if the @p UART_RECEIVE state.
+   */
+  uartccb_t                 rxchar_cb;
+  /**
+   * @brief   Receive error callback.
+   */
+  uartecb_t                 rxerr_cb;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Bit rate.
+   */
+  uint32_t                  speed;
+  /* End of the mandatory fields. */
+  /**
+   * @brief Initialization value for the CTL register.
+   */
+  uint16_t                  ctl;
+  /**
+   * @brief Initialization value for the LCRH register.
+   */
+  uint8_t                   lcrh;
+  /**
+   * @brief Initialization value for the IFLS register.
+   */
+  uint8_t                   ifls;
+  /**
+   * @brief Initialization value for the CC register.
+   */
+  uint8_t                   cc;
+} UARTConfig;
+
+/**
+ * @brief   Structure representing an UART driver.
+ */
+struct UARTDriver {
+  /**
+   * @brief   Driver state.
+   */
+  uartstate_t               state;
+  /**
+   * @brief   Transmitter state.
+   */
+  uarttxstate_t             txstate;
+  /**
+   * @brief   Receiver state.
+   */
+  uartrxstate_t             rxstate;
+  /**
+   * @brief   Current configuration data.
+   */
+  const UARTConfig          *config;
+#if (UART_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+  /**
+   * @brief   Synchronization flag for transmit operations.
+   */
+  bool                      early;
+  /**
+   * @brief   Waiting thread on RX.
+   */
+  thread_reference_t        threadrx;
+  /**
+   * @brief   Waiting thread on TX.
+   */
+  thread_reference_t        threadtx;
+#endif /* UART_USE_WAIT */
+#if (UART_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__)
+  /**
+   * @brief   Mutex protecting the peripheral.
+   */
+  mutex_t                   mutex;
+#endif /* UART_USE_MUTUAL_EXCLUSION */
+#if defined(UART_DRIVER_EXT_FIELDS)
+  UART_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Pointer to the UART registers block.
+   */
+  uint32_t                  uart;
+  /**
+   * @brief Receive DMA channel number.
+   */
+  uint8_t                   dmarxnr;
+  /**
+   * @brief Transmit DMA channel number.
+   */
+  uint8_t                   dmatxnr;
+  /**
+   * @brief Receive DMA channel map.
+   */
+  uint8_t                   rxchnmap;
+  /**
+   * @brief Transmit DMA channel map.
+   */
+  uint8_t                   txchnmap;
+  /**
+   * @brief   Default receive buffer while into @p UART_RX_IDLE state.
+   */
+  volatile uint16_t         rxbuf;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if TIVA_UART_USE_UART0 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD1;
+#endif
+
+#if TIVA_UART_USE_UART1 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD2;
+#endif
+
+#if TIVA_UART_USE_UART2 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD3;
+#endif
+
+#if TIVA_UART_USE_UART3 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD4;
+#endif
+
+#if TIVA_UART_USE_UART4 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD5;
+#endif
+
+#if TIVA_UART_USE_UART5 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD6;
+#endif
+
+#if TIVA_UART_USE_UART6 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD7;
+#endif
+
+#if TIVA_UART_USE_UART7 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD8;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void uart_lld_init(void);
+  void uart_lld_start(UARTDriver *uartp);
+  void uart_lld_stop(UARTDriver *uartp);
+  void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf);
+  size_t uart_lld_stop_send(UARTDriver *uartp);
+  void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf);
+  size_t uart_lld_stop_receive(UARTDriver *uartp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_UART */
+
+#endif /* HAL_UART_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/TIVA/LLD/WDT/driver.mk b/os/hal/ports/TIVA/LLD/WDT/driver.mk
new file mode 100644
index 0000000..867d0e6
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/WDT/driver.mk
@@ -0,0 +1,9 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c
+endif
+else
+PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c
+endif
+
+PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/WDT
diff --git a/os/hal/ports/TIVA/LLD/hal_wdg_lld.c b/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c
index 38dcef0..705fce6 100644
--- a/os/hal/ports/TIVA/LLD/hal_wdg_lld.c
+++ b/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -16,7 +16,7 @@
 
 
 /**
- * @file    TIVA/wdg_lld.c
+ * @file    WDT/hal_wdg_lld.c
  * @brief   WDG Driver subsystem low level driver source.
  *
  * @addtogroup WDG
@@ -60,14 +60,14 @@ static void serve_interrupt(WDGDriver *wdgp)
 {
   uint32_t mis;
 
-  mis = wdgp->wdt->MIS;
+  mis = HWREG(wdgp->wdt + WDT_O_MIS);
 
-  if (mis & MIS_WDTMIS) {
+  if (mis & WDT_MIS_WDTMIS) {
     /* Invoke callback, if any */
     if (wdgp->config->callback) {
       if (wdgp->config->callback(wdgp)) {
         /* Clear interrupt */
-        wdgp->wdt->ICR = 0;
+        HWREG(wdgp->wdt + WDT_O_ICR) = 0;
         wdgTivaSyncWrite(wdgp);
       }
     }
@@ -113,12 +113,12 @@ void wdg_lld_init(void)
 {
 #if TIVA_WDG_USE_WDT0
   WDGD1.state = WDG_STOP;
-  WDGD1.wdt = WDT0;
+  WDGD1.wdt = WATCHDOG0_BASE;
 #endif /* TIVA_WDG_USE_WDT0 */
 
 #if TIVA_WDG_USE_WDT1
   WDGD2.state = WDG_STOP;
-  WDGD2.wdt = WDT1;
+  WDGD2.wdt = WATCHDOG1_BASE;
 #endif /* TIVA_WDG_USE_WDT1 */
 
   /* The shared vector is initialized on driver initialization and never
@@ -137,32 +137,32 @@ void wdg_lld_start(WDGDriver *wdgp)
 {
 #if TIVA_WDG_USE_WDT0
   if (&WDGD1 == wdgp) {
-    SYSCTL->RCGCWD |= (1 << 0);
+    HWREG(SYSCTL_RCGCWD) |= (1 << 0);
 
-    while (!(SYSCTL->PRWD & (1 << 0)))
+    while (!(HWREG(SYSCTL_PRWD) & (1 << 0)))
       ;
   }
 #endif /* TIVA_WDG_USE_WDT0 */
 
 #if TIVA_WDG_USE_WDT1
   if (&WDGD2 == wdgp) {
-    SYSCTL->RCGCWD |= (1 << 1);
+    HWREG(SYSCTL_RCGCWD) |= (1 << 1);
 
-    while (!(SYSCTL->PRWD & (1 << 1)))
+    while (!(HWREG(SYSCTL_PRWD) & (1 << 1)))
       ;
   }
 #endif /* TIVA_WDG_USE_WDT1 */
 
-  wdgp->wdt->LOAD = wdgp->config->load;
+  HWREG(wdgp->wdt + WDT_O_LOAD) = wdgp->config->load;
   wdgTivaSyncWrite(wdgp);
 
-  wdgp->wdt->TEST = wdgp->config->test;
+  HWREG(wdgp->wdt + WDT_O_TEST) = wdgp->config->test;
   wdgTivaSyncWrite(wdgp);
 
-  wdgp->wdt->CTL |= CTL_RESEN;
+  HWREG(wdgp->wdt + WDT_O_CTL) |= WDT_CTL_RESEN;
   wdgTivaSyncWrite(wdgp);
 
-  wdgp->wdt->CTL |= CTL_INTEN;
+  HWREG(wdgp->wdt + WDT_O_CTL) |= WDT_CTL_INTEN;
   wdgTivaSyncWrite(wdgp);
 }
 
@@ -177,15 +177,15 @@ void wdg_lld_stop(WDGDriver *wdgp)
 {
 #if TIVA_WDG_USE_WDT0
   if (&WDGD1 == wdgp) {
-    SYSCTL->SRWD |= (1 << 0);
-    SYSCTL->SRWD &= ~(1 << 0);
+    HWREG(SYSCTL_SRWD) |= (1 << 0);
+    HWREG(SYSCTL_SRWD) &= ~(1 << 0);
   }
 #endif /* TIVA_WDG_USE_WDT0 */
 
 #if TIVA_WDG_USE_WDT1
   if (&WDGD2 == wdgp) {
-    SYSCTL->SRWD |= (1 << 1);
-    SYSCTL->SRWD &= ~(1 << 1);
+    HWREG(SYSCTL_SRWD) |= (1 << 1);
+    HWREG(SYSCTL_SRWD) &= ~(1 << 1);
   }
 #endif /* TIVA_WDG_USE_WDT1 */
 }
@@ -219,7 +219,7 @@ void wdg_lld_reset(WDGDriver *wdgp)
 
 #endif /* defined(TM4C123_USE_REVISION_6_FIX) ||
           defined(TM4C123_USE_REVISION_7_FIX) */
-  wdgp->wdt->LOAD = wdgp->config->load;
+  HWREG(wdgp->wdt + WDT_O_LOAD) = wdgp->config->load;
   wdgTivaSyncWrite(wdgp);
 }
 
@@ -234,7 +234,7 @@ void wdg_lld_reset(WDGDriver *wdgp)
 void wdgTivaSyncWrite(WDGDriver *wdgp)
 {
   if (&WDGD2 == wdgp) {
-    while (!(wdgp->wdt->CTL & CTL_WRC)) {
+    while (!(HWREG(wdgp->wdt + WDT_O_CTL) & CTL_WRC)) {
       ;
     }
   }
diff --git a/os/hal/ports/TIVA/LLD/hal_wdg_lld.h b/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.h
index f88fa26..0f694c5 100644
--- a/os/hal/ports/TIVA/LLD/hal_wdg_lld.h
+++ b/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.h
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -16,7 +16,7 @@
 
 
 /**
- * @file    TIVA/wdg_lld.h
+ * @file    WDT/hal_wdg_lld.h
  * @brief   WDG Driver subsystem low level driver header.
  *
  * @addtogroup WDG
@@ -32,23 +32,6 @@
 /* Driver constants.                                                         */
 /*===========================================================================*/
 
-#define LOCK_UNLOCK        0x1ACCE551U
-#define LOCK_LOCK          0x00000000U
-
-#define LOCK_IS_UNLOCKED   0U
-#define LOCK_IS_LOCKED     1U
-
-#define TEST_STALL         (1 << 8)
-
-#define MIS_WDTMIS         (1 << 0)
-#define RIS_WDTRIS         (1 << 0)
-#define ICR_WDTICR         (1 << 0)
-
-#define CTL_INTEN          (1 << 0)
-#define CTL_RESEN          (1 << 1)
-#define CTL_INTTYPE        (1 << 2)
-#define CTL_WRC            (1 << 31)
-
 /*===========================================================================*/
 /* Driver pre-compile time settings.                                         */
 /*===========================================================================*/
@@ -146,7 +129,7 @@ struct WDGDriver
   /**
    * @brief   Pointer to the WDT registers block.
    */
-  WDT_TypeDef               *wdt;
+  uint32_t                  wdt;
 };
 
 /*===========================================================================*/
diff --git a/os/hal/ports/TIVA/LLD/hal_ext_lld.c b/os/hal/ports/TIVA/LLD/hal_ext_lld.c
deleted file mode 100644
index efe6421..0000000
--- a/os/hal/ports/TIVA/LLD/hal_ext_lld.c
+++ /dev/null
@@ -1,981 +0,0 @@
-/*
-    Copyright (C) 2014..2016 Marco Veeneman
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    Tiva/ext_lld.c
- * @brief   Tiva EXT subsystem low level driver source.
- *
- * @addtogroup EXT
- * @{
- */
-
-#include "hal.h"
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/**
- * @brief   Generic interrupt serving code for multiple pins per interrupt
- *          handler.
- */
-#define ext_lld_serve_port_interrupt(gpiop, start)                            \
-  do {                                                                        \
-    uint32_t mis = gpiop->MIS;                                                \
-                                                                              \
-    gpiop->ICR = mis;                                                         \
-                                                                              \
-    if (mis & (1 << 0)) {                                                     \
-      EXTD1.config->channels[start + 0].cb(&EXTD1, start + 0);                \
-    }                                                                         \
-    if (mis & (1 << 1)) {                                                     \
-      EXTD1.config->channels[start + 1].cb(&EXTD1, start + 1);                \
-    }                                                                         \
-    if (mis & (1 << 2)) {                                                     \
-      EXTD1.config->channels[start + 2].cb(&EXTD1, start + 2);                \
-    }                                                                         \
-    if (mis & (1 << 3)) {                                                     \
-      EXTD1.config->channels[start + 3].cb(&EXTD1, start + 3);                \
-    }                                                                         \
-    if (mis & (1 << 4)) {                                                     \
-      EXTD1.config->channels[start + 4].cb(&EXTD1, start + 4);                \
-    }                                                                         \
-    if (mis & (1 << 5)) {                                                     \
-      EXTD1.config->channels[start + 5].cb(&EXTD1, start + 5);                \
-    }                                                                         \
-    if (mis & (1 << 6)) {                                                     \
-      EXTD1.config->channels[start + 6].cb(&EXTD1, start + 6);                \
-    }                                                                         \
-    if (mis & (1 << 7)) {                                                     \
-      EXTD1.config->channels[start + 7].cb(&EXTD1, start + 7);                \
-    }                                                                         \
-  } while (0);
-
-/**
- * @brief   Generic interrupt serving code for single pin per interrupt
- *          handler.
- */
-#define ext_lld_serve_pin_interrupt(gpiop, start, pin)                        \
-  do {                                                                        \
-    gpiop->ICR = (1 << pin);                                                  \
-    EXTD1.config->channels[start].cb(&EXTD1, start);                          \
-  } while (0);
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   EXTD1 driver identifier.
- */
-EXTDriver EXTD1;
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-const ioportid_t gpio[] =
-{
-#if TIVA_HAS_GPIOA
-  GPIOA,
-#endif
-#if TIVA_HAS_GPIOB
-  GPIOB,
-#endif
-#if TIVA_HAS_GPIOC
-  GPIOC,
-#endif
-#if TIVA_HAS_GPIOD
-  GPIOD,
-#endif
-#if TIVA_HAS_GPIOE
-  GPIOE,
-#endif
-#if TIVA_HAS_GPIOF
-  GPIOF,
-#endif
-#if TIVA_HAS_GPIOG
-  GPIOG,
-#endif
-#if TIVA_HAS_GPIOH
-  GPIOH,
-#endif
-#if TIVA_HAS_GPIOJ
-  GPIOJ,
-#endif
-#if TIVA_HAS_GPIOK
-  GPIOK,
-#endif
-#if TIVA_HAS_GPIOL
-  GPIOL,
-#endif
-#if TIVA_HAS_GPIOM
-  GPIOM,
-#endif
-#if TIVA_HAS_GPION
-  GPION,
-#endif
-#if TIVA_HAS_GPIOP
-  GPIOP,
-#endif
-#if TIVA_HAS_GPIOQ
-  GPIOQ,
-#endif
-#if TIVA_HAS_GPIOR
-  GPIOR,
-#endif
-#if TIVA_HAS_GPIOS
-  GPIOS,
-#endif
-#if TIVA_HAS_GPIOT
-  GPIOT,
-#endif
-};
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Enables GPIO IRQ sources.
- *
- * @notapi
- */
-static void ext_lld_irq_enable(void)
-{
-#if TIVA_HAS_GPIOA
-  nvicEnableVector(TIVA_GPIOA_NUMBER, TIVA_EXT_GPIOA_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOB
-  nvicEnableVector(TIVA_GPIOB_NUMBER, TIVA_EXT_GPIOB_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOC
-  nvicEnableVector(TIVA_GPIOC_NUMBER, TIVA_EXT_GPIOC_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOD
-  nvicEnableVector(TIVA_GPIOD_NUMBER, TIVA_EXT_GPIOD_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOE
-  nvicEnableVector(TIVA_GPIOE_NUMBER, TIVA_EXT_GPIOE_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOF
-  nvicEnableVector(TIVA_GPIOF_NUMBER, TIVA_EXT_GPIOF_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOG
-  nvicEnableVector(TIVA_GPIOG_NUMBER, TIVA_EXT_GPIOG_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOH
-  nvicEnableVector(TIVA_GPIOH_NUMBER, TIVA_EXT_GPIOH_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOJ
-  nvicEnableVector(TIVA_GPIOJ_NUMBER, TIVA_EXT_GPIOJ_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOK
-  nvicEnableVector(TIVA_GPIOK_NUMBER, TIVA_EXT_GPIOK_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOL
-  nvicEnableVector(TIVA_GPIOL_NUMBER, TIVA_EXT_GPIOL_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOM
-  nvicEnableVector(TIVA_GPIOM_NUMBER, TIVA_EXT_GPIOM_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPION
-  nvicEnableVector(TIVA_GPION_NUMBER, TIVA_EXT_GPION_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOP
-  nvicEnableVector(TIVA_GPIOP0_NUMBER, TIVA_EXT_GPIOP0_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOP1_NUMBER, TIVA_EXT_GPIOP1_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOP2_NUMBER, TIVA_EXT_GPIOP2_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOP3_NUMBER, TIVA_EXT_GPIOP3_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOP4_NUMBER, TIVA_EXT_GPIOP4_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOP5_NUMBER, TIVA_EXT_GPIOP5_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOP6_NUMBER, TIVA_EXT_GPIOP6_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOP7_NUMBER, TIVA_EXT_GPIOP7_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOQ
-  nvicEnableVector(TIVA_GPIOQ0_NUMBER, TIVA_EXT_GPIOQ0_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOQ1_NUMBER, TIVA_EXT_GPIOQ1_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOQ2_NUMBER, TIVA_EXT_GPIOQ2_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOQ3_NUMBER, TIVA_EXT_GPIOQ3_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOQ4_NUMBER, TIVA_EXT_GPIOQ4_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOQ5_NUMBER, TIVA_EXT_GPIOQ5_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOQ6_NUMBER, TIVA_EXT_GPIOQ6_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOQ7_NUMBER, TIVA_EXT_GPIOQ7_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOR
-  nvicEnableVector(TIVA_GPIOR_NUMBER, TIVA_EXT_GPIOR_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOS
-  nvicEnableVector(TIVA_GPIOS_NUMBER, TIVA_EXT_GPIOS_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOT
-  nvicEnableVector(TIVA_GPIOT_NUMBER, TIVA_EXT_GPIOT_IRQ_PRIORITY);
-#endif
-}
-
-/**
- * @brief   Disables GPIO IRQ sources.
- *
- * @notapi
- */
-static void ext_lld_irq_disable(void)
-{
-#if TIVA_HAS_GPIOA
-  nvicDisableVector(TIVA_GPIOA_NUMBER);
-#endif
-#if TIVA_HAS_GPIOB
-  nvicDisableVector(TIVA_GPIOB_NUMBER);
-#endif
-#if TIVA_HAS_GPIOC
-  nvicDisableVector(TIVA_GPIOC_NUMBER);
-#endif
-#if TIVA_HAS_GPIOD
-  nvicDisableVector(TIVA_GPIOD_NUMBER);
-#endif
-#if TIVA_HAS_GPIOE
-  nvicDisableVector(TIVA_GPIOE_NUMBER);
-#endif
-#if TIVA_HAS_GPIOF
-  nvicDisableVector(TIVA_GPIOF_NUMBER);
-#endif
-#if TIVA_HAS_GPIOG
-  nvicDisableVector(TIVA_GPIOG_NUMBER);
-#endif
-#if TIVA_HAS_GPIOH
-  nvicDisableVector(TIVA_GPIOH_NUMBER);
-#endif
-#if TIVA_HAS_GPIOJ
-  nvicDisableVector(TIVA_GPIOJ_NUMBER);
-#endif
-#if TIVA_HAS_GPIOK
-  nvicDisableVector(TIVA_GPIOK_NUMBER);
-#endif
-#if TIVA_HAS_GPIOL
-  nvicDisableVector(TIVA_GPIOL_NUMBER);
-#endif
-#if TIVA_HAS_GPIOM
-  nvicDisableVector(TIVA_GPIOM_NUMBER);
-#endif
-#if TIVA_HAS_GPION
-  nvicDisableVector(TIVA_GPION_NUMBER);
-#endif
-#if TIVA_HAS_GPIOP
-  nvicDisableVector(TIVA_GPIOP0_NUMBER);
-  nvicDisableVector(TIVA_GPIOP1_NUMBER);
-  nvicDisableVector(TIVA_GPIOP2_NUMBER);
-  nvicDisableVector(TIVA_GPIOP3_NUMBER);
-  nvicDisableVector(TIVA_GPIOP4_NUMBER);
-  nvicDisableVector(TIVA_GPIOP5_NUMBER);
-  nvicDisableVector(TIVA_GPIOP6_NUMBER);
-  nvicDisableVector(TIVA_GPIOP7_NUMBER);
-#endif
-#if TIVA_HAS_GPIOQ
-  nvicDisableVector(TIVA_GPIOQ0_NUMBER);
-  nvicDisableVector(TIVA_GPIOQ1_NUMBER);
-  nvicDisableVector(TIVA_GPIOQ2_NUMBER);
-  nvicDisableVector(TIVA_GPIOQ3_NUMBER);
-  nvicDisableVector(TIVA_GPIOQ4_NUMBER);
-  nvicDisableVector(TIVA_GPIOQ5_NUMBER);
-  nvicDisableVector(TIVA_GPIOQ6_NUMBER);
-  nvicDisableVector(TIVA_GPIOQ7_NUMBER);
-#endif
-#if TIVA_HAS_GPIOR
-  nvicDisableVector(TIVA_GPIOR_NUMBER);
-#endif
-#if TIVA_HAS_GPIOS
-  nvicDisableVector(TIVA_GPIOS_NUMBER);
-#endif
-#if TIVA_HAS_GPIOT
-  nvicDisableVector(TIVA_GPIOT_NUMBER);
-#endif
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if TIVA_HAS_GPIOA || defined(__DOXYGEN__)
-/**
- * @brief   GPIOA interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOA_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(GPIOA, 0);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOB || defined(__DOXYGEN__)
-/**
- * @brief   GPIOB interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOB_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(GPIOB, 8);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOC || defined(__DOXYGEN__)
-/**
- * @brief   GPIOC interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOC_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(GPIOC, 16);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOD || defined(__DOXYGEN__)
-/**
- * @brief   GPIOD interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOD_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(GPIOD, 24);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOE || defined(__DOXYGEN__)
-/**
- * @brief   GPIOE interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOE_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(GPIOE, 32);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOF || defined(__DOXYGEN__)
-/**
- * @brief   GPIOF interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOF_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(GPIOF, 40);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
-/**
- * @brief   GPIOG interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOG_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(&GPIOG, 48);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
-/**
- * @brief   GPIOH interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOH_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(&GPIOH, 56);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
-/**
- * @brief   GPIOJ interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOJ_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(&GPIOJ, 64);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
-/**
- * @brief   GPIOK interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOK_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(&GPIOK, 72);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
-/**
- * @brief   GPIOL interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOL_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(&GPIOL, 80);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
-/**
- * @brief   GPIOM interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOM_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(&GPIOM, 88);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPION || defined(__DOXYGEN__)
-/**
- * @brief   GPION interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPION_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(&GPION, 96);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
-/**
- * @brief   GPIOP0 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOP0_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOP, 104, 0);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   GPIOP1 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOP1_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOP, 105, 1);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   GPIOP2 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOP2_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOP, 106, 2);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   GPIOP3 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOP3_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOP, 107, 3);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   GPIOP4 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOP4_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOP, 108, 4);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   GPIOP5 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOP5_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOP, 109, 5);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   GPIOP6 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOP6_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOP, 110, 6);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   GPIOP7 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOP7_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOP, 111, 7);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
-/**
- * @brief   GPIOQ0 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOQ0_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOQ, 112, 0);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   GPIOQ1 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOQ1_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOQ, 113, 1);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   GPIOQ2 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOQ2_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOQ, 114, 2);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   GPIOQ3 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOQ3_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOQ, 115, 3);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   GPIOQ4 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOQ4_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOQ, 116, 4);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   GPIOQ5 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOQ5_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOQ, 117, 5);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   GPIOQ6 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOQ6_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOQ, 118, 6);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   GPIOQ7 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOQ7_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOQ, 119, 7);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
-/**
- * @brief   GPIOR interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOR_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(&GPIOR, 120);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
-/**
- * @brief   GPIOS interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOS_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(&GPIOS, 128);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
-/**
- * @brief   GPIOT interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOT_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(&GPIOT, 132);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level EXT driver initialization.
- *
- * @notapi
- */
-void ext_lld_init(void)
-{
-  extObjectInit(&EXTD1);
-}
-
-/**
- * @brief   Configures and activates the EXT peripheral.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- *
- * @notapi
- */
-void ext_lld_start(EXTDriver *extp)
-{
-  uint8_t i;
-
-  if (extp->state == EXT_STOP) {
-    ext_lld_irq_enable();
-  }
-
-  /* Configuration of automatic channels.*/
-  for (i = 0; i < EXT_MAX_CHANNELS; i++) {
-    if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART) {
-      ext_lld_channel_enable(extp, i);
-    }
-    else {
-      ext_lld_channel_disable(extp, i);
-    }
-  }
-}
-
-/**
- * @brief   Deactivates the EXT peripheral.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- *
- * @notapi
- */
-void ext_lld_stop(EXTDriver *extp)
-{
-  if (extp->state == EXT_ACTIVE) {
-    ext_lld_irq_disable();
-  }
-
-#if TIVA_HAS_GPIOA
-  GPIOA->IM = 0;
-#endif
-#if TIVA_HAS_GPIOB
-  GPIOB->IM = 0;
-#endif
-#if TIVA_HAS_GPIOC
-  GPIOC->IM = 0;
-#endif
-#if TIVA_HAS_GPIOD
-  GPIOD->IM = 0;
-#endif
-#if TIVA_HAS_GPIOE
-  GPIOE->IM = 0;
-#endif
-#if TIVA_HAS_GPIOF
-  GPIOF->IM = 0;
-#endif
-#if TIVA_HAS_GPIOG
-  GPIOG->IM = 0;
-#endif
-#if TIVA_HAS_GPIOH
-  GPIOH->IM = 0;
-#endif
-#if TIVA_HAS_GPIOJ
-  GPIOJ->IM = 0;
-#endif
-#if TIVA_HAS_GPIOK
-  GPIOK->IM = 0;
-#endif
-#if TIVA_HAS_GPIOL
-  GPIOL->IM = 0;
-#endif
-#if TIVA_HAS_GPIOM
-  GPIOM->IM = 0;
-#endif
-#if TIVA_HAS_GPION
-  GPION->IM = 0;
-#endif
-#if TIVA_HAS_GPIOP
-  GPIOP->IM = 0;
-#endif
-#if TIVA_HAS_GPIOQ
-  GPIOQ->IM = 0;
-#endif
-#if TIVA_HAS_GPIOR
-  GPIOR->IM = 0;
-#endif
-#if TIVA_HAS_GPIOS
-  GPIOS->IM = 0;
-#endif
-#if TIVA_HAS_GPIOT
-  GPIOT->IM = 0;
-#endif
-}
-
-/**
- * @brief   Enables an EXT channel.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- * @param[in] channel   channel to be enabled
- *
- * @notapi
- */
-void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel)
-{
-  GPIO_TypeDef *gpiop;
-  uint8_t pin;
-  uint32_t im;
-
-  pin = channel & 0x07;
-  gpiop = gpio[channel >> 3];
-
-  /* Disable interrupts */
-  im = gpiop->IM;
-  gpiop->IM = 0;
-
-  /* Configure pin to be edge-sensitive.*/
-  gpiop->IS &= ~(1 << pin);
-
-  /* Programming edge registers.*/
-  if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) ==
-      EXT_CH_MODE_BOTH_EDGES) {
-    gpiop->IBE |= (1 << pin);
-  }
-  else if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) ==
-      EXT_CH_MODE_FALLING_EDGE) {
-    gpiop->IBE &= ~(1 << pin);
-    gpiop->IEV &= ~(1 << pin);
-  }
-  else if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) ==
-      EXT_CH_MODE_RISING_EDGE) {
-    gpiop->IBE &= ~(1 << pin);
-    gpiop->IEV |= (1 << pin);
-  }
-
-  /* Programming interrupt and event registers.*/
-  if ((extp->config->channels[channel].cb != NULL) &&
-      ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) !=
-          EXT_CH_MODE_DISABLED)) {
-    im |= (1 << pin);
-  }
-  else {
-    im &= ~(1 << pin);
-  }
-
-  /* Restore interrupts */
-  gpiop->IM = im;
-}
-
-/**
- * @brief   Disables an EXT channel.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- * @param[in] channel   channel to be disabled
- *
- * @notapi
- */
-void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel)
-{
-  (void)extp;
-  GPIO_TypeDef *gpiop;
-  uint8_t pin;
-
-  pin = channel & 0x07;
-  gpiop = gpio[channel >> 3];
-
-  gpiop->IM &= ~(1 << pin);
-}
-
-#endif /* HAL_USE_EXT */
-
-/** @} */
diff --git a/os/hal/ports/TIVA/LLD/hal_ext_lld.h b/os/hal/ports/TIVA/LLD/hal_ext_lld.h
deleted file mode 100644
index 08accb2..0000000
--- a/os/hal/ports/TIVA/LLD/hal_ext_lld.h
+++ /dev/null
@@ -1,523 +0,0 @@
-/*
-    Copyright (C) 2014..2016 Marco Veeneman
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    Tiva/ext_lld.h
- * @brief   Tiva EXT subsystem low level driver header.
- *
- * @addtogroup EXT
- * @{
- */
-
-#ifndef HAL_EXT_LLD_H
-#define HAL_EXT_LLD_H
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Number of EXT per port.
- */
-#define EXT_MAX_CHANNELS    TIVA_GPIO_PINS
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   GPIOA interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOA_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPIOB interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOB_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOB_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPIOC interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOC_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOC_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPIOD interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOD_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOD_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPIOE interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOE_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOE_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPIOF interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOF_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOF_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPIOG interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOG_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOG_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPIOH interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOH_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOH_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPIOJ interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOJ_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOJ_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPIOK interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOK_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOK_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPIOL interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOL_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOL_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPIOM interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOM_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOM_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPION interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPION_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPION_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPIOP0 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOP0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOP0_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOP1 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOP1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOP1_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOP2 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOP2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOP2_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOP3 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOP3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOP3_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOP4 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOP4_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOP4_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOP5 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOP5_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOP5_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOP6 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOP6_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOP6_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOP7 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOP7_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOP7_IRQ_PRIORITY        3
-#endif
-/** @} */
-
-/**
- * @brief   GPIOQ0 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOQ0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOQ0_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOQ1 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOQ1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOQ1_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOQ2 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOQ2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOQ2_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOQ3 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOQ3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOQ3_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOQ4 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOQ4_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOQ4_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOQ5 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOQ5_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOQ5_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOQ6 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOQ6_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOQ6_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOQ7 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOQ7_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOQ7_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOR interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOR_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOR_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPIOS interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOS_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOS_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPIOT interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOT_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOT_IRQ_PRIORITY         3
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if TIVA_HAS_GPIOA &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOA_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOA"
-#endif
-
-#if TIVA_HAS_GPIOB &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOB_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOB"
-#endif
-
-#if TIVA_HAS_GPIOC &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOC_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOC"
-#endif
-
-#if TIVA_HAS_GPIOD &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOD_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOD"
-#endif
-
-#if TIVA_HAS_GPIOE &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOE_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOE"
-#endif
-
-#if TIVA_HAS_GPIOF &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOF_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOF"
-#endif
-
-#if TIVA_HAS_GPIOG &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOG_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOG"
-#endif
-
-#if TIVA_HAS_GPIOH &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOH_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOH"
-#endif
-
-#if TIVA_HAS_GPIOJ &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOJ_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOJ"
-#endif
-
-#if TIVA_HAS_GPIOK &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOK_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOK"
-#endif
-
-#if TIVA_HAS_GPIOL &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOL_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOL"
-#endif
-
-#if TIVA_HAS_GPIOM &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOM_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOM"
-#endif
-
-#if TIVA_HAS_GPION &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPION_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPION"
-#endif
-
-#if TIVA_HAS_GPIOP0 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP0_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOP0"
-#endif
-
-#if TIVA_HAS_GPIOP1 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOP1"
-#endif
-
-#if TIVA_HAS_GPIOP2 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP2_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOP2"
-#endif
-
-#if TIVA_HAS_GPIOP3 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP3_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOP3"
-#endif
-
-#if TIVA_HAS_GPIOP4 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP4_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOP4"
-#endif
-
-#if TIVA_HAS_GPIOP5 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP5_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOP5"
-#endif
-
-#if TIVA_HAS_GPIOP6 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP6_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOP6"
-#endif
-
-#if TIVA_HAS_GPIOP7 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP7_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOP7"
-#endif
-
-#if TIVA_HAS_GPIOQ0 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ0_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOQ0"
-#endif
-
-#if TIVA_HAS_GPIOQ1 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOQ1"
-#endif
-
-#if TIVA_HAS_GPIOQ2 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ2_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOQ2"
-#endif
-
-#if TIVA_HAS_GPIOQ3 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ3_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOQ3"
-#endif
-
-#if TIVA_HAS_GPIOQ4 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ4_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOQ4"
-#endif
-
-#if TIVA_HAS_GPIOQ5 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ5_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOQ5"
-#endif
-
-#if TIVA_HAS_GPIOQ6 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ6_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOQ6"
-#endif
-
-#if TIVA_HAS_GPIOQ7 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ7_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOQ7"
-#endif
-
-#if TIVA_HAS_GPIOR &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOR_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOR"
-#endif
-
-#if TIVA_HAS_GPIOS &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOS_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOS"
-#endif
-
-#if TIVA_HAS_GPIOT &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOT_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOT"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   EXT channel identifier.
- */
-typedef uint32_t expchannel_t;
-
-/**
- * @brief   Type of an EXT generic notification callback.
- *
- * @param[in] extp      pointer to the @p EXPDriver object triggering the
- *                      callback
- */
-typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel);
-
-/**
- * @brief   Channel configuration structure.
- */
-typedef struct {
-  /**
-   * @brief Channel mode.
-   */
-  uint32_t              mode;
-  /**
-   * @brief Channel callback.
-   */
-  extcallback_t         cb;
-} EXTChannelConfig;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  /**
-   * @brief Channel configurations.
-   */
-  EXTChannelConfig      channels[EXT_MAX_CHANNELS];
-  /* End of the mandatory fields.*/
-} EXTConfig;
-
-/**
- * @brief   Structure representing an EXT driver.
- */
-struct EXTDriver {
-  /**
-   * @brief Driver state.
-   */
-  extstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const EXTConfig           *config;
-  /* End of the mandatory fields.*/
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern EXTDriver EXTD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void ext_lld_init(void);
-  void ext_lld_start(EXTDriver *extp);
-  void ext_lld_stop(EXTDriver *extp);
-  void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel);
-  void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_EXT */
-
-#endif /* HAL_EXT_LLD_H */
-
-/** @} */
diff --git a/os/hal/ports/TIVA/LLD/hal_pal_lld.c b/os/hal/ports/TIVA/LLD/hal_pal_lld.c
deleted file mode 100644
index 5460fd4..0000000
--- a/os/hal/ports/TIVA/LLD/hal_pal_lld.c
+++ /dev/null
@@ -1,445 +0,0 @@
-/*
-    Copyright (C) 2014..2016 Marco Veeneman
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    TIVA/LLD/pal_lld.c
- * @brief   TM4C123x/TM4C129x PAL subsystem low level driver.
- *
- * @addtogroup PAL
- * @{
- */
-
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-#if TIVA_HAS_GPIOA || defined(__DOXYGEN__)
-#define GPIOA_BIT       (1 << 0)
-#if TIVA_GPIO_GPIOA_USE_AHB && defined(TM4C123x)
-#define GPIOA_AHB_BIT   (1 << 0)
-#else
-#define GPIOA_AHB_BIT   0
-#endif
-#else
-#define GPIOA_BIT       0
-#define GPIOA_AHB_BIT   0
-#endif
-
-#if TIVA_HAS_GPIOB || defined(__DOXYGEN__)
-#define GPIOB_BIT       (1 << 1)
-#if TIVA_GPIO_GPIOB_USE_AHB && defined(TM4C123x)
-#define GPIOB_AHB_BIT   (1 << 1)
-#else
-#define GPIOB_AHB_BIT   0
-#endif
-#else
-#define GPIOB_BIT       0
-#define GPIOB_AHB_BIT   0
-#endif
-
-#if TIVA_HAS_GPIOC || defined(__DOXYGEN__)
-#define GPIOC_BIT       (1 << 2)
-#if TIVA_GPIO_GPIOC_USE_AHB && defined(TM4C123x)
-#define GPIOC_AHB_BIT   (1 << 2)
-#else
-#define GPIOC_AHB_BIT   0
-#endif
-#else
-#define GPIOC_BIT       0
-#define GPIOC_AHB_BIT   0
-#endif
-
-#if TIVA_HAS_GPIOD || defined(__DOXYGEN__)
-#define GPIOD_BIT       (1 << 3)
-#if TIVA_GPIO_GPIOD_USE_AHB && defined(TM4C123x)
-#define GPIOD_AHB_BIT   (1 << 3)
-#else
-#define GPIOD_AHB_BIT   0
-#endif
-#else
-#define GPIOD_BIT       0
-#define GPIOD_AHB_BIT   0
-#endif
-
-#if TIVA_HAS_GPIOE || defined(__DOXYGEN__)
-#define GPIOE_BIT       (1 << 4)
-#if TIVA_GPIO_GPIOE_USE_AHB && defined(TM4C123x)
-#define GPIOE_AHB_BIT   (1 << 4)
-#else
-#define GPIOE_AHB_BIT   0
-#endif
-#else
-#define GPIOE_BIT       0
-#define GPIOE_AHB_BIT   0
-#endif
-
-#if TIVA_HAS_GPIOF || defined(__DOXYGEN__)
-#define GPIOF_BIT       (1 << 5)
-#if TIVA_GPIO_GPIOF_USE_AHB && defined(TM4C123x)
-#define GPIOF_AHB_BIT   (1 << 5)
-#else
-#define GPIOF_AHB_BIT   0
-#endif
-#else
-#define GPIOF_BIT       0
-#define GPIOF_AHB_BIT   0
-#endif
-
-#if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
-#define GPIOG_BIT       (1 << 6)
-#if TIVA_GPIO_GPIOG_USE_AHB && defined(TM4C123x)
-#define GPIOG_AHB_BIT   (1 << 6)
-#else
-#define GPIOG_AHB_BIT   0
-#endif
-#else
-#define GPIOG_BIT       0
-#define GPIOG_AHB_BIT   0
-#endif
-
-#if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
-#define GPIOH_BIT       (1 << 7)
-#if TIVA_GPIO_GPIOH_USE_AHB && defined(TM4C123x)
-#define GPIOH_AHB_BIT   (1 << 7)
-#else
-#define GPIOH_AHB_BIT   0
-#endif
-#else
-#define GPIOH_BIT       0
-#define GPIOH_AHB_BIT   0
-#endif
-
-#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
-#define GPIOJ_BIT       (1 << 8)
-#if TIVA_GPIO_GPIOJ_USE_AHB && defined(TM4C123x)
-#define GPIOJ_AHB_BIT   (1 << 8)
-#else
-#define GPIOJ_AHB_BIT   0
-#endif
-#else
-#define GPIOJ_BIT       0
-#define GPIOJ_AHB_BIT   0
-#endif
-
-#if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
-#define GPIOK_BIT       (1 << 9)
-#define GPIOK_AHB_BIT   (1 << 9)
-#else
-#define GPIOK_BIT       0
-#define GPIOK_AHB_BIT   0
-#endif
-
-#if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
-#define GPIOL_BIT       (1 << 10)
-#define GPIOL_AHB_BIT   (1 << 10)
-#else
-#define GPIOL_BIT       0
-#define GPIOL_AHB_BIT   0
-#endif
-
-#if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
-#define GPIOM_BIT       (1 << 11)
-#define GPIOM_AHB_BIT   (1 << 11)
-#else
-#define GPIOM_BIT       0
-#define GPIOM_AHB_BIT   0
-#endif
-
-#if TIVA_HAS_GPION || defined(__DOXYGEN__)
-#define GPION_BIT       (1 << 12)
-#define GPION_AHB_BIT   (1 << 12)
-#else
-#define GPION_BIT       0
-#define GPION_AHB_BIT   0
-#endif
-
-#if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
-#define GPIOP_BIT       (1 << 13)
-#define GPIOP_AHB_BIT   (1 << 13)
-#else
-#define GPIOP_BIT       0
-#define GPIOP_AHB_BIT   0
-#endif
-
-#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
-#define GPIOQ_BIT       (1 << 14)
-#define GPIOQ_AHB_BIT   (1 << 14)
-#else
-#define GPIOQ_BIT       0
-#define GPIOQ_AHB_BIT   0
-#endif
-
-#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
-#define GPIOR_BIT       (1 << 15)
-#define GPIOR_AHB_BIT   (1 << 15)
-#else
-#define GPIOR_BIT       0
-#define GPIOR_AHB_BIT   0
-#endif
-
-#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
-#define GPIOS_BIT       (1 << 16)
-#define GPIOS_AHB_BIT   (1 << 16)
-#else
-#define GPIOS_BIT       0
-#define GPIOS_AHB_BIT   0
-#endif
-
-#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
-#define GPIOT_BIT       (1 << 17)
-#define GPIOT_AHB_BIT   (1 << 17)
-#else
-#define GPIOT_BIT       0
-#define GPIOT_AHB_BIT   0
-#endif
-
-#define RCGCGPIO_MASK   (GPIOA_BIT | GPIOB_BIT | GPIOC_BIT | GPIOD_BIT |      \
-                         GPIOE_BIT | GPIOF_BIT | GPIOG_BIT | GPIOH_BIT |      \
-                         GPIOJ_BIT | GPIOK_BIT | GPIOL_BIT | GPIOM_BIT |      \
-                         GPION_BIT | GPIOP_BIT | GPIOQ_BIT | GPIOR_BIT |      \
-                         GPIOS_BIT | GPIOR_BIT)
-
-#define GPIOHBCTL_MASK  (GPIOA_AHB_BIT | GPIOB_AHB_BIT | GPIOC_AHB_BIT |      \
-                         GPIOD_AHB_BIT | GPIOE_AHB_BIT | GPIOF_AHB_BIT |      \
-                         GPIOG_AHB_BIT | GPIOH_AHB_BIT | GPIOJ_AHB_BIT |      \
-                         GPIOK_AHB_BIT | GPIOL_AHB_BIT | GPIOM_AHB_BIT |      \
-                         GPION_AHB_BIT | GPIOP_AHB_BIT | GPIOQ_AHB_BIT |      \
-                         GPIOR_AHB_BIT | GPIOS_AHB_BIT | GPIOT_AHB_BIT)
-
-/* GPIO lock password.*/
-#define TIVA_GPIO_LOCK_PWD                  0x4C4F434B
-
-#define GPIOC_JTAG_MASK     (0x0F)
-#define GPIOD_NMI_MASK      (0x80)
-#define GPIOF_NMI_MASK      (0x01)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Initializes the port with the port configuration.
- *
- * @param[in] port      the port identifier
- * @param[in] config    the port configuration
- */
-static void gpio_init(ioportid_t port, const tiva_gpio_setup_t *config)
-{
-  port->DATA   = config->data;
-  port->DIR    = config->dir;
-  port->AFSEL  = config->afsel;
-  port->DR2R   = config->dr2r;
-  port->DR4R   = config->dr4r;
-  port->DR8R   = config->dr8r;
-  port->ODR    = config->odr;
-  port->PUR    = config->pur;
-  port->PDR    = config->pdr;
-  port->SLR    = config->slr;
-  port->DEN    = config->den;
-  port->AMSEL  = config->amsel;
-  port->PCTL   = config->pctl;
-}
-
-/**
- * @brief   Unlocks the masked pins of the GPIO peripheral.
- * @note    This function is only useful for PORTC0-3, PORTD7 and PORTF0.
- *
- * @param[in] port      the port identifier
- * @param[in] mask      the pin mask
- */
-static void gpio_unlock(ioportid_t port, ioportmask_t mask)
-{
-  port->LOCK = TIVA_GPIO_LOCK_PWD;
-  port->CR = mask;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Tiva I/O ports configuration.
- * @details Ports A-F (G, H, J, K, L, M, N, P, Q, R, S, T) clocks enabled.
- *
- * @param[in] config    the Tiva ports configuration
- *
- * @notapi
- */
-void _pal_lld_init(const PALConfig *config)
-{
-  /*
-   * Enables all GPIO clocks.
-   */
-  SYSCTL->RCGCGPIO = RCGCGPIO_MASK;
-#if defined(TM4C123x)
-  SYSCTL->GPIOHBCTL = GPIOHBCTL_MASK;
-#endif
-
-  /* Wait until all GPIO modules are ready */
-  while (!((SYSCTL->PRGPIO & RCGCGPIO_MASK) == RCGCGPIO_MASK))
-    ;
-  
-#if TIVA_HAS_GPIOA
-  gpio_init(GPIOA, &config->PAData);
-#endif
-#if TIVA_HAS_GPIOB
-  gpio_init(GPIOB, &config->PBData);
-#endif
-#if TIVA_HAS_GPIOC
-  /* Unlock JTAG pins.*/
-  gpio_unlock(GPIOC, GPIOC_JTAG_MASK);
-  gpio_init(GPIOC, &config->PCData);
-#endif
-#if TIVA_HAS_GPIOD
-  /* Unlock NMI pin.*/
-  gpio_unlock(GPIOD, GPIOD_NMI_MASK);
-  gpio_init(GPIOD, &config->PDData);
-#endif
-#if TIVA_HAS_GPIOE
-  gpio_init(GPIOE, &config->PEData);
-#endif
-#if TIVA_HAS_GPIOF
-  /* Unlock NMI pin.*/
-  gpio_unlock(GPIOF, GPIOF_NMI_MASK);
-  gpio_init(GPIOF, &config->PFData);
-#endif
-#if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
-  gpio_init(GPIOG, &config->PGData);
-#endif
-#if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
-  gpio_init(GPIOH, &config->PHData);
-#endif
-#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
-  gpio_init(GPIOJ, &config->PJData);
-#endif
-#if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
-  gpio_init(GPIOK, &config->PKData);
-#endif
-#if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
-  gpio_init(GPIOL, &config->PLData);
-#endif
-#if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
-  gpio_init(GPIOM, &config->PMData);
-#endif
-#if TIVA_HAS_GPION || defined(__DOXYGEN__)
-  gpio_init(GPION, &config->PNData);
-#endif
-#if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
-  gpio_init(GPIOP, &config->PPData);
-#endif
-#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
-  gpio_init(GPIOQ, &config->PQData);
-#endif
-#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
-  gpio_init(GPIOR, &config->PRData);
-#endif
-#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
-  gpio_init(GPIOS, &config->PSData);
-#endif
-#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
-  gpio_init(GPIOT, &config->PTData);
-#endif
-}
-
-/**
- * @brief   Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- *
- * @param[in] port      the port identifier
- * @param[in] mask      the group mask
- * @param[in] mode      the mode
- *
- * @notapi
- */
-void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, iomode_t mode)
-{
-  uint32_t dir   = (mode & PAL_TIVA_DIR_MASK)   >> 0;
-  uint32_t afsel = (mode & PAL_TIVA_AFSEL_MASK) >> 1;
-  uint32_t dr2r  = (mode & PAL_TIVA_DR2R_MASK)  >> 2;
-  uint32_t dr4r  = (mode & PAL_TIVA_DR4R_MASK)  >> 3;
-  uint32_t dr8r  = (mode & PAL_TIVA_DR8R_MASK)  >> 4;
-  uint32_t odr   = (mode & PAL_TIVA_ODR_MASK)   >> 5;
-  uint32_t pur   = (mode & PAL_TIVA_PUR_MASK)   >> 6;
-  uint32_t pdr   = (mode & PAL_TIVA_PDR_MASK)   >> 7;
-  uint32_t slr   = (mode & PAL_TIVA_SLR_MASK)   >> 8;
-  uint32_t den   = (mode & PAL_TIVA_DEN_MASK)   >> 9;
-  uint32_t amsel = (mode & PAL_TIVA_AMSEL_MASK) >> 10;
-  uint32_t pctl  = (mode & PAL_TIVA_PCTL_MASK)  >> 11;
-  uint32_t bit   = 0;
-
-  while(TRUE) {
-    uint32_t pctl_mask = (7 << (4 * bit));
-    uint32_t bit_mask = (1 << bit);
-
-    if ((mask & 1) != 0) {
-      port->DIR   = (port->DIR   & ~bit_mask)  | dir;
-      port->AFSEL = (port->AFSEL & ~bit_mask)  | afsel;
-      port->DR2R  = (port->DR2R  & ~bit_mask)  | dr2r;
-      port->DR4R  = (port->DR4R  & ~bit_mask)  | dr4r;
-      port->DR8R  = (port->DR8R  & ~bit_mask)  | dr8r;
-      port->ODR   = (port->ODR   & ~bit_mask)  | odr;
-      port->PUR   = (port->PUR   & ~bit_mask)  | pur;
-      port->PDR   = (port->PDR   & ~bit_mask)  | pdr;
-      port->SLR   = (port->SLR   & ~bit_mask)  | slr;
-      port->DEN   = (port->DEN   & ~bit_mask)  | den;
-      port->AMSEL = (port->AMSEL & ~bit_mask)  | amsel;
-      port->PCTL  = (port->PCTL  & ~pctl_mask) | pctl;
-    }
-
-    mask >>= 1;
-    if (!mask) {
-      return;
-    }
-
-    dir   <<= 1;
-    afsel <<= 1;
-    dr2r  <<= 1;
-    dr4r  <<= 1;
-    dr8r  <<= 1;
-    odr   <<= 1;
-    pur   <<= 1;
-    pdr   <<= 1;
-    slr   <<= 1;
-    den   <<= 1;
-    amsel <<= 1;
-    pctl  <<= 4;
-
-    bit++;
-  }
-}
-
-#endif /* HAL_USE_PAL */
-
-/**
- * @}
- */
diff --git a/os/hal/ports/TIVA/LLD/hal_pal_lld.h b/os/hal/ports/TIVA/LLD/hal_pal_lld.h
deleted file mode 100644
index c0cd82b..0000000
--- a/os/hal/ports/TIVA/LLD/hal_pal_lld.h
+++ /dev/null
@@ -1,762 +0,0 @@
-/*
-    Copyright (C) 2014..2016 Marco Veeneman
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    TIVA/LLD/pal_lld.h
- * @brief   TM4C123x/TM4C129x PAL subsystem low level driver header.
- *
- * @addtogroup PAL
- * @{
- */
-
-#ifndef HAL_PAL_LLD_H
-#define HAL_PAL_LLD_H
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#undef PAL_MODE_RESET
-#undef PAL_MODE_UNCONNECTED
-#undef PAL_MODE_INPUT
-#undef PAL_MODE_INPUT_PULLUP
-#undef PAL_MODE_INPUT_PULLDOWN
-#undef PAL_MODE_INPUT_ANALOG
-#undef PAL_MODE_OUTPUT_PUSHPULL
-#undef PAL_MODE_OUTPUT_OPENDRAIN
-
-/**
- * @name    TIVA-specific I/O mode flags
- * @{
- */
-#define PAL_TIVA_DIR_MASK           (1 << 0)
-#define PAL_TIVA_DIR_INPUT          (0 << 0)
-#define PAL_TIVA_DIR_OUTPUT         (1 << 0)
-
-#define PAL_TIVA_AFSEL_MASK         (1 << 1)
-#define PAL_TIVA_AFSEL_GPIO         (0 << 1)
-#define PAL_TIVA_AFSEL_ALTERNATE    (1 << 1)
-
-#define PAL_TIVA_DR2R_MASK          (1 << 2)
-#define PAL_TIVA_DR2R_DISABLE       (0 << 2)
-#define PAL_TIVA_DR2R_ENABLE        (1 << 2)
-
-#define PAL_TIVA_DR4R_MASK          (1 << 3)
-#define PAL_TIVA_DR4R_DISABLE       (0 << 3)
-#define PAL_TIVA_DR4R_ENABLE        (1 << 3)
-
-#define PAL_TIVA_DR8R_MASK          (1 << 4)
-#define PAL_TIVA_DR8R_DISABLE       (0 << 4)
-#define PAL_TIVA_DR8R_ENABLE        (1 << 4)
-
-#define PAL_TIVA_ODR_MASK           (1 << 5)
-#define PAL_TIVA_ODR_PUSHPULL       (0 << 5)
-#define PAL_TIVA_ODR_OPENDRAIN      (1 << 5)
-
-#define PAL_TIVA_PUR_MASK           (1 << 6)
-#define PAL_TIVA_PUR_DISABLE        (0 << 6)
-#define PAL_TIVA_PUR_ENABLE         (1 << 6)
-
-#define PAL_TIVA_PDR_MASK           (1 << 7)
-#define PAL_TIVA_PDR_DISABLE        (0 << 7)
-#define PAL_TIVA_PDR_ENABLE         (1 << 7)
-
-#define PAL_TIVA_SLR_MASK           (1 << 8)
-#define PAL_TIVA_SLR_DISABLE        (0 << 8)
-#define PAL_TIVA_SLR_ENABLE         (1 << 8)
-
-#define PAL_TIVA_DEN_MASK           (1 << 9)
-#define PAL_TIVA_DEN_DISABLE        (0 << 9)
-#define PAL_TIVA_DEN_ENABLE         (1 << 9)
-
-#define PAL_TIVA_AMSEL_MASK         (1 << 10)
-#define PAL_TIVA_AMSEL_DISABLE      (0 << 10)
-#define PAL_TIVA_AMSEL_ENABLE       (1 << 10)
-
-#define PAL_TIVA_PCTL_MASK          (7 << 11)
-#define PAL_TIVA_PCTL(n)            ((n) << 11)
-
-/**
- * @brief   Alternate function.
- *
- * @param[in] n         alternate function selector
- */
-#define PAL_MODE_ALTERNATE(n)       (PAL_TIVA_AFSEL_ALTERNATE |               \
-                                     PAL_TIVA_PCTL(n))
-/**
- * @}
- */
-
-/**
- * @name    Standard I/O mode flags
- * @{
- */
-/**
- * @brief   This mode is implemented as input.
- */
-#define PAL_MODE_RESET                  PAL_MODE_INPUT
-
-/**
- * @brief   This mode is implemented as input with pull-up.
- */
-#define PAL_MODE_UNCONNECTED            PAL_MODE_INPUT_PULLUP
-
-/**
- * @brief   Regular input high-Z pad.
- */
-#define PAL_MODE_INPUT                  (PAL_TIVA_DEN_ENABLE |                \
-                                         PAL_TIVA_DIR_INPUT)
-
-/**
- * @brief   Input pad with weak pull up resistor.
- */
-#define PAL_MODE_INPUT_PULLUP           (PAL_TIVA_DIR_INPUT |                 \
-                                         PAL_TIVA_PUR_ENABLE |                \
-                                         PAL_TIVA_DEN_ENABLE)
-
-/**
- * @brief   Input pad with weak pull down resistor.
- */
-#define PAL_MODE_INPUT_PULLDOWN         (PAL_TIVA_DIR_INPUT |                 \
-                                         PAL_TIVA_PDR_ENABLE |                \
-                                         PAL_TIVA_DEN_ENABLE)
-
-/**
- * @brief   Analog input mode.
- */
-#define PAL_MODE_INPUT_ANALOG           (PAL_TIVA_DEN_DISABLE |               \
-                                         PAL_TIVA_AMSEL_ENABLE)
-
-/**
- * @brief   Push-pull output pad.
- */
-#define PAL_MODE_OUTPUT_PUSHPULL        (PAL_TIVA_DIR_OUTPUT |                \
-                                         PAL_TIVA_DR2R_ENABLE |               \
-                                         PAL_TIVA_ODR_PUSHPULL |              \
-                                         PAL_TIVA_DEN_ENABLE)
-
-/**
- * @brief   Open-drain output pad.
- */
-#define PAL_MODE_OUTPUT_OPENDRAIN       (PAL_TIVA_DIR_OUTPUT |                \
-                                         PAL_TIVA_DR2R_ENABLE |               \
-                                         PAL_TIVA_ODR_OPENDRAIN |             \
-                                         PAL_TIVA_DEN_ENABLE)
-/**
- * @}
- */
-
-/** @brief   GPIOA port identifier.*/
-#define IOPORT1         GPIOA
-
-/** @brief   GPIOB port identifier.*/
-#define IOPORT2         GPIOB
-
-/** @brief   GPIOC port identifier.*/
-#define IOPORT3         GPIOC
-
-/** @brief   GPIOD port identifier.*/
-#define IOPORT4         GPIOD
-
-/** @brief   GPIOE port identifier.*/
-#define IOPORT5         GPIOE
-
-/** @brief   GPIOF port identifier.*/
-#define IOPORT6         GPIOF
-
-#if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
-/** @brief Port G setup data.*/
-#define IOPORT7         GPIOG
-#endif /* TIVA_HAS_GPIOG.*/
-
-#if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
-/** @brief Port H setup data.*/
-#define IOPORT8         GPIOH
-#endif /* TIVA_HAS_GPIOH.*/
-
-#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
-/** @brief Port J setup data.*/
-#define IOPORT9         GPIOJ
-#endif /* TIVA_HAS_GPIOJ.*/
-
-#if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
-/** @brief Port K setup data.*/
-#define IOPORT10        GPIOK
-#endif /* TIVA_HAS_GPIOK.*/
-
-#if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
-/** @brief Port L setup data.*/
-#define IOPORT11        GPIOL
-#endif /* TIVA_HAS_GPIOL.*/
-
-#if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
-/** @brief Port M setup data.*/
-#define IOPORT12        GPIOM
-#endif /* TIVA_HAS_GPIOM.*/
-
-#if TIVA_HAS_GPION || defined(__DOXYGEN__)
-/** @brief Port N setup data.*/
-#define IOPORT13        GPION
-#endif /* TIVA_HAS_GPION.*/
-
-#if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
-/** @brief Port P setup data.*/
-#define IOPORT14        GPIOP
-#endif /* TIVA_HAS_GPIOP.*/
-
-#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
-/** @brief Port Q setup data.*/
-#define IOPORT15        GPIOQ
-#endif /* TIVA_HAS_GPIOQ.*/
-
-#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
-/** @brief Port R setup data.*/
-#define IOPORT16        GPIOR
-#endif /* TIVA_HAS_GPIOR.*/
-
-#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
-/** @brief Port S setup data.*/
-#define IOPORT17        GPIOS
-#endif /* TIVA_HAS_GPIOS.*/
-
-#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
-/** @brief Port T setup data.*/
-#define IOPORT18        GPIOT
-#endif /* TIVA_HAS_GPIOT.*/
-
-/**
- * @brief   Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 8
-
-/**
- * @brief   Whole port mask.
- * @brief   This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFF)
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-#if defined(TM4C123x)
-
-/**
- * @brief   GPIOA AHB enable switch.
- * @details When set to @p TRUE the AHB bus is used to access GPIOA. When set
- *          to @p FALSE the APB bus is used to access GPIOA.
- * @note    The default is TRUE.
- */
-#if !defined(TIVA_GPIO_GPIOA_USE_AHB) || defined(__DOXYGEN__)
-#define TIVA_GPIO_GPIOA_USE_AHB             TRUE
-#endif
-
-/**
- * @brief   GPIOB AHB enable switch.
- * @details When set to @p TRUE the AHB bus is used to access GPIOB. When set
- *          to @p FALSE the APB bus is used to access GPIOB.
- * @note    The default is TRUE.
- */
-#if !defined(TIVA_GPIO_GPIOB_USE_AHB) || defined(__DOXYGEN__)
-#define TIVA_GPIO_GPIOB_USE_AHB             TRUE
-#endif
-
-/**
- * @brief   GPIOC AHB enable switch.
- * @details When set to @p TRUE the AHB bus is used to access GPIOC. When set
- *          to @p FALSE the APB bus is used to access GPIOC.
- * @note    The default is TRUE.
- */
-#if !defined(TIVA_GPIO_GPIOC_USE_AHB) || defined(__DOXYGEN__)
-#define TIVA_GPIO_GPIOC_USE_AHB             TRUE
-#endif
-
-/**
- * @brief   GPIOD AHB enable switch.
- * @details When set to @p TRUE the AHB bus is used to access GPIOD. When set
- *          to @p FALSE the APB bus is used to access GPIOD.
- * @note    The default is TRUE.
- */
-#if !defined(TIVA_GPIO_GPIOD_USE_AHB) || defined(__DOXYGEN__)
-#define TIVA_GPIO_GPIOD_USE_AHB             TRUE
-#endif
-
-/**
- * @brief   GPIOE AHB enable switch.
- * @details When set to @p TRUE the AHB bus is used to access GPIOE. When set
- *          to @p FALSE the APB bus is used to access GPIOE.
- * @note    The default is TRUE.
- */
-#if !defined(TIVA_GPIO_GPIOE_USE_AHB) || defined(__DOXYGEN__)
-#define TIVA_GPIO_GPIOE_USE_AHB             TRUE
-#endif
-
-/**
- * @brief   GPIOF AHB enable switch.
- * @details When set to @p TRUE the AHB bus is used to access GPIOF. When set
- *          to @p FALSE the APB bus is used to access GPIOF.
- * @note    The default is TRUE.
- */
-#if !defined(TIVA_GPIO_GPIOF_USE_AHB) || defined(__DOXYGEN__)
-#define TIVA_GPIO_GPIOF_USE_AHB             TRUE
-#endif
-
-/**
- * @brief   GPIOG AHB enable switch.
- * @details When set to @p TRUE the AHB bus is used to access GPIOG. When set
- *          to @p FALSE the APB bus is used to access GPIOG.
- * @note    The default is TRUE.
- */
-#if !defined(TIVA_GPIO_GPIOG_USE_AHB) || defined(__DOXYGEN__)
-#define TIVA_GPIO_GPIOG_USE_AHB             TRUE
-#endif
-
-/**
- * @brief   GPIOH AHB enable switch.
- * @details When set to @p TRUE the AHB bus is used to access GPIOH. When set
- *          to @p FALSE the APB bus is used to access GPIOH.
- * @note    The default is TRUE.
- */
-#if !defined(TIVA_GPIO_GPIOH_USE_AHB) || defined(__DOXYGEN__)
-#define TIVA_GPIO_GPIOH_USE_AHB             TRUE
-#endif
-
-/**
- * @brief   GPIOJ AHB enable switch.
- * @details When set to @p TRUE the AHB bus is used to access GPIOJ. When set
- *          to @p FALSE the APB bus is used to access GPIOJ.
- * @note    The default is TRUE.
- */
-#if !defined(TIVA_GPIO_GPIOJ_USE_AHB) || defined(__DOXYGEN__)
-#define TIVA_GPIO_GPIOJ_USE_AHB             TRUE
-#endif
-
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if defined(TM4C123x)
-
-#if TIVA_GPIO_GPIOA_USE_AHB
-#define GPIOA                               GPIOA_AHB
-#else
-#define GPIOA                               GPIOA_APB
-#endif
-
-#if TIVA_GPIO_GPIOB_USE_AHB
-#define GPIOB                               GPIOB_AHB
-#else
-#define GPIOB                               GPIOB_APB
-#endif
-
-#if TIVA_GPIO_GPIOC_USE_AHB
-#define GPIOC                               GPIOC_AHB
-#else
-#define GPIOC                               GPIOC_APB
-#endif
-
-#if TIVA_GPIO_GPIOD_USE_AHB
-#define GPIOD                               GPIOD_AHB
-#else
-#define GPIOD                               GPIOD_APB
-#endif
-
-#if TIVA_GPIO_GPIOE_USE_AHB
-#define GPIOE                               GPIOE_AHB
-#else
-#define GPIOE                               GPIOE_APB
-#endif
-
-#if TIVA_GPIO_GPIOF_USE_AHB
-#define GPIOF                               GPIOF_AHB
-#else
-#define GPIOF                               GPIOF_APB
-#endif
-
-#if TIVA_GPIO_GPIOG_USE_AHB
-#define GPIOG                               GPIOG_AHB
-#else
-#define GPIOG                               GPIOG_APB
-#endif
-
-#if TIVA_GPIO_GPIOH_USE_AHB
-#define GPIOH                               GPIOH_AHB
-#else
-#define GPIOH                               GPIOH_APB
-#endif
-
-#if TIVA_GPIO_GPIOJ_USE_AHB
-#define GPIOJ                               GPIOJ_AHB
-#else
-#define GPIOJ                               GPIOJ_APB
-#endif
-
-#define GPIOK                               GPIOK_AHB
-#define GPIOL                               GPIOL_AHB
-#define GPIOM                               GPIOM_AHB
-#define GPION                               GPION_AHB
-#define GPIOP                               GPIOP_AHB
-#define GPIOQ                               GPIOQ_AHB
-
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   GPIO port setup info.
- */
-typedef struct 
-{
-  /** @brief Initial value for DATA register.*/
-  uint32_t data;
-  /** @brief Initial value for DIR register.*/
-  uint32_t dir;
-  /** @brief Initial value for AFSEL register.*/
-  uint32_t afsel;
-  /** @brief Initial value for DR2R register.*/
-  uint32_t dr2r;
-  /** @brief Initial value for DR4R register.*/
-  uint32_t dr4r;
-  /** @brief Initial value for DR8R register.*/
-  uint32_t dr8r;
-  /** @brief Initial value for ODR register.*/
-  uint32_t odr;
-  /** @brief Initial value for PUR register.*/
-  uint32_t pur;
-  /** @brief Initial value for PDR register.*/
-  uint32_t pdr;
-  /** @brief Initial value for SLR register.*/
-  uint32_t slr;
-  /** @brief Initial value for DEN register.*/
-  uint32_t den;
-  /** @brief Initial value for AMSEL register.*/
-  uint32_t amsel;
-  /** @brief Initial value for PCTL register.*/
-  uint32_t pctl;
-} tiva_gpio_setup_t;
-
-/**
- * @brief   Tiva GPIO static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- *          system startup time in order to initialized the digital I/O
- *          subsystem. This represents only the initial setup, specific pads
- *          or whole ports can be reprogrammed at later time.
- */
-typedef struct
-{
-  /** @brief Port A setup data.*/
-  tiva_gpio_setup_t     PAData;
-  /** @brief Port B setup data.*/
-  tiva_gpio_setup_t     PBData;
-  /** @brief Port C setup data.*/
-  tiva_gpio_setup_t     PCData;
-  /** @brief Port D setup data.*/
-  tiva_gpio_setup_t     PDData;
-  /** @brief Port E setup data.*/
-  tiva_gpio_setup_t     PEData;
-  /** @brief Port F setup data.*/
-  tiva_gpio_setup_t     PFData;
-
-#if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
-  /** @brief Port G setup data.*/
-  tiva_gpio_setup_t     PGData;
-#endif /* TIVA_HAS_GPIOG.*/
-
-#if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
-  /** @brief Port H setup data.*/
-  tiva_gpio_setup_t     PHData;
-#endif /* TIVA_HAS_GPIOH.*/
-
-#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
-  /** @brief Port J setup data.*/
-  tiva_gpio_setup_t     PJData;
-#endif /* TIVA_HAS_GPIOJ.*/
-
-#if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
-  /** @brief Port K setup data.*/
-  tiva_gpio_setup_t     PKData;
-#endif /* TIVA_HAS_GPIOK.*/
-
-#if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
-  /** @brief Port L setup data.*/
-  tiva_gpio_setup_t     PLData;
-#endif /* TIVA_HAS_GPIOL.*/
-
-#if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
-  /** @brief Port M setup data.*/
-  tiva_gpio_setup_t     PMData;
-#endif /* TIVA_HAS_GPIOM.*/
-
-#if TIVA_HAS_GPION || defined(__DOXYGEN__)
-  /** @brief Port N setup data.*/
-  tiva_gpio_setup_t     PNData;
-#endif /* TIVA_HAS_GPION.*/
-
-#if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
-  /** @brief Port P setup data.*/
-  tiva_gpio_setup_t     PPData;
-#endif /* TIVA_HAS_GPIOP.*/
-
-#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
-  /** @brief Port Q setup data.*/
-  tiva_gpio_setup_t     PQData;
-#endif /* TIVA_HAS_GPIOQ.*/
-
-#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
-  /** @brief Port R setup data.*/
-  tiva_gpio_setup_t     PRData;
-#endif /* TIVA_HAS_GPIOR.*/
-
-#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
-  /** @brief Port S setup data.*/
-  tiva_gpio_setup_t     PSData;
-#endif /* TIVA_HAS_GPIOS.*/
-
-#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
-  /** @brief Port T setup data.*/
-  tiva_gpio_setup_t     PTData;
-#endif /* TIVA_HAS_GPIOT.*/
-} PALConfig;
-
-/**
- * @brief   Digital I/O port sized unsigned type.
- */
-typedef uint32_t ioportmask_t;
-
-/**
- * @brief   Digital I/O modes.
- */
-typedef uint32_t iomode_t;
-
-/**
- * @brief   Port Identifier.
- */
-typedef GPIO_TypeDef *ioportid_t;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Low level PAL subsystem initialization.
- *
- * @param[in] config    architecture-dependent ports configuration
- *
- * @notapi
- */
-#define pal_lld_init(config) _pal_lld_init(config)
-
-/**
- * @brief   Reads the physical I/O port states.
- *
- * @param[in] port      port identifier
- * @return              The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port)  ((port)->DATA)
-
-/**
- * @brief   Reads the output latch.
- * @details The purpose of this function is to read back the latched output
- *          value.
- *
- * @param[in] port      port identifier
- * @return              The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port) ((port)->DATA)
-
-/**
- * @brief   Writes a bits mask on a I/O port.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits)   ((port)->DATA = (bits))
-
-/**
- * @brief   Sets a bits mask on a I/O port.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be ORed on the specified port
- *
- * @notapi
- */
-#define pal_lld_setport(port, bits) ((port)->MASKED_ACCESS[bits] = 0xFF)
-
-/**
- * @brief   Clears a bits mask on a I/O port.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be cleared on the specified port
- *
- * @notapi
- */
-#define pal_lld_clearport(port, bits)   ((port)->MASKED_ACCESS[bits] = 0)
-
-/**
- * @brief   Reads a group of bits.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @return              The group logical states.
- *
- * @notapi
- */
-#define pal_lld_readgroup(port, mask, offset)   \
-  ((port)->MASKED_ACCESS[(mask) << (offset)])
-
-/**
- * @brief   Writes a group of bits.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] bits      bits to be written. Values exceeding the group width
- *                      are masked.
- *
- * @notapi
- */
-#define pal_lld_writegroup(port, mask, offset, bits)    \
-  ((port)->MASKED_ACCESS[(mask) << (offset)] = (bits))
-
-/**
- * @brief   Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] mode      group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode)                      \
-  _pal_lld_setgroupmode(port, mask << offset, mode)
-
-/**
- * @brief   Reads a logical state from an I/O pad.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- * @return              The logical state.
- * @retval PAL_LOW      low logical state.
- * @retval PAL_HIGH     high logical state.
- *
- * @notapi
- */
-#define pal_lld_readpad(port, pad) ((port)->MASKED_ACCESS[1 << (pad)])
-
-/**
- * @brief   Writes a logical state on an output pad.
- * @note    This function is not meant to be invoked directly by the
- *          application  code.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- * @param[in] bit       logical value, the value must be @p PAL_LOW or
- *                      @p PAL_HIGH
- *
- * @notapi
- */
-#define pal_lld_writepad(port, pad, bit)    \
-  ((port)->MASKED_ACCESS[1 << (pad)] = (bit))
-
-/**
- * @brief   Sets a pad logical state to @p PAL_HIGH.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_setpad(port, pad)   \
-  ((port)->MASKED_ACCESS[1 << (pad)] = 1 << (pad))
-
-/**
- * @brief   Clears a pad logical state to @p PAL_LOW.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_clearpad(port, pad) \
-  ((port)->MASKED_ACCESS[1 << (pad)] = 0)
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern const PALConfig pal_default_config;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _pal_lld_init(const PALConfig *config);
-  void _pal_lld_setgroupmode(ioportid_t port,
-                             ioportmask_t mask,
-                             iomode_t mode);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PAL */
-
-#endif /* HAL_PAL_LLD_H */
-
-/**
- * @}
- */
diff --git a/os/hal/ports/TIVA/LLD/tiva_gpt.h b/os/hal/ports/TIVA/LLD/tiva_gpt.h
deleted file mode 100644
index 114831b..0000000
--- a/os/hal/ports/TIVA/LLD/tiva_gpt.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
-    Copyright (C) 2014..2016 Marco Veeneman
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    tiva_gpt.h
- * @brief   TIVA GPT registers layout header.
- *
- * @addtogroup TIVA_GPT
- * @{
- */
-
-#ifndef TIVA_GPT_H_
-#define TIVA_GPT_H_
-
-// cfg
-#define GPTM_CFG_CFG_MASK       (7 << 0)
-#define GPTM_CFG_CFG_WHOLE      (0 << 0)
-#define GPTM_CFG_CFG_RTC        (1 << 0)
-#define GPTM_CFG_CFG_SPLIT      (4 << 0)
-
-// tamr
-#define GPTM_TAMR_TAMR_MASK     (3 << 0)
-#define GPTM_TAMR_TAMR_ONESHOT  (1 << 0)
-#define GPTM_TAMR_TAMR_PERIODIC (2 << 0)
-#define GPTM_TAMR_TAMR_CAPTURE  (3 << 0)
-
-#define GPTM_TAMR_TACMR         (1 << 2)
-
-#define GPTM_TAMR_TAAMS         (1 << 3)
-
-#define GPTM_TAMR_TACDIR        (1 << 4)
-
-#define GPTM_TAMR_TAMIE         (1 << 5)
-
-#define GPTM_TAMR_TAWOT         (1 << 6)
-
-#define GPTM_TAMR_TASNAPS       (1 << 7)
-
-#define GPTM_TAMR_TAILD         (1 << 8)
-
-#define GPTM_TAMR_TAPWMIE       (1 << 9)
-
-#define GPTM_TAMR_TAMRSU        (1 << 10)
-
-#define GPTM_TAMR_TAPLO         (1 << 11)
-
-// ctl
-#define GPTM_CTL_TAEN           (1 << 0)
-
-#define GPTM_CTL_TASTALL        (1 << 1)
-
-#define GPTM_CTL_TAEVENT_MASK   (3 << 2)
-#define GPTM_CTL_TAEVENT_POS    (0 << 2)
-#define GPTM_CTL_TAEVENT_NEG    (1 << 2)
-#define GPTM_CTL_TAEVENT_BOTH   (3 << 2)
-
-#define GPTM_CTL_RTCEN          (1 << 4)
-
-#define GPTM_CTL_TAOTE          (1 << 5)
-
-#define GPTM_CTL_TAPWML         (1 << 6)
-
-#define GPTM_CTL_TBEN           (1 << 8)
-
-#define GPTM_CTL_TBSTALL        (1 << 9)
-
-#define GPTM_CTL_TBEVENT_MASK   (3 << 10)
-#define GPTM_CTL_TBEVENT_POS    (0 << 10)
-#define GPTM_CTL_TBEVENT_NEG    (1 << 10)
-#define GPTM_CTL_TBEVENT_BOTH   (3 << 10)
-
-#define GPTM_CTL_TBOTE          (1 << 13)
-
-#define GPTM_CTL_TBPWML         (1 << 14)
-
-// imr
-#define GPTM_IMR_TATOIM         (1 << 0)
-
-#define GPTM_IMR_CAMIM          (1 << 1)
-
-#define GPTM_IMR_CAEIM          (1 << 2)
-
-#define GPTM_IMR_RTCIM          (1 << 3)
-
-#define GPTM_IMR_TAMIM          (1 << 4)
-
-#define GPTM_IMR_TBTOIM         (1 << 8)
-
-#define GPTM_IMR_CBMIM          (1 << 9)
-
-#define GPTM_IMR_CBEIM          (1 << 10)
-
-#define GPTM_IMR_TBMIM          (1 << 11)
-
-#define GPTM_IMR_WUEIM          (1 << 16)
-
-// icr
-#define GPTM_ICR_TATOCINT         (1 << 0)
-
-#define GPTM_ICR_CAMCINT          (1 << 1)
-
-#define GPTM_ICR_CAECINT          (1 << 2)
-
-#define GPTM_ICR_RTCCINT          (1 << 3)
-
-#define GPTM_ICR_TAMCINT          (1 << 4)
-
-#define GPTM_ICR_TBTOCINT         (1 << 8)
-
-#define GPTM_ICR_CBMCINT          (1 << 9)
-
-#define GPTM_ICR_CBECINT          (1 << 10)
-
-#define GPTM_ICR_TBMCINT          (1 << 11)
-
-#define GPTM_ICR_WUECINT          (1 << 16)
-
-#endif /* TIVA_GPT_H_ */
-
-/*
- * @}
- */
diff --git a/os/hal/ports/TIVA/LLD/uDMA/driver.mk b/os/hal/ports/TIVA/LLD/uDMA/driver.mk
new file mode 100644
index 0000000..3a2d929
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/uDMA/driver.mk
@@ -0,0 +1,2 @@
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c
+PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/uDMA
diff --git a/os/hal/ports/TIVA/LLD/tiva_udma.c b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c
index 9f122b2..2d18ff5 100644
--- a/os/hal/ports/TIVA/LLD/tiva_udma.c
+++ b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -14,6 +14,14 @@
     limitations under the License.
 */
 
+/**
+ * @file    uDMA/tiva_udma.c
+ * @brief   DMA helper driver code.
+ *
+ * @addtogroup TIVA_DMA
+ * @{
+ */
+
 #include "hal.h"
 
 /* The following macro is only defined if some driver requiring DMA services
@@ -75,8 +83,8 @@ OSAL_IRQ_HANDLER(TIVA_UDMA_ERR_HANDLER)
 
   /* TODO Do we need to halt the system on a DMA error?*/
 
-  if (UDMA->ERRCLR) {
-    UDMA->ERRCLR = 1;
+  if (HWREG(UDMA_ERRCLR)) {
+    HWREG(UDMA_ERRCLR) = 1;
   }
 
   OSAL_IRQ_EPILOGUE();
@@ -96,18 +104,18 @@ void udmaInit(void)
   udma_channel_mask = 0;
 
   /* Enable UDMA module.*/
-  SYSCTL->RCGCDMA = 1;
-  while (!(SYSCTL->PRDMA & (1 << 0)))
+  HWREG(SYSCTL_RCGCDMA) = 1;
+  while (!(HWREG(SYSCTL_PRDMA) & (1 << 0)))
     ;
 
   nvicEnableVector(TIVA_UDMA_ERR_NUMBER, TIVA_UDMA_ERR_IRQ_PRIORITY);
   nvicEnableVector(TIVA_UDMA_SW_NUMBER, TIVA_UDMA_SW_IRQ_PRIORITY);
 
   /* Enable UDMA controller.*/
-  UDMA->CFG = 1;
+  HWREG(UDMA_CFG) = UDMA_CFG_MASTEN;
 
   /* Set address of control table.*/
-  UDMA->CTLBASE = (uint32_t)udmaControlTable.primary;
+  HWREG(UDMA_CTLBASE) = (uint32_t)udmaControlTable.primary;
 }
 
 /**
@@ -139,3 +147,5 @@ void udmaChannelRelease(uint8_t dmach)
 }
 
 #endif
+
+/** @} */
diff --git a/os/hal/ports/TIVA/LLD/tiva_udma.h b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.h
index 6479b08..a473f6c 100644
--- a/os/hal/ports/TIVA/LLD/tiva_udma.h
+++ b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.h
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -14,6 +14,14 @@
     limitations under the License.
 */
 
+/**
+ * @file    uDMA/tiva_udma.h
+ * @brief   DMA helper driver header.
+ *
+ * @addtogroup TIVA_DMA
+ * @{
+ */
+
 #ifndef TIVA_UDMA_H_
 #define TIVA_UDMA_H_
 
@@ -22,52 +30,9 @@
 /*===========================================================================*/
 
 /**
- * @name    CHCTL register defines.
- * @{
+ * @brief   CHCTL XFERSIZE helper.
  */
-#define UDMA_CHCTL_DSTINC_MASK          0xC0000000
-#define UDMA_CHCTL_DSTINC_0             0xC0000000
-#define UDMA_CHCTL_DSTINC_8             0x00000000
-#define UDMA_CHCTL_DSTINC_16            0x40000000
-#define UDMA_CHCTL_DSTINC_32            0x80000000
-#define UDMA_CHCTL_DSTSIZE_MASK         0x30000000
-#define UDMA_CHCTL_DSTSIZE_8            0x00000000
-#define UDMA_CHCTL_DSTSIZE_16           0x10000000
-#define UDMA_CHCTL_DSTSIZE_32           0x20000000
-#define UDMA_CHCTL_SRCINC_MASK          0x0C000000
-#define UDMA_CHCTL_SRCINC_0             0x0C000000
-#define UDMA_CHCTL_SRCINC_8             0x00000000
-#define UDMA_CHCTL_SRCINC_16            0x04000000
-#define UDMA_CHCTL_SRCINC_32            0x08000000
-#define UDMA_CHCTL_SRCSIZE_MASK         0x03000000
-#define UDMA_CHCTL_SRCSIZE_8            0x00000000
-#define UDMA_CHCTL_SRCSIZE_16           0x01000000
-#define UDMA_CHCTL_SRCSIZE_32           0x02000000
-#define UDMA_CHCTL_ARBSIZE_MASK         0x0003C000
-#define UDMA_CHCTL_ARBSIZE_1            0x00000000
-#define UDMA_CHCTL_ARBSIZE_2            0x00004000
-#define UDMA_CHCTL_ARBSIZE_4            0x00008000
-#define UDMA_CHCTL_ARBSIZE_8            0x0000C000
-#define UDMA_CHCTL_ARBSIZE_16           0x00010000
-#define UDMA_CHCTL_ARBSIZE_32           0x00014000
-#define UDMA_CHCTL_ARBSIZE_64           0x00018000
-#define UDMA_CHCTL_ARBSIZE_128          0x0001C000
-#define UDMA_CHCTL_ARBSIZE_256          0x00020000
-#define UDMA_CHCTL_ARBSIZE_512          0x00024000
-#define UDMA_CHCTL_ARBSIZE_1024         0x00028000
-#define UDMA_CHCTL_XFERSIZE_MASK        0x00003FF0
-#define UDMA_CHCTL_XFERSIZE(n)          ((n-1) << 4)
-#define UDMA_CHCTL_NXTUSEBURST          0x00000008
-#define UDMA_CHCTL_XFERMODE_MASK        0x00000007
-#define UDMA_CHCTL_XFERMODE_STOP        0x00000000
-#define UDMA_CHCTL_XFERMODE_BASIC       0x00000001
-#define UDMA_CHCTL_XFERMODE_AUTO        0x00000002
-#define UDMA_CHCTL_XFERMODE_PINGPONG    0x00000003
-#define UDMA_CHCTL_XFERMODE_MSG         0x00000004
-#define UDMA_CHCTL_XFERMODE_AMSG        0x00000005
-#define UDMA_CHCTL_XFERMODE_PSG         0x00000006
-#define UDMA_CHCTL_XFERMODE_APSG        0x00000007
-/** @} */
+#define UDMA_CHCTL_XFERSIZE(n)          (((n)-1) << 4)
 
 /*===========================================================================*/
 /* Driver pre-compile time settings.                                         */
@@ -137,43 +102,43 @@ typedef struct __attribute__((packed, aligned(1024)))
 /*===========================================================================*/
 
 #define dmaChannelEnable(dmach) {\
-  UDMA->ENASET = (1 << dmach);\
+  HWREG(UDMA_ENASET) = (1 << dmach);\
 }
 
 #define dmaChannelDisable(dmach) { \
-  UDMA->ENACLR = (1 << dmach); \
+  HWREG(UDMA_ENACLR) = (1 << dmach); \
 }
 
 #define dmaChannelPrimary(dmach) {\
-  UDMA->ALTCLR = (1 << dmach); \
+  HWREG(UDMA_ALTCLR) = (1 << dmach); \
 }
 
 #define dmaChannelAlternate(dmach) { \
-  UDMA->ALTSET = (1 << dmach); \
+  HWREG(UDMA_ALTSET) = (1 << dmach); \
 }
 
 #define dmaChannelSingleBurst(dmach) { \
-  UDMA->USEBURSTCLR = (1 << dmach); \
+  HWREG(UDMA_USEBURSTCLR) = (1 << dmach); \
 }
 
 #define dmaChannelBurstOnly(dmach) { \
-  UDMA->USEBURSTSET = (1 << dmach); \
+  HWREG(UDMA_USEBURSTSET) = (1 << dmach); \
 }
 
 #define dmaChannelPriorityHigh(dmach) { \
-  UDMA->PRIOSET = (1 << dmach); \
+  HWREG(UDMA_PRIOSET) = (1 << dmach); \
 }
 
 #define dmaChannelPriorityDefault(dmach) { \
-  UDMA->PRIOCLR = (1 << dmach); \
+  HWREG(UDMA_PRIOCLR) = (1 << dmach); \
 }
 
 #define dmaChannelEnableRequest(dmach) {\
-  UDMA->REQMASKCLR = (1 << dmach); \
+  HWREG(UDMA_REQMASKCLR) = (1 << dmach); \
 }
 
 #define dmaChannelDisableRequest(dmach) {\
-  UDMA->REQMASKSET = (1 << dmach); \
+  HWREG(UDMA_REQMASKSET) = (1 << dmach); \
 }
 
 /*===========================================================================*/
@@ -193,3 +158,5 @@ extern "C" {
 #endif
 
 #endif /* TIVA_UDMA_H_ */
+
+/** @} */
diff --git a/os/hal/ports/TIVA/TM4C123x/hal_lld.c b/os/hal/ports/TIVA/TM4C123x/hal_lld.c
index ddcddb3..10cd903 100644
--- a/os/hal/ports/TIVA/TM4C123x/hal_lld.c
+++ b/os/hal/ports/TIVA/TM4C123x/hal_lld.c
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -76,60 +76,60 @@ void tiva_clock_init(void)
    * PLL. */
   /* read */
 
-  rcc = SYSCTL->RCC;
-  rcc2 = SYSCTL->RCC2;
+  rcc = HWREG(SYSCTL_RCC);
+  rcc2 = HWREG(SYSCTL_RCC2);
   
   /* modify */
-  rcc |= TIVA_RCC_BYPASS;
-  rcc &= ~TIVA_RCC_USESYSDIV;
-  rcc2 |= TIVA_RCC2_BYPASS2 | TIVA_RCC2_USERCC2;
+  rcc |= SYSCTL_RCC_BYPASS;
+  rcc &= ~SYSCTL_RCC_USESYSDIV;
+  rcc2 |= SYSCTL_RCC2_BYPASS2 | SYSCTL_RCC2_USERCC2;
   
   /* write */
-  SYSCTL->RCC = rcc;
-  SYSCTL->RCC2 = rcc2;
+  HWREG(SYSCTL_RCC) = rcc;
+  HWREG(SYSCTL_RCC2) = rcc2;
 
   /* 2 Select the crystal value (XTAL) and oscillator source (OSCSRC), and
    * clear the PWRDN bit in RCC and RCC2. Setting the XTAL field automatically
    * pulls valid PLL configuration data for the appropriate crystal, and
    * clearing the PWRDN bit powers and enables the PLL and its output. */
   /* modify */
-  rcc &= ~(TIVA_RCC_OSCSRC_MASK | TIVA_RCC_XTAL_MASK | TIVA_RCC_PWRDN | TIVA_RCC_MOSCDIS);
-  rcc |= ((TIVA_XTAL | TIVA_OSCSRC | TIVA_MOSCDIS) & (TIVA_RCC_XTAL_MASK | TIVA_RCC_OSCSRC_MASK | TIVA_RCC_MOSCDIS));
-  rcc2 &= ~(TIVA_RCC2_OSCSRC2_MASK | TIVA_RCC2_PWRDN2);
-  rcc2 |= ((TIVA_OSCSRC | TIVA_DIV400) & (TIVA_RCC2_OSCSRC2_MASK | TIVA_RCC2_DIV400));
+  rcc &= ~(SYSCTL_RCC_OSCSRC_M | SYSCTL_RCC_XTAL_M | SYSCTL_RCC_PWRDN | SYSCTL_RCC_MOSCDIS);
+  rcc |= ((TIVA_XTAL | TIVA_OSCSRC | TIVA_MOSCDIS) & (SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M | SYSCTL_RCC_MOSCDIS));
+  rcc2 &= ~(SYSCTL_RCC2_OSCSRC2_M | SYSCTL_RCC2_PWRDN2);
+  rcc2 |= ((TIVA_OSCSRC | TIVA_DIV400) & (SYSCTL_RCC2_OSCSRC2_M | SYSCTL_RCC2_DIV400));
   
   /* write */
-  SYSCTL->RCC = rcc;
-  SYSCTL->RCC2 = rcc2;
+  HWREG(SYSCTL_RCC) = rcc;
+  HWREG(SYSCTL_RCC2) = rcc2;
   for(i = 100000; i; i--);
 
   /* 3. Select the desired system divider (SYSDIV) in RCC and RCC2 and set the
    * USESYSDIV bit in RCC. The SYSDIV field determines the system frequency for
    * the microcontroller. */
   /* modify */
-  rcc &= ~TIVA_RCC_SYSDIV_MASK;
-  rcc |= (TIVA_SYSDIV & TIVA_RCC_SYSDIV_MASK) | TIVA_USESYSDIV;
-  rcc2 &= ~(TIVA_RCC2_SYSDIV2_MASK | TIVA_RCC2_SYSDIV2LSB);
-  rcc2 |= ((TIVA_SYSDIV2 | TIVA_SYSDIV2LSB) & (TIVA_RCC2_SYSDIV2_MASK | TIVA_RCC2_SYSDIV2LSB));
+  rcc &= ~SYSCTL_RCC_SYSDIV_M;
+  rcc |= (TIVA_SYSDIV & SYSCTL_RCC_SYSDIV_M) | SYSCTL_RCC_USESYSDIV;
+  rcc2 &= ~(SYSCTL_RCC2_SYSDIV2_M | SYSCTL_RCC2_SYSDIV2LSB);
+  rcc2 |= ((TIVA_SYSDIV2 | TIVA_SYSDIV2LSB) & (SYSCTL_RCC2_SYSDIV2_M | SYSCTL_RCC2_SYSDIV2LSB));
   
   /* write */
-  SYSCTL->RCC = rcc;
-  SYSCTL->RCC2 = rcc2;
+  HWREG(SYSCTL_RCC) = rcc;
+  HWREG(SYSCTL_RCC2) = rcc2;
 
   /* 4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw
    * Interrupt Status (RIS) register. */
-  while ((SYSCTL->RIS & SYSCTL_RIS_PLLLRIS) == 0);
+  while ((HWREG(SYSCTL_RIS) & SYSCTL_RIS_PLLLRIS) == 0);
 
   /* 5. Enable use of the PLL by clearing the BYPASS bit in RCC and RCC2. */
-  rcc &= ~TIVA_RCC_BYPASS;
-  rcc2 &= ~TIVA_RCC2_BYPASS2;
+  rcc &= ~SYSCTL_RCC_BYPASS;
+  rcc2 &= ~SYSCTL_RCC2_BYPASS2;
   rcc |= (TIVA_BYPASS_VALUE << 11);
   rcc2 |= (TIVA_BYPASS_VALUE << 11);
-  SYSCTL->RCC = rcc;
-  SYSCTL->RCC2 = rcc2;
+  HWREG(SYSCTL_RCC) = rcc;
+  HWREG(SYSCTL_RCC2) = rcc2;
 
 #if HAL_USE_PWM
-  SYSCTL->RCC |= TIVA_PWM_FIELDS;
+  HWREG(SYSCTL_RCC) |= TIVA_PWM_FIELDS;
 #endif
 
 #if defined(TIVA_UDMA_REQUIRED)
diff --git a/os/hal/ports/TIVA/TM4C123x/hal_lld.h b/os/hal/ports/TIVA/TM4C123x/hal_lld.h
index ec81806..5d38a67 100644
--- a/os/hal/ports/TIVA/TM4C123x/hal_lld.h
+++ b/os/hal/ports/TIVA/TM4C123x/hal_lld.h
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -45,123 +45,6 @@
  * @}
  */
 
-/**
- * @name    RCC register bits definitions
- * @{
- */
-
-#define TIVA_RCC_MOSCDIS            (0x01 << 0)
-
-#define TIVA_RCC_OSCSRC_MASK        (0x03 << 4)
-#define TIVA_RCC_OSCSRC_MOSC        (0x00 << 4)
-#define TIVA_RCC_OSCSRC_PIOSC       (0x01 << 4)
-#define TIVA_RCC_OSCSRC_PIOSC_4     (0x02 << 4)
-#define TIVA_RCC_OSCSRC_LFIOSC      (0x03 << 4)
-
-#define TIVA_RCC_XTAL_MASK          (0x1f << 6)
-#define TIVA_RCC_XTAL_4000000       (0x06 << 6)
-#define TIVA_RCC_XTAL_4096000       (0x07 << 6)
-#define TIVA_RCC_XTAL_4915200       (0x08 << 6)
-#define TIVA_RCC_XTAL_5000000       (0x09 << 6)
-#define TIVA_RCC_XTAL_5120000       (0x0a << 6)
-#define TIVA_RCC_XTAL_6000000       (0x0b << 6)
-#define TIVA_RCC_XTAL_6144000       (0x0c << 6)
-#define TIVA_RCC_XTAL_7372800       (0x0d << 6)
-#define TIVA_RCC_XTAL_8000000       (0x0e << 6)
-#define TIVA_RCC_XTAL_8192000       (0x0f << 6)
-#define TIVA_RCC_XTAL_10000000      (0x10 << 6)
-#define TIVA_RCC_XTAL_12000000      (0x11 << 6)
-#define TIVA_RCC_XTAL_12288000      (0x12 << 6)
-#define TIVA_RCC_XTAL_13560000      (0x13 << 6)
-#define TIVA_RCC_XTAL_14318180      (0x14 << 6)
-#define TIVA_RCC_XTAL_16000000      (0x15 << 6)
-#define TIVA_RCC_XTAL_16384000      (0x16 << 6)
-#define TIVA_RCC_XTAL_18000000      (0x17 << 6)
-#define TIVA_RCC_XTAL_20000000      (0x18 << 6)
-#define TIVA_RCC_XTAL_24000000      (0x19 << 6)
-#define TIVA_RCC_XTAL_25000000      (0x1a << 6)
-
-#define TIVA_RCC_BYPASS             (1 << 11)
-
-#define TIVA_RCC_PWRDN              (1 << 13)
-
-#define TIVA_RCC_PWMDIV_MASK        (0x07 << 17)
-#define TIVA_RCC_PWMDIV_2           (0x00 << 17)
-#define TIVA_RCC_PWMDIV_4           (0x01 << 17)
-#define TIVA_RCC_PWMDIV_8           (0x02 << 17)
-#define TIVA_RCC_PWMDIV_16          (0x03 << 17)
-#define TIVA_RCC_PWMDIV_32          (0x04 << 17)
-#define TIVA_RCC_PWMDIV_64          (0x07 << 17)
-
-#define TIVA_RCC_USEPWMDIV          (1 << 20)
-
-#define TIVA_RCC_USESYSDIV	        (1 << 22)
-
-#define TIVA_RCC_SYSDIV_MASK	    (0x0f << 23)
-#define TIVA_RCC_SYSDIV_1           (0x00 << 23)
-#define TIVA_RCC_SYSDIV_2           (0x01 << 23)
-#define TIVA_RCC_SYSDIV_3           (0x02 << 23)
-#define TIVA_RCC_SYSDIV_4           (0x03 << 23)
-#define TIVA_RCC_SYSDIV_5           (0x04 << 23)
-#define TIVA_RCC_SYSDIV_6           (0x05 << 23)
-#define TIVA_RCC_SYSDIV_7           (0x06 << 23)
-#define TIVA_RCC_SYSDIV_8           (0x07 << 23)
-#define TIVA_RCC_SYSDIV_9           (0x08 << 23)
-#define TIVA_RCC_SYSDIV_10          (0x09 << 23)
-#define TIVA_RCC_SYSDIV_11          (0x0a << 23)
-#define TIVA_RCC_SYSDIV_12          (0x0b << 23)
-#define TIVA_RCC_SYSDIV_13          (0x0c << 23)
-#define TIVA_RCC_SYSDIV_14          (0x0d << 23)
-#define TIVA_RCC_SYSDIV_15          (0x0e << 23)
-#define TIVA_RCC_SYSDIV_16          (0x0f << 23)
-
-#define TIVA_RCC_ACG		        (1 << 27)
-
-/**
- * @}
- */
-
-/**
- * @name    RCC2 register bits definitions
- * @{
- */
-
-#define TIVA_RCC2_OSCSRC2_MASK      (0x07 << 4)
-#define TIVA_RCC2_OSCSRC2_MOSC      (0x00 << 4)
-#define TIVA_RCC2_OSCSRC2_PIOSC     (0x01 << 4)
-#define TIVA_RCC2_OSCSRC2_PIOSC_4   (0x02 << 4)
-#define TIVA_RCC2_OSCSRC2_LFIOSC    (0x03 << 4)
-#define TIVA_RCC2_OSCSRC2_32768     (0x07 << 4)
-
-#define TIVA_RCC2_BYPASS2           (1 << 11)
-
-#define TIVA_RCC2_PWRDN2            (1 << 13)
-
-#define TIVA_RCC2_USBPWRDN          (1 << 14)
-
-#define TIVA_RCC2_SYSDIV2LSB        (1 << 22)
-
-#define TIVA_RCC2_SYSDIV2_MASK      (0x3f << 23)
-
-#define TIVA_RCC2_DIV400            (1 << 30)
-
-#define TIVA_RCC2_USERCC2           (1 << 31)
-
-/**
- * @}
- */
-
-/**
- * @name    RIS register bits definitions
- * @{
- */
-
-#define SYSCTL_RIS_PLLLRIS	            (1 << 6)
-
-/**
- * @}
- */
-
 /*===========================================================================*/
 /* Driver pre-compile time settings.                                         */
 /*===========================================================================*/
@@ -172,7 +55,7 @@
  */
 
 #if !defined(TIVA_OSCSRC)
-#define TIVA_OSCSRC                     TIVA_RCC2_OSCSRC2_MOSC
+#define TIVA_OSCSRC                     SYSCTL_RCC2_OSCSRC2_MO
 #endif
 
 #if !defined(TIVA_MOSC_ENABLE)
@@ -217,56 +100,56 @@
 /*
  * Oscillator-related checks.
  */
-#if !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_MOSC) &&                                 \
-    !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_PIOSC) &&                                \
-    !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_PIOSC_4) &&                              \
-    !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_LFIOSC) &&                               \
-    !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_32768)
+#if !(TIVA_OSCSRC == SYSCTL_RCC2_OSCSRC2_MO) &&                                 \
+    !(TIVA_OSCSRC == SYSCTL_RCC2_OSCSRC2_IO) &&                                \
+    !(TIVA_OSCSRC == SYSCTL_RCC2_OSCSRC2_IO4) &&                              \
+    !(TIVA_OSCSRC == SYSCTL_RCC2_OSCSRC2_30) &&                               \
+    !(TIVA_OSCSRC == SYSCTL_RCC2_OSCSRC2_32)
 #error "Invalid value for TIVA_OSCSRC defined"
 #endif
 
 #if TIVA_XTAL_VALUE == 4000000
-#define TIVA_XTAL_              (0x06 << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_4MHZ
 #elif TIVA_XTAL_VALUE == 4096000
-#define TIVA_XTAL_              (0x07 << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_4_09MHZ
 #elif TIVA_XTAL_VALUE == 4915200
-#define TIVA_XTAL_              (0x08 << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_4_91MHZ
 #elif TIVA_XTAL_VALUE == 5000000
-#define TIVA_XTAL_              (0x09 << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_5MHZ
 #elif TIVA_XTAL_VALUE == 5120000
-#define TIVA_XTAL_              (0x0a << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_5_12MHZ
 #elif TIVA_XTAL_VALUE == 6000000
-#define TIVA_XTAL_              (0x0b << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_6MHZ
 #elif TIVA_XTAL_VALUE == 6144000
-#define TIVA_XTAL_              (0x0c << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_6_14MHZ
 #elif TIVA_XTAL_VALUE == 7372800
-#define TIVA_XTAL_              (0x0d << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_7_37MHZ
 #elif TIVA_XTAL_VALUE == 8000000
-#define TIVA_XTAL_              (0x0e << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_8MHZ
 #elif TIVA_XTAL_VALUE == 8192000
-#define TIVA_XTAL_              (0x0f << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_8_19MHZ
 #elif TIVA_XTAL_VALUE == 10000000
-#define TIVA_XTAL_              (0x10 << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_10MHZ
 #elif TIVA_XTAL_VALUE == 12000000
-#define TIVA_XTAL_              (0x11 << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_12MHZ
 #elif TIVA_XTAL_VALUE == 12288000
-#define TIVA_XTAL_              (0x12 << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_12_2MHZ
 #elif TIVA_XTAL_VALUE == 13560000
-#define TIVA_XTAL_              (0x13 << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_13_5MHZ
 #elif TIVA_XTAL_VALUE == 14318180
-#define TIVA_XTAL_              (0x14 << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_14_3MHZ
 #elif TIVA_XTAL_VALUE == 16000000
-#define TIVA_XTAL_              (0x15 << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_16MHZ
 #elif TIVA_XTAL_VALUE == 16384000
-#define TIVA_XTAL_              (0x16 << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_16_3MHZ
 #elif TIVA_XTAL_VALUE == 18000000
-#define TIVA_XTAL_              (0x17 << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_18MHZ
 #elif TIVA_XTAL_VALUE == 20000000
-#define TIVA_XTAL_              (0x18 << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_20MHZ
 #elif TIVA_XTAL_VALUE == 24000000
-#define TIVA_XTAL_              (0x19 << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_24MHZ
 #elif TIVA_XTAL_VALUE == 25000000
-#define TIVA_XTAL_              (0x1a << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_25MHZ
 #else
 #error "Invalid value for TIVA_XTAL_VALUE defined"
 #endif
@@ -320,7 +203,7 @@
 #error "Invalid value for TIVA_BYPASS_VALUE defined"
 #endif
 
-#if (TIVA_OSCSRC == TIVA_RCC_OSCSRC_MOSC) && (TIVA_MOSC_ENABLE == FALSE)
+#if (TIVA_OSCSRC == SYSCTL_RCC2_OSCSRC2_MO) && (TIVA_MOSC_ENABLE == FALSE)
 #error "Main Oscillator selected but not enabled"
 #endif
 
diff --git a/os/hal/ports/TIVA/TM4C123x/platform.mk b/os/hal/ports/TIVA/TM4C123x/platform.mk
index 0abafcc..8e447ec 100644
--- a/os/hal/ports/TIVA/TM4C123x/platform.mk
+++ b/os/hal/ports/TIVA/TM4C123x/platform.mk
@@ -1,18 +1,33 @@
-# List of all the TM4C123x platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
-              ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C123x/hal_lld.c \
-              ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_st_lld.c \
-              ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_pal_lld.c \
-              ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_serial_lld.c \
-              ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_i2c_lld.c \
-              ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_gpt_lld.c \
-              ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_pwm_lld.c \
-              ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_spi_lld.c \
-              ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/tiva_udma.c \
-              ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_ext_lld.c \
-              ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_wdg_lld.c
+# Required platform files.
+PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C123x/hal_lld.c
 
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
-              ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C123x \
-              ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD
+# Required include directories.
+PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C123x
+
+ifeq ($(USE_SMART_BUILD),yes)
+
+# Configuration files directory
+ifeq ($(CONFDIR),)
+  CONFDIR = .
+endif
+
+HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h | egrep -e "\#define"))
+else
+endif
+
+# Drivers compatible with the platform.
+include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/ADC/driver.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPIO/driver.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPTM/driver.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/I2C/driver.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/PWM/driver.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/SSI/driver.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/driver.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/uDMA/driver.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/WDT/driver.mk
+
+# Shared variables
+ALLCSRC += $(PLATFORMSRC)
+ALLINC  += $(PLATFORMINC)
diff --git a/os/hal/ports/TIVA/TM4C123x/tiva_isr.h b/os/hal/ports/TIVA/TM4C123x/tiva_isr.h
index b380e46..f4bec51 100644
--- a/os/hal/ports/TIVA/TM4C123x/tiva_isr.h
+++ b/os/hal/ports/TIVA/TM4C123x/tiva_isr.h
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -42,11 +42,11 @@
 #define TIVA_UDMA_ERR_NUMBER                47
 
 /* GPIO units.*/
-#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
-  || defined(TM4C1230H6PM) || defined(TM4C1232C3PM) || defined(TM4C1232D5PM)  \
-  || defined(TM4C1232E6PM) || defined(TM4C1232H6PM) || defined(TM4C1236D5PM)  \
-  || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) || defined(TM4C123AE6PM)  \
-  || defined(TM4C123AH6PM) || defined(TM4C123FE6PM) || defined(TM4C123FH6PM)
+#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM)   \
+  || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM)  \
+  || defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1236D5PM)  \
+  || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) || defined(PART_TM4C123AE6PM)  \
+  || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM)
 #define TIVA_GPIOA_HANDLER                  Vector40
 #define TIVA_GPIOB_HANDLER                  Vector44
 #define TIVA_GPIOC_HANDLER                  Vector48
@@ -63,11 +63,11 @@
 #define TIVA_GPIOF_NUMBER                   30
 #define TIVA_GPIOG_NUMBER                   31
 #endif
-#if defined(TM4C1231C3PM) || defined(TM4C1231D5PM) || defined(TM4C1231E6PM)   \
-  || defined(TM4C1231H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
-  || defined(TM4C1233E6PM) || defined(TM4C1233H6PM) || defined(TM4C1237D5PM)  \
-  || defined(TM4C1237E6PM) || defined(TM4C1237H6PM) || defined(TM4C123BE6PM)  \
-  || defined(TM4C123BH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM)
+#if defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231E6PM)   \
+  || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM)  \
+  || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1237D5PM)  \
+  || defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237H6PM) || defined(PART_TM4C123BE6PM)  \
+  || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GH6PM)
 #define TIVA_GPIOA_HANDLER                  Vector40
 #define TIVA_GPIOB_HANDLER                  Vector44
 #define TIVA_GPIOC_HANDLER                  Vector48
@@ -82,11 +82,11 @@
 #define TIVA_GPIOE_NUMBER                   4
 #define TIVA_GPIOF_NUMBER                   30
 #endif
-#if defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) || defined(TM4C1231H6PZ)   \
-  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) || defined(TM4C1233H6PZ)  \
-  || defined(TM4C1237D5PZ) || defined(TM4C1237E6PZ) || defined(TM4C1237H6PZ)  \
-  || defined(TM4C123BE6PZ) || defined(TM4C123BH6PZ) || defined(TM4C123GE6PZ)  \
-  || defined(TM4C123GH6PZ)
+#if defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PZ) || defined(PART_TM4C1231H6PZ)   \
+  || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PZ)  \
+  || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PZ)  \
+  || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123GE6PZ)  \
+  || defined(PART_TM4C123GH6PZ)
 #define TIVA_GPIOA_HANDLER                  Vector40
 #define TIVA_GPIOB_HANDLER                  Vector44
 #define TIVA_GPIOC_HANDLER                  Vector48
@@ -111,8 +111,8 @@
 #define TIVA_GPIOK_NUMBER                   55
 #define TIVA_GPIOL_NUMBER                   56
 #endif
-#if defined(TM4C1231H6PGE) || defined(TM4C1233H6PGE) || defined(TM4C1237H6PGE)\
-  || defined(TM4C123BH6PGE) || defined(TM4C123GH6PGE)
+#if defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1237H6PGE)\
+  || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123GH6PGE)
 #define TIVA_GPIOA_HANDLER                  Vector40
 #define TIVA_GPIOB_HANDLER                  Vector44
 #define TIVA_GPIOC_HANDLER                  Vector48
@@ -157,7 +157,7 @@
 #define TIVA_GPIOP6_NUMBER                  122
 #define TIVA_GPIOP7_NUMBER                  123
 #endif
-#if defined(TM4C123BH6ZRB) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#if defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR)
 #define TIVA_GPIOA_HANDLER                  Vector40
 #define TIVA_GPIOB_HANDLER                  Vector44
 #define TIVA_GPIOC_HANDLER                  Vector48
@@ -220,23 +220,23 @@
 #endif
 
 /* GPTM units.*/
-#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
-  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
-  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
-  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
-  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
-  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
-  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
-  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
-  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
-  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
-  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
-  || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM)  \
-  || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \
-  || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \
-  || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM)  \
-  || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \
-  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM)   \
+  || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM)  \
+  || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ)  \
+  || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \
+  || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM)  \
+  || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM)  \
+  || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ)  \
+  || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \
+  || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM)  \
+  || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM)  \
+  || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \
+  || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM)  \
+  || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \
+  || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \
+  || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM)  \
+  || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \
+  || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR)
 #define TIVA_GPT0A_HANDLER                   Vector8C
 #define TIVA_GPT0B_HANDLER                   Vector90
 #define TIVA_GPT1A_HANDLER                   Vector94
@@ -291,46 +291,46 @@
 #endif
 
 /* WDT units.*/
-#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
-  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
-  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
-  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
-  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
-  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
-  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
-  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
-  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
-  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
-  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
-  || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM)  \
-  || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \
-  || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \
-  || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM)  \
-  || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \
-  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM)   \
+  || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM)  \
+  || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ)  \
+  || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \
+  || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM)  \
+  || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM)  \
+  || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ)  \
+  || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \
+  || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM)  \
+  || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM)  \
+  || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \
+  || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM)  \
+  || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \
+  || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \
+  || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM)  \
+  || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \
+  || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR)
 #define TIVA_WDT_HANDLER                    Vector88
 
 #define TIVA_WDT_NUMBER                     18
 #endif
 
 /* ADC units.*/
-#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
-  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
-  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
-  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
-  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
-  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
-  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
-  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
-  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
-  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
-  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
-  || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM)  \
-  || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \
-  || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \
-  || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM)  \
-  || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \
-  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM)   \
+  || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM)  \
+  || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ)  \
+  || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \
+  || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM)  \
+  || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM)  \
+  || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ)  \
+  || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \
+  || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM)  \
+  || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM)  \
+  || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \
+  || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM)  \
+  || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \
+  || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \
+  || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM)  \
+  || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \
+  || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR)
 #define TIVA_ADC0_SEQ0_HANDLER              Vector78
 #define TIVA_ADC0_SEQ1_HANDLER              Vector7C
 #define TIVA_ADC0_SEQ2_HANDLER              Vector80
@@ -351,23 +351,23 @@
 #endif
 
 /* UART units.*/
-#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
-  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
-  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
-  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
-  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
-  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
-  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
-  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
-  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
-  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
-  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
-  || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM)  \
-  || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \
-  || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \
-  || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM)  \
-  || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \
-  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM)   \
+  || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM)  \
+  || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ)  \
+  || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \
+  || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM)  \
+  || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM)  \
+  || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ)  \
+  || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \
+  || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM)  \
+  || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM)  \
+  || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \
+  || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM)  \
+  || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \
+  || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \
+  || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM)  \
+  || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \
+  || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR)
 #define TIVA_UART0_HANDLER                  Vector54
 #define TIVA_UART1_HANDLER                  Vector58
 #define TIVA_UART2_HANDLER                  VectorC4
@@ -388,23 +388,23 @@
 #endif
 
 /* SPI units.*/
-#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
-  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
-  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
-  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
-  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
-  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
-  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
-  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
-  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
-  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
-  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
-  || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM)  \
-  || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \
-  || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \
-  || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM)  \
-  || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \
-  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM)   \
+  || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM)  \
+  || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ)  \
+  || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \
+  || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM)  \
+  || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM)  \
+  || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ)  \
+  || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \
+  || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM)  \
+  || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM)  \
+  || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \
+  || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM)  \
+  || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \
+  || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \
+  || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM)  \
+  || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \
+  || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR)
 #define TIVA_SSI0_HANDLER                   Vector5C
 #define TIVA_SSI1_HANDLER                   VectorC8
 #define TIVA_SSI2_HANDLER                   Vector124
@@ -417,18 +417,18 @@
 #endif
 
 /* I2C units.*/
-#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
-  || defined(TM4C1230H6PM) || defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ)  \
-  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PZ) || defined(TM4C1232C3PM) \
-  || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) || defined(TM4C1232H6PM)  \
-  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) || defined(TM4C1233H6PGE) \
-  || defined(TM4C1233H6PZ) || defined(TM4C1236D5PM) || defined(TM4C1236E6PM)  \
-  || defined(TM4C1236H6PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PZ)  \
-  || defined(TM4C1237H6PGE) || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) \
-  || defined(TM4C123AH6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \
-  || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \
-  || defined(TM4C123FH6PM) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) \
-  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM)   \
+  || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PZ)  \
+  || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PZ) || defined(PART_TM4C1232C3PM) \
+  || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM)  \
+  || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PGE) \
+  || defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM)  \
+  || defined(PART_TM4C1236H6PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PZ)  \
+  || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) \
+  || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \
+  || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123FE6PM) \
+  || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) \
+  || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR)
 #define TIVA_I2C0_HANDLER                   Vector60
 #define TIVA_I2C1_HANDLER                   VectorD4
 #define TIVA_I2C2_HANDLER                   Vector150
@@ -443,11 +443,11 @@
 #define TIVA_I2C4_NUMBER                    109
 #define TIVA_I2C5_NUMBER                    110
 #endif
-#if defined(TM4C1231C3PM) || defined(TM4C1231D5PM) || defined(TM4C1231E6PM)   \
-  || defined(TM4C1231H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
-  || defined(TM4C1233E6PM) || defined(TM4C1233H6PM) || defined(TM4C1237D5PM)  \
-  || defined(TM4C1237E6PM) || defined(TM4C1237H6PM) || defined(TM4C123BE6PM)  \
-  || defined(TM4C123BH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM)
+#if defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231E6PM)   \
+  || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM)  \
+  || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1237D5PM)  \
+  || defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237H6PM) || defined(PART_TM4C123BE6PM)  \
+  || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GH6PM)
 #define TIVA_I2C0_HANDLER                   Vector60
 #define TIVA_I2C1_HANDLER                   VectorD4
 #define TIVA_I2C2_HANDLER                   Vector150
@@ -460,28 +460,28 @@
 #endif
 
 /* CAN units.*/
-#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
-  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
-  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
-  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
-  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
-  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
-  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
-  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
-  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
-  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
-  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
-  || defined(TM4C1237H6PZ)
+#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM)   \
+  || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM)  \
+  || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ)  \
+  || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \
+  || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM)  \
+  || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM)  \
+  || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ)  \
+  || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \
+  || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM)  \
+  || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM)  \
+  || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \
+  || defined(PART_TM4C1237H6PZ)
 #define TIVA_CAN0_HANDLER                   VectorDC
 
 #define TIVA_CAN0_NUMBER                    39
 #endif
-#if defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM)   \
-  || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \
-  || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \
-  || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ)  \
-  || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) \
-  || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#if defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PM)   \
+  || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PM) \
+  || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123FE6PM) \
+  || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ)  \
+  || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) \
+  || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR)
 #define TIVA_CAN0_HANDLER                   VectorDC
 #define TIVA_CAN1_HANDLER                   VectorE0
 
@@ -490,55 +490,55 @@
 #endif
 
 /* USB units.*/
-#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
-  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
-  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
-  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
-  || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM)  \
-  || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \
-  || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB)
+#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM)   \
+  || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM)  \
+  || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ)  \
+  || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \
+  || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PM)  \
+  || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PM) \
+  || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB)
 /* No interrupt handler and number.*/
 #endif
-#if defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)   \
-  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
-  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
-  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
-  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
-  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
-  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
-  || defined(TM4C1237H6PZ) || defined(TM4C123FE6PM) || defined(TM4C123FH6PM)  \
-  || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) \
-  || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) \
-  || defined(TM4C123GH5ZXR)
+#if defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM)   \
+  || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM)  \
+  || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ)  \
+  || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \
+  || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM)  \
+  || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM)  \
+  || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \
+  || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM)  \
+  || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) \
+  || defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) \
+  || defined(PART_TM4C123GH5ZXR)
 #define TIVA_USB0_HANDLER                   VectorF0
 
 #define TIVA_USB0_NUMBER                    44
 #endif
 
 /* AC units.*/
-#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
-  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
-  || defined(TM4C1231E6PM) || defined(TM4C1231H6PM) || defined(TM4C1232C3PM)  \
-  || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) || defined(TM4C1232H6PM)  \
-  || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) || defined(TM4C1233E6PM)  \
-  || defined(TM4C1233H6PM) || defined(TM4C1236D5PM) || defined(TM4C1236E6PM)  \
-  || defined(TM4C1236H6PM) || defined(TM4C1237D5PM) || defined(TM4C1237E6PM)  \
-  || defined(TM4C1237H6PM) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM)  \
-  || defined(TM4C123BE6PM) || defined(TM4C123BH6PM) || defined(TM4C123FE6PM)  \
-  || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM)
+#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM)   \
+  || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM)  \
+  || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1232C3PM)  \
+  || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM)  \
+  || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) || defined(PART_TM4C1233E6PM)  \
+  || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM)  \
+  || defined(PART_TM4C1236H6PM) || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237E6PM)  \
+  || defined(PART_TM4C1237H6PM) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM)  \
+  || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123FE6PM)  \
+  || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GH6PM)
 #define TIVA_AC0_HANDLER                    VectorA4
 #define TIVA_AC1_HANDLER                    VectorA8
 
 #define TIVA_AC0_NUMBER                     25
 #define TIVA_AC1_NUMBER                     26
 #endif
-#if defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) || defined(TM4C1231H6PGE)  \
-  || defined(TM4C1231H6PZ) || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ)  \
-  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PZ) || defined(TM4C1237D5PZ) \
-  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PZ) \
-  || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PZ) \
-  || defined(TM4C123BH6ZRB) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE)\
-  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#if defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PZ) || defined(PART_TM4C1231H6PGE)  \
+  || defined(PART_TM4C1231H6PZ) || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PZ)  \
+  || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1237D5PZ) \
+  || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PZ) \
+  || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PZ) \
+  || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE)\
+  || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR)
 #define TIVA_AC0_HANDLER                    VectorA4
 #define TIVA_AC1_HANDLER                    VectorA8
 #define TIVA_AC2_HANDLER                    VectorAC
@@ -549,26 +549,26 @@
 #endif
 
 /* PWM units.*/
-#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
-  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
-  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
-  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
-  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
-  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
-  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
-  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
-  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
-  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
-  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
-  || defined(TM4C1237H6PZ)
+#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM)   \
+  || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM)  \
+  || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ)  \
+  || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \
+  || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM)  \
+  || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM)  \
+  || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ)  \
+  || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \
+  || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM)  \
+  || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM)  \
+  || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \
+  || defined(PART_TM4C1237H6PZ)
 /* No interrupt handler and number.*/
 #endif
-#if defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM)   \
-  || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \
-  || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \
-  || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ)  \
-  || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) \
-  || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#if defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PM)   \
+  || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PM) \
+  || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123FE6PM) \
+  || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ)  \
+  || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) \
+  || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR)
 #define TIVA_PWM0FAULT_HANDLER              Vector64
 #define TIVA_PWM0GEN0_HANDLER               Vector68
 #define TIVA_PWM0GEN1_HANDLER               Vector6C
@@ -593,25 +593,25 @@
 #endif
 
 /* QEI units.*/
-#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
-  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
-  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
-  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
-  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
-  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
-  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
-  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
-  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
-  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
-  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
-  || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM)
+#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM)   \
+  || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM)  \
+  || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ)  \
+  || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \
+  || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM)  \
+  || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM)  \
+  || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ)  \
+  || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \
+  || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM)  \
+  || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM)  \
+  || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \
+  || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM)
 /* No interrupt handler and number.*/
 #endif
-#if defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE)  \
-  || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \
-  || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM)  \
-  || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \
-  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#if defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE)  \
+  || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \
+  || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM)  \
+  || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \
+  || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR)
 #define TIVA_QEI0_HANLDER                   Vector74
 #define TIVA_QEI1_HANLDER                   VectorD8
 
diff --git a/os/hal/ports/TIVA/TM4C123x/tiva_registry.h b/os/hal/ports/TIVA/TM4C123x/tiva_registry.h
index ac7a1d2..7604936 100644
--- a/os/hal/ports/TIVA/TM4C123x/tiva_registry.h
+++ b/os/hal/ports/TIVA/TM4C123x/tiva_registry.h
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -29,35 +29,41 @@
 /* Defined device check.                                                     */
 /*===========================================================================*/
 
-#if !defined(TM4C1230C3PM) && !defined(TM4C1230D5PM) &&                       \
-  !defined(TM4C1230E6PM) && !defined(TM4C1230H6PM) &&                         \
-  !defined(TM4C1231C3PM) && !defined(TM4C1231D5PM) &&                         \
-  !defined(TM4C1231D5PZ) && !defined(TM4C1231E6PM) &&                         \
-  !defined(TM4C1231E6PZ) && !defined(TM4C1231H6PGE) &&                        \
-  !defined(TM4C1231H6PM) && !defined(TM4C1231H6PZ) &&                         \
-  !defined(TM4C1232C3PM) && !defined(TM4C1232D5PM) &&                         \
-  !defined(TM4C1232E6PM) && !defined(TM4C1232H6PM) &&                         \
-  !defined(TM4C1233C3PM) && !defined(TM4C1233D5PM) &&                         \
-  !defined(TM4C1233D5PZ) && !defined(TM4C1233E6PM) &&                         \
-  !defined(TM4C1233E6PZ) && !defined(TM4C1233H6PGE) &&                        \
-  !defined(TM4C1233H6PM) && !defined(TM4C1233H6PZ) &&                         \
-  !defined(TM4C1236D5PM) && !defined(TM4C1236E6PM) &&                         \
-  !defined(TM4C1236H6PM) && !defined(TM4C1237D5PM) &&                         \
-  !defined(TM4C1237D5PZ) && !defined(TM4C1237E6PM) &&                         \
-  !defined(TM4C1237E6PZ) && !defined(TM4C1237H6PGE) &&                        \
-  !defined(TM4C1237H6PM) && !defined(TM4C1237H6PZ) &&                         \
-  !defined(TM4C123AE6PM) && !defined(TM4C123AH6PM) &&                         \
-  !defined(TM4C123BE6PM) && !defined(TM4C123BE6PZ) &&                         \
-  !defined(TM4C123BH6PGE) && !defined(TM4C123BH6PM) &&                        \
-  !defined(TM4C123BH6PZ) && !defined(TM4C123BH6ZRB) &&                        \
-  !defined(TM4C123FE6PM) && !defined(TM4C123FH6PM) &&                         \
-  !defined(TM4C123GE6PM) && !defined(TM4C123GE6PZ) &&                         \
-  !defined(TM4C123GH6PGE) && !defined(TM4C123GH6PM) &&                        \
-  !defined(TM4C123GH6PZ) && !defined(TM4C123GH6ZRB) &&                        \
-  !defined(TM4C123GH5ZXR)
+#if !defined(PART_TM4C1230C3PM) && !defined(PART_TM4C1230D5PM) &&                       \
+  !defined(PART_TM4C1230E6PM) && !defined(PART_TM4C1230H6PM) &&                         \
+  !defined(PART_TM4C1231C3PM) && !defined(PART_TM4C1231D5PM) &&                         \
+  !defined(PART_TM4C1231D5PZ) && !defined(PART_TM4C1231E6PM) &&                         \
+  !defined(PART_TM4C1231E6PZ) && !defined(PART_TM4C1231H6PGE) &&                        \
+  !defined(PART_TM4C1231H6PM) && !defined(PART_TM4C1231H6PZ) &&                         \
+  !defined(PART_TM4C1232C3PM) && !defined(PART_TM4C1232D5PM) &&                         \
+  !defined(PART_TM4C1232E6PM) && !defined(PART_TM4C1232H6PM) &&                         \
+  !defined(PART_TM4C1233C3PM) && !defined(PART_TM4C1233D5PM) &&                         \
+  !defined(PART_TM4C1233D5PZ) && !defined(PART_TM4C1233E6PM) &&                         \
+  !defined(PART_TM4C1233E6PZ) && !defined(PART_TM4C1233H6PGE) &&                        \
+  !defined(PART_TM4C1233H6PM) && !defined(PART_TM4C1233H6PZ) &&                         \
+  !defined(PART_TM4C1236D5PM) && !defined(PART_TM4C1236E6PM) &&                         \
+  !defined(PART_TM4C1236H6PM) && !defined(PART_TM4C1237D5PM) &&                         \
+  !defined(PART_TM4C1237D5PZ) && !defined(PART_TM4C1237E6PM) &&                         \
+  !defined(PART_TM4C1237E6PZ) && !defined(PART_TM4C1237H6PGE) &&                        \
+  !defined(PART_TM4C1237H6PM) && !defined(PART_TM4C1237H6PZ) &&                         \
+  !defined(PART_TM4C123AE6PM) && !defined(PART_TM4C123AH6PM) &&                         \
+  !defined(PART_TM4C123BE6PM) && !defined(PART_TM4C123BE6PZ) &&                         \
+  !defined(PART_TM4C123BH6PGE) && !defined(PART_TM4C123BH6PM) &&                        \
+  !defined(PART_TM4C123BH6PZ) && !defined(PART_TM4C123BH6ZRB) &&                        \
+  !defined(PART_TM4C123FE6PM) && !defined(PART_TM4C123FH6PM) &&                         \
+  !defined(PART_TM4C123GE6PM) && !defined(PART_TM4C123GE6PZ) &&                         \
+  !defined(PART_TM4C123GH6PGE) && !defined(PART_TM4C123GH6PM) &&                        \
+  !defined(PART_TM4C123GH6PZ) && !defined(PART_TM4C123GH6ZRB) &&                        \
+  !defined(PART_TM4C123GH5ZXR)
 #error "No valid device defined."
 #endif
 
+#if !defined(TARGET_IS_TM4C123_RA1) && !defined(TARGET_IS_TM4C123_RA2) && \
+    !defined(TARGET_IS_TM4C123_RA3) && !defined(TARGET_IS_TM4C123_RB0) && \
+    !defined(TARGET_IS_TM4C123_RB1)
+#error "No valid device revision defined."
+#endif
+
 /**
  * @brief   Sub-family identifier.
  */
@@ -75,11 +81,11 @@
  */
 
 /* GPIO attributes.*/
-#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
-  || defined(TM4C1230H6PM) || defined(TM4C1232C3PM) || defined(TM4C1232D5PM)  \
-  || defined(TM4C1232E6PM) || defined(TM4C1232H6PM) || defined(TM4C1236D5PM)  \
-  || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) || defined(TM4C123AE6PM)  \
-  || defined(TM4C123AH6PM) || defined(TM4C123FE6PM) || defined(TM4C123FH6PM)
+#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM)   \
+  || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM)  \
+  || defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1236D5PM)  \
+  || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) || defined(PART_TM4C123AE6PM)  \
+  || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM)
 #define TIVA_HAS_GPIOA                      TRUE
 #define TIVA_HAS_GPIOB                      TRUE
 #define TIVA_HAS_GPIOC                      TRUE
@@ -100,11 +106,11 @@
 #define TIVA_HAS_GPIOT                      FALSE
 #define TIVA_GPIO_PINS                      56
 #endif
-#if defined(TM4C1231C3PM) || defined(TM4C1231D5PM) || defined(TM4C1231E6PM)   \
-  || defined(TM4C1231H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
-  || defined(TM4C1233E6PM) || defined(TM4C1233H6PM) || defined(TM4C1237D5PM)  \
-  || defined(TM4C1237E6PM) || defined(TM4C1237H6PM) || defined(TM4C123BE6PM)  \
-  || defined(TM4C123BH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM)
+#if defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231E6PM)   \
+  || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM)  \
+  || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1237D5PM)  \
+  || defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237H6PM) || defined(PART_TM4C123BE6PM)  \
+  || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GH6PM)
 #define TIVA_HAS_GPIOA                      TRUE
 #define TIVA_HAS_GPIOB                      TRUE
 #define TIVA_HAS_GPIOC                      TRUE
@@ -125,11 +131,11 @@
 #define TIVA_HAS_GPIOT                      FALSE
 #define TIVA_GPIO_PINS                      48
 #endif
-#if defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) || defined(TM4C1231H6PZ)   \
-  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) || defined(TM4C1233H6PZ)  \
-  || defined(TM4C1237D5PZ) || defined(TM4C1237E6PZ) || defined(TM4C1237H6PZ)  \
-  || defined(TM4C123BE6PZ) || defined(TM4C123BH6PZ) || defined(TM4C123GE6PZ)  \
-  || defined(TM4C123GH6PZ)
+#if defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PZ) || defined(PART_TM4C1231H6PZ)   \
+  || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PZ)  \
+  || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PZ)  \
+  || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123GE6PZ)  \
+  || defined(PART_TM4C123GH6PZ)
 #define TIVA_HAS_GPIOA                      TRUE
 #define TIVA_HAS_GPIOB                      TRUE
 #define TIVA_HAS_GPIOC                      TRUE
@@ -150,8 +156,8 @@
 #define TIVA_HAS_GPIOT                      FALSE
 #define TIVA_GPIO_PINS                      88
 #endif
-#if defined(TM4C1231H6PGE) || defined(TM4C1233H6PGE) || defined(TM4C1237H6PGE)\
-  || defined(TM4C123BH6PGE) || defined(TM4C123GH6PGE)
+#if defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1237H6PGE)\
+  || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123GH6PGE)
 #define TIVA_HAS_GPIOA                      TRUE
 #define TIVA_HAS_GPIOB                      TRUE
 #define TIVA_HAS_GPIOC                      TRUE
@@ -172,7 +178,7 @@
 #define TIVA_HAS_GPIOT                      FALSE
 #define TIVA_GPIO_PINS                      112
 #endif
-#if defined(TM4C123BH6ZRB) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#if defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR)
 #define TIVA_HAS_GPIOA                      TRUE
 #define TIVA_HAS_GPIOB                      TRUE
 #define TIVA_HAS_GPIOC                      TRUE
@@ -195,23 +201,23 @@
 #endif
 
 /* GPTM attributes.*/
-#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
-  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
-  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
-  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
-  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
-  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
-  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
-  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
-  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
-  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
-  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
-  || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM)  \
-  || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \
-  || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \
-  || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM)  \
-  || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \
-  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM)   \
+  || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM)  \
+  || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ)  \
+  || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \
+  || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM)  \
+  || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM)  \
+  || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ)  \
+  || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \
+  || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM)  \
+  || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM)  \
+  || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \
+  || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM)  \
+  || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \
+  || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \
+  || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM)  \
+  || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \
+  || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR)
 #define TIVA_HAS_GPT0                       TRUE
 #define TIVA_HAS_GPT1                       TRUE
 #define TIVA_HAS_GPT2                       TRUE
@@ -229,67 +235,67 @@
 #endif
 
 /* WDT attributes.*/
-#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
-  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
-  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
-  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
-  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
-  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
-  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
-  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
-  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
-  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
-  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
-  || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM)  \
-  || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \
-  || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \
-  || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM)  \
-  || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \
-  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM)   \
+  || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM)  \
+  || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ)  \
+  || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \
+  || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM)  \
+  || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM)  \
+  || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ)  \
+  || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \
+  || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM)  \
+  || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM)  \
+  || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \
+  || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM)  \
+  || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \
+  || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \
+  || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM)  \
+  || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \
+  || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR)
 #define TIVA_HAS_WDT0                       TRUE
 #define TIVA_HAS_WDT1                       TRUE
 #endif
 
 /* ADC attributes.*/
-#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
-  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
-  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
-  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
-  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
-  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
-  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
-  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
-  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
-  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
-  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
-  || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM)  \
-  || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \
-  || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \
-  || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM)  \
-  || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \
-  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM)   \
+  || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM)  \
+  || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ)  \
+  || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \
+  || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM)  \
+  || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM)  \
+  || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ)  \
+  || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \
+  || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM)  \
+  || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM)  \
+  || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \
+  || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM)  \
+  || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \
+  || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \
+  || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM)  \
+  || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \
+  || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR)
 #define TIVA_HAS_ADC0                       TRUE
 #define TIVA_HAS_ADC1                       TRUE
 #endif
 
 /* UART attributes.*/
-#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
-  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
-  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
-  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
-  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
-  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
-  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
-  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
-  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
-  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
-  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
-  || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM)  \
-  || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \
-  || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \
-  || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM)  \
-  || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \
-  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM)   \
+  || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM)  \
+  || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ)  \
+  || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \
+  || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM)  \
+  || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM)  \
+  || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ)  \
+  || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \
+  || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM)  \
+  || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM)  \
+  || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \
+  || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM)  \
+  || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \
+  || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \
+  || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM)  \
+  || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \
+  || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR)
 #define TIVA_HAS_UART0                      TRUE
 #define TIVA_HAS_UART1                      TRUE
 #define TIVA_HAS_UART2                      TRUE
@@ -301,23 +307,23 @@
 #endif
 
 /* SPI attributes.*/
-#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
-  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
-  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
-  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
-  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
-  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
-  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
-  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
-  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
-  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
-  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
-  || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM)  \
-  || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \
-  || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \
-  || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM)  \
-  || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \
-  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM)   \
+  || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM)  \
+  || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ)  \
+  || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \
+  || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM)  \
+  || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM)  \
+  || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ)  \
+  || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \
+  || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM)  \
+  || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM)  \
+  || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \
+  || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM)  \
+  || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \
+  || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \
+  || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM)  \
+  || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \
+  || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR)
 #define TIVA_HAS_SSI0                       TRUE
 #define TIVA_HAS_SSI1                       TRUE
 #define TIVA_HAS_SSI2                       TRUE
@@ -325,18 +331,18 @@
 #endif
 
 /* I2C attributes.*/
-#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
-  || defined(TM4C1230H6PM) || defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ)  \
-  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PZ) || defined(TM4C1232C3PM) \
-  || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) || defined(TM4C1232H6PM)  \
-  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) || defined(TM4C1233H6PGE) \
-  || defined(TM4C1233H6PZ) || defined(TM4C1236D5PM) || defined(TM4C1236E6PM)  \
-  || defined(TM4C1236H6PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PZ)  \
-  || defined(TM4C1237H6PGE) || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) \
-  || defined(TM4C123AH6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \
-  || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \
-  || defined(TM4C123FH6PM) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) \
-  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM)   \
+  || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PZ)  \
+  || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PZ) || defined(PART_TM4C1232C3PM) \
+  || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM)  \
+  || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PGE) \
+  || defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM)  \
+  || defined(PART_TM4C1236H6PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PZ)  \
+  || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) \
+  || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \
+  || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123FE6PM) \
+  || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) \
+  || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR)
 #define TIVA_HAS_I2C0                       TRUE
 #define TIVA_HAS_I2C1                       TRUE
 #define TIVA_HAS_I2C2                       TRUE
@@ -348,11 +354,11 @@
 #define TIVA_HAS_I2C8                       FALSE
 #define TIVA_HAS_I2C9                       FALSE
 #endif
-#if defined(TM4C1231C3PM) || defined(TM4C1231D5PM) || defined(TM4C1231E6PM)   \
-  || defined(TM4C1231H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
-  || defined(TM4C1233E6PM) || defined(TM4C1233H6PM) || defined(TM4C1237D5PM)  \
-  || defined(TM4C1237E6PM) || defined(TM4C1237H6PM) || defined(TM4C123BE6PM)  \
-  || defined(TM4C123BH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM)
+#if defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231E6PM)   \
+  || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM)  \
+  || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1237D5PM)  \
+  || defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237H6PM) || defined(PART_TM4C123BE6PM)  \
+  || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GH6PM)
 #define TIVA_HAS_I2C0                       TRUE
 #define TIVA_HAS_I2C1                       TRUE
 #define TIVA_HAS_I2C2                       TRUE
@@ -366,129 +372,129 @@
 #endif
 
 /* CAN attributes.*/
-#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
-  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
-  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
-  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
-  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
-  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
-  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
-  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
-  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
-  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
-  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
-  || defined(TM4C1237H6PZ)
+#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM)   \
+  || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM)  \
+  || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ)  \
+  || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \
+  || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM)  \
+  || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM)  \
+  || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ)  \
+  || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \
+  || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM)  \
+  || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM)  \
+  || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \
+  || defined(PART_TM4C1237H6PZ)
 #define TIVA_HAS_CAN0                       TRUE
 #define TIVA_HAS_CAN1                       FALSE
 #endif
-#if defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM)   \
-  || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \
-  || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \
-  || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ)  \
-  || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) \
-  || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#if defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PM)   \
+  || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PM) \
+  || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123FE6PM) \
+  || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ)  \
+  || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) \
+  || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR)
 #define TIVA_HAS_CAN0                       TRUE
 #define TIVA_HAS_CAN1                       TRUE
 #endif
 
 /* USB attributes.*/
-#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
-  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
-  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
-  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
-  || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM)  \
-  || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \
-  || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB)
+#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM)   \
+  || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM)  \
+  || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ)  \
+  || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \
+  || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PM)  \
+  || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PM) \
+  || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB)
 #define TIVA_HAS_USB0                       FALSE
 #endif
-#if defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)   \
-  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
-  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
-  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
-  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
-  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
-  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
-  || defined(TM4C1237H6PZ) || defined(TM4C123FE6PM) || defined(TM4C123FH6PM)  \
-  || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) \
-  || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) \
-  || defined(TM4C123GH5ZXR)
+#if defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM)   \
+  || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM)  \
+  || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ)  \
+  || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \
+  || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM)  \
+  || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM)  \
+  || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \
+  || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM)  \
+  || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) \
+  || defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) \
+  || defined(PART_TM4C123GH5ZXR)
 #define TIVA_HAS_USB0                       TRUE
 #endif
 
 /* AC attributes.*/
-#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
-  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
-  || defined(TM4C1231E6PM) || defined(TM4C1231H6PM) || defined(TM4C1232C3PM)  \
-  || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) || defined(TM4C1232H6PM)  \
-  || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) || defined(TM4C1233E6PM)  \
-  || defined(TM4C1233H6PM) || defined(TM4C1236D5PM) || defined(TM4C1236E6PM)  \
-  || defined(TM4C1236H6PM) || defined(TM4C1237D5PM) || defined(TM4C1237E6PM)  \
-  || defined(TM4C1237H6PM) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM)  \
-  || defined(TM4C123BE6PM) || defined(TM4C123BH6PM) || defined(TM4C123FE6PM)  \
-  || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM)
+#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM)   \
+  || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM)  \
+  || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1232C3PM)  \
+  || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM)  \
+  || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) || defined(PART_TM4C1233E6PM)  \
+  || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM)  \
+  || defined(PART_TM4C1236H6PM) || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237E6PM)  \
+  || defined(PART_TM4C1237H6PM) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM)  \
+  || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123FE6PM)  \
+  || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GH6PM)
 #define TIVA_HAS_AC0                        TRUE
 #define TIVA_HAS_AC1                        TRUE
 #define TIVA_HAS_AC2                        FALSE
 #endif
-#if defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) || defined(TM4C1231H6PGE)  \
-  || defined(TM4C1231H6PZ) || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ)  \
-  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PZ) || defined(TM4C1237D5PZ) \
-  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PZ) \
-  || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PZ) \
-  || defined(TM4C123BH6ZRB) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE)\
-  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#if defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PZ) || defined(PART_TM4C1231H6PGE)  \
+  || defined(PART_TM4C1231H6PZ) || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PZ)  \
+  || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1237D5PZ) \
+  || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PZ) \
+  || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PZ) \
+  || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE)\
+  || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR)
 #define TIVA_HAS_AC0                        TRUE
 #define TIVA_HAS_AC1                        TRUE
 #define TIVA_HAS_AC2                        TRUE
 #endif
 
 /* PWM attributes.*/
-#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
-  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
-  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
-  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
-  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
-  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
-  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
-  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
-  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
-  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
-  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
-  || defined(TM4C1237H6PZ)
+#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM)   \
+  || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM)  \
+  || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ)  \
+  || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \
+  || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM)  \
+  || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM)  \
+  || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ)  \
+  || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \
+  || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM)  \
+  || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM)  \
+  || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \
+  || defined(PART_TM4C1237H6PZ)
 #define TIVA_HAS_PWM0                       FALSE
 #define TIVA_HAS_PWM1                       FALSE
 #endif
-#if defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM)   \
-  || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \
-  || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \
-  || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ)  \
-  || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) \
-  || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#if defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PM)   \
+  || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PM) \
+  || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123FE6PM) \
+  || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ)  \
+  || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) \
+  || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR)
 #define TIVA_HAS_PWM0                       TRUE
 #define TIVA_HAS_PWM1                       TRUE
 #endif
 
 /* QEI attributes.*/
-#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
-  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
-  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
-  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
-  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
-  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
-  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
-  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
-  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
-  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
-  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
-  || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM)
+#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM)   \
+  || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM)  \
+  || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ)  \
+  || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \
+  || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM)  \
+  || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM)  \
+  || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ)  \
+  || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \
+  || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM)  \
+  || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM)  \
+  || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \
+  || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM)
 #define TIVA_HAS_QEI0                       FALSE
 #define TIVA_HAS_QEI1                       FALSE
 #endif
-#if defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE)  \
-  || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \
-  || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM)  \
-  || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \
-  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#if defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE)  \
+  || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \
+  || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM)  \
+  || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \
+  || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR)
 #define TIVA_HAS_QEI0                       TRUE
 #define TIVA_HAS_QEI1                       TRUE
 #endif
diff --git a/os/hal/ports/TIVA/TM4C123x/tm4c123x.h b/os/hal/ports/TIVA/TM4C123x/tm4c123x.h
deleted file mode 100644
index d64afa8..0000000
--- a/os/hal/ports/TIVA/TM4C123x/tm4c123x.h
+++ /dev/null
@@ -1,958 +0,0 @@
-/*
-    Copyright (C) 2014..2016 Marco Veeneman
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @addtogroup CMSIS
- * @{
- */
-
-/**
- * @addtogroup TM4C123x
- * @{
- */
-
-#ifndef __TM4C123x_H
-#define __TM4C123x_H
-
-/** 
- * @addtogroup Configuration_section_for_CMSIS
- * @{
- */
-
-/**
- * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
- */
-#define __CM4_REV               0x0001  /**< Cortex-M4 Core Revision         */
-#define __MPU_PRESENT           1       /**< MPU present                     */
-#define __NVIC_PRIO_BITS        3       /**< Bits used for Priority Levels   */
-#define __Vendor_SysTickConfig  0       /**< Use different SysTick Config    */
-#define __FPU_PRESENT           1       /**< FPU present                     */
-
-/**
- * @brief   TM4C123x Interrupt Number Definitions
- */
-typedef enum IRQn
-{
-  /***** Cortex-M4 Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn   = -14,  /**< Cortex-M4 Non-Maskable Interrupt        */
-  HardFault_IRQn        = -13,  /**< Cortex-M4 Hard Fault Interrupt          */
-  MemoryManagement_IRQn = -12,  /**< Cortex-M4 Memory Management Interrupt   */
-  BusFault_IRQn         = -11,  /**< Cortex-M4 Bus Fault Interrupt           */
-  UsageFault_IRQn       = -10,  /**< Cortex-M4 Usage Fault Interrupt         */
-  SVCall_IRQn           = -5,   /**< Cortex-M4 SV Call Interrupt             */
-  DebugMonitor_IRQn     = -4,   /**< Cortex-M4 Debug Monitor Interrupt       */
-  PendSV_IRQn           = -3,   /**< Cortex-M4 Pend SV Interrupt             */
-  SysTick_IRQn          = -1,   /**< Cortex-M4 System Tick Interrupt         */
-  /***** TM4C123x Specific Interrupt Numbers *********************************/
-  GPIOA_IRQn            = 0,    /**< GPIO Port A                             */
-  GPIOB_IRQn            = 1,    /**< GPIO Port B                             */
-  GPIOC_IRQn            = 2,    /**< GPIO Port C                             */
-  GPIOD_IRQn            = 3,    /**< GPIO Port D                             */
-  GPIOE_IRQn            = 4,    /**< GPIO Port E                             */
-  UART0_IRQn            = 5,    /**< UART0                                   */
-  UART1_IRQn            = 6,    /**< UART1                                   */
-  SSI0_IRQn             = 7,    /**< SSI0                                    */
-  I2C0_IRQn             = 8,    /**< I2C0                                    */
-  PWM0FAULT_IRQn        = 9,    /**< PWM0 Fault                              */
-  PWM0GEN0_IRQn         = 10,   /**< PWM0 Generator 0                        */
-  PWM0GEN1_IRQn         = 11,   /**< PWM0 Generator 1                        */
-  PWM0GEN2_IRQn         = 12,   /**< PWM0 Generator 2                        */
-  QEI0_IRQn             = 13,   /**< QEI0                                    */
-  ADC0SEQ0_IRQn         = 14,   /**< ADC0 Sequence 0                         */
-  ADC0SEQ1_IRQn         = 15,   /**< ADC0 Sequence 1                         */
-  ADC0SEQ2_IRQn         = 16,   /**< ADC0 Sequence 2                         */
-  ADC0SEQ3_IRQn         = 17,   /**< ADC0 Sequence 3                         */
-  WATCHDOG_IRQn         = 18,   /**< Watchdog Timers 0 and 1                 */
-  TIMER0A_IRQn          = 19,   /**< 16/32-Bit Timer 0A                      */
-  TIMER0B_IRQn          = 20,   /**< 16/32-Bit Timer 0B                      */
-  TIMER1A_IRQn          = 21,   /**< 16/32-Bit Timer 1A                      */
-  TIMER1B_IRQn          = 22,   /**< 16/32-Bit Timer 1B                      */
-  TIMER2A_IRQn          = 23,   /**< 16/32-Bit Timer 2A                      */
-  TIMER2B_IRQn          = 24,   /**< 16/32-Bit Timer 2B                      */
-  ACOMP0_IRQn           = 25,   /**< Analog Comparator 0                     */
-  ACOMP1_IRQn           = 26,   /**< Analog Comparator 1                     */
-  SYSCON_IRQn           = 28,   /**< System Control                          */
-  FMCEECON_IRQn         = 29,   /**< Flash Memory Control and EEPROM Control */
-  GPIOF_IRQn            = 30,   /**< GPIO Port F                             */
-  UART2_IRQn            = 33,   /**< UART2                                   */
-  SSI1_IRQn             = 34,   /**< SSI1                                    */
-  TIMER3A_IRQn          = 35,   /**< 16/32-Bit Timer 3A                      */
-  TIMER3B_IRQn          = 36,   /**< 16/32-Bit Timer 3B                      */
-  I2C1_IRQn             = 37,   /**< I2C1                                    */
-  QEI1_IRQn             = 38,   /**< QEI1                                    */
-  CAN0_IRQn             = 39,   /**< CAN0                                    */
-  CAN1_IRQn             = 40,   /**< CAN1                                    */
-  HIBMODULE_IRQn        = 43,   /**< Hibernation Module                      */
-  USB_IRQn              = 44,   /**< USB                                     */
-  PWM0GEN3_IRQn         = 45,   /**< PWM0 Generator 3                        */
-  UDMASFW_IRQn          = 46,   /**< UDMA Software                           */
-  UDMAERR_IRQn          = 47,   /**< UDMA Error                              */
-  ADC1SEQ0_IRQn         = 48,   /**< ADC1 Sequence 0                         */
-  ADC1SEQ1_IRQn         = 49,   /**< ADC1 Sequence 1                         */
-  ADC1SEQ2_IRQn         = 50,   /**< ADC1 Sequence 2                         */
-  ADC1SEQ3_IRQn         = 51,   /**< ADC1 Sequence 3                         */
-  SSI2_IRQn             = 57,   /**< SSI2                                    */
-  SSI3_IRQn             = 58,   /**< SSI3                                    */
-  UART3_IRQn            = 59,   /**< UART3                                   */
-  UART4_IRQn            = 60,   /**< UART4                                   */
-  UART5_IRQn            = 61,   /**< UART5                                   */
-  UART6_IRQn            = 62,   /**< UART6                                   */
-  UART7_IRQn            = 63,   /**< UART7                                   */
-  I2C2_IRQn             = 68,   /**< I2C2                                    */
-  I2C3_IRQn             = 69,   /**< I2C3                                    */
-  TIMER4A_IRQn          = 70,   /**< 16/32-Bit Timer 4A                      */
-  TIMER4B_IRQn          = 71,   /**< 16/32-Bit Timer 4B                      */
-  TIMER5A_IRQn          = 92,   /**< 16/32-Bit Timer 5A                      */
-  TIMER5B_IRQn          = 93,   /**< 16/32-Bit Timer 5B                      */
-  WTIMER0A_IRQn         = 94,   /**< 32/64-Bit Timer 0A                      */
-  WTIMER0B_IRQn         = 95,   /**< 32/64-Bit Timer 0B                      */
-  WTIMER1A_IRQn         = 96,   /**< 32/64-Bit Timer 1A                      */
-  WTIMER1B_IRQn         = 97,   /**< 32/64-Bit Timer 1B                      */
-  WTIMER2A_IRQn         = 98,   /**< 32/64-Bit Timer 2A                      */
-  WTIMER2B_IRQn         = 99,   /**< 32/64-Bit Timer 2B                      */
-  WTIMER3A_IRQn         = 100,  /**< 32/64-Bit Timer 3A                      */
-  WTIMER3B_IRQn         = 101,  /**< 32/64-Bit Timer 3B                      */
-  WTIMER4A_IRQn         = 102,  /**< 32/64-Bit Timer 4A                      */
-  WTIMER4B_IRQn         = 103,  /**< 32/64-Bit Timer 4B                      */
-  WTIMER5A_IRQn         = 104,  /**< 32/64-Bit Timer 5A                      */
-  WTIMER5B_IRQn         = 105,  /**< 32/64-Bit Timer 5B                      */
-  SYSEXCEPT_IRQn        = 106,  /**< System Exception (imprecise)            */
-  PWM1GEN0_IRQn         = 134,  /**< PWM1 Generator 0                        */
-  PWM1GEN1_IRQn         = 135,  /**< PWM1 Generator 1                        */
-  PWM1GEN2_IRQn         = 136,  /**< PWM1 Generator 2                        */
-  PWM1GEN3_IRQn         = 137,  /**< PWM1 Generator 3                        */
-  PWM1FAULT_IRQn        = 138   /**< PWM1 Fault                              */
-} IRQn_Type;
- 
-/**
- * @}
- */
-
-#include "core_cm4.h"   /* Cortex-M4 processor and core peripherals.*/
-#include <stdint.h>
-
-/**
- * @addtogroup Peripheral_registers_structures
- * @{
- */
-
-/**
- * @brief Analog Comparator
- */
-typedef struct
-{
-  __IO uint32_t MIS;            /**< Masked Interrupt Status                 */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __IO uint32_t INTEN;          /**< Interrupt Enable                        */
-  __I  uint32_t _RESERVED0[1];  /**< Reserved                                */
-  __IO uint32_t REFCTL;         /**< Reference Voltage Control               */
-  __I  uint32_t _RESERVED1[3];  /**< Reserved                                */
-  __I  uint32_t STAT0;          /**< Status 0                                */
-  __IO uint32_t CTL0;           /**< Control 0                               */
-  __I  uint32_t _RESERVED2[6];  /**< Reserved                                */
-  __I  uint32_t STAT1;          /**< Status 1                                */
-  __IO uint32_t CTL1;           /**< Control 1                               */
-  __I  uint32_t _RESERVED3[990];/**< Reserved                                */
-  __I  uint32_t PP;             /**< Peripheral Properties                   */
-} ACMP_TypeDef;
-
-/**
- * @brief Analog-to-Digital Converter
- */
-typedef struct
-{
-  __IO uint32_t MUX;            /**< Sample Sequence Input Multiplexer
-                                     Select                                  */
-  __IO uint32_t CTL;            /**< Sample Sequence Control                 */
-  __I  uint32_t FIFO;           /**< Sample Sequence Result FIFO             */
-  __I  uint32_t FSTAT;          /**< Sample Sequence FIFO Status             */
-  __IO uint32_t OP;             /**< Sample Sequence Operation               */
-  __IO uint32_t DC;             /**< Sample Sequence Digital Comparator
-                                     Select                                  */
-  __I  uint32_t _RESERVED0[2];  /**< Reserved                                */
-} ADC_SS_t;
-
-typedef struct
-{
-  __IO uint32_t ACTSS;          /**< Active Sample Sequencer                 */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __IO uint32_t IM;             /**< Interrupt Mask                          */
-  __IO uint32_t ISC;            /**< Interrupt Status and Clear              */
-  __IO uint32_t OSTAT;          /**< Overflow Status                         */
-  __IO uint32_t EMUX;           /**< Event Multiplexer Select                */
-  __IO uint32_t USTAT;          /**< Underflow Status                        */
-  __IO uint32_t TSSEL;          /**< Trigger Source Select                   */
-  __IO uint32_t SSPRI;          /**< Sample Sequencer Priority               */
-  __IO uint32_t SPC;            /**< Sample Phase Control                    */
-  __IO uint32_t PSSI;           /**< Processor Sample Sequence Initiate      */
-  __I  uint32_t _RESERVED0[1];  /**< Reserved                                */
-  __IO uint32_t SAC;            /**< Sample Averaging Control                */
-  __IO uint32_t DCISC;          /**< Digital Comparator Interrupt Status and
-                                     Clear                                   */
-  __IO uint32_t CTL;            /**< Control                                 */
-  __I  uint32_t _RESERVED1[1];  /**< Reserved                                */
-  ADC_SS_t SS[4];               /**< Sample Sequence 0, 1, 2 and 3           */
-  __I  uint32_t _RESERVED2[784];/**< Reserved */
-  __O  uint32_t DCRIC;          /**< Digital Comparator Reset Initial
-                                     Conditions                              */
-  __I  uint32_t _RESERVED3[63]; /**< Reserved                                */
-  __IO uint32_t DCCTL[8];       /**< Digital Comparator Control 0 - 7        */
-  __I  uint32_t _RESERVED4[8];  /**< Reserved                                */
-  __IO uint32_t DCCMP[8];       /**< Digital Comparator Range 0 - 7          */
-  __I  uint32_t _RESERVED5[88]; /**< Reserved                                */
-  __I  uint32_t PP;             /**< Peripheral Properties                   */
-  __IO uint32_t PC;             /**< Peripheral Configuration                */
-  __IO uint32_t CC;             /**< Clock Configuration                     */
-} ADC_TypeDef;
-
-/**
- * @brief Controller Area Network
- */
-typedef struct
-{
-  __IO uint32_t CRQ;            /**< Command Request                         */
-  __IO uint32_t CMSK;           /**< Command Mask                            */
-  __IO uint32_t MSK[2];         /**< Mask 1 and 2                            */
-  __IO uint32_t ARB[2];         /**< Arbitration 1 and 2                     */
-  __IO uint32_t MCTL;           /**< Message Control                         */
-  __IO uint32_t DA[2];          /**< Data A1 and A2                          */
-  __IO uint32_t DB[2];          /**< Data B1 and B2                          */
-  __I  uint32_t _RESERVED0[13]; /**< Reserved                                */
-} CAN_INTERFACE_t;
-
-typedef struct
-{
-  __IO uint32_t CTL;            /**< Control                                 */
-  __IO uint32_t STS;            /**< Status                                  */
-  __I  uint32_t ERR;            /**< Error Counter                           */
-  __IO uint32_t BIT;            /**< Bit Timing                              */
-  __I  uint32_t INT;            /**< Interrupt                               */
-  __IO uint32_t TST;            /**< Test                                    */
-  __IO uint32_t BRPE;           /**< Baud Rate Prescaler Extension           */
-  __I  uint32_t _RESERVED0[1];  /**< Reserved                                */
-  CAN_INTERFACE_t IF[2];        /**< IF1 and IF2                             */
-  __I  uint32_t _RESERVED1[8];  /**< Reserved                                */
-  __I  uint32_t TXRQ[2];        /**< Transmission Request 1 and 2            */
-  __I  uint32_t _RESERVED2[6];  /**< Reserved                                */
-  __I  uint32_t NWDA[2];        /**< New Data 1 and 2                        */
-  __I  uint32_t _RESERVED3[6];  /**< Reserved                                */
-  __I  uint32_t MSGINT[2];      /**< Message 1 and 2 Interrupt Pending       */
-  __I  uint32_t _RESERVED4[6];  /**< Reserved                                */
-  __I  uint32_t MSGVAL[2];      /**< Message 1 and 2 Valid                   */
-} CAN_TypeDef;
-
-/**
- * @brief EEPROM Memory
- */
-typedef struct
-{
-  __IO uint32_t EESIZE;         /**< Size Information                        */
-  __IO uint32_t EEBLOCK;        /**< Current Block                           */
-  __IO uint32_t EEOFFSET;       /**< Current Offset                          */
-  __I  uint32_t _RESERVED0[1];  /**< Reserved                                */
-  __IO uint32_t EERDWR;         /**< Read-Write                              */
-  __IO uint32_t EERDWRINC;      /**< Read-Write with Increment               */
-  __IO uint32_t EEDONE;         /**< Done Status                             */
-  __IO uint32_t EESUPP;         /**< Support Control and Status              */
-  __IO uint32_t EEUNLOCK;       /**< Unlock                                  */
-  __I  uint32_t _RESERVED1[3];  /**< Reserved                                */
-  __IO uint32_t EEPROT;         /**< Protection                              */
-  __IO uint32_t EEPASS[3];      /**< Password                                */
-  __IO uint32_t EEINT;          /**< Interrupt                               */
-  __I  uint32_t _RESERVED2[3];  /**< Reserved                                */
-  __IO uint32_t EEHIDE;         /**< Block Hide                              */
-  __I  uint32_t _RESERVED3[11]; /**< Reserved                                */
-  __IO uint32_t EEDBGME;        /**< Debug Mass Erase                        */
-  __I  uint32_t _RESERVED4[975];/**< Reserved                                */
-  __IO uint32_t EEPROMPP;       /**< Peripheral Properties                   */
-} EEPROM_TypeDef;
-
-/**
- * @brief Flash Memory
- */
-typedef struct
-{
-  __IO uint32_t FMA;            /**< Flash Memory Address                    */
-  __IO uint32_t FMD;            /**< Flash Memory Data                       */
-  __IO uint32_t FMC;            /**< Flash Memory Control                    */
-  __I  uint32_t FCRIS;          /**< Flash Controller Raw Interrupt Status   */
-  __IO uint32_t FCIM;           /**< Flash Controller Interrupt Mask         */
-  __IO uint32_t FCMISC;         /**< Masked Interrupt Status and Clear       */
-  __I  uint32_t _RESERVED0[2];  /**< Reserved                                */
-  __IO uint32_t FMC2;           /**< Flash Memory Control 2                  */
-  __I  uint32_t _RESERVED1[3];  /**< Reserved                                */
-  __IO uint32_t FWBVAL;         /**< Flash Write Buffer Valid                */
-  __I  uint32_t _RESERVED2[51]; /**< Reserved                                */
-  __IO uint32_t FWBN;           /**< Flash Write Buffer n                    */
-  __I  uint32_t _RESERVED3[943];/**< Reserved                                */
-  __I  uint32_t FSIZE;          /**< Flash Size                              */
-  __I  uint32_t SSIZE;          /**< SRAM Size                               */
-  __I  uint32_t _RESERVED4[1];  /**< Reserved                                */
-  __IO uint32_t ROMSWMAP;       /**< ROM Software Map                        */
-} FLASH_TypeDef;
-
-/**
- * @brief General Purpose Input/Outputs
- */
-typedef struct
-{
-  union {
-    __IO uint32_t MASKED_ACCESS[256];   /**< Masked access of Data Register  */
-    struct {
-      __I  uint32_t _RESERVED0[255];    /**< Reserved                        */
-      __IO uint32_t DATA;       /**< Data                                    */
-    };
-  };
-  __IO uint32_t DIR;            /**< Direction                               */
-  __IO uint32_t IS;             /**< Interrupt Sense                         */
-  __IO uint32_t IBE;            /**< Interrupt Both Edges                    */
-  __IO uint32_t IEV;            /**< Interrupt Event                         */
-  __IO uint32_t IM;             /**< Interrupt Mask                          */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
-  __O  uint32_t ICR;            /**< Interrupt Clear                         */
-  __IO uint32_t AFSEL;          /**< Alternate Function Select               */
-  __I  uint32_t _RESERVED1[55]; /**< Reserved                                */
-  __IO uint32_t DR2R;           /**< 2-mA Drive Select                       */
-  __IO uint32_t DR4R;           /**< 4-mA Drive Select                       */
-  __IO uint32_t DR8R;           /**< 8-mA Drive Select                       */
-  __IO uint32_t ODR;            /**< Open Drain Select                       */
-  __IO uint32_t PUR;            /**< Pull-Up Select                          */
-  __IO uint32_t PDR;            /**< Pull-Down Select                        */
-  __IO uint32_t SLR;            /**< Slew Rate Control Select                */
-  __IO uint32_t DEN;            /**< Digital Enable                          */
-  __IO uint32_t LOCK;           /**< Lock                                    */
-  __IO uint32_t CR;             /**< Commit                                  */
-  __IO uint32_t AMSEL;          /**< Analog Mode Select                      */
-  __IO uint32_t PCTL;           /**< Port Control                            */
-  __IO uint32_t ADCCTL;         /**< ADC Control                             */
-  __IO uint32_t DMACTL;         /**< DMA Control                             */
-} GPIO_TypeDef;
-
-/**
- * @brief General Purpose Timer
- */
-typedef struct
-{
-  __IO uint32_t CFG;            /**< Configuration                           */
-  __IO uint32_t TAMR;           /**< Timer A Mode                            */
-  __IO uint32_t TBMR;           /**< Timer B Mode                            */
-  __IO uint32_t CTL;            /**< Control                                 */
-  __IO uint32_t SYNC;           /**< Synchronize                             */
-  __I  uint32_t _RESERVED0[1];  /**< Reserved                                */
-  __IO uint32_t IMR;            /**< Interrupt Mask                          */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
-  __O  uint32_t ICR;            /**< Interrupt Clear                         */
-  __IO uint32_t TAILR;          /**< Timer A Interval Load                   */
-  __IO uint32_t TBILR;          /**< Timer B Interval Load                   */
-  __IO uint32_t TAMATCHR;       /**< Timer A Match                           */
-  __IO uint32_t TBMATCHR;       /**< Timer B Match                           */
-  __IO uint32_t TAPR;           /**< Timer A Prescale                        */
-  __IO uint32_t TBPR;           /**< Timer B Prescale                        */
-  __IO uint32_t TAPMR;          /**< Timer A Prescale Match                  */
-  __IO uint32_t TBPMR;          /**< Timer B Prescale Match                  */
-  __I  uint32_t TAR;            /**< Timer A                                 */
-  __I  uint32_t TBR;            /**< Timer B                                 */
-  __IO uint32_t TAV;            /**< Timer A Value                           */
-  __IO uint32_t TBV;            /**< Timer B Value                           */
-  __I  uint32_t RTCPD;          /**< RTC Predivide                           */
-  __I  uint32_t TAPS;           /**< Timer A Prescale Snapshot               */
-  __I  uint32_t TBPS;           /**< Timer B Prescale Snapshot               */
-  __I  uint32_t TAPV;           /**< Timer A Prescale Value                  */
-  __I  uint32_t TBPV;           /**< Timer B Prescale Value                  */
-  __I  uint32_t _RESERVED1[981];/**< Reserved                                */
-  __I  uint32_t PP;             /**< Peripheral Properties                   */
-} GPT_TypeDef;
-
-/**
- * @brief Hibernation Module
- */
-typedef struct
-{
-  __I  uint32_t RTCC;           /**< RTC Counter                             */
-  __IO uint32_t RTCM0;          /**< RTC Match 0                             */
-  __I  uint32_t _RESERVED0[1];  /**< Reserved                                */
-  __IO uint32_t RTCLD;          /**< RTC Load                                */
-  __IO uint32_t CTL;            /**< Control                                 */
-  __IO uint32_t IM;             /**< Interrupt Mask                          */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
-  __IO uint32_t IC;             /**< Interrupt Clear                         */
-  __IO uint32_t RTCT;           /**< RTC Trim                                */
-  __IO uint32_t RTCSS;          /**< RTC Sub Seconds                         */
-  __I  uint32_t _RESERVED1[1];  /**< Reserved                                */
-  __IO uint32_t DATA;           /**< Data                                    */
-} HIB_TypeDef;
-
-/**
- * @brief Inter-Integrated Circuit
- */
-typedef struct
-{
-  __IO uint32_t MSA;            /**< Master Slave Address                    */
-  __IO uint32_t MCS;            /**< Master Control/Status                   */
-  __IO uint32_t MDR;            /**< Master Data                             */
-  __IO uint32_t MTPR;           /**< Master Timer Period                     */
-  __IO uint32_t MIMR;           /**< Master Interrupt Mask                   */
-  __I  uint32_t MRIS;           /**< Master Raw Interrupt Status             */
-  __IO uint32_t MMIS;           /**< Master Masked Interrupt Status          */
-  __O  uint32_t MICR;           /**< Master Interrupt Clear                  */
-  __IO uint32_t MCR;            /**< Master Configuration                    */
-  __IO uint32_t MCLKOCNT;       /**< Master Clock Low Timeout Count          */
-  __I  uint32_t _RESERVED0[1];  /**< Reserved                                */
-  __I  uint32_t MBMON;          /**< Master Bus Monitor                      */
-  __IO uint32_t MCR2;           /**< Master Configuration 2                  */
-  __I  uint32_t _RESERVED1[497];/**< Reserved                                */
-  __IO uint32_t SOAR;           /**< Slave Own Address                       */
-  __IO uint32_t SCSR;           /**< Slave Control/Status                    */
-  __IO uint32_t SDR;            /**< Slave Data                              */
-  __IO uint32_t SIMR;           /**< Slave Interrupt Mask                    */
-  __I  uint32_t SRIS;           /**< Slave Raw Interrupt Status              */
-  __I  uint32_t SMIS;           /**< Slave Masked Interrupt Status           */
-  __O  uint32_t SICR;           /**< Slave Interrupt Clear                   */
-  __IO uint32_t SOAR2;          /**< Slave Own Address 2                     */
-  __IO uint32_t SACKCTL;        /**< Slave ACK Control                       */
-  __I  uint32_t _RESERVED2[487];/**< Reserved                                */
-  __I  uint32_t PP;             /**< Peripheral Properties                   */
-  __I  uint32_t PC;             /**< Peripheral Configuration                */
-} I2C_TypeDef;
-
-/*
- * @brief Pulse Width Modulator
- */
-typedef struct
-{
-  __IO uint32_t CTL;            /**< Control                                 */
-  __IO uint32_t INTEN;          /**< Interrupt and Trigger Enable            */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __IO uint32_t ISC;            /**< Interrupt Status and Clear              */
-  __IO uint32_t LOAD;           /**< Load                                    */
-  __I  uint32_t COUNT;          /**< Counter                                 */
-  __IO uint32_t CMP[2];         /**< Compare A, B                            */
-  __IO uint32_t GEN[2];         /**< Generator A, B Control                  */
-  __IO uint32_t DBCTL;          /**< Dead-Band Control                       */
-  __IO uint32_t DBRISE;         /**< Dead-Band Rising-Edge Delay             */
-  __IO uint32_t DBFALL;         /**< Dead-Band Falling-Edge Delay            */
-  __IO uint32_t FLTSRC[2];      /**< Fault Source 0, 1                       */
-  __IO uint32_t MINFLTPER;      /**< Minimum Fault Period                    */
-} PWM_GENERATOR_T;
-
-typedef struct
-{
-  union {
-    __IO uint32_t SEN;          /**< Fault Pin Logic Sense, for GEN 0 and 1  */
-    __I  uint32_t _RESERVED0[1];/**< Reserved, for GEN 2 and 3               */
-  };
-  __IO uint32_t STAT[2];        /**< Fault Status                            */
-  __I  uint32_t _RESERVED1[29]; /**< Reserved                                */
-} PWM_FLT_t;
-
-typedef struct
-{
-  __IO uint32_t CTL;            /**< Master Control                          */
-  __IO uint32_t SYNC;           /**< Time Base Sync                          */
-  __IO uint32_t ENABLE;         /**< Output Enable                           */
-  __IO uint32_t INVERT;         /**< Output Inversion                        */
-  __IO uint32_t FAULT;          /**< Output Fault                            */
-  __IO uint32_t INTEN;          /**< Interrupt Enable                        */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __IO uint32_t ISC;            /**< Interrupt Status and Clear              */
-  __I  uint32_t STATUS;         /**< Status                                  */
-  __IO uint32_t FAULTVAL;       /**< Fault Condition Value                   */
-  __IO uint32_t ENUPD;          /**< Enable Update                           */
-  __I  uint32_t _RESERVED0[5];  /**< Reserved                                */
-  __IO PWM_GENERATOR_T PWM[4];  /**< PWM Generator 0, 1, 2 and 3             */
-  __I  uint32_t _RESERVED1[432];/**< Reserved                                */
-  PWM_FLT_t FLT[4];             /**< Fault registers 0, 1, 2 and 3           */
-  __I  uint32_t _RESERVED2[368];/**< Reserved                                */
-  __I  uint32_t PP;             /**< Peripheral Properties                   */
-} PWM_TypeDef;
-
-/**
- * @brief Quadrature Encoder Interface
- */
-typedef struct
-{
-  __IO uint32_t CTL;            /**< Control                                 */
-  __I  uint32_t STAT;           /**< Status                                  */
-  __IO uint32_t POS;            /**< Position                                */
-  __IO uint32_t MAXPOS;         /**< Maximum Position                        */
-  __IO uint32_t LOAD;           /**< Timer Load                              */
-  __I  uint32_t TIME;           /**< Timer                                   */
-  __I  uint32_t COUNT;          /**< Velocity Counter                        */
-  __I  uint32_t SPEED;          /**< Velocity                                */
-  __IO uint32_t INTEN;          /**< Interrupt Enable                        */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __IO uint32_t ISC;            /**< Interrupt Status and Clear              */
-} QEI_TypeDef;
-
-/**
- * @brief Synchronous Serial Interface
- */
-typedef struct
-{
-  __IO uint32_t CR0;            /**< Control 0                               */
-  __IO uint32_t CR1;            /**< Control 1                               */
-  __IO uint32_t DR;             /**< Data                                    */
-  __I  uint32_t SR;             /**< Status                                  */
-  __IO uint32_t CPSR;           /**< Clock Prescale                          */
-  __IO uint32_t IM;             /**< Interrupt Mask                          */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
-  __O  uint32_t ICR;            /**< Interrupt Clear                         */
-  __IO uint32_t DMACTL;         /**< DMA Control                             */
-  __I  uint32_t _RESERVED0[1000];/**< Reserved                               */
-  __IO uint32_t CC;             /**< Clock Configuration                     */
-} SSI_TypeDef;
-
-/** 
- * @brief System Control
- */
-typedef struct
-{
-  __I  uint32_t DID0;           /**< Device Identification 0                 */
-  __I  uint32_t DID1;           /**< Device Identification 1                 */
-  __I  uint32_t RESERVED0[10];  /**< Reserved                                */
-  __IO uint32_t PBORCTL;        /**< Brown-Out Reset Control                 */
-  __I  uint32_t RESERVED1[7];   /**< Reserved                                */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __IO uint32_t IMC;            /**< Interrupt Mask Control                  */
-  __IO uint32_t MISC;           /**< Interrupt Status and Clear              */
-  __IO uint32_t RESC;           /**< Reset Cause                             */
-  __IO uint32_t RCC;            /**< Run-Mode Clock Configuration            */
-  __I  uint32_t RESERVED2[2];   /**< Reserved                                */
-  __IO uint32_t GPIOHBCTL;      /**< GPIO High-Performance Bus Control       */
-  __IO uint32_t RCC2;           /**< Run-Mode Clock Configuration 2          */
-  __I  uint32_t RESERVED3[2];   /**< Reserved                                */
-  __IO uint32_t MOSCCTL;        /**< Main Oscillator Control                 */
-  __I  uint32_t RESERVED4[49];  /**< Reserved                                */
-  __IO uint32_t DSLPCLKCFG;     /**< Deep Sleep Clock Configuration          */
-  __I  uint32_t RESERVED5[1];   /**< Reserved                                */
-  __I  uint32_t SYSPROP;        /**< System Properties                       */
-  __IO uint32_t PIOSCCAL;       /**< PIOSC Calibration                       */
-  __I  uint32_t PIOSCSTAT;      /**< PIOSC Statistics                        */
-  __I  uint32_t RESERVED6[2];   /**< Reserved                                */
-  __I  uint32_t PLLFREQ0;       /**< PLL Frequency 0                         */
-  __I  uint32_t PLLFREQ1;       /**< PLL Frequency 1                         */
-  __I  uint32_t PLLSTAT;        /**< PLL Frequency Status                    */
-  __I  uint32_t RESERVED7[7];   /**< Reserved                                */
-  __IO uint32_t SLPPWRCFG;      /**< Sleep Power Configuration               */
-  __IO uint32_t DSLPPWRCFG;     /**< Deep-Sleep Power Configuration          */
-  __I  uint32_t RESERVED8[9];   /**< Reserved                                */
-  __IO uint32_t LDOSPCTL;       /**< LDO Sleep Power Control                 */
-  __I  uint32_t LDOSPCAL;       /**< LDO Sleep Power Calibration             */
-  __IO uint32_t LDODPCTL;       /**< LDO Deep-Sleep Power Control            */
-  __I  uint32_t LDODPCAL;       /**< LDO Deep-Sleep Power Calibration        */
-  __I  uint32_t RESERVED9[2];   /**< Reserved                                */
-  __I  uint32_t SDPMST;         /**< Sleep/Deep-Sleep Power Mode Status      */
-  __I  uint32_t RESERVED10[76]; /**< Reserved                                */
-  __I  uint32_t PPWD;           /**< WDT Peripheral Present                  */
-  __I  uint32_t PPTIMER;        /**< GPT Peripheral Present                  */
-  __I  uint32_t PPGPIO;         /**< GPIO Peripheral Present                 */
-  __I  uint32_t PPDMA;          /**< UDMA Peripheral Present                 */
-  __I  uint32_t RESERVED11[1];  /**< Reserved                                */
-  __I  uint32_t PPHIB;          /**< HIB Peripheral Present                  */
-  __I  uint32_t PPUART;         /**< UART Peripheral Present                 */
-  __I  uint32_t PPSSI;          /**< SSI Peripheral Present                  */
-  __I  uint32_t PPI2C;          /**< I2C Peripheral Present                  */
-  __I  uint32_t RESERVED12[1];  /**< Reserved                                */
-  __I  uint32_t PPUSB;          /**< USB Peripheral Present                  */
-  __I  uint32_t RESERVED13[2];  /**< Reserved                                */
-  __I  uint32_t PPCAN;          /**< CAN Peripheral Present                  */
-  __I  uint32_t PPADC;          /**< ADC Peripheral Present                  */
-  __I  uint32_t PPACMP;         /**< ACMP Peripheral Present                 */
-  __I  uint32_t PPPWM;          /**< PWM Peripheral Present                  */
-  __I  uint32_t PPQEI;          /**< QEI Peripheral Present                  */
-  __I  uint32_t RESERVED14[4];  /**< Reserved                                */
-  __I  uint32_t PPEEPROM;       /**< EEPROM Peripheral Present               */
-  __I  uint32_t PPWTIMER;       /**< Wide GPT Peripheral Present             */
-  __I  uint32_t RESERVED15[104];/**< Reserved                                */
-  __IO uint32_t SRWD;           /**< WDT Software Reset                      */
-  __IO uint32_t SRTIMER;        /**< GPT Software Reset                      */
-  __IO uint32_t SRGPIO;         /**< GPIO Software Reset                     */
-  __IO uint32_t SRDMA;          /**< UDMA Software Reset                     */
-  __I  uint32_t RESERVED16[1];  /**< Reserved                                */
-  __IO uint32_t SRHIB;          /**< HIB Software Reset                      */
-  __IO uint32_t SRUART;         /**< UART Software Reset                     */
-  __IO uint32_t SRSSI;          /**< SSI Software Reset                      */
-  __IO uint32_t SRI2C;          /**< I2C Software Reset                      */
-  __I  uint32_t RESERVED17[1];  /**< Reserved                                */
-  __IO uint32_t SRUSB;          /**< USB Software Reset                      */
-  __I  uint32_t RESERVED18[2];  /**< Reserved                                */
-  __IO uint32_t SRCAN;          /**< CAN Software Reset                      */
-  __IO uint32_t SRADC;          /**< ADC Software Reset                      */
-  __IO uint32_t SRACMP;         /**< ACMP Software Reset                     */
-  __IO uint32_t SRPWM;          /**< PWM Software Reset                      */
-  __IO uint32_t SRQEI;          /**< QEI Software Reset                      */
-  __I  uint32_t RESERVED19[4];  /**< Reserved                                */
-  __IO uint32_t SREEPROM;       /**< EEPROM Software Reset                   */
-  __IO uint32_t SRWTIMER;       /**< Wide GPT Software Reset                 */
-  __I  uint32_t RESERVED20[40]; /**< Reserved                                */
-  __IO uint32_t RCGCWD;         /**< WDT Run Mode Clock Gating Control       */
-  __IO uint32_t RCGCTIMER;      /**< GPT Run Mode Clock Gating Control       */
-  __IO uint32_t RCGCGPIO;       /**< GPIO Run Mode Clock Gating Control      */
-  __IO uint32_t RCGCDMA;        /**< UDMA Run Mode Clock Gating Control      */
-  __I  uint32_t RESERVED21[1];  /**< Reserved                                */
-  __IO uint32_t RCGCHIB;        /**< HIB Run Mode Clock Gating Control       */
-  __IO uint32_t RCGCUART;       /**< UART Run Mode Control                   */
-  __IO uint32_t RCGCSSI;        /**< SSI Run Mode Clock Gating Control       */
-  __IO uint32_t RCGCI2C;        /**< I2C Run Mode Clock Gating Control       */
-  __I  uint32_t RESERVED22[1];  /**< Reserved                                */
-  __IO uint32_t RCGCUSB;        /**< USB Run Mode Clock Gating Control       */
-  __I  uint32_t RESERVED23[2];  /**< Reserved                                */
-  __IO uint32_t RCGCCAN;        /**< CAN Run Mode Clock Gating Control       */
-  __IO uint32_t RCGCADC;        /**< ADC Run Mode Clock Gating Control       */
-  __IO uint32_t RCGCACMP;       /**< ACMP Run Mode Clock Gating Control      */
-  __IO uint32_t RCGCPWM;        /**< PWM Run Mode Clock Gating Control       */
-  __IO uint32_t RCGCQEI;        /**< QEI Run Mode Clock Gating Control       */
-  __I  uint32_t RESERVED24[4];  /**< Reserved                                */
-  __IO uint32_t RCGCEEPROM;     /**< EEPROM Run Mode Clock Gating Control    */
-  __IO uint32_t RCGCWTIMER;     /**< Wide GPT Run Mode Clock Gating Control  */
-  __I  uint32_t RESERVED25[40]; /**< Reserved                                */
-  __IO uint32_t SCGCWD;         /**< WDT Sleep Mode Clock Gating Control     */
-  __IO uint32_t SCGCTIMER;      /**< GPT Sleep Mode Clock Gating Control     */
-  __IO uint32_t SCGCGPIO;       /**< GPIO Sleep Mode Clock Gating Control    */
-  __IO uint32_t SCGCDMA;        /**< UDMA Sleep Mode Clock Gating Control    */
-  __I  uint32_t RESERVED26[1];  /**< Reserved                                */
-  __IO uint32_t SCGCHIB;        /**< HIB Sleep Mode Clock Gating Control     */
-  __IO uint32_t SCGCUART;       /**< UART Sleep Mode Clock Gating Control    */
-  __IO uint32_t SCGCSSI;        /**< SSI Sleep Mode Clock Gating Control     */
-  __IO uint32_t SCGCI2C;        /**< I2C Sleep Mode Clock Gating Control     */
-  __I  uint32_t RESERVED27[1];  /**< Reserved                                */
-  __IO uint32_t SCGCUSB;        /**< USB Sleep Mode Clock Gating Control     */
-  __I  uint32_t RESERVED28[2];  /**< Reserved                                */
-  __IO uint32_t SCGCCAN;        /**< CAN Sleep Mode Clock Gating Control     */
-  __IO uint32_t SCGCADC;        /**< ADC Sleep Mode Clock Gating Control     */
-  __IO uint32_t SCGCACMP;       /**< ACMP Sleep Mode Clock Gating Control    */
-  __IO uint32_t SCGCPWM;        /**< PWM Sleep Mode Clock Gating Control     */
-  __IO uint32_t SCGCQEI;        /**< QEI Sleep Mode Clock Gating Control     */
-  __I  uint32_t RESERVED29[4];  /**< Reserved                                */
-  __IO uint32_t SCGCEEPROM;     /**< EEPROM Sleep Mode Clock Gating Control  */
-  __IO uint32_t SCGCWTIMER;     /**< Wide GPT Sleep Mode Clock Gating Control*/
-  __I  uint32_t RESERVED30[40]; /**< Reserved                                */
-  __IO uint32_t DCGCWD;         /**< WDT Deep-Sleep Mode Clock Gating Control*/
-  __IO uint32_t DCGCTIMER;      /**< GPT Deep-Sleep Mode Clock Gating Control*/
-  __IO uint32_t DCGCGPIO;       /**< GPIO Deep-Sleep Mode Clock Gating
-                                     Control                                 */
-  __IO uint32_t DCGCDMA;        /**< UDMA Deep-Sleep Mode Clock Gating
-                                     Control                                 */
-  __I  uint32_t RESERVED31[1];  /**< Reserved                                */
-  __IO uint32_t DCGCHIB;        /**< HIB Deep-Sleep Mode Clock Gating Control*/
-  __IO uint32_t DCGCUART;       /**< UART Deep-Sleep Mode Clock Gating
-                                     Control                                 */
-  __IO uint32_t DCGCSSI;        /**< SSI Deep-Sleep Mode Clock Gating Control*/
-  __IO uint32_t DCGCI2C;        /**< I2C Deep-Sleep Mode Clock Gating Control*/
-  __I  uint32_t RESERVED32[1];  /**< Reserved                                */
-  __IO uint32_t DCGCUSB;        /**< USB Deep-Sleep Mode Clock Gating Control*/
-  __I  uint32_t RESERVED33[2];  /**< Reserved                                */
-  __IO uint32_t DCGCCAN;        /**< CAN Deep-Sleep Mode Clock Gating Control*/
-  __IO uint32_t DCGCADC;        /**< ADC Deep-Sleep Mode Clock Gating Control*/
-  __IO uint32_t DCGCACMP;       /**< ACMP Deep-Sleep Mode Clock Gating
-                                     Control                                 */
-  __IO uint32_t DCGCPWM;        /**< PWM Deep-Sleep Mode Clock Gating Control*/
-  __IO uint32_t DCGCQEI;        /**< QEI Deep-Sleep Mode Clock Gating Control*/
-  __I  uint32_t RESERVED34[4];  /**< Reserved                                */
-  __IO uint32_t DCGCEEPROM;     /**< EEPROM Deep-Sleep Mode Clock Gating
-                                     Control                                 */
-  __IO uint32_t DCGCWTIMER;     /**< Wide GPT Deep-Sleep Mode Clock Gating
-                                     Control                                 */
-  __I  uint32_t RESERVED35[104];/**< Reserved                                */
-  __IO uint32_t PRWD;           /**< WDT Peripheral Ready                    */
-  __IO uint32_t PRTIMER;        /**< GPT Peripheral Ready                    */
-  __IO uint32_t PRGPIO;         /**< GPIO Peripheral Ready                   */
-  __IO uint32_t PRDMA;          /**< UDMA Peripheral Ready                   */
-  __I  uint32_t RESERVED36[1];  /**< Reserved                                */
-  __IO uint32_t PRHIB;          /**< HIB Peripheral Ready                    */
-  __IO uint32_t PRUART;         /**< UART Peripheral Ready                   */
-  __IO uint32_t PRSSI;          /**< SSI Peripheral Ready                    */
-  __IO uint32_t PRI2C;          /**< I2C Peripheral Ready                    */
-  __I  uint32_t RESERVED37[1];  /**< Reserved                                */
-  __IO uint32_t PRUSB;          /**< USB Peripheral Ready                    */
-  __I  uint32_t RESERVED38[2];  /**< Reserved                                */
-  __IO uint32_t PRCAN;          /**< CAN Peripheral Ready                    */
-  __IO uint32_t PRADC;          /**< ADC Peripheral Ready                    */
-  __IO uint32_t PRACMP;         /**< ACMP Peripheral Ready                   */
-  __IO uint32_t PRPWM;          /**< PWM Peripheral Ready                    */
-  __IO uint32_t PRQEI;          /**< QEI Peripheral Ready                    */
-  __I  uint32_t RESERVED39[4];  /**< Reserved                                */
-  __IO uint32_t PREEPROM;       /**< EEPROM Peripheral Ready                 */
-  __IO uint32_t PRWTIMER;       /**< Wide GPT Peripheral Ready               */
-} SYSCTL_TypeDef;
-
-/**
- * @brief Universal Asynchronous Receiver/Transmitter
- */
-typedef struct
-{
-  __IO uint32_t DR;             /**< Data                                    */
-  union  {
-    __I  uint32_t RSR;          /**< Receive Status                          */
-    __O  uint32_t ECR;          /**< Error Clear                             */
-  };
-  __I  uint32_t _RESERVED0[4];  /**< Reserved                                */
-  __I  uint32_t FR;             /**< Flag                                    */
-  __I  uint32_t _RESERVED1[1];  /**< Reserved                                */
-  __IO uint32_t ILPR;           /**< IrDA Low-Power Register                 */
-  __IO uint32_t IBRD;           /**< Integer Baud-Rate Divisor               */
-  __IO uint32_t FBRD;           /**< Fractional Baud-Rate Divisor            */
-  __IO uint32_t LCRH;           /**< Line Control                            */
-  __IO uint32_t CTL;            /**< Control                                 */
-  __IO uint32_t IFLS;           /**< Interrupt FIFO Level Select             */
-  __IO uint32_t IM;             /**< Interrupt Mask                          */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
-  __O uint32_t ICR;             /**< Interrupt Clear                         */
-  __IO uint32_t DMACTL;         /**< DMA Control                             */
-  __I  uint32_t _RESERVED2[22]; /**< Reserved                                */
-  __IO uint32_t BIT9ADDR;       /**< 9-Bit Self Address                      */
-  __IO uint32_t BIT9AMASK;      /**< 9-Bit Self Address Mask                 */
-  __I  uint32_t _RESERVED3[965];/**< Reserved                                */
-  __I  uint32_t PP;             /**< Peripheral Properties                   */
-  __I  uint32_t _RESERVED4[1];  /**< Reserved                                */
-  __IO uint32_t CC;             /**< Clock Configuration                     */
-} UART_TypeDef;
-
-/**
- * @brief Micro Direct Memory Access
- */
-typedef struct
-{
-  __IO uint32_t SET;            /**< Set                                     */
-  __O  uint32_t CLR;            /**< Clear                                   */
-} UDMA_SC_t;
-
-typedef struct
-{
-  __IO uint32_t STAT;           /**< Status                                  */
-  __O  uint32_t CFG;            /**< Configuration                           */
-  __IO uint32_t CTLBASE;        /**< Channel Control Base Pointer            */
-  __IO uint32_t ALTBASE;        /**< Alternate Channel Control Base Pointer  */
-  __IO uint32_t WAITSTAT;       /**< Channel Wait-on-Request Status          */
-  __O  uint32_t SWREQ;          /**< Channel Software Request                */
-  __IO uint32_t USEBURSTSET;    /**< Channel Useburst Set                    */
-  __O  uint32_t USEBURSTCLR;    /**< Channel Useburst Clear                  */
-  __IO uint32_t REQMASKSET;     /**< Channel Request Mask Set                */
-  __O  uint32_t REQMASKCLR;     /**< Channel Request Mask Clear              */
-  __IO uint32_t ENASET;         /**< Channel Enable Set                      */
-  __O  uint32_t ENACLR;         /**< Channel Enable Clear                    */
-  __IO uint32_t ALTSET;         /**< Channel Primary Alternate Set           */
-  __O  uint32_t ALTCLR;         /**< Channel Primary Alternate Clear         */
-  __IO uint32_t PRIOSET;        /**< Channel Priority Set                    */
-  __O  uint32_t PRIOCLR;        /**< Channel Priority Clear                  */
-  __I  uint32_t _RESERVED0[3];  /**< Reserved                                */
-  __IO uint32_t ERRCLR;         /**< Bus Error Clear                         */
-  __I  uint32_t _RESERVED1[300];/**< Reserved                                */
-  __IO uint32_t CHASGN;         /**< Channel Assignment                      */
-  __IO uint32_t CHIS;           /**< Channel Interrupt Status                */
-  __I  uint32_t _RESERVED2[2];  /**< Reserved                                */
-  __IO uint32_t CHMAP[4];       /**< Channel Map Select 0, 1, 2 and 3        */
-} UDMA_TypeDef;
-
-// USB
-
-/**
- * @brief Watchdog Timer
- */
-typedef struct
-{
-  __IO uint32_t LOAD;           /**< Load                                    */
-  __I  uint32_t VALUE;          /**< Value                                   */
-  __IO uint32_t CTL;            /**< Control                                 */
-  __O  uint32_t ICR;            /**< Interrupt Clear                         */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
-  __I  uint32_t _RESERVED0[256];/**< Reserved                                */
-  __IO uint32_t TEST;           /**< Test                                    */
-  __I  uint32_t _RESERVED1[505];/**< Reserved                                */
-  __IO uint32_t LOCK;           /**< Lock                                    */
-} WDT_TypeDef;
-
-/**
- * @}
- */
-
-/**
- * @addtogroup Peripheral_memorymap
- * @{
- */
-
-#define SYSCTL_BASE     0x400FE000
-#define HIB_BASE        0x400FC000
-#define FLASH_BASE      0x400FD000
-#define EEPROM_BASE     0x400AF000
-#define UDMA_BASE       0x400FF000
-#define GPIOA_APB_BASE  0x40004000
-#define GPIOA_AHB_BASE  0x40058000
-#define GPIOB_APB_BASE  0x40005000
-#define GPIOB_AHB_BASE  0x40059000
-#define GPIOC_APB_BASE  0x40006000
-#define GPIOC_AHB_BASE  0x4005A000
-#define GPIOD_APB_BASE  0x40007000
-#define GPIOD_AHB_BASE  0x4005B000
-#define GPIOE_APB_BASE  0x40024000
-#define GPIOE_AHB_BASE  0x4005C000
-#define GPIOF_APB_BASE  0x40025000
-#define GPIOF_AHB_BASE  0x4005D000
-#define GPIOG_APB_BASE  0x40026000
-#define GPIOG_AHB_BASE  0x4005E000
-#define GPIOH_APB_BASE  0x40027000
-#define GPIOH_AHB_BASE  0x4005F000
-#define GPIOJ_APB_BASE  0x4003D000
-#define GPIOJ_AHB_BASE  0x40060000
-#define GPIOK_AHB_BASE  0x40061000
-#define GPIOL_AHB_BASE  0x40062000
-#define GPIOM_AHB_BASE  0x40063000
-#define GPION_AHB_BASE  0x40064000
-#define GPIOP_AHB_BASE  0x40065000
-#define GPIOQ_AHB_BASE  0x40066000
-#define GPT0_BASE       0x40030000
-#define GPT1_BASE       0x40031000
-#define GPT2_BASE       0x40032000
-#define GPT3_BASE       0x40033000
-#define GPT4_BASE       0x40034000
-#define GPT5_BASE       0x40035000
-#define WGPT0_BASE      0x40036000
-#define WGPT1_BASE      0x40037000
-#define WGPT2_BASE      0x4004C000
-#define WGPT3_BASE      0x4004D000
-#define WGPT4_BASE      0x4004E000
-#define WGPT5_BASE      0x4004F000
-#define WDT0_BASE       0x40000000
-#define WDT1_BASE       0x40001000
-#define ADC0_BASE       0x40038000
-#define ADC1_BASE       0x40039000
-#define UART0_BASE      0x4000C000
-#define UART1_BASE      0x4000D000
-#define UART2_BASE      0x4000E000
-#define UART3_BASE      0x4000F000
-#define UART4_BASE      0x40010000
-#define UART5_BASE      0x40011000
-#define UART6_BASE      0x40012000
-#define UART7_BASE      0x40013000
-#define SSI0_BASE       0x40008000
-#define SSI1_BASE       0x40009000
-#define SSI2_BASE       0x4000A000
-#define SSI3_BASE       0x4000B000
-#define I2C0_BASE       0x40020000
-#define I2C1_BASE       0x40021000
-#define I2C2_BASE       0x40022000
-#define I2C3_BASE       0x40023000
-#define I2C4_BASE       0x40023000
-#define I2C5_BASE       0x40023000
-#define CAN0_BASE       0x40040000
-#define CAN1_BASE       0x40041000
-// usb
-#define ACMP_BASE       0x4003C000
-#define PWM0_BASE       0x40028000
-#define PWM1_BASE       0x40029000
-#define QEI0_BASE       0x4002C000
-#define QEI1_BASE       0x4002D000
-
-/**
- * @}
- */
-
-/** 
- * @addtogroup Peripheral_declaration
- * @{
- */
-
-#define SYSCTL          ((SYSCTL_TypeDef *) SYSCTL_BASE)
-#define HIB             ((HIB_TypeDef *)    HIB_BASE)
-#define FLASH           ((FLASH_TypeDef *)  FLASH_BASE)
-#define EEPROM          ((EEPROM_TypeDef *) EEPROM_BASE)
-#define UDMA            ((UDMA_TypeDef *)   UDMA_BASE)
-#define GPIOA_APB       ((GPIO_TypeDef *)   GPIOA_APB_BASE)
-#define GPIOA_AHB       ((GPIO_TypeDef *)   GPIOA_AHB_BASE)
-#define GPIOB_APB       ((GPIO_TypeDef *)   GPIOB_APB_BASE)
-#define GPIOB_AHB       ((GPIO_TypeDef *)   GPIOB_AHB_BASE)
-#define GPIOC_APB       ((GPIO_TypeDef *)   GPIOC_APB_BASE)
-#define GPIOC_AHB       ((GPIO_TypeDef *)   GPIOC_AHB_BASE)
-#define GPIOD_APB       ((GPIO_TypeDef *)   GPIOD_APB_BASE)
-#define GPIOD_AHB       ((GPIO_TypeDef *)   GPIOD_AHB_BASE)
-#define GPIOE_APB       ((GPIO_TypeDef *)   GPIOE_APB_BASE)
-#define GPIOE_AHB       ((GPIO_TypeDef *)   GPIOE_AHB_BASE)
-#define GPIOF_APB       ((GPIO_TypeDef *)   GPIOF_APB_BASE)
-#define GPIOF_AHB       ((GPIO_TypeDef *)   GPIOF_AHB_BASE)
-#define GPIOG_APB       ((GPIO_TypeDef *)   GPIOG_APB_BASE)
-#define GPIOG_AHB       ((GPIO_TypeDef *)   GPIOG_AHB_BASE)
-#define GPIOH_APB       ((GPIO_TypeDef *)   GPIOH_APB_BASE)
-#define GPIOH_AHB       ((GPIO_TypeDef *)   GPIOH_AHB_BASE)
-#define GPIOJ_APB       ((GPIO_TypeDef *)   GPIOJ_APB_BASE)
-#define GPIOJ_AHB       ((GPIO_TypeDef *)   GPIOJ_AHB_BASE)
-#define GPIOK_AHB       ((GPIO_TypeDef *)   GPIOK_AHB_BASE)
-#define GPIOL_AHB       ((GPIO_TypeDef *)   GPIOL_AHB_BASE)
-#define GPIOM_AHB       ((GPIO_TypeDef *)   GPIOM_AHB_BASE)
-#define GPION_AHB       ((GPIO_TypeDef *)   GPION_AHB_BASE)
-#define GPIOP_AHB       ((GPIO_TypeDef *)   GPIOP_AHB_BASE)
-#define GPIOQ_AHB       ((GPIO_TypeDef *)   GPIOQ_AHB_BASE)
-#define GPT0            ((GPT_TypeDef *)    GPT0_BASE)
-#define GPT1            ((GPT_TypeDef *)    GPT1_BASE)
-#define GPT2            ((GPT_TypeDef *)    GPT2_BASE)
-#define GPT3            ((GPT_TypeDef *)    GPT3_BASE)
-#define GPT4            ((GPT_TypeDef *)    GPT4_BASE)
-#define GPT5            ((GPT_TypeDef *)    GPT5_BASE)
-#define WGPT0           ((GPT_TypeDef *)    WGPT0_BASE)
-#define WGPT1           ((GPT_TypeDef *)    WGPT1_BASE)
-#define WGPT2           ((GPT_TypeDef *)    WGPT2_BASE)
-#define WGPT3           ((GPT_TypeDef *)    WGPT3_BASE)
-#define WGPT4           ((GPT_TypeDef *)    WGPT4_BASE)
-#define WGPT5           ((GPT_TypeDef *)    WGPT5_BASE)
-#define WDT0            ((WDT_TypeDef *)    WDT0_BASE)
-#define WDT1            ((WDT_TypeDef *)    WDT1_BASE)
-#define ADC0            ((ADC_TypeDef*)     ADC0_BASE)
-#define ADC1            ((ADC_TypeDef*)     ADC1_BASE)
-#define UART0           ((UART_TypeDef *)   UART0_BASE)
-#define UART1           ((UART_TypeDef *)   UART1_BASE)
-#define UART2           ((UART_TypeDef *)   UART2_BASE)
-#define UART3           ((UART_TypeDef *)   UART3_BASE)
-#define UART4           ((UART_TypeDef *)   UART4_BASE)
-#define UART5           ((UART_TypeDef *)   UART5_BASE)
-#define UART6           ((UART_TypeDef *)   UART6_BASE)
-#define UART7           ((UART_TypeDef *)   UART7_BASE)
-#define SSI0            ((SSI_TypeDef *)    SSI0_BASE)
-#define SSI1            ((SSI_TypeDef *)    SSI1_BASE)
-#define SSI2            ((SSI_TypeDef *)    SSI2_BASE)
-#define SSI3            ((SSI_TypeDef *)    SSI3_BASE)
-#define I2C0            ((I2C_TypeDef *)    I2C0_BASE)
-#define I2C1            ((I2C_TypeDef *)    I2C1_BASE)
-#define I2C2            ((I2C_TypeDef *)    I2C2_BASE)
-#define I2C3            ((I2C_TypeDef *)    I2C3_BASE)
-#define I2C4            ((I2C_TypeDef *)    I2C4_BASE)
-#define I2C5            ((I2C_TypeDef *)    I2C5_BASE)
-#define CAN0            ((CAN_TypeDef *)    CAN0_BASE)
-#define CAN1            ((CAN_TypeDef *)    CAN1_BASE)
-// usb
-#define ACMP            ((ACMP_TypeDef *)   ACMP_BASE)
-#define PWM0            ((PWM_TypeDef *)    PWM0_BASE)
-#define PWM1            ((PWM_TypeDef *)    PWM1_BASE)
-#define QEI0            ((QEI_TypeDef *)    QEI0_BASE)
-#define QEI1            ((QEI_TypeDef *)    QEI1_BASE)
-
-/**
- * @}
- */
-
-#endif /* __TM4C123x_H */
-
-/**
- * @}
- */
- 
-/**
- * @}
- */
diff --git a/os/hal/ports/TIVA/TM4C129x/hal_lld.c b/os/hal/ports/TIVA/TM4C129x/hal_lld.c
index 60d6763..7af3cc4 100644
--- a/os/hal/ports/TIVA/TM4C129x/hal_lld.c
+++ b/os/hal/ports/TIVA/TM4C129x/hal_lld.c
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -76,8 +76,8 @@ void tiva_clock_init(void)
   /*
    * 2. Power up the MOSC by clearing the NOXTAL bit in the MOSCCTL register.
    */
-  moscctl = SYSCTL->MOSCCTL;
-  moscctl &= ~MOSCCTL_NOXTAL;
+  moscctl = HWREG(SYSCTL_MOSCCTL);
+  moscctl &= ~SYSCTL_MOSCCTL_NOXTAL;
 
   /*
    * 3. If single-ended MOSC mode is required, the MOSC is ready to use. If crystal mode is required,
@@ -85,18 +85,18 @@ void tiva_clock_init(void)
    * (RIS), indicating MOSC crystal mode is ready.
    */
 #if TIVA_MOSC_SINGLE_ENDED
-  SYSCTL->MOSCCTL = moscctl;
+  HWREG(SYSCTL_MOSCCTL) = moscctl;
 #else
-  moscctl &= ~MOSCCTL_PWRDN;
-  SYSCTL->MOSCCTL = moscctl;
+  moscctl &= ~SYSCTL_MOSCCTL_PWRDN;
+  HWREG(SYSCTL_MOSCCTL) = moscctl;
 
-  while (!(SYSCTL->RIS & SYSCTL_RIS_MOSCPUPRIS));
+  while (!(HWREG(SYSCTL_RIS) & SYSCTL_RIS_MOSCPUPRIS));
 #endif
 
   /*
    * 4. Set the OSCSRC field to 0x3 in the RSCLKCFG register at offset 0x0B0.
    */
-  rsclkcfg = SYSCTL->RSCLKCFG;
+  rsclkcfg = HWREG(SYSCTL_RSCLKCFG);
 
   rsclkcfg |= TIVA_RSCLKCFG_OSCSRC;
 
@@ -109,44 +109,42 @@ void tiva_clock_init(void)
    * 6. Write the PLLFREQ0 and PLLFREQ1 registers with the values of Q, N, MINT, and MFRAC to
    * the configure the desired VCO frequency setting.
    */
-  SYSCTL->PLLFREQ1 = (0x04 << 0); // 5 - 1
-  SYSCTL->PLLFREQ0 = (0x60 << 0) | PLLFREQ0_PLLPWR;
+  HWREG(SYSCTL_PLLFREQ1) = (0x04 << 0); // 5 - 1
+  HWREG(SYSCTL_PLLFREQ0) = (0x60 << 0) | SYSCTL_PLLFREQ0_PLLPWR;
 
   /*
    * 7. Write the MEMTIM0 register to correspond to the new system clock setting.
    */
-  SYSCTL->MEMTIM0 = (MEMTIM0_FBCHT_3_5 | MEMTIM0_FWS_5 | MEMTIM0_EBCHT_3_5 | MEMTIM0_EWS_5 | MEMTIM0_MB1);
+  HWREG(SYSCTL_MEMTIM0) = (SYSCTL_MEMTIM0_FBCHT_3_5 | (5 << SYSCTL_MEMTIM0_FWS_S) | SYSCTL_MEMTIM0_EBCHT_3_5 | (5 << SYSCTL_MEMTIM0_EWS_S) | SYSCTL_MEMTIM0_MB1);
 
   /*
    * Wait for the PLLSTAT register to indicate the PLL has reached lock at the new operating point
    * (or that a timeout period has passed and lock has failed, in which case an error condition exists
    * and this sequence is abandoned and error processing is initiated).
    */
-  while (!SYSCTL->PLLSTAT & PLLSTAT_LOCK);
+  while (!HWREG(SYSCTL_PLLSTAT) & SYSCTL_PLLSTAT_LOCK);
 
   /*
    * 9. Write the RSCLKCFG register's PSYSDIV value, set the USEPLL bit to enabled, and MEMTIMU
    * bit.
    */
 
-  rsclkcfg = SYSCTL->RSCLKCFG;
+  rsclkcfg = HWREG(SYSCTL_RSCLKCFG);
 
-  rsclkcfg |= (RSCLKCFG_USEPLL | (0x03 << 0) | (0x03 << 20) | (0x03 << 24));
+  rsclkcfg |= (SYSCTL_RSCLKCFG_USEPLL | (0x03 << 0) | (0x03 << 20) | (0x03 << 24));
 
   //rsclkcfg |= ((0x03 << 0) | (1 << 28) | (0x03 << 20));
 
-  rsclkcfg |= RSCLKCFG_MEMTIMU;
+  rsclkcfg |= SYSCTL_RSCLKCFG_MEMTIMU;
 
   // set new configuration
-  SYSCTL->RSCLKCFG = rsclkcfg;
+  HWREG(SYSCTL_RSCLKCFG) = rsclkcfg;
 
 #if HAL_USE_PWM
 #if TIVA_PWM_USE_PWM0
-  PWM0->CC = TIVA_PWM_FIELDS;
+  HWREG(PWM0_CC) = TIVA_PWM_FIELDS;
 #endif
 #endif
 }
 
-/**
- * @}
- */
+/** @} */
diff --git a/os/hal/ports/TIVA/TM4C129x/hal_lld.h b/os/hal/ports/TIVA/TM4C129x/hal_lld.h
index e5c667d..1080fae 100644
--- a/os/hal/ports/TIVA/TM4C129x/hal_lld.h
+++ b/os/hal/ports/TIVA/TM4C129x/hal_lld.h
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -38,170 +38,8 @@
  * @name    Platform identification
  * @{
  */
- 
 #define PLATFORM_NAME           "Tiva C Series TM4C129x"
-
-/**
- * @}
- */
-
-/**
- * @name    RIS register bits definitions
- * @{
- */
-
-#define SYSCTL_RIS_PLLLRIS	            (1 << 6)
-#define SYSCTL_RIS_MOSCPUPRIS           (1 << 8)
-
-/**
- * @}
- */
-
-/**
- * @name    MOSCCTL register bits definitions
- * @{
- */
-
-#define MOSCCTL_CVAL                (1 << 0)
-#define MOSCCTL_MOSCIM              (1 << 1)
-#define MOSCCTL_NOXTAL              (1 << 2)
-#define MOSCCTL_PWRDN               (1 << 3)
-#define MOSCCTL_OSCRNG              (1 << 4)
-
-/**
- * @}
- */
-
-/**
- * @name    RSCLKCFG register bits definitions
- * @{
- */
-
-#define RSCLKCFG_PSYSDIV_bm         (0xfffff << 0)
-#define RSCLKCFG_OSYSDIV_bm         (0xfffff << 10
-
-#define RSCLKCFG_OSCSRC_bm          (0xff << 20)
-#define RSCLKCFG_OSCSRC_PIOSC       (0 << 20)
-#define RSCLKCFG_OSCSRC_LFIOSC      (0x02 << 20)
-#define RSCLKCFG_OSCSRC_MOSC        (0x03 << 20)
-#define RSCLKCFG_OSCSRC_RTCOSC      (0x04 << 20)
-
-#define RSCLKCFG_PLLSRC_bm          (0xff << 24)
-#define RSCLKCFG_PLLSRC_PIOSC       (0 << 24)
-#define RSCLKCFG_PLLSRC_MOSC        (0x03 << 24)
-
-#define RSCLKCFG_USEPLL             (1 << 28)
-
-#define RSCLKCFG_ACG                (1 << 29)
-
-#define RSCLKCFG_NEWFREQ            (1 << 30)
-
-#define RSCLKCFG_MEMTIMU            (1 << 31)
-
-/**
- * @}
- */
-
-/**
- * @name    PLLFREQ0 register bits definitions
- * The PLL frequency can be calculated using the following equation:
- * fVCO = (fIN * MDIV)
- * where
- * fIN = fXTAL/(Q+1)(N+1) or fPIOSC/(Q+1)(N+1)
- * MDIV = MINT + (MFRAC / 1024)
- * The Q and N values are programmed in the PLLFREQ1 register. Note that to reduce jitter, MFRAC
- * should be programmed to 0x0.
- * @{
- */
-
-#define PLLFREQ0_MINT_bm            (0xfffff << 0)
-#define PLLFREQ0_MFRAC_bm           (0xfffff << 10)
-#define PLLFREQ0_PLLPWR             (1 << 23)
-
-/**
- * @}
- */
-
-/**
- * @name    PLLFREQ1 register bits definitions
- * @{
- */
-
-#define PLLFREQ1_N_bm               (0x7ff << 0)
-#define PLLFREQ1_Q_bm               (0x7ff << 8)
-
-/**
- * @}
- */
-
-/**
- * @name    MEMTIM0 register bits definitions
- * @{
- */
-
-#define MEMTIM0_FWS_bm              (0xff << 0)
-#define MEMTIM0_FWS_0               (0x00 << 0)
-#define MEMTIM0_FWS_1               (0x01 << 0)
-#define MEMTIM0_FWS_2               (0x02 << 0)
-#define MEMTIM0_FWS_3               (0x03 << 0)
-#define MEMTIM0_FWS_4               (0x04 << 0)
-#define MEMTIM0_FWS_5               (0x05 << 0)
-#define MEMTIM0_FWS_6               (0x06 << 0)
-#define MEMTIM0_FWS_7               (0x07 << 0)
-
-#define MEMTIM0_FBCE                (1 << 5)
-
-#define MEMTIM0_FBCHT_bm            (0xff << 6)
-#define MEMTIM0_FBCHT_0_5           (0x00 << 6)
-#define MEMTIM0_FBCHT_1             (0x01 << 6)
-#define MEMTIM0_FBCHT_1_5           (0x02 << 6)
-#define MEMTIM0_FBCHT_2             (0x03 << 6)
-#define MEMTIM0_FBCHT_2_5           (0x04 << 6)
-#define MEMTIM0_FBCHT_3             (0x05 << 6)
-#define MEMTIM0_FBCHT_3_5           (0x06 << 6)
-#define MEMTIM0_FBCHT_4             (0x07 << 6)
-#define MEMTIM0_FBCHT_4_5           (0x08 << 6)
-
-#define MEMTIM0_EWS_bm              (0xff << 16)
-#define MEMTIM0_EWS_0               (0x00 << 16)
-#define MEMTIM0_EWS_1               (0x01 << 16)
-#define MEMTIM0_EWS_2               (0x02 << 16)
-#define MEMTIM0_EWS_3               (0x03 << 16)
-#define MEMTIM0_EWS_4               (0x04 << 16)
-#define MEMTIM0_EWS_5               (0x05 << 16)
-#define MEMTIM0_EWS_6               (0x06 << 16)
-#define MEMTIM0_EWS_7               (0x07 << 16)
-
-#define MEMTIM0_EBCE                (1 << 21)
-
-#define MEMTIM0_EBCHT_bm            (0xff << 22)
-#define MEMTIM0_EBCHT_0_5           (0x00 << 22)
-#define MEMTIM0_EBCHT_1             (0x01 << 22)
-#define MEMTIM0_EBCHT_1_5           (0x02 << 22)
-#define MEMTIM0_EBCHT_2             (0x03 << 22)
-#define MEMTIM0_EBCHT_2_5           (0x04 << 22)
-#define MEMTIM0_EBCHT_3             (0x05 << 22)
-#define MEMTIM0_EBCHT_3_5           (0x06 << 22)
-#define MEMTIM0_EBCHT_4             (0x07 << 22)
-#define MEMTIM0_EBCHT_4_5           (0x08 << 22)
-
-// XXX: what is this?
-#define MEMTIM0_MB1          0x00100010  // MB1 = Must be one
-
-/**
- * @}
- */
-
-/**
- * @name    PLLSTAT register bits definitions
- * @{
- */
-
-#define PLLSTAT_LOCK                (1 << 0)
-
-/**
- * @}
- */
+/** @} */
 
 /*===========================================================================*/
 /* Driver pre-compile time settings.                                         */
@@ -212,7 +50,7 @@
 #endif
 
 #if !defined(TIVA_RSCLKCFG_OSCSRC)
-#define TIVA_RSCLKCFG_OSCSRC            RSCLKCFG_OSCSRC_MOSC
+#define TIVA_RSCLKCFG_OSCSRC            SYSCTL_RSCLKCFG_OSCSRC_MOSC
 #endif
 
 /*===========================================================================*/
@@ -229,55 +67,55 @@
 /*
  * Oscillator-related checks.
  */
-#if !(TIVA_RSCLKCFG_OSCSRC == RSCLKCFG_OSCSRC_PIOSC) &&                       \
-    !(TIVA_RSCLKCFG_OSCSRC == RSCLKCFG_OSCSRC_LFIOSC) &&                      \
-    !(TIVA_RSCLKCFG_OSCSRC == RSCLKCFG_OSCSRC_MOSC) &&                        \
-    !(TIVA_RSCLKCFG_OSCSRC == RSCLKCFG_OSCSRC_RTCOSC)
+#if !(TIVA_RSCLKCFG_OSCSRC == SYSCTL_RSCLKCFG_OSCSRC_PIOSC) &&                       \
+    !(TIVA_RSCLKCFG_OSCSRC == SYSCTL_RSCLKCFG_OSCSRC_LFIOSC) &&                      \
+    !(TIVA_RSCLKCFG_OSCSRC == SYSCTL_RSCLKCFG_OSCSRC_MOSC) &&                        \
+    !(TIVA_RSCLKCFG_OSCSRC == SYSCTL_RSCLKCFG_OSCSRC_RTC)
 #error "Invalid value for TIVA_RSCLKCFG_OSCSRC defined"
 #endif
 
 #if TIVA_XTAL_VALUE == 4000000
-#define TIVA_XTAL_              (0x06 << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_4MHZ
 #elif TIVA_XTAL_VALUE == 4096000
-#define TIVA_XTAL_              (0x07 << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_4_09MHZ
 #elif TIVA_XTAL_VALUE == 4915200
-#define TIVA_XTAL_              (0x08 << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_4_91MHZ
 #elif TIVA_XTAL_VALUE == 5000000
-#define TIVA_XTAL_              (0x09 << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_5MHZ
 #elif TIVA_XTAL_VALUE == 5120000
-#define TIVA_XTAL_              (0x0a << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_5_12MHZ
 #elif TIVA_XTAL_VALUE == 6000000
-#define TIVA_XTAL_              (0x0b << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_6MHZ
 #elif TIVA_XTAL_VALUE == 6144000
-#define TIVA_XTAL_              (0x0c << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_6_14MHZ
 #elif TIVA_XTAL_VALUE == 7372800
-#define TIVA_XTAL_              (0x0d << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_7_37MHZ
 #elif TIVA_XTAL_VALUE == 8000000
-#define TIVA_XTAL_              (0x0e << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_8MHZ
 #elif TIVA_XTAL_VALUE == 8192000
-#define TIVA_XTAL_              (0x0f << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_8_19MHZ
 #elif TIVA_XTAL_VALUE == 10000000
-#define TIVA_XTAL_              (0x10 << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_10MHZ
 #elif TIVA_XTAL_VALUE == 12000000
-#define TIVA_XTAL_              (0x11 << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_12MHZ
 #elif TIVA_XTAL_VALUE == 12288000
-#define TIVA_XTAL_              (0x12 << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_12_2MHZ
 #elif TIVA_XTAL_VALUE == 13560000
-#define TIVA_XTAL_              (0x13 << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_13_5MHZ
 #elif TIVA_XTAL_VALUE == 14318180
-#define TIVA_XTAL_              (0x14 << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_14_3MHZ
 #elif TIVA_XTAL_VALUE == 16000000
-#define TIVA_XTAL_              (0x15 << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_16MHZ
 #elif TIVA_XTAL_VALUE == 16384000
-#define TIVA_XTAL_              (0x16 << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_16_3MHZ
 #elif TIVA_XTAL_VALUE == 18000000
-#define TIVA_XTAL_              (0x17 << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_18MHZ
 #elif TIVA_XTAL_VALUE == 20000000
-#define TIVA_XTAL_              (0x18 << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_20MHZ
 #elif TIVA_XTAL_VALUE == 24000000
-#define TIVA_XTAL_              (0x19 << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_24MHZ
 #elif TIVA_XTAL_VALUE == 25000000
-#define TIVA_XTAL_              (0x1a << 6)
+#define TIVA_XTAL_              SYSCTL_RCC_XTAL_25MHZ
 #else
 #error "Invalid value for TIVA_XTAL_VALUE defined"
 #endif
diff --git a/os/hal/ports/TIVA/TM4C129x/platform.mk b/os/hal/ports/TIVA/TM4C129x/platform.mk
index b8363f3..9702796 100644
--- a/os/hal/ports/TIVA/TM4C129x/platform.mk
+++ b/os/hal/ports/TIVA/TM4C129x/platform.mk
@@ -1,14 +1,34 @@
-# List of all the TM4C129x platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
-              ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C129x/hal_lld.c \
-              ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_st_lld.c \
-              ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_pal_lld.c \
-              ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_serial_lld.c \
-              ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_mac_lld.c \
-              ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_ext_lld.c \
-              ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_wdg_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
-              ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C129x \
-              ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD
+# Required platform files.
+PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C129x/hal_lld.c
+
+# Required include directories.
+PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C129x
+
+ifeq ($(USE_SMART_BUILD),yes)
+
+# Configuration files directory
+ifeq ($(CONFDIR),)
+  CONFDIR = .
+endif
+
+HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h | egrep -e "\#define"))
+else
+endif
+
+# Drivers compatible with the platform.
+include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/ADC/driver.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPIO/driver.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPTM/driver.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/I2C/driver.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/MAC/driver.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/PWM/driver.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/SSI/driver.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/driver.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/uDMA/driver.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/WDT/driver.mk
+
+# Shared variables
+ALLCSRC += $(PLATFORMSRC)
+ALLINC  += $(PLATFORMINC)
diff --git a/os/hal/ports/TIVA/TM4C129x/tiva_isr.h b/os/hal/ports/TIVA/TM4C129x/tiva_isr.h
index 255bfd6..3db9ba3 100644
--- a/os/hal/ports/TIVA/TM4C129x/tiva_isr.h
+++ b/os/hal/ports/TIVA/TM4C129x/tiva_isr.h
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -35,9 +35,9 @@
  */
 
 /* GPIO units.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1292NCPDT) || defined(TM4C1294KCPDT)\
-  || defined(TM4C1294NCPDT) || defined(TM4C129CNCPDT) || defined(TM4C129DNCPDT)\
-  || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1292NCPDT) || defined(PART_TM4C1294KCPDT)\
+  || defined(PART_TM4C1294NCPDT) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129DNCPDT)\
+  || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT)
 #define TIVA_GPIOA_HANDLER                  Vector40
 #define TIVA_GPIOB_HANDLER                  Vector44
 #define TIVA_GPIOC_HANDLER                  Vector48
@@ -98,10 +98,10 @@
 #define TIVA_GPIOQ6_NUMBER                  90
 #define TIVA_GPIOQ7_NUMBER                  91
 #endif
-#if defined(TM4C1290NCZAD) || defined(TM4C1292NCZAD) || defined(TM4C1294NCZAD)\
-  || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD) || defined(TM4C1299NCZAD)\
-  || defined(TM4C129CNCZAD) || defined(TM4C129DNCZAD) || defined(TM4C129ENCZAD)\
-  || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294NCZAD)\
+  || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || defined(PART_TM4C1299NCZAD)\
+  || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129ENCZAD)\
+  || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_GPIOA_HANDLER                  Vector40
 #define TIVA_GPIOB_HANDLER                  Vector44
 #define TIVA_GPIOC_HANDLER                  Vector48
@@ -170,85 +170,85 @@
 #endif
 
 /* EPI units.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
-  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
-  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\
+  || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\
+  || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_EPI0_HANDLER                   Vector108
 
 #define TIVA_EPI0_NUMBER                    50
 #endif
 
 /* CRC units.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
-  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
-  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\
+  || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\
+  || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 /* CRC has no interrupts.*/
 #endif
 
 /* AES Accelerator units.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD)
 /* no interrupts.*/
 #endif
-#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) \
-  || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\
-  || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\
-  || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) \
+  || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT)\
+  || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD)\
+  || defined(PART_TM4C129XNCZAD)
 #define TIVA_AES_HANDLER                    Vector1BC
 
 #define TIVA_AES_NUMBER                     95
 #endif
 
 /* DES Accelerator units.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD)
 /* no interrupts.*/
 #endif
-#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT)\
-  || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\
-  || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\
-  || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT)\
+  || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT)\
+  || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD)\
+  || defined(PART_TM4C129XNCZAD)
 #define TIVA_DES_HANDLER                    Vector1C0
 
 #define TIVA_DES_NUMBER                     51
 #endif
 
 /* SHA/MD5 Accelerator units.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD)
 /* no interrupts.*/
 #endif
-#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT)\
-  || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\
-  || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\
-  || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT)\
+  || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT)\
+  || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD)\
+  || defined(PART_TM4C129XNCZAD)
 #define TIVA_SHA_MD5_HANDLER                Vector1B8
 
 #define TIVA_SHA_MD5_NUMBER                 94
 #endif
 
 /* GPT units.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
-  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
-  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\
+  || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\
+  || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_GPT0A_HANDLER                   Vector8C
 #define TIVA_GPT0B_HANDLER                   Vector90
 #define TIVA_GPT1A_HANDLER                   Vector94
@@ -285,26 +285,26 @@
 #endif
 
 /* WDT units.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
-  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
-  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\
+  || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\
+  || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_WDT_HANDLER                    Vector88
 
 #define TIVA_WDT_NUMBER                     18
 #endif
 
 /* ADC units.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
-  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
-  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\
+  || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\
+  || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_ADC0_SEQ0_HANDLER              Vector78
 #define TIVA_ADC0_SEQ1_HANDLER              Vector7C
 #define TIVA_ADC0_SEQ2_HANDLER              Vector80
@@ -325,13 +325,13 @@
 #endif
 
 /* UART units.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
-  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
-  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\
+  || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\
+  || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_UART0_HANDLER                  Vector54
 #define TIVA_UART1_HANDLER                  Vector58
 #define TIVA_UART2_HANDLER                  VectorC4
@@ -352,13 +352,13 @@
 #endif
 
 /* QSSI units.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
-  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
-  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\
+  || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\
+  || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_QSSI0_HANDLER                  Vector5C
 #define TIVA_QSSI1_HANDLER                  VectorC8
 #define TIVA_QSSI2_HANDLER                  Vector118
@@ -371,13 +371,13 @@
 #endif
 
 /* I2C units.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
-  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
-  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\
+  || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\
+  || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_I2C0_HANDLER                   Vector60
 #define TIVA_I2C1_HANDLER                   VectorD4
 #define TIVA_I2C2_HANDLER                   Vector134
@@ -402,28 +402,28 @@
 #endif
 
 /* 1-Wire Master units.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
-  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\
+  || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)
 #define TIVA_HAS_1WIRE                      FALSE
 #endif
-#if defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_1WIRE_HANDLER                  Vector1E4
 
 #define TIVA_1WIRE_NUMBER                   105
 #endif
 
 /* CAN units.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
-  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
-  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\
+  || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\
+  || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_CAN0_HANDLER                   VectorD8
 #define TIVA_CAN1_HANDLER                   VectorDC
 
@@ -432,69 +432,69 @@
 #endif
 
 /* Ethernet MAC units.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1297NCZAD)\
-  || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1297NCZAD)\
+  || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)
 /* no interrupts.*/
 #endif
-#if defined(TM4C1292NCPDT) || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT)\
-  || defined(TM4C1294NCPDT) || defined(TM4C1294NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD)\
-  || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD)\
-  || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1292NCPDT) || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT)\
+  || defined(PART_TM4C1294NCPDT) || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD)\
+  || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD)\
+  || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_MAC_HANDLER                    VectorE0
 
 #define TIVA_MAC_NUMBER                     40
 #endif
 
 /* Ethernet PHY units.*/
-#if defined(TM4C1290NCPDT)|| defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT) \
-  || defined(TM4C1292NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C129CNCPDT)\
-  || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD)
+#if defined(PART_TM4C1290NCPDT)|| defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT) \
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C129CNCPDT)\
+  || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD)
 /* no interrupts.*/
 #endif
-#if  defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT) || defined(TM4C1294NCZAD)\
-  || defined(TM4C1299KCZAD) || defined(TM4C1299NCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
-  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if  defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT) || defined(PART_TM4C1294NCZAD)\
+  || defined(PART_TM4C1299KCZAD) || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\
+  || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 /* no interrupts.*/
 #endif
 
 /* USB units.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
-  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
-  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\
+  || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\
+  || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_USB0_HANDLER                   VectorE8
 
 #define TIVA_USB0_NUMBER                    42
 #endif
 
 /* LCD units.*/
-#if  defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD) || defined(TM4C129DNCZAD)\
-  || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if  defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || defined(PART_TM4C129DNCZAD)\
+  || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_LCD_HANDLER                    Vector1C4
 
 #define TIVA_LCD_NUMBER                     97
 #endif
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT)\
-  || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT)\
+  || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD)
 /* no interrupts.*/
 #endif
 
 /* AC units.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
-  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
-  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\
+  || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\
+  || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_AC0_HANDLER                    VectorA4
 #define TIVA_AC1_HANDLER                    VectorA8
 #define TIVA_AC2_HANDLER                    VectorAC
@@ -505,13 +505,13 @@
 #endif
 
 /* PWM units.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
-  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
-  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\
+  || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\
+  || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_PWM0FAULT_HANDLER              Vector64
 #define TIVA_PWM0GEN0_HANDLER               Vector68
 #define TIVA_PWM0GEN1_HANDLER               Vector6C
@@ -526,13 +526,13 @@
 #endif
 
 /* QEI units.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
-  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
-  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\
+  || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\
+  || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_QEI0_HANLDER                   Vector74
 
 #define TIVA_QEI0_NUMBER                    13
diff --git a/os/hal/ports/TIVA/TM4C129x/tiva_registry.h b/os/hal/ports/TIVA/TM4C129x/tiva_registry.h
index 5815351..cd8344d 100644
--- a/os/hal/ports/TIVA/TM4C129x/tiva_registry.h
+++ b/os/hal/ports/TIVA/TM4C129x/tiva_registry.h
@@ -1,5 +1,5 @@
 /*
-    Copyright (C) 2014..2016 Marco Veeneman
+    Copyright (C) 2014..2017 Marco Veeneman
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -25,6 +25,27 @@
 #ifndef _TIVA_REGISTRY_H_
 #define _TIVA_REGISTRY_H_
 
+#if !defined(PART_TM4C1290NCPDT) && !defined(PART_TM4C1290NCZAD) && !defined(PART_TM4C1292NCPDT)\
+  && !defined(PART_TM4C1292NCZAD) && !defined(PART_TM4C1294KCPDT) && !defined(PART_TM4C1294NCPDT)\
+  && !defined(PART_TM4C1294NCZAD) && !defined(PART_TM4C1297NCZAD) && !defined(PART_TM4C1299KCZAD)\
+  && !defined(PART_TM4C1299NCZAD) && !defined(PART_TM4C129CNCPDT) && !defined(PART_TM4C129CNCZAD)\
+  && !defined(PART_TM4C129DNCPDT) && !defined(PART_TM4C129DNCZAD) && !defined(PART_TM4C129EKCPDT)\
+  && !defined(PART_TM4C129ENCPDT) && !defined(PART_TM4C129ENCZAD) && !defined(PART_TM4C129LNCZAD)\
+  && !defined(PART_TM4C129XKCZAD) && !defined(PART_TM4C129XNCZAD)
+#error "No valid device defined."
+#endif
+
+#if !defined(TARGET_IS_TM4C129_RA0)
+#error "No valid device revision defined."
+#endif
+
+/**
+ * @brief   Sub-family identifier.
+ */
+#if !defined(TM4C129x) || defined(__DOXYGEN__)
+#define TM4C129x
+#endif
+
 /*===========================================================================*/
 /* Platform capabilities.                                                    */
 /*===========================================================================*/
@@ -35,9 +56,9 @@
  */
  
 /* GPIO attributes.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1292NCPDT) || defined(TM4C1294KCPDT)\
-  || defined(TM4C1294NCPDT) || defined(TM4C129CNCPDT) || defined(TM4C129DNCPDT)\
-  || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1292NCPDT) || defined(PART_TM4C1294KCPDT)\
+  || defined(PART_TM4C1294NCPDT) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129DNCPDT)\
+  || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT)
 #define TIVA_HAS_GPIOA                      TRUE
 #define TIVA_HAS_GPIOB                      TRUE
 #define TIVA_HAS_GPIOC                      TRUE
@@ -56,11 +77,12 @@
 #define TIVA_HAS_GPIOR                      FALSE
 #define TIVA_HAS_GPIOS                      FALSE
 #define TIVA_HAS_GPIOT                      FALSE
+#define TIVA_GPIO_PINS                      120
 #endif
-#if defined(TM4C1290NCZAD) || defined(TM4C1292NCZAD) || defined(TM4C1294NCZAD)\
-  || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD) || defined(TM4C1299NCZAD)\
-  || defined(TM4C129CNCZAD) || defined(TM4C129DNCZAD) || defined(TM4C129ENCZAD)\
-  || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294NCZAD)\
+  || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || defined(PART_TM4C1299NCZAD)\
+  || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129ENCZAD)\
+  || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_HAS_GPIOA                      TRUE
 #define TIVA_HAS_GPIOB                      TRUE
 #define TIVA_HAS_GPIOC                      TRUE
@@ -79,80 +101,81 @@
 #define TIVA_HAS_GPIOR                      TRUE
 #define TIVA_HAS_GPIOS                      TRUE
 #define TIVA_HAS_GPIOT                      TRUE
+#define TIVA_GPIO_PINS                      144
 #endif
 
 /* EPI attributes.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
-  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
-  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\
+  || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\
+  || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_HAS_EPI0                       TRUE
 #endif
 
 /* CRC attributes.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
-  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
-  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\
+  || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\
+  || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_HAS_CRC0                       TRUE
 #endif
 
 /* AES Accelerator attributes.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD)
 #define TIVA_HAS_AES                        FALSE
 #endif
-#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) \
-  || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\
-  || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\
-  || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) \
+  || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT)\
+  || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD)\
+  || defined(PART_TM4C129XNCZAD)
 #define TIVA_HAS_AES                        TRUE
 #endif
 
 /* DES Accelerator attributes.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD)
 #define TIVA_HAS_DES                        FALSE
 #endif
-#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT)\
-  || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\
-  || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\
-  || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT)\
+  || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT)\
+  || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD)\
+  || defined(PART_TM4C129XNCZAD)
 #define TIVA_HAS_DES                        TRUE
 #endif
 
 /* SHA/MD5 Accelerator attributes.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD)
 #define TIVA_HAS_SHA_MD5                    FALSE
 #endif
-#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT)\
-  || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\
-  || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\
-  || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT)\
+  || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT)\
+  || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD)\
+  || defined(PART_TM4C129XNCZAD)
 #define TIVA_HAS_SHA_MD5                    TRUE
 #endif
 
 /* GPT attributes.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
-  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
-  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\
+  || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\
+  || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_HAS_GPT0                       TRUE
 #define TIVA_HAS_GPT1                       TRUE
 #define TIVA_HAS_GPT2                       TRUE
@@ -170,37 +193,37 @@
 #endif
 
 /* WDT attributes.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
-  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
-  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\
+  || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\
+  || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_HAS_WDT0                       TRUE
 #define TIVA_HAS_WDT1                       TRUE
 #endif
 
 /* ADC attributes.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
-  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
-  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\
+  || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\
+  || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_HAS_ADC0                       TRUE
 #define TIVA_HAS_ADC1                       TRUE
 #endif
 
 /* UART attributes.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
-  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
-  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\
+  || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\
+  || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_HAS_UART0                      TRUE
 #define TIVA_HAS_UART1                      TRUE
 #define TIVA_HAS_UART2                      TRUE
@@ -212,13 +235,13 @@
 #endif
 
 /* QSSI attributes.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
-  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
-  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\
+  || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\
+  || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_HAS_QSSI0                      TRUE
 #define TIVA_HAS_QSSI1                      TRUE
 #define TIVA_HAS_QSSI2                      TRUE
@@ -226,13 +249,13 @@
 #endif
 
 /* I2C attributes.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
-  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
-  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\
+  || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\
+  || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_HAS_I2C0                       TRUE
 #define TIVA_HAS_I2C1                       TRUE
 #define TIVA_HAS_I2C2                       TRUE
@@ -246,113 +269,113 @@
 #endif
 
 /* 1-Wire Master attributes.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
-  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\
+  || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)
 #define TIVA_HAS_1WIRE                      FALSE
 #endif
-#if defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_HAS_1WIRE                      TRUE
 #endif
 
 /* CAN attributes.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
-  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
-  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\
+  || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\
+  || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_HAS_CAN0                       TRUE
 #define TIVA_HAS_CAN1                       TRUE
 #endif
 
 /* Ethernet MAC attributes.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1297NCZAD)\
-  || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1297NCZAD)\
+  || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)
 #define TIVA_HAS_ETHERNET_MAC               FALSE
 #endif
-#if defined(TM4C1292NCPDT) || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT)\
-  || defined(TM4C1294NCPDT) || defined(TM4C1294NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD)\
-  || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD)\
-  || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1292NCPDT) || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT)\
+  || defined(PART_TM4C1294NCPDT) || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD)\
+  || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD)\
+  || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_HAS_ETHERNET_MAC               TRUE
 #endif
 
 /* Ethernet PHY attributes.*/
-#if defined(TM4C1290NCPDT)|| defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT) \
-  || defined(TM4C1292NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C129CNCPDT)\
-  || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD)
+#if defined(PART_TM4C1290NCPDT)|| defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT) \
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C129CNCPDT)\
+  || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD)
 #define TIVA_HAS_ETHERNET_PHY               FALSE
 #endif
-#if  defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT) || defined(TM4C1294NCZAD)\
-  || defined(TM4C1299KCZAD) || defined(TM4C1299NCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
-  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if  defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT) || defined(PART_TM4C1294NCZAD)\
+  || defined(PART_TM4C1299KCZAD) || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\
+  || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_HAS_ETHERNET_PHY               TRUE
 #endif
 
 /* USB attributes.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
-  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
-  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\
+  || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\
+  || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_HAS_USB0                       TRUE
 #endif
 
 /* LCD attributes.*/
-#if  defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD) || defined(TM4C129DNCZAD)\
-  || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if  defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || defined(PART_TM4C129DNCZAD)\
+  || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_HAS_LCD                        TRUE
 #endif
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT)\
-  || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT)\
+  || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD)
 #define TIVA_HAS_LCD                        FALSE
 #endif
 
 /* AC attributes.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
-  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
-  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\
+  || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\
+  || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_HAS_AC0                        TRUE
 #define TIVA_HAS_AC1                        TRUE
 #define TIVA_HAS_AC2                        TRUE
 #endif
 
 /* PWM attributes.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
-  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
-  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\
+  || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\
+  || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_HAS_PWM0                       TRUE
 #define TIVA_HAS_PWM1                       FALSE
 #endif
 
 /* QEI attributes.*/
-#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
-  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
-  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
-  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
-  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
-  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
-  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\
+  || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\
+  || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\
+  || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\
+  || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\
+  || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\
+  || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD)
 #define TIVA_HAS_QEI0                       TRUE
 #define TIVA_HAS_QEI1                       FALSE
 #endif
diff --git a/os/hal/ports/TIVA/TM4C129x/tm4c129x.h b/os/hal/ports/TIVA/TM4C129x/tm4c129x.h
deleted file mode 100644
index 5a5f4f2..0000000
--- a/os/hal/ports/TIVA/TM4C129x/tm4c129x.h
+++ /dev/null
@@ -1,1131 +0,0 @@
-/*
-    Copyright (C) 2014..2016 Marco Veeneman
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @addtogroup CMSIS
- * @{
- */
-
-/**
- * @addtogroup TM4C129x
- * @{
- */
-
-#ifndef __TM4C129x_H
-#define __TM4C129x_H
-
-/** 
- * @addtogroup Configuration_section_for_CMSIS
- * @{
- */
-
-/**
- * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
- */
-#define __CM4_REV               0x0001  /**< Cortex-M4 Core Revision         */
-#define __MPU_PRESENT           1       /**< MPU present                     */
-#define __NVIC_PRIO_BITS        3       /**< Bits used for Priority Levels   */
-#define __Vendor_SysTickConfig  0       /**< Use different SysTick Config    */
-#define __FPU_PRESENT           1       /**< FPU present                     */
-
-/**
- * @brief   TM4C129x Interrupt Number Definitions
- */
-typedef enum IRQn
-{
-  /* TODO: check interrupt numbers with tm4c129 device */
-  /***** Cortex-M4 Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn   = -14,  /**< Cortex-M4 Non-Maskable Interrupt        */
-  HardFault_IRQn        = -13,  /**< Cortex-M4 Hard Fault Interrupt          */
-  MemoryManagement_IRQn = -12,  /**< Cortex-M4 Memory Management Interrupt   */
-  BusFault_IRQn         = -11,  /**< Cortex-M4 Bus Fault Interrupt           */
-  UsageFault_IRQn       = -10,  /**< Cortex-M4 Usage Fault Interrupt         */
-  SVCall_IRQn           = -5,   /**< Cortex-M4 SV Call Interrupt             */
-  DebugMonitor_IRQn     = -4,   /**< Cortex-M4 Debug Monitor Interrupt       */
-  PendSV_IRQn           = -3,   /**< Cortex-M4 Pend SV Interrupt             */
-  SysTick_IRQn          = -1,   /**< Cortex-M4 System Tick Interrupt         */
-  /***** TM4C129x Specific Interrupt Numbers *********************************/
-  GPIOA_IRQn            = 0,    /**< GPIO Port A                             */
-  GPIOB_IRQn            = 1,    /**< GPIO Port B                             */
-  GPIOC_IRQn            = 2,    /**< GPIO Port C                             */
-  GPIOD_IRQn            = 3,    /**< GPIO Port D                             */
-  GPIOE_IRQn            = 4,    /**< GPIO Port E                             */
-  UART0_IRQn            = 5,    /**< UART0                                   */
-  UART1_IRQn            = 6,    /**< UART1                                   */
-  SSI0_IRQn             = 7,    /**< SSI0                                    */
-  I2C0_IRQn             = 8,    /**< I2C0                                    */
-  PWM0FAULT_IRQn        = 9,    /**< PWM0 Fault                              */
-  PWM0GEN0_IRQn         = 10,   /**< PWM0 Generator 0                        */
-  PWM0GEN1_IRQn         = 11,   /**< PWM0 Generator 1                        */
-  PWM0GEN2_IRQn         = 12,   /**< PWM0 Generator 2                        */
-  QEI0_IRQn             = 13,   /**< QEI0                                    */
-  ADC0SEQ0_IRQn         = 14,   /**< ADC0 Sequence 0                         */
-  ADC0SEQ1_IRQn         = 15,   /**< ADC0 Sequence 1                         */
-  ADC0SEQ2_IRQn         = 16,   /**< ADC0 Sequence 2                         */
-  ADC0SEQ3_IRQn         = 17,   /**< ADC0 Sequence 3                         */
-  WATCHDOG_IRQn         = 18,   /**< Watchdog Timers 0 and 1                 */
-  TIMER0A_IRQn          = 19,   /**< 16/32-Bit Timer 0A                      */
-  TIMER0B_IRQn          = 20,   /**< 16/32-Bit Timer 0B                      */
-  TIMER1A_IRQn          = 21,   /**< 16/32-Bit Timer 1A                      */
-  TIMER1B_IRQn          = 22,   /**< 16/32-Bit Timer 1B                      */
-  TIMER2A_IRQn          = 23,   /**< 16/32-Bit Timer 2A                      */
-  TIMER2B_IRQn          = 24,   /**< 16/32-Bit Timer 2B                      */
-  ACOMP0_IRQn           = 25,   /**< Analog Comparator 0                     */
-  ACOMP1_IRQn           = 26,   /**< Analog Comparator 1                     */
-  SYSCON_IRQn           = 28,   /**< System Control                          */
-  FMCEECON_IRQn         = 29,   /**< Flash Memory Control and EEPROM Control */
-  GPIOF_IRQn            = 30,   /**< GPIO Port F                             */
-  UART2_IRQn            = 33,   /**< UART2                                   */
-  SSI1_IRQn             = 34,   /**< SSI1                                    */
-  TIMER3A_IRQn          = 35,   /**< 16/32-Bit Timer 3A                      */
-  TIMER3B_IRQn          = 36,   /**< 16/32-Bit Timer 3B                      */
-  I2C1_IRQn             = 37,   /**< I2C1                                    */
-  QEI1_IRQn             = 38,   /**< QEI1                                    */
-  CAN0_IRQn             = 39,   /**< CAN0                                    */
-  CAN1_IRQn             = 40,   /**< CAN1                                    */
-  HIBMODULE_IRQn        = 43,   /**< Hibernation Module                      */
-  USB_IRQn              = 44,   /**< USB                                     */
-  PWM0GEN3_IRQn         = 45,   /**< PWM0 Generator 3                        */
-  UDMASFW_IRQn          = 46,   /**< UDMA Software                           */
-  UDMAERR_IRQn          = 47,   /**< UDMA Error                              */
-  ADC1SEQ0_IRQn         = 48,   /**< ADC1 Sequence 0                         */
-  ADC1SEQ1_IRQn         = 49,   /**< ADC1 Sequence 1                         */
-  ADC1SEQ2_IRQn         = 50,   /**< ADC1 Sequence 2                         */
-  ADC1SEQ3_IRQn         = 51,   /**< ADC1 Sequence 3                         */
-  SSI2_IRQn             = 57,   /**< SSI2                                    */
-  SSI3_IRQn             = 58,   /**< SSI3                                    */
-  UART3_IRQn            = 59,   /**< UART3                                   */
-  UART4_IRQn            = 60,   /**< UART4                                   */
-  UART5_IRQn            = 61,   /**< UART5                                   */
-  UART6_IRQn            = 62,   /**< UART6                                   */
-  UART7_IRQn            = 63,   /**< UART7                                   */
-  I2C2_IRQn             = 68,   /**< I2C2                                    */
-  I2C3_IRQn             = 69,   /**< I2C3                                    */
-  TIMER4A_IRQn          = 70,   /**< 16/32-Bit Timer 4A                      */
-  TIMER4B_IRQn          = 71,   /**< 16/32-Bit Timer 4B                      */
-  TIMER5A_IRQn          = 92,   /**< 16/32-Bit Timer 5A                      */
-  TIMER5B_IRQn          = 93,   /**< 16/32-Bit Timer 5B                      */
-  WTIMER0A_IRQn         = 94,   /**< 32/64-Bit Timer 0A                      */
-  WTIMER0B_IRQn         = 95,   /**< 32/64-Bit Timer 0B                      */
-  WTIMER1A_IRQn         = 96,   /**< 32/64-Bit Timer 1A                      */
-  WTIMER1B_IRQn         = 97,   /**< 32/64-Bit Timer 1B                      */
-  WTIMER2A_IRQn         = 98,   /**< 32/64-Bit Timer 2A                      */
-  WTIMER2B_IRQn         = 99,   /**< 32/64-Bit Timer 2B                      */
-  WTIMER3A_IRQn         = 100,  /**< 32/64-Bit Timer 3A                      */
-  WTIMER3B_IRQn         = 101,  /**< 32/64-Bit Timer 3B                      */
-  WTIMER4A_IRQn         = 102,  /**< 32/64-Bit Timer 4A                      */
-  WTIMER4B_IRQn         = 103,  /**< 32/64-Bit Timer 4B                      */
-  WTIMER5A_IRQn         = 104,  /**< 32/64-Bit Timer 5A                      */
-  WTIMER5B_IRQn         = 105,  /**< 32/64-Bit Timer 5B                      */
-  SYSEXCEPT_IRQn        = 106,  /**< System Exception (imprecise)            */
-  PWM1GEN0_IRQn         = 134,  /**< PWM1 Generator 0                        */
-  PWM1GEN1_IRQn         = 135,  /**< PWM1 Generator 1                        */
-  PWM1GEN2_IRQn         = 136,  /**< PWM1 Generator 2                        */
-  PWM1GEN3_IRQn         = 137,  /**< PWM1 Generator 3                        */
-  PWM1FAULT_IRQn        = 138   /**< PWM1 Fault                              */
-} IRQn_Type;
- 
-/**
- * @}
- */
-
-#include "core_cm4.h"   /* Cortex-M4 processor and core peripherals.*/
-#include <stdint.h>
-
-/**
- * @addtogroup Peripheral_registers_structures
- * @{
- */
-
-/**
- * @brief Analog Comparator
- */
-typedef struct
-{
-  __IO uint32_t MIS;            /**< Masked Interrupt Status                 */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __IO uint32_t INTEN;          /**< Interrupt Enable                        */
-  __I  uint32_t _RESERVED0[1];  /**< Reserved                                */
-  __IO uint32_t REFCTL;         /**< Reference Voltage Control               */
-  __I  uint32_t _RESERVED1[3];  /**< Reserved                                */
-  __I  uint32_t STAT0;          /**< Status 0                                */
-  __IO uint32_t CTL0;           /**< Control 0                               */
-  __I  uint32_t _RESERVED2[6];  /**< Reserved                                */
-  __I  uint32_t STAT1;          /**< Status 1                                */
-  __IO uint32_t CTL1;           /**< Control 1                               */
-  __I  uint32_t _RESERVED3[990];/**< Reserved                                */
-  __I  uint32_t PP;             /**< Peripheral Properties                   */
-} ACMP_TypeDef;
-
-/**
- * @brief Analog-to-Digital Converter
- */
-typedef struct
-{
-  __IO uint32_t MUX;            /**< Sample Sequence Input Multiplexer
-                                     Select                                  */
-  __IO uint32_t CTL;            /**< Sample Sequence Control                 */
-  __I  uint32_t FIFO;           /**< Sample Sequence Result FIFO             */
-  __I  uint32_t FSTAT;          /**< Sample Sequence FIFO Status             */
-  __IO uint32_t OP;             /**< Sample Sequence Operation               */
-  __IO uint32_t DC;             /**< Sample Sequence Digital Comparator
-                                     Select                                  */
-  __I  uint32_t _RESERVED0[2];  /**< Reserved                                */
-} ADC_SS_t;
-
-typedef struct
-{
-  __IO uint32_t ACTSS;          /**< Active Sample Sequencer                 */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __IO uint32_t IM;             /**< Interrupt Mask                          */
-  __IO uint32_t ISC;            /**< Interrupt Status and Clear              */
-  __IO uint32_t OSTAT;          /**< Overflow Status                         */
-  __IO uint32_t EMUX;           /**< Event Multiplexer Select                */
-  __IO uint32_t USTAT;          /**< Underflow Status                        */
-  __IO uint32_t TSSEL;          /**< Trigger Source Select                   */
-  __IO uint32_t SSPRI;          /**< Sample Sequencer Priority               */
-  __IO uint32_t SPC;            /**< Sample Phase Control                    */
-  __IO uint32_t PSSI;           /**< Processor Sample Sequence Initiate      */
-  __I  uint32_t _RESERVED0[1];  /**< Reserved                                */
-  __IO uint32_t SAC;            /**< Sample Averaging Control                */
-  __IO uint32_t DCISC;          /**< Digital Comparator Interrupt Status and
-                                     Clear                                   */
-  __IO uint32_t CTL;            /**< Control                                 */
-  __I  uint32_t _RESERVED1[1];  /**< Reserved                                */
-  ADC_SS_t SS[4];               /**< Sample Sequence 0, 1, 2 and 3           */
-  __I  uint32_t _RESERVED2[784];/**< Reserved */
-  __O  uint32_t DCRIC;          /**< Digital Comparator Reset Initial
-                                     Conditions                              */
-  __I  uint32_t _RESERVED3[63]; /**< Reserved                                */
-  __IO uint32_t DCCTL[8];       /**< Digital Comparator Control 0 - 7        */
-  __I  uint32_t _RESERVED4[8];  /**< Reserved                                */
-  __IO uint32_t DCCMP[8];       /**< Digital Comparator Range 0 - 7          */
-  __I  uint32_t _RESERVED5[88]; /**< Reserved                                */
-  __I  uint32_t PP;             /**< Peripheral Properties                   */
-  __IO uint32_t PC;             /**< Peripheral Configuration                */
-  __IO uint32_t CC;             /**< Clock Configuration                     */
-} ADC_TypeDef;
-
-/**
- * @brief Controller Area Network
- */
-typedef struct
-{
-  __IO uint32_t CRQ;            /**< Command Request                         */
-  __IO uint32_t CMSK;           /**< Command Mask                            */
-  __IO uint32_t MSK[2];         /**< Mask 1 and 2                            */
-  __IO uint32_t ARB[2];         /**< Arbitration 1 and 2                     */
-  __IO uint32_t MCTL;           /**< Message Control                         */
-  __IO uint32_t DA[2];          /**< Data A1 and A2                          */
-  __IO uint32_t DB[2];          /**< Data B1 and B2                          */
-  __I  uint32_t _RESERVED0[13]; /**< Reserved                                */
-} CAN_INTERFACE_t;
-
-typedef struct
-{
-  __IO uint32_t CTL;            /**< Control                                 */
-  __IO uint32_t STS;            /**< Status                                  */
-  __I  uint32_t ERR;            /**< Error Counter                           */
-  __IO uint32_t BIT;            /**< Bit Timing                              */
-  __I  uint32_t INT;            /**< Interrupt                               */
-  __IO uint32_t TST;            /**< Test                                    */
-  __IO uint32_t BRPE;           /**< Baud Rate Prescaler Extension           */
-  __I  uint32_t _RESERVED0[1];  /**< Reserved                                */
-  CAN_INTERFACE_t IF[2];        /**< IF1 and IF2                             */
-  __I  uint32_t _RESERVED1[8];  /**< Reserved                                */
-  __I  uint32_t TXRQ[2];        /**< Transmission Request 1 and 2            */
-  __I  uint32_t _RESERVED2[6];  /**< Reserved                                */
-  __I  uint32_t NWDA[2];        /**< New Data 1 and 2                        */
-  __I  uint32_t _RESERVED3[6];  /**< Reserved                                */
-  __I  uint32_t MSGINT[2];      /**< Message 1 and 2 Interrupt Pending       */
-  __I  uint32_t _RESERVED4[6];  /**< Reserved                                */
-  __I  uint32_t MSGVAL[2];      /**< Message 1 and 2 Valid                   */
-} CAN_TypeDef;
-
-/**
- * @brief EEPROM Memory
- */
-typedef struct
-{
-  __IO uint32_t EESIZE;         /**< Size Information                        */
-  __IO uint32_t EEBLOCK;        /**< Current Block                           */
-  __IO uint32_t EEOFFSET;       /**< Current Offset                          */
-  __I  uint32_t _RESERVED0[1];  /**< Reserved                                */
-  __IO uint32_t EERDWR;         /**< Read-Write                              */
-  __IO uint32_t EERDWRINC;      /**< Read-Write with Increment               */
-  __IO uint32_t EEDONE;         /**< Done Status                             */
-  __IO uint32_t EESUPP;         /**< Support Control and Status              */
-  __IO uint32_t EEUNLOCK;       /**< Unlock                                  */
-  __I  uint32_t _RESERVED1[3];  /**< Reserved                                */
-  __IO uint32_t EEPROT;         /**< Protection                              */
-  __IO uint32_t EEPASS[3];      /**< Password                                */
-  __IO uint32_t EEINT;          /**< Interrupt                               */
-  __I  uint32_t _RESERVED2[3];  /**< Reserved                                */
-  __IO uint32_t EEHIDE;         /**< Block Hide                              */
-  __I  uint32_t _RESERVED3[11]; /**< Reserved                                */
-  __IO uint32_t EEDBGME;        /**< Debug Mass Erase                        */
-  __I  uint32_t _RESERVED4[975];/**< Reserved                                */
-  __IO uint32_t EEPROMPP;       /**< Peripheral Properties                   */
-} EEPROM_TypeDef;
-
-/**
- * @brief Flash Memory
- */
-typedef struct
-{
-  __IO uint32_t FMA;            /**< Flash Memory Address                    */
-  __IO uint32_t FMD;            /**< Flash Memory Data                       */
-  __IO uint32_t FMC;            /**< Flash Memory Control                    */
-  __I  uint32_t FCRIS;          /**< Flash Controller Raw Interrupt Status   */
-  __IO uint32_t FCIM;           /**< Flash Controller Interrupt Mask         */
-  __IO uint32_t FCMISC;         /**< Masked Interrupt Status and Clear       */
-  __I  uint32_t _RESERVED0[2];  /**< Reserved                                */
-  __IO uint32_t FMC2;           /**< Flash Memory Control 2                  */
-  __I  uint32_t _RESERVED1[3];  /**< Reserved                                */
-  __IO uint32_t FWBVAL;         /**< Flash Write Buffer Valid                */
-  __I  uint32_t _RESERVED2[51]; /**< Reserved                                */
-  __IO uint32_t FWBN;           /**< Flash Write Buffer n                    */
-  __I  uint32_t _RESERVED3[943];/**< Reserved                                */
-  __I  uint32_t FSIZE;          /**< Flash Size                              */
-  __I  uint32_t SSIZE;          /**< SRAM Size                               */
-  __I  uint32_t _RESERVED4[1];  /**< Reserved                                */
-  __IO uint32_t ROMSWMAP;       /**< ROM Software Map                        */
-} FLASH_TypeDef;
-
-
-
-/**
- * @brief General Purpose Input/Outputs
- */
-typedef struct
-{
-  union {
-    __IO uint32_t MASKED_ACCESS[256];   /**< Masked access of Data Register  */
-    struct {
-      __I  uint32_t _RESERVED0[255];    /**< Reserved                        */
-      __IO uint32_t DATA;       /**< Data                                    */
-    };
-  };
-  __IO uint32_t DIR;            /**< Direction                               */
-  __IO uint32_t IS;             /**< Interrupt Sense                         */
-  __IO uint32_t IBE;            /**< Interrupt Both Edges                    */
-  __IO uint32_t IEV;            /**< Interrupt Event                         */
-  __IO uint32_t IM;             /**< Interrupt Mask                          */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
-  __O  uint32_t ICR;            /**< Interrupt Clear                         */
-  __IO uint32_t AFSEL;          /**< Alternate Function Select               */
-  __I  uint32_t _RESERVED1[55]; /**< Reserved                                */
-  __IO uint32_t DR2R;           /**< 2-mA Drive Select                       */
-  __IO uint32_t DR4R;           /**< 4-mA Drive Select                       */
-  __IO uint32_t DR8R;           /**< 8-mA Drive Select                       */
-  __IO uint32_t ODR;            /**< Open Drain Select                       */
-  __IO uint32_t PUR;            /**< Pull-Up Select                          */
-  __IO uint32_t PDR;            /**< Pull-Down Select                        */
-  __IO uint32_t SLR;            /**< Slew Rate Control Select                */
-  __IO uint32_t DEN;            /**< Digital Enable                          */
-  __IO uint32_t LOCK;           /**< Lock                                    */
-  __IO uint32_t CR;             /**< Commit                                  */
-  __IO uint32_t AMSEL;          /**< Analog Mode Select                      */
-  __IO uint32_t PCTL;           /**< Port Control                            */
-  __IO uint32_t ADCCTL;         /**< ADC Control                             */
-  __IO uint32_t DMACTL;         /**< DMA Control                             */
-  __IO uint32_t SI;             /**< */
-  __IO uint32_t DR12R;          /**< */
-  __IO uint32_t WAKEPEN;        /**< */
-  __IO uint32_t WAKELVL;        /**< */
-  __IO uint32_t WAKESTAT;       /**< */
-  __I  uint32_t _RESERVED2[669];/**< */
-  __I  uint32_t PP;             /**< */
-  __IO uint32_t PC;             /**< */
-} GPIO_TypeDef;
-
-/**
- * @brief General Purpose Timer
- */
-typedef struct
-{
-  __IO uint32_t CFG;            /**< Configuration                           */
-  __IO uint32_t TAMR;           /**< Timer A Mode                            */
-  __IO uint32_t TBMR;           /**< Timer B Mode                            */
-  __IO uint32_t CTL;            /**< Control                                 */
-  __IO uint32_t SYNC;           /**< Synchronize                             */
-  __I  uint32_t _RESERVED0[1];  /**< Reserved                                */
-  __IO uint32_t IMR;            /**< Interrupt Mask                          */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
-  __O  uint32_t ICR;            /**< Interrupt Clear                         */
-  __IO uint32_t TAILR;          /**< Timer A Interval Load                   */
-  __IO uint32_t TBILR;          /**< Timer B Interval Load                   */
-  __IO uint32_t TAMATCHR;       /**< Timer A Match                           */
-  __IO uint32_t TBMATCHR;       /**< Timer B Match                           */
-  __IO uint32_t TAPR;           /**< Timer A Prescale                        */
-  __IO uint32_t TBPR;           /**< Timer B Prescale                        */
-  __IO uint32_t TAPMR;          /**< Timer A Prescale Match                  */
-  __IO uint32_t TBPMR;          /**< Timer B Prescale Match                  */
-  __I  uint32_t TAR;            /**< Timer A                                 */
-  __I  uint32_t TBR;            /**< Timer B                                 */
-  __IO uint32_t TAV;            /**< Timer A Value                           */
-  __IO uint32_t TBV;            /**< Timer B Value                           */
-  __I  uint32_t RTCPD;          /**< RTC Predivide                           */
-  __I  uint32_t TAPS;           /**< Timer A Prescale Snapshot               */
-  __I  uint32_t TBPS;           /**< Timer B Prescale Snapshot               */
-  __I  uint32_t TAPV;           /**< Timer A Prescale Value                  */
-  __I  uint32_t TBPV;           /**< Timer B Prescale Value                  */
-  __I  uint32_t _RESERVED1[981];/**< Reserved                                */
-  __I  uint32_t PP;             /**< Peripheral Properties                   */
-} GPT_TypeDef;
-
-/**
- * @brief Hibernation Module
- */
-typedef struct
-{
-  __I  uint32_t RTCC;           /**< RTC Counter                             */
-  __IO uint32_t RTCM0;          /**< RTC Match 0                             */
-  __I  uint32_t _RESERVED0[1];  /**< Reserved                                */
-  __IO uint32_t RTCLD;          /**< RTC Load                                */
-  __IO uint32_t CTL;            /**< Control                                 */
-  __IO uint32_t IM;             /**< Interrupt Mask                          */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
-  __IO uint32_t IC;             /**< Interrupt Clear                         */
-  __IO uint32_t RTCT;           /**< RTC Trim                                */
-  __IO uint32_t RTCSS;          /**< RTC Sub Seconds                         */
-  __I  uint32_t _RESERVED1[1];  /**< Reserved                                */
-  __IO uint32_t DATA;           /**< Data                                    */
-} HIB_TypeDef;
-
-/**
- * @brief Inter-Integrated Circuit
- */
-typedef struct
-{
-  __IO uint32_t MSA;            /**< Master Slave Address                    */
-  __IO uint32_t MCS;            /**< Master Control/Status                   */
-  __IO uint32_t MDR;            /**< Master Data                             */
-  __IO uint32_t MTPR;           /**< Master Timer Period                     */
-  __IO uint32_t MIMR;           /**< Master Interrupt Mask                   */
-  __I  uint32_t MRIS;           /**< Master Raw Interrupt Status             */
-  __IO uint32_t MMIS;           /**< Master Masked Interrupt Status          */
-  __O  uint32_t MICR;           /**< Master Interrupt Clear                  */
-  __IO uint32_t MCR;            /**< Master Configuration                    */
-  __IO uint32_t MCLKOCNT;       /**< Master Clock Low Timeout Count          */
-  __I  uint32_t _RESERVED0[1];  /**< Reserved                                */
-  __I  uint32_t MBMON;          /**< Master Bus Monitor                      */
-  __IO uint32_t MCR2;           /**< Master Configuration 2                  */
-  __I  uint32_t _RESERVED1[497];/**< Reserved                                */
-  __IO uint32_t SOAR;           /**< Slave Own Address                       */
-  __IO uint32_t SCSR;           /**< Slave Control/Status                    */
-  __IO uint32_t SDR;            /**< Slave Data                              */
-  __IO uint32_t SIMR;           /**< Slave Interrupt Mask                    */
-  __I  uint32_t SRIS;           /**< Slave Raw Interrupt Status              */
-  __I  uint32_t SMIS;           /**< Slave Masked Interrupt Status           */
-  __O  uint32_t SICR;           /**< Slave Interrupt Clear                   */
-  __IO uint32_t SOAR2;          /**< Slave Own Address 2                     */
-  __IO uint32_t SACKCTL;        /**< Slave ACK Control                       */
-  __I  uint32_t _RESERVED2[487];/**< Reserved                                */
-  __I  uint32_t PP;             /**< Peripheral Properties                   */
-  __I  uint32_t PC;             /**< Peripheral Configuration                */
-} I2C_TypeDef;
-
-/*
- * @brief Pulse Width Modulator
- */
-typedef struct
-{
-  __IO uint32_t CTL;            /**< Control                                 */
-  __IO uint32_t INTEN;          /**< Interrupt and Trigger Enable            */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __IO uint32_t ISC;            /**< Interrupt Status and Clear              */
-  __IO uint32_t LOAD;           /**< Load                                    */
-  __I  uint32_t COUNT;          /**< Counter                                 */
-  __IO uint32_t CMP[2];         /**< Compare A, B                            */
-  __IO uint32_t GEN[2];         /**< Generator A, B Control                  */
-  __IO uint32_t DBCTL;          /**< Dead-Band Control                       */
-  __IO uint32_t DBRISE;         /**< Dead-Band Rising-Edge Delay             */
-  __IO uint32_t DBFALL;         /**< Dead-Band Falling-Edge Delay            */
-  __IO uint32_t FLTSRC[2];      /**< Fault Source 0, 1                       */
-  __IO uint32_t MINFLTPER;      /**< Minimum Fault Period                    */
-} PWM_GENERATOR_T;
-
-typedef struct
-{
-  union {
-    __IO uint32_t SEN;          /**< Fault Pin Logic Sense, for GEN 0 and 1  */
-    __I  uint32_t _RESERVED0[1];/**< Reserved, for GEN 2 and 3               */
-  };
-  __IO uint32_t STAT[2];        /**< Fault Status                            */
-  __I  uint32_t _RESERVED1[29]; /**< Reserved                                */
-} PWM_FLT_t;
-
-typedef struct
-{
-  __IO uint32_t CTL;            /**< Master Control                          */
-  __IO uint32_t SYNC;           /**< Time Base Sync                          */
-  __IO uint32_t ENABLE;         /**< Output Enable                           */
-  __IO uint32_t INVERT;         /**< Output Inversion                        */
-  __IO uint32_t FAULT;          /**< Output Fault                            */
-  __IO uint32_t INTEN;          /**< Interrupt Enable                        */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __IO uint32_t ISC;            /**< Interrupt Status and Clear              */
-  __I  uint32_t STATUS;         /**< Status                                  */
-  __IO uint32_t FAULTVAL;       /**< Fault Condition Value                   */
-  __IO uint32_t ENUPD;          /**< Enable Update                           */
-  __I  uint32_t _RESERVED0[5];  /**< Reserved                                */
-  __IO PWM_GENERATOR_T PWM[4];  /**< PWM Generator 0, 1, 2 and 3             */
-  __I  uint32_t _RESERVED1[432];/**< Reserved                                */
-  PWM_FLT_t FLT[4];             /**< Fault registers 0, 1, 2 and 3           */
-  __I  uint32_t _RESERVED2[368];/**< Reserved                                */
-  __I  uint32_t PP;             /**< Peripheral Properties                   */
-} PWM_TypeDef;
-
-/**
- * @brief Quadrature Encoder Interface
- */
-typedef struct
-{
-  __IO uint32_t CTL;            /**< Control                                 */
-  __I  uint32_t STAT;           /**< Status                                  */
-  __IO uint32_t POS;            /**< Position                                */
-  __IO uint32_t MAXPOS;         /**< Maximum Position                        */
-  __IO uint32_t LOAD;           /**< Timer Load                              */
-  __I  uint32_t TIME;           /**< Timer                                   */
-  __I  uint32_t COUNT;          /**< Velocity Counter                        */
-  __I  uint32_t SPEED;          /**< Velocity                                */
-  __IO uint32_t INTEN;          /**< Interrupt Enable                        */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __IO uint32_t ISC;            /**< Interrupt Status and Clear              */
-} QEI_TypeDef;
-
-/**
- * @brief Synchronous Serial Interface
- */
-typedef struct
-{
-  __IO uint32_t CR[2];          /**< Control 0, 1                            */
-  __IO uint32_t DR;             /**< Data                                    */
-  __I  uint32_t SR;             /**< Status                                  */
-  __IO uint32_t CPSR;           /**< Clock Prescale                          */
-  __IO uint32_t IM;             /**< Interrupt Mask                          */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
-  __O  uint32_t ICR;            /**< Interrupt Clear                         */
-  __IO uint32_t DMACTL;         /**< DMA Control                             */
-  __I  uint32_t _RESERVED0[1000];/**< Reserved                               */
-  __IO uint32_t CC;             /**< Clock Configuration                     */
-} SSI_TypeDef;
-
-/** 
- * @brief System Control
- */
-typedef struct
-{
-  __I  uint32_t DID0;           /**< Device Identification 0                 */
-  __I  uint32_t DID1;           /**< Device Identification 1                 */
-  __I  uint32_t RESERVED0[12];  /**< Reserved                                */
-  __IO uint32_t PBORCTL;        /**< Power-Temp Brown Out Control                 */
-  __I  uint32_t RESERVED1[5];   /**< Reserved                                */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __IO uint32_t IMC;            /**< Interrupt Mask Control                  */
-  __IO uint32_t MISC;           /**< Interrupt Status and Clear              */
-  __IO uint32_t RESC;           /**< Reset Cause                             */
-  __IO uint32_t PWRTC;          /**< Power-Temperature Cause */
-  __IO uint32_t NMIC;           /**< NMI Cause Register */
-  __I  uint32_t RESERVED2[5];   /**< Reserved */
-  __IO uint32_t MOSCCTL;        /**< Main Oscillator Control */
-  __I  uint32_t RESERVED3[12];  /**< Reserved */
-  __IO uint32_t RSCLKCFG;       /**< Run and Sleep Mode Configuration Register */
-  __I  uint32_t RESERVEDx[3];
-  __IO uint32_t MEMTIM0;        /**< Memory Timing Parameter Register 0 for Main Flash and EEPROM */
-  __I  uint32_t RESERVED4[29];  /**< Reserved */
-  __IO uint32_t ALTCLKCFG;      /**< Alternate Clock Configuration */
-  __I  uint32_t RESERVED5[2];   /**< Reserved                                */
-  __IO uint32_t DSLPCLKCFG;     /**< Deep Sleep Clock Configuration          */
-  __IO uint32_t DIVSCLK;        /**< Divisor and Source Clock Configuration  */
-  __I  uint32_t SYSPROP;        /**< System Properties                       */
-  __IO uint32_t PIOSCCAL;       /**< PIOSC Calibration                       */
-  __I  uint32_t PIOSCSTAT;      /**< PIOSC Statistics                        */
-  __I  uint32_t RESERVED6[2];   /**< Reserved                                */
-  __IO uint32_t PLLFREQ0;       /**< PLL Frequency 0                         */
-  __IO uint32_t PLLFREQ1;       /**< PLL Frequency 1                         */
-  __I  uint32_t PLLSTAT;        /**< PLL Frequency Status                    */
-  __I  uint32_t RESERVED7[7];   /**< Reserved                                */
-  __IO uint32_t SLPPWRCFG;      /**< Sleep Power Configuration               */
-  __IO uint32_t DSLPPWRCFG;     /**< Deep-Sleep Power Configuration          */
-  __I  uint32_t RESERVED8[4];   /**< Reserved                                */
-  __I  uint32_t NVMSTAT;        /**< Non-Volatile Memory Information */
-  __I  uint32_t RESERVED9[4];   /**< Reserved */
-  __IO uint32_t LDOSPCTL;       /**< LDO Sleep Power Control                 */
-  __I  uint32_t LDOSPCAL;       /**< LDO Sleep Power Calibration             */
-  __IO uint32_t LDODPCTL;       /**< LDO Deep-Sleep Power Control            */
-  __I  uint32_t LDODPCAL;       /**< LDO Deep-Sleep Power Calibration        */
-  __I  uint32_t RESERVED10[2];  /**< Reserved                                */
-  __I  uint32_t SDPMST;         /**< Sleep/Deep-Sleep Power Mode Status      */
-  __I  uint32_t RESERVED11[2];  /**< Reserved */
-  __IO uint32_t RESBEHAVCTL;    /**< Reset Behavior Control Register */
-  __I  uint32_t RESERVED12[6];  /**< Reserved */
-  __IO uint32_t HSSR;           /**< Hardware System Service Request */
-  __I  uint32_t RESERVED[34];   /**< Reserved */
-  __I  uint32_t USBPDS;         /**< USB Power Domain Status */
-  __IO uint32_t USBMPC;         /**< USB Memory Power Control */
-  __I  uint32_t EMACPDS;        /**< Ethernet MAC Power Domain Status */
-  __IO uint32_t EMACMPC;        /**< Ethernet MAC Memory Power Control */
-  __I  uint32_t RESERVED13[2];  /**< Reserved */
-  __I  uint32_t CAN0PDS;        /**< CAN 0 Power Domain Status */
-  __IO uint32_t CAN0MPC;        /**< CAN 0 Memory Power Control */
-  __I  uint32_t CAN1PDS;        /**< CAN 1 Power Domain Status */
-  __IO uint32_t CAN1MPC;        /**< CAN 1 Memory Power Control */
-  __I  uint32_t RESERVED14[22]; /**< Reserved */
-  __I  uint32_t PPWD;           /**< WDT Peripheral Present                  */
-  __I  uint32_t PPTIMER;        /**< GPT Peripheral Present                  */
-  __I  uint32_t PPGPIO;         /**< GPIO Peripheral Present                 */
-  __I  uint32_t PPDMA;          /**< UDMA Peripheral Present                 */
-  __I  uint32_t PPEPI;          /**< EPI Peripheral Present */
-  __I  uint32_t PPHIB;          /**< HIB Peripheral Present                  */
-  __I  uint32_t PPUART;         /**< UART Peripheral Present                 */
-  __I  uint32_t PPSSI;          /**< SSI Peripheral Present                  */
-  __I  uint32_t PPI2C;          /**< I2C Peripheral Present                  */
-  __I  uint32_t RESERVED15[1];  /**< Reserved                                */
-  __I  uint32_t PPUSB;          /**< USB Peripheral Present                  */
-  __I  uint32_t RESERVED16[1];  /**< Reserved                                */
-  __I  uint32_t PPEPHY;         /**< Ethernet PHY Peripheral Present */
-  __I  uint32_t PPCAN;          /**< CAN Peripheral Present                  */
-  __I  uint32_t PPADC;          /**< ADC Peripheral Present                  */
-  __I  uint32_t PPACMP;         /**< ACMP Peripheral Present                 */
-  __I  uint32_t PPPWM;          /**< PWM Peripheral Present                  */
-  __I  uint32_t PPQEI;          /**< QEI Peripheral Present                  */
-  __I  uint32_t PPLPC;          /**< Low Pin Count Interface Peripheral Present */
-  __I  uint32_t RESERVED17[1];  /**< Reserved */
-  __I  uint32_t PPPECI;         /**< Platform Environment Control Interface Peripheral Present */
-  __I  uint32_t PPFAN;          /**< Fan Control Peripheral Present */
-  __I  uint32_t PPEEPROM;       /**< EEPROM Peripheral Present               */
-  __I  uint32_t PPWTIMER;       /**< Wide GPT Peripheral Present             */
-  __I  uint32_t RESERVED18[4];  /**< Reserved */
-  __I  uint32_t PPRTS;          /**< Remote Temperature Sensor Peripheral Present */
-  __I  uint32_t PPCCM;          /**< CRC Module Peripheral Present */
-  __I  uint32_t RESERVED19[6];  /**< Reserved */
-  __I  uint32_t PPLCD;          /**< LCD Peripheral Present */
-  __I  uint32_t RESERVED20[1];  /**< Reserved */
-  __I  uint32_t PPOWIRE;        /**< 1-Wire Peripheral Present */
-  __I  uint32_t PPEMAC;         /**< Ethernet MAC Peripheral Present */
-  __I  uint32_t PPPRB;          /**< Power Regulator Bus Peripheral Present */
-  __I  uint32_t PPHIM;          /**< Human Interface Master Peripheral Present */
-  __I  uint32_t RESERVED21[86]; /**< Reserved */
-  __IO uint32_t SRWD;           /**< WDT Software Reset                      */
-  __IO uint32_t SRTIMER;        /**< GPT Software Reset                      */
-  __IO uint32_t SRGPIO;         /**< GPIO Software Reset                     */
-  __IO uint32_t SRDMA;          /**< UDMA Software Reset                     */
-  __IO uint32_t SREPI;          /**< EPI Software Reset */
-  __IO uint32_t SRHIB;          /**< HIB Software Reset                      */
-  __IO uint32_t SRUART;         /**< UART Software Reset                     */
-  __IO uint32_t SRSSI;          /**< SSI Software Reset                      */
-  __IO uint32_t SRI2C;          /**< I2C Software Reset                      */
-  __I  uint32_t RESERVED22[1];  /**< Reserved                                */
-  __IO uint32_t SRUSB;          /**< USB Software Reset                      */
-  __I  uint32_t RESERVED23[1];  /**< Reserved                                */
-  __IO uint32_t SREPHY;         /**< Ethernet PHY Software Reset */
-  __IO uint32_t SRCAN;          /**< CAN Software Reset                      */
-  __IO uint32_t SRADC;          /**< ADC Software Reset                      */
-  __IO uint32_t SRACMP;         /**< ACMP Software Reset                     */
-  __IO uint32_t SRPWM;          /**< PWM Software Reset                      */
-  __IO uint32_t SRQEI;          /**< QEI Software Reset                      */
-  __I  uint32_t RESERVED24[4];  /**< Reserved                                */
-  __IO uint32_t SREEPROM;       /**< EEPROM Software Reset                   */
-  __I  uint32_t RESERVED25[6];  /**< Reserved */
-  __IO uint32_t SRCCM;          /**< CRC Module Software Reset */
-  __I  uint32_t RESERVED26[9];  /**< Reserved */
-  __IO uint32_t SREMAC;         /**< Ethernet MAC Software Reset */
-  __I  uint32_t RESERVED27[24]; /**< Reserved                                */
-  __IO uint32_t RCGCWD;         /**< WDT Run Mode Clock Gating Control       */
-  __IO uint32_t RCGCTIMER;      /**< GPT Run Mode Clock Gating Control       */
-  __IO uint32_t RCGCGPIO;       /**< GPIO Run Mode Clock Gating Control      */
-  __IO uint32_t RCGCDMA;        /**< UDMA Run Mode Clock Gating Control      */
-  __IO uint32_t RCGCEPI;        /**< EPI Run Mode Clock Gating Control */
-  __IO uint32_t RCGCHIB;        /**< HIB Run Mode Clock Gating Control       */
-  __IO uint32_t RCGCUART;       /**< UART Run Mode Control                   */
-  __IO uint32_t RCGCSSI;        /**< SSI Run Mode Clock Gating Control       */
-  __IO uint32_t RCGCI2C;        /**< I2C Run Mode Clock Gating Control       */
-  __I  uint32_t RESERVED28[1];  /**< Reserved                                */
-  __IO uint32_t RCGCUSB;        /**< USB Run Mode Clock Gating Control       */
-  __I  uint32_t RESERVED29[1];  /**< Reserved                                */
-  __IO uint32_t RCGCEPHY;       /**< Ethernet PHY Run Mode Clock Gating Control */
-  __IO uint32_t RCGCCAN;        /**< CAN Run Mode Clock Gating Control       */
-  __IO uint32_t RCGCADC;        /**< ADC Run Mode Clock Gating Control       */
-  __IO uint32_t RCGCACMP;       /**< ACMP Run Mode Clock Gating Control      */
-  __IO uint32_t RCGCPWM;        /**< PWM Run Mode Clock Gating Control       */
-  __IO uint32_t RCGCQEI;        /**< QEI Run Mode Clock Gating Control       */
-  __I  uint32_t RESERVED30[4];  /**< Reserved                                */
-  __IO uint32_t RCGCEEPROM;     /**< EEPROM Run Mode Clock Gating Control    */
-  __I  uint32_t RESERVED31[6];  /**< Reserved */
-  __IO uint32_t RCGCCCM;        /**< CRC Module Run Mode Clock Gating Control */
-  __I  uint32_t RESERVED32[9];  /**< Reserved */
-  __IO uint32_t RCGCEMAC;       /**< Ethernet MAC Run Mode Clock Gating Control */
-  __I  uint32_t RESERVED33[24]; /**< Reserved */
-  __IO uint32_t SCGCWD;         /**< WDT Sleep Mode Clock Gating Control     */
-  __IO uint32_t SCGCTIMER;      /**< GPT Sleep Mode Clock Gating Control     */
-  __IO uint32_t SCGCGPIO;       /**< GPIO Sleep Mode Clock Gating Control    */
-  __IO uint32_t SCGCDMA;        /**< UDMA Sleep Mode Clock Gating Control    */
-  __IO uint32_t SCGCEPI;        /**< EPI Sleep Mode Clock Gating Control */
-  __IO uint32_t SCGCHIB;        /**< HIB Sleep Mode Clock Gating Control     */
-  __IO uint32_t SCGCUART;       /**< UART Sleep Mode Clock Gating Control    */
-  __IO uint32_t SCGCSSI;        /**< SSI Sleep Mode Clock Gating Control     */
-  __IO uint32_t SCGCI2C;        /**< I2C Sleep Mode Clock Gating Control     */
-  __I  uint32_t RESERVED34[1];  /**< Reserved                                */
-  __IO uint32_t SCGCUSB;        /**< USB Sleep Mode Clock Gating Control     */
-  __I  uint32_t RESERVED35[1];  /**< Reserved                                */
-  __IO uint32_t SCGCEPHY;       /**< Ethernet PHY Sleep Mode Clock Gating Control */
-  __IO uint32_t SCGCCAN;        /**< CAN Sleep Mode Clock Gating Control     */
-  __IO uint32_t SCGCADC;        /**< ADC Sleep Mode Clock Gating Control     */
-  __IO uint32_t SCGCACMP;       /**< ACMP Sleep Mode Clock Gating Control    */
-  __IO uint32_t SCGCPWM;        /**< PWM Sleep Mode Clock Gating Control     */
-  __IO uint32_t SCGCQEI;        /**< QEI Sleep Mode Clock Gating Control     */
-  __I  uint32_t RESERVED36[4];  /**< Reserved                                */
-  __IO uint32_t SCGCEEPROM;     /**< EEPROM Sleep Mode Clock Gating Control  */
-  __I  uint32_t RESERVED37[6];  /**< Reserved */
-  __IO uint32_t SCGCCCM;        /**< CRC Module Sleep Mode Clock Gating Control */
-  __I  uint32_t RESERVED38[9];  /**< Reserved */
-  __IO uint32_t SCGCEMAC;       /**< Ethernet MAC Sleep Mode Clock Gating Control */
-  __I  uint32_t RESERVED39[24]; /**< Reserved                                */
-  __IO uint32_t DCGCWD;         /**< WDT Deep-Sleep Mode Clock Gating Control*/
-  __IO uint32_t DCGCTIMER;      /**< GPT Deep-Sleep Mode Clock Gating Control*/
-  __IO uint32_t DCGCGPIO;       /**< GPIO Deep-Sleep Mode Clock Gating
-                                     Control                                 */
-  __IO uint32_t DCGCDMA;        /**< UDMA Deep-Sleep Mode Clock Gating
-                                     Control                                 */
-  __IO uint32_t DCGCEPI;        /**< EPI Deep-Sleep Mode Clock Gating Control */
-  __IO uint32_t DCGCHIB;        /**< HIB Deep-Sleep Mode Clock Gating Control*/
-  __IO uint32_t DCGCUART;       /**< UART Deep-Sleep Mode Clock Gating
-                                     Control                                 */
-  __IO uint32_t DCGCSSI;        /**< SSI Deep-Sleep Mode Clock Gating Control*/
-  __IO uint32_t DCGCI2C;        /**< I2C Deep-Sleep Mode Clock Gating Control*/
-  __I  uint32_t RESERVED40[1];  /**< Reserved                                */
-  __IO uint32_t DCGCUSB;        /**< USB Deep-Sleep Mode Clock Gating Control*/
-  __I  uint32_t RESERVED41[1];  /**< Reserved                                */
-  __IO uint32_t DCGCEPHY;       /**< Ethernet PHY Deep-Sleep Mode Clock Gating Control */
-  __IO uint32_t DCGCCAN;        /**< CAN Deep-Sleep Mode Clock Gating Control*/
-  __IO uint32_t DCGCADC;        /**< ADC Deep-Sleep Mode Clock Gating Control*/
-  __IO uint32_t DCGCACMP;       /**< ACMP Deep-Sleep Mode Clock Gating
-                                     Control                                 */
-  __IO uint32_t DCGCPWM;        /**< PWM Deep-Sleep Mode Clock Gating Control*/
-  __IO uint32_t DCGCQEI;        /**< QEI Deep-Sleep Mode Clock Gating Control*/
-  __I  uint32_t RESERVED42[4];  /**< Reserved                                */
-  __IO uint32_t DCGCEEPROM;     /**< EEPROM Deep-Sleep Mode Clock Gating
-                                     Control                                 */
-  __I  uint32_t RESERVED43[6];  /**< Reserved */
-  __IO uint32_t DCGCCCM;        /**< CRC Module Deep-Sleep Mode Clock Gating Control */
-  __I  uint32_t RESERVED44[9];  /**< Reserved */
-  __IO uint32_t DCGCEMAC;       /**< Ethernet MAC Deep-Sleep Mode Clock Gating Control */
-  __I  uint32_t RESERVED45[24]; /**< Reserved                                */
-  __IO uint32_t PCWD;           /**< Watchdog Timer Power Control       */
-  __IO uint32_t PCTIMER;        /**< 16/32-Bit General-Purpose Timer Power Control       */
-  __IO uint32_t PCGPIO;         /**< General-Purpose Input/Output Power Control      */
-  __IO uint32_t PCDMA;          /**< Micro Direct Memory Access Power Control      */
-  __IO uint32_t PCEPI;          /**< External Peripheral Interface Power Control */
-  __IO uint32_t PCHIB;          /**< Hibernation Power Control       */
-  __IO uint32_t PCUART;         /**< Universal Asynchronous Receiver/Transmitter Power Control                   */
-  __IO uint32_t PCSSI;          /**< Synchronous Serial Interface Power Control       */
-  __IO uint32_t PCI2C;          /**< Inter-Integrated Circuit Power Control       */
-  __I  uint32_t RESERVED46[1];  /**< Reserved                                */
-  __IO uint32_t PCUSB;          /**< Universal Serial Bus Power Control       */
-  __I  uint32_t RESERVED47[1];  /**< Reserved                                */
-  __IO uint32_t PCEPHY;         /**< Ethernet PHY Power Control */
-  __IO uint32_t PCCAN;          /**< Controller Area Network Power Control       */
-  __IO uint32_t PCADC;          /**< Analog-to-Digital Converter Power Control       */
-  __IO uint32_t PCACMP;         /**< Analog Comparator Power Control      */
-  __IO uint32_t PCPWM;          /**< Pulse Width Modulator Power Control       */
-  __IO uint32_t PCQEI;          /**< Quadrature Encoder Interface Power Control       */
-  __I  uint32_t RESERVED48[4];  /**< Reserved                                */
-  __IO uint32_t PCEEPROM;       /**< EEPROM Power Control    */
-  __I  uint32_t RESERVED49[6];  /**< Reserved */
-  __IO uint32_t PCCCM;          /**< CRC Module Power Control */
-  __I  uint32_t RESERVED50[9];  /**< Reserved */
-  __IO uint32_t PCEMAC;         /**< Ethernet MAC Power Control */
-  __I  uint32_t RESERVED51[24]; /**< Reserved */
-  __IO uint32_t PRWD;           /**< WDT Peripheral Ready                    */
-  __IO uint32_t PRTIMER;        /**< GPT Peripheral Ready                    */
-  __IO uint32_t PRGPIO;         /**< GPIO Peripheral Ready                   */
-  __IO uint32_t PRDMA;          /**< UDMA Peripheral Ready                   */
-  __IO uint32_t PREPI;          /**< EPI Peripheral Ready                                */
-  __IO uint32_t PRHIB;          /**< HIB Peripheral Ready                    */
-  __IO uint32_t PRUART;         /**< UART Peripheral Ready                   */
-  __IO uint32_t PRSSI;          /**< SSI Peripheral Ready                    */
-  __IO uint32_t PRI2C;          /**< I2C Peripheral Ready                    */
-  __I  uint32_t RESERVED52[1];  /**< Reserved                                */
-  __IO uint32_t PRUSB;          /**< USB Peripheral Ready                    */
-  __I  uint32_t RESERVED53[1];  /**< Reserved                                */
-  __IO uint32_t PREPHY;         /**< Ethernet PHY Peripheral Ready */
-  __IO uint32_t PRCAN;          /**< CAN Peripheral Ready                    */
-  __IO uint32_t PRADC;          /**< ADC Peripheral Ready                    */
-  __IO uint32_t PRACMP;         /**< ACMP Peripheral Ready                   */
-  __IO uint32_t PRPWM;          /**< PWM Peripheral Ready                    */
-  __IO uint32_t PRQEI;          /**< QEI Peripheral Ready                    */
-  __I  uint32_t RESERVED54[4];  /**< Reserved                                */
-  __IO uint32_t PREEPROM;       /**< EEPROM Peripheral Ready                 */
-  __I  uint32_t RESERVED55[6];  /**< Reserved */
-  __IO uint32_t PRCCM;          /**< CRC Module Peripheral Ready               */
-  __I  uint32_t RESERVED56[9];  /**< Reserved */
-  __IO uint32_t PREMAC;         /**< Ethernet MAC Peripheral Ready */
-} SYSCTL_TypeDef;
-
-/**
- * @brief Universal Asynchronous Receiver/Transmitter
- */
-typedef struct
-{
-  __IO uint32_t DR;             /**< Data                                    */
-  union  {
-    __I  uint32_t RSR;          /**< Receive Status                          */
-    __O  uint32_t ECR;          /**< Error Clear                             */
-  };
-  __I  uint32_t _RESERVED0[4];  /**< Reserved                                */
-  __I  uint32_t FR;             /**< Flag                                    */
-  __I  uint32_t _RESERVED1[1];  /**< Reserved                                */
-  __IO uint32_t ILPR;           /**< IrDA Low-Power Register                 */
-  __IO uint32_t IBRD;           /**< Integer Baud-Rate Divisor               */
-  __IO uint32_t FBRD;           /**< Fractional Baud-Rate Divisor            */
-  __IO uint32_t LCRH;           /**< Line Control                            */
-  __IO uint32_t CTL;            /**< Control                                 */
-  __IO uint32_t IFLS;           /**< Interrupt FIFO Level Select             */
-  __IO uint32_t IM;             /**< Interrupt Mask                          */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
-  __O uint32_t ICR;             /**< Interrupt Clear                         */
-  __IO uint32_t DMACTL;         /**< DMA Control                             */
-  __I  uint32_t _RESERVED2[22]; /**< Reserved                                */
-  __IO uint32_t BIT9ADDR;       /**< 9-Bit Self Address                      */
-  __IO uint32_t BIT9AMASK;      /**< 9-Bit Self Address Mask                 */
-  __I  uint32_t _RESERVED3[965];/**< Reserved                                */
-  __I  uint32_t PP;             /**< Peripheral Properties                   */
-  __I  uint32_t _RESERVED4[1];  /**< Reserved                                */
-  __IO uint32_t CC;             /**< Clock Configuration                     */
-} UART_TypeDef;
-
-/**
- * @brief Micro Direct Memory Access
- */
-typedef struct
-{
-  __IO uint32_t SET;            /**< Set                                     */
-  __O  uint32_t CLR;            /**< Clear                                   */
-} UDMA_SC_t;
-
-typedef struct
-{
-  __IO uint32_t STAT;           /**< Status                                  */
-  __O  uint32_t CFG;            /**< Configuration                           */
-  __IO uint32_t CTLBASE;        /**< Channel Control Base Pointer            */
-  __IO uint32_t ALTBASE;        /**< Alternate Channel Control Base Pointer  */
-  __IO uint32_t WAITSTAT;       /**< Channel Wait-on-Request Status          */
-  __O  uint32_t SWREQ;          /**< Channel Software Request                */
-  UDMA_SC_t USEBURST;           /**< Channel Useburst registers              */
-  UDMA_SC_t REQMASK;            /**< Channel Request Mask registers          */
-  UDMA_SC_t ENA;                /**< Channel Enable registers                */
-  UDMA_SC_t ALT;                /**< Channel Primary Alternate registers     */
-  UDMA_SC_t PRIO;               /**< Channel Priority registers              */
-  __I  uint32_t _RESERVED0[3];  /**< Reserved                                */
-  __IO uint32_t ERRCLR;         /**< Bus Error Clear                         */
-  __I  uint32_t _RESERVED1[300];/**< Reserved                                */
-  __IO uint32_t CHASGN;         /**< Channel Assignment                      */
-  __IO uint32_t CHIS;           /**< Channel Interrupt Status                */
-  __I  uint32_t _RESERVED2[2];  /**< Reserved                                */
-  __IO uint32_t CHMAP[4];       /**< Channel Map Select 0, 1, 2 and 3        */
-} UDMA_TypeDef;
-
-// USB
-
-/**
- * @brief Watchdog Timer
- */
-typedef struct
-{
-  __IO uint32_t LOAD;           /**< Load                                    */
-  __I  uint32_t VALUE;          /**< Value                                   */
-  __IO uint32_t CTL;            /**< Control                                 */
-  __O  uint32_t ICR;            /**< Interrupt Clear                         */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
-  __I  uint32_t _RESERVED0[256];/**< Reserved                                */
-  __IO uint32_t TEST;           /**< Test                                    */
-  __I  uint32_t _RESERVED1[505];/**< Reserved                                */
-  __IO uint32_t LOCK;           /**< Lock                                    */
-} WDG_TypeDef;
-
-/**
- * @brief   Ethernet peripheral
- */
-typedef struct {
-  __IO uint32_t CFG;            /**< Configuration                           */
-  __IO uint32_t FRAMEFLTR;      /**< Frame Filter                            */
-  __IO uint32_t HASHTBLH;       /**< Hash Table High                         */
-  __IO uint32_t HASHTBLL;       /**< Hash Table Low                          */
-  __IO uint32_t MIIADDR;        /**< MII Address                             */
-  __IO uint32_t MIIDATA;        /**< MII Data Register                       */
-  __IO uint32_t FLOWCTL;        /**< Flow Control                            */
-  __IO uint32_t VLANTG;         /**< VLAN Tag                                */
-  __I  uint32_t RESERVED0[1];   /**< Reserved                                */
-  __IO uint32_t STATUS;         /**< Status                                  */
-  __IO uint32_t RWUFF;          /**< Remote Wake-Up Frame Filter             */
-  __IO uint32_t PMTCTLSTAT;     /**< PMT Control and Status Register         */
-  __I  uint32_t RESERVED1[2];   /**< Reserved                                */
-  __IO uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __IO uint32_t IM;             /**< Interrupt Mask                          */
-  __IO uint32_t ADDR0H;         /**< Address 0 High                          */
-  __IO uint32_t ADDR0L;         /**< Address 0 Low Register                  */
-  __IO uint32_t ADDR1H;         /**< Address 1 High                          */
-  __IO uint32_t ADDR1L;         /**< Address 1 Low                           */
-  __IO uint32_t ADDR2H;         /**< Address 2 High                          */
-  __IO uint32_t ADDR2L;         /**< Address 2 Low                           */
-  __IO uint32_t ADDR3H;         /**< Address 3 High                          */
-  __IO uint32_t ADDR3L;         /**< Address 3 Low                           */
-  __I  uint32_t RESERVED2[31];  /**< Reserved                                */
-  __IO uint32_t WDOGTO;         /**< Watchdog Timeout                        */
-  __I  uint32_t RESERVED3[8];   /**< Reserved                                */
-  __IO uint32_t MMCCTRL;        /**< MMC Control                             */
-  __IO uint32_t MMCRXRIS;       /**< MMC Receive Raw Interrupt Status        */
-  __IO uint32_t MMCTXRIS;       /**< MMC Transmit Raw Interrupt Status       */
-  __IO uint32_t MMCRXIM;        /**< MMC Receive Interrupt Mask              */
-  __IO uint32_t MMCTXIM;        /**< MMC Transmit Interrupt Mask             */
-  __I  uint32_t RESERVED4[1];   /**< Reserved                                */
-  __IO uint32_t TXCNTGB;        /**< Transmit Frame Count for Good and Bad
-                                     Frames                                  */
-  __I  uint32_t RESERVED5[12];  /**< Reserved                                */
-  __IO uint32_t TXCNTSCOL;      /**< Transmit Frame Count for Frames
-                                     Transmitted after Single Collision      */
-  __IO uint32_t TXCNTMCOL;      /**< Transmit Frame Count for Frames
-                                     Transmitted after Multiple Collisions   */
-  __I  uint32_t RESERVED6[4];   /**< Reserved                                */
-  __IO uint32_t TXOCTCNTG;      /**< Transmit Octet Count Good               */
-  __I  uint32_t RESERVED7[6];   /**< Reserved                                */
-  __IO uint32_t RXCNTGB;        /**< Receive Frame Count for Good and Bad
-                                     Frames                                  */
-  __I  uint32_t RESERVED8[4];   /**< Reserved                                */
-  __IO uint32_t RXCNTCRCERR;    /**< Receive Frame Count for CRC Error Frames*/
-  __IO uint32_t RXCNTALGNERR;   /**< Receive Frame Count for Alignment Error
-                                     Frames                                  */
-  __I  uint32_t RESERVED9[10];  /**< Reserved                                */
-  __IO uint32_t RXCNTGUNI;      /**< Receive Frame Count for Good Unicast
-                                     Frames                                  */
-  __I  uint32_t RESERVED10[239];/**< Reserved                                */
-  __IO uint32_t VLNINCREP;      /**< VLAN Tag Inclusion or Replacement       */
-  __IO uint32_t VLANHASH;       /**< VLAN Hash Table                         */
-  __I  uint32_t RESERVED11[93]; /**< Reserved                                */
-  __IO uint32_t TIMSTCTRL;      /**< Timestamp Control                       */
-  __IO uint32_t SUBSECINC;      /**< Sub-Second Increment                    */
-  __IO uint32_t TIMSEC;         /**< System Time - Seconds                   */
-  __IO uint32_t TIMNANO;        /**< System Time - Nanoseconds               */
-  __IO uint32_t TIMSECU;        /**< System Time - Seconds Update            */
-  __IO uint32_t TIMNANOU;       /**< System Time - Nanoseconds Update        */
-  __IO uint32_t TIMADD;         /**< Timestamp Addend                        */
-  __IO uint32_t TARGSEC;        /**< Target Time Seconds                     */
-  __IO uint32_t TARGNANO;       /**< Target Time Nanoseconds                 */
-  __IO uint32_t HWORDSEC;       /**< System Time-Higher Word Seconds         */
-  __IO uint32_t TIMSTAT;        /**< Timestamp Status                        */
-  __IO uint32_t PPSCTRL;        /**< PPS Control                             */
-  __I  uint32_t RESERVED12[12]; /**< Reserved                                */
-  __IO uint32_t PPS0INTVL;      /**< PPS0 Interval                           */
-  __IO uint32_t PPS0WIDTH;      /**< PPS0 Width                              */
-  __I  uint32_t RESERVED13[294];/**< Reserved                                */
-  __IO uint32_t DMABUSMOD;      /**< DMA Bus Mode                            */
-  __O  uint32_t TXPOLLD;        /**< Transmit Poll Demand                    */
-  __O  uint32_t RXPOLLD;        /**< Receive Poll Demand                     */
-  __IO uint32_t RXDLADDR;       /**< Receive Descriptor List Address         */
-  __IO uint32_t TXDLADDR;       /**< Transmit Descriptor List Address        */
-  __IO uint32_t DMARIS;         /**< DMA Interrupt Status                    */
-  __IO uint32_t DMAOPMODE;      /**< DMA Operation Mode                      */
-  __IO uint32_t DMAIM;          /**< DMA Interrupt Mask Register             */
-  __IO uint32_t MFBOC;          /**< Missed Frame and Buffer Overflow Counter*/
-  __IO uint32_t RXINTWDT;       /**< Receive Interrupt Watchdog Timer        */
-  __I  uint32_t RESERVED14[8];  /**< Reserved                                */
-  __IO uint32_t HOSTXDESC;      /**< Current Host Transmit Descriptor        */
-  __IO uint32_t HOSRXDESC;      /**< Current Host Receive Descriptor         */
-  __IO uint32_t HOSTXBA;        /**< Current Host Transmit Buffer Address    */
-  __IO uint32_t HOSRXBA;        /**< Current Host Receive Buffer Address     */
-  __I  uint32_t RESERVED15[218];/**< Reserved                                */
-  __IO uint32_t PP;             /**< Peripheral Property Register            */
-  __IO uint32_t PC;             /**< Peripheral Configuration Register       */
-  __IO uint32_t CC;             /**< Clock Configuration Register            */
-  __I  uint32_t RESERVED16[1];  /**< Reserved                                */
-  __I  uint32_t PHYRIS;         /**< PHY Raw Interrupt Status                */
-  __IO uint32_t PHYIM;          /**< PHY Interrupt Mask                      */
-  __IO uint32_t PHYMISC;        /**< PHY Masked Interrupt Status and Clear   */
-} ETH_TypeDef;
-
-/**
- * @}
- */
-
-/**
- * @addtogroup Peripheral_memorymap
- * @{
- */
-
-#define SYSCTL_BASE 0x400FE000
-#define HIB_BASE    0x400FC000
-#define FLASH_BASE  0x400FD000
-#define EEPROM_BASE 0x400AF000
-#define UDMA_BASE   0x400FF000
-#define GPIOA_BASE  0x40058000
-#define GPIOB_BASE  0x40059000
-#define GPIOC_BASE  0x4005A000
-#define GPIOD_BASE  0x4005B000
-#define GPIOE_BASE  0x4005C000
-#define GPIOF_BASE  0x4005D000
-#define GPIOG_BASE  0x4005E000
-#define GPIOH_BASE  0x4005F000
-#define GPIOJ_BASE  0x40060000
-#define GPIOK_BASE  0x40061000
-#define GPIOL_BASE  0x40062000
-#define GPIOM_BASE  0x40063000
-#define GPION_BASE  0x40064000
-#define GPIOP_BASE  0x40065000
-#define GPIOQ_BASE  0x40066000
-#define GPIOR_BASE  0x40067000
-#define GPIOS_BASE  0x40068000
-#define GPIOT_BASE  0x40069000
-#define GPT0_BASE   0x40030000
-#define GPT1_BASE   0x40031000
-#define GPT2_BASE   0x40032000
-#define GPT3_BASE   0x40033000
-#define GPT4_BASE   0x40034000
-#define GPT5_BASE   0x40035000
-#define GPT6_BASE   0x400E0000
-#define GPT7_BASE   0x400E1000
-#define WDT0_BASE   0x40000000
-#define WDT1_BASE   0x40001000
-#define ADC0_BASE   0x40038000
-#define ADC1_BASE   0x40039000
-#define UART0_BASE  0x4000C000
-#define UART1_BASE  0x4000D000
-#define UART2_BASE  0x4000E000
-#define UART3_BASE  0x4000F000
-#define UART4_BASE  0x40010000
-#define UART5_BASE  0x40011000
-#define UART6_BASE  0x40012000
-#define UART7_BASE  0x40013000
-#define SSI0_BASE   0x40008000
-#define SSI1_BASE   0x40009000
-#define SSI2_BASE   0x4000A000
-#define SSI3_BASE   0x4000B000
-#define I2C0_BASE   0x40020000
-#define I2C1_BASE   0x40021000
-#define I2C2_BASE   0x40022000
-#define I2C3_BASE   0x40023000
-#define I2C4_BASE   0x400C0000
-#define I2C5_BASE   0x400C1000
-#define I2C6_BASE   0x400C2000
-#define I2C7_BASE   0x400C3000
-#define I2C8_BASE   0x400B8000
-#define I2C9_BASE   0x400B9000
-#define CAN0_BASE   0x40040000
-#define CAN1_BASE   0x40041000
-// usb
-#define ACMP_BASE   0x4003C000
-#define PWM0_BASE   0x40028000
-#define QEI0_BASE   0x4002C000
-#define QEI1_BASE   0x4002D000
-
-#define ETH_BASE    0x400EC000
-
-/**
- * @}
- */
-
-/** 
- * @addtogroup Peripheral_declaration
- * @{
- */
-
-#define SYSCTL  ((SYSCTL_TypeDef *) SYSCTL_BASE)
-#define HIB     ((HIB_TypeDef *)    HIB_BASE)
-#define FLASH   ((FLASH_TypeDef *)  FLASH_BASE)
-#define EEPROM  ((EEPROM_TypeDef *) EEPROM_BASE)
-#define UDMA    ((UDMA_TypeDef *)   UDMA_BASE)										
-#define GPIOA   ((GPIO_TypeDef *)   GPIOA_BASE)
-#define GPIOB   ((GPIO_TypeDef *)   GPIOB_BASE)
-#define GPIOC   ((GPIO_TypeDef *)   GPIOC_BASE)
-#define GPIOD   ((GPIO_TypeDef *)   GPIOD_BASE)
-#define GPIOE   ((GPIO_TypeDef *)   GPIOE_BASE)
-#define GPIOF   ((GPIO_TypeDef *)   GPIOF_BASE)
-#define GPIOG   ((GPIO_TypeDef *)   GPIOG_BASE)
-#define GPIOH   ((GPIO_TypeDef *)   GPIOH_BASE)
-#define GPIOJ   ((GPIO_TypeDef *)   GPIOJ_BASE)
-#define GPIOK   ((GPIO_TypeDef *)   GPIOK_BASE)
-#define GPIOL   ((GPIO_TypeDef *)   GPIOL_BASE)
-#define GPIOM   ((GPIO_TypeDef *)   GPIOM_BASE)
-#define GPION   ((GPIO_TypeDef *)   GPION_BASE)
-#define GPIOP   ((GPIO_TypeDef *)   GPIOP_BASE)
-#define GPIOQ   ((GPIO_TypeDef *)   GPIOQ_BASE)
-#define GPIOR   ((GPIO_TypeDef *)   GPIOR_BASE)
-#define GPIOS   ((GPIO_TypeDef *)   GPIOS_BASE)
-#define GPIOT   ((GPIO_TypeDef *)   GPIOT_BASE)
-#define GPT0    ((GPT_TypeDef *)    GPT0_BASE)
-#define GPT1    ((GPT_TypeDef *)    GPT1_BASE)
-#define GPT2    ((GPT_TypeDef *)    GPT2_BASE)
-#define GPT3    ((GPT_TypeDef *)    GPT3_BASE)
-#define GPT4    ((GPT_TypeDef *)    GPT4_BASE)
-#define GPT5    ((GPT_TypeDef *)    GPT5_BASE)
-#define GPT6    ((GPT_TypeDef *)    GPT6_BASE)
-#define GPT7    ((GPT_TypeDef *)    GPT7_BASE)
-#define WDT0    ((WDT_TypeDef *)    WDT0_BASE)
-#define WDT1    ((WDT_TypeDef *)    WDT1_BASE)
-#define ADC0    ((ADC_TypeDef*)     ADC0_BASE)
-#define ADC1    ((ADC_TypeDef*)     ADC1_BASE)
-#define UART0   ((UART_TypeDef *)   UART0_BASE)
-#define UART1   ((UART_TypeDef *)   UART1_BASE)
-#define UART2   ((UART_TypeDef *)   UART2_BASE)
-#define UART3   ((UART_TypeDef *)   UART3_BASE)
-#define UART4   ((UART_TypeDef *)   UART4_BASE)
-#define UART5   ((UART_TypeDef *)   UART5_BASE)
-#define UART6   ((UART_TypeDef *)   UART6_BASE)
-#define UART7   ((UART_TypeDef *)   UART7_BASE)
-#define SSI0    ((SSI_TypeDef *)    SSI0_BASE)
-#define SSI1    ((SSI_TypeDef *)    SSI1_BASE)
-#define SSI2    ((SSI_TypeDef *)    SSI2_BASE)
-#define SSI3    ((SSI_TypeDef *)    SSI3_BASE)
-#define I2C0    ((I2C_TypeDef *)    I2C0_BASE)
-#define I2C1    ((I2C_TypeDef *)    I2C1_BASE)
-#define I2C2    ((I2C_TypeDef *)    I2C2_BASE)
-#define I2C3    ((I2C_TypeDef *)    I2C3_BASE)
-#define I2C4    ((I2C_TypeDef *)    I2C4_BASE)
-#define I2C5    ((I2C_TypeDef *)    I2C5_BASE)
-#define I2C6    ((I2C_TypeDef *)    I2C6_BASE)
-#define I2C7    ((I2C_TypeDef *)    I2C7_BASE)
-#define I2C8    ((I2C_TypeDef *)    I2C8_BASE)
-#define I2C9    ((I2C_TypeDef *)    I2C9_BASE)
-#define CAN0    ((CAN_TypeDef *)    CAN0_BASE)
-#define CAN1    ((CAN_TypeDef *)    CAN1_BASE)
-// usb
-#define ACMP    ((ACMP_TypeDef *)   ACMP_BASE)
-#define PWM0    ((PWM_TypeDef *)    PWM0_BASE)
-#define QEI0    ((QEI_TypeDef *)    QEI0_BASE)
-#define QEI1    ((QEI_TypeDef *)    QEI1_BASE)
-
-#define ETH     ((ETH_TypeDef *)  ETH_BASE)
-
-/**
- * @}
- */
-
-#endif /* __TM4C129x_H */
-
-/**
- * @}
- */
- 
-/**
- * @}
- */
diff --git a/os/hal/src/hal_community.c b/os/hal/src/hal_community.c
index 8a39bf1..ad05fe4 100644
--- a/os/hal/src/hal_community.c
+++ b/os/hal/src/hal_community.c
@@ -80,6 +80,10 @@ void halCommunityInit(void) {
 #if HAL_USE_QEI || defined(__DOXYGEN__)

   qeiInit();

 #endif

+

+#if HAL_USE_COMP || defined(__DOXYGEN__)

+  compInit();

+#endif

 }

 

 #endif /* HAL_USE_COMMUNITY */

diff --git a/os/hal/src/hal_comp.c b/os/hal/src/hal_comp.c
new file mode 100644
index 0000000..abc0fad
--- /dev/null
+++ b/os/hal/src/hal_comp.c
@@ -0,0 +1,155 @@
+/*
+    ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio
+              Copyright (C) 2017 Fabien Poussin (fabien.poussin (at) google's mail)
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    hal_comp.c
+ * @brief   COMP Driver code.
+ *
+ * @addtogroup COMP
+ * @{
+ */
+
+#include "hal_comp.h"
+
+#if HAL_USE_COMP || defined(__DOXYGEN__)
+
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   COMP Driver initialization.
+ * @note    This function is implicitly invoked by @p halInit(), there is
+ *          no need to explicitly initialize the driver.
+ *
+ * @init
+ */
+void compInit(void) {
+
+  comp_lld_init();
+}
+
+/**
+ * @brief   Initializes the standard part of a @p COMPDriver structure.
+ *
+ * @param[out] compp     pointer to the @p COMPDriver object
+ *
+ * @init
+ */
+void compObjectInit(COMPDriver *compp) {
+
+  compp->state  = COMP_STOP;
+  compp->config = NULL;
+}
+
+/**
+ * @brief   Configures and activates the COMP peripheral.
+ *
+ * @param[in] compp      pointer to the @p COMPDriver object
+ * @param[in] config    pointer to the @p COMPConfig object
+ *
+ * @api
+ */
+void compStart(COMPDriver *compp, const COMPConfig *config) {
+
+  osalDbgCheck((compp != NULL) && (config != NULL));
+
+  osalSysLock();
+  osalDbgAssert((compp->state == COMP_STOP) || (compp->state == COMP_READY),
+              "invalid state");
+  compp->config = config;
+  comp_lld_start(compp);
+  compp->state = COMP_READY;
+  osalSysUnlock();
+}
+
+/**
+ * @brief   Deactivates the COMP peripheral.
+ *
+ * @param[in] compp      pointer to the @p COMPDriver object
+ *
+ * @api
+ */
+void compStop(COMPDriver *compp) {
+
+  osalDbgCheck(compp != NULL);
+
+  osalSysLock();
+  osalDbgAssert((compp->state == COMP_STOP) || (compp->state == COMP_READY),
+              "invalid state");
+  comp_lld_stop(compp);
+  compp->state = COMP_STOP;
+  osalSysUnlock();
+}
+
+/**
+ * @brief   Activates the comparator.
+ *
+ * @param[in] compp      pointer to the @p COMPDriver object
+ *
+ * @api
+ */
+void compEnable(COMPDriver *compp) {
+
+  osalDbgCheck(compp != NULL);
+
+  osalSysLock();
+  osalDbgAssert(compp->state == COMP_READY, "invalid state");
+  comp_lld_enable(compp);
+  compp->state = COMP_ACTIVE;
+  osalSysUnlock();
+}
+
+/**
+ * @brief   Deactivates the comparator.
+ *
+ * @param[in] compp      pointer to the @p COMPDriver object
+ *
+ * @api
+ */
+void compDisable(COMPDriver *compp) {
+
+  osalDbgCheck(compp != NULL);
+
+  osalSysLock();
+  osalDbgAssert((compp->state == COMP_READY) || (compp->state == COMP_ACTIVE),
+             "invalid state");
+  comp_lld_disable(compp);
+  compp->state = COMP_READY;
+  osalSysUnlock();
+}
+
+#endif /* HAL_USE_COMP */
+
+/** @} */
diff --git a/os/hal/src/hal_ee24xx.c b/os/hal/src/hal_ee24xx.c
index 632ffbb..725258c 100644
--- a/os/hal/src/hal_ee24xx.c
+++ b/os/hal/src/hal_ee24xx.c
@@ -105,7 +105,7 @@ static systime_t calc_timeout(I2CDriver *i2cp, size_t txbytes, size_t rxbytes) {
   tmo = ((txbytes + rxbytes + 1) * bitsinbyte * 1000);
   tmo /= EEPROM_I2C_CLOCK;
   tmo += 10; /* some additional milliseconds to be safer */
-  return MS2ST(tmo);
+  return TIME_MS2I(tmo);
 }
 
 /**
@@ -202,7 +202,7 @@ static void __fitted_write(void *ip, const uint8_t *data, size_t len, uint32_t *
 
   msg_t status = MSG_RESET;
 
-  osalDbgAssert(len != 0, "something broken in hi level part");
+  osalDbgAssert(len > 0, "len must be greater than 0");
 
   status = eeprom_write(((I2CEepromFileStream *)ip)->cfg,
                         eepfs_getposition(ip), data, len);
@@ -214,15 +214,15 @@ static void __fitted_write(void *ip, const uint8_t *data, size_t len, uint32_t *
 
 /**
  * @brief     Write data to EEPROM.
- * @details   Only one EEPROM page can be written at once. So fucntion
+ * @details   Only one EEPROM page can be written at once. So function
  *            splits large data chunks in small EEPROM transactions if needed.
- * @note      To achieve the maximum effectivity use write operations
+ * @note      To achieve the maximum efficiency use write operations
  *            aligned to EEPROM page boundaries.
  */
 static size_t write(void *ip, const uint8_t *bp, size_t n) {
 
-  size_t   len = 0;     /* bytes to be written at one trasaction */
-  uint32_t written; /* total bytes successfully written */
+  size_t   len = 0;      /* bytes to be written per transaction */
+  uint32_t written = 0;  /* total bytes successfully written */
   uint16_t pagesize;
   uint32_t firstpage;
   uint32_t lastpage;
@@ -242,12 +242,10 @@ static size_t write(void *ip, const uint8_t *bp, size_t n) {
   lastpage  = (((EepromFileStream *)ip)->cfg->barrier_low +
                eepfs_getposition(ip) + n - 1) / pagesize;
 
-  written = 0;
-  /* data fitted in single page */
+  /* data fits in single page */
   if (firstpage == lastpage) {
     len = n;
     __fitted_write(ip, bp, len, &written);
-    bp += len;
     return written;
   }
 
@@ -255,17 +253,19 @@ static size_t write(void *ip, const uint8_t *bp, size_t n) {
     /* write first piece of data to first page boundary */
     len =  ((firstpage + 1) * pagesize) - eepfs_getposition(ip);
     len -= ((EepromFileStream *)ip)->cfg->barrier_low;
-    __fitted_write(ip, bp, len, &written);
+    if (__fitted_write(ip, bp, len, &written) != MSG_OK)
+      return written;
     bp += len;
 
-    /* now writes blocks at a size of pages (may be no one) */
+    /* now write page sized blocks (zero or more) */
     while ((n - written) > pagesize) {
       len = pagesize;
-      __fitted_write(ip, bp, len, &written);
+      if (__fitted_write(ip, bp, len, &written) != MSG_OK)
+        return written;
       bp += len;
     }
 
-    /* wrtie tail */
+    /* write tail */
     len = n - written;
     if (len == 0)
       return written;
diff --git a/os/hal/src/hal_ee25xx.c b/os/hal/src/hal_ee25xx.c
index 102aef8..8c35976 100644
--- a/os/hal/src/hal_ee25xx.c
+++ b/os/hal/src/hal_ee25xx.c
@@ -277,7 +277,7 @@ static msg_t __fitted_write(void *ip, const uint8_t *data, size_t len, uint32_t
 
   msg_t status = MSG_RESET;
 
-  osalDbgAssert(len != 0, "something broken in hi level part");
+  osalDbgAssert(len > 0, "len must be greater than 0");
 
   status = ll_eeprom_write(((SPIEepromFileStream *)ip)->cfg,
                            eepfs_getposition(ip), data, len);
@@ -290,15 +290,15 @@ static msg_t __fitted_write(void *ip, const uint8_t *data, size_t len, uint32_t
 
 /**
  * @brief     Write data to EEPROM.
- * @details   Only one EEPROM page can be written at once. So fucntion
+ * @details   Only one EEPROM page can be written at once. So function
  *            splits large data chunks in small EEPROM transactions if needed.
- * @note      To achieve the maximum effectivity use write operations
+ * @note      To achieve the maximum efficiency use write operations
  *            aligned to EEPROM page boundaries.
  */
 static size_t write(void *ip, const uint8_t *bp, size_t n) {
 
-  size_t   len = 0;     /* bytes to be written at one trasaction */
-  uint32_t written; /* total bytes successfully written */
+  size_t   len = 0;      /* bytes to be written per transaction */
+  uint32_t written = 0;  /* total bytes successfully written */
   uint16_t pagesize;
   uint32_t firstpage;
   uint32_t lastpage;
@@ -318,32 +318,30 @@ static size_t write(void *ip, const uint8_t *bp, size_t n) {
   firstpage = (cfg->barrier_low + eepfs_getposition(ip)) / pagesize;
   lastpage  = ((cfg->barrier_low + eepfs_getposition(ip) + n) - 1) / pagesize;
 
-  written = 0;
-  /* data fitted in single page */
+  /* data fits in single page */
   if (firstpage == lastpage) {
     len = n;
     __fitted_write(ip, bp, len, &written);
-    bp += len;
     return written;
   }
+  
   else {
     /* write first piece of data to first page boundary */
     len =  ((firstpage + 1) * pagesize) - eepfs_getposition(ip);
     len -= cfg->barrier_low;
-    __fitted_write(ip, bp, len, &written);
+    if (__fitted_write(ip, bp, len, &written) != MSG_OK)
+      return written;
     bp += len;
 
-    /* now writes blocks at a size of pages (may be no one) */
+    /* now write page sized blocks (zero or more) */
     while ((n - written) > pagesize) {
       len = pagesize;
-      if (__fitted_write(ip, bp, len, &written) != MSG_OK) // Fixed: Would increase bp forever and crash in case of timeouts...
+      if (__fitted_write(ip, bp, len, &written) != MSG_OK)
         return written;
-
       bp += len;
     }
 
-
-    /* wrtie tail */
+    /* write tail */
     len = n - written;
     if (len == 0)
       return written;
diff --git a/os/hal/src/hal_nand.c b/os/hal/src/hal_nand.c
index 24dd6de..a2101d6 100644
--- a/os/hal/src/hal_nand.c
+++ b/os/hal/src/hal_nand.c
@@ -80,16 +80,13 @@ static void pagesize_check(size_t page_data_size) {
  */
 static void calc_addr(const NANDConfig *cfg, uint32_t block, uint32_t page,
                       uint32_t page_offset, uint8_t *addr, size_t addr_len) {
-  size_t i = 0;
-  uint32_t row = 0;
+  size_t i;
+  uint32_t row;
 
-  /* Incorrect buffer length.*/
   osalDbgCheck(cfg->rowcycles + cfg->colcycles == addr_len);
   osalDbgCheck((block < cfg->blocks) && (page < cfg->pages_per_block) &&
              (page_offset < cfg->page_data_size + cfg->page_spare_size));
 
-  /* convert address to NAND specific */
-  memset(addr, 0, addr_len);
   row = (block * cfg->pages_per_block) + page;
   for (i=0; i<cfg->colcycles; i++){
     addr[i] = page_offset & 0xFF;
@@ -115,17 +112,14 @@ static void calc_addr(const NANDConfig *cfg, uint32_t block, uint32_t page,
  */
 static void calc_blk_addr(const NANDConfig *cfg, uint32_t block,
                           uint8_t *addr, size_t addr_len) {
-  size_t i = 0;
-  uint32_t row = 0;
+  size_t i;
+  uint32_t row;
 
-  /* Incorrect buffer length.*/
-  osalDbgCheck(cfg->rowcycles == addr_len);
-  osalDbgCheck((block < cfg->blocks));
+  osalDbgCheck(cfg->rowcycles == addr_len); /* Incorrect buffer length  */
+  osalDbgCheck(block < cfg->blocks);        /* Overflow                 */
 
-  /* convert address to NAND specific */
-  memset(addr, 0, addr_len);
   row = block * cfg->pages_per_block;
-  for (i=0; i<addr_len; i++){
+  for (i=0; i<addr_len; i++) {
     addr[i] = row & 0xFF;
     row = row >> 8;
   }
@@ -145,12 +139,13 @@ static void calc_blk_addr(const NANDConfig *cfg, uint32_t block,
  */
 static bool read_is_block_bad(NANDDriver *nandp, size_t block) {
 
-  if (0xFF != nandReadBadMark(nandp, block, 0))
-    return true;
-  if (0xFF != nandReadBadMark(nandp, block, 1))
-    return true;
+  uint16_t badmark0 = nandReadBadMark(nandp, block, 0);
+  uint16_t badmark1 = nandReadBadMark(nandp, block, 1);
 
-  return false;
+  if ((0xFFFF != badmark0) || (0xFFFF != badmark1))
+    return true;
+  else
+    return false;
 }
 
 /**
@@ -235,6 +230,7 @@ void nandStart(NANDDriver *nandp, const NANDConfig *config, bitmap_t *bb_map) {
   pagesize_check(nandp->config->page_data_size);
   nand_lld_start(nandp);
   nandp->state = NAND_READY;
+  nand_lld_reset(nandp);
 
   if (NULL != bb_map) {
     nandp->bb_map = bb_map;
@@ -265,24 +261,24 @@ void nandStop(NANDDriver *nandp) {
  * @param[in] nandp         pointer to the @p NANDDriver object
  * @param[in] block         block number
  * @param[in] page          page number related to begin of block
- * @param[out] data         buffer to store data
- * @param[in] datalen       length of data buffer
+ * @param[out] data         buffer to store data, half word aligned
+ * @param[in] datalen       length of data buffer in bytes, half word aligned
  *
  * @api
  */
 void nandReadPageWhole(NANDDriver *nandp, uint32_t block, uint32_t page,
-                       uint8_t *data, size_t datalen) {
+                       void *data, size_t datalen) {
 
   const NANDConfig *cfg = nandp->config;
-  uint8_t addrbuf[8];
-  size_t addrlen = cfg->rowcycles + cfg->colcycles;
+  const size_t addrlen = cfg->rowcycles + cfg->colcycles;
+  uint8_t addr[addrlen];
 
   osalDbgCheck((nandp != NULL) && (data != NULL));
   osalDbgCheck((datalen <= (cfg->page_data_size + cfg->page_spare_size)));
   osalDbgAssert(nandp->state == NAND_READY, "invalid state");
 
-  calc_addr(cfg, block, page, 0, addrbuf, addrlen);
-  nand_lld_read_data(nandp, data, datalen, addrbuf, addrlen, NULL);
+  calc_addr(cfg, block, page, 0, addr, addrlen);
+  nand_lld_read_data(nandp, data, datalen, addr, addrlen, NULL);
 }
 
 /**
@@ -291,20 +287,20 @@ void nandReadPageWhole(NANDDriver *nandp, uint32_t block, uint32_t page,
  * @param[in] nandp         pointer to the @p NANDDriver object
  * @param[in] block         block number
  * @param[in] page          page number related to begin of block
- * @param[in] data          buffer with data to be written
- * @param[in] datalen       length of data buffer
+ * @param[in] data          buffer with data to be written, half word aligned
+ * @param[in] datalen       length of data buffer in bytes, half word aligned
  *
  * @return    The operation status reported by NAND IC (0x70 command).
  *
  * @api
  */
 uint8_t nandWritePageWhole(NANDDriver *nandp, uint32_t block, uint32_t page,
-                           const uint8_t *data, size_t datalen) {
+                           const void *data, size_t datalen) {
 
   uint8_t retval;
   const NANDConfig *cfg = nandp->config;
-  uint8_t addr[8];
-  size_t addrlen = cfg->rowcycles + cfg->colcycles;
+  const size_t addrlen = cfg->rowcycles + cfg->colcycles;
+  uint8_t addr[addrlen];
 
   osalDbgCheck((nandp != NULL) && (data != NULL));
   osalDbgCheck((datalen <= (cfg->page_data_size + cfg->page_spare_size)));
@@ -321,25 +317,25 @@ uint8_t nandWritePageWhole(NANDDriver *nandp, uint32_t block, uint32_t page,
  * @param[in] nandp         pointer to the @p NANDDriver object
  * @param[in] block         block number
  * @param[in] page          page number related to begin of block
- * @param[out] data         buffer to store data
- * @param[in] datalen       length of data buffer
+ * @param[out] data         buffer to store data, half word aligned
+ * @param[in] datalen       length of data buffer in bytes, half word aligned
  * @param[out] ecc          pointer to calculated ECC. Ignored when NULL.
  *
  * @api
  */
 void nandReadPageData(NANDDriver *nandp, uint32_t block, uint32_t page,
-                         uint8_t *data, size_t datalen, uint32_t *ecc) {
+                         void *data, size_t datalen, uint32_t *ecc) {
 
   const NANDConfig *cfg = nandp->config;
-  uint8_t addrbuf[8];
-  size_t addrlen = cfg->rowcycles + cfg->colcycles;
+  const size_t addrlen = cfg->rowcycles + cfg->colcycles;
+  uint8_t addr[addrlen];
 
   osalDbgCheck((nandp != NULL) && (data != NULL));
   osalDbgCheck((datalen <= cfg->page_data_size));
   osalDbgAssert(nandp->state == NAND_READY, "invalid state");
 
-  calc_addr(cfg, block, page, 0, addrbuf, addrlen);
-  nand_lld_read_data(nandp, data, datalen, addrbuf, addrlen, ecc);
+  calc_addr(cfg, block, page, 0, addr, addrlen);
+  nand_lld_read_data(nandp, data, datalen, addr, addrlen, ecc);
 }
 
 /**
@@ -348,8 +344,8 @@ void nandReadPageData(NANDDriver *nandp, uint32_t block, uint32_t page,
  * @param[in] nandp         pointer to the @p NANDDriver object
  * @param[in] block         block number
  * @param[in] page          page number related to begin of block
- * @param[in] data          buffer with data to be written
- * @param[in] datalen       length of data buffer
+ * @param[in] data          buffer with data to be written, half word aligned
+ * @param[in] datalen       length of data buffer in bytes, half word aligned
  * @param[out] ecc          pointer to calculated ECC. Ignored when NULL.
  *
  * @return    The operation status reported by NAND IC (0x70 command).
@@ -357,12 +353,12 @@ void nandReadPageData(NANDDriver *nandp, uint32_t block, uint32_t page,
  * @api
  */
 uint8_t nandWritePageData(NANDDriver *nandp, uint32_t block, uint32_t page,
-                          const uint8_t *data, size_t datalen, uint32_t *ecc) {
+                          const void *data, size_t datalen, uint32_t *ecc) {
 
   uint8_t retval;
   const NANDConfig *cfg = nandp->config;
-  uint8_t addr[8];
-  size_t addrlen = cfg->rowcycles + cfg->colcycles;
+  const size_t addrlen = cfg->rowcycles + cfg->colcycles;
+  uint8_t addr[addrlen];
 
   osalDbgCheck((nandp != NULL) && (data != NULL));
   osalDbgCheck((datalen <= cfg->page_data_size));
@@ -379,17 +375,17 @@ uint8_t nandWritePageData(NANDDriver *nandp, uint32_t block, uint32_t page,
  * @param[in] nandp         pointer to the @p NANDDriver object
  * @param[in] block         block number
  * @param[in] page          page number related to begin of block
- * @param[out] spare        buffer to store data
- * @param[in] sparelen      length of data buffer
+ * @param[out] spare        buffer to store data, half word aligned
+ * @param[in] sparelen      length of data buffer in bytes, half word aligned
  *
  * @api
  */
 void nandReadPageSpare(NANDDriver *nandp, uint32_t block, uint32_t page,
-                       uint8_t *spare, size_t sparelen) {
+                       void *spare, size_t sparelen) {
 
   const NANDConfig *cfg = nandp->config;
-  uint8_t addr[8];
-  size_t addrlen = cfg->rowcycles + cfg->colcycles;
+  const size_t addrlen = cfg->rowcycles + cfg->colcycles;
+  uint8_t addr[addrlen];
 
   osalDbgCheck((NULL != spare) && (nandp != NULL));
   osalDbgCheck(sparelen <= cfg->page_spare_size);
@@ -405,28 +401,26 @@ void nandReadPageSpare(NANDDriver *nandp, uint32_t block, uint32_t page,
  * @param[in] nandp         pointer to the @p NANDDriver object
  * @param[in] block         block number
  * @param[in] page          page number related to begin of block
- * @param[in] spare         buffer with spare data to be written
- * @param[in] sparelen      length of data buffer
+ * @param[in] spare         buffer with spare data to be written, half word aligned
+ * @param[in] sparelen      length of data buffer in bytes, half word aligned
  *
  * @return    The operation status reported by NAND IC (0x70 command).
  *
  * @api
  */
 uint8_t nandWritePageSpare(NANDDriver *nandp, uint32_t block, uint32_t page,
-                           const uint8_t *spare, size_t sparelen) {
+                           const void *spare, size_t sparelen) {
 
-  uint8_t retVal;
   const NANDConfig *cfg = nandp->config;
-  uint8_t addr[8];
-  size_t addrlen = cfg->rowcycles + cfg->colcycles;
+  const size_t addrlen = cfg->rowcycles + cfg->colcycles;
+  uint8_t addr[addrlen];
 
   osalDbgCheck((NULL != spare) && (nandp != NULL));
   osalDbgCheck(sparelen <= cfg->page_spare_size);
   osalDbgAssert(nandp->state == NAND_READY, "invalid state");
 
   calc_addr(cfg, block, page, cfg->page_data_size, addr, addrlen);
-  retVal = nand_lld_write_data(nandp, spare, sparelen, addr, addrlen, NULL);
-  return retVal;
+  return nand_lld_write_data(nandp, spare, sparelen, addr, addrlen, NULL);
 }
 
 /**
@@ -439,10 +433,10 @@ uint8_t nandWritePageSpare(NANDDriver *nandp, uint32_t block, uint32_t page,
  */
 void nandMarkBad(NANDDriver *nandp, uint32_t block) {
 
-  uint8_t bb_mark[2] = {0, 0};
+  uint16_t bb_mark = 0;
 
-  nandWritePageSpare(nandp, block, 0, bb_mark, sizeof(bb_mark));
-  nandWritePageSpare(nandp, block, 1, bb_mark, sizeof(bb_mark));
+  nandWritePageSpare(nandp, block, 0, &bb_mark, sizeof(bb_mark));
+  nandWritePageSpare(nandp, block, 1, &bb_mark, sizeof(bb_mark));
 
   if (NULL != nandp->bb_map)
     bitmapSet(nandp->bb_map, block);
@@ -459,11 +453,11 @@ void nandMarkBad(NANDDriver *nandp, uint32_t block) {
  *
  * @api
  */
-uint8_t nandReadBadMark(NANDDriver *nandp, uint32_t block, uint32_t page) {
-  uint8_t bb_mark[1];
+uint16_t nandReadBadMark(NANDDriver *nandp, uint32_t block, uint32_t page) {
+  uint16_t bb_mark;
 
-  nandReadPageSpare(nandp, block, page, bb_mark, sizeof(bb_mark));
-  return bb_mark[0];
+  nandReadPageSpare(nandp, block, page, &bb_mark, sizeof(bb_mark));
+  return bb_mark;
 }
 
 /**
@@ -478,17 +472,15 @@ uint8_t nandReadBadMark(NANDDriver *nandp, uint32_t block, uint32_t page) {
  */
 uint8_t nandErase(NANDDriver *nandp, uint32_t block) {
 
-  uint8_t retVal;
   const NANDConfig *cfg = nandp->config;
-  uint8_t addr[4];
-  size_t addrlen = cfg->rowcycles;
+  const size_t addrlen = cfg->rowcycles;
+  uint8_t addr[addrlen];
 
   osalDbgCheck(nandp != NULL);
   osalDbgAssert(nandp->state == NAND_READY, "invalid state");
 
   calc_blk_addr(cfg, block, addr, addrlen);
-  retVal = nand_lld_erase(nandp, addr, addrlen);
-  return retVal;
+  return nand_lld_erase(nandp, addr, addrlen);
 }
 
 /**
diff --git a/os/hal/src/hal_onewire.c b/os/hal/src/hal_onewire.c
index a93eec0..06e63e6 100644
--- a/os/hal/src/hal_onewire.c
+++ b/os/hal/src/hal_onewire.c
@@ -46,7 +46,7 @@ on every timer overflow event.
  */
 
 /**
- * @file    onewire.c
+ * @file    hal_onewire.c
  * @brief   1-wire Driver code.
  *
  * @addtogroup onewire
@@ -251,7 +251,6 @@ static void ow_write_bit_I(onewireDriver *owp, ioline_t bit) {
 static void ow_reset_cb(PWMDriver *pwmp, onewireDriver *owp) {
 
   owp->reg.slave_present = (PAL_LOW == ow_read_bit(owp));
-
   osalSysLockFromISR();
   pwmDisableChannelI(pwmp, owp->config->sample_channel);
   osalThreadResumeI(&owp->thread, MSG_OK);
@@ -661,7 +660,7 @@ bool onewireReset(onewireDriver *owp) {
   pwmcfg->channels[mch].callback = NULL;
   pwmcfg->channels[mch].mode = owp->config->pwmmode;
   pwmcfg->channels[sch].callback = pwm_reset_cb;
-  pwmcfg->channels[sch].mode = PWM_OUTPUT_ACTIVE_LOW;
+  pwmcfg->channels[sch].mode = PWM_OUTPUT_DISABLED;
 
   ow_bus_active(owp);
 
@@ -680,7 +679,7 @@ bool onewireReset(onewireDriver *owp) {
 }
 
 /**
- * @brief     Read some bites from slave device.
+ * @brief     Read some bytes from slave device.
  *
  * @param[in] owp       pointer to the @p onewireDriver object
  * @param[out] rxbuf    pointer to the buffer for read data
@@ -714,7 +713,7 @@ void onewireRead(onewireDriver *owp, uint8_t *rxbuf, size_t rxbytes) {
   pwmcfg->channels[mch].callback = NULL;
   pwmcfg->channels[mch].mode = owp->config->pwmmode;
   pwmcfg->channels[sch].callback = pwm_read_bit_cb;
-  pwmcfg->channels[sch].mode = PWM_OUTPUT_ACTIVE_LOW;
+  pwmcfg->channels[sch].mode = PWM_OUTPUT_DISABLED;
 
   ow_bus_active(owp);
   osalSysLock();
@@ -728,7 +727,7 @@ void onewireRead(onewireDriver *owp, uint8_t *rxbuf, size_t rxbytes) {
 }
 
 /**
- * @brief     Read some bites from slave device.
+ * @brief     Write some bytes to slave device.
  *
  * @param[in] owp           pointer to the @p onewireDriver object
  * @param[in] txbuf         pointer to the buffer with data to be written
@@ -848,7 +847,7 @@ size_t onewireSearchRom(onewireDriver *owp, uint8_t *result,
     pwmcfg->channels[mch].callback = NULL;
     pwmcfg->channels[mch].mode = owp->config->pwmmode;
     pwmcfg->channels[sch].callback = pwm_search_rom_cb;
-    pwmcfg->channels[sch].mode = PWM_OUTPUT_ACTIVE_LOW;
+    pwmcfg->channels[sch].mode = PWM_OUTPUT_DISABLED;
 
     ow_bus_active(owp);
     osalSysLock();
@@ -882,7 +881,7 @@ size_t onewireSearchRom(onewireDriver *owp, uint8_t *result,
  * Include test code (if enabled).
  */
 #if ONEWIRE_SYNTH_SEARCH_TEST
-#include "search_rom_synth.c"
+#include "synth_searchrom.c"
 #endif
 
 #endif /* HAL_USE_ONEWIRE */
diff --git a/os/hal/src/hal_qei.c b/os/hal/src/hal_qei.c
index a2b7303..9b084f7 100644
--- a/os/hal/src/hal_qei.c
+++ b/os/hal/src/hal_qei.c
@@ -42,6 +42,92 @@
 /* Driver local functions.                                                   */

 /*===========================================================================*/

 

+/**

+ * @brief   Helper for correclty handling overflow/underflow

+ *

+ * @details Underflow/overflow will be handled according to mode:

+ *          QEI_OVERFLOW_WRAP:    counter value will wrap around.

+ *          QEI_OVERFLOW_DISCARD: counter will not change

+ *          QEI_OVERFLOW_MINMAX:  counter will be updated upto min or max.

+ *

+ * @note    This function is for use by low level driver.

+ *

+ * @param[in,out] count counter value

+ * @param[in,out] delta adjustment value

+ * @param[in]     min   minimum allowed value for counter

+ * @param[in]     max   maximum allowed value for counter

+ * @param[in]     mode  how to handle overflow

+ *

+ * @return        true if counter underflow/overflow occured or

+ *                was due to occur

+ *

+ */

+static inline

+bool qei_adjust_count(qeicnt_t *count, qeidelta_t *delta,

+		      qeicnt_t min, qeicnt_t max, qeioverflow_t mode) {

+  /* For information on signed integer overflow see:

+   * https://www.securecoding.cert.org/confluence/x/RgE

+   */

+

+  /* Get values */

+  const qeicnt_t   _count = *count;

+  const qeidelta_t _delta = *delta;

+

+  /* Overflow operation

+   */

+  if ((_delta > 0) && (_count > (max - _delta))) {

+    switch(mode) {

+    case QEI_OVERFLOW_WRAP:

+      *delta = 0;

+      *count = (min + (_count - (max - _delta))) - 1;

+      break;

+#if QEI_USE_OVERFLOW_DISCARD == TRUE

+    case QEI_OVERFLOW_DISCARD:

+      *delta = _delta;

+      *count = _count;

+      break;

+#endif

+#if QEI_USE_OVERFLOW_MINMAX == TRUE

+    case QEI_OVERFLOW_MINMAX:

+      *delta = _count - (max - _delta);

+      *count = max;

+      break;

+#endif

+    }

+    return true;

+    

+ /* Underflow operation

+  */

+  } else if ((_delta < 0) && (_count < (min - _delta))) {

+    switch(mode) {

+    case QEI_OVERFLOW_WRAP:

+      *delta = 0;

+      *count = (max + (_count - (min - _delta))) + 1;

+    break;

+#if QEI_USE_OVERFLOW_DISCARD == TRUE

+    case QEI_OVERFLOW_DISCARD:

+      *delta = _delta;

+      *count = _count;

+      break;

+#endif

+#if QEI_USE_OVERFLOW_MINMAX == TRUE

+    case QEI_OVERFLOW_MINMAX:

+      *delta = _count - (min - _delta);

+      *count = min;

+      break;

+#endif

+    }

+    return true;

+

+  /* Normal operation

+   */

+  } else {

+    *delta = 0;

+    *count = _count + _delta;

+    return false;

+  }

+}

+

 /*===========================================================================*/

 /* Driver exported functions.                                                */

 /*===========================================================================*/

@@ -168,6 +254,81 @@ qeicnt_t qeiGetCount(QEIDriver *qeip) {
 }

 

 /**

+ * @brief   Set counter value.

+ *

+ * @param[in] qeip      pointer to the @p QEIDriver object.

+ * @param[in] value     the new counter value.

+ *

+ * @api

+ */

+void qeiSetCount(QEIDriver *qeip, qeicnt_t value) {

+  osalDbgCheck(qeip != NULL);

+  osalDbgAssert((qeip->state == QEI_READY) || (qeip->state == QEI_ACTIVE),

+		"invalid state");

+

+  osalSysLock();

+  qei_lld_set_count(qeip, value);

+  osalSysUnlock();

+}

+

+/**

+ * @brief   Adjust the counter by delta.

+ *

+ * @param[in] qeip      pointer to the @p QEIDriver object.

+ * @param[in] delta     the adjustement value.

+ * @return              the remaining delta (can occur during overflow).

+ *

+ * @api

+ */

+qeidelta_t qeiAdjust(QEIDriver *qeip, qeidelta_t delta) {

+  osalDbgCheck(qeip != NULL);

+  osalDbgAssert((qeip->state == QEI_ACTIVE), "invalid state");

+

+  osalSysLock();

+  delta = qeiAdjustI(qeip, delta);

+  osalSysUnlock();

+

+  return delta;

+}

+

+/**

+ * @brief   Adjust the counter by delta.

+ *

+ * @param[in] qeip      pointer to the @p QEIDriver object.

+ * @param[in] delta     the adjustement value.

+ * @return              the remaining delta (can occur during overflow).

+ *

+ * @api

+ */

+qeidelta_t qeiAdjustI(QEIDriver *qeip, qeidelta_t delta) {

+  /* Get boundaries */

+  qeicnt_t min = QEI_COUNT_MIN;

+  qeicnt_t max = QEI_COUNT_MAX;

+  if (qeip->config->min != qeip->config->max) {

+    min = qeip->config->min;

+    max = qeip->config->max;

+  }

+

+  /* Get counter */

+  qeicnt_t count = qei_lld_get_count(qeip);

+  

+  /* Adjust counter value */

+  bool overflowed = qei_adjust_count(&count, &delta,

+				     min, max, qeip->config->overflow);

+

+  /* Notify for value change */

+  qei_lld_set_count(qeip, count);

+

+  /* Notify for overflow (passing the remaining delta) */

+  if (overflowed && qeip->config->overflow_cb)

+    qeip->config->overflow_cb(qeip, delta);

+

+  /* Remaining delta */

+  return delta;

+}

+

+

+/**

  * @brief   Returns the counter delta from last reading.

  *

  * @param[in] qeip      pointer to the @p QEIDriver object

@@ -203,7 +364,7 @@ qeidelta_t qeiUpdateI(QEIDriver *qeip) {
                 "invalid state");

 

   cnt = qei_lld_get_count(qeip);

-  delta = cnt - qeip->last;

+  delta = (qeicnt_t)(cnt - qeip->last);

   qeip->last = cnt;

 

   return delta;

diff --git a/os/hal/src/hal_timcap.c b/os/hal/src/hal_timcap.c
index a352490..309c147 100644
--- a/os/hal/src/hal_timcap.c
+++ b/os/hal/src/hal_timcap.c
@@ -19,7 +19,7 @@
 */
 
 /**
- * @file    timcap.c
+ * @file    hal_timcap.c
  * @brief   TIMCAP Driver code.
  *
  * @addtogroup TIMCAP
diff --git a/os/hal/src/hal_usb_hid.c b/os/hal/src/hal_usb_hid.c
index 56be9b7..d9d671b 100644
--- a/os/hal/src/hal_usb_hid.c
+++ b/os/hal/src/hal_usb_hid.c
@@ -221,10 +221,10 @@ void hidObjectInit(USBHIDDriver *uhdp) {
   uhdp->vmt = &vmt;

   osalEventObjectInit(&uhdp->event);

   uhdp->state = HID_STOP;

-  ibqObjectInit(&uhdp->ibqueue, uhdp->ib,

+  ibqObjectInit(&uhdp->ibqueue, true, uhdp->ib,

                 USB_HID_BUFFERS_SIZE, USB_HID_BUFFERS_NUMBER,

                 ibnotify, uhdp);

-  obqObjectInit(&uhdp->obqueue, uhdp->ob,

+  obqObjectInit(&uhdp->obqueue, true, uhdp->ob,

                 USB_HID_BUFFERS_SIZE, USB_HID_BUFFERS_NUMBER,

                 obnotify, uhdp);

 }

diff --git a/os/hal/src/hal_usb_msd.c b/os/hal/src/hal_usb_msd.c
new file mode 100644
index 0000000..564bad0
--- /dev/null
+++ b/os/hal/src/hal_usb_msd.c
@@ -0,0 +1,429 @@
+/*
+    ChibiOS/HAL - Copyright (C) 2016 Uladzimir Pylinsky aka barthess
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    hal_usb_msd.c
+ * @brief   USM mass storage device code.
+ *
+ * @addtogroup usb_msd
+ * @{
+ */
+
+#include "hal.h"
+
+#if (HAL_USE_USB_MSD == TRUE) || defined(__DOXYGEN__)
+
+#include <string.h>
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#define MSD_REQ_RESET                   0xFF
+#define MSD_GET_MAX_LUN                 0xFE
+
+#define MSD_CBW_SIGNATURE               0x43425355
+#define MSD_CSW_SIGNATURE               0x53425355
+
+#define MSD_THD_PRIO                    NORMALPRIO
+
+#define CBW_FLAGS_RESERVED_MASK         0b01111111
+#define CBW_LUN_RESERVED_MASK           0b11110000
+#define CBW_CMD_LEN_RESERVED_MASK       0b11000000
+
+#define CSW_STATUS_PASSED               0x00
+#define CSW_STATUS_FAILED               0x01
+#define CSW_STATUS_PHASE_ERROR          0x02
+
+#define MSD_SETUP_WORD(setup, index) (uint16_t)(((uint16_t)setup[index+1] << 8)\
+                                                | (setup[index] & 0x00FF))
+
+#define MSD_SETUP_VALUE(setup)  MSD_SETUP_WORD(setup, 2)
+#define MSD_SETUP_INDEX(setup)  MSD_SETUP_WORD(setup, 4)
+#define MSD_SETUP_LENGTH(setup) MSD_SETUP_WORD(setup, 6)
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+/**
+ * @brief   USB mass storage driver identifier.
+ */
+USBMassStorageDriver USBMSD1;
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Hardcoded default SCSI inquiry response structure.
+ */
+static const scsi_inquiry_response_t default_scsi_inquiry_response = {
+    0x00,           /* direct access block device     */
+    0x80,           /* removable                      */
+    0x04,           /* SPC-2                          */
+    0x02,           /* response data format           */
+    0x20,           /* response has 0x20 + 4 bytes    */
+    0x00,
+    0x00,
+    0x00,
+    "Chibios",
+    "Mass Storage",
+    {'v',CH_KERNEL_MAJOR+'0','.',CH_KERNEL_MINOR+'0'}
+};
+
+/**
+ * @brief   Hardcoded default SCSI unit serial number inquiry response structure.
+ */
+static const scsi_unit_serial_number_inquiry_response_t default_scsi_unit_serial_number_inquiry_response =
+{
+    0x00,
+    0x80,
+    0x00,
+    0x08,
+    "00000000"
+};
+
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Checks validity of CBW content.
+ * @details The device shall consider the CBW valid when:
+ *          • The CBW was received after the device had sent a CSW or after a reset,
+ *          • the CBW is 31 (1Fh) bytes in length,
+ *          • and the dCBWSignature is equal to 43425355h.
+ *
+ * @param[in] cbw       pointer to the @p msd_cbw_t object
+ * @param[in] recvd     number of received bytes
+ *
+ * @return              Operation status.
+ * @retval true         CBW is meaningful.
+ * @retval false        CBW is bad.
+ *
+ * @notapi
+ */
+static bool cbw_valid(const msd_cbw_t *cbw, msg_t recvd) {
+  if ((sizeof(msd_cbw_t) != recvd) || (cbw->signature != MSD_CBW_SIGNATURE)) {
+    return false;
+  }
+  else {
+    return true;
+  }
+}
+
+/**
+ * @brief   Checks meaningfulness of CBW content.
+ * @details The device shall consider the contents of a valid CBW meaningful when:
+ *          • no reserved bits are set,
+ *          • the bCBWLUN contains a valid LUN supported by the device,
+ *          • and both bCBWCBLength and the content of the CBWCB are in
+ *            accordance with bInterfaceSubClass.
+ *
+ * @param[in] cbw       pointer to the @p msd_cbw_t object
+ *
+ * @return              Operation status.
+ * @retval true         CBW is meaningful.
+ * @retval false        CBW is bad.
+ *
+ * @notapi
+ */
+static bool cbw_meaningful(const msd_cbw_t *cbw) {
+  if (((cbw->cmd_len & CBW_CMD_LEN_RESERVED_MASK) != 0)
+      || ((cbw->flags & CBW_FLAGS_RESERVED_MASK) != 0)
+      || (cbw->lun != 0)) {
+    return false;
+  }
+  else {
+    return true;
+  }
+}
+
+/**
+ * @brief   SCSI transport transmit function.
+ *
+ * @param[in] transport pointer to the @p SCSITransport object
+ * @param[in] data      payload
+ * @param[in] len       number of bytes to be transmitted
+ *
+ * @return              Number of successfully transmitted bytes.
+
+ * @notapi
+ */
+static uint32_t scsi_transport_transmit(const SCSITransport *transport,
+                                        const uint8_t *data, size_t len) {
+
+  usb_scsi_transport_handler_t *trp = transport->handler;
+  msg_t status = usbTransmit(trp->usbp, trp->ep, data, len);
+  if (MSG_OK == status)
+    return len;
+  else
+    return 0;
+}
+
+/**
+ * @brief   SCSI transport receive function.
+ *
+ * @param[in] transport pointer to the @p SCSITransport object
+ * @param[in] data      payload
+ * @param[in] len       number bytes to be received
+ *
+ * @return              Number of successfully received bytes.
+
+ * @notapi
+ */
+static uint32_t scsi_transport_receive(const SCSITransport *transport,
+                                       uint8_t *data, size_t len) {
+
+  usb_scsi_transport_handler_t *trp = transport->handler;
+  msg_t status = usbReceive(trp->usbp, trp->ep, data, len);
+  if (MSG_RESET != status)
+    return status;
+  else
+    return 0;
+}
+
+/**
+ * @brief   Fills and sends CSW message.
+ *
+ * @param[in] msdp      pointer to the @p USBMassStorageDriver object
+ * @param[in] status    status returned by SCSI layer
+ * @param[in] residue   number of residue bytes in case of failed transaction
+ *
+ * @notapi
+ */
+static void send_csw(USBMassStorageDriver *msdp, uint8_t status,
+                     uint32_t residue) {
+
+  msdp->csw.signature = MSD_CSW_SIGNATURE;
+  msdp->csw.data_residue = residue;
+  msdp->csw.tag = msdp->cbw.tag;
+  msdp->csw.status = status;
+
+  usbTransmit(msdp->usbp, USB_MSD_DATA_EP, (uint8_t *)&msdp->csw,
+      sizeof(msd_csw_t));
+}
+
+/**
+ * @brief   Mass storage worker thread.
+ *
+ * @param[in] arg     pointer to the @p USBMassStorageDriver object
+ *
+ * @notapi
+ */
+static THD_FUNCTION(usb_msd_worker, arg) {
+  USBMassStorageDriver *msdp = arg;
+  chRegSetThreadName("usb_msd_worker");
+
+  while(! chThdShouldTerminateX()) {
+    const msg_t status = usbReceive(msdp->usbp, USB_MSD_DATA_EP,
+                                   (uint8_t *)&msdp->cbw, sizeof(msd_cbw_t));
+    if (MSG_RESET == status) {
+      osalThreadSleepMilliseconds(50);
+    }
+    else if (cbw_valid(&msdp->cbw, status) && cbw_meaningful(&msdp->cbw)) {
+      if (SCSI_SUCCESS == scsiExecCmd(&msdp->scsi_target, msdp->cbw.cmd_data)) {
+        send_csw(msdp, CSW_STATUS_PASSED, 0);
+      }
+      else {
+        send_csw(msdp, CSW_STATUS_FAILED, scsiResidue(&msdp->scsi_target));
+      }
+    }
+    else {
+      ; /* do NOT send CSW here. Incorrect CBW must be silently ignored */
+    }
+  }
+
+  chThdExit(MSG_OK);
+}
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Mass storage specific request hook for USB.
+ *
+ * @param[in] usbp     pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+bool msd_request_hook(USBDriver *usbp) {
+
+  if (((usbp->setup[0] & USB_RTYPE_TYPE_MASK) == USB_RTYPE_TYPE_CLASS) &&
+    ((usbp->setup[0] & USB_RTYPE_RECIPIENT_MASK) == USB_RTYPE_RECIPIENT_INTERFACE)) {
+    /* check that the request is for interface 0.*/
+    if (MSD_SETUP_INDEX(usbp->setup) != 0)
+      return false;
+
+    /* act depending on bRequest = setup[1] */
+    switch(usbp->setup[1]) {
+    case MSD_REQ_RESET:
+      /* check that it is a HOST2DEV request */
+      if (((usbp->setup[0] & USB_RTYPE_DIR_MASK) != USB_RTYPE_DIR_HOST2DEV) ||
+         (MSD_SETUP_LENGTH(usbp->setup) != 0) ||
+         (MSD_SETUP_VALUE(usbp->setup) != 0)) {
+        return false;
+      }
+
+      /*
+      As required by the BOT specification, the Bulk-only mass storage reset request (classspecific
+      request) is implemented. This request is used to reset the mass storage device and
+      its associated interface. This class-specific request should prepare the device for the next
+      CBW from the host.
+      To generate the BOT Mass Storage Reset, the host must send a device request on the
+      default pipe of:
+      • bmRequestType: Class, interface, host to device
+      • bRequest field set to 255 (FFh)
+      • wValue field set to ‘0’
+      • wIndex field set to the interface number
+      • wLength field set to ‘0’
+      */
+      chSysLockFromISR();
+
+      /* release and abandon current transmission */
+      usbStallReceiveI(usbp, 1);
+      usbStallTransmitI(usbp, 1);
+      /* The device shall NAK the status stage of the device request until
+       * the Bulk-Only Mass Storage Reset is complete.
+       * NAK EP1 in and out */
+      usbp->otg->ie[1].DIEPCTL = DIEPCTL_SNAK;
+      usbp->otg->oe[1].DOEPCTL = DOEPCTL_SNAK;
+
+      chSysUnlockFromISR();
+
+      /* response to this request using EP0 */
+      usbSetupTransfer(usbp, 0, 0, NULL);
+      return true;
+
+    case MSD_GET_MAX_LUN:
+      /* check that it is a DEV2HOST request */
+      if (((usbp->setup[0] & USB_RTYPE_DIR_MASK) != USB_RTYPE_DIR_DEV2HOST) ||
+         (MSD_SETUP_LENGTH(usbp->setup) != 1) ||
+         (MSD_SETUP_VALUE(usbp->setup) != 0)) {
+        return false;
+      }
+
+      /* stall to indicate that we don't support LUN */
+      osalSysLockFromISR();
+      usbStallTransmitI(usbp, 0);
+      osalSysUnlockFromISR();
+      return true;
+
+    default:
+      return false;
+      break;
+    }
+  }
+  return false;
+}
+
+/**
+ * @brief   Initializes the standard part of a @p USBMassStorageDriver structure.
+ *
+ * @param[out] msdp     pointer to the @p USBMassStorageDriver object
+ *
+ * @init
+ */
+void msdObjectInit(USBMassStorageDriver *msdp) {
+
+  memset(msdp, 0x55, sizeof(USBMassStorageDriver));
+  msdp->state = USB_MSD_STOP;
+  msdp->usbp = NULL;
+  msdp->worker = NULL;
+
+  scsiObjectInit(&msdp->scsi_target);
+}
+
+/**
+ * @brief   Stops the USB mass storage driver.
+ *
+ * @param[in] msdp      pointer to the @p USBMassStorageDriver object
+ *
+ * @api
+ */
+void msdStop(USBMassStorageDriver *msdp) {
+
+  osalDbgCheck(msdp != NULL);
+  osalDbgAssert((msdp->state == USB_MSD_READY), "invalid state");
+
+  chThdTerminate(msdp->worker);
+  chThdWait(msdp->worker);
+
+  scsiStop(&msdp->scsi_target);
+
+  msdp->worker = NULL;
+  msdp->state = USB_MSD_STOP;
+  msdp->usbp = NULL;
+}
+
+/**
+ * @brief   Configures and activates the USB mass storage driver.
+ *
+ * @param[in] msdp      pointer to the @p USBMassStorageDriver object
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] blkdev    pointer to the @p BaseBlockDevice object
+ * @param[in] blkbuf    pointer to the working area buffer, must be allocated
+ *                      by user, must be big enough to store 1 data block
+ * @param[in] inquiry   pointer to the SCSI inquiry response structure,
+ *                      set it to @p NULL to use default hardcoded value.
+ *
+ * @api
+ */
+void msdStart(USBMassStorageDriver *msdp, USBDriver *usbp,
+              BaseBlockDevice *blkdev, uint8_t *blkbuf,
+              const scsi_inquiry_response_t *inquiry,
+              const scsi_unit_serial_number_inquiry_response_t *serialInquiry) {
+
+  osalDbgCheck((msdp != NULL) && (usbp != NULL)
+              && (blkdev != NULL) && (blkbuf != NULL));
+  osalDbgAssert((msdp->state == USB_MSD_STOP), "invalid state");
+
+  msdp->usbp = usbp;
+
+  msdp->usb_scsi_transport_handler.usbp = msdp->usbp;
+  msdp->usb_scsi_transport_handler.ep   = USB_MSD_DATA_EP;
+  msdp->scsi_transport.handler  = &msdp->usb_scsi_transport_handler;
+  msdp->scsi_transport.transmit = scsi_transport_transmit;
+  msdp->scsi_transport.receive  = scsi_transport_receive;
+
+  if (NULL == inquiry) {
+    msdp->scsi_config.inquiry_response = &default_scsi_inquiry_response;
+  }
+  else {
+    msdp->scsi_config.inquiry_response = inquiry;
+  }
+  if (NULL == serialInquiry) {
+    msdp->scsi_config.unit_serial_number_inquiry_response = &default_scsi_unit_serial_number_inquiry_response;
+  }
+  else {
+    msdp->scsi_config.unit_serial_number_inquiry_response = serialInquiry;
+  }
+  msdp->scsi_config.blkbuf = blkbuf;
+  msdp->scsi_config.blkdev = blkdev;
+  msdp->scsi_config.transport = &msdp->scsi_transport;
+
+  scsiStart(&msdp->scsi_target, &msdp->scsi_config);
+
+  msdp->state = USB_MSD_READY;
+  msdp->worker = chThdCreateStatic(msdp->waMSDWorker, sizeof(msdp->waMSDWorker),
+                                   MSD_THD_PRIO, usb_msd_worker, msdp);
+}
+
+#endif /* HAL_USE_USB_MSD */
+
+/** @} */
diff --git a/os/hal/src/hal_usbh.c b/os/hal/src/hal_usbh.c
index 1caa183..7dff98a 100644
--- a/os/hal/src/hal_usbh.c
+++ b/os/hal/src/hal_usbh.c
@@ -1,6 +1,6 @@
 /*
-    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
-              Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail)
+    ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio
+              Copyright (C) 2015..2017 Diego Ismirlian, (dismirlian (at) google's mail)
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -19,8 +19,8 @@
 
 #if HAL_USE_USBH
 
-#include "usbh/dev/hub.h"
 #include "usbh/internal.h"
+#include "usbh/dev/hub.h"
 #include <string.h>
 
 #if USBH_DEBUG_ENABLE_TRACE
@@ -55,21 +55,18 @@
 #define uerr(f, ...)   do {} while(0)
 #endif
 
-#if STM32_USBH_USE_OTG1
-USBHDriver USBHD1;
-#endif
-#if STM32_USBH_USE_OTG2
-USBHDriver USBHD2;
-#endif
-
-
 static void _classdriver_process_device(usbh_device_t *dev);
-static bool _classdriver_load(usbh_device_t *dev, uint8_t class,
-		uint8_t subclass, uint8_t protocol, uint8_t *descbuff, uint16_t rem);
+static bool _classdriver_load(usbh_device_t *dev, uint8_t *descbuff, uint16_t rem);
 
+#if HAL_USBH_USE_ADDITIONAL_CLASS_DRIVERS
+#include "usbh_additional_class_drivers.h"
+#ifndef HAL_USBH_ADDITIONAL_CLASS_DRIVERS
+#error "Must define HAL_USBH_ADDITIONAL_CLASS_DRIVERS"
+#endif
+#endif
 
 /*===========================================================================*/
-/* Checks.								                                     */
+/* Checks.                                                                   */
 /*===========================================================================*/
 
 static inline void _check_dev(usbh_device_t *dev) {
@@ -92,7 +89,7 @@ static inline void _check_urb(usbh_urb_t *urb) {
 }
 
 /*===========================================================================*/
-/* Main driver API.						                                     */
+/* Main driver API.                                                          */
 /*===========================================================================*/
 
 void usbhObjectInit(USBHDriver *usbh) {
@@ -106,16 +103,6 @@ void usbhObjectInit(USBHDriver *usbh) {
 #endif
 }
 
-void usbhInit(void) {
-#if HAL_USBH_USE_HUB
-	uint8_t i;
-	for (i = 0; i < HAL_USBHHUB_MAX_INSTANCES; i++) {
-		usbhhubObjectInit(&USBHHUBD[i]);
-	}
-#endif
-	usbh_lld_init();
-}
-
 void usbhStart(USBHDriver *usbh) {
 	usbDbgInit(usbh);
 
@@ -124,11 +111,9 @@ void usbhStart(USBHDriver *usbh) {
 				"invalid state");
 	usbh_lld_start(usbh);
 	usbh->status = USBH_STATUS_STARTED;
-	osalOsRescheduleS();
 	osalSysUnlock();
 }
 
-
 void usbhStop(USBHDriver *usbh) {
 	//TODO: implement
 	(void)usbh;
@@ -143,7 +128,7 @@ void usbhResume(USBHDriver *usbh) {
 }
 
 /*===========================================================================*/
-/* Endpoint API.						                                     */
+/* Endpoint API.                                                             */
 /*===========================================================================*/
 
 void usbhEPObjectInit(usbh_ep_t *ep, usbh_device_t *dev, const usbh_endpoint_descriptor_t *desc) {
@@ -181,9 +166,28 @@ static void _ep0_object_init(usbh_device_t *dev, uint16_t wMaxPacketSize) {
 	usbhEPSetName(&dev->ctrl, "DEV[CTRL]");
 }
 
+bool usbhEPReset(usbh_ep_t *ep) {
+	osalDbgCheck(ep != NULL);
+	osalDbgAssert((ep->status == USBH_EPSTATUS_OPEN) || (ep->status == USBH_EPSTATUS_HALTED), "invalid state");
+	osalDbgAssert(ep->type != USBH_EPTYPE_CTRL, "don't need to reset control endpoint");
+
+	usbh_urbstatus_t ret = usbhControlRequest(ep->device,
+			USBH_REQTYPE_STANDARDOUT(USBH_REQTYPE_RECIP_ENDPOINT),
+			USBH_REQ_CLEAR_FEATURE,
+			0, ep->address | (ep->in ? 0x80 : 0x00), 0, 0);
+
+	/* TODO: GET_STATUS to see if endpoint is still halted */
+	osalSysLock();
+	if ((ret == USBH_URBSTATUS_OK) && usbh_lld_ep_reset(ep)) {
+		osalSysUnlock();
+		return HAL_SUCCESS;
+	}
+	osalSysUnlock();
+	return HAL_FAILED;
+}
 
 /*===========================================================================*/
-/* URB API.				    	                                     		 */
+/* URB API.                                                                  */
 /*===========================================================================*/
 
 void usbhURBObjectInit(usbh_urb_t *urb, usbh_ep_t *ep, usbh_completion_cb callback,
@@ -219,6 +223,7 @@ void usbhURBObjectResetI(usbh_urb_t *urb) {
 	usbh_lld_urb_object_reset(urb);
 }
 
+/* usbhURBSubmitI may require a reschedule if called from a S-locked state */
 void usbhURBSubmitI(usbh_urb_t *urb) {
 	osalDbgCheckClassI();
 	_check_urb(urb);
@@ -228,11 +233,8 @@ void usbhURBSubmitI(usbh_urb_t *urb) {
 		_usbh_urb_completeI(urb, USBH_URBSTATUS_STALL);
 		return;
 	}
-	if (ep->status != USBH_EPSTATUS_OPEN) {
-		_usbh_urb_completeI(urb, USBH_URBSTATUS_DISCONNECTED);
-		return;
-	}
-	if (!(usbhDeviceGetPort(ep->device)->status & USBH_PORTSTATUS_ENABLE)) {
+	if ((ep->status != USBH_EPSTATUS_OPEN)
+		|| !(usbhDeviceGetPort(ep->device)->status & USBH_PORTSTATUS_ENABLE)) {
 		_usbh_urb_completeI(urb, USBH_URBSTATUS_DISCONNECTED);
 		return;
 	}
@@ -240,28 +242,21 @@ void usbhURBSubmitI(usbh_urb_t *urb) {
 	usbh_lld_urb_submit(urb);
 }
 
+/* _usbh_urb_abortI may require a reschedule if called from a S-locked state */
 bool _usbh_urb_abortI(usbh_urb_t *urb, usbh_urbstatus_t status) {
 	osalDbgCheckClassI();
 	_check_urb(urb);
+	osalDbgCheck(urb->status != USBH_URBSTATUS_UNINITIALIZED);
 
-	switch (urb->status) {
-/*	case USBH_URBSTATUS_UNINITIALIZED:
- * 	case USBH_URBSTATUS_INITIALIZED:
- *	case USBH_URBSTATUS_ERROR:
- *	case USBH_URBSTATUS_TIMEOUT:
- *	case USBH_URBSTATUS_CANCELLED:
- *	case USBH_URBSTATUS_STALL:
- *	case USBH_URBSTATUS_DISCONNECTED:
- *	case USBH_URBSTATUS_OK: */
-	default:
-		/* already finished */
-		_usbh_urb_completeI(urb, status);
-		return TRUE;
-
-//	case USBH_URBSTATUS_QUEUED:
-	case USBH_URBSTATUS_PENDING:
+	if (urb->status == USBH_URBSTATUS_PENDING) {
 		return usbh_lld_urb_abort(urb, status);
 	}
+
+	/* already finished or never submitted:
+	 * USBH_URBSTATUS_INITIALIZED, USBH_URBSTATUS_ERROR, USBH_URBSTATUS_TIMEOUT,
+	 * USBH_URBSTATUS_CANCELLED, USBH_URBSTATUS_STALL, USBH_URBSTATUS_DISCONNECTED
+	 * USBH_URBSTATUS_OK */
+	return TRUE;
 }
 
 void _usbh_urb_abort_and_waitS(usbh_urb_t *urb, usbh_urbstatus_t status) {
@@ -271,13 +266,16 @@ void _usbh_urb_abort_and_waitS(usbh_urb_t *urb, usbh_urbstatus_t status) {
 	if (_usbh_urb_abortI(urb, status) == FALSE) {
 		uwarn("URB wasn't aborted immediately, suspend");
 		osalThreadSuspendS(&urb->abortingThread);
-		urb->abortingThread = 0;
+		osalDbgAssert(urb->abortingThread == 0, "maybe we should uncomment the line below");
+		//urb->abortingThread = 0;
 	} else {
+		/* This call is necessary because _usbh_urb_abortI may require a reschedule */
 		osalOsRescheduleS();
 	}
 	uwarn("URB aborted");
 }
 
+/* usbhURBCancelI may require a reschedule if called from a S-locked state */
 bool usbhURBCancelI(usbh_urb_t *urb) {
 	return _usbh_urb_abortI(urb, USBH_URBSTATUS_CANCELLED);
 }
@@ -287,36 +285,14 @@ void usbhURBCancelAndWaitS(usbh_urb_t *urb) {
 }
 
 msg_t usbhURBWaitTimeoutS(usbh_urb_t *urb, systime_t timeout) {
-	msg_t ret;
-
 	osalDbgCheckClassS();
 	_check_urb(urb);
-
-	switch (urb->status) {
-	case USBH_URBSTATUS_INITIALIZED:
-	case USBH_URBSTATUS_PENDING:
-//	case USBH_URBSTATUS_QUEUED:
-		ret = osalThreadSuspendTimeoutS(&urb->waitingThread, timeout);
-		urb->waitingThread = 0;
-		break;
-
-	case USBH_URBSTATUS_OK:
-		ret = MSG_OK;
-		osalOsRescheduleS();
-		break;
-
-/*	case USBH_URBSTATUS_UNINITIALIZED:
- *	case USBH_URBSTATUS_ERROR:
- *	case USBH_URBSTATUS_TIMEOUT:
- *	case USBH_URBSTATUS_CANCELLED:
- *	case USBH_URBSTATUS_STALL:
- *	case USBH_URBSTATUS_DISCONNECTED: */
-	default:
-		ret = MSG_RESET;
-		osalOsRescheduleS();
-		break;
+	if (urb->status == USBH_URBSTATUS_OK) {
+		return MSG_OK;
+	} else if (urb->status != USBH_URBSTATUS_PENDING) {
+		return MSG_RESET;
 	}
-	return ret;
+	return osalThreadSuspendTimeoutS(&urb->waitingThread, timeout);
 }
 
 msg_t usbhURBSubmitAndWaitS(usbh_urb_t *urb, systime_t timeout) {
@@ -339,6 +315,7 @@ static inline msg_t _wakeup_message(usbh_urbstatus_t status) {
 	return MSG_RESET;
 }
 
+/* _usbh_urb_completeI may require a reschedule if called from a S-locked state */
 void _usbh_urb_completeI(usbh_urb_t *urb, usbh_urbstatus_t status) {
 	osalDbgCheckClassI();
 	_check_urb(urb);
@@ -350,7 +327,7 @@ void _usbh_urb_completeI(usbh_urb_t *urb, usbh_urbstatus_t status) {
 }
 
 /*===========================================================================*/
-/* Synchronous API.		    	                                     		 */
+/* Synchronous API.                                                          */
 /*===========================================================================*/
 
 usbh_urbstatus_t usbhBulkTransfer(usbh_ep_t *ep,
@@ -382,7 +359,8 @@ usbh_urbstatus_t usbhControlRequestExtended(usbh_device_t *dev,
 		uint32_t *actual_len,
 		systime_t timeout) {
 
-	_check_dev(dev);
+	if (!dev) return USBH_URBSTATUS_DISCONNECTED;
+
 	osalDbgCheck(req != NULL);
 
 	usbh_urb_t urb;
@@ -408,41 +386,33 @@ usbh_urbstatus_t usbhControlRequest(usbh_device_t *dev,
 		uint16_t wLength,
 		uint8_t *buff) {
 
-	const USBH_DEFINE_BUFFER(usbh_control_request_t, req) = {
+	USBH_DEFINE_BUFFER(const usbh_control_request_t req) = {
 			bmRequestType,
 			bRequest,
 			wValue,
 			wIndex,
 			wLength
 	};
-	return usbhControlRequestExtended(dev, &req, buff, NULL, MS2ST(1000));
+	return usbhControlRequestExtended(dev, &req, buff, NULL, HAL_USBH_CONTROL_REQUEST_DEFAULT_TIMEOUT);
 }
 
 /*===========================================================================*/
-/* Standard request helpers.   	                                     		 */
+/* Standard request helpers.                                                 */
 /*===========================================================================*/
 
-#define USBH_GET_DESCRIPTOR(type, value, index)	\
-	USBH_STANDARDIN(type, \
-	USBH_REQ_GET_DESCRIPTOR, \
-	value, \
-	index) \
-
-#define USBH_GETDEVICEDESCRIPTOR \
-	USBH_GET_DESCRIPTOR(USBH_REQTYPE_DEVICE, (USBH_DT_DEVICE << 8) | 0, 0)
-
-#define USBH_GETCONFIGURATIONDESCRIPTOR(index) \
-	USBH_GET_DESCRIPTOR(USBH_REQTYPE_DEVICE, (USBH_DT_CONFIG << 8) | index, 0)
-
-#define USBH_GETSTRINGDESCRIPTOR(index, langID) \
-	USBH_GET_DESCRIPTOR(USBH_REQTYPE_DEVICE, (USBH_DT_STRING << 8) | index, langID)
-
 bool usbhStdReqGetDeviceDescriptor(usbh_device_t *dev,
 		uint16_t wLength,
 		uint8_t *buf) {
 	usbh_device_descriptor_t *desc;
-	usbh_urbstatus_t ret = usbhControlRequest(dev, USBH_GETDEVICEDESCRIPTOR, wLength, buf);
+
+	usbh_urbstatus_t ret = usbhControlRequest(dev,
+			USBH_REQTYPE_STANDARDIN(USBH_REQTYPE_RECIP_DEVICE),
+			USBH_REQ_GET_DESCRIPTOR,
+			(USBH_DT_DEVICE << 8) | 0, 0,
+			wLength, buf);
+
 	desc = (usbh_device_descriptor_t *)buf;
+
 	if ((ret != USBH_URBSTATUS_OK)
 			|| (desc->bLength != USBH_DT_DEVICE_SIZE)
 			|| (desc->bDescriptorType != USBH_DT_DEVICE)) {
@@ -455,8 +425,15 @@ bool usbhStdReqGetConfigurationDescriptor(usbh_device_t *dev,
 		uint8_t index,
 		uint16_t wLength,
 		uint8_t *buf) {
-	usbh_urbstatus_t ret = usbhControlRequest(dev, USBH_GETCONFIGURATIONDESCRIPTOR(index), wLength, buf);
+
+	usbh_urbstatus_t ret = usbhControlRequest(dev,
+			USBH_REQTYPE_STANDARDIN(USBH_REQTYPE_RECIP_DEVICE),
+			USBH_REQ_GET_DESCRIPTOR,
+			(USBH_DT_CONFIG << 8) | index, 0,
+			wLength, buf);
+
 	usbh_config_descriptor_t *const desc = (usbh_config_descriptor_t *)buf;
+
 	if ((ret != USBH_URBSTATUS_OK)
 			|| (desc->bLength < USBH_DT_CONFIG_SIZE)
 			|| (desc->bDescriptorType != USBH_DT_CONFIG)) {
@@ -473,7 +450,13 @@ bool usbhStdReqGetStringDescriptor(usbh_device_t *dev,
 
 	osalDbgAssert(wLength >= USBH_DT_STRING_SIZE, "wrong size");
 	usbh_string_descriptor_t *desc = (usbh_string_descriptor_t *)buf;
-	usbh_urbstatus_t ret = usbhControlRequest(dev, USBH_GETSTRINGDESCRIPTOR(index, langID), wLength, buf);
+
+	usbh_urbstatus_t ret = usbhControlRequest(dev,
+			USBH_REQTYPE_STANDARDIN(USBH_REQTYPE_RECIP_DEVICE),
+			USBH_REQ_GET_DESCRIPTOR,
+			(USBH_DT_STRING << 8) | index, langID,
+			wLength, buf);
+
 	if ((ret != USBH_URBSTATUS_OK)
 			|| (desc->bLength < USBH_DT_STRING_SIZE)
 			|| (desc->bDescriptorType != USBH_DT_STRING)) {
@@ -482,25 +465,17 @@ bool usbhStdReqGetStringDescriptor(usbh_device_t *dev,
 	return HAL_SUCCESS;
 }
 
-
-
-#define USBH_SET_INTERFACE(interface, alt)	\
-	USBH_STANDARDOUT(USBH_REQTYPE_INTERFACE, \
-	USBH_REQ_SET_INTERFACE, \
-	alt, \
-	interface) \
-
-#define USBH_GET_INTERFACE(interface)	\
-	USBH_STANDARDIN(USBH_REQTYPE_INTERFACE, \
-	USBH_REQ_GET_INTERFACE, \
-	0, \
-	interface) \
-
 bool usbhStdReqSetInterface(usbh_device_t *dev,
 		uint8_t bInterfaceNumber,
 		uint8_t bAlternateSetting) {
 
-	usbh_urbstatus_t ret = usbhControlRequest(dev, USBH_SET_INTERFACE(bInterfaceNumber, bAlternateSetting), 0, NULL);
+	usbh_urbstatus_t ret = usbhControlRequest(dev,
+			USBH_REQTYPE_STANDARDOUT(USBH_REQTYPE_RECIP_INTERFACE),
+			USBH_REQ_SET_INTERFACE,
+			bAlternateSetting,
+			bInterfaceNumber,
+			0, NULL);
+
 	if (ret != USBH_URBSTATUS_OK)
 		return HAL_FAILED;
 
@@ -511,9 +486,15 @@ bool usbhStdReqGetInterface(usbh_device_t *dev,
 		uint8_t bInterfaceNumber,
 		uint8_t *bAlternateSetting) {
 
-	USBH_DEFINE_BUFFER(uint8_t, alt);
+	USBH_DEFINE_BUFFER(uint8_t alt);
+
+	usbh_urbstatus_t ret = usbhControlRequest(dev,
+			USBH_REQTYPE_STANDARDIN(USBH_REQTYPE_RECIP_INTERFACE),
+			USBH_REQ_GET_INTERFACE,
+			0,
+			bInterfaceNumber,
+			1, &alt);
 
-	usbh_urbstatus_t ret = usbhControlRequest(dev, USBH_GET_INTERFACE(bInterfaceNumber), 1, &alt);
 	if (ret != USBH_URBSTATUS_OK)
 		return HAL_FAILED;
 
@@ -523,7 +504,7 @@ bool usbhStdReqGetInterface(usbh_device_t *dev,
 
 
 /*===========================================================================*/
-/* Device-related functions.   	                                     		 */
+/* Device-related functions.                                                 */
 /*===========================================================================*/
 
 static uint8_t _find_address(USBHDriver *host) {
@@ -558,7 +539,8 @@ static void _device_initialize(usbh_device_t *dev, usbh_devspeed_t speed) {
 
 static bool _device_setaddress(usbh_device_t *dev, uint8_t address) {
 	usbh_urbstatus_t ret = usbhControlRequest(dev,
-			USBH_STANDARDOUT(USBH_REQTYPE_DEVICE, USBH_REQ_SET_ADDRESS, address, 0),
+			USBH_REQTYPE_STANDARDOUT(USBH_REQTYPE_RECIP_DEVICE),
+			USBH_REQ_SET_ADDRESS, address, 0,
 			0,
 			0);
 	if (ret != USBH_URBSTATUS_OK)
@@ -611,22 +593,12 @@ static void _device_free_full_cfgdesc(usbh_device_t *dev) {
 	}
 }
 
-
-#define USBH_SET_CONFIGURATION(type, value, index)	\
-	USBH_STANDARDOUT(type, \
-	USBH_REQ_SET_CONFIGURATION, \
-	value, \
-	index) \
-
-#define USBH_SETDEVICECONFIGURATION(index) \
-	USBH_SET_CONFIGURATION(USBH_REQTYPE_DEVICE, index, 0)
-
-
 static bool _device_set_configuration(usbh_device_t *dev, uint8_t configuration) {
 	usbh_urbstatus_t ret = usbhControlRequest(dev,
-			USBH_SETDEVICECONFIGURATION(configuration),
-			0,
-			0);
+			USBH_REQTYPE_STANDARDOUT(USBH_REQTYPE_RECIP_DEVICE),
+			USBH_REQ_SET_CONFIGURATION,
+			configuration,
+			0, 0, 0);
 	if (ret != USBH_URBSTATUS_OK)
 		return HAL_FAILED;
 	return HAL_SUCCESS;
@@ -720,7 +692,7 @@ static bool _device_enumerate(usbh_device_t *dev) {
 
 #if USBH_DEBUG_ENABLE && USBH_DEBUG_ENABLE_INFO
 void usbhDevicePrintInfo(usbh_device_t *dev) {
-	USBH_DEFINE_BUFFER(char, str[64]);
+	USBH_DEFINE_BUFFER(char str[64]);
 	usbh_device_descriptor_t *const desc = &dev->devDesc;
 
 	uinfo("----- Device info -----");
@@ -842,11 +814,8 @@ bool usbhDeviceReadString(usbh_device_t *dev, char *dest, uint8_t size,
 	return HAL_SUCCESS;
 }
 
-
-
-
 /*===========================================================================*/
-/* Port processing functions.  	                                     		 */
+/* Port processing functions.                                                */
 /*===========================================================================*/
 
 static void _port_connected(usbh_port_t *port);
@@ -856,7 +825,7 @@ static void _port_reset(usbh_port_t *port) {
 #if HAL_USBH_USE_HUB
 			port->hub,
 #endif
-			USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_OTHER,
+			USBH_REQTYPE_DIR_OUT | USBH_REQTYPE_TYPE_CLASS | USBH_REQTYPE_RECIP_OTHER,
 			USBH_REQ_SET_FEATURE,
 			USBH_PORT_FEAT_RESET,
 			port->number,
@@ -870,7 +839,7 @@ static void _port_update_status(usbh_port_t *port) {
 #if HAL_USBH_USE_HUB
 			port->hub,
 #endif
-			USBH_REQTYPE_IN | USBH_REQTYPE_CLASS | USBH_REQTYPE_OTHER,
+			USBH_REQTYPE_DIR_IN | USBH_REQTYPE_TYPE_CLASS | USBH_REQTYPE_RECIP_OTHER,
 			USBH_REQ_GET_STATUS,
 			0,
 			port->number,
@@ -887,46 +856,48 @@ static void _port_process_status_change(usbh_port_t *port) {
 	_port_update_status(port);
 
 	if (port->c_status & USBH_PORTSTATUS_C_CONNECTION) {
-		/* port connected status changed */
 		port->c_status &= ~USBH_PORTSTATUS_C_CONNECTION;
 		usbhhubClearFeaturePort(port, USBH_PORT_FEAT_C_CONNECTION);
-		if ((port->status & (USBH_PORTSTATUS_CONNECTION | USBH_PORTSTATUS_ENABLE))
-				== USBH_PORTSTATUS_CONNECTION) {
-			if (port->device.status != USBH_DEVSTATUS_DISCONNECTED) {
+
+		if (port->device.status != USBH_DEVSTATUS_DISCONNECTED) {
+			if (!(port->status & USBH_PORTSTATUS_CONNECTION)) {
 				_usbh_port_disconnected(port);
 			}
+		}
+	}
 
-			/* connected, disabled */
+	if (port->device.status == USBH_DEVSTATUS_DISCONNECTED) {
+		if (port->status & USBH_PORTSTATUS_CONNECTION) {
 			_port_connected(port);
-		} else {
-			/* disconnected */
-			_usbh_port_disconnected(port);
 		}
 	}
 
 	if (port->c_status & USBH_PORTSTATUS_C_RESET) {
 		port->c_status &= ~USBH_PORTSTATUS_C_RESET;
 		usbhhubClearFeaturePort(port, USBH_PORT_FEAT_C_RESET);
+		udbgf("Port %d: reset=%d", port->number, port->status & USBH_PORTSTATUS_RESET ? 1 : 0);
 	}
 
 	if (port->c_status & USBH_PORTSTATUS_C_ENABLE) {
 		port->c_status &= ~USBH_PORTSTATUS_C_ENABLE;
 		usbhhubClearFeaturePort(port, USBH_PORT_FEAT_C_ENABLE);
+		udbgf("Port %d: enable=%d", port->number, port->status & USBH_PORTSTATUS_ENABLE ? 1 : 0);
 	}
 
 	if (port->c_status & USBH_PORTSTATUS_C_OVERCURRENT) {
 		port->c_status &= ~USBH_PORTSTATUS_C_OVERCURRENT;
 		usbhhubClearFeaturePort(port, USBH_PORT_FEAT_C_OVERCURRENT);
+		uwarnf("Port %d: overcurrent=%d", port->number, port->status & USBH_PORTSTATUS_OVERCURRENT ? 1 : 0);
 	}
 
 	if (port->c_status & USBH_PORTSTATUS_C_SUSPEND) {
 		port->c_status &= ~USBH_PORTSTATUS_C_SUSPEND;
 		usbhhubClearFeaturePort(port, USBH_PORT_FEAT_C_SUSPEND);
+		uinfof("Port %d: suspend=%d", port->number, port->status & USBH_PORTSTATUS_SUSPEND ? 1 : 0);
 	}
 
 }
 
-
 static void _port_connected(usbh_port_t *port) {
 	/* connected */
 
@@ -934,11 +905,10 @@ static void _port_connected(usbh_port_t *port) {
 	uint8_t i;
 	uint8_t retries;
 	usbh_devspeed_t speed;
-	USBH_DEFINE_BUFFER(usbh_string_descriptor_t, strdesc);
-
-	uinfof("Port %d connected, wait debounce...", port->number);
+	USBH_DEFINE_BUFFER(usbh_string_descriptor_t strdesc);
 
 	port->device.status = USBH_DEVSTATUS_ATTACHED;
+	uinfof("Port %d: attached, wait debounce...", port->number);
 
 	/* wait for attach de-bounce */
 	osalThreadSleepMilliseconds(HAL_USBH_PORT_DEBOUNCE_TIME);
@@ -946,16 +916,26 @@ static void _port_connected(usbh_port_t *port) {
 	/* check disconnection */
 	_port_update_status(port);
 	if (port->c_status & USBH_PORTSTATUS_C_CONNECTION) {
-		/* connection state changed; abort */
+		port->c_status &= ~USBH_PORTSTATUS_C_CONNECTION;
+		usbhhubClearFeaturePort(port, USBH_PORT_FEAT_C_CONNECTION);
+		uwarnf("Port %d: connection state changed; abort #1", port->number);
+		goto abort;
+	}
+
+	/* make sure that the device is still connected */
+	if ((port->status & USBH_PORTSTATUS_CONNECTION) == 0) {
+		uwarnf("Port %d: device is disconnected", port->number);
 		goto abort;
 	}
 
+	uinfof("Port %d: connected", port->number);
 	port->device.status = USBH_DEVSTATUS_CONNECTED;
 	retries = 3;
 
 reset:
 	for (i = 0; i < 3; i++) {
-		uinfo("Try reset...");
+		uinfof("Port %d: Try reset...", port->number);
+		/* TODO: check that port is actually disabled */
 		port->c_status &= ~(USBH_PORTSTATUS_C_RESET | USBH_PORTSTATUS_C_ENABLE);
 		_port_reset(port);
 		osalThreadSleepMilliseconds(20);	/* give it some time to reset (min. 10ms) */
@@ -964,8 +944,12 @@ reset:
 			_port_update_status(port);
 
 			/* check for disconnection */
-			if (port->c_status & USBH_PORTSTATUS_C_CONNECTION)
+			if (port->c_status & USBH_PORTSTATUS_C_CONNECTION) {
+				port->c_status &= ~USBH_PORTSTATUS_C_CONNECTION;
+				usbhhubClearFeaturePort(port, USBH_PORT_FEAT_C_CONNECTION);
+				uwarnf("Port %d: connection state changed; abort #2", port->number);
 				goto abort;
+			}
 
 			/* check for reset completion */
 			if (port->c_status & USBH_PORTSTATUS_C_RESET) {
@@ -979,7 +963,10 @@ reset:
 			}
 
 			/* check for timeout */
-			if (osalOsGetSystemTimeX() - start > HAL_USBH_PORT_RESET_TIMEOUT) break;
+			if (osalOsGetSystemTimeX() - start > HAL_USBH_PORT_RESET_TIMEOUT) {
+				uwarnf("Port %d: reset timeout", port->number);
+				break;
+			}
 		}
 	}
 
@@ -987,8 +974,7 @@ reset:
 	goto abort;
 
 reset_success:
-
-	uinfo("Reset OK, recovery...");
+	uinfof("Port %d: Reset OK, recovery...", port->number);
 
 	/* reset recovery */
 	osalThreadSleepMilliseconds(100);
@@ -1005,19 +991,22 @@ reset_success:
 	usbhEPOpen(&port->device.ctrl);
 
 	/* device with default address (0), try enumeration */
-	if (_device_enumerate(&port->device)) {
+	if (_device_enumerate(&port->device) != HAL_SUCCESS) {
 		/* enumeration failed */
 		usbhEPClose(&port->device.ctrl);
 
-		if (!--retries)
+		if (!--retries) {
+			uwarnf("Port %d: enumeration failed; abort", port->number);
 			goto abort;
+		}
 
 		/* retry reset & enumeration */
+		uwarnf("Port %d: enumeration failed; retry reset & enumeration", port->number);
 		goto reset;
 	}
 
 	/* load the default language ID */
-	uinfo("Loading langID0...");
+	uinfof("Port %d: Loading langID0...", port->number);
 	if (!usbhStdReqGetStringDescriptor(&port->device, 0, 0,
 			USBH_DT_STRING_SIZE, (uint8_t *)&strdesc)
 		&& (strdesc.bLength >= 4)
@@ -1025,12 +1014,12 @@ reset_success:
 			4, (uint8_t *)&strdesc)) {
 
 		port->device.langID0 = strdesc.wData[0];
-		uinfof("langID0=%04x", port->device.langID0);
+		uinfof("Port %d: langID0=%04x", port->number, port->device.langID0);
 	}
 
 	/* check if the device has only one configuration */
 	if (port->device.devDesc.bNumConfigurations == 1) {
-		uinfo("Device has only one configuration");
+		uinfof("Port %d: device has only one configuration", port->number);
 		_device_configure(&port->device, 0);
 	}
 
@@ -1038,7 +1027,7 @@ reset_success:
 	return;
 
 abort:
-	uerr("Abort");
+	uerrf("Port %d: abort", port->number);
 	port->device.status = USBH_DEVSTATUS_DISCONNECTED;
 }
 
@@ -1046,14 +1035,14 @@ void _usbh_port_disconnected(usbh_port_t *port) {
 	if (port->device.status == USBH_DEVSTATUS_DISCONNECTED)
 		return;
 
-	uinfo("Port disconnected");
+	uinfof("Port %d: disconnected", port->number);
 
 	/* unload drivers */
 	while (port->device.drivers) {
 		usbh_baseclassdriver_t *drv = port->device.drivers;
 
 		/* unload */
-		uinfof("Unload driver %s", drv->info->name);
+		uinfof("Port %d: unload driver %s", port->number, drv->info->name);
 		drv->info->vmt->unload(drv);
 
 		/* unlink */
@@ -1062,9 +1051,7 @@ void _usbh_port_disconnected(usbh_port_t *port) {
 	}
 
 	/* close control endpoint */
-	osalSysLock();
-	usbhEPCloseS(&port->device.ctrl);
-	osalSysUnlock();
+	usbhEPClose(&port->device.ctrl);
 
 	/* free address */
 	if (port->device.address)
@@ -1076,9 +1063,8 @@ void _usbh_port_disconnected(usbh_port_t *port) {
 }
 
 
-
 /*===========================================================================*/
-/* Hub processing functions.  	                                     		 */
+/* Hub processing functions.                                                 */
 /*===========================================================================*/
 
 #if HAL_USBH_USE_HUB
@@ -1086,7 +1072,7 @@ static void _hub_update_status(USBHDriver *host, USBHHubDriver *hub) {
 	uint32_t stat;
 	if (usbhhubControlRequest(host,
 			hub,
-			USBH_REQTYPE_IN | USBH_REQTYPE_CLASS | USBH_REQTYPE_DEVICE,
+			USBH_REQTYPE_DIR_IN | USBH_REQTYPE_TYPE_CLASS | USBH_REQTYPE_RECIP_DEVICE,
 			USBH_REQ_GET_STATUS,
 			0,
 			0,
@@ -1104,7 +1090,7 @@ static void _hub_process_status_change(USBHDriver *host, USBHHubDriver *hub) {
 	uinfo("Hub status change. GET_STATUS.");
 	_hub_update_status(host, hub);
 
-	if (hub->c_status & USBH_HUBSTATUS_C_HUB_LOCAL_POWER) {
+		if (hub->c_status & USBH_HUBSTATUS_C_HUB_LOCAL_POWER) {
 		hub->c_status &= ~USBH_HUBSTATUS_C_HUB_LOCAL_POWER;
 		uinfo("Clear USBH_HUB_FEAT_C_HUB_LOCAL_POWER");
 		usbhhubClearFeatureHub(host, hub, USBH_HUB_FEAT_C_HUB_LOCAL_POWER);
@@ -1122,7 +1108,6 @@ static uint32_t _hub_get_status_change_bitmap(USBHDriver *host, USBHHubDriver *h
 		osalSysLock();
 		uint32_t ret = hub->statuschange;
 		hub->statuschange = 0;
-		osalOsRescheduleS();
 		osalSysUnlock();
 		return ret;
 	}
@@ -1176,7 +1161,7 @@ static void _hub_process(USBHDriver *host) {
 #endif
 
 /*===========================================================================*/
-/* Main processing loop (enumeration, loading/unloading drivers, etc). 		 */
+/* Main processing loop (enumeration, loading/unloading drivers, etc).       */
 /*===========================================================================*/
 void usbhMainLoop(USBHDriver *usbh) {
 
@@ -1188,8 +1173,8 @@ void usbhMainLoop(USBHDriver *usbh) {
 	_hub_process(usbh, NULL);
 
 	/* process connected hubs */
-	USBHHubDriver *hub;
-    list_for_each_entry(hub, USBHHubDriver, &usbh->hubs, node) {
+	USBHHubDriver *hub, *temp;
+    list_for_each_entry_safe(hub, USBHHubDriver, temp, &usbh->hubs, node) {
 		_hub_process(usbh, hub);
 	}
 #else
@@ -1198,75 +1183,78 @@ void usbhMainLoop(USBHDriver *usbh) {
 #endif
 }
 
-
 /*===========================================================================*/
-/* IAD class driver.											 		 	 */
+/* Class driver loader.                                                      */
 /*===========================================================================*/
-#if HAL_USBH_USE_IAD
-static usbh_baseclassdriver_t *iad_load(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem);
-static void iad_unload(usbh_baseclassdriver_t *drv);
-static const usbh_classdriver_vmt_t usbhiadClassDriverVMT = {
-	iad_load,
-	iad_unload
-};
-static const usbh_classdriverinfo_t usbhiadClassDriverInfo = {
-	0xef, 0x02, 0x01, "IAD", &usbhiadClassDriverVMT
-};
 
-static usbh_baseclassdriver_t *iad_load(usbh_device_t *dev,
-		const uint8_t *descriptor, uint16_t rem) {
-	(void)rem;
+bool _usbh_match_vid_pid(usbh_device_t *dev, int32_t vid, int32_t pid) {
+	if (((vid < 0) || (dev->devDesc.idVendor == vid))
+		&& ((pid < 0) || (dev->devDesc.idProduct == pid)))
+		return HAL_SUCCESS;
 
-	if (descriptor[1] != USBH_DT_DEVICE)
-		return 0;
+	return HAL_FAILED;
+}
 
-	uinfo("Load a driver for each IF collection.");
+bool _usbh_match_descriptor(const uint8_t *descriptor, uint16_t rem,
+		int16_t type, int16_t _class, int16_t subclass, int16_t protocol) {
 
-	generic_iterator_t icfg;
-	if_iterator_t iif;
-	const usbh_ia_descriptor_t *last_iad = 0;
+	int16_t dclass, dsubclass, dprotocol;
 
-	cfg_iter_init(&icfg, dev->fullConfigurationDescriptor,
-			dev->basicConfigDesc.wTotalLength);
-	if (!icfg.valid) {
-		uerr("Invalid configuration descriptor.");
-		return 0;
-	}
+	if ((rem < descriptor[0]) || (rem < 2))
+		return HAL_FAILED;
 
-	for (if_iter_init(&iif, &icfg); iif.valid; if_iter_next(&iif)) {
-		if (iif.iad && (iif.iad != last_iad)) {
-			last_iad = iif.iad;
-			if (_classdriver_load(dev, iif.iad->bFunctionClass,
-					iif.iad->bFunctionSubClass,
-					iif.iad->bFunctionProtocol,
-					(uint8_t *)iif.iad,
-					(uint8_t *)iif.curr - (uint8_t *)iif.iad + iif.rem) != HAL_SUCCESS) {
-				uwarnf("No drivers found for IF collection #%d:%d",
-						iif.iad->bFirstInterface,
-						iif.iad->bFirstInterface + iif.iad->bInterfaceCount - 1);
-			}
-		}
-	}
+	uint8_t dtype = descriptor[1];
 
-	return 0;
-}
+	if ((type >= 0) && (type != dtype))
+		return HAL_FAILED;
 
-static void iad_unload(usbh_baseclassdriver_t *drv) {
-	(void)drv;
-}
-#endif
+	switch (dtype) {
+	case USBH_DT_DEVICE: {
+		if (rem < USBH_DT_DEVICE_SIZE)
+			return HAL_FAILED;
+		const usbh_device_descriptor_t *const desc = (const usbh_device_descriptor_t *)descriptor;
+		dclass = desc->bDeviceClass;
+		dsubclass = desc->bDeviceSubClass;
+		dprotocol = desc->bDeviceProtocol;
+	}	break;
+	case USBH_DT_INTERFACE: {
+		if (rem < USBH_DT_INTERFACE_SIZE)
+			return HAL_FAILED;
+		const usbh_interface_descriptor_t *const desc = (const usbh_interface_descriptor_t *)descriptor;
+		dclass = desc->bInterfaceClass;
+		dsubclass = desc->bInterfaceSubClass;
+		dprotocol = desc->bInterfaceProtocol;
+	}	break;
+	case USBH_DT_INTERFACE_ASSOCIATION: {
+		if (rem < USBH_DT_INTERFACE_ASSOCIATION_SIZE)
+			return HAL_FAILED;
+		const usbh_ia_descriptor_t *const desc = (const usbh_ia_descriptor_t *)descriptor;
+		dclass = desc->bFunctionClass;
+		dsubclass = desc->bFunctionSubClass;
+		dprotocol = desc->bFunctionProtocol;
+	}	break;
+	default:
+		return HAL_FAILED;
+	}
 
+	if (((_class < 0) || (_class == dclass))
+		&& ((subclass < 0) || (subclass == dsubclass))
+		&& ((protocol < 0) || (protocol == dprotocol)))
+		return HAL_SUCCESS;
 
-/*===========================================================================*/
-/* Class driver loader.											 		 	 */
-/*===========================================================================*/
+	return HAL_FAILED;
+}
 
 static const usbh_classdriverinfo_t *usbh_classdrivers_lookup[] = {
+#if HAL_USBH_USE_ADDITIONAL_CLASS_DRIVERS
+	/* user-defined out of tree class drivers */
+	HAL_USBH_ADDITIONAL_CLASS_DRIVERS
+#endif
 #if HAL_USBH_USE_FTDI
 	&usbhftdiClassDriverInfo,
 #endif
-#if HAL_USBH_USE_IAD
-	&usbhiadClassDriverInfo,
+#if HAL_USBH_USE_HUB
+	&usbhhubClassDriverInfo,
 #endif
 #if HAL_USBH_USE_UVC
 	&usbhuvcClassDriverInfo,
@@ -1274,48 +1262,39 @@ static const usbh_classdriverinfo_t *usbh_classdrivers_lookup[] = {
 #if HAL_USBH_USE_MSD
 	&usbhmsdClassDriverInfo,
 #endif
-#if HAL_USBH_USE_HUB
-	&usbhhubClassDriverInfo
+#if HAL_USBH_USE_HID
+	&usbhhidClassDriverInfo,
+#endif
+#if HAL_USBH_USE_UVC
+	&usbhuvcClassDriverInfo,
+#endif
+#if HAL_USBH_USE_AOA
+	&usbhaoaClassDriverInfo,	/* Leave always last */
 #endif
 };
 
-static bool _classdriver_load(usbh_device_t *dev, uint8_t class,
-		uint8_t subclass, uint8_t protocol, uint8_t *descbuff, uint16_t rem) {
+static bool _classdriver_load(usbh_device_t *dev, uint8_t *descbuff, uint16_t rem) {
 	uint8_t i;
 	usbh_baseclassdriver_t *drv = NULL;
 	for (i = 0; i < sizeof_array(usbh_classdrivers_lookup); i++) {
 		const usbh_classdriverinfo_t *const info = usbh_classdrivers_lookup[i];
-		if (class == 0xff) {
-			/* vendor specific */
-			if (info->class == 0xff) {
-				uinfof("Try load vendor-specific driver %s", info->name);
-				drv = info->vmt->load(dev, descbuff, rem);
-				if (drv != NULL)
-					goto success;
-			}
-		} else if ((info->class < 0) || ((info->class == class)
-			&& ((info->subclass < 0) || ((info->subclass == subclass)
-			&& ((info->protocol < 0) || (info->protocol == protocol)))))) {
-			uinfof("Try load driver %s", info->name);
-			drv = info->vmt->load(dev, descbuff, rem);
 
-#if HAL_USBH_USE_IAD
-			/* special case: */
-			if (info == &usbhiadClassDriverInfo)
-				return HAL_SUCCESS;
-#endif
+		uinfof("Try load driver %s", info->name);
+		drv = info->vmt->load(dev, descbuff, rem);
 
-			if (drv != NULL)
-				goto success;
-		}
+		if (drv != NULL)
+			goto success;
 	}
+
 	return HAL_FAILED;
 
 success:
 	/* Link this driver to the device */
-	drv->next = dev->drivers;
-	dev->drivers = drv;
-	drv->dev = dev;
+	if (!drv->dev) {
+		drv->next = dev->drivers;
+		dev->drivers = drv;
+		drv->dev = dev;
+	}
 	return HAL_SUCCESS;
 }
 
@@ -1347,13 +1326,16 @@ static void _classdriver_process_device(usbh_device_t *dev) {
 	usbhDevicePrintConfiguration(dev->fullConfigurationDescriptor,
 			dev->basicConfigDesc.wTotalLength);
 
-	if (devdesc->bDeviceClass == 0) {
-		/* each interface defines its own device class/subclass/protocol */
-		uinfo("Load a driver for each IF.");
+#if HAL_USBH_USE_IAD
+	if (dev->devDesc.bDeviceClass == 0xef
+			&& dev->devDesc.bDeviceSubClass == 0x02
+			&& dev->devDesc.bDeviceProtocol == 0x01) {
+
+		uinfo("Load a driver for each IF collection.");
 
 		generic_iterator_t icfg;
 		if_iterator_t iif;
-		uint8_t last_if = 0xff;
+		const usbh_ia_descriptor_t *last_iad = 0;
 
 		cfg_iter_init(&icfg, dev->fullConfigurationDescriptor,
 				dev->basicConfigDesc.wTotalLength);
@@ -1363,24 +1345,49 @@ static void _classdriver_process_device(usbh_device_t *dev) {
 		}
 
 		for (if_iter_init(&iif, &icfg); iif.valid; if_iter_next(&iif)) {
-			const usbh_interface_descriptor_t *const ifdesc = if_get(&iif);
-			if (ifdesc->bInterfaceNumber != last_if) {
-				last_if = ifdesc->bInterfaceNumber;
-				if (_classdriver_load(dev, ifdesc->bInterfaceClass,
-						ifdesc->bInterfaceSubClass,
-						ifdesc->bInterfaceProtocol,
-						(uint8_t *)ifdesc, iif.rem) != HAL_SUCCESS) {
-					uwarnf("No drivers found for IF #%d", ifdesc->bInterfaceNumber);
+			if (iif.iad && (iif.iad != last_iad)) {
+				last_iad = iif.iad;
+				if (_classdriver_load(dev,
+						(uint8_t *)iif.iad,
+						(uint8_t *)iif.curr - (uint8_t *)iif.iad + iif.rem) != HAL_SUCCESS) {
+					uwarnf("No drivers found for IF collection #%d:%d",
+							iif.iad->bFirstInterface,
+							iif.iad->bFirstInterface + iif.iad->bInterfaceCount - 1);
 				}
 			}
 		}
 
-	} else {
-		if (_classdriver_load(dev, devdesc->bDeviceClass,
-				devdesc->bDeviceSubClass,
-				devdesc->bDeviceProtocol,
-				(uint8_t *)devdesc, USBH_DT_DEVICE_SIZE) != HAL_SUCCESS) {
-			uwarn("No drivers found.");
+	} else
+#endif
+	if (_classdriver_load(dev, (uint8_t *)devdesc, USBH_DT_DEVICE_SIZE) != HAL_SUCCESS) {
+		uinfo("No drivers found for device.");
+
+		if (devdesc->bDeviceClass == 0) {
+			/* each interface defines its own device class/subclass/protocol */
+			uinfo("Try load a driver for each IF.");
+
+			generic_iterator_t icfg;
+			if_iterator_t iif;
+			uint8_t last_if = 0xff;
+
+			cfg_iter_init(&icfg, dev->fullConfigurationDescriptor,
+					dev->basicConfigDesc.wTotalLength);
+			if (!icfg.valid) {
+				uerr("Invalid configuration descriptor.");
+				goto exit;
+			}
+
+			for (if_iter_init(&iif, &icfg); iif.valid; if_iter_next(&iif)) {
+				const usbh_interface_descriptor_t *const ifdesc = if_get(&iif);
+				if (ifdesc->bInterfaceNumber != last_if) {
+					last_if = ifdesc->bInterfaceNumber;
+					if (_classdriver_load(dev, (uint8_t *)ifdesc, iif.rem) != HAL_SUCCESS) {
+						uwarnf("No drivers found for IF #%d", ifdesc->bInterfaceNumber);
+					}
+				}
+			}
+		} else {
+			uwarn("Unable to load driver.");
 		}
 	}
 
@@ -1390,6 +1397,15 @@ exit:
 	}
 }
 
+void usbhInit(void) {
+	uint8_t i;
+	for (i = 0; i < sizeof_array(usbh_classdrivers_lookup); i++) {
+		if (usbh_classdrivers_lookup[i]->vmt->init) {
+			usbh_classdrivers_lookup[i]->vmt->init();
+		}
+	}
+	usbh_lld_init();
+}
 
 #endif
 
diff --git a/os/hal/src/usbh/TODO.txt b/os/hal/src/usbh/TODO.txt
new file mode 100644
index 0000000..87269be
--- /dev/null
+++ b/os/hal/src/usbh/TODO.txt
@@ -0,0 +1,21 @@
+In decreasing order of priority:
+
+Bugs:
+- Synchronization on driver unload between usbhMainLoop and driver APIs
+    - MSD: ok
+    - AOA: not done
+    - HUB: ok
+    - FTDI: not done
+    - HID: ok
+    - UVC: not done
+
+
+Enhancements:
+- Way to return error from the load() functions in order to stop the enumeration process
+- Event sources from the low-level driver, in order to know when to call usbhMainLoop (from the low-level driver and from the HUB driver status callback)
+- Possibility of internal main loop
+- Linked list for drivers for dynamic registration
+- A way to automate matching (similar to linux)
+- Hooks to override driver loading and to inform the user of problems
+- for STM32 LLD: think of a way to prevent Bulk IN NAK interrupt flood.
+- Integrate VBUS power switching functionality to the API.
diff --git a/os/hal/src/usbh/hal_usbh_aoa.c b/os/hal/src/usbh/hal_usbh_aoa.c
new file mode 100644
index 0000000..d565595
--- /dev/null
+++ b/os/hal/src/usbh/hal_usbh_aoa.c
@@ -0,0 +1,671 @@
+/*
+    ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio
+              Copyright (C) 2015..2017 Diego Ismirlian, (dismirlian (at) google's mail)
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USBH_USE_AOA
+
+#if !HAL_USE_USBH
+#error "USBHAOA needs USBH"
+#endif
+
+#include <string.h>
+#include "usbh/dev/aoa.h"
+#include "usbh/internal.h"
+
+//#pragma GCC optimize("Og")
+
+
+#if USBHAOA_DEBUG_ENABLE_TRACE
+#define udbgf(f, ...)  usbDbgPrintf(f, ##__VA_ARGS__)
+#define udbg(f, ...)  usbDbgPuts(f, ##__VA_ARGS__)
+#else
+#define udbgf(f, ...)  do {} while(0)
+#define udbg(f, ...)   do {} while(0)
+#endif
+
+#if USBHAOA_DEBUG_ENABLE_INFO
+#define uinfof(f, ...)  usbDbgPrintf(f, ##__VA_ARGS__)
+#define uinfo(f, ...)  usbDbgPuts(f, ##__VA_ARGS__)
+#else
+#define uinfof(f, ...)  do {} while(0)
+#define uinfo(f, ...)   do {} while(0)
+#endif
+
+#if USBHAOA_DEBUG_ENABLE_WARNINGS
+#define uwarnf(f, ...)  usbDbgPrintf(f, ##__VA_ARGS__)
+#define uwarn(f, ...)  usbDbgPuts(f, ##__VA_ARGS__)
+#else
+#define uwarnf(f, ...)  do {} while(0)
+#define uwarn(f, ...)   do {} while(0)
+#endif
+
+#if USBHAOA_DEBUG_ENABLE_ERRORS
+#define uerrf(f, ...)  usbDbgPrintf(f, ##__VA_ARGS__)
+#define uerr(f, ...)  usbDbgPuts(f, ##__VA_ARGS__)
+#else
+#define uerrf(f, ...)  do {} while(0)
+#define uerr(f, ...)   do {} while(0)
+#endif
+
+
+/*===========================================================================*/
+/* Constants													 		 	 */
+/*===========================================================================*/
+
+#if !defined(HAL_USBHAOA_DEFAULT_MANUFACTURER)
+#define HAL_USBHAOA_DEFAULT_MANUFACTURER   "ChibiOS"
+#endif
+
+#if !defined(HAL_USBHAOA_DEFAULT_MODEL)
+#define HAL_USBHAOA_DEFAULT_MODEL          "USBH AOA Driver"
+#endif
+
+#if !defined(HAL_USBHAOA_DEFAULT_DESCRIPTION)
+#define HAL_USBHAOA_DEFAULT_DESCRIPTION    "ChibiOS USBH AOA Driver"
+#endif
+
+#if !defined(HAL_USBHAOA_DEFAULT_VERSION)
+#define HAL_USBHAOA_DEFAULT_VERSION        CH_KERNEL_VERSION
+#endif
+
+#if !defined(HAL_USBHAOA_DEFAULT_URI)
+#define HAL_USBHAOA_DEFAULT_URI            NULL
+#endif
+
+#if !defined(HAL_USBHAOA_DEFAULT_SERIAL)
+#define HAL_USBHAOA_DEFAULT_SERIAL         NULL
+#endif
+
+#if !defined(HAL_USBHAOA_DEFAULT_AUDIO_MODE)
+#define HAL_USBHAOA_DEFAULT_AUDIO_MODE	   USBHAOA_AUDIO_MODE_DISABLED
+#endif
+
+#define AOA_GOOGLE_VID 	        			0x18D1
+#define AOA_GOOGLE_PID_ACCESSORY    		0x2D00
+#define AOA_GOOGLE_PID_ACCESSORY_ABD    	0x2D01
+#define AOA_GOOGLE_PID_AUDIO    			0x2D02
+#define AOA_GOOGLE_PID_AUDIO_ABD    		0x2D03
+#define AOA_GOOGLE_PID_ACCESSORY_AUDIO    	0x2D04
+#define AOA_GOOGLE_PID_ACCESSORY_AUDIO_ABD  0x2D05
+
+#define AOA_ACCESSORY_GET_PROTOCOL          51
+#define AOA_ACCESSORY_SEND_STRING           52
+#define AOA_ACCESSORY_START                 53
+
+#define AOA_SET_AUDIO_MODE					58
+
+static bool _get_protocol(usbh_device_t *dev, uint16_t *protocol);
+static bool _accessory_start(usbh_device_t *dev);
+static bool _set_audio_mode(usbh_device_t *dev, uint16_t mode);
+static bool _send_string(usbh_device_t *dev, uint8_t index, const char *string);
+
+
+static void _stop_channelS(USBHAOAChannel *aoacp);
+
+/*===========================================================================*/
+/* USB Class driver loader for AOA								 		 	 */
+/*===========================================================================*/
+USBHAOADriver USBHAOAD[HAL_USBHAOA_MAX_INSTANCES];
+
+static usbh_baseclassdriver_t *_aoa_load(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem);
+static void _aoa_unload(usbh_baseclassdriver_t *drv);
+static void _aoa_init(void);
+
+static const usbh_classdriver_vmt_t class_driver_vmt = {
+	_aoa_init,
+	_aoa_load,
+	_aoa_unload
+};
+
+const usbh_classdriverinfo_t usbhaoaClassDriverInfo = {
+	"AOA", &class_driver_vmt
+};
+
+#if defined(HAL_USBHAOA_FILTER_CALLBACK)
+extern usbhaoa_filter_callback_t HAL_USBHAOA_FILTER_CALLBACK;
+#endif
+
+static usbh_baseclassdriver_t *_aoa_load(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem) {
+	int i;
+	USBHAOADriver *aoap;
+
+	if (dev->devDesc.idVendor != AOA_GOOGLE_VID) {
+		uint16_t protocol;
+		static USBHAOAConfig config = {
+			{
+				HAL_USBHAOA_DEFAULT_MANUFACTURER,
+				HAL_USBHAOA_DEFAULT_MODEL,
+				HAL_USBHAOA_DEFAULT_DESCRIPTION,
+				HAL_USBHAOA_DEFAULT_VERSION,
+				HAL_USBHAOA_DEFAULT_URI,
+				HAL_USBHAOA_DEFAULT_SERIAL
+			},
+
+			{
+				HAL_USBHAOA_DEFAULT_AUDIO_MODE,
+			}
+		};
+
+		uinfo("AOA: Unrecognized VID");
+
+#if defined(HAL_USBHAOA_FILTER_CALLBACK)
+		if (!HAL_USBHAOA_FILTER_CALLBACK(dev, descriptor, rem, &config)) {
+			return NULL;
+		}
+#endif
+
+		uinfo("AOA: Try if it's an Android device");
+		if (_get_protocol(dev, &protocol) != HAL_SUCCESS) {
+			return NULL;
+		}
+		uinfof("AOA: Possible Android device found (protocol=%d)", protocol);
+
+		if (config.channel.manufacturer != NULL) {
+			if ((_send_string(dev, USBHAOA_ACCESSORY_STRING_MANUFACTURER, config.channel.manufacturer) != HAL_SUCCESS)
+				|| (_send_string(dev, USBHAOA_ACCESSORY_STRING_MODEL, config.channel.model) != HAL_SUCCESS)
+				|| (_send_string(dev, USBHAOA_ACCESSORY_STRING_DESCRIPTION, config.channel.description) != HAL_SUCCESS)
+				|| (_send_string(dev, USBHAOA_ACCESSORY_STRING_VERSION, config.channel.version) != HAL_SUCCESS)
+				|| (_send_string(dev, USBHAOA_ACCESSORY_STRING_URI, config.channel.uri) != HAL_SUCCESS)
+				|| (_send_string(dev, USBHAOA_ACCESSORY_STRING_SERIAL, config.channel.serial) != HAL_SUCCESS)) {
+				uerr("AOA: Can't send string; abort start");
+				return NULL;
+			}
+		}
+
+		if (protocol > 1) {
+			if (_set_audio_mode(dev, (uint16_t)(config.audio.mode)) != HAL_SUCCESS) {
+				uerr("AOA: Can't set audio mode; abort channel start");
+				return NULL;
+			}
+		}
+
+		if (_accessory_start(dev) != HAL_SUCCESS) {
+			uerr("AOA: Can't start accessory; abort channel start");
+		}
+
+		return NULL;
+	}
+
+	/* AOAv2:
+		0x2D00	accessory				Provides two bulk endpoints for communicating with an Android application.
+		0x2D01	accessory + adb			For debugging purposes during accessory development. Available only if the user has enabled USB Debugging in the Android device settings.
+		0x2D02	audio					For streaming audio from an Android device to an accessory.
+		0x2D03	audio + adb
+		0x2D04	accessory + audio
+		0x2D05  accessory + audio + adb
+	*/
+
+	switch (dev->devDesc.idProduct) {
+	case AOA_GOOGLE_PID_ACCESSORY:
+	case AOA_GOOGLE_PID_ACCESSORY_ABD:
+//	case AOA_GOOGLE_PID_AUDIO:
+//	case AOA_GOOGLE_PID_AUDIO_ABD:
+	case AOA_GOOGLE_PID_ACCESSORY_AUDIO:
+	case AOA_GOOGLE_PID_ACCESSORY_AUDIO_ABD:
+		break;
+	default:
+		uerr("AOA: Unrecognized PID");
+		return NULL;
+	}
+
+	const usbh_interface_descriptor_t * const ifdesc = (const usbh_interface_descriptor_t *)descriptor;
+	if ((_usbh_match_descriptor(descriptor, rem, USBH_DT_INTERFACE, 0xFF, 0xFF, 0x00) != HAL_SUCCESS)
+			|| (ifdesc->bNumEndpoints < 2)) {
+		uerr("AOA: This IF is not the Accessory IF");
+		return NULL;
+	}
+
+	uinfof("AOA: Found Accessory Interface #%d", ifdesc->bInterfaceNumber);
+
+	for (i = 0; i < HAL_USBHAOA_MAX_INSTANCES; i++) {
+		if (USBHAOAD[i].dev == NULL) {
+			aoap = &USBHAOAD[i];
+			goto alloc_ok;
+		}
+	}
+
+	uwarn("AOA: Can't alloc driver");
+
+	/* can't alloc */
+	return NULL;
+
+alloc_ok:
+	/* initialize the driver's variables */
+	usbhEPSetName(&dev->ctrl, "AOA[CTRL]");
+	aoap->state = USBHAOA_STATE_ACTIVE;
+
+	generic_iterator_t iep;
+	if_iterator_t iif;
+	iif.iad = 0;
+	iif.curr = descriptor;
+	iif.rem = rem;
+
+	aoap->channel.epin.status = USBH_EPSTATUS_UNINITIALIZED;
+	aoap->channel.epout.status = USBH_EPSTATUS_UNINITIALIZED;
+
+	for (ep_iter_init(&iep, &iif); iep.valid; ep_iter_next(&iep)) {
+		const usbh_endpoint_descriptor_t *const epdesc = ep_get(&iep);
+		if ((epdesc->bEndpointAddress & 0x80) && (epdesc->bmAttributes == USBH_EPTYPE_BULK)) {
+			uinfof("AOA: BULK IN endpoint found: bEndpointAddress=%02x", epdesc->bEndpointAddress);
+			usbhEPObjectInit(&aoap->channel.epin, dev, epdesc);
+			usbhEPSetName(&aoap->channel.epin, "AOA[BIN ]");
+		} else if (((epdesc->bEndpointAddress & 0x80) == 0)
+				&& (epdesc->bmAttributes == USBH_EPTYPE_BULK)) {
+			uinfof("AOA: BULK OUT endpoint found: bEndpointAddress=%02x", epdesc->bEndpointAddress);
+			usbhEPObjectInit(&aoap->channel.epout, dev, epdesc);
+			usbhEPSetName(&aoap->channel.epout, "AOA[BOUT]");
+		} else {
+			uinfof("AOA: unsupported endpoint found: bEndpointAddress=%02x, bmAttributes=%02x",
+				epdesc->bEndpointAddress, epdesc->bmAttributes);
+		}
+	}
+
+	if ((aoap->channel.epin.status != USBH_EPSTATUS_CLOSED)
+		|| (aoap->channel.epout.status != USBH_EPSTATUS_CLOSED)) {
+		uwarn("AOA: Couldn't find endpoints");
+		aoap->state = USBHAOA_STATE_STOP;
+		return NULL;
+	}
+
+	aoap->state = USBHAOA_STATE_READY;
+	aoap->channel.state = USBHAOA_CHANNEL_STATE_ACTIVE;
+	uwarn("AOA: Ready");
+	return (usbh_baseclassdriver_t *)aoap;
+}
+
+static void _aoa_unload(usbh_baseclassdriver_t *drv) {
+	osalDbgCheck(drv != NULL);
+	USBHAOADriver *const aoap = (USBHAOADriver *)drv;
+	osalSysLock();
+	_stop_channelS(&aoap->channel);
+	aoap->channel.state = USBHAOA_CHANNEL_STATE_STOP;
+	aoap->state = USBHAOA_STATE_STOP;
+	osalSysUnlock();
+}
+
+/* ------------------------------------ */
+/*      Accessory data channel          */
+/* ------------------------------------ */
+
+static void _submitOutI(USBHAOAChannel *aoacp, uint32_t len) {
+	udbgf("AOA: Submit OUT %d", len);
+	aoacp->oq_urb.requestedLength = len;
+	usbhURBObjectResetI(&aoacp->oq_urb);
+	usbhURBSubmitI(&aoacp->oq_urb);
+}
+
+static void _out_cb(usbh_urb_t *urb) {
+	USBHAOAChannel *const aoacp = (USBHAOAChannel *)urb->userData;
+	switch (urb->status) {
+	case USBH_URBSTATUS_OK:
+		aoacp->oq_ptr = aoacp->oq_buff;
+		aoacp->oq_counter = 64;
+		chThdDequeueNextI(&aoacp->oq_waiting, Q_OK);
+		chnAddFlagsI(aoacp, CHN_OUTPUT_EMPTY | CHN_TRANSMISSION_END);
+		return;
+	case USBH_URBSTATUS_DISCONNECTED:
+		uwarn("AOA: URB OUT disconnected");
+		chThdDequeueNextI(&aoacp->oq_waiting, Q_RESET);
+		chnAddFlagsI(aoacp, CHN_OUTPUT_EMPTY);
+		return;
+	default:
+		uerrf("AOA: URB OUT status unexpected = %d", urb->status);
+		break;
+	}
+	usbhURBObjectResetI(&aoacp->oq_urb);
+	usbhURBSubmitI(&aoacp->oq_urb);
+}
+
+static size_t _write_timeout(USBHAOAChannel *aoacp, const uint8_t *bp,
+		size_t n, systime_t timeout) {
+	chDbgCheck(n > 0U);
+
+	size_t w = 0;
+	osalSysLock();
+	while (true) {
+		if (aoacp->state != USBHAOA_CHANNEL_STATE_READY) {
+			osalSysUnlock();
+			return w;
+		}
+		while (usbhURBIsBusy(&aoacp->oq_urb)) {
+			if (chThdEnqueueTimeoutS(&aoacp->oq_waiting, timeout) != Q_OK) {
+				osalSysUnlock();
+				return w;
+			}
+		}
+
+		*aoacp->oq_ptr++ = *bp++;
+		if (--aoacp->oq_counter == 0) {
+			_submitOutI(aoacp, 64);
+			osalOsRescheduleS();
+		}
+		osalSysUnlock(); /* Gives a preemption chance in a controlled point.*/
+
+		w++;
+		if (--n == 0U)
+			return w;
+
+		osalSysLock();
+	}
+}
+
+static msg_t _put_timeout(USBHAOAChannel *aoacp, uint8_t b, systime_t timeout) {
+
+	osalSysLock();
+	if (aoacp->state != USBHAOA_CHANNEL_STATE_READY) {
+		osalSysUnlock();
+		return Q_RESET;
+	}
+
+	while (usbhURBIsBusy(&aoacp->oq_urb)) {
+		msg_t msg = chThdEnqueueTimeoutS(&aoacp->oq_waiting, timeout);
+		if (msg < Q_OK) {
+			osalSysUnlock();
+			return msg;
+		}
+	}
+
+	*aoacp->oq_ptr++ = b;
+	if (--aoacp->oq_counter == 0) {
+		_submitOutI(aoacp, 64);
+		osalOsRescheduleS();
+	}
+	osalSysUnlock();
+	return Q_OK;
+}
+
+static size_t _write(USBHAOAChannel *aoacp, const uint8_t *bp, size_t n) {
+	return _write_timeout(aoacp, bp, n, TIME_INFINITE);
+}
+
+static msg_t _put(USBHAOAChannel *aoacp, uint8_t b) {
+	return _put_timeout(aoacp, b, TIME_INFINITE);
+}
+
+static void _submitInI(USBHAOAChannel *aoacp) {
+	udbg("AOA: Submit IN");
+	usbhURBObjectResetI(&aoacp->iq_urb);
+	usbhURBSubmitI(&aoacp->iq_urb);
+}
+
+static void _in_cb(usbh_urb_t *urb) {
+	USBHAOAChannel *const aoacp = (USBHAOAChannel *)urb->userData;
+	switch (urb->status) {
+	case USBH_URBSTATUS_OK:
+		if (urb->actualLength == 0) {
+			udbgf("AOA: URB IN no data");
+		} else {
+			udbgf("AOA: URB IN data len=%d", urb->actualLength);
+			aoacp->iq_ptr = aoacp->iq_buff;
+			aoacp->iq_counter = urb->actualLength;
+			chThdDequeueNextI(&aoacp->iq_waiting, Q_OK);
+			chnAddFlagsI(aoacp, CHN_INPUT_AVAILABLE);
+		}
+		break;
+	case USBH_URBSTATUS_DISCONNECTED:
+		uwarn("AOA: URB IN disconnected");
+		chThdDequeueNextI(&aoacp->iq_waiting, Q_RESET);
+		break;
+	default:
+		uerrf("AOA: URB IN status unexpected = %d", urb->status);
+		_submitInI(aoacp);
+		break;
+	}
+}
+
+static size_t _read_timeout(USBHAOAChannel *aoacp, uint8_t *bp,
+		size_t n, systime_t timeout) {
+	size_t r = 0;
+
+	chDbgCheck(n > 0U);
+
+	osalSysLock();
+	while (true) {
+		if (aoacp->state != USBHAOA_CHANNEL_STATE_READY) {
+			osalSysUnlock();
+			return r;
+		}
+		while (aoacp->iq_counter == 0) {
+			if (!usbhURBIsBusy(&aoacp->iq_urb))
+				_submitInI(aoacp);
+			if (chThdEnqueueTimeoutS(&aoacp->iq_waiting, timeout) != Q_OK) {
+				osalSysUnlock();
+				return r;
+			}
+		}
+		*bp++ = *aoacp->iq_ptr++;
+		if (--aoacp->iq_counter == 0) {
+			_submitInI(aoacp);
+			osalOsRescheduleS();
+		}
+		osalSysUnlock();
+
+		r++;
+		if (--n == 0U)
+			return r;
+
+		osalSysLock();
+	}
+}
+
+static msg_t _get_timeout(USBHAOAChannel *aoacp, systime_t timeout) {
+	uint8_t b;
+
+	osalSysLock();
+	if (aoacp->state != USBHAOA_CHANNEL_STATE_READY) {
+		osalSysUnlock();
+		return Q_RESET;
+	}
+	while (aoacp->iq_counter == 0) {
+		if (!usbhURBIsBusy(&aoacp->iq_urb))
+			_submitInI(aoacp);
+		msg_t msg = chThdEnqueueTimeoutS(&aoacp->iq_waiting, timeout);
+		if (msg < Q_OK) {
+			osalSysUnlock();
+			return msg;
+		}
+	}
+	b = *aoacp->iq_ptr++;
+	if (--aoacp->iq_counter == 0) {
+		_submitInI(aoacp);
+		osalOsRescheduleS();
+	}
+	osalSysUnlock();
+
+	return (msg_t)b;
+}
+
+static msg_t _get(USBHAOAChannel *aoacp) {
+	return _get_timeout(aoacp, TIME_INFINITE);
+}
+
+static size_t _read(USBHAOAChannel *aoacp, uint8_t *bp, size_t n) {
+	return _read_timeout(aoacp, bp, n, TIME_INFINITE);
+}
+
+static const struct AOADriverVMT async_channel_vmt = {
+	(size_t (*)(void *, const uint8_t *, size_t))_write,
+	(size_t (*)(void *, uint8_t *, size_t))_read,
+	(msg_t (*)(void *, uint8_t))_put,
+	(msg_t (*)(void *))_get,
+	(msg_t (*)(void *, uint8_t, systime_t))_put_timeout,
+	(msg_t (*)(void *, systime_t))_get_timeout,
+	(size_t (*)(void *, const uint8_t *, size_t, systime_t))_write_timeout,
+	(size_t (*)(void *, uint8_t *, size_t, systime_t))_read_timeout
+};
+
+static void _stop_channelS(USBHAOAChannel *aoacp) {
+	if (aoacp->state != USBHAOA_CHANNEL_STATE_READY)
+		return;
+	uwarn("AOA: Stop channel");
+	chVTResetI(&aoacp->vt);
+	usbhEPCloseS(&aoacp->epin);
+	usbhEPCloseS(&aoacp->epout);
+	chThdDequeueAllI(&aoacp->iq_waiting, Q_RESET);
+	chThdDequeueAllI(&aoacp->oq_waiting, Q_RESET);
+	chnAddFlagsI(aoacp, CHN_DISCONNECTED);
+	aoacp->state = USBHAOA_CHANNEL_STATE_ACTIVE;
+	osalOsRescheduleS();
+}
+
+static void _vt(void *p) {
+	USBHAOAChannel *const aoacp = (USBHAOAChannel *)p;
+	osalSysLockFromISR();
+	uint32_t len = aoacp->oq_ptr - aoacp->oq_buff;
+	if (len && !usbhURBIsBusy(&aoacp->oq_urb)) {
+		_submitOutI(aoacp, len);
+	}
+	if ((aoacp->iq_counter == 0) && !usbhURBIsBusy(&aoacp->iq_urb)) {
+		_submitInI(aoacp);
+	}
+	chVTSetI(&aoacp->vt, OSAL_MS2I(16), _vt, aoacp);
+	osalSysUnlockFromISR();
+}
+
+void usbhaoaChannelStart(USBHAOADriver *aoap) {
+
+	osalDbgCheck(aoap);
+
+	USBHAOAChannel *const aoacp = (USBHAOAChannel *)&aoap->channel;
+
+	osalDbgCheck(aoap->state == USBHAOA_STATE_READY);
+
+	osalDbgCheck((aoacp->state == USBHAOA_CHANNEL_STATE_ACTIVE)
+			|| (aoacp->state == USBHAOA_CHANNEL_STATE_READY));
+
+	if (aoacp->state == USBHAOA_CHANNEL_STATE_READY)
+		return;
+
+	usbhURBObjectInit(&aoacp->oq_urb, &aoacp->epout, _out_cb, aoacp, aoacp->oq_buff, 0);
+	chThdQueueObjectInit(&aoacp->oq_waiting);
+	aoacp->oq_counter = 64;
+	aoacp->oq_ptr = aoacp->oq_buff;
+	usbhEPOpen(&aoacp->epout);
+
+	usbhURBObjectInit(&aoacp->iq_urb, &aoacp->epin, _in_cb, aoacp, aoacp->iq_buff, 64);
+	chThdQueueObjectInit(&aoacp->iq_waiting);
+	aoacp->iq_counter = 0;
+	aoacp->iq_ptr = aoacp->iq_buff;
+	usbhEPOpen(&aoacp->epin);
+	usbhURBSubmit(&aoacp->iq_urb);
+
+	chVTObjectInit(&aoacp->vt);
+	chVTSet(&aoacp->vt, OSAL_MS2I(16), _vt, aoacp);
+
+	aoacp->state = USBHAOA_CHANNEL_STATE_READY;
+
+	osalEventBroadcastFlags(&aoacp->event, CHN_CONNECTED | CHN_OUTPUT_EMPTY);
+}
+
+void usbhaoaChannelStop(USBHAOADriver *aoap) {
+	osalDbgCheck((aoap->channel.state == USBHAOA_CHANNEL_STATE_ACTIVE)
+			|| (aoap->channel.state == USBHAOA_CHANNEL_STATE_READY));
+	osalSysLock();
+	_stop_channelS(&aoap->channel);
+	osalSysUnlock();
+}
+
+/* ------------------------------------ */
+/*      General AOA functions           */
+/* ------------------------------------ */
+static bool _get_protocol(usbh_device_t *dev, uint16_t *protocol) {
+	USBH_DEFINE_BUFFER(uint16_t proto);
+
+	usbh_urbstatus_t ret = usbhControlRequest(dev,
+			USBH_REQTYPE_DIR_IN | USBH_REQTYPE_TYPE_VENDOR | USBH_REQTYPE_RECIP_DEVICE,
+			AOA_ACCESSORY_GET_PROTOCOL,
+			0,
+			0,
+			2,
+			(uint8_t *)&proto);
+
+	if ((ret != USBH_URBSTATUS_OK) || (proto > 2))
+		return HAL_FAILED;
+
+	*protocol = proto;
+	return HAL_SUCCESS;
+}
+
+static bool _accessory_start(usbh_device_t *dev) {
+	usbh_urbstatus_t ret = usbhControlRequest(dev,
+			USBH_REQTYPE_DIR_OUT | USBH_REQTYPE_TYPE_VENDOR | USBH_REQTYPE_RECIP_DEVICE,
+			AOA_ACCESSORY_START,
+			0,
+			0,
+			0,
+			NULL);
+
+	if (ret != USBH_URBSTATUS_OK)
+		return HAL_FAILED;
+
+	return HAL_SUCCESS;
+}
+
+static bool _set_audio_mode(usbh_device_t *dev, uint16_t mode) {
+	usbh_urbstatus_t ret = usbhControlRequest(dev,
+			USBH_REQTYPE_DIR_OUT | USBH_REQTYPE_TYPE_VENDOR | USBH_REQTYPE_RECIP_DEVICE,
+			AOA_SET_AUDIO_MODE,
+			mode,
+			0,
+			0,
+			NULL);
+
+	if (ret != USBH_URBSTATUS_OK)
+		return HAL_FAILED;
+
+	return HAL_SUCCESS;
+}
+
+static bool _send_string(usbh_device_t *dev, uint8_t index, const char *string)
+{
+	USBH_DEFINE_BUFFER(const char nullstr[1]) = {0};
+	if (string == NULL)
+		string = nullstr;
+
+	usbh_urbstatus_t ret = usbhControlRequest(dev,
+			USBH_REQTYPE_DIR_OUT | USBH_REQTYPE_TYPE_VENDOR | USBH_REQTYPE_RECIP_DEVICE,
+			AOA_ACCESSORY_SEND_STRING,
+			0,
+			index,
+			strlen(string) + 1,
+			(uint8_t *)string);
+
+	if (ret != USBH_URBSTATUS_OK)
+		return HAL_FAILED;
+
+	return HAL_SUCCESS;
+}
+
+static void _object_init(USBHAOADriver *aoap) {
+	osalDbgCheck(aoap != NULL);
+	memset(aoap, 0, sizeof(*aoap));
+	aoap->info = &usbhaoaClassDriverInfo;
+	aoap->state = USBHAOA_STATE_STOP;
+	aoap->channel.vmt = &async_channel_vmt;
+	osalEventObjectInit(&aoap->channel.event);
+	aoap->channel.state = USBHAOA_CHANNEL_STATE_STOP;
+}
+
+static void _aoa_init(void) {
+	uint8_t i;
+	for (i = 0; i < HAL_USBHAOA_MAX_INSTANCES; i++) {
+		_object_init(&USBHAOAD[i]);
+	}
+}
+
+#endif
diff --git a/os/hal/src/usbh/hal_usbh_debug.c b/os/hal/src/usbh/hal_usbh_debug.c
index 9f17189..d32f1c6 100644
--- a/os/hal/src/usbh/hal_usbh_debug.c
+++ b/os/hal/src/usbh/hal_usbh_debug.c
@@ -1,6 +1,6 @@
 /*
-    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
-              Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail)
+    ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio
+              Copyright (C) 2015..2017 Diego Ismirlian, (dismirlian (at) google's mail)
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -17,15 +17,13 @@
 
 #include "hal.h"
 
-#if HAL_USE_USBH
+#if HAL_USE_USBH && USBH_DEBUG_ENABLE
 
 #include "ch.h"
 #include "usbh/debug.h"
 #include <stdarg.h>
 #include "chprintf.h"
 
-#if USBH_DEBUG_ENABLE
-
 #define MAX_FILLER 11
 #define FLOAT_PRECISION 9
 #define MPRINTF_USE_FLOAT 0
@@ -108,17 +106,18 @@ static char *ftoa(char *p, double num, unsigned long precision, bool dot) {
 }
 #endif
 
-static inline void _put(char c) {
-	input_queue_t *iqp = &USBH_DEBUG_USBHD.iq;
-
-	if (chIQIsFullI(iqp))
-		return;
-
-	iqp->q_counter++;
+static inline void _wr(input_queue_t *iqp, char c) {
 	*iqp->q_wrptr++ = c;
 	if (iqp->q_wrptr >= iqp->q_top)
 		iqp->q_wrptr = iqp->q_buffer;
+}
 
+static inline void _put(char c) {
+	input_queue_t *iqp = &USBH_DEBUG_USBHD.iq;
+	if (sizeof(USBH_DEBUG_USBHD.dbg_buff) - iqp->q_counter <= 1)
+		return;
+	iqp->q_counter++;
+	_wr(iqp, c);
 }
 
 int _dbg_printf(const char *fmt, va_list ap) {
@@ -343,19 +342,39 @@ unsigned_common:
 
 }
 
-static void _print_hdr(void)
-{
+static systime_t first, last;
+static bool ena;
+static uint32_t hdr[2];
+
+static void _build_hdr(void) {
 	uint32_t hfnum = USBH_DEBUG_USBHD.otg->HFNUM;
 	uint16_t hfir = USBH_DEBUG_USBHD.otg->HFIR;
+	last = osalOsGetSystemTimeX();
+	if (ena) {
+		first = last;
+	}
 
-	_put(0xff);
-	_put(0xff);
-	_put(hfir & 0xff);
-	_put(hfir >> 8);
-	_put(hfnum & 0xff);
-	_put((hfnum >> 8) & 0xff);
-	_put((hfnum >> 16) & 0xff);
-	_put((hfnum >> 24) & 0xff);
+	if (((hfnum & 0x3fff) == 0x3fff) && (hfir == (hfnum >> 16))) {
+		hdr[0] = 0xfeff;
+		hdr[1] = last - first;
+		ena = FALSE;
+	} else {
+		hdr[0] = 0xffff | (hfir << 16);
+		hdr[1] = hfnum;
+		ena = TRUE;
+	}
+}
+
+static void _print_hdr(void)
+{
+	_put(hdr[0] & 0xff);
+	_put((hdr[0] >> 8) & 0xff);
+	_put((hdr[0] >> 16) & 0xff);
+	_put((hdr[0] >> 24) & 0xff);
+	_put(hdr[1] & 0xff);
+	_put((hdr[1] >> 8) & 0xff);
+	_put((hdr[1] >> 16) & 0xff);
+	_put((hdr[1] >> 24) & 0xff);
 }
 
 void usbDbgPrintf(const char *fmt, ...)
@@ -363,10 +382,16 @@ void usbDbgPrintf(const char *fmt, ...)
 	va_list ap;
 	va_start(ap, fmt);
 	syssts_t sts = chSysGetStatusAndLockX();
-	_print_hdr();
-	_dbg_printf(fmt, ap);
-	_put(0);
-	chThdDequeueNextI(&USBH_DEBUG_USBHD.iq.q_waiting, Q_OK);
+	input_queue_t *iqp = &USBH_DEBUG_USBHD.iq;
+	int rem = sizeof(USBH_DEBUG_USBHD.dbg_buff) - iqp->q_counter;
+	if (rem >= 9) {
+		_build_hdr();
+		_print_hdr();
+		_dbg_printf(fmt, ap);
+		iqp->q_counter++;
+		_wr(iqp, 0);
+		chThdDequeueNextI(&USBH_DEBUG_USBHD.iq.q_waiting, Q_OK);
+	}
 	chSysRestoreStatusX(sts);
 	va_end(ap);
 }
@@ -374,32 +399,28 @@ void usbDbgPrintf(const char *fmt, ...)
 
 void usbDbgPuts(const char *s)
 {
-	uint32_t buff[2] = {
-		0xffff | (USBH_DEBUG_USBHD.otg->HFIR << 16),
-		USBH_DEBUG_USBHD.otg->HFNUM
-	};
-	uint8_t *p = (uint8_t *)buff;
+	_build_hdr();
+	uint8_t *p = (uint8_t *)hdr;
 	uint8_t *top = p + 8;
 
 	syssts_t sts = chSysGetStatusAndLockX();
 	input_queue_t *iqp = &USBH_DEBUG_USBHD.iq;
 	int rem = sizeof(USBH_DEBUG_USBHD.dbg_buff) - iqp->q_counter;
-	while (rem) {
-		*iqp->q_wrptr++ = *p;
-		if (iqp->q_wrptr >= iqp->q_top)
-			iqp->q_wrptr = iqp->q_buffer;
-		rem--;
-		if (++p == top) break;
-	}
-	while (rem) {
-		*iqp->q_wrptr++ = *s;
-		if (iqp->q_wrptr >= iqp->q_top)
-			iqp->q_wrptr = iqp->q_buffer;
-		rem--;
-		if (!*s++) break;
+	if (rem >= 9) {
+		while (rem) {
+			_wr(iqp, *p);
+			if (++p == top) break;
+		}
+		rem -= 9;
+		while (rem && *s) {
+			_wr(iqp, *s);
+			rem--;
+			s++;
+		}
+		_wr(iqp, 0);
+		iqp->q_counter = sizeof(USBH_DEBUG_USBHD.dbg_buff) - rem;
+		chThdDequeueNextI(&USBH_DEBUG_USBHD.iq.q_waiting, Q_OK);
 	}
-	iqp->q_counter = sizeof(USBH_DEBUG_USBHD.dbg_buff) - rem;
-	chThdDequeueNextI(&USBH_DEBUG_USBHD.iq.q_waiting, Q_OK);
 	chSysRestoreStatusX(sts);
 }
 
@@ -407,8 +428,8 @@ void usbDbgReset(void) {
 	const char *msg = "\r\n\r\n==== DEBUG OUTPUT RESET ====\r\n";
 
 	syssts_t sts = chSysGetStatusAndLockX();
-	chIQResetI(&USBH_DEBUG_USBHD.iq);
-	chOQResetI(&USBH_DEBUG_SD.oqueue);
+	iqResetI(&USBH_DEBUG_USBHD.iq);
+	oqResetI(&USBH_DEBUG_SD.oqueue);
 	while (*msg) {
 		*USBH_DEBUG_SD.oqueue.q_wrptr++ = *msg++;
 		USBH_DEBUG_SD.oqueue.q_counter--;
@@ -431,8 +452,8 @@ void usbDbgSystemHalted(void) {
 		if (!((bool)((USBH_DEBUG_SD.oqueue.q_wrptr == USBH_DEBUG_SD.oqueue.q_rdptr) && (USBH_DEBUG_SD.oqueue.q_counter != 0U))))
 			break;
 		USBH_DEBUG_SD.oqueue.q_counter++;
-		while (!(USART1->SR & USART_SR_TXE));
-		USART1->DR = *USBH_DEBUG_SD.oqueue.q_rdptr++;
+		while (!(USBH_DEBUG_SD.usart->SR & USART_SR_TXE));
+		USBH_DEBUG_SD.usart->DR = *USBH_DEBUG_SD.oqueue.q_rdptr++;
 		if (USBH_DEBUG_SD.oqueue.q_rdptr >= USBH_DEBUG_SD.oqueue.q_top) {
 			USBH_DEBUG_SD.oqueue.q_rdptr = USBH_DEBUG_SD.oqueue.q_buffer;
 		}
@@ -458,57 +479,74 @@ void usbDbgSystemHalted(void) {
 			while (true) {
 				c = _get(); if (c < 0) return;
 				if (!c) {
-					while (!(USART1->SR & USART_SR_TXE));
-					USART1->DR = '\r';
-					while (!(USART1->SR & USART_SR_TXE));
-					USART1->DR = '\n';
+					while (!(USBH_DEBUG_SD.usart->SR & USART_SR_TXE));
+					USBH_DEBUG_SD.usart->DR = '\r';
+					while (!(USBH_DEBUG_SD.usart->SR & USART_SR_TXE));
+					USBH_DEBUG_SD.usart->DR = '\n';
 					state = 0;
 					break;
 				}
-				while (!(USART1->SR & USART_SR_TXE));
-				USART1->DR = c;
+				while (!(USBH_DEBUG_SD.usart->SR & USART_SR_TXE));
+				USBH_DEBUG_SD.usart->DR = c;
 			}
 		}
 	}
 }
 
-static void usb_debug_thread(void *p) {
-	USBHDriver *host = (USBHDriver *)p;
+static void usb_debug_thread(void *arg) {
+	USBHDriver *host = (USBHDriver *)arg;
 	uint8_t state = 0;
 
 	chRegSetThreadName("USBH_DBG");
 	while (true) {
-		msg_t c = chIQGet(&host->iq);
+		msg_t c = iqGet(&host->iq);
 		if (c < 0) goto reset;
 
 		if (state == 0) {
 			if (c == 0xff) state = 1;
 		} else if (state == 1) {
 			if (c == 0xff) state = 2;
+			else if (c == 0xfe) state = 3;
 			else (state = 0);
-		} else {
+		} else if (state == 2) {
 			uint16_t hfir;
 			uint32_t hfnum;
 
 			hfir = c;
-			c = chIQGet(&host->iq); if (c < 0) goto reset;
+			c = iqGet(&host->iq); if (c < 0) goto reset;
 			hfir |= c << 8;
 
-			c = chIQGet(&host->iq); if (c < 0) goto reset;
+			c = iqGet(&host->iq); if (c < 0) goto reset;
 			hfnum = c;
-			c = chIQGet(&host->iq); if (c < 0) goto reset;
+			c = iqGet(&host->iq); if (c < 0) goto reset;
 			hfnum |= c << 8;
-			c = chIQGet(&host->iq); if (c < 0) goto reset;
+			c = iqGet(&host->iq); if (c < 0) goto reset;
 			hfnum |= c << 16;
-			c = chIQGet(&host->iq); if (c < 0) goto reset;
+			c = iqGet(&host->iq); if (c < 0) goto reset;
 			hfnum |= c << 24;
 
 			uint32_t f = hfnum & 0xffff;
 			uint32_t p = 1000 - ((hfnum >> 16) / (hfir / 1000));
-			chprintf((BaseSequentialStream *)&USBH_DEBUG_SD, "%05d.%03d  ", f, p);
-
+			chprintf((BaseSequentialStream *)&USBH_DEBUG_SD, "%05d.%03d ", f, p);
+			state = 4;
+		} else if (state == 3) {
+			uint32_t t;
+
+			c = iqGet(&host->iq); if (c < 0) goto reset;
+			c = iqGet(&host->iq); if (c < 0) goto reset;
+
+			t = c;
+			c = iqGet(&host->iq); if (c < 0) goto reset;
+			t |= c << 8;
+			c = iqGet(&host->iq); if (c < 0) goto reset;
+			t |= c << 16;
+			c = iqGet(&host->iq); if (c < 0) goto reset;
+			t |= c << 24;
+
+			chprintf((BaseSequentialStream *)&USBH_DEBUG_SD, "+%08d ", t);
+			state = 4;
+		} else {
 			while (true) {
-				c = chIQGet(&host->iq); if (c < 0) goto reset;
 				if (!c) {
 					sdPut(&USBH_DEBUG_SD, '\r');
 					sdPut(&USBH_DEBUG_SD, '\n');
@@ -516,6 +554,7 @@ static void usb_debug_thread(void *p) {
 					break;
 				}
 				sdPut(&USBH_DEBUG_SD, (uint8_t)c);
+				c = iqGet(&host->iq); if (c < 0) goto reset;
 			}
 		}
 
@@ -528,9 +567,8 @@ reset:
 void usbDbgInit(USBHDriver *host) {
 	if (host != &USBH_DEBUG_USBHD)
 		return;
-	chIQObjectInit(&USBH_DEBUG_USBHD.iq, USBH_DEBUG_USBHD.dbg_buff, sizeof(USBH_DEBUG_USBHD.dbg_buff), 0, 0);
+	iqObjectInit(&USBH_DEBUG_USBHD.iq, USBH_DEBUG_USBHD.dbg_buff, sizeof(USBH_DEBUG_USBHD.dbg_buff), 0, 0);
 	chThdCreateStatic(USBH_DEBUG_USBHD.waDebug, sizeof(USBH_DEBUG_USBHD.waDebug), NORMALPRIO, usb_debug_thread, &USBH_DEBUG_USBHD);
 }
-#endif
 
 #endif
diff --git a/os/hal/src/usbh/hal_usbh_desciter.c b/os/hal/src/usbh/hal_usbh_desciter.c
index 63137d4..3695881 100644
--- a/os/hal/src/usbh/hal_usbh_desciter.c
+++ b/os/hal/src/usbh/hal_usbh_desciter.c
@@ -1,6 +1,6 @@
 /*
-    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
-              Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail)
+    ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio
+              Copyright (C) 2015..2017 Diego Ismirlian, (dismirlian (at) google's mail)
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -134,22 +134,18 @@ void cs_iter_next(generic_iterator_t *ics) {
 	if ((curr[0] < 2) || (rem < 2) || (rem < curr[0]))
 		return;
 
-	//for (;;) {
-		rem -= curr[0];
-		curr += curr[0];
+	rem -= curr[0];
+	curr += curr[0];
 
-		if ((curr[0] < 2) || (rem < 2) || (rem < curr[0]))
-			return;
-
-		if ((curr[1] == USBH_DT_INTERFACE_ASSOCIATION)
-				|| (curr[1] == USBH_DT_INTERFACE)
-				|| (curr[1] == USBH_DT_CONFIG)
-				|| (curr[1] == USBH_DT_ENDPOINT)) {
-			return;
-		}
+	if ((curr[0] < 2) || (rem < 2) || (rem < curr[0]))
+		return;
 
-	//	break;
-	//}
+	if ((curr[1] == USBH_DT_INTERFACE_ASSOCIATION)
+			|| (curr[1] == USBH_DT_INTERFACE)
+			|| (curr[1] == USBH_DT_CONFIG)
+			|| (curr[1] == USBH_DT_ENDPOINT)) {
+		return;
+	}
 
 	ics->valid = 1;
 	ics->rem = rem;
diff --git a/os/hal/src/usbh/hal_usbh_ftdi.c b/os/hal/src/usbh/hal_usbh_ftdi.c
index 4bd7296..6966028 100644
--- a/os/hal/src/usbh/hal_usbh_ftdi.c
+++ b/os/hal/src/usbh/hal_usbh_ftdi.c
@@ -1,6 +1,6 @@
 /*
-    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
-              Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail)
+    ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio
+              Copyright (C) 2015..2017 Diego Ismirlian, (dismirlian (at) google's mail)
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -16,7 +16,6 @@
 */
 
 #include "hal.h"
-#include "hal_usbh.h"
 
 #if HAL_USBH_USE_FTDI
 
@@ -28,9 +27,6 @@
 #include "usbh/dev/ftdi.h"
 #include "usbh/internal.h"
 
-//#pragma GCC optimize("Og")
-
-
 #if USBHFTDI_DEBUG_ENABLE_TRACE
 #define udbgf(f, ...)  usbDbgPrintf(f, ##__VA_ARGS__)
 #define udbg(f, ...)  usbDbgPuts(f, ##__VA_ARGS__)
@@ -63,22 +59,25 @@
 #define uerr(f, ...)   do {} while(0)
 #endif
 
+static void _ftdip_object_init(USBHFTDIPortDriver *ftdipp);
 
 /*===========================================================================*/
 /* USB Class driver loader for FTDI								 		 	 */
 /*===========================================================================*/
 USBHFTDIDriver USBHFTDID[HAL_USBHFTDI_MAX_INSTANCES];
 
+static void _ftdi_init(void);
 static usbh_baseclassdriver_t *_ftdi_load(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem);
 static void _ftdi_unload(usbh_baseclassdriver_t *drv);
 
 static const usbh_classdriver_vmt_t class_driver_vmt = {
+	_ftdi_init,
 	_ftdi_load,
 	_ftdi_unload
 };
 
 const usbh_classdriverinfo_t usbhftdiClassDriverInfo = {
-	0xff, 0xff, 0xff, "FTDI", &class_driver_vmt
+	"FTDI", &class_driver_vmt
 };
 
 static USBHFTDIPortDriver *_find_port(void) {
@@ -94,10 +93,8 @@ static usbh_baseclassdriver_t *_ftdi_load(usbh_device_t *dev, const uint8_t *des
 	int i;
 	USBHFTDIDriver *ftdip;
 
-	if (dev->devDesc.idVendor != 0x0403) {
-		uerr("FTDI: Unrecognized VID");
+	if (_usbh_match_vid_pid(dev, 0x0403, -1) != HAL_SUCCESS)
 		return NULL;
-	}
 
 	switch (dev->devDesc.idProduct) {
 	case 0x6001:
@@ -105,17 +102,18 @@ static usbh_baseclassdriver_t *_ftdi_load(usbh_device_t *dev, const uint8_t *des
 	case 0x6011:
 	case 0x6014:
 	case 0x6015:
+	case 0xE2E6:
 		break;
 	default:
 		uerr("FTDI: Unrecognized PID");
 		return NULL;
 	}
 
-	if ((rem < descriptor[0]) || (descriptor[1] != USBH_DT_INTERFACE))
+	if (_usbh_match_descriptor(descriptor, rem, USBH_DT_INTERFACE,
+			0xff, 0xff, 0xff) != HAL_SUCCESS)
 		return NULL;
 
-	const usbh_interface_descriptor_t * const ifdesc = (const usbh_interface_descriptor_t * const)descriptor;
-	if (ifdesc->bInterfaceNumber != 0) {
+	if (((const usbh_interface_descriptor_t *)descriptor)->bInterfaceNumber != 0) {
 		uwarn("FTDI: Will allocate driver along with IF #0");
 	}
 
@@ -211,7 +209,7 @@ alloc_ok:
 
 }
 
-static void _stop(USBHFTDIPortDriver *ftdipp);
+static void _stopS(USBHFTDIPortDriver *ftdipp);
 static void _ftdi_unload(usbh_baseclassdriver_t *drv) {
 	osalDbgCheck(drv != NULL);
 	USBHFTDIDriver *const ftdip = (USBHFTDIDriver *)drv;
@@ -219,7 +217,9 @@ static void _ftdi_unload(usbh_baseclassdriver_t *drv) {
 
 	osalMutexLock(&ftdip->mtx);
 	while (ftdipp) {
-		_stop(ftdipp);
+		osalSysLock();
+		_stopS(ftdipp);
+		osalSysUnlock();
 		ftdipp = ftdipp->next;
 	}
 
@@ -227,7 +227,7 @@ static void _ftdi_unload(usbh_baseclassdriver_t *drv) {
 	osalSysLock();
 	while (ftdipp) {
 		USBHFTDIPortDriver *next = ftdipp->next;
-		usbhftdipObjectInit(ftdipp);
+		_ftdip_object_init(ftdipp);
 		ftdipp = next;
 	}
 	osalSysUnlock();
@@ -314,17 +314,17 @@ static usbh_urbstatus_t _ftdi_port_control(USBHFTDIPortDriver *ftdipp,
 		uint8_t *buff) {
 
 	static const uint8_t bmRequestType[] = {
-		USBH_REQTYPE_VENDOR | USBH_REQTYPE_OUT | USBH_REQTYPE_DEVICE, //0 FTDI_COMMAND_RESET
-		USBH_REQTYPE_VENDOR | USBH_REQTYPE_OUT | USBH_REQTYPE_DEVICE, //1 FTDI_COMMAND_MODEMCTRL
-		USBH_REQTYPE_VENDOR | USBH_REQTYPE_OUT | USBH_REQTYPE_DEVICE, //2 FTDI_COMMAND_SETFLOW
-		USBH_REQTYPE_VENDOR | USBH_REQTYPE_OUT | USBH_REQTYPE_DEVICE, //3 FTDI_COMMAND_SETBAUD
-		USBH_REQTYPE_VENDOR | USBH_REQTYPE_OUT | USBH_REQTYPE_DEVICE, //4 FTDI_COMMAND_SETDATA
+		USBH_REQTYPE_TYPE_VENDOR | USBH_REQTYPE_DIR_OUT | USBH_REQTYPE_RECIP_DEVICE, //0 FTDI_COMMAND_RESET
+		USBH_REQTYPE_TYPE_VENDOR | USBH_REQTYPE_DIR_OUT | USBH_REQTYPE_RECIP_DEVICE, //1 FTDI_COMMAND_MODEMCTRL
+		USBH_REQTYPE_TYPE_VENDOR | USBH_REQTYPE_DIR_OUT | USBH_REQTYPE_RECIP_DEVICE, //2 FTDI_COMMAND_SETFLOW
+		USBH_REQTYPE_TYPE_VENDOR | USBH_REQTYPE_DIR_OUT | USBH_REQTYPE_RECIP_DEVICE, //3 FTDI_COMMAND_SETBAUD
+		USBH_REQTYPE_TYPE_VENDOR | USBH_REQTYPE_DIR_OUT | USBH_REQTYPE_RECIP_DEVICE, //4 FTDI_COMMAND_SETDATA
 	};
 
 	osalDbgCheck(bRequest < sizeof_array(bmRequestType));
 	osalDbgCheck(bRequest != 1);
 
-	const USBH_DEFINE_BUFFER(usbh_control_request_t, req) = {
+	USBH_DEFINE_BUFFER(const usbh_control_request_t req) = {
 			bmRequestType[bRequest],
 			bRequest,
 			wValue,
@@ -332,7 +332,7 @@ static usbh_urbstatus_t _ftdi_port_control(USBHFTDIPortDriver *ftdipp,
 			wLength
 	};
 
-	return usbhControlRequestExtended(ftdipp->ftdip->dev, &req, buff, NULL, MS2ST(1000));
+	return usbhControlRequestExtended(ftdipp->ftdip->dev, &req, buff, NULL, OSAL_MS2I(1000));
 }
 
 static uint32_t _get_divisor(uint32_t baud, usbhftdi_type_t type) {
@@ -387,14 +387,14 @@ static usbh_urbstatus_t _set_baudrate(USBHFTDIPortDriver *ftdipp, uint32_t baudr
 	if (ftdipp->ftdip->dev->basicConfigDesc.bNumInterfaces > 1)
 		wIndex = (wIndex << 8) | (ftdipp->ifnum + 1);
 
-	const USBH_DEFINE_BUFFER(usbh_control_request_t, req) = {
-		USBH_REQTYPE_VENDOR | USBH_REQTYPE_OUT | USBH_REQTYPE_DEVICE,
+	USBH_DEFINE_BUFFER(const usbh_control_request_t req) = {
+		USBH_REQTYPE_TYPE_VENDOR | USBH_REQTYPE_DIR_OUT | USBH_REQTYPE_RECIP_DEVICE,
 		FTDI_COMMAND_SETBAUD,
 		wValue,
 		wIndex,
 		0
 	};
-	return usbhControlRequestExtended(ftdipp->ftdip->dev, &req, NULL, NULL, MS2ST(1000));
+	return usbhControlRequestExtended(ftdipp->ftdip->dev, &req, NULL, NULL, OSAL_MS2I(1000));
 }
 
 
@@ -415,7 +415,7 @@ static void _out_cb(usbh_urb_t *urb) {
 		return;
 	case USBH_URBSTATUS_DISCONNECTED:
 		uwarn("FTDI: URB OUT disconnected");
-		chThdDequeueNextI(&ftdipp->oq_waiting, Q_RESET);
+		chThdDequeueAllI(&ftdipp->oq_waiting, Q_RESET);
 		return;
 	default:
 		uerrf("FTDI: URB OUT status unexpected = %d", urb->status);
@@ -430,15 +430,15 @@ static size_t _write_timeout(USBHFTDIPortDriver *ftdipp, const uint8_t *bp,
 	chDbgCheck(n > 0U);
 
 	size_t w = 0;
-	chSysLock();
+	osalSysLock();
 	while (true) {
 		if (ftdipp->state != USBHFTDIP_STATE_READY) {
-			chSysUnlock();
+			osalSysUnlock();
 			return w;
 		}
 		while (usbhURBIsBusy(&ftdipp->oq_urb)) {
 			if (chThdEnqueueTimeoutS(&ftdipp->oq_waiting, timeout) != Q_OK) {
-				chSysUnlock();
+				osalSysUnlock();
 				return w;
 			}
 		}
@@ -446,30 +446,30 @@ static size_t _write_timeout(USBHFTDIPortDriver *ftdipp, const uint8_t *bp,
 		*ftdipp->oq_ptr++ = *bp++;
 		if (--ftdipp->oq_counter == 0) {
 			_submitOutI(ftdipp, 64);
-			chSchRescheduleS();
+			osalOsRescheduleS();
 		}
-		chSysUnlock(); /* Gives a preemption chance in a controlled point.*/
+		osalSysUnlock(); /* Gives a preemption chance in a controlled point.*/
 
 		w++;
 		if (--n == 0U)
 			return w;
 
-		chSysLock();
+		osalSysLock();
 	}
 }
 
 static msg_t _put_timeout(USBHFTDIPortDriver *ftdipp, uint8_t b, systime_t timeout) {
 
-	chSysLock();
+	osalSysLock();
 	if (ftdipp->state != USBHFTDIP_STATE_READY) {
-		chSysUnlock();
+		osalSysUnlock();
 		return Q_RESET;
 	}
 
 	while (usbhURBIsBusy(&ftdipp->oq_urb)) {
 		msg_t msg = chThdEnqueueTimeoutS(&ftdipp->oq_waiting, timeout);
 		if (msg < Q_OK) {
-			chSysUnlock();
+			osalSysUnlock();
 			return msg;
 		}
 	}
@@ -477,9 +477,9 @@ static msg_t _put_timeout(USBHFTDIPortDriver *ftdipp, uint8_t b, systime_t timeo
 	*ftdipp->oq_ptr++ = b;
 	if (--ftdipp->oq_counter == 0) {
 		_submitOutI(ftdipp, 64);
-		chSchRescheduleS();
+		osalOsRescheduleS();
 	}
-	chSysUnlock();
+	osalSysUnlock();
 	return Q_OK;
 }
 
@@ -516,12 +516,12 @@ static void _in_cb(usbh_urb_t *urb) {
 			udbgf("FTDI: URB IN no data, status=%02x %02x",
 					((uint8_t *)urb->buff)[0],
 					((uint8_t *)urb->buff)[1]);
-			return;
+		//	return;
 		}
 		break;
 	case USBH_URBSTATUS_DISCONNECTED:
 		uwarn("FTDI: URB IN disconnected");
-		chThdDequeueNextI(&ftdipp->iq_waiting, Q_RESET);
+		chThdDequeueAllI(&ftdipp->iq_waiting, Q_RESET);
 		return;
 	default:
 		uerrf("FTDI: URB IN status unexpected = %d", urb->status);
@@ -536,41 +536,41 @@ static size_t _read_timeout(USBHFTDIPortDriver *ftdipp, uint8_t *bp,
 
 	chDbgCheck(n > 0U);
 
-	chSysLock();
+	osalSysLock();
 	while (true) {
 		if (ftdipp->state != USBHFTDIP_STATE_READY) {
-			chSysUnlock();
+			osalSysUnlock();
 			return r;
 		}
 		while (ftdipp->iq_counter == 0) {
 			if (!usbhURBIsBusy(&ftdipp->iq_urb))
 				_submitInI(ftdipp);
 			if (chThdEnqueueTimeoutS(&ftdipp->iq_waiting, timeout) != Q_OK) {
-				chSysUnlock();
+				osalSysUnlock();
 				return r;
 			}
 		}
 		*bp++ = *ftdipp->iq_ptr++;
 		if (--ftdipp->iq_counter == 0) {
 			_submitInI(ftdipp);
-			chSchRescheduleS();
+			osalOsRescheduleS();
 		}
-		chSysUnlock();
+		osalSysUnlock();
 
 		r++;
 		if (--n == 0U)
 			return r;
 
-		chSysLock();
+		osalSysLock();
 	}
 }
 
 static msg_t _get_timeout(USBHFTDIPortDriver *ftdipp, systime_t timeout) {
 	uint8_t b;
 
-	chSysLock();
+	osalSysLock();
 	if (ftdipp->state != USBHFTDIP_STATE_READY) {
-		chSysUnlock();
+		osalSysUnlock();
 		return Q_RESET;
 	}
 	while (ftdipp->iq_counter == 0) {
@@ -578,16 +578,16 @@ static msg_t _get_timeout(USBHFTDIPortDriver *ftdipp, systime_t timeout) {
 			_submitInI(ftdipp);
 		msg_t msg = chThdEnqueueTimeoutS(&ftdipp->iq_waiting, timeout);
 		if (msg < Q_OK) {
-			chSysUnlock();
+			osalSysUnlock();
 			return msg;
 		}
 	}
 	b = *ftdipp->iq_ptr++;
 	if (--ftdipp->iq_counter == 0) {
 		_submitInI(ftdipp);
-		chSchRescheduleS();
+		osalOsRescheduleS();
 	}
-	chSysUnlock();
+	osalSysUnlock();
 
 	return (msg_t)b;
 }
@@ -602,7 +602,7 @@ static size_t _read(USBHFTDIPortDriver *ftdipp, uint8_t *bp, size_t n) {
 
 static void _vt(void *p) {
 	USBHFTDIPortDriver *const ftdipp = (USBHFTDIPortDriver *)p;
-	chSysLockFromISR();
+	osalSysLockFromISR();
 	uint32_t len = ftdipp->oq_ptr - ftdipp->oq_buff;
 	if (len && !usbhURBIsBusy(&ftdipp->oq_urb)) {
 		_submitOutI(ftdipp, len);
@@ -610,8 +610,8 @@ static void _vt(void *p) {
 	if ((ftdipp->iq_counter == 0) && !usbhURBIsBusy(&ftdipp->iq_urb)) {
 		_submitInI(ftdipp);
 	}
-	chVTSetI(&ftdipp->vt, MS2ST(16), _vt, ftdipp);
-	chSysUnlockFromISR();
+	chVTSetI(&ftdipp->vt, OSAL_MS2I(16), _vt, ftdipp);
+	osalSysUnlockFromISR();
 }
 
 static const struct FTDIPortDriverVMT async_channel_vmt = {
@@ -626,29 +626,27 @@ static const struct FTDIPortDriverVMT async_channel_vmt = {
 };
 
 
-static void _stop(USBHFTDIPortDriver *ftdipp) {
-	osalSysLock();
+static void _stopS(USBHFTDIPortDriver *ftdipp) {
+	if (ftdipp->state != USBHFTDIP_STATE_READY)
+		return;
 	chVTResetI(&ftdipp->vt);
 	usbhEPCloseS(&ftdipp->epin);
 	usbhEPCloseS(&ftdipp->epout);
 	chThdDequeueAllI(&ftdipp->iq_waiting, Q_RESET);
 	chThdDequeueAllI(&ftdipp->oq_waiting, Q_RESET);
-	osalOsRescheduleS();
 	ftdipp->state = USBHFTDIP_STATE_ACTIVE;
-	osalSysUnlock();
+	osalOsRescheduleS();
 }
 
 void usbhftdipStop(USBHFTDIPortDriver *ftdipp) {
 	osalDbgCheck((ftdipp->state == USBHFTDIP_STATE_ACTIVE)
 			|| (ftdipp->state == USBHFTDIP_STATE_READY));
 
-	if (ftdipp->state == USBHFTDIP_STATE_ACTIVE) {
-		return;
-	}
-
-	osalMutexLock(&ftdipp->ftdip->mtx);
-	_stop(ftdipp);
-	osalMutexUnlock(&ftdipp->ftdip->mtx);
+	osalSysLock();
+	chMtxLockS(&ftdipp->ftdip->mtx);
+	_stopS(ftdipp);
+	chMtxUnlockS(&ftdipp->ftdip->mtx);
+	osalSysUnlock();
 }
 
 void usbhftdipStart(USBHFTDIPortDriver *ftdipp, const USBHFTDIPortConfig *config) {
@@ -689,29 +687,37 @@ void usbhftdipStart(USBHFTDIPortDriver *ftdipp, const USBHFTDIPortConfig *config
 	ftdipp->iq_counter = 0;
 	ftdipp->iq_ptr = ftdipp->iq_buff;
 	usbhEPOpen(&ftdipp->epin);
-	osalSysLock();
-	usbhURBSubmitI(&ftdipp->iq_urb);
-	osalSysUnlock();
+	usbhURBSubmit(&ftdipp->iq_urb);
 
 	chVTObjectInit(&ftdipp->vt);
-	chVTSet(&ftdipp->vt, MS2ST(16), _vt, ftdipp);
+	chVTSet(&ftdipp->vt, OSAL_MS2I(16), _vt, ftdipp);
 
 	ftdipp->state = USBHFTDIP_STATE_READY;
 	osalMutexUnlock(&ftdipp->ftdip->mtx);
 }
 
-void usbhftdiObjectInit(USBHFTDIDriver *ftdip) {
+static void _ftdi_object_init(USBHFTDIDriver *ftdip) {
 	osalDbgCheck(ftdip != NULL);
 	memset(ftdip, 0, sizeof(*ftdip));
 	ftdip->info = &usbhftdiClassDriverInfo;
 	osalMutexObjectInit(&ftdip->mtx);
 }
 
-void usbhftdipObjectInit(USBHFTDIPortDriver *ftdipp) {
+static void _ftdip_object_init(USBHFTDIPortDriver *ftdipp) {
 	osalDbgCheck(ftdipp != NULL);
 	memset(ftdipp, 0, sizeof(*ftdipp));
 	ftdipp->vmt = &async_channel_vmt;
 	ftdipp->state = USBHFTDIP_STATE_STOP;
 }
 
+static void _ftdi_init(void) {
+	uint8_t i;
+	for (i = 0; i < HAL_USBHFTDI_MAX_INSTANCES; i++) {
+		_ftdi_object_init(&USBHFTDID[i]);
+	}
+	for (i = 0; i < HAL_USBHFTDI_MAX_PORTS; i++) {
+		_ftdip_object_init(&FTDIPD[i]);
+	}
+}
+
 #endif
diff --git a/os/hal/src/usbh/hal_usbh_hid.c b/os/hal/src/usbh/hal_usbh_hid.c
new file mode 100644
index 0000000..2b2c5ce
--- /dev/null
+++ b/os/hal/src/usbh/hal_usbh_hid.c
@@ -0,0 +1,338 @@
+/*
+    ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio
+              Copyright (C) 2015..2017 Diego Ismirlian, (dismirlian (at) google's mail)
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USBH_USE_HID
+
+#if !HAL_USE_USBH
+#error "USBHHID needs USBH"
+#endif
+
+#include <string.h>
+#include "usbh/dev/hid.h"
+#include "usbh/internal.h"
+
+#if USBHHID_DEBUG_ENABLE_TRACE
+#define udbgf(f, ...)  usbDbgPrintf(f, ##__VA_ARGS__)
+#define udbg(f, ...)  usbDbgPuts(f, ##__VA_ARGS__)
+#else
+#define udbgf(f, ...)  do {} while(0)
+#define udbg(f, ...)   do {} while(0)
+#endif
+
+#if USBHHID_DEBUG_ENABLE_INFO
+#define uinfof(f, ...)  usbDbgPrintf(f, ##__VA_ARGS__)
+#define uinfo(f, ...)  usbDbgPuts(f, ##__VA_ARGS__)
+#else
+#define uinfof(f, ...)  do {} while(0)
+#define uinfo(f, ...)   do {} while(0)
+#endif
+
+#if USBHHID_DEBUG_ENABLE_WARNINGS
+#define uwarnf(f, ...)  usbDbgPrintf(f, ##__VA_ARGS__)
+#define uwarn(f, ...)  usbDbgPuts(f, ##__VA_ARGS__)
+#else
+#define uwarnf(f, ...)  do {} while(0)
+#define uwarn(f, ...)   do {} while(0)
+#endif
+
+#if USBHHID_DEBUG_ENABLE_ERRORS
+#define uerrf(f, ...)  usbDbgPrintf(f, ##__VA_ARGS__)
+#define uerr(f, ...)  usbDbgPuts(f, ##__VA_ARGS__)
+#else
+#define uerrf(f, ...)  do {} while(0)
+#define uerr(f, ...)   do {} while(0)
+#endif
+
+
+
+#define USBH_HID_REQ_GET_REPORT		0x01
+#define USBH_HID_REQ_GET_IDLE		0x02
+#define USBH_HID_REQ_GET_PROTOCOL	0x03
+#define USBH_HID_REQ_SET_REPORT		0x09
+#define USBH_HID_REQ_SET_IDLE		0x0A
+#define USBH_HID_REQ_SET_PROTOCOL	0x0B
+
+/*===========================================================================*/
+/* USB Class driver loader for HID								 		 	 */
+/*===========================================================================*/
+
+USBHHIDDriver USBHHIDD[HAL_USBHHID_MAX_INSTANCES];
+
+static void _hid_init(void);
+static usbh_baseclassdriver_t *_hid_load(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem);
+static void _hid_unload(usbh_baseclassdriver_t *drv);
+static void _stop_locked(USBHHIDDriver *hidp);
+
+static const usbh_classdriver_vmt_t class_driver_vmt = {
+	_hid_init,
+	_hid_load,
+	_hid_unload
+};
+
+const usbh_classdriverinfo_t usbhhidClassDriverInfo = {
+	"HID", &class_driver_vmt
+};
+
+static usbh_baseclassdriver_t *_hid_load(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem) {
+	int i;
+	USBHHIDDriver *hidp;
+
+	if (_usbh_match_descriptor(descriptor, rem, USBH_DT_INTERFACE,
+			0x03, -1, -1) != HAL_SUCCESS)
+		return NULL;
+
+	const usbh_interface_descriptor_t * const ifdesc = (const usbh_interface_descriptor_t *)descriptor;
+
+	if ((ifdesc->bAlternateSetting != 0)
+			|| (ifdesc->bNumEndpoints < 1)) {
+		return NULL;
+	}
+
+
+	/* alloc driver */
+	for (i = 0; i < HAL_USBHHID_MAX_INSTANCES; i++) {
+		if (USBHHIDD[i].dev == NULL) {
+			hidp = &USBHHIDD[i];
+			goto alloc_ok;
+		}
+	}
+
+	uwarn("Can't alloc HID driver");
+
+	/* can't alloc */
+	return NULL;
+
+alloc_ok:
+	/* initialize the driver's variables */
+	hidp->epin.status = USBH_EPSTATUS_UNINITIALIZED;
+#if HAL_USBHHID_USE_INTERRUPT_OUT
+	hidp->epout.status = USBH_EPSTATUS_UNINITIALIZED;
+#endif
+	hidp->ifnum = ifdesc->bInterfaceNumber;
+	usbhEPSetName(&dev->ctrl, "HID[CTRL]");
+
+	/* parse the configuration descriptor */
+	if_iterator_t iif;
+	generic_iterator_t iep;
+	iif.iad = 0;
+	iif.curr = descriptor;
+	iif.rem = rem;
+	for (ep_iter_init(&iep, &iif); iep.valid; ep_iter_next(&iep)) {
+		const usbh_endpoint_descriptor_t *const epdesc = ep_get(&iep);
+		if ((epdesc->bEndpointAddress & 0x80) && (epdesc->bmAttributes == USBH_EPTYPE_INT)) {
+			uinfof("INT IN endpoint found: bEndpointAddress=%02x", epdesc->bEndpointAddress);
+			usbhEPObjectInit(&hidp->epin, dev, epdesc);
+			usbhEPSetName(&hidp->epin, "HID[IIN ]");
+#if HAL_USBHHID_USE_INTERRUPT_OUT
+		} else if (((epdesc->bEndpointAddress & 0x80) == 0)
+				&& (epdesc->bmAttributes == USBH_EPTYPE_INT)) {
+			uinfof("INT OUT endpoint found: bEndpointAddress=%02x", epdesc->bEndpointAddress);
+			usbhEPObjectInit(&hidp->epout, dev, epdesc);
+			usbhEPSetName(&hidp->epout, "HID[IOUT]");
+#endif
+		} else {
+			uinfof("unsupported endpoint found: bEndpointAddress=%02x, bmAttributes=%02x",
+					epdesc->bEndpointAddress, epdesc->bmAttributes);
+		}
+	}
+	if (hidp->epin.status != USBH_EPSTATUS_CLOSED) {
+		goto deinit;
+	}
+
+	if (ifdesc->bInterfaceSubClass != 0x01) {
+		hidp->type = USBHHID_DEVTYPE_GENERIC;
+		uinfof("HID: bInterfaceSubClass=%02x, generic HID", ifdesc->bInterfaceSubClass);
+		if (ifdesc->bInterfaceSubClass != 0x00) {
+			uinfof("HID: bInterfaceSubClass=%02x is an invalid bInterfaceSubClass value",
+					ifdesc->bInterfaceSubClass);
+		}
+	} else if (ifdesc->bInterfaceProtocol == 0x01) {
+		hidp->type = USBHHID_DEVTYPE_BOOT_KEYBOARD;
+		uinfo("HID: BOOT protocol keyboard found");
+	} else if (ifdesc->bInterfaceProtocol == 0x02) {
+		hidp->type = USBHHID_DEVTYPE_BOOT_MOUSE;
+		uinfo("HID: BOOT protocol mouse found");
+	} else {
+		uerrf("HID: bInterfaceProtocol=%02x is an invalid boot protocol, abort",
+				ifdesc->bInterfaceProtocol);
+		goto deinit;
+	}
+
+	hidp->state = USBHHID_STATE_ACTIVE;
+
+	return (usbh_baseclassdriver_t *)hidp;
+
+deinit:
+	/* Here, the enpoints are closed, and the driver is unlinked */
+	return NULL;
+}
+
+static void _hid_unload(usbh_baseclassdriver_t *drv) {
+	USBHHIDDriver *const hidp = (USBHHIDDriver *)drv;
+	chSemWait(&hidp->sem);
+	_stop_locked(hidp);
+	hidp->state = USBHHID_STATE_STOP;
+	chSemSignal(&hidp->sem);
+}
+
+static void _in_cb(usbh_urb_t *urb) {
+	USBHHIDDriver *const hidp = (USBHHIDDriver *)urb->userData;
+	switch (urb->status) {
+	case USBH_URBSTATUS_OK:
+		if (hidp->config->cb_report) {
+			hidp->config->cb_report(hidp, urb->actualLength);
+		}
+		break;
+	case USBH_URBSTATUS_DISCONNECTED:
+		uwarn("HID: URB IN disconnected");
+
+		return;
+	case USBH_URBSTATUS_TIMEOUT:
+		//no data
+		break;
+	default:
+		uerrf("HID: URB IN status unexpected = %d", urb->status);
+		break;
+	}
+	usbhURBObjectResetI(&hidp->in_urb);
+	usbhURBSubmitI(&hidp->in_urb);
+}
+
+void usbhhidStart(USBHHIDDriver *hidp, const USBHHIDConfig *cfg) {
+	osalDbgCheck(hidp && cfg);
+	osalDbgCheck(cfg->report_buffer && (cfg->protocol <= USBHHID_PROTOCOL_REPORT));
+
+	chSemWait(&hidp->sem);
+	if (hidp->state == USBHHID_STATE_READY) {
+		chSemSignal(&hidp->sem);
+		return;
+	}
+	osalDbgCheck(hidp->state == USBHHID_STATE_ACTIVE);
+
+	hidp->config = cfg;
+
+	/* init the URBs */
+	uint32_t report_len = hidp->epin.wMaxPacketSize;
+	if (report_len > cfg->report_len)
+		report_len = cfg->report_len;
+	usbhURBObjectInit(&hidp->in_urb, &hidp->epin, _in_cb, hidp,
+			cfg->report_buffer, report_len);
+
+	/* open the int IN/OUT endpoints */
+	usbhEPOpen(&hidp->epin);
+#if HAL_USBHHID_USE_INTERRUPT_OUT
+	if (hidp->epout.status == USBH_EPSTATUS_CLOSED) {
+		usbhEPOpen(&hidp->epout);
+	}
+#endif
+
+	usbhhidSetProtocol(hidp, cfg->protocol);
+
+	usbhURBSubmit(&hidp->in_urb);
+
+	hidp->state = USBHHID_STATE_READY;
+	chSemSignal(&hidp->sem);
+}
+
+static void _stop_locked(USBHHIDDriver *hidp) {
+	if (hidp->state == USBHHID_STATE_ACTIVE)
+		return;
+
+	osalDbgCheck(hidp->state == USBHHID_STATE_READY);
+
+	usbhEPClose(&hidp->epin);
+#if HAL_USBHHID_USE_INTERRUPT_OUT
+	if (hidp->epout.status != USBH_EPSTATUS_UNINITIALIZED) {
+		usbhEPClose(&hidp->epout);
+	}
+#endif
+	hidp->state = USBHHID_STATE_ACTIVE;
+}
+
+void usbhhidStop(USBHHIDDriver *hidp) {
+	chSemWait(&hidp->sem);
+	_stop_locked(hidp);
+	chSemSignal(&hidp->sem);
+}
+
+usbh_urbstatus_t usbhhidGetReport(USBHHIDDriver *hidp,
+		uint8_t report_id, usbhhid_reporttype_t report_type,
+		void *data, uint16_t len) {
+	osalDbgCheck(hidp);
+	osalDbgAssert((uint8_t)report_type <= USBHHID_REPORTTYPE_FEATURE, "wrong report type");
+	return usbhControlRequest(hidp->dev,
+			USBH_REQTYPE_CLASSIN(USBH_REQTYPE_RECIP_INTERFACE), USBH_HID_REQ_GET_REPORT,
+			((uint8_t)report_type << 8) | report_id, hidp->ifnum, len, data);
+}
+
+usbh_urbstatus_t usbhhidSetReport(USBHHIDDriver *hidp,
+		uint8_t report_id, usbhhid_reporttype_t report_type,
+		const void *data, uint16_t len) {
+	osalDbgCheck(hidp);
+	osalDbgAssert((uint8_t)report_type <= USBHHID_REPORTTYPE_FEATURE, "wrong report type");
+	return usbhControlRequest(hidp->dev,
+			USBH_REQTYPE_CLASSOUT(USBH_REQTYPE_RECIP_INTERFACE), USBH_HID_REQ_SET_REPORT,
+			((uint8_t)report_type << 8) | report_id, hidp->ifnum, len, (void *)data);
+}
+
+usbh_urbstatus_t usbhhidGetIdle(USBHHIDDriver *hidp, uint8_t report_id, uint8_t *duration) {
+	osalDbgCheck(hidp);
+	return usbhControlRequest(hidp->dev,
+			USBH_REQTYPE_CLASSIN(USBH_REQTYPE_RECIP_INTERFACE), USBH_HID_REQ_GET_IDLE,
+			report_id, hidp->ifnum, 1, duration);
+}
+
+usbh_urbstatus_t usbhhidSetIdle(USBHHIDDriver *hidp, uint8_t report_id, uint8_t duration) {
+	osalDbgCheck(hidp);
+	return usbhControlRequest(hidp->dev,
+			USBH_REQTYPE_CLASSOUT(USBH_REQTYPE_RECIP_INTERFACE), USBH_HID_REQ_SET_IDLE,
+			(duration << 8) | report_id, hidp->ifnum, 0, NULL);
+}
+
+usbh_urbstatus_t usbhhidGetProtocol(USBHHIDDriver *hidp, uint8_t *protocol) {
+	osalDbgCheck(hidp);
+	return usbhControlRequest(hidp->dev,
+			USBH_REQTYPE_CLASSIN(USBH_REQTYPE_RECIP_INTERFACE), USBH_HID_REQ_GET_PROTOCOL,
+			0, hidp->ifnum, 1, protocol);
+}
+
+usbh_urbstatus_t usbhhidSetProtocol(USBHHIDDriver *hidp, uint8_t protocol) {
+	osalDbgCheck(hidp);
+	osalDbgAssert(protocol <= 1, "invalid protocol");
+	return usbhControlRequest(hidp->dev,
+			USBH_REQTYPE_CLASSOUT(USBH_REQTYPE_RECIP_INTERFACE), USBH_HID_REQ_SET_PROTOCOL,
+			protocol, hidp->ifnum, 0, NULL);
+}
+
+static void _hid_object_init(USBHHIDDriver *hidp) {
+	osalDbgCheck(hidp != NULL);
+	memset(hidp, 0, sizeof(*hidp));
+	hidp->info = &usbhhidClassDriverInfo;
+	hidp->state = USBHHID_STATE_STOP;
+	chSemObjectInit(&hidp->sem, 1);
+}
+
+static void _hid_init(void) {
+	uint8_t i;
+	for (i = 0; i < HAL_USBHHID_MAX_INSTANCES; i++) {
+		_hid_object_init(&USBHHIDD[i]);
+	}
+}
+
+#endif
diff --git a/os/hal/src/usbh/hal_usbh_hub.c b/os/hal/src/usbh/hal_usbh_hub.c
index 7fdcef1..6a83c66 100644
--- a/os/hal/src/usbh/hal_usbh_hub.c
+++ b/os/hal/src/usbh/hal_usbh_hub.c
@@ -1,6 +1,6 @@
 /*
-    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
-              Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail)
+    ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio
+              Copyright (C) 2015..2017 Diego Ismirlian, (dismirlian (at) google's mail)
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -16,8 +16,6 @@
 */
 
 #include "hal.h"
-#include "hal_usbh.h"
-#include "usbh/internal.h"
 
 #if HAL_USBH_USE_HUB
 
@@ -27,6 +25,7 @@
 
 #include <string.h>
 #include "usbh/dev/hub.h"
+#include "usbh/internal.h"
 
 #if USBHHUB_DEBUG_ENABLE_TRACE
 #define udbgf(f, ...)  usbDbgPrintf(f, ##__VA_ARGS__)
@@ -62,16 +61,19 @@
 
 
 USBHHubDriver USBHHUBD[HAL_USBHHUB_MAX_INSTANCES];
-usbh_port_t USBHPorts[HAL_USBHHUB_MAX_PORTS];
+static usbh_port_t USBHPorts[HAL_USBHHUB_MAX_PORTS];
 
-static usbh_baseclassdriver_t *hub_load(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem);
-static void hub_unload(usbh_baseclassdriver_t *drv);
+static void _hub_init(void);
+static usbh_baseclassdriver_t *_hub_load(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem);
+static void _hub_unload(usbh_baseclassdriver_t *drv);
 static const usbh_classdriver_vmt_t usbhhubClassDriverVMT = {
-	hub_load,
-	hub_unload
+	_hub_init,
+	_hub_load,
+	_hub_unload
 };
+
 const usbh_classdriverinfo_t usbhhubClassDriverInfo = {
-	0x09, 0x00, -1, "HUB", &usbhhubClassDriverVMT
+	"HUB", &usbhhubClassDriverVMT
 };
 
 
@@ -105,7 +107,7 @@ static void _urb_complete(usbh_urb_t *urb) {
 	case USBH_URBSTATUS_TIMEOUT:
 		/* the device NAKed */
 		udbg("HUB: no info");
-		hubdp->statuschange = 0;
+		//hubdp->statuschange = 0;
 		break;
 	case USBH_URBSTATUS_OK: {
 		uint8_t len = hubdp->hubDesc.bNbrPorts / 8 + 1;
@@ -138,16 +140,14 @@ static void _urb_complete(usbh_urb_t *urb) {
 	usbhURBSubmitI(urb);
 }
 
-static usbh_baseclassdriver_t *hub_load(usbh_device_t *dev,
+static usbh_baseclassdriver_t *_hub_load(usbh_device_t *dev,
 		const uint8_t *descriptor, uint16_t rem) {
 	int i;
 
 	USBHHubDriver *hubdp;
 
-	if ((rem < descriptor[0]) || (descriptor[1] != USBH_DT_DEVICE))
-		return NULL;
-
-	if (dev->devDesc.bDeviceProtocol != 0)
+	if (_usbh_match_descriptor(descriptor, rem, USBH_DT_DEVICE,
+			0x09, 0x00, 0x00) != HAL_SUCCESS)
 		return NULL;
 
 	generic_iterator_t iep, icfg;
@@ -159,12 +159,10 @@ static usbh_baseclassdriver_t *hub_load(usbh_device_t *dev,
 	if_iter_init(&iif, &icfg);
 	if (!iif.valid)
 		return NULL;
-	const usbh_interface_descriptor_t *const ifdesc = if_get(&iif);
-	if ((ifdesc->bInterfaceClass != 0x09)
-		|| (ifdesc->bInterfaceSubClass != 0x00)
-		|| (ifdesc->bInterfaceProtocol != 0x00)) {
+
+	if (_usbh_match_descriptor(iif.curr, iif.rem, USBH_DT_INTERFACE,
+			0x09, 0x00, 0x00) != HAL_SUCCESS)
 		return NULL;
-	}
 
 	ep_iter_init(&iep, &iif);
 	if (!iep.valid)
@@ -199,7 +197,7 @@ alloc_ok:
 	/* read Hub descriptor */
 	uinfo("Read Hub descriptor");
 	if (usbhhubControlRequest(dev->host, hubdp,
-			USBH_REQTYPE_IN | USBH_REQTYPE_CLASS | USBH_REQTYPE_DEVICE,
+			USBH_REQTYPE_DIR_IN | USBH_REQTYPE_TYPE_CLASS | USBH_REQTYPE_RECIP_DEVICE,
 			USBH_REQ_GET_DESCRIPTOR,
 			(USBH_DT_HUB << 8), 0, sizeof(hubdp->hubDesc),
 			(uint8_t *)&hubdp->hubDesc) != USBH_URBSTATUS_OK) {
@@ -254,22 +252,18 @@ alloc_ok:
 			_urb_complete, hubdp, hubdp->scbuff,
 			(hubdesc->bNbrPorts + 8) / 8);
 
-	osalSysLock();
-	usbhURBSubmitI(&hubdp->urb);
-	osalOsRescheduleS();
-	osalSysUnlock();
+	usbhURBSubmit(&hubdp->urb);
 
+	hubdp->dev = NULL;
 	return (usbh_baseclassdriver_t *)hubdp;
 }
 
-static void hub_unload(usbh_baseclassdriver_t *drv) {
+static void _hub_unload(usbh_baseclassdriver_t *drv) {
 	osalDbgCheck(drv != NULL);
 	USBHHubDriver *const hubdp = (USBHHubDriver *)drv;
 
 	/* close the status change endpoint (this cancels ongoing URBs) */
-	osalSysLock();
-	usbhEPCloseS(&hubdp->epint);
-	osalSysUnlock();
+	usbhEPClose(&hubdp->epint);
 
 	/* de-alloc ports and unload drivers */
 	usbh_port_t *port = hubdp->ports;
@@ -284,14 +278,23 @@ static void hub_unload(usbh_baseclassdriver_t *drv) {
 
 }
 
-void usbhhubObjectInit(USBHHubDriver *hubdp) {
+static void _object_init(USBHHubDriver *hubdp) {
 	osalDbgCheck(hubdp != NULL);
 	memset(hubdp, 0, sizeof(*hubdp));
 	hubdp->info = &usbhhubClassDriverInfo;
 }
+
+static void _hub_init(void) {
+	uint8_t i;
+	for (i = 0; i < HAL_USBHHUB_MAX_INSTANCES; i++) {
+		_object_init(&USBHHUBD[i]);
+	}
+}
+
 #else
 
 #if HAL_USE_USBH
+#include <string.h>
 void _usbhub_port_object_init(usbh_port_t *port, USBHDriver *usbh, uint8_t number) {
 	memset(port, 0, sizeof(*port));
 	port->number = number;
diff --git a/os/hal/src/usbh/hal_usbh_msd.c b/os/hal/src/usbh/hal_usbh_msd.c
index 6869a74..7233a0b 100644
--- a/os/hal/src/usbh/hal_usbh_msd.c
+++ b/os/hal/src/usbh/hal_usbh_msd.c
@@ -1,6 +1,6 @@
 /*
-    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
-              Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail)
+    ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio
+              Copyright (C) 2015..2017 Diego Ismirlian, (dismirlian (at) google's mail)
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -16,7 +16,6 @@
 */
 
 #include "hal.h"
-#include "hal_usbh.h"
 
 #if HAL_USBH_USE_MSD
 
@@ -28,9 +27,6 @@
 #include "usbh/dev/msd.h"
 #include "usbh/internal.h"
 
-//#pragma GCC optimize("Og")
-
-
 #if USBHMSD_DEBUG_ENABLE_TRACE
 #define udbgf(f, ...)  usbDbgPrintf(f, ##__VA_ARGS__)
 #define udbg(f, ...)  usbDbgPuts(f, ##__VA_ARGS__)
@@ -63,26 +59,39 @@
 #define uerr(f, ...)   do {} while(0)
 #endif
 
+static void _lun_object_deinit(USBHMassStorageLUNDriver *lunp);
 
+/*===========================================================================*/
+/* USB Class driver loader for MSD                                           */
+/*===========================================================================*/
 
+struct USBHMassStorageDriver {
+	/* inherited from abstract class driver */
+	_usbh_base_classdriver_data
 
+	usbh_ep_t epin;
+	usbh_ep_t epout;
+	uint8_t ifnum;
+	uint8_t max_lun;
+	uint32_t tag;
 
-/*===========================================================================*/
-/* USB Class driver loader for MSD								 		 	 */
-/*===========================================================================*/
+	USBHMassStorageLUNDriver *luns;
+};
 
-USBHMassStorageDriver USBHMSD[HAL_USBHMSD_MAX_INSTANCES];
+static USBHMassStorageDriver USBHMSD[HAL_USBHMSD_MAX_INSTANCES];
 
+static void _msd_init(void);
 static usbh_baseclassdriver_t *_msd_load(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem);
 static void _msd_unload(usbh_baseclassdriver_t *drv);
 
 static const usbh_classdriver_vmt_t class_driver_vmt = {
+	_msd_init,
 	_msd_load,
 	_msd_unload
 };
 
 const usbh_classdriverinfo_t usbhmsdClassDriverInfo = {
-	0x08, 0x06, 0x50, "MSD", &class_driver_vmt
+	"MSD", &class_driver_vmt
 };
 
 #define MSD_REQ_RESET							0xFF
@@ -91,18 +100,17 @@ const usbh_classdriverinfo_t usbhmsdClassDriverInfo = {
 static usbh_baseclassdriver_t *_msd_load(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem) {
 	int i;
 	USBHMassStorageDriver *msdp;
-	uint8_t luns; // should declare it here to eliminate 'control bypass initialization' warning
-	usbh_urbstatus_t stat;  // should declare it here to eliminate 'control bypass initialization' warning
+	uint8_t luns;
+	usbh_urbstatus_t stat;
 
-	if ((rem < descriptor[0]) || (descriptor[1] != USBH_DT_INTERFACE))
+	if (_usbh_match_descriptor(descriptor, rem, USBH_DT_INTERFACE,
+			0x08, 0x06, 0x50) != HAL_SUCCESS)
 		return NULL;
 
 	const usbh_interface_descriptor_t * const ifdesc = (const usbh_interface_descriptor_t *)descriptor;
 
 	if ((ifdesc->bAlternateSetting != 0)
-			|| (ifdesc->bNumEndpoints < 2)
-			|| (ifdesc->bInterfaceSubClass != 0x06)
-			|| (ifdesc->bInterfaceProtocol != 0x50)) {
+			|| (ifdesc->bNumEndpoints < 2)) {
 		return NULL;
 	}
 
@@ -157,10 +165,10 @@ alloc_ok:
 
 	/* read the number of LUNs */
 	uinfo("Reading Max LUN:");
-	USBH_DEFINE_BUFFER(uint8_t, buff[4]);
+	USBH_DEFINE_BUFFER(uint8_t buff[4]);
 	stat = usbhControlRequest(dev,
-			USBH_CLASSIN(USBH_REQTYPE_INTERFACE, MSD_GET_MAX_LUN, 0, msdp->ifnum),
-			1, buff);
+			USBH_REQTYPE_CLASSIN(USBH_REQTYPE_RECIP_INTERFACE),
+			MSD_GET_MAX_LUN, 0, msdp->ifnum, 1, buff);
 	if (stat == USBH_URBSTATUS_OK) {
 		msdp->max_lun = buff[0] + 1;
 		uinfof("\tmax_lun = %d", msdp->max_lun);
@@ -188,13 +196,7 @@ alloc_ok:
 			MSBLKD[i].next = msdp->luns;
 			msdp->luns = &MSBLKD[i];
 			MSBLKD[i].msdp = msdp;
-
-			osalSysLock();
-			MSBLKD[i].state = BLK_ACTIVE;	/* transition directly to active, instead of BLK_STOP */
-			osalSysUnlock();
-
-			/* connect the LUN (TODO: review if it's best to leave the LUN disconnected) */
-			usbhmsdLUNConnect(&MSBLKD[i]);
+			MSBLKD[i].state = BLK_ACTIVE;
 			luns--;
 		}
 	}
@@ -211,36 +213,24 @@ static void _msd_unload(usbh_baseclassdriver_t *drv) {
 	USBHMassStorageDriver *const msdp = (USBHMassStorageDriver *)drv;
 	USBHMassStorageLUNDriver *lunp = msdp->luns;
 
-	osalMutexLock(&msdp->mtx);
-	osalSysLock();
-	usbhEPCloseS(&msdp->epin);
-	usbhEPCloseS(&msdp->epout);
+	/* disconnect all LUNs */
 	while (lunp) {
-		lunp->state = BLK_STOP;
+		usbhmsdLUNDisconnect(lunp);
+		_lun_object_deinit(lunp);
 		lunp = lunp->next;
 	}
-	osalSysUnlock();
-	osalMutexUnlock(&msdp->mtx);
 
-	/* now that the LUNs are idle, deinit them */
-	lunp = msdp->luns;
-	osalSysLock();
-	while (lunp) {
-		usbhmsdLUNObjectInit(lunp);
-		lunp = lunp->next;
-	}
-	osalSysUnlock();
+	usbhEPClose(&msdp->epin);
+	usbhEPClose(&msdp->epout);
 }
 
 
 /*===========================================================================*/
-/* MSD Class driver operations (Bulk-Only transport)			 		 	 */
+/* MSD Class driver operations (Bulk-Only transport)                         */
 /*===========================================================================*/
 
-
-
 /* USB Bulk Only Transport SCSI Command block wrapper */
-PACKED_STRUCT {
+typedef PACKED_STRUCT {
 	uint32_t dCBWSignature;
 	uint32_t dCBWTag;
 	uint32_t dCBWDataTransferLength;
@@ -253,9 +243,8 @@ PACKED_STRUCT {
 #define MSD_CBWFLAGS_D2H						0x80
 #define MSD_CBWFLAGS_H2D						0x00
 
-
 /* USB Bulk Only Transport SCSI Command status wrapper */
-PACKED_STRUCT {
+typedef PACKED_STRUCT {
 	uint32_t dCSWSignature;
 	uint32_t dCSWTag;
 	uint32_t dCSWDataResidue;
@@ -263,34 +252,174 @@ PACKED_STRUCT {
 } msd_csw_t;
 #define MSD_CSW_SIGNATURE						0x53425355
 
-
-typedef union {
-	msd_cbw_t cbw;
-	msd_csw_t csw;
+typedef struct {
+	msd_cbw_t *cbw;
+	uint8_t csw_status;
+	uint32_t data_processed;
 } msd_transaction_t;
 
 typedef enum {
-	MSD_TRANSACTIONRESULT_OK,
-	MSD_TRANSACTIONRESULT_DISCONNECTED,
-	MSD_TRANSACTIONRESULT_STALL,
-	MSD_TRANSACTIONRESULT_BUS_ERROR,
-	MSD_TRANSACTIONRESULT_SYNC_ERROR
-} msd_transaction_result_t;
+	MSD_BOTRESULT_OK,
+	MSD_BOTRESULT_DISCONNECTED,
+	MSD_BOTRESULT_ERROR
+} msd_bot_result_t;
 
 typedef enum {
-	MSD_COMMANDRESULT_PASSED = 0,
-	MSD_COMMANDRESULT_FAILED = 1,
-	MSD_COMMANDRESULT_PHASE_ERROR = 2
-} msd_command_result_t;
-
-typedef struct {
-	msd_transaction_result_t tres;
-	msd_command_result_t cres;
+	MSD_RESULT_OK = MSD_BOTRESULT_OK,
+	MSD_RESULT_DISCONNECTED = MSD_BOTRESULT_DISCONNECTED,
+	MSD_RESULT_TRANSPORT_ERROR = MSD_BOTRESULT_ERROR,
+	MSD_RESULT_FAILED
 } msd_result_t;
 
 
+#define	CSW_STATUS_PASSED		0
+#define	CSW_STATUS_FAILED		1
+#define	CSW_STATUS_PHASE_ERROR	2
+
+static bool _msd_bot_reset(USBHMassStorageDriver *msdp) {
+
+	usbh_urbstatus_t res;
+	res = usbhControlRequest(msdp->dev,
+			USBH_REQTYPE_CLASSOUT(USBH_REQTYPE_RECIP_INTERFACE),
+			0xFF, 0, msdp->ifnum, 0, NULL);
+	if (res != USBH_URBSTATUS_OK) {
+		return FALSE;
+	}
+
+	osalThreadSleepMilliseconds(100);
+
+	return usbhEPReset(&msdp->epin) && usbhEPReset(&msdp->epout);
+}
+
+static msd_bot_result_t _msd_bot_transaction(msd_transaction_t *tran, USBHMassStorageLUNDriver *lunp, void *data) {
+
+	uint32_t data_actual_len, actual_len;
+	usbh_urbstatus_t status;
+	USBH_DEFINE_BUFFER(msd_csw_t csw);
+
+	tran->cbw->bCBWLUN = (uint8_t)(lunp - &lunp->msdp->luns[0]);
+	tran->cbw->dCBWSignature = MSD_CBW_SIGNATURE;
+	tran->cbw->dCBWTag = ++lunp->msdp->tag;
+	tran->data_processed = 0;
+
+	/* control phase */
+	status = usbhBulkTransfer(&lunp->msdp->epout, tran->cbw,
+					sizeof(*tran->cbw), &actual_len, OSAL_MS2I(1000));
+
+	if (status == USBH_URBSTATUS_CANCELLED) {
+		uerr("\tMSD: Control phase: USBH_URBSTATUS_CANCELLED");
+		return MSD_BOTRESULT_DISCONNECTED;
+	}
+
+	if ((status != USBH_URBSTATUS_OK) || (actual_len != sizeof(*tran->cbw))) {
+		uerrf("\tMSD: Control phase: status = %d (!= OK), actual_len = %d (expected to send %d)",
+				status, actual_len, sizeof(*tran->cbw));
+		_msd_bot_reset(lunp->msdp);
+		return MSD_BOTRESULT_ERROR;
+	}
+
+
+	/* data phase */
+	data_actual_len = 0;
+	if (tran->cbw->dCBWDataTransferLength) {
+		usbh_ep_t *const ep = tran->cbw->bmCBWFlags & MSD_CBWFLAGS_D2H ? &lunp->msdp->epin : &lunp->msdp->epout;
+		status = usbhBulkTransfer(
+				ep,
+				data,
+				tran->cbw->dCBWDataTransferLength,
+				&data_actual_len, OSAL_MS2I(20000));
+
+		if (status == USBH_URBSTATUS_CANCELLED) {
+			uerr("\tMSD: Data phase: USBH_URBSTATUS_CANCELLED");
+			return MSD_BOTRESULT_DISCONNECTED;
+		}
+
+		if (status == USBH_URBSTATUS_STALL) {
+			uerrf("\tMSD: Data phase: USBH_URBSTATUS_STALL, clear halt");
+			status = (usbhEPReset(ep) == HAL_SUCCESS) ? USBH_URBSTATUS_OK : USBH_URBSTATUS_ERROR;
+		}
+
+		if (status != USBH_URBSTATUS_OK) {
+			uerrf("\tMSD: Data phase: status = %d (!= OK), resetting", status);
+			_msd_bot_reset(lunp->msdp);
+			return MSD_BOTRESULT_ERROR;
+		}
+	}
+
+
+	/* status phase */
+	status = usbhBulkTransfer(&lunp->msdp->epin, &csw,
+				sizeof(csw), &actual_len, OSAL_MS2I(1000));
+
+	if (status == USBH_URBSTATUS_STALL) {
+		uwarn("\tMSD: Status phase: USBH_URBSTATUS_STALL, clear halt and retry");
+
+		status = (usbhEPReset(&lunp->msdp->epin) == HAL_SUCCESS) ? USBH_URBSTATUS_OK : USBH_URBSTATUS_ERROR;
+
+		if (status == USBH_URBSTATUS_OK) {
+			status = usbhBulkTransfer(&lunp->msdp->epin, &csw,
+						sizeof(csw), &actual_len, OSAL_MS2I(1000));
+		}
+	}
+
+	if (status == USBH_URBSTATUS_CANCELLED) {
+		uerr("\tMSD: Status phase: USBH_URBSTATUS_CANCELLED");
+		return MSD_BOTRESULT_DISCONNECTED;
+	}
+
+	if (status != USBH_URBSTATUS_OK) {
+		uerrf("\tMSD: Status phase: status = %d (!= OK), resetting", status);
+		_msd_bot_reset(lunp->msdp);
+		return MSD_BOTRESULT_ERROR;
+	}
+
+	/* validate CSW */
+	if ((actual_len != sizeof(csw))
+		|| (csw.dCSWSignature != MSD_CSW_SIGNATURE)
+		|| (csw.dCSWTag != lunp->msdp->tag)
+		|| (csw.bCSWStatus >= CSW_STATUS_PHASE_ERROR)) {
+		/* CSW is not valid */
+		uerrf("\tMSD: Status phase: Invalid CSW: len=%d, dCSWSignature=%x, dCSWTag=%x (expected %x), bCSWStatus=%d, resetting",
+				actual_len,
+				csw.dCSWSignature,
+				csw.dCSWTag,
+				lunp->msdp->tag,
+				csw.bCSWStatus);
+		_msd_bot_reset(lunp->msdp);
+		return MSD_BOTRESULT_ERROR;
+	}
+
+	/* check if CSW is meaningful */
+	if ((csw.bCSWStatus != CSW_STATUS_PHASE_ERROR)
+			&& (csw.dCSWDataResidue > tran->cbw->dCBWDataTransferLength)) {
+		/* CSW is not meaningful */
+		uerrf("\tMSD: Status phase: CSW not meaningful: bCSWStatus=%d, dCSWDataResidue=%u, dCBWDataTransferLength=%u, resetting",
+				csw.bCSWStatus,
+				csw.dCSWDataResidue,
+				tran->cbw->dCBWDataTransferLength);
+		_msd_bot_reset(lunp->msdp);
+		return MSD_BOTRESULT_ERROR;
+	}
+
+	if (csw.bCSWStatus == CSW_STATUS_PHASE_ERROR) {
+		uerr("\tMSD: Status phase: Phase error, resetting");
+		_msd_bot_reset(lunp->msdp);
+		return MSD_BOTRESULT_ERROR;
+	}
+
+	tran->data_processed = tran->cbw->dCBWDataTransferLength - csw.dCSWDataResidue;
+	if (data_actual_len < tran->data_processed) {
+		tran->data_processed = data_actual_len;
+	}
+
+	tran->csw_status = csw.bCSWStatus;
+
+	return MSD_BOTRESULT_OK;
+}
+
+
 /* ----------------------------------------------------- */
-/* 			SCSI Commands 								*/
+/* SCSI Commands                                         */
 /* ----------------------------------------------------- */
 
 /* Read 10 and Write 10 */
@@ -299,7 +428,7 @@ typedef struct {
 
 /* Request sense */
 #define SCSI_CMD_REQUEST_SENSE 					0x03
-PACKED_STRUCT {
+typedef PACKED_STRUCT {
 	uint8_t byte[18];
 } scsi_sense_response_t;
 
@@ -333,7 +462,7 @@ PACKED_STRUCT {
 
 /* Inquiry */
 #define SCSI_CMD_INQUIRY 						0x12
-PACKED_STRUCT {
+typedef PACKED_STRUCT {
 	uint8_t peripheral;
 	uint8_t removable;
 	uint8_t version;
@@ -349,14 +478,14 @@ PACKED_STRUCT {
 
 /* Read Capacity 10 */
 #define SCSI_CMD_READ_CAPACITY_10				0x25
-PACKED_STRUCT {
+typedef PACKED_STRUCT {
 	uint32_t last_block_addr;
 	uint32_t block_size;
 } scsi_readcapacity10_response_t;
 
 /* Start/Stop Unit */
 #define SCSI_CMD_START_STOP_UNIT				0x1B
-PACKED_STRUCT {
+typedef PACKED_STRUCT {
 	uint8_t op_code;
 	uint8_t lun_immed;
 	uint8_t res1;
@@ -368,223 +497,187 @@ PACKED_STRUCT {
 /* test unit ready */
 #define SCSI_CMD_TEST_UNIT_READY				0x00
 
-/* Other commands, TODO: use or remove them
-#define SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL	0x1E
-#define SCSI_CMD_VERIFY_10						0x2F
-#define SCSI_CMD_SEND_DIAGNOSTIC				0x1D
-#define SCSI_CMD_MODE_SENSE_6                   0x1A
-*/
+static msd_result_t scsi_requestsense(USBHMassStorageLUNDriver *lunp, scsi_sense_response_t *resp);
 
-static inline void _prepare_cbw(msd_transaction_t *tran, USBHMassStorageLUNDriver *lunp) {
-	tran->cbw.bCBWLUN = (uint8_t)(lunp - &lunp->msdp->luns[0]);
-	memset(&tran->cbw.CBWCB, 0, sizeof(tran->cbw.CBWCB));
-}
-
-static msd_transaction_result_t _msd_transaction(msd_transaction_t *tran, USBHMassStorageLUNDriver *lunp, void *data) {
+static msd_result_t _scsi_perform_transaction(USBHMassStorageLUNDriver *lunp,
+		msd_transaction_t *transaction, void *data) {
 
-	uint32_t actual_len;
-	usbh_urbstatus_t status;
-
-	tran->cbw.dCBWSignature = MSD_CBW_SIGNATURE;
-	tran->cbw.dCBWTag = ++lunp->msdp->tag;
-
-	/* control phase */
-	status = usbhBulkTransfer(&lunp->msdp->epout, &tran->cbw,
-					sizeof(tran->cbw), &actual_len, MS2ST(1000));
-
-	if (status == USBH_URBSTATUS_CANCELLED) {
-		uerr("\tMSD: Control phase: USBH_URBSTATUS_CANCELLED");
-		return MSD_TRANSACTIONRESULT_DISCONNECTED;
-	} else if (status == USBH_URBSTATUS_STALL) {
-		uerr("\tMSD: Control phase: USBH_URBSTATUS_STALL");
-		return MSD_TRANSACTIONRESULT_STALL;
-	} else if (status != USBH_URBSTATUS_OK) {
-		uerrf("\tMSD: Control phase: status = %d, != OK", status);
-		return MSD_TRANSACTIONRESULT_BUS_ERROR;
-	} else if (actual_len != sizeof(tran->cbw)) {
-		uerrf("\tMSD: Control phase: wrong actual_len = %d", actual_len);
-		return MSD_TRANSACTIONRESULT_BUS_ERROR;
+	msd_bot_result_t res;
+	res = _msd_bot_transaction(transaction, lunp, data);
+	if (res != MSD_BOTRESULT_OK) {
+		return (msd_result_t)res;
 	}
 
-
-	/* data phase */
-	if (tran->cbw.dCBWDataTransferLength) {
-		status = usbhBulkTransfer(
-				tran->cbw.bmCBWFlags & MSD_CBWFLAGS_D2H ? &lunp->msdp->epin : &lunp->msdp->epout,
-				data,
-				tran->cbw.dCBWDataTransferLength,
-				&actual_len, MS2ST(20000));
-
-		if (status == USBH_URBSTATUS_CANCELLED) {
-			uerr("\tMSD: Data phase: USBH_URBSTATUS_CANCELLED");
-			return MSD_TRANSACTIONRESULT_DISCONNECTED;
-		} else if (status == USBH_URBSTATUS_STALL) {
-			uerr("\tMSD: Data phase: USBH_URBSTATUS_STALL");
-			return MSD_TRANSACTIONRESULT_STALL;
-		} else if (status != USBH_URBSTATUS_OK) {
-			uerrf("\tMSD: Data phase: status = %d, != OK", status);
-			return MSD_TRANSACTIONRESULT_BUS_ERROR;
-		} else if (actual_len != tran->cbw.dCBWDataTransferLength) {
-			uerrf("\tMSD: Data phase: wrong actual_len = %d", actual_len);
-			return MSD_TRANSACTIONRESULT_BUS_ERROR;
+	if (transaction->csw_status == CSW_STATUS_FAILED) {
+		if (transaction->cbw->CBWCB[0] != SCSI_CMD_REQUEST_SENSE) {
+			/* do auto-sense (except for SCSI_CMD_REQUEST_SENSE!) */
+			uwarn("\tMSD: Command failed, auto-sense");
+			USBH_DEFINE_BUFFER(scsi_sense_response_t sense);
+			if (scsi_requestsense(lunp, &sense) == MSD_RESULT_OK) {
+				uwarnf("\tMSD: REQUEST SENSE: Sense key=%x, ASC=%02x, ASCQ=%02x",
+						sense.byte[2] & 0xf, sense.byte[12], sense.byte[13]);
+			}
 		}
+		return MSD_RESULT_FAILED;
 	}
 
-
-	/* status phase */
-	status = usbhBulkTransfer(&lunp->msdp->epin, &tran->csw,
-			sizeof(tran->csw), &actual_len, MS2ST(1000));
-
-	if (status == USBH_URBSTATUS_CANCELLED) {
-		uerr("\tMSD: Status phase: USBH_URBSTATUS_CANCELLED");
-		return MSD_TRANSACTIONRESULT_DISCONNECTED;
-	} else if (status == USBH_URBSTATUS_STALL) {
-		uerr("\tMSD: Status phase: USBH_URBSTATUS_STALL");
-		return MSD_TRANSACTIONRESULT_STALL;
-	} else if (status != USBH_URBSTATUS_OK) {
-		uerrf("\tMSD: Status phase: status = %d, != OK", status);
-		return MSD_TRANSACTIONRESULT_BUS_ERROR;
-	} else if (actual_len != sizeof(tran->csw)) {
-		uerrf("\tMSD: Status phase: wrong actual_len = %d", actual_len);
-		return MSD_TRANSACTIONRESULT_BUS_ERROR;
-	} else if (tran->csw.dCSWSignature != MSD_CSW_SIGNATURE) {
-		uerr("\tMSD: Status phase: wrong signature");
-		return MSD_TRANSACTIONRESULT_BUS_ERROR;
-	} else if (tran->csw.dCSWTag != lunp->msdp->tag) {
-		uerrf("\tMSD: Status phase: wrong tag (expected %d, got %d)",
-				lunp->msdp->tag, tran->csw.dCSWTag);
-		return MSD_TRANSACTIONRESULT_SYNC_ERROR;
-	}
-
-	if (tran->csw.dCSWDataResidue) {
-		uwarnf("\tMSD: Residue=%d", tran->csw.dCSWDataResidue);
-	}
-
-	return MSD_TRANSACTIONRESULT_OK;
+	return MSD_RESULT_OK;
 }
 
-
 static msd_result_t scsi_inquiry(USBHMassStorageLUNDriver *lunp, scsi_inquiry_response_t *resp) {
+	USBH_DEFINE_BUFFER(msd_cbw_t cbw);
 	msd_transaction_t transaction;
 	msd_result_t res;
 
-	_prepare_cbw(&transaction, lunp);
-	transaction.cbw.dCBWDataTransferLength = sizeof(scsi_inquiry_response_t);
-	transaction.cbw.bmCBWFlags = MSD_CBWFLAGS_D2H;
-	transaction.cbw.bCBWCBLength = 6;
-	transaction.cbw.CBWCB[0] = SCSI_CMD_INQUIRY;
-	transaction.cbw.CBWCB[4] = sizeof(scsi_inquiry_response_t);
-
-	res.tres = _msd_transaction(&transaction, lunp, resp);
-	if (res.tres == MSD_TRANSACTIONRESULT_OK) {
-		res.cres = (msd_command_result_t) transaction.csw.bCSWStatus;
+	memset(cbw.CBWCB, 0, sizeof(cbw.CBWCB));
+	cbw.dCBWDataTransferLength = sizeof(scsi_inquiry_response_t);
+	cbw.bmCBWFlags = MSD_CBWFLAGS_D2H;
+	cbw.bCBWCBLength = 6;
+	cbw.CBWCB[0] = SCSI_CMD_INQUIRY;
+	cbw.CBWCB[4] = sizeof(scsi_inquiry_response_t);
+	transaction.cbw = &cbw;
+
+	res = _scsi_perform_transaction(lunp, &transaction, resp);
+	if (res == MSD_RESULT_OK) {
+		//transaction is OK; check length
+		if (transaction.data_processed < cbw.dCBWDataTransferLength) {
+			res = MSD_RESULT_TRANSPORT_ERROR;
+		}
 	}
+
 	return res;
 }
 
 static msd_result_t scsi_requestsense(USBHMassStorageLUNDriver *lunp, scsi_sense_response_t *resp) {
+	USBH_DEFINE_BUFFER(msd_cbw_t cbw);
 	msd_transaction_t transaction;
 	msd_result_t res;
 
-	_prepare_cbw(&transaction, lunp);
-	transaction.cbw.dCBWDataTransferLength = sizeof(scsi_sense_response_t);
-	transaction.cbw.bmCBWFlags = MSD_CBWFLAGS_D2H;
-	transaction.cbw.bCBWCBLength = 12;
-	transaction.cbw.CBWCB[0] = SCSI_CMD_REQUEST_SENSE;
-	transaction.cbw.CBWCB[4] = sizeof(scsi_sense_response_t);
-
-	res.tres = _msd_transaction(&transaction, lunp, resp);
-	if (res.tres == MSD_TRANSACTIONRESULT_OK) {
-		res.cres = (msd_command_result_t) transaction.csw.bCSWStatus;
+	memset(cbw.CBWCB, 0, sizeof(cbw.CBWCB));
+	cbw.dCBWDataTransferLength = sizeof(scsi_sense_response_t);
+	cbw.bmCBWFlags = MSD_CBWFLAGS_D2H;
+	cbw.bCBWCBLength = 12;
+	cbw.CBWCB[0] = SCSI_CMD_REQUEST_SENSE;
+	cbw.CBWCB[4] = sizeof(scsi_sense_response_t);
+	transaction.cbw = &cbw;
+
+	res = _scsi_perform_transaction(lunp, &transaction, resp);
+	if (res == MSD_RESULT_OK) {
+		//transaction is OK; check length
+		if (transaction.data_processed < cbw.dCBWDataTransferLength) {
+			res = MSD_RESULT_TRANSPORT_ERROR;
+		}
 	}
+
 	return res;
 }
 
 static msd_result_t scsi_testunitready(USBHMassStorageLUNDriver *lunp) {
+	USBH_DEFINE_BUFFER(msd_cbw_t cbw);
 	msd_transaction_t transaction;
-	msd_result_t res;
 
-	_prepare_cbw(&transaction, lunp);
-	transaction.cbw.dCBWDataTransferLength = 0;
-	transaction.cbw.bmCBWFlags = MSD_CBWFLAGS_D2H;
-	transaction.cbw.bCBWCBLength = 6;
-	transaction.cbw.CBWCB[0] = SCSI_CMD_TEST_UNIT_READY;
+	memset(cbw.CBWCB, 0, sizeof(cbw.CBWCB));
+	cbw.dCBWDataTransferLength = 0;
+	cbw.bmCBWFlags = MSD_CBWFLAGS_D2H;
+	cbw.bCBWCBLength = 6;
+	cbw.CBWCB[0] = SCSI_CMD_TEST_UNIT_READY;
+	transaction.cbw = &cbw;
 
-	res.tres = _msd_transaction(&transaction, lunp, NULL);
-	if (res.tres == MSD_TRANSACTIONRESULT_OK) {
-		res.cres = (msd_command_result_t) transaction.csw.bCSWStatus;
-	}
-	return res;
+	return _scsi_perform_transaction(lunp, &transaction, NULL);
 }
 
 static msd_result_t scsi_readcapacity10(USBHMassStorageLUNDriver *lunp, scsi_readcapacity10_response_t *resp) {
+	USBH_DEFINE_BUFFER(msd_cbw_t cbw);
 	msd_transaction_t transaction;
 	msd_result_t res;
 
-	_prepare_cbw(&transaction, lunp);
-	transaction.cbw.dCBWDataTransferLength = sizeof(scsi_readcapacity10_response_t);
-	transaction.cbw.bmCBWFlags = MSD_CBWFLAGS_D2H;
-	transaction.cbw.bCBWCBLength = 12;
-	transaction.cbw.CBWCB[0] = SCSI_CMD_READ_CAPACITY_10;
-
-	res.tres = _msd_transaction(&transaction, lunp, resp);
-	if (res.tres == MSD_TRANSACTIONRESULT_OK) {
-		res.cres = (msd_command_result_t) transaction.csw.bCSWStatus;
+	memset(cbw.CBWCB, 0, sizeof(cbw.CBWCB));
+	cbw.dCBWDataTransferLength = sizeof(scsi_readcapacity10_response_t);
+	cbw.bmCBWFlags = MSD_CBWFLAGS_D2H;
+	cbw.bCBWCBLength = 12;
+	cbw.CBWCB[0] = SCSI_CMD_READ_CAPACITY_10;
+	transaction.cbw = &cbw;
+
+	res = _scsi_perform_transaction(lunp, &transaction, resp);
+	if (res == MSD_RESULT_OK) {
+		//transaction is OK; check length
+		if (transaction.data_processed < cbw.dCBWDataTransferLength) {
+			res = MSD_RESULT_TRANSPORT_ERROR;
+		}
 	}
+
 	return res;
 }
 
 
-static msd_result_t scsi_read10(USBHMassStorageLUNDriver *lunp, uint32_t lba, uint16_t n, uint8_t *data) {
+static msd_result_t scsi_read10(USBHMassStorageLUNDriver *lunp, uint32_t lba, uint16_t n, uint8_t *data, uint32_t *actual_len) {
+	USBH_DEFINE_BUFFER(msd_cbw_t cbw);
 	msd_transaction_t transaction;
 	msd_result_t res;
 
-	_prepare_cbw(&transaction, lunp);
-	transaction.cbw.dCBWDataTransferLength = n * lunp->info.blk_size;
-	transaction.cbw.bmCBWFlags = MSD_CBWFLAGS_D2H;
-	transaction.cbw.bCBWCBLength = 10;
-	transaction.cbw.CBWCB[0] = SCSI_CMD_READ_10;
-	transaction.cbw.CBWCB[2] = (uint8_t)(lba >> 24);
-	transaction.cbw.CBWCB[3] = (uint8_t)(lba >> 16);
-	transaction.cbw.CBWCB[4] = (uint8_t)(lba >> 8);
-	transaction.cbw.CBWCB[5] = (uint8_t)(lba);
-	transaction.cbw.CBWCB[7] = (uint8_t)(n >> 8);
-	transaction.cbw.CBWCB[8] = (uint8_t)(n);
-
-	res.tres = _msd_transaction(&transaction, lunp, data);
-	if (res.tres == MSD_TRANSACTIONRESULT_OK) {
-		res.cres = (msd_command_result_t) transaction.csw.bCSWStatus;
+	memset(cbw.CBWCB, 0, sizeof(cbw.CBWCB));
+	cbw.dCBWDataTransferLength = n * lunp->info.blk_size;
+	cbw.bmCBWFlags = MSD_CBWFLAGS_D2H;
+	cbw.bCBWCBLength = 10;
+	cbw.CBWCB[0] = SCSI_CMD_READ_10;
+	cbw.CBWCB[2] = (uint8_t)(lba >> 24);
+	cbw.CBWCB[3] = (uint8_t)(lba >> 16);
+	cbw.CBWCB[4] = (uint8_t)(lba >> 8);
+	cbw.CBWCB[5] = (uint8_t)(lba);
+	cbw.CBWCB[7] = (uint8_t)(n >> 8);
+	cbw.CBWCB[8] = (uint8_t)(n);
+	transaction.cbw = &cbw;
+
+	res = _scsi_perform_transaction(lunp, &transaction, data);
+	if (actual_len) {
+		*actual_len = transaction.data_processed;
 	}
+	if (res == MSD_RESULT_OK) {
+		//transaction is OK; check length
+		if (transaction.data_processed < cbw.dCBWDataTransferLength) {
+			res = MSD_RESULT_TRANSPORT_ERROR;
+		}
+	}
+
 	return res;
 }
 
-static msd_result_t scsi_write10(USBHMassStorageLUNDriver *lunp, uint32_t lba, uint16_t n, const uint8_t *data) {
+static msd_result_t scsi_write10(USBHMassStorageLUNDriver *lunp, uint32_t lba, uint16_t n, const uint8_t *data, uint32_t *actual_len) {
+	USBH_DEFINE_BUFFER(msd_cbw_t cbw);
 	msd_transaction_t transaction;
 	msd_result_t res;
 
-	_prepare_cbw(&transaction, lunp);
-	transaction.cbw.dCBWDataTransferLength = n * lunp->info.blk_size;
-	transaction.cbw.bmCBWFlags = MSD_CBWFLAGS_H2D;
-	transaction.cbw.bCBWCBLength = 10;
-	transaction.cbw.CBWCB[0] = SCSI_CMD_WRITE_10;
-	transaction.cbw.CBWCB[2] = (uint8_t)(lba >> 24);
-	transaction.cbw.CBWCB[3] = (uint8_t)(lba >> 16);
-	transaction.cbw.CBWCB[4] = (uint8_t)(lba >> 8);
-	transaction.cbw.CBWCB[5] = (uint8_t)(lba);
-	transaction.cbw.CBWCB[7] = (uint8_t)(n >> 8);
-	transaction.cbw.CBWCB[8] = (uint8_t)(n);
-
-	res.tres = _msd_transaction(&transaction, lunp, (uint8_t *)data);
-	if (res.tres == MSD_TRANSACTIONRESULT_OK) {
-		res.cres = (msd_command_result_t) transaction.csw.bCSWStatus;
+	memset(cbw.CBWCB, 0, sizeof(cbw.CBWCB));
+	cbw.dCBWDataTransferLength = n * lunp->info.blk_size;
+	cbw.bmCBWFlags = MSD_CBWFLAGS_H2D;
+	cbw.bCBWCBLength = 10;
+	cbw.CBWCB[0] = SCSI_CMD_WRITE_10;
+	cbw.CBWCB[2] = (uint8_t)(lba >> 24);
+	cbw.CBWCB[3] = (uint8_t)(lba >> 16);
+	cbw.CBWCB[4] = (uint8_t)(lba >> 8);
+	cbw.CBWCB[5] = (uint8_t)(lba);
+	cbw.CBWCB[7] = (uint8_t)(n >> 8);
+	cbw.CBWCB[8] = (uint8_t)(n);
+	transaction.cbw = &cbw;
+
+	res = _scsi_perform_transaction(lunp, &transaction, (void *)data);
+	if (actual_len) {
+		*actual_len = transaction.data_processed;
+	}
+	if (res == MSD_RESULT_OK) {
+		//transaction is OK; check length
+		if (transaction.data_processed < cbw.dCBWDataTransferLength) {
+			res = MSD_RESULT_TRANSPORT_ERROR;
+		}
 	}
+
 	return res;
 }
 
 
 
 /*===========================================================================*/
-/* Block driver data/functions								 		 	 	 */
+/* Block driver data/functions                                               */
 /*===========================================================================*/
 
 USBHMassStorageLUNDriver MSBLKD[HAL_USBHMSD_MAX_LUNS];
@@ -600,39 +693,22 @@ static const struct USBHMassStorageDriverVMT blk_vmt = {
 	(bool (*)(void *, BlockDeviceInfo *))usbhmsdLUNGetInfo
 };
 
-
-
-static uint32_t _requestsense(USBHMassStorageLUNDriver *lunp) {
-	scsi_sense_response_t sense;
-	msd_result_t res;
-
-	res = scsi_requestsense(lunp, &sense);
-	if (res.tres != MSD_TRANSACTIONRESULT_OK) {
-		uerr("\tREQUEST SENSE: Transaction error");
-		goto failed;
-	} else if (res.cres == MSD_COMMANDRESULT_FAILED) {
-		uerr("\tREQUEST SENSE: Command Failed");
-		goto failed;
-	} else if (res.cres == MSD_COMMANDRESULT_PHASE_ERROR) {
-		//TODO: Do reset, etc.
-		uerr("\tREQUEST SENSE: Command Phase Error");
-		goto failed;
-	}
-
-	uerrf("\tREQUEST SENSE: Sense key=%x, ASC=%02x, ASCQ=%02x",
-			sense.byte[2] & 0xf, sense.byte[12], sense.byte[13]);
-
-	return (sense.byte[2] & 0xf) | (sense.byte[12] << 8) | (sense.byte[13] << 16);
-
-failed:
-	return 0xffffffff;
+static void _lun_object_deinit(USBHMassStorageLUNDriver *lunp) {
+	osalDbgCheck(lunp != NULL);
+	chSemWait(&lunp->sem);
+	lunp->msdp = NULL;
+	lunp->next = NULL;
+	memset(&lunp->info, 0, sizeof(lunp->info));
+	lunp->state = BLK_STOP;
+	chSemSignal(&lunp->sem);
 }
 
-void usbhmsdLUNObjectInit(USBHMassStorageLUNDriver *lunp) {
+static void _lun_object_init(USBHMassStorageLUNDriver *lunp) {
 	osalDbgCheck(lunp != NULL);
 	memset(lunp, 0, sizeof(*lunp));
 	lunp->vmt = &blk_vmt;
 	lunp->state = BLK_STOP;
+	chSemObjectInit(&lunp->sem, 1);
 	/* Unnecessary because of the memset:
 		lunp->msdp = NULL;
 		lunp->next = NULL;
@@ -640,150 +716,111 @@ void usbhmsdLUNObjectInit(USBHMassStorageLUNDriver *lunp) {
 	*/
 }
 
-void usbhmsdLUNStart(USBHMassStorageLUNDriver *lunp) {
-	osalDbgCheck(lunp != NULL);
-	osalSysLock();
-	osalDbgAssert((lunp->state == BLK_STOP) || (lunp->state == BLK_ACTIVE),
-			"invalid state");
-	//TODO: complete
-	//lunp->state = BLK_ACTIVE;
-	osalSysUnlock();
-}
-
-void usbhmsdLUNStop(USBHMassStorageLUNDriver *lunp) {
-	osalDbgCheck(lunp != NULL);
-	osalSysLock();
-	osalDbgAssert((lunp->state == BLK_STOP) || (lunp->state == BLK_ACTIVE),
-			"invalid state");
-	//TODO: complete
-	//lunp->state = BLK_STOP;
-	osalSysUnlock();
-}
-
 bool usbhmsdLUNConnect(USBHMassStorageLUNDriver *lunp) {
-	USBHMassStorageDriver *const msdp = lunp->msdp;
+	osalDbgCheck(lunp != NULL);
+	osalDbgCheck(lunp->msdp != NULL);
 	msd_result_t res;
 
-	osalDbgCheck(msdp != NULL);
-	osalSysLock();
-	//osalDbgAssert((lunp->state == BLK_ACTIVE) || (lunp->state == BLK_READY),
-    //            "invalid state");
+	chSemWait(&lunp->sem);
+	osalDbgAssert((lunp->state == BLK_READY) || (lunp->state == BLK_ACTIVE), "invalid state");
 	if (lunp->state == BLK_READY) {
-	    osalSysUnlock();
+		chSemSignal(&lunp->sem);
 		return HAL_SUCCESS;
-	} else if (lunp->state != BLK_ACTIVE) {
-		osalSysUnlock();
-		return HAL_FAILED;
 	}
 	lunp->state = BLK_CONNECTING;
-    osalSysUnlock();
 
-    osalMutexLock(&msdp->mtx);
-
-    USBH_DEFINE_BUFFER(union {
-    		scsi_inquiry_response_t inq;
-    		scsi_readcapacity10_response_t cap;	}, u);
-
-	uinfo("INQUIRY...");
-	res = scsi_inquiry(lunp, &u.inq);
-	if (res.tres != MSD_TRANSACTIONRESULT_OK) {
-		uerr("\tINQUIRY: Transaction error");
-		goto failed;
-	} else if (res.cres == MSD_COMMANDRESULT_FAILED) {
-		uerr("\tINQUIRY: Command Failed");
-		_requestsense(lunp);
-		goto failed;
-	} else if (res.cres == MSD_COMMANDRESULT_PHASE_ERROR) {
-		//TODO: Do reset, etc.
-		uerr("\tINQUIRY: Command Phase Error");
-		goto failed;
-	}
+    {
+		USBH_DEFINE_BUFFER(scsi_inquiry_response_t inq);
+		uinfo("INQUIRY...");
+		res = scsi_inquiry(lunp, &inq);
+		if (res == MSD_RESULT_DISCONNECTED) {
+			goto failed;
+		} else if (res == MSD_RESULT_TRANSPORT_ERROR) {
+			//retry?
+			goto failed;
+		} else if (res == MSD_RESULT_FAILED) {
+			//retry?
+			goto failed;
+		}
 
-	uinfof("\tPDT=%02x", u.inq.peripheral & 0x1f);
-	if (u.inq.peripheral != 0) {
-		uerr("\tUnsupported PDT");
-		goto failed;
+		uinfof("\tPDT=%02x", inq.peripheral & 0x1f);
+		if (inq.peripheral != 0) {
+			uerr("\tUnsupported PDT");
+			goto failed;
+		}
 	}
 
 	// Test if unit ready
-	uint8_t i;
+    uint8_t i;
 	for (i = 0; i < 10; i++) {
 		uinfo("TEST UNIT READY...");
 		res = scsi_testunitready(lunp);
-		if (res.tres != MSD_TRANSACTIONRESULT_OK) {
-			uerr("\tTEST UNIT READY: Transaction error");
+		if (res == MSD_RESULT_DISCONNECTED) {
 			goto failed;
-		} else if (res.cres == MSD_COMMANDRESULT_FAILED) {
-			uerr("\tTEST UNIT READY: Command Failed");
-			_requestsense(lunp);
-			continue;
-		} else if (res.cres == MSD_COMMANDRESULT_PHASE_ERROR) {
-			//TODO: Do reset, etc.
-			uerr("\tTEST UNIT READY: Command Phase Error");
+		} else if (res == MSD_RESULT_TRANSPORT_ERROR) {
+			//retry?
 			goto failed;
+		} else if (res == MSD_RESULT_FAILED) {
+			uinfo("\tTEST UNIT READY: Command Failed, retry");
+			osalThreadSleepMilliseconds(200);
+			continue;
 		}
 		uinfo("\tReady.");
 		break;
-		// osalThreadSleepMilliseconds(200); // will raise 'code is unreachable' warning
 	}
 	if (i == 10) goto failed;
 
-	// Read capacity
-	uinfo("READ CAPACITY(10)...");
-	res = scsi_readcapacity10(lunp, &u.cap);
-	if (res.tres != MSD_TRANSACTIONRESULT_OK) {
-		uerr("\tREAD CAPACITY(10): Transaction error");
-		goto failed;
-	} else if (res.cres == MSD_COMMANDRESULT_FAILED) {
-		uerr("\tREAD CAPACITY(10): Command Failed");
-		_requestsense(lunp);
-		goto failed;
-	} else if (res.cres == MSD_COMMANDRESULT_PHASE_ERROR) {
-		//TODO: Do reset, etc.
-		uerr("\tREAD CAPACITY(10): Command Phase Error");
-		goto failed;
-	}
-	lunp->info.blk_size = __REV(u.cap.block_size);
-	lunp->info.blk_num = __REV(u.cap.last_block_addr) + 1;
+	{
+		USBH_DEFINE_BUFFER(scsi_readcapacity10_response_t cap);
+		// Read capacity
+		uinfo("READ CAPACITY(10)...");
+		res = scsi_readcapacity10(lunp, &cap);
+		if (res == MSD_RESULT_DISCONNECTED) {
+			goto failed;
+		} else if (res == MSD_RESULT_TRANSPORT_ERROR) {
+			//retry?
+			goto failed;
+		} else if (res == MSD_RESULT_FAILED) {
+			//retry?
+			goto failed;
+		}
+
+		lunp->info.blk_size = __REV(cap.block_size);
+		lunp->info.blk_num = __REV(cap.last_block_addr) + 1;
+	}
+
 	uinfof("\tBlock size=%dbytes, blocks=%u (~%u MB)", lunp->info.blk_size, lunp->info.blk_num,
 		(uint32_t)(((uint64_t)lunp->info.blk_size * lunp->info.blk_num) / (1024UL * 1024UL)));
 
 	uinfo("MSD Connected.");
-
-	osalMutexUnlock(&msdp->mtx);
-	osalSysLock();
 	lunp->state = BLK_READY;
-    osalSysUnlock();
-
+	chSemSignal(&lunp->sem);
 	return HAL_SUCCESS;
 
   /* Connection failed, state reset to BLK_ACTIVE.*/
 failed:
-	osalMutexUnlock(&msdp->mtx);
-	osalSysLock();
+	uinfo("MSD Connect failed.");
 	lunp->state = BLK_ACTIVE;
-    osalSysUnlock();
+	chSemSignal(&lunp->sem);
 	return HAL_FAILED;
 }
 
-
 bool usbhmsdLUNDisconnect(USBHMassStorageLUNDriver *lunp) {
 	osalDbgCheck(lunp != NULL);
-	osalSysLock();
-	osalDbgAssert((lunp->state == BLK_ACTIVE) || (lunp->state == BLK_READY),
-				"invalid state");
+
+	chSemWait(&lunp->sem);
+	osalDbgAssert((lunp->state == BLK_READY) || (lunp->state == BLK_ACTIVE), "invalid state");
 	if (lunp->state == BLK_ACTIVE) {
-		osalSysUnlock();
+		chSemSignal(&lunp->sem);
 		return HAL_SUCCESS;
 	}
 	lunp->state = BLK_DISCONNECTING;
-	osalSysUnlock();
 
-	//TODO: complete
+	//TODO: complete: sync, etc.
 
-	osalSysLock();
 	lunp->state = BLK_ACTIVE;
-	osalSysUnlock();
+	chSemSignal(&lunp->sem);
+
 	return HAL_SUCCESS;
 }
 
@@ -794,34 +831,29 @@ bool usbhmsdLUNRead(USBHMassStorageLUNDriver *lunp, uint32_t startblk,
 	bool ret = HAL_FAILED;
 	uint16_t blocks;
 	msd_result_t res;
+	uint32_t actual_len;
 
-	osalSysLock();
+	chSemWait(&lunp->sem);
 	if (lunp->state != BLK_READY) {
-		osalSysUnlock();
+		chSemSignal(&lunp->sem);
 		return ret;
 	}
 	lunp->state = BLK_READING;
-    osalSysUnlock();
 
-	osalMutexLock(&lunp->msdp->mtx);
 	while (n) {
 		if (n > 0xffff) {
 			blocks = 0xffff;
 		} else {
 			blocks = (uint16_t)n;
 		}
-		res = scsi_read10(lunp, startblk, blocks, buffer);
-		if (res.tres != MSD_TRANSACTIONRESULT_OK) {
-			uerr("\tREAD (10): Transaction error");
+		res = scsi_read10(lunp, startblk, blocks, buffer, &actual_len);
+		if (res == MSD_RESULT_DISCONNECTED) {
 			goto exit;
-		} else if (res.cres == MSD_COMMANDRESULT_FAILED) {
-			//TODO: request sense, and act appropriately
-			uerr("\tREAD (10): Command Failed");
-			_requestsense(lunp);
+		} else if (res == MSD_RESULT_TRANSPORT_ERROR) {
+			//retry?
 			goto exit;
-		} else if (res.cres == MSD_COMMANDRESULT_PHASE_ERROR) {
-			//TODO: Do reset, etc.
-			uerr("\tREAD (10): Command Phase Error");
+		} else if (res == MSD_RESULT_FAILED) {
+			//retry?
 			goto exit;
 		}
 		n -= blocks;
@@ -832,15 +864,8 @@ bool usbhmsdLUNRead(USBHMassStorageLUNDriver *lunp, uint32_t startblk,
 	ret = HAL_SUCCESS;
 
 exit:
-	osalMutexUnlock(&lunp->msdp->mtx);
-	osalSysLock();
-	if (lunp->state == BLK_READING) {
-		lunp->state = BLK_READY;
-	} else {
-		osalDbgCheck(lunp->state == BLK_STOP);
-		uwarn("MSD: State = BLK_STOP");
-	}
-    osalSysUnlock();
+	lunp->state = BLK_READY;
+	chSemSignal(&lunp->sem);
 	return ret;
 }
 
@@ -851,34 +876,29 @@ bool usbhmsdLUNWrite(USBHMassStorageLUNDriver *lunp, uint32_t startblk,
 	bool ret = HAL_FAILED;
 	uint16_t blocks;
 	msd_result_t res;
+	uint32_t actual_len;
 
-	osalSysLock();
+	chSemWait(&lunp->sem);
 	if (lunp->state != BLK_READY) {
-		osalSysUnlock();
+		chSemSignal(&lunp->sem);
 		return ret;
 	}
 	lunp->state = BLK_WRITING;
-    osalSysUnlock();
 
-	osalMutexLock(&lunp->msdp->mtx);
 	while (n) {
 		if (n > 0xffff) {
 			blocks = 0xffff;
 		} else {
 			blocks = (uint16_t)n;
 		}
-		res = scsi_write10(lunp, startblk, blocks, buffer);
-		if (res.tres != MSD_TRANSACTIONRESULT_OK) {
-			uerr("\tWRITE (10): Transaction error");
+		res = scsi_write10(lunp, startblk, blocks, buffer, &actual_len);
+		if (res == MSD_RESULT_DISCONNECTED) {
 			goto exit;
-		} else if (res.cres == MSD_COMMANDRESULT_FAILED) {
-			//TODO: request sense, and act appropriately
-			uerr("\tWRITE (10): Command Failed");
-			_requestsense(lunp);
+		} else if (res == MSD_RESULT_TRANSPORT_ERROR) {
+			//retry?
 			goto exit;
-		} else if (res.cres == MSD_COMMANDRESULT_PHASE_ERROR) {
-			//TODO: Do reset, etc.
-			uerr("\tWRITE (10): Command Phase Error");
+		} else if (res == MSD_RESULT_FAILED) {
+			//retry?
 			goto exit;
 		}
 		n -= blocks;
@@ -889,15 +909,8 @@ bool usbhmsdLUNWrite(USBHMassStorageLUNDriver *lunp, uint32_t startblk,
 	ret = HAL_SUCCESS;
 
 exit:
-	osalMutexUnlock(&lunp->msdp->mtx);
-	osalSysLock();
-	if (lunp->state == BLK_WRITING) {
-		lunp->state = BLK_READY;
-	} else {
-		osalDbgCheck(lunp->state == BLK_STOP);
-		uwarn("MSD: State = BLK_STOP");
-	}
-	osalSysUnlock();
+	lunp->state = BLK_READY;
+	chSemSignal(&lunp->sem);
 	return ret;
 }
 
@@ -911,29 +924,41 @@ bool usbhmsdLUNSync(USBHMassStorageLUNDriver *lunp) {
 bool usbhmsdLUNGetInfo(USBHMassStorageLUNDriver *lunp, BlockDeviceInfo *bdip) {
 	osalDbgCheck(lunp != NULL);
 	osalDbgCheck(bdip != NULL);
-	*bdip = lunp->info;
-	return HAL_SUCCESS;
+
+	osalSysLock();
+	if (lunp->state >= BLK_READY) {
+		*bdip = lunp->info;
+		osalSysUnlock();
+		return HAL_SUCCESS;
+	}
+	osalSysUnlock();
+	return HAL_FAILED;
 }
 
 bool usbhmsdLUNIsInserted(USBHMassStorageLUNDriver *lunp) {
 	osalDbgCheck(lunp != NULL);
-	blkstate_t state;
-	osalSysLock();
-	state = lunp->state;
-	osalSysUnlock();
-	return (state >= BLK_ACTIVE);
+	return (lunp->state >= BLK_ACTIVE);
 }
 
 bool usbhmsdLUNIsProtected(USBHMassStorageLUNDriver *lunp) {
 	osalDbgCheck(lunp != NULL);
+	//TODO: Implement
 	return FALSE;
 }
 
-void usbhmsdObjectInit(USBHMassStorageDriver *msdp) {
+static void _msd_object_init(USBHMassStorageDriver *msdp) {
 	osalDbgCheck(msdp != NULL);
 	memset(msdp, 0, sizeof(*msdp));
 	msdp->info = &usbhmsdClassDriverInfo;
-	osalMutexObjectInit(&msdp->mtx);
 }
 
+static void _msd_init(void) {
+	uint8_t i;
+	for (i = 0; i < HAL_USBHMSD_MAX_INSTANCES; i++) {
+		_msd_object_init(&USBHMSD[i]);
+	}
+	for (i = 0; i < HAL_USBHMSD_MAX_LUNS; i++) {
+		_lun_object_init(&MSBLKD[i]);
+	}
+}
 #endif
diff --git a/os/hal/src/usbh/hal_usbh_uvc.c b/os/hal/src/usbh/hal_usbh_uvc.c
index 09a0f1d..a795cd8 100644
--- a/os/hal/src/usbh/hal_usbh_uvc.c
+++ b/os/hal/src/usbh/hal_usbh_uvc.c
@@ -1,6 +1,6 @@
 /*
-    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
-              Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail)
+    ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio
+              Copyright (C) 2015..2017 Diego Ismirlian, (dismirlian (at) google's mail)
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -13,10 +13,9 @@
     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
     See the License for the specific language governing permissions and
     limitations under the License.
-*/
+ */
 
 #include "hal.h"
-#include "hal_usbh.h"
 
 #if HAL_USBH_USE_UVC
 
@@ -28,6 +27,10 @@
 #error "USBHUVC needs HAL_USBH_USE_IAD"
 #endif
 
+#include <string.h>
+#include "usbh/dev/uvc.h"
+#include "usbh/internal.h"
+
 #if USBHUVC_DEBUG_ENABLE_TRACE
 #define udbgf(f, ...)  usbDbgPrintf(f, ##__VA_ARGS__)
 #define udbg(f, ...)  usbDbgPuts(f, ##__VA_ARGS__)
@@ -61,28 +64,673 @@
 #endif
 
 
-static usbh_baseclassdriver_t *uvc_load(usbh_device_t *dev,
+USBHUVCDriver USBHUVCD[HAL_USBHUVC_MAX_INSTANCES];
+
+static void _uvc_init(void);
+static usbh_baseclassdriver_t *_uvc_load(usbh_device_t *dev,
 		const uint8_t *descriptor, uint16_t rem);
-static void uvc_unload(usbh_baseclassdriver_t *drv);
+static void _uvc_unload(usbh_baseclassdriver_t *drv);
 
 static const usbh_classdriver_vmt_t class_driver_vmt = {
-	uvc_load,
-	uvc_unload
+	_uvc_init,
+	_uvc_load,
+	_uvc_unload
 };
 const usbh_classdriverinfo_t usbhuvcClassDriverInfo = {
-	0x0e, 0x03, 0x00, "UVC", &class_driver_vmt
+	"UVC", &class_driver_vmt
 };
 
+static bool _request(USBHUVCDriver *uvcdp,
+		uint8_t bRequest, uint8_t entity, uint8_t control,
+		uint16_t wLength, uint8_t *data, uint8_t interf) {
+
+	usbh_urbstatus_t res;
+
+	if (bRequest & 0x80) {
+		res = usbhControlRequest(uvcdp->dev,
+				USBH_REQTYPE_CLASSIN(USBH_REQTYPE_RECIP_INTERFACE),
+				bRequest,
+				((control) << 8),
+				(interf) | ((entity) << 8),
+				wLength, data);
+	} else {
+		res = usbhControlRequest(uvcdp->dev,
+				USBH_REQTYPE_CLASSOUT(USBH_REQTYPE_RECIP_INTERFACE),
+				bRequest,
+				((control) << 8),
+				(interf) | ((entity) << 8),
+				wLength, data);
+	}
+
+	if (res != USBH_URBSTATUS_OK)
+		return HAL_FAILED;
+
+	 return HAL_SUCCESS;
+}
+
+bool usbhuvcVCRequest(USBHUVCDriver *uvcdp,
+		uint8_t bRequest, uint8_t entity, uint8_t control,
+		uint16_t wLength, uint8_t *data) {
+	return _request(uvcdp, bRequest, entity, control, wLength, data, if_get(&uvcdp->ivc)->bInterfaceNumber);
+}
+
+bool usbhuvcVSRequest(USBHUVCDriver *uvcdp,
+		uint8_t bRequest, uint8_t control,
+		uint16_t wLength, uint8_t *data) {
+
+	return _request(uvcdp, bRequest, 0, control, wLength, data, if_get(&uvcdp->ivs)->bInterfaceNumber);
+}
+
+static bool _set_vs_alternate(USBHUVCDriver *uvcdp, uint16_t min_ep_size) {
+
+	if (min_ep_size == 0) {
+		uinfo("Selecting Alternate setting 0");
+		return usbhStdReqSetInterface(uvcdp->dev, if_get(&uvcdp->ivs)->bInterfaceNumber, 0);
+	}
+
+	if_iterator_t iif = uvcdp->ivs;
+	generic_iterator_t iep;
+	const usbh_endpoint_descriptor_t *ep = NULL;
+	uint8_t alt = 0;
+	uint16_t sz = 0xffff;
+
+	uinfof("Searching alternate setting with min_ep_size=%d", min_ep_size);
+
+	for (; iif.valid; if_iter_next(&iif)) {
+		const usbh_interface_descriptor_t *const ifdesc = if_get(&iif);
+
+		if ((ifdesc->bInterfaceClass != UVC_CC_VIDEO)
+				|| (ifdesc->bInterfaceSubClass != UVC_SC_VIDEOSTREAMING))
+			continue;
+
+		uinfof("\tScanning alternate setting=%d", ifdesc->bAlternateSetting);
+
+		if (ifdesc->bNumEndpoints == 0)
+			continue;
+
+		for (ep_iter_init(&iep, &iif); iep.valid; ep_iter_next(&iep)) {
+			const usbh_endpoint_descriptor_t *const epdesc = ep_get(&iep);
+			if (((epdesc->bmAttributes & 0x03) == USBH_EPTYPE_ISO)
+					&& ((epdesc->bEndpointAddress & 0x80) ==  USBH_EPDIR_IN)) {
+
+				uinfof("\t  Endpoint wMaxPacketSize = %d", epdesc->wMaxPacketSize);
+
+				if (epdesc->wMaxPacketSize >= min_ep_size) {
+					if (epdesc->wMaxPacketSize < sz) {
+						uinfo("\t    Found new optimal alternate setting");
+						sz = epdesc->wMaxPacketSize;
+						alt = ifdesc->bAlternateSetting;
+						ep = epdesc;
+					}
+				}
+			}
+		}
+	}
+
+	if (ep && alt) {
+		uinfof("\tSelecting Alternate setting %d", alt);
+		if (usbhStdReqSetInterface(uvcdp->dev, if_get(&uvcdp->ivs)->bInterfaceNumber, alt) == HAL_SUCCESS) {
+			usbhEPObjectInit(&uvcdp->ep_iso, uvcdp->dev, ep);
+			usbhEPSetName(&uvcdp->ep_iso, "UVC[ISO ]");
+			return HAL_SUCCESS;
+		}
+	}
+
+	return HAL_FAILED;
+}
+
+#if	USBH_DEBUG_ENABLE && USBHUVC_DEBUG_ENABLE_INFO
+void usbhuvcPrintProbeCommit(const usbh_uvc_ctrl_vs_probecommit_data_t *pc) {
+
+	//uinfof("UVC: probe/commit data:");
+	uinfof("\tbmHint=%04x", pc->bmHint);
+	uinfof("\tbFormatIndex=%d, bFrameIndex=%d, dwFrameInterval=%u",
+			pc->bFormatIndex, pc->bFrameIndex, pc->dwFrameInterval);
+	uinfof("\twKeyFrameRate=%d, wPFrameRate=%d, wCompQuality=%u, wCompWindowSize=%u",
+			pc->wKeyFrameRate, pc->wPFrameRate, pc->wCompQuality, pc->wCompWindowSize);
+	uinfof("\twDelay=%d", pc->wDelay);
+	uinfof("\tdwMaxVideoFrameSize=%u", pc->dwMaxVideoFrameSize);
+	uinfof("\tdwMaxPayloadTransferSize=%u", pc->dwMaxPayloadTransferSize);
+/*	uinfof("\tdwClockFrequency=%u", pc->dwClockFrequency);
+	uinfof("\tbmFramingInfo=%02x", pc->bmFramingInfo);
+	uinfof("\tbPreferedVersion=%d, bMinVersion=%d, bMaxVersion=%d",
+			pc->bPreferedVersion, pc->bMinVersion, pc->bMaxVersion); */
+}
+#endif
+
+static void _post(USBHUVCDriver *uvcdp, usbh_urb_t *urb, memory_pool_t *mp, uint16_t type) {
+	usbhuvc_message_base_t *const msg = (usbhuvc_message_base_t *)((uint8_t *)urb->buff - offsetof(usbhuvc_message_data_t, data));
+	msg->timestamp = osalOsGetSystemTimeX();
+
+	usbhuvc_message_base_t *const new_msg = (usbhuvc_message_base_t *)chPoolAllocI(mp);
+	if (new_msg != NULL) {
+		/* allocated the new buffer, now try to post the message to the mailbox */
+		if (chMBPostI(&uvcdp->mb, (msg_t)msg) == MSG_OK) {
+			/* everything OK, complete the missing fields */
+			msg->type = type;
+			msg->length = urb->actualLength;
+
+			/* change the URB's buffer to the newly allocated one */
+			urb->buff = ((usbhuvc_message_data_t *)new_msg)->data;
+		} else {
+			/* couldn't post the message, free the newly allocated buffer */
+			uerr("UVC: error, mailbox overrun");
+			chPoolFreeI(&uvcdp->mp_status, new_msg);
+		}
+	} else {
+		uerrf("UVC: error, %s pool overrun", mp == &uvcdp->mp_data ? "data" : "status");
+	}
+}
+
+static void _cb_int(usbh_urb_t *urb) {
+	USBHUVCDriver *uvcdp = (USBHUVCDriver *)urb->userData;
+
+	switch (urb->status) {
+	case USBH_URBSTATUS_OK:
+		if (urb->actualLength >= 2) {
+			_post(uvcdp, urb, &uvcdp->mp_status, USBHUVC_MESSAGETYPE_STATUS);
+		} else {
+			uerrf("UVC: INT IN, actualLength=%d", urb->actualLength);
+		}
+		break;
+	case USBH_URBSTATUS_TIMEOUT:	/* the device NAKed */
+		udbg("UVC: INT IN no info");
+		break;
+	case USBH_URBSTATUS_DISCONNECTED:
+	case USBH_URBSTATUS_CANCELLED:
+		uwarn("UVC: INT IN status = DISCONNECTED/CANCELLED, aborting");
+		return;
+	default:
+		uerrf("UVC: INT IN error, unexpected status = %d", urb->status);
+		break;
+	}
+
+	usbhURBObjectResetI(urb);
+	usbhURBSubmitI(urb);
+}
+
+static void _cb_iso(usbh_urb_t *urb) {
+	USBHUVCDriver *uvcdp = (USBHUVCDriver *)urb->userData;
+
+	if ((urb->status == USBH_URBSTATUS_DISCONNECTED)
+			|| (urb->status == USBH_URBSTATUS_CANCELLED)) {
+		uwarn("UVC: ISO IN status = DISCONNECTED/CANCELLED, aborting");
+		return;
+	}
+
+	if (urb->status != USBH_URBSTATUS_OK) {
+		uerrf("UVC: ISO IN error, unexpected status = %d", urb->status);
+	} else if (urb->actualLength >= 2) {
+		const uint8_t *const buff = (const uint8_t *)urb->buff;
+		if (buff[0] < 2) {
+			uerrf("UVC: ISO IN, bHeaderLength=%d", buff[0]);
+		} else if (buff[0] > urb->actualLength) {
+			uerrf("UVC: ISO IN, bHeaderLength=%d > actualLength=%d", buff[0], urb->actualLength);
+		} else {
+			udbgf("UVC: ISO IN len=%d, hdr=%d, FID=%d, EOF=%d, ERR=%d, EOH=%d",
+						urb->actualLength,
+						buff[0],
+						buff[1] & UVC_HDR_FID,
+						buff[1] & UVC_HDR_EOF,
+						buff[1] & UVC_HDR_ERR,
+						buff[1] & UVC_HDR_EOH);
+
+			if ((urb->actualLength > buff[0])
+					|| (buff[1] & (UVC_HDR_EOF | UVC_HDR_ERR))) {
+				_post(uvcdp, urb, &uvcdp->mp_data, USBHUVC_MESSAGETYPE_DATA);
+			} else {
+				udbgf("UVC: ISO IN skip: len=%d, hdr=%d, FID=%d, EOF=%d, ERR=%d, EOH=%d",
+						urb->actualLength,
+						buff[0],
+						buff[1] & UVC_HDR_FID,
+						buff[1] & UVC_HDR_EOF,
+						buff[1] & UVC_HDR_ERR,
+						buff[1] & UVC_HDR_EOH);
+			}
+		}
+	} else if (urb->actualLength > 0) {
+		uerrf("UVC: ISO IN, actualLength=%d", urb->actualLength);
+	}
+
+	usbhURBObjectResetI(urb);
+	usbhURBSubmitI(urb);
+}
+
+
+bool usbhuvcStreamStart(USBHUVCDriver *uvcdp, uint16_t min_ep_sz) {
+	bool ret = HAL_FAILED;
+
+	osalSysLock();
+	osalDbgCheck(uvcdp && (uvcdp->state != USBHUVC_STATE_UNINITIALIZED) &&
+					(uvcdp->state != USBHUVC_STATE_BUSY));
+	if (uvcdp->state == USBHUVC_STATE_STREAMING) {
+		osalSysUnlock();
+		return HAL_SUCCESS;
+	}
+	if (uvcdp->state != USBHUVC_STATE_READY) {
+		osalSysUnlock();
+		return HAL_FAILED;
+	}
+	uvcdp->state = USBHUVC_STATE_BUSY;
+	osalSysUnlock();
+
+	uint32_t workramsz;
+	const uint8_t *elem;
+	uint32_t datapackets;
+	uint32_t data_sz;
+
+	//set the alternate setting
+	if (_set_vs_alternate(uvcdp, min_ep_sz) != HAL_SUCCESS)
+		goto exit;
+
+	//reserve working RAM
+	data_sz = (uvcdp->ep_iso.wMaxPacketSize + sizeof(usbhuvc_message_data_t) + 3) & ~3;
+	datapackets = HAL_USBHUVC_WORK_RAM_SIZE / data_sz;
+	if (datapackets == 0) {
+		uerr("Not enough work RAM");
+		goto failed;
+	}
+
+	workramsz = datapackets * data_sz;
+	uinfof("Reserving %u bytes of RAM (%d data packets of %d bytes)", workramsz, datapackets, data_sz);
+	if (datapackets > (HAL_USBHUVC_MAX_MAILBOX_SZ - HAL_USBHUVC_STATUS_PACKETS_COUNT)) {
+		uwarn("Mailbox may overflow, use a larger HAL_USBHUVC_MAX_MAILBOX_SZ. UVC will under-utilize the assigned work RAM.");
+	}
+	chMBResumeX(&uvcdp->mb);
+
+	uvcdp->mp_data_buffer = chHeapAlloc(NULL, workramsz);
+	if (uvcdp->mp_data_buffer == NULL) {
+		uerr("Couldn't reserve RAM");
+		goto failed;
+	}
+
+	//initialize the mempool
+	chPoolObjectInit(&uvcdp->mp_data, data_sz, NULL);
+	elem = (const uint8_t *)uvcdp->mp_data_buffer;
+	while (datapackets--) {
+		chPoolFree(&uvcdp->mp_data, (void *)elem);
+		elem += data_sz;
+	}
+
+	//open the endpoint
+	usbhEPOpen(&uvcdp->ep_iso);
+
+	//allocate 1 buffer and submit the first transfer
+	{
+		usbhuvc_message_data_t *const msg = (usbhuvc_message_data_t *)chPoolAlloc(&uvcdp->mp_data);
+		osalDbgCheck(msg);
+		usbhURBObjectInit(&uvcdp->urb_iso, &uvcdp->ep_iso, _cb_iso, uvcdp, msg->data, uvcdp->ep_iso.wMaxPacketSize);
+	}
+
+	usbhURBSubmit(&uvcdp->urb_iso);
+
+	ret = HAL_SUCCESS;
+	goto exit;
+
+failed:
+	_set_vs_alternate(uvcdp, 0);
+	if (uvcdp->mp_data_buffer)
+		chHeapFree(uvcdp->mp_data_buffer);
+
+exit:
+	osalSysLock();
+	if (ret == HAL_SUCCESS)
+		uvcdp->state = USBHUVC_STATE_STREAMING;
+	else
+		uvcdp->state = USBHUVC_STATE_READY;
+	osalSysUnlock();
+	return ret;
+}
+
+bool usbhuvcStreamStop(USBHUVCDriver *uvcdp) {
+	osalSysLock();
+	osalDbgCheck(uvcdp && (uvcdp->state != USBHUVC_STATE_UNINITIALIZED) &&
+					(uvcdp->state != USBHUVC_STATE_BUSY));
+	if (uvcdp->state != USBHUVC_STATE_STREAMING) {
+		osalSysUnlock();
+		return HAL_SUCCESS;
+	}
+	uvcdp->state = USBHUVC_STATE_BUSY;
 
-static usbh_baseclassdriver_t *uvc_load(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem) {
-	(void)dev;
-	(void)descriptor;
-	(void)rem;
+	//close the ISO endpoint
+	usbhEPCloseS(&uvcdp->ep_iso);
+
+	//purge the mailbox
+	chMBResetI(&uvcdp->mb);		//TODO: the status messages are lost!!
+	chMtxLockS(&uvcdp->mtx);
+	osalSysUnlock();
+
+	//free the working memory
+	chHeapFree(uvcdp->mp_data_buffer);
+	uvcdp->mp_data_buffer = 0;
+
+	//set alternate setting to 0
+	_set_vs_alternate(uvcdp, 0);
+
+	osalSysLock();
+	uvcdp->state = USBHUVC_STATE_READY;
+	chMtxUnlockS(&uvcdp->mtx);
+	osalSysUnlock();
+	return HAL_SUCCESS;
+}
+
+bool usbhuvcFindVSDescriptor(USBHUVCDriver *uvcdp,
+		generic_iterator_t *ics,
+		uint8_t bDescriptorSubtype,
+		bool start) {
+
+	if (start)
+		cs_iter_init(ics, (generic_iterator_t *)&uvcdp->ivs);
+	else
+		cs_iter_next(ics);
+
+	for (; ics->valid; cs_iter_next(ics)) {
+		if (ics->curr[1] != UVC_CS_INTERFACE)
+			break;
+		if (ics->curr[2] == bDescriptorSubtype)
+			return HAL_SUCCESS;
+		if (!start)
+			break;
+	}
+	return HAL_FAILED;
+}
+
+void usbhuvcResetPC(USBHUVCDriver *uvcdp) {
+	memset(&uvcdp->pc, 0, sizeof(uvcdp->pc));
+}
+
+bool usbhuvcProbe(USBHUVCDriver *uvcdp) {
+//	memset(&uvcdp->pc_min, 0, sizeof(uvcdp->pc_min));
+//	memset(&uvcdp->pc_max, 0, sizeof(uvcdp->pc_max));
+
+	if (usbhuvcVSRequest(uvcdp, UVC_SET_CUR, UVC_CTRL_VS_PROBE_CONTROL, sizeof(uvcdp->pc), (uint8_t *)&uvcdp->pc) != HAL_SUCCESS)
+		return HAL_FAILED;
+	if (usbhuvcVSRequest(uvcdp, UVC_GET_CUR, UVC_CTRL_VS_PROBE_CONTROL, sizeof(uvcdp->pc), (uint8_t *)&uvcdp->pc) != HAL_SUCCESS)
+		return HAL_FAILED;
+	if (usbhuvcVSRequest(uvcdp, UVC_GET_MAX, UVC_CTRL_VS_PROBE_CONTROL, sizeof(uvcdp->pc_max), (uint8_t *)&uvcdp->pc_max) != HAL_SUCCESS)
+		return HAL_FAILED;
+	if (usbhuvcVSRequest(uvcdp, UVC_GET_MIN, UVC_CTRL_VS_PROBE_CONTROL, sizeof(uvcdp->pc_min), (uint8_t *)&uvcdp->pc_min) != HAL_SUCCESS)
+		return HAL_FAILED;
+	return HAL_SUCCESS;
+}
+
+bool usbhuvcCommit(USBHUVCDriver *uvcdp) {
+	if (usbhuvcVSRequest(uvcdp, UVC_SET_CUR, UVC_CTRL_VS_COMMIT_CONTROL, sizeof(uvcdp->pc), (uint8_t *)&uvcdp->pc) != HAL_SUCCESS)
+		return HAL_FAILED;
+
+	osalSysLock();
+	if (uvcdp->state == USBHUVC_STATE_ACTIVE)
+		uvcdp->state = USBHUVC_STATE_READY;
+	osalSysUnlock();
+	return HAL_SUCCESS;
+}
+
+uint32_t usbhuvcEstimateRequiredEPSize(USBHUVCDriver *uvcdp, const uint8_t *formatdesc,
+		const uint8_t *framedesc, uint32_t dwFrameInterval) {
+
+	osalDbgCheck(framedesc);
+	osalDbgCheck(framedesc[0] > 3);
+	osalDbgCheck(framedesc[1] == UVC_CS_INTERFACE);
+	osalDbgCheck(formatdesc);
+	osalDbgCheck(formatdesc[0] > 3);
+	osalDbgCheck(formatdesc[1] == UVC_CS_INTERFACE);
+
+	uint16_t w, h, div, mul;
+	uint8_t bpp;
+
+	switch (framedesc[2]) {
+	case UVC_VS_FRAME_MJPEG: {
+		const usbh_uvc_frame_mjpeg_t *frame = (const usbh_uvc_frame_mjpeg_t *)framedesc;
+		//const usbh_uvc_format_mjpeg_t *fmt = (const usbh_uvc_format_mjpeg_t *)formatdesc;
+		w = frame->wWidth;
+		h = frame->wHeight;
+		bpp = 16;	//TODO: check this!!
+		mul = 1;
+		div = 5;	//TODO: check this estimate
+	}	break;
+	case UVC_VS_FRAME_UNCOMPRESSED: {
+		const usbh_uvc_frame_uncompressed_t *frame = (const usbh_uvc_frame_uncompressed_t *)framedesc;
+		const usbh_uvc_format_uncompressed *fmt = (const usbh_uvc_format_uncompressed *)formatdesc;
+		w = frame->wWidth;
+		h = frame->wHeight;
+		bpp = fmt->bBitsPerPixel;
+		mul = div = 1;
+	}	break;
+	default:
+		uwarn("Unsupported format");
+		return 0xffffffff;
+	}
+
+	uint32_t sz = w * h / 8 * bpp;
+	sz *= 10000000UL / dwFrameInterval;
+	sz /= 1000;
+
+	if (uvcdp->dev->speed == USBH_DEVSPEED_HIGH)
+		div *= 8;
+
+	return (sz * mul) / div + 12;
+}
+
+static usbh_baseclassdriver_t *_uvc_load(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem) {
+
+	USBHUVCDriver *uvcdp;
+	uint8_t i;
+
+	if (_usbh_match_descriptor(descriptor, rem, USBH_DT_INTERFACE_ASSOCIATION,
+			0x0e, 0x03, 0x00) != HAL_SUCCESS)
+		return NULL;
+
+	/* alloc driver */
+	for (i = 0; i < HAL_USBHUVC_MAX_INSTANCES; i++) {
+		if (USBHUVCD[i].dev == NULL) {
+			uvcdp = &USBHUVCD[i];
+			goto alloc_ok;
+		}
+	}
+
+	uwarn("Can't alloc UVC driver");
+
+	/* can't alloc */
 	return NULL;
+
+alloc_ok:
+	/* initialize the driver's variables */
+	uvcdp->ivc.curr = uvcdp->ivs.curr = NULL;
+
+	usbhEPSetName(&dev->ctrl, "UVC[CTRL]");
+
+	const usbh_ia_descriptor_t *iad = (const usbh_ia_descriptor_t *)descriptor;
+	if_iterator_t iif;
+	generic_iterator_t ics;
+	generic_iterator_t iep;
+
+	iif.iad = iad;
+	iif.curr = descriptor;
+	iif.rem = rem;
+
+	for (if_iter_next(&iif); iif.valid; if_iter_next(&iif)) {
+		if (iif.iad != iad) break;
+
+		const usbh_interface_descriptor_t *const ifdesc = if_get(&iif);
+		if (ifdesc->bInterfaceClass != UVC_CC_VIDEO) {
+			uwarnf("Skipping Interface %d (class != UVC_CC_VIDEO)",
+					ifdesc->bInterfaceNumber);
+			continue;
+		}
+
+		uinfof("Interface %d, Alt=%d, Class=UVC_CC_VIDEO, Subclass=%02x",
+				ifdesc->bInterfaceNumber,
+				ifdesc->bAlternateSetting,
+				ifdesc->bInterfaceSubClass);
+
+		switch (ifdesc->bInterfaceSubClass) {
+		case UVC_SC_VIDEOCONTROL:
+			if (uvcdp->ivc.curr == NULL) {
+				uvcdp->ivc = iif;
+			}
+			for (cs_iter_init(&ics, (generic_iterator_t *)&iif); ics.valid; cs_iter_next(&ics)) {
+				if (ics.curr[1] != UVC_CS_INTERFACE) {
+					uwarnf("Unknown descriptor=%02X", ics.curr[1]);
+					continue;
+				}
+				switch (ics.curr[2]) {
+				case UVC_VC_HEADER:
+					uinfo("  VC_HEADER"); break;
+				case UVC_VC_INPUT_TERMINAL:
+					uinfof("    VC_INPUT_TERMINAL, ID=%d", ics.curr[3]); break;
+				case UVC_VC_OUTPUT_TERMINAL:
+					uinfof("    VC_OUTPUT_TERMINAL, ID=%d", ics.curr[3]); break;
+				case UVC_VC_SELECTOR_UNIT:
+					uinfof("    VC_SELECTOR_UNIT, ID=%d", ics.curr[3]); break;
+				case UVC_VC_PROCESSING_UNIT:
+					uinfof("    VC_PROCESSING_UNIT, ID=%d", ics.curr[3]); break;
+				case UVC_VC_EXTENSION_UNIT:
+					uinfof("    VC_EXTENSION_UNIT, ID=%d", ics.curr[3]); break;
+				default:
+					uwarnf("Unknown video bDescriptorSubtype=%02x", ics.curr[2]);
+					break;
+				}
+			}
+			break;
+		case UVC_SC_VIDEOSTREAMING:
+			if (uvcdp->ivs.curr == NULL) {
+				uvcdp->ivs = iif;
+			}
+			for (cs_iter_init(&ics, (generic_iterator_t *)&iif); ics.valid; cs_iter_next(&ics)) {
+				if (ics.curr[1] != UVC_CS_INTERFACE) {
+					uwarnf("Unknown descriptor=%02X", ics.curr[1]);
+					continue;
+				}
+				switch (ics.curr[2]) {
+				case UVC_VS_INPUT_HEADER:
+					uinfo("  VS_INPUT_HEADER"); break;
+				case UVC_VS_OUTPUT_HEADER:
+					uinfo("  VS_OUTPUT_HEADER"); break;
+				case UVC_VS_STILL_IMAGE_FRAME:
+					uinfo("    VS_STILL_IMAGE_FRAME"); break;
+
+				case UVC_VS_FORMAT_UNCOMPRESSED:
+					uinfof("    VS_FORMAT_UNCOMPRESSED, bFormatIndex=%d", ics.curr[3]); break;
+				case UVC_VS_FORMAT_MPEG2TS:
+					uinfof("    VS_FORMAT_MPEG2TS, bFormatIndex=%d", ics.curr[3]); break;
+				case UVC_VS_FORMAT_DV:
+					uinfof("    VS_FORMAT_DV, bFormatIndex=%d", ics.curr[3]); break;
+				case UVC_VS_FORMAT_MJPEG:
+					uinfof("    VS_FORMAT_MJPEG, bFormatIndex=%d", ics.curr[3]); break;
+				case UVC_VS_FORMAT_FRAME_BASED:
+					uinfof("    VS_FORMAT_FRAME_BASED, bFormatIndex=%d", ics.curr[3]); break;
+				case UVC_VS_FORMAT_STREAM_BASED:
+					uinfof("    VS_FORMAT_STREAM_BASED, bFormatIndex=%d", ics.curr[3]); break;
+
+				case UVC_VS_FRAME_UNCOMPRESSED:
+					uinfof("      VS_FRAME_UNCOMPRESSED, bFrameIndex=%d", ics.curr[3]); break;
+				case UVC_VS_FRAME_MJPEG:
+					uinfof("      VS_FRAME_MJPEG, bFrameIndex=%d", ics.curr[3]); break;
+				case UVC_VS_FRAME_FRAME_BASED:
+					uinfof("      VS_FRAME_FRAME_BASED, bFrameIndex=%d", ics.curr[3]); break;
+
+				case UVC_VS_COLOR_FORMAT:
+					uinfo("      VS_COLOR_FORMAT"); break;
+				default:
+					uwarnf("Unknown video bDescriptorSubtype=%02x", ics.curr[2]);
+					break;
+				}
+			}
+			break;
+		default:
+			uwarnf("Unknown video bInterfaceSubClass=%02x", ifdesc->bInterfaceSubClass);
+			break;
+		}
+
+		for (ep_iter_init(&iep, &iif); iep.valid; ep_iter_next(&iep)) {
+			const usbh_endpoint_descriptor_t *const epdesc = ep_get(&iep);
+
+			if ((ifdesc->bInterfaceSubClass == UVC_SC_VIDEOCONTROL)
+					&& ((epdesc->bmAttributes & 0x03) == USBH_EPTYPE_INT)
+					&& ((epdesc->bEndpointAddress & 0x80) ==  USBH_EPDIR_IN)) {
+				/* found VC interrupt endpoint */
+				uinfof("  VC Interrupt endpoint; %02x, bInterval=%d",
+						epdesc->bEndpointAddress, epdesc->bInterval);
+				usbhEPObjectInit(&uvcdp->ep_int, dev, epdesc);
+				usbhEPSetName(&uvcdp->ep_int, "UVC[INT ]");
+			} else if ((ifdesc->bInterfaceSubClass == UVC_SC_VIDEOSTREAMING)
+					&& ((epdesc->bmAttributes & 0x03) == USBH_EPTYPE_ISO)
+					&& ((epdesc->bEndpointAddress & 0x80) ==  USBH_EPDIR_IN)) {
+				/* found VS isochronous endpoint */
+				uinfof("  VS Isochronous endpoint; %02x, bInterval=%d, bmAttributes=%02x",
+						epdesc->bEndpointAddress, epdesc->bInterval, epdesc->bmAttributes);
+			} else {
+				/* unknown EP */
+				uwarnf("  <unknown endpoint>, bEndpointAddress=%02x, bmAttributes=%02x",
+									epdesc->bEndpointAddress, epdesc->bmAttributes);
+			}
+
+			for (cs_iter_init(&ics, &iep); ics.valid; cs_iter_next(&ics)) {
+				uinfof("    CS_ENDPOINT bLength=%d, bDescriptorType=%02X",
+						ics.curr[0], ics.curr[1]);
+			}
+		}
+	}
+
+	if ((uvcdp->ivc.curr == NULL) || (uvcdp->ivs.curr == NULL)) {
+		return NULL;
+	}
+
+//	uvcdp->dev = dev;
+
+	_set_vs_alternate(uvcdp, 0);
+
+	/* initialize the INT endpoint */
+	chPoolObjectInit(&uvcdp->mp_status, sizeof(usbhuvc_message_status_t), NULL);
+	for(i = 0; i < HAL_USBHUVC_STATUS_PACKETS_COUNT; i++)
+		chPoolFree(&uvcdp->mp_status, &uvcdp->mp_status_buffer[i]);
+
+	usbhEPOpen(&uvcdp->ep_int);
+
+	usbhuvc_message_status_t *const msg = (usbhuvc_message_status_t *)chPoolAlloc(&uvcdp->mp_status);
+	osalDbgCheck(msg);
+	usbhURBObjectInit(&uvcdp->urb_int, &uvcdp->ep_int, _cb_int, uvcdp, msg->data, USBHUVC_MAX_STATUS_PACKET_SZ);
+	osalSysLock();
+	usbhURBSubmitI(&uvcdp->urb_int);
+	uvcdp->state = USBHUVC_STATE_ACTIVE;
+	osalOsRescheduleS();	/* because of usbhURBSubmitI */
+	osalSysUnlock();
+
+	dev->keepFullCfgDesc++;
+	return (usbh_baseclassdriver_t *)uvcdp;
+}
+
+static void _uvc_unload(usbh_baseclassdriver_t *drv) {
+	USBHUVCDriver *const uvcdp = (USBHUVCDriver *)drv;
+
+	usbhuvcStreamStop(uvcdp);
+
+	usbhEPClose(&uvcdp->ep_int);
+
+	//TODO: free
+
+	if (drv->dev->keepFullCfgDesc)
+		drv->dev->keepFullCfgDesc--;
+
+	osalSysLock();
+	uvcdp->state = USBHUVC_STATE_STOP;
+	osalSysUnlock();
+}
+
+static void _object_init(USBHUVCDriver *uvcdp) {
+	osalDbgCheck(uvcdp != NULL);
+	memset(uvcdp, 0, sizeof(*uvcdp));
+	uvcdp->info = &usbhuvcClassDriverInfo;
+	chMBObjectInit(&uvcdp->mb, uvcdp->mb_buff, HAL_USBHUVC_MAX_MAILBOX_SZ);
+	chMtxObjectInit(&uvcdp->mtx);
+	uvcdp->state = USBHUVC_STATE_STOP;
 }
 
-static void uvc_unload(usbh_baseclassdriver_t *drv) {
-	(void)drv;
+static void _uvc_init(void) {
+	uint8_t i;
+	for (i = 0; i < HAL_USBHUVC_MAX_INSTANCES; i++) {
+		_object_init(&USBHUVCD[i]);
+	}
 }
 
 #endif
diff --git a/os/various/bitmap.h b/os/various/bitmap.h
index d7831aa..115b54c 100644
--- a/os/various/bitmap.h
+++ b/os/various/bitmap.h
@@ -22,8 +22,8 @@
  * @{
  */
 
-#ifndef _BITMAP_H_
-#define _BITMAP_H_
+#ifndef BITMAP_H_
+#define BITMAP_H_
 
 /*===========================================================================*/
 /* Module constants.                                                         */
@@ -72,6 +72,6 @@ extern "C" {
 }
 #endif
 
-#endif /* _BITMAP_H_ */
+#endif /* BITMAP_H_ */
 
 /** @} */
diff --git a/os/various/dbgtrace.h b/os/various/dbgtrace.h
new file mode 100644
index 0000000..b1fc297
--- /dev/null
+++ b/os/various/dbgtrace.h
@@ -0,0 +1,41 @@
+#ifndef DBGTRACE_H_
+#define DBGTRACE_H_
+
+#include "chprintf.h"
+
+#if !defined(DEBUG_TRACE_PRINT)
+#define DEBUG_TRACE_PRINT     FALSE
+#endif
+
+#if !defined(DEBUG_TRACE_WARNING)
+#define DEBUG_TRACE_WARNING   FALSE
+#endif
+
+#if !defined(DEBUG_TRACE_ERROR)
+#define DEBUG_TRACE_ERROR     FALSE
+#endif
+
+/* user must provide correctly initialized pointer to print channel */
+#if DEBUG_TRACE_PRINT || DEBUG_TRACE_WARNING || DEBUG_TRACE_ERROR
+extern BaseSequentialStream   *GlobalDebugChannel;
+#endif
+
+#if DEBUG_TRACE_PRINT
+#define dbgprintf(fmt, ...)  chprintf(GlobalDebugChannel, fmt, ##__VA_ARGS__)
+#else
+#define dbgprintf(fmt, ...)  do {} while(0)
+#endif
+
+#if DEBUG_TRACE_WARNING
+#define warnprintf(fmt, ...)  chprintf(GlobalDebugChannel, fmt, ##__VA_ARGS__)
+#else
+#define warnprintf(fmt, ...)  do {} while(0)
+#endif
+
+#if DEBUG_TRACE_ERROR
+#define errprintf(fmt, ...)  chprintf(GlobalDebugChannel, fmt, ##__VA_ARGS__)
+#else
+#define errprintf(fmt, ...)  do {} while(0)
+#endif
+
+#endif /* DBGTRACE_H_ */
diff --git a/os/various/fatfs_bindings/fatfs.mk b/os/various/fatfs_bindings/fatfs.mk
new file mode 100644
index 0000000..f2feeb5
--- /dev/null
+++ b/os/various/fatfs_bindings/fatfs.mk
@@ -0,0 +1,7 @@
+# FATFS files.
+FATFSSRC = ${CHIBIOS_CONTRIB}/os/various/fatfs_bindings/fatfs_diskio.c \
+           ${CHIBIOS}/os/various/fatfs_bindings/fatfs_syscall.c \
+           ${CHIBIOS}/ext/fatfs/src/ff.c \
+           $(CHIBIOS)/ext/fatfs/src/ffunicode.c
+
+FATFSINC = ${CHIBIOS}/ext/fatfs/src
diff --git a/os/various/fatfs_bindings/fatfs_diskio.c b/os/various/fatfs_bindings/fatfs_diskio.c
new file mode 100644
index 0000000..80d1502
--- /dev/null
+++ b/os/various/fatfs_bindings/fatfs_diskio.c
@@ -0,0 +1,320 @@
+/*-----------------------------------------------------------------------*/
+/* Low level disk I/O module skeleton for FatFs     (C)ChaN, 2007        */
+/*-----------------------------------------------------------------------*/
+/* This is a stub disk I/O module that acts as front end of the existing */
+/* disk I/O modules and attach it to FatFs module with common interface. */
+/*-----------------------------------------------------------------------*/
+
+#include "hal.h"
+#include "ffconf.h"
+#include "diskio.h"
+#include "usbh/dev/msd.h"
+
+#if HAL_USE_MMC_SPI && HAL_USE_SDC
+#error "cannot specify both MMC_SPI and SDC drivers"
+#endif
+
+#if HAL_USE_MMC_SPI
+extern MMCDriver MMCD1;
+#elif HAL_USE_SDC
+extern SDCDriver SDCD1;
+#elif HAL_USBH_USE_MSD
+
+#else
+#error "MMC_SPI, SDC or USBH_MSD driver must be specified"
+#endif
+
+/*-----------------------------------------------------------------------*/
+/* Correspondence between physical drive number and physical drive.      */
+#if HAL_USE_MMC_SPI
+#define MMC         0
+#endif
+
+#if HAL_USE_SDC
+#define SDC         0
+#endif
+
+#if HAL_USBH_USE_MSD
+#if defined(MMC) || defined(SDC)
+#define MSDLUN0     1
+#else
+#define MSDLUN0     0
+#endif
+#endif
+
+/*-----------------------------------------------------------------------*/
+/* Inidialize a Drive                                                    */
+
+DSTATUS disk_initialize (
+    BYTE pdrv                /* Physical drive nmuber (0..) */
+)
+{
+  DSTATUS stat;
+
+  switch (pdrv) {
+#if HAL_USE_MMC_SPI
+  case MMC:
+    stat = 0;
+    /* It is initialized externally, just reads the status.*/
+    if (blkGetDriverState(&MMCD1) != BLK_READY)
+      stat |= STA_NOINIT;
+    if (mmcIsWriteProtected(&MMCD1))
+      stat |=  STA_PROTECT;
+    return stat;
+#elif HAL_USE_SDC
+  case SDC:
+    stat = 0;
+    /* It is initialized externally, just reads the status.*/
+    if (blkGetDriverState(&SDCD1) != BLK_READY)
+      stat |= STA_NOINIT;
+    if (sdcIsWriteProtected(&SDCD1))
+      stat |=  STA_PROTECT;
+    return stat;
+#endif
+#if HAL_USBH_USE_MSD
+  case MSDLUN0:
+	stat = 0;
+	/* It is initialized externally, just reads the status.*/
+	if (blkGetDriverState(&MSBLKD[0]) != BLK_READY)
+	  stat |= STA_NOINIT;
+	return stat;
+#endif
+  }
+  return STA_NOINIT;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Return Disk Status                                                    */
+
+DSTATUS disk_status (
+    BYTE pdrv         /* Physical drive number (0..) */
+)
+{
+  DSTATUS stat;
+
+  switch (pdrv) {
+#if HAL_USE_MMC_SPI
+  case MMC:
+    stat = 0;
+    /* It is initialized externally, just reads the status.*/
+    if (blkGetDriverState(&MMCD1) != BLK_READY)
+      stat |= STA_NOINIT;
+    if (mmcIsWriteProtected(&MMCD1))
+      stat |= STA_PROTECT;
+    return stat;
+#elif HAL_USE_SDC
+  case SDC:
+    stat = 0;
+    /* It is initialized externally, just reads the status.*/
+    if (blkGetDriverState(&SDCD1) != BLK_READY)
+      stat |= STA_NOINIT;
+    if (sdcIsWriteProtected(&SDCD1))
+      stat |= STA_PROTECT;
+    return stat;
+#endif
+#if HAL_USBH_USE_MSD
+  case MSDLUN0:
+    stat = 0;
+    /* It is initialized externally, just reads the status.*/
+    if (blkGetDriverState(&MSBLKD[0]) != BLK_READY)
+      stat |= STA_NOINIT;
+    return stat;
+#endif
+  }
+  return STA_NOINIT;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Sector(s)                                                        */
+
+DRESULT disk_read (
+    BYTE pdrv,        /* Physical drive number (0..) */
+    BYTE *buff,       /* Data buffer to store read data */
+    DWORD sector,     /* Sector address (LBA) */
+    UINT count        /* Number of sectors to read (1..255) */
+)
+{
+  switch (pdrv) {
+#if HAL_USE_MMC_SPI
+  case MMC:
+    if (blkGetDriverState(&MMCD1) != BLK_READY)
+      return RES_NOTRDY;
+    if (mmcStartSequentialRead(&MMCD1, sector))
+      return RES_ERROR;
+    while (count > 0) {
+      if (mmcSequentialRead(&MMCD1, buff))
+        return RES_ERROR;
+      buff += MMCSD_BLOCK_SIZE;
+      count--;
+    }
+    if (mmcStopSequentialRead(&MMCD1))
+        return RES_ERROR;
+    return RES_OK;
+#elif HAL_USE_SDC
+  case SDC:
+    if (blkGetDriverState(&SDCD1) != BLK_READY)
+      return RES_NOTRDY;
+    if (sdcRead(&SDCD1, sector, buff, count))
+      return RES_ERROR;
+    return RES_OK;
+#endif
+#if HAL_USBH_USE_MSD
+  case MSDLUN0:
+	/* It is initialized externally, just reads the status.*/
+	if (blkGetDriverState(&MSBLKD[0]) != BLK_READY)
+		return RES_NOTRDY;
+	if (usbhmsdLUNRead(&MSBLKD[0], sector, buff, count))
+		return RES_ERROR;
+	return RES_OK;
+#endif
+  }
+  return RES_PARERR;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Write Sector(s)                                                       */
+
+DRESULT disk_write (
+    BYTE pdrv,        /* Physical drive number (0..) */
+    const BYTE *buff, /* Data to be written */
+    DWORD sector,     /* Sector address (LBA) */
+    UINT count        /* Number of sectors to write (1..255) */
+)
+{
+  switch (pdrv) {
+#if HAL_USE_MMC_SPI
+  case MMC:
+    if (blkGetDriverState(&MMCD1) != BLK_READY)
+        return RES_NOTRDY;
+    if (mmcIsWriteProtected(&MMCD1))
+        return RES_WRPRT;
+    if (mmcStartSequentialWrite(&MMCD1, sector))
+        return RES_ERROR;
+    while (count > 0) {
+        if (mmcSequentialWrite(&MMCD1, buff))
+            return RES_ERROR;
+        buff += MMCSD_BLOCK_SIZE;
+        count--;
+    }
+    if (mmcStopSequentialWrite(&MMCD1))
+        return RES_ERROR;
+    return RES_OK;
+#elif HAL_USE_SDC
+  case SDC:
+    if (blkGetDriverState(&SDCD1) != BLK_READY)
+      return RES_NOTRDY;
+    if (sdcWrite(&SDCD1, sector, buff, count))
+      return RES_ERROR;
+    return RES_OK;
+#endif
+#if HAL_USBH_USE_MSD
+  case MSDLUN0:
+	/* It is initialized externally, just reads the status.*/
+	if (blkGetDriverState(&MSBLKD[0]) != BLK_READY)
+		return RES_NOTRDY;
+	if (usbhmsdLUNWrite(&MSBLKD[0], sector, buff, count))
+		return RES_ERROR;
+	return RES_OK;
+#endif
+  }
+  return RES_PARERR;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Miscellaneous Functions                                               */
+
+DRESULT disk_ioctl (
+    BYTE pdrv,        /* Physical drive number (0..) */
+    BYTE cmd,         /* Control code */
+    void *buff        /* Buffer to send/receive control data */
+)
+{
+  switch (pdrv) {
+#if HAL_USE_MMC_SPI
+  case MMC:
+    switch (cmd) {
+    case CTRL_SYNC:
+        return RES_OK;
+#if _MAX_SS > _MIN_SS
+    case GET_SECTOR_SIZE:
+        *((WORD *)buff) = MMCSD_BLOCK_SIZE;
+        return RES_OK;
+#endif
+#if _USE_TRIM
+    case CTRL_TRIM:
+        mmcErase(&MMCD1, *((DWORD *)buff), *((DWORD *)buff + 1));
+        return RES_OK;
+#endif
+    default:
+        return RES_PARERR;
+    }
+#elif HAL_USE_SDC
+  case SDC:
+    switch (cmd) {
+    case CTRL_SYNC:
+        return RES_OK;
+    case GET_SECTOR_COUNT:
+        *((DWORD *)buff) = mmcsdGetCardCapacity(&SDCD1);
+        return RES_OK;
+#if _MAX_SS > _MIN_SS
+    case GET_SECTOR_SIZE:
+        *((WORD *)buff) = MMCSD_BLOCK_SIZE;
+        return RES_OK;
+#endif
+    case GET_BLOCK_SIZE:
+        *((DWORD *)buff) = 256; /* 512b blocks in one erase block */
+        return RES_OK;
+#if _USE_TRIM
+    case CTRL_TRIM:
+        sdcErase(&SDCD1, *((DWORD *)buff), *((DWORD *)buff + 1));
+        return RES_OK;
+#endif
+    default:
+        return RES_PARERR;
+    }
+#endif
+#if HAL_USBH_USE_MSD
+    case MSDLUN0:
+      switch (cmd) {
+      case CTRL_SYNC:
+          return RES_OK;
+      case GET_SECTOR_COUNT:
+          *((DWORD *)buff) = MSBLKD[0].info.blk_num;
+          return RES_OK;
+#if _MAX_SS > _MIN_SS
+      case GET_SECTOR_SIZE:
+          *((WORD *)buff) = MSBLKD[0].info.blk_size;
+          return RES_OK;
+#endif
+#if _USE_TRIM
+#error "unimplemented yet!"
+//    case CTRL_TRIM:
+//      ....
+//      return RES_OK;
+#endif
+      default:
+          return RES_PARERR;
+      }
+#endif
+  }
+  return RES_PARERR;
+}
+
+DWORD get_fattime(void) {
+#if HAL_USE_RTC
+    RTCDateTime timespec;
+
+    rtcGetTime(&RTCD1, &timespec);
+    return rtcConvertDateTimeToFAT(&timespec);
+#else
+    return ((uint32_t)0 | (1 << 16)) | (1 << 21); /* wrong but valid time */
+#endif
+}
diff --git a/os/various/jlink.mk b/os/various/jlink.mk
index 1a13bd3..00fedb3 100644
--- a/os/various/jlink.mk
+++ b/os/various/jlink.mk
@@ -27,6 +27,10 @@ jlink-reset:
 	printf "r\nexit\n" > $(BUILDDIR)/reset.jlink
 	$(JLINK) $(JLINK_COMMON_OPTS) $(BUILDDIR)/reset.jlink
 
+jlink-pin-reset: 
+	printf "$(JLINK_PIN_RESET)\nexit\n" > $(BUILDDIR)/pin-reset.jlink
+	$(JLINK) $(JLINK_COMMON_OPTS) $(BUILDDIR)/pin-reset.jlink
+
 jlink-debug-server:
 	$(JLINK_GDB_SERVER) $(JLINK_COMMON_OPTS) -port $(JLINK_GDB_PORT)
 
diff --git a/os/various/lib_scsi.c b/os/various/lib_scsi.c
new file mode 100644
index 0000000..720a90f
--- /dev/null
+++ b/os/various/lib_scsi.c
@@ -0,0 +1,548 @@
+/*
+    ChibiOS/HAL - Copyright (C) 2016 Uladzimir Pylinsky aka barthess
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    lib_scsi.c
+ * @brief   SCSI target driver source code.
+ *
+ * @addtogroup SCSI
+ * @{
+ */
+
+#include <string.h>
+
+#include "hal.h"
+
+#include "lib_scsi.h"
+
+#define DEBUG_TRACE_PRINT     FALSE
+#define DEBUG_TRACE_WARNING   FALSE
+#define DEBUG_TRACE_ERROR     FALSE
+#include "dbgtrace.h"
+
+#define ARCH_LITTLE_ENDIAN
+#include "bswap.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+typedef struct {
+  uint32_t first_lba;
+  uint16_t blk_cnt;
+} data_request_t;
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Combines data request from byte array.
+ *
+ * @notapi
+ */
+static data_request_t decode_data_request(const uint8_t *cmd) {
+
+  data_request_t req;
+  uint32_t lba;
+  uint16_t blk;
+
+  memcpy(&lba, &cmd[2], sizeof(lba));
+  memcpy(&blk, &cmd[7], sizeof(blk));
+
+  req.first_lba = be32_to_cpu(lba);
+  req.blk_cnt = be16_to_cpu(blk);
+
+  return req;
+}
+
+/**
+ * @brief   Fills sense structure.
+ *
+ * @param[in] scsip   pointer to @p SCSITarget structure
+ * @param[in] key     SCSI sense key
+ * @param[in] code    SCSI sense code
+ * @param[in] qual    SCSI sense qualifier
+ *
+ * @notapi
+ */
+static void set_sense(SCSITarget *scsip, uint8_t key,
+                      uint8_t code, uint8_t qual) {
+
+  scsi_sense_response_t *sense = &scsip->sense;
+  memset(sense, 0 , sizeof(scsi_sense_response_t));
+
+  sense->byte[0]  = 0x70;
+  sense->byte[2]  = key;
+  sense->byte[7]  = 8;
+  sense->byte[12] = code;
+  sense->byte[13] = qual;
+}
+
+/**
+ * @brief   Sets all values in sense data to 'success' condition.
+ *
+ * @param[in] scsip   pointer to @p SCSITarget structure
+ *
+ * @notapi
+ */
+static void set_sense_ok(SCSITarget *scsip) {
+  set_sense(scsip, SCSI_SENSE_KEY_GOOD,
+                   SCSI_ASENSE_NO_ADDITIONAL_INFORMATION,
+                   SCSI_ASENSEQ_NO_QUALIFIER);
+}
+
+/**
+ * @brief   Transmits data via transport channel.
+ *
+ * @param[in] scsip   pointer to @p SCSITarget structure
+ * @param[in] data    pointer to data buffer
+ * @param[in] len     number of bytes to be transmitted
+ *
+ * @return            The operation status.
+ *
+ * @notapi
+ */
+static bool transmit_data(SCSITarget *scsip, const uint8_t *data, uint32_t len) {
+
+  const SCSITransport *trp = scsip->config->transport;
+  const uint32_t residue = len - trp->transmit(trp, data, len);
+
+  if (residue > 0) {
+    scsip->residue = residue;
+    return SCSI_FAILED;
+  }
+  else {
+    return SCSI_SUCCESS;
+  }
+}
+
+/**
+ * @brief   Stub for unhandled SCSI commands.
+ * @details Sets error flags in sense data structure and returns error error.
+ */
+static bool cmd_unhandled(SCSITarget *scsip, const uint8_t *cmd) {
+  (void)cmd;
+
+  set_sense(scsip, SCSI_SENSE_KEY_ILLEGAL_REQUEST,
+                   SCSI_ASENSE_INVALID_COMMAND,
+                   SCSI_ASENSEQ_NO_QUALIFIER);
+  return SCSI_FAILED;
+}
+
+/**
+ * @brief   Stub for unrealized but required SCSI commands.
+ * @details Sets sense data in 'all OK' condition and returns success status.
+ */
+static bool cmd_ignored(SCSITarget *scsip, const uint8_t *cmd) {
+  (void)scsip;
+  (void)cmd;
+
+  return SCSI_SUCCESS;
+}
+
+/**
+ * @brief   SCSI inquiry command handler.
+ *
+ * @param[in] scsip   pointer to @p SCSITarget structure
+ * @param[in] cmd     pointer to SCSI command data
+ *
+ * @return            The operation status.
+ *
+ * @notapi
+ */
+static bool inquiry(SCSITarget *scsip, const uint8_t *cmd) {
+
+  if ((cmd[1] & 0b1) && cmd[2] == 0x80) {
+    /* Unit serial number page */
+    return transmit_data(scsip, (const uint8_t *)scsip->config->unit_serial_number_inquiry_response,
+                                sizeof(scsi_unit_serial_number_inquiry_response_t));
+  }
+  else if ((cmd[1] & 0b11) || cmd[2] != 0) {
+    set_sense(scsip, SCSI_SENSE_KEY_ILLEGAL_REQUEST,
+                     SCSI_ASENSE_INVALID_FIELD_IN_CDB,
+                     SCSI_ASENSEQ_NO_QUALIFIER);
+    return SCSI_FAILED;
+  }
+  else {
+    return transmit_data(scsip, (const uint8_t *)scsip->config->inquiry_response,
+                                sizeof(scsi_inquiry_response_t));
+  }
+}
+
+/**
+ * @brief   SCSI request sense command handler.
+ *
+ * @param[in] scsip   pointer to @p SCSITarget structure
+ * @param[in] cmd     pointer to SCSI command data
+ *
+ * @return            The operation status.
+ *
+ * @notapi
+ */
+static bool request_sense(SCSITarget *scsip, const uint8_t *cmd) {
+
+  if (((cmd[1] & 0x01) != 0) || (cmd[4] != sizeof(scsi_sense_response_t))) {
+    set_sense(scsip, SCSI_SENSE_KEY_ILLEGAL_REQUEST,
+                     SCSI_ASENSE_INVALID_FIELD_IN_CDB,
+                     SCSI_ASENSEQ_NO_QUALIFIER);
+    return SCSI_FAILED;
+  }
+  else {
+    return transmit_data(scsip, (uint8_t *)&scsip->sense,
+                                 sizeof(scsi_sense_response_t));
+  }
+}
+
+/**
+ * @brief   SCSI mode sense (6) command handler.
+ *
+ * @param[in] scsip   pointer to @p SCSITarget structure
+ * @param[in] cmd     pointer to SCSI command data
+ *
+ * @return            The operation status.
+ *
+ * @notapi
+ */
+static bool mode_sense6(SCSITarget *scsip, const uint8_t *cmd) {
+  (void)cmd;
+
+  scsip->mode_sense.byte[0] = sizeof(scsi_mode_sense6_response_t) - 1;
+  scsip->mode_sense.byte[1] = 0;
+  if (blkIsWriteProtected(scsip->config->blkdev)) {
+    scsip->mode_sense.byte[2] = 0x01 << 7;
+  }
+  else {
+    scsip->mode_sense.byte[2] = 0;
+  }
+  scsip->mode_sense.byte[3] = 0;
+
+  return transmit_data(scsip, (uint8_t *)&scsip->mode_sense,
+                              sizeof(scsi_mode_sense6_response_t));
+}
+
+/**
+ * @brief   SCSI read format capacities command handler.
+ *
+ * @param[in] scsip   pointer to @p SCSITarget structure
+ * @param[in] cmd     pointer to SCSI command data
+ *
+ * @return            The operation status.
+ *
+ * @notapi
+ */
+static bool read_format_capacities(SCSITarget *scsip, const uint8_t *cmd) {
+
+  /* An Allocation Length of zero indicates that no data shall be transferred.
+     This condition shall not be considered as an error. The Logical Unit
+     shall terminate the data transfer when Allocation Length bytes have
+     been transferred or when all available data have been transferred to
+     the Initiator, whatever is less. */
+
+  uint16_t len = cmd[7] << 8 | cmd[8];
+
+  if (0 == len) {
+    return SCSI_SUCCESS;
+  }
+  else {
+    scsi_read_format_capacities_response_t ret;
+    BlockDeviceInfo bdi;
+    blkGetInfo(scsip->config->blkdev, &bdi);
+
+    uint32_t tmp = cpu_to_be32(bdi.blk_num);
+    memcpy(ret.blocknum, &tmp, 4);
+
+    uint8_t formatted_media = 0b10;
+    uint16_t blocklen = bdi.blk_size;
+    ret.blocklen[0] = formatted_media;
+    ret.blocklen[1] = 0;
+    ret.blocklen[2] = blocklen >> 8;
+    ret.blocklen[3] = blocklen & 0xFF;
+
+    ret.header[3] = 1 * 8;
+
+    return transmit_data(scsip, (uint8_t *)&ret,
+                         sizeof(scsi_read_format_capacities_response_t));
+  }
+}
+
+/**
+ * @brief   SCSI read capacity (10) command handler.
+ *
+ * @param[in] scsip   pointer to @p SCSITarget structure
+ * @param[in] cmd     pointer to SCSI command data
+ *
+ * @return            The operation status.
+ *
+ * @notapi
+ */
+static bool read_capacity10(SCSITarget *scsip, const uint8_t *cmd) {
+
+  (void)cmd;
+
+  BlockDeviceInfo bdi;
+  blkGetInfo(scsip->config->blkdev, &bdi);
+  scsi_read_capacity10_response_t ret;
+  ret.block_size      = cpu_to_be32(bdi.blk_size);
+  ret.last_block_addr = cpu_to_be32(bdi.blk_num - 1);
+
+  return transmit_data(scsip, (uint8_t *)&ret,
+                        sizeof(scsi_read_capacity10_response_t));
+}
+
+/**
+ * @brief   Checks data request for media overflow.
+ *
+ * @param[in] scsip   pointer to @p SCSITarget structure
+ * @param[in] cmd     pointer to SCSI command data
+ *
+ * @return            The operation status.
+ * @retval true       When media overflow detected.
+ * @retval false      Otherwise.
+ *
+ * @notapi
+ */
+static bool data_overflow(SCSITarget *scsip, const data_request_t *req) {
+
+  BlockDeviceInfo bdi;
+  blkGetInfo(scsip->config->blkdev, &bdi);
+
+  if (req->first_lba + req->blk_cnt > bdi.blk_num) {
+    set_sense(scsip, SCSI_SENSE_KEY_ILLEGAL_REQUEST,
+                     SCSI_ASENSE_LBA_OUT_OF_RANGE,
+                     SCSI_ASENSEQ_NO_QUALIFIER);
+    return true;
+  }
+  else {
+    return false;
+  }
+}
+
+/**
+ * @brief   SCSI read/write (10) command handler.
+ *
+ * @param[in] scsip   pointer to @p SCSITarget structure
+ * @param[in] cmd     pointer to SCSI command data
+ *
+ * @return            The operation status.
+ *
+ * @notapi
+ */
+static bool data_read_write10(SCSITarget *scsip, const uint8_t *cmd) {
+
+  data_request_t req = decode_data_request(cmd);
+
+  if (data_overflow(scsip, &req)) {
+    return SCSI_FAILED;
+  }
+  else {
+    const SCSITransport *tr = scsip->config->transport;
+    BaseBlockDevice *blkdev = scsip->config->blkdev;
+    BlockDeviceInfo bdi;
+    blkGetInfo(blkdev, &bdi);
+    size_t bs = bdi.blk_size;
+    uint8_t *buf = scsip->config->blkbuf;
+
+    size_t i = 0;
+    for (i=0; i<req.blk_cnt; i++) {
+      if (cmd[0] == SCSI_CMD_READ_10) {
+        // TODO: block error handling
+        blkRead(blkdev, req.first_lba + i, buf, 1);
+        tr->transmit(tr, buf, bs);
+      }
+      else {
+        // TODO: block error handling
+        tr->receive(tr, buf, bs);
+        blkWrite(blkdev, req.first_lba + i, buf, 1);
+      }
+    }
+  }
+  return SCSI_SUCCESS;
+}
+
+/**
+ * @brief   SCSI test unit ready command handler
+ * @details If block device is inserted, sets sense data in 'all OK' condition
+ *          and returns success status.
+ *          If block device is not inserted, sets sense data to 'Medium not present' considion,
+ *          and returns check condition status.
+ */
+static bool test_unit_ready(SCSITarget *scsip, const uint8_t *cmd) {
+  (void)cmd;
+
+  if (blkIsInserted(scsip->config->blkdev)) {
+    return SCSI_SUCCESS;
+  }
+  else {
+    warnprintf("SCSI Medium is not inserted.\r\n");
+    set_sense(scsip, SCSI_SENSE_KEY_NOT_READY,
+                     SCSI_ASENSE_MEDIUM_NOT_PRESENT,
+                     SCSI_ASENSEQ_NO_QUALIFIER);
+    return SCSI_FAILED;
+  }
+
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Executes SCSI command encoded in byte array.
+ *
+ * @param[in] scsip   pointer to @p SCSITarget structure
+ * @param[in] cmd     pointer to SCSI command data
+ *
+ * @return            The operation status.
+ *
+ * @api
+ */
+bool scsiExecCmd(SCSITarget *scsip, const uint8_t *cmd) {
+
+  bool ret = SCSI_SUCCESS;
+
+  switch (cmd[0]) {
+  case SCSI_CMD_INQUIRY:
+    dbgprintf("SCSI_CMD_INQUIRY\r\n");
+    ret = inquiry(scsip, cmd);
+    break;
+
+  case SCSI_CMD_REQUEST_SENSE:
+    dbgprintf("SCSI_CMD_REQUEST_SENSE\r\n");
+    ret = request_sense(scsip, cmd);
+    break;
+
+  case SCSI_CMD_READ_CAPACITY_10:
+    dbgprintf("SCSI_CMD_READ_CAPACITY_10\r\n");
+    ret = read_capacity10(scsip, cmd);
+    break;
+
+  case SCSI_CMD_READ_10:
+    dbgprintf("SCSI_CMD_READ_10\r\n");
+    ret = data_read_write10(scsip, cmd);
+    break;
+
+  case SCSI_CMD_WRITE_10:
+    dbgprintf("SCSI_CMD_WRITE_10\r\n");
+    ret = data_read_write10(scsip, cmd);
+    break;
+
+  case SCSI_CMD_TEST_UNIT_READY:
+    dbgprintf("SCSI_CMD_TEST_UNIT_READY\r\n");
+    ret = test_unit_ready(scsip, cmd);
+    break;
+
+  case SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL:
+    dbgprintf("SCSI_CMD_ALLOW_MEDIUM_REMOVAL\r\n");
+    ret = cmd_ignored(scsip, cmd);
+    break;
+
+  case SCSI_CMD_MODE_SENSE_6:
+    dbgprintf("SCSI_CMD_MODE_SENSE_6\r\n");
+    ret = mode_sense6(scsip, cmd);
+    break;
+
+  case SCSI_CMD_READ_FORMAT_CAPACITIES:
+    dbgprintf("SCSI_CMD_READ_FORMAT_CAPACITIES\r\n");
+    ret = read_format_capacities(scsip, cmd);
+    break;
+
+  case SCSI_CMD_VERIFY_10:
+    dbgprintf("SCSI_CMD_VERIFY_10\r\n");
+    ret = cmd_ignored(scsip, cmd);
+    break;
+
+  default:
+    warnprintf("SCSI unhandled command: %X\r\n", cmd[0]);
+    ret = cmd_unhandled(scsip, cmd);
+    break;
+  }
+
+  if (ret == SCSI_SUCCESS)
+    set_sense_ok(scsip);
+
+  return ret;
+}
+
+/**
+ * @brief   Driver structure initialization.
+ *
+ * @param[in] scsip   pointer to @p SCSITarget structure
+ *
+ * @api
+ */
+void scsiObjectInit(SCSITarget *scsip) {
+
+  scsip->config = NULL;
+  scsip->residue = 0;
+  memset(&scsip->sense, 0 , sizeof(scsi_sense_response_t));
+  scsip->state = SCSI_TRGT_STOP;
+}
+
+/**
+ * @brief   Starts SCSITarget driver.
+ *
+ * @param[in] scsip   pointer to @p SCSITarget structure
+ * @param[in] config  pointer to @p SCSITargetConfig structure
+ *
+ * @api
+ */
+void scsiStart(SCSITarget *scsip, const SCSITargetConfig *config) {
+
+  scsip->config = config;
+  scsip->state = SCSI_TRGT_READY;
+}
+
+/**
+ * @brief   Stops SCSITarget driver.
+ *
+ * @param[in] scsip   pointer to @p SCSITarget structure
+ *
+ * @api
+ */
+void scsiStop(SCSITarget *scsip) {
+
+  scsip->config = NULL;
+  scsip->state = SCSI_TRGT_STOP;
+}
+
+/**
+ * @brief   Retrieves residue bytes.
+ *
+ * @param[in] scsip   pointer to @p SCSITarget structure
+ *
+ * @return            Residue bytes.
+ *
+ * @api
+ */
+uint32_t scsiResidue(const SCSITarget *scsip) {
+
+  return scsip->residue;
+}
+
+/** @} */
diff --git a/os/various/lib_scsi.h b/os/various/lib_scsi.h
new file mode 100644
index 0000000..8384ae3
--- /dev/null
+++ b/os/various/lib_scsi.h
@@ -0,0 +1,293 @@
+/*
+    ChibiOS/HAL - Copyright (C) 2016 Uladzimir Pylinsky aka barthess
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    wdg_lld.h
+ * @brief   WDG Driver subsystem low level driver header template.
+ *
+ * @addtogroup WDG
+ * @{
+ */
+
+#ifndef LIB_SCSI_H_
+#define LIB_SCSI_H_
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+#define SCSI_CMD_TEST_UNIT_READY                0x00
+#define SCSI_CMD_REQUEST_SENSE                  0x03
+#define SCSI_CMD_INQUIRY                        0x12
+#define SCSI_CMD_MODE_SENSE_6                   0x1A
+#define SCSI_CMD_START_STOP_UNIT                0x1B
+#define SCSI_CMD_SEND_DIAGNOSTIC                0x1D
+#define SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL   0x1E
+#define SCSI_CMD_READ_CAPACITY_10               0x25
+#define SCSI_CMD_READ_FORMAT_CAPACITIES         0x23
+#define SCSI_CMD_READ_10                        0x28
+#define SCSI_CMD_WRITE_10                       0x2A
+#define SCSI_CMD_VERIFY_10                      0x2F
+
+#define SCSI_SENSE_KEY_GOOD                     0x00
+#define SCSI_SENSE_KEY_RECOVERED_ERROR          0x01
+#define SCSI_SENSE_KEY_NOT_READY                0x02
+#define SCSI_SENSE_KEY_MEDIUM_ERROR             0x03
+#define SCSI_SENSE_KEY_HARDWARE_ERROR           0x04
+#define SCSI_SENSE_KEY_ILLEGAL_REQUEST          0x05
+#define SCSI_SENSE_KEY_UNIT_ATTENTION           0x06
+#define SCSI_SENSE_KEY_DATA_PROTECT             0x07
+#define SCSI_SENSE_KEY_BLANK_CHECK              0x08
+#define SCSI_SENSE_KEY_VENDOR_SPECIFIC          0x09
+#define SCSI_SENSE_KEY_COPY_ABORTED             0x0A
+#define SCSI_SENSE_KEY_ABORTED_COMMAND          0x0B
+#define SCSI_SENSE_KEY_VOLUME_OVERFLOW          0x0D
+#define SCSI_SENSE_KEY_MISCOMPARE               0x0E
+
+#define SCSI_ASENSE_NO_ADDITIONAL_INFORMATION   0x00
+#define SCSI_ASENSE_LOGICAL_UNIT_NOT_READY      0x04
+#define SCSI_ASENSE_INVALID_FIELD_IN_CDB        0x24
+#define SCSI_ASENSE_NOT_READY_TO_READY_CHANGE   0x28
+#define SCSI_ASENSE_WRITE_PROTECTED             0x27
+#define SCSI_ASENSE_FORMAT_ERROR                0x31
+#define SCSI_ASENSE_INVALID_COMMAND             0x20
+#define SCSI_ASENSE_LBA_OUT_OF_RANGE            0x21
+#define SCSI_ASENSE_MEDIUM_NOT_PRESENT          0x3A
+
+#define SCSI_ASENSEQ_NO_QUALIFIER               0x00
+#define SCSI_ASENSEQ_FORMAT_COMMAND_FAILED      0x01
+#define SCSI_ASENSEQ_INIT_COMMAND_REQUIRED      0x02
+#define SCSI_ASENSEQ_OPERATION_IN_PROGRESS      0x07
+
+#define SCSI_SUCCESS                            HAL_SUCCESS
+#define SCSI_FAILED                             HAL_FAILED
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of a structure representing an SCSI target.
+ */
+typedef struct SCSITarget     SCSITarget;
+
+/**
+ * @brief   Type of a structure representing an SCSI transport.
+ */
+typedef struct SCSITransport  SCSITransport;
+
+/**
+ * @brief   State of SCSI target.
+ */
+typedef enum {
+  SCSI_TRGT_UNINIT = 0,
+  SCSI_TRGT_STOP,
+  SCSI_TRGT_READY,
+} scsitrgtstate_t;
+
+/**
+ * @brief   Represents SCSI sense data structure.
+ * @details See SCSI specification.
+ */
+typedef struct PACKED_VAR {
+  uint8_t byte[18];
+} scsi_sense_response_t;
+
+/**
+ * @brief   Represents SCSI inquiry response structure.
+ * @details See SCSI specification.
+ */
+typedef struct PACKED_VAR {
+  uint8_t peripheral;
+  uint8_t removable;
+  uint8_t version;
+  uint8_t response_data_format;
+  uint8_t additional_length;
+  uint8_t sccstp;
+  uint8_t bqueetc;
+  uint8_t cmdque;
+  uint8_t vendorID[8];
+  uint8_t productID[16];
+  uint8_t productRev[4];
+} scsi_inquiry_response_t;
+
+/**
+ * @brief   Represents SCSI unit serial number inquiry response structure.
+ * @details See SCSI specification.
+ */
+typedef struct PACKED_VAR {
+  uint8_t peripheral;
+  uint8_t page_code;
+  uint8_t reserved;
+  uint8_t page_length;
+  uint8_t serianNumber[8];
+} scsi_unit_serial_number_inquiry_response_t;
+/**
+ * @brief   Represents SCSI mode sense (6) request structure.
+ * @details See SCSI specification.
+ */
+typedef struct PACKED_VAR {
+  uint8_t   byte[6];
+} scsi_mode_sense6_request_t;
+
+/**
+ * @brief   Represents SCSI mode sense (6) response structure.
+ * @details See SCSI specification.
+ */
+typedef struct PACKED_VAR{
+  uint8_t   byte[4];
+} scsi_mode_sense6_response_t;
+
+/**
+ * @brief   Represents SCSI read capacity (10) response structure.
+ * @details See SCSI specification.
+ */
+typedef struct PACKED_VAR {
+  uint32_t last_block_addr;
+  uint32_t block_size;
+} scsi_read_capacity10_response_t;
+
+/**
+ * @brief   Represents SCSI read format capacity response structure.
+ * @details See SCSI specification.
+ */
+typedef struct PACKED_VAR {
+  uint8_t header[4];
+  uint8_t blocknum[4];
+  uint8_t blocklen[4];
+} scsi_read_format_capacities_response_t;
+
+/**
+ * @brief   Type of a SCSI transport transmit call.
+ *
+ * @param[in] usbp      pointer to the @p SCSITransport object
+ * @param[in] data      pointer to payload buffer
+ * @param[in] len       payload length
+ */
+typedef uint32_t (*scsi_transport_transmit_t)(const SCSITransport *transport,
+                                              const uint8_t *data, size_t len);
+
+/**
+ * @brief   Type of a SCSI transport transmit call.
+ *
+ * @param[in] usbp      pointer to the @p SCSITransport object
+ * @param[out] data     pointer to receive buffer
+ * @param[in] len       number of bytes to be received
+ */
+typedef uint32_t (*scsi_transport_receive_t)(const SCSITransport *transport,
+                                             uint8_t *data, size_t len);
+
+/**
+ * @brief   SCSI transport structure.
+ */
+struct SCSITransport {
+  /**
+   * @brief   Transmit call provided by lower level driver.
+   */
+  scsi_transport_transmit_t     transmit;
+  /**
+   * @brief   Receive call provided by lower level driver.
+   */
+  scsi_transport_receive_t      receive;
+  /**
+   * @brief   Transport handler provided by lower level driver.
+   */
+  void                          *handler;
+};
+
+/**
+ * @brief   SCSI target config structure.
+ */
+typedef struct {
+  /**
+   * @brief   Pointer to @p SCSITransport object.
+   */
+  const SCSITransport           *transport;
+  /**
+   * @brief   Pointer to @p BaseBlockDevice object.
+   */
+  BaseBlockDevice               *blkdev;
+  /**
+   * @brief   Pointer to data buffer for single block.
+   */
+  uint8_t                       *blkbuf;
+  /**
+   * @brief   Pointer to SCSI inquiry response object.
+   */
+  const scsi_inquiry_response_t *inquiry_response;
+  /**
+   * @brief   Pointer to SCSI unit serial number inquiry response object.
+   */
+  const scsi_unit_serial_number_inquiry_response_t *unit_serial_number_inquiry_response;
+} SCSITargetConfig;
+
+/**
+ *
+ */
+struct SCSITarget {
+  /**
+   * @brief   Pointer to @p SCSITargetConfig object.
+   */
+  const SCSITargetConfig        *config;
+  /**
+   * @brief   Target state.
+   */
+  scsitrgtstate_t               state;
+  /**
+   * @brief   SCSI sense response structure.
+   */
+  scsi_sense_response_t         sense;
+  /**
+   * @brief   SCSI mode sense (6) response structure.
+   */
+  scsi_mode_sense6_response_t   mode_sense;
+  /**
+   * @brief   Residue bytes.
+   */
+  uint32_t                      residue;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void scsiObjectInit(SCSITarget *scsip);
+  void scsiStart(SCSITarget *scsip, const SCSITargetConfig *config);
+  void scsiStop(SCSITarget *scsip);
+  bool scsiExecCmd(SCSITarget *scsip, const uint8_t *cmd);
+  uint32_t scsiResidue(const SCSITarget *scsip);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LIB_SCSI_H_ */
+
+/** @} */
diff --git a/os/various/ramdisk.c b/os/various/ramdisk.c
new file mode 100644
index 0000000..23bf658
--- /dev/null
+++ b/os/various/ramdisk.c
@@ -0,0 +1,219 @@
+/*
+    ChibiOS/HAL - Copyright (C) 2016 Uladzimir Pylinsky aka barthess
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    ramdisk.c
+ * @brief   Virtual block devise driver source.
+ *
+ * @addtogroup ramdisk
+ * @{
+ */
+
+#include "hal.h"
+
+#include "ramdisk.h"
+
+#include <string.h>
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*
+ * Interface implementation.
+ */
+static bool overflow(const RamDisk *rd, uint32_t startblk, uint32_t n) {
+  return (startblk + n) > rd->blk_num;
+}
+
+static bool is_inserted(void *instance) {
+  (void)instance;
+  return true;
+}
+
+static bool is_protected(void *instance) {
+  RamDisk *rd = instance;
+  if (BLK_READY == rd->state) {
+    return rd->readonly;
+  }
+  else {
+    return true;
+  }
+}
+
+static bool connect(void *instance) {
+  RamDisk *rd = instance;
+  if (BLK_STOP == rd->state) {
+    rd->state = BLK_READY;
+  }
+  return HAL_SUCCESS;
+}
+
+static bool disconnect(void *instance) {
+  RamDisk *rd = instance;
+  if (BLK_STOP != rd->state) {
+    rd->state = BLK_STOP;
+  }
+  return HAL_SUCCESS;
+}
+
+static bool read(void *instance, uint32_t startblk,
+                 uint8_t *buffer, uint32_t n) {
+
+  RamDisk *rd = instance;
+
+  if (overflow(rd, startblk, n)) {
+    return HAL_FAILED;
+  }
+  else {
+    const uint32_t bs = rd->blk_size;
+    memcpy(buffer, &rd->storage[startblk * bs], n * bs);
+    return HAL_SUCCESS;
+  }
+}
+
+static bool write(void *instance, uint32_t startblk,
+                const uint8_t *buffer, uint32_t n) {
+
+  RamDisk *rd = instance;
+  if (overflow(rd, startblk, n)) {
+    return HAL_FAILED;
+  }
+  else {
+    const uint32_t bs = rd->blk_size;
+    memcpy(&rd->storage[startblk * bs], buffer, n * bs);
+    return HAL_SUCCESS;
+  }
+}
+
+static bool sync(void *instance) {
+
+  RamDisk *rd = instance;
+  if (BLK_READY != rd->state) {
+    return HAL_FAILED;
+  }
+  else {
+    return HAL_SUCCESS;
+  }
+}
+
+static bool get_info(void *instance, BlockDeviceInfo *bdip) {
+
+  RamDisk *rd = instance;
+  if (BLK_READY != rd->state) {
+    return HAL_FAILED;
+  }
+  else {
+    bdip->blk_num = rd->blk_num;
+    bdip->blk_size = rd->blk_size;
+    return HAL_SUCCESS;
+  }
+}
+
+/**
+ *
+ */
+static const struct BaseBlockDeviceVMT vmt = {
+    is_inserted,
+    is_protected,
+    connect,
+    disconnect,
+    read,
+    write,
+    sync,
+    get_info
+};
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   RAM disk object initialization.
+ *
+ * @param[in] rdp   pointer to @p RamDisk object
+ *
+ * @init
+ */
+void ramdiskObjectInit(RamDisk *rdp) {
+
+  rdp->vmt = &vmt;
+  rdp->state = BLK_STOP;
+}
+
+/**
+ * @brief   Starts RAM disk.
+ *
+ * @param[in] rdp       pointer to @p RamDisk object
+ * @param[in] storage   pointer to array representing disk storage
+ * @param[in] blksize   size of blocks in bytes
+ * @param[in] blknum    total number of blocks in device
+ * @param[in] readonly  read only flag
+ *
+ * @api
+ */
+void ramdiskStart(RamDisk *rdp, uint8_t *storage, uint32_t blksize,
+                  uint32_t blknum, bool readonly) {
+
+  osalDbgCheck(rdp != NULL);
+
+  osalSysLock();
+  osalDbgAssert((rdp->state == BLK_STOP) || (rdp->state == BLK_READY),
+                "invalid state");
+  rdp->blk_num  = blknum;
+  rdp->blk_size = blksize;
+  rdp->readonly = readonly;
+  rdp->storage  = storage;
+  rdp->state    = BLK_READY;
+  osalSysUnlock();
+}
+
+/**
+ * @brief   Stops RAM disk.
+ *
+ * @param[in] rdp       pointer to @p RamDisk object
+ *
+ * @api
+ */
+void ramdiskStop(RamDisk *rdp) {
+
+  osalDbgCheck(rdp != NULL);
+
+  osalSysLock();
+  osalDbgAssert((rdp->state == BLK_STOP) || (rdp->state == BLK_READY),
+                "invalid state");
+  rdp->storage = NULL;
+  rdp->state = BLK_STOP;
+  osalSysUnlock();
+}
+
+/** @} */
diff --git a/os/various/ramdisk.h b/os/various/ramdisk.h
new file mode 100644
index 0000000..0860662
--- /dev/null
+++ b/os/various/ramdisk.h
@@ -0,0 +1,86 @@
+/*
+    ChibiOS/HAL - Copyright (C) 2016 Uladzimir Pylinsky aka barthess
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    ramdisk.h
+ * @brief   Virtual block devise driver header.
+ *
+ * @addtogroup ramdisk
+ * @{
+ */
+
+#ifndef RAMDISK_H_
+#define RAMDISK_H_
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+typedef struct RamDisk RamDisk;
+
+/**
+ *
+ */
+#define _ramdisk_device_data                                                \
+  _base_block_device_data                                                   \
+  uint8_t       *storage;                                                   \
+  uint32_t      blk_size;                                                   \
+  uint32_t      blk_num;                                                    \
+  bool          readonly;
+
+/**
+ *
+ */
+struct RamDisk {
+  /** @brief Virtual Methods Table.*/
+  const struct BaseBlockDeviceVMT *vmt;
+  _ramdisk_device_data
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void ramdiskObjectInit(RamDisk *rdp);
+  void ramdiskStart(RamDisk *rdp, uint8_t *storage, uint32_t blksize,
+                    uint32_t blknum, bool readonly);
+  void ramdiskStop(RamDisk *rdp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RAMDISK_H_ */
+
+/** @} */
diff --git a/os/various/tribuf.h b/os/various/tribuf.h
index 4ba3f25..8d8f9f4 100644
--- a/os/various/tribuf.h
+++ b/os/various/tribuf.h
@@ -22,8 +22,8 @@
  * @{

  */

 

-#ifndef _TRIBUF_H_

-#define _TRIBUF_H_

+#ifndef TRIBUF_H_

+#define TRIBUF_H_

 

 /*===========================================================================*/

 /* Driver constants.                                                         */

@@ -221,5 +221,5 @@ extern "C" {
 }

 #endif

 

-#endif  /* _TRIBUF_H_ */

+#endif  /* TRIBUF_H_ */

 /** @} */