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Diffstat (limited to 'os/common/ext/TivaWare/inc/hw_qei.h')
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1 files changed, 178 insertions, 0 deletions
diff --git a/os/common/ext/TivaWare/inc/hw_qei.h b/os/common/ext/TivaWare/inc/hw_qei.h new file mode 100644 index 0000000..93c4a07 --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_qei.h @@ -0,0 +1,178 @@ +//***************************************************************************** +// +// hw_qei.h - Macros used when accessing the QEI hardware. +// +// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_QEI_H__ +#define __HW_QEI_H__ + +//***************************************************************************** +// +// The following are defines for the QEI register offsets. +// +//***************************************************************************** +#define QEI_O_CTL 0x00000000 // QEI Control +#define QEI_O_STAT 0x00000004 // QEI Status +#define QEI_O_POS 0x00000008 // QEI Position +#define QEI_O_MAXPOS 0x0000000C // QEI Maximum Position +#define QEI_O_LOAD 0x00000010 // QEI Timer Load +#define QEI_O_TIME 0x00000014 // QEI Timer +#define QEI_O_COUNT 0x00000018 // QEI Velocity Counter +#define QEI_O_SPEED 0x0000001C // QEI Velocity +#define QEI_O_INTEN 0x00000020 // QEI Interrupt Enable +#define QEI_O_RIS 0x00000024 // QEI Raw Interrupt Status +#define QEI_O_ISC 0x00000028 // QEI Interrupt Status and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_CTL register. +// +//***************************************************************************** +#define QEI_CTL_FILTCNT_M 0x000F0000 // Input Filter Prescale Count +#define QEI_CTL_FILTEN 0x00002000 // Enable Input Filter +#define QEI_CTL_STALLEN 0x00001000 // Stall QEI +#define QEI_CTL_INVI 0x00000800 // Invert Index Pulse +#define QEI_CTL_INVB 0x00000400 // Invert PhB +#define QEI_CTL_INVA 0x00000200 // Invert PhA +#define QEI_CTL_VELDIV_M 0x000001C0 // Predivide Velocity +#define QEI_CTL_VELDIV_1 0x00000000 // QEI clock /1 +#define QEI_CTL_VELDIV_2 0x00000040 // QEI clock /2 +#define QEI_CTL_VELDIV_4 0x00000080 // QEI clock /4 +#define QEI_CTL_VELDIV_8 0x000000C0 // QEI clock /8 +#define QEI_CTL_VELDIV_16 0x00000100 // QEI clock /16 +#define QEI_CTL_VELDIV_32 0x00000140 // QEI clock /32 +#define QEI_CTL_VELDIV_64 0x00000180 // QEI clock /64 +#define QEI_CTL_VELDIV_128 0x000001C0 // QEI clock /128 +#define QEI_CTL_VELEN 0x00000020 // Capture Velocity +#define QEI_CTL_RESMODE 0x00000010 // Reset Mode +#define QEI_CTL_CAPMODE 0x00000008 // Capture Mode +#define QEI_CTL_SIGMODE 0x00000004 // Signal Mode +#define QEI_CTL_SWAP 0x00000002 // Swap Signals +#define QEI_CTL_ENABLE 0x00000001 // Enable QEI +#define QEI_CTL_FILTCNT_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_STAT register. +// +//***************************************************************************** +#define QEI_STAT_DIRECTION 0x00000002 // Direction of Rotation +#define QEI_STAT_ERROR 0x00000001 // Error Detected + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_POS register. +// +//***************************************************************************** +#define QEI_POS_M 0xFFFFFFFF // Current Position Integrator + // Value +#define QEI_POS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_MAXPOS register. +// +//***************************************************************************** +#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum Position Integrator + // Value +#define QEI_MAXPOS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_LOAD register. +// +//***************************************************************************** +#define QEI_LOAD_M 0xFFFFFFFF // Velocity Timer Load Value +#define QEI_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_TIME register. +// +//***************************************************************************** +#define QEI_TIME_M 0xFFFFFFFF // Velocity Timer Current Value +#define QEI_TIME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_COUNT register. +// +//***************************************************************************** +#define QEI_COUNT_M 0xFFFFFFFF // Velocity Pulse Count +#define QEI_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_SPEED register. +// +//***************************************************************************** +#define QEI_SPEED_M 0xFFFFFFFF // Velocity +#define QEI_SPEED_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_INTEN register. +// +//***************************************************************************** +#define QEI_INTEN_ERROR 0x00000008 // Phase Error Interrupt Enable +#define QEI_INTEN_DIR 0x00000004 // Direction Change Interrupt + // Enable +#define QEI_INTEN_TIMER 0x00000002 // Timer Expires Interrupt Enable +#define QEI_INTEN_INDEX 0x00000001 // Index Pulse Detected Interrupt + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_RIS register. +// +//***************************************************************************** +#define QEI_RIS_ERROR 0x00000008 // Phase Error Detected +#define QEI_RIS_DIR 0x00000004 // Direction Change Detected +#define QEI_RIS_TIMER 0x00000002 // Velocity Timer Expired +#define QEI_RIS_INDEX 0x00000001 // Index Pulse Asserted + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_ISC register. +// +//***************************************************************************** +#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt +#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt +#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired Interrupt +#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt + +#endif // __HW_QEI_H__ |