diff options
Diffstat (limited to 'os/hal/ports/TIVA/TM4C123x/hal_lld.c')
| -rw-r--r-- | os/hal/ports/TIVA/TM4C123x/hal_lld.c | 52 |
1 files changed, 26 insertions, 26 deletions
diff --git a/os/hal/ports/TIVA/TM4C123x/hal_lld.c b/os/hal/ports/TIVA/TM4C123x/hal_lld.c index ddcddb3..10cd903 100644 --- a/os/hal/ports/TIVA/TM4C123x/hal_lld.c +++ b/os/hal/ports/TIVA/TM4C123x/hal_lld.c @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -76,60 +76,60 @@ void tiva_clock_init(void) * PLL. */ /* read */ - rcc = SYSCTL->RCC; - rcc2 = SYSCTL->RCC2; + rcc = HWREG(SYSCTL_RCC); + rcc2 = HWREG(SYSCTL_RCC2); /* modify */ - rcc |= TIVA_RCC_BYPASS; - rcc &= ~TIVA_RCC_USESYSDIV; - rcc2 |= TIVA_RCC2_BYPASS2 | TIVA_RCC2_USERCC2; + rcc |= SYSCTL_RCC_BYPASS; + rcc &= ~SYSCTL_RCC_USESYSDIV; + rcc2 |= SYSCTL_RCC2_BYPASS2 | SYSCTL_RCC2_USERCC2; /* write */ - SYSCTL->RCC = rcc; - SYSCTL->RCC2 = rcc2; + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC2) = rcc2; /* 2 Select the crystal value (XTAL) and oscillator source (OSCSRC), and * clear the PWRDN bit in RCC and RCC2. Setting the XTAL field automatically * pulls valid PLL configuration data for the appropriate crystal, and * clearing the PWRDN bit powers and enables the PLL and its output. */ /* modify */ - rcc &= ~(TIVA_RCC_OSCSRC_MASK | TIVA_RCC_XTAL_MASK | TIVA_RCC_PWRDN | TIVA_RCC_MOSCDIS); - rcc |= ((TIVA_XTAL | TIVA_OSCSRC | TIVA_MOSCDIS) & (TIVA_RCC_XTAL_MASK | TIVA_RCC_OSCSRC_MASK | TIVA_RCC_MOSCDIS)); - rcc2 &= ~(TIVA_RCC2_OSCSRC2_MASK | TIVA_RCC2_PWRDN2); - rcc2 |= ((TIVA_OSCSRC | TIVA_DIV400) & (TIVA_RCC2_OSCSRC2_MASK | TIVA_RCC2_DIV400)); + rcc &= ~(SYSCTL_RCC_OSCSRC_M | SYSCTL_RCC_XTAL_M | SYSCTL_RCC_PWRDN | SYSCTL_RCC_MOSCDIS); + rcc |= ((TIVA_XTAL | TIVA_OSCSRC | TIVA_MOSCDIS) & (SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M | SYSCTL_RCC_MOSCDIS)); + rcc2 &= ~(SYSCTL_RCC2_OSCSRC2_M | SYSCTL_RCC2_PWRDN2); + rcc2 |= ((TIVA_OSCSRC | TIVA_DIV400) & (SYSCTL_RCC2_OSCSRC2_M | SYSCTL_RCC2_DIV400)); /* write */ - SYSCTL->RCC = rcc; - SYSCTL->RCC2 = rcc2; + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC2) = rcc2; for(i = 100000; i; i--); /* 3. Select the desired system divider (SYSDIV) in RCC and RCC2 and set the * USESYSDIV bit in RCC. The SYSDIV field determines the system frequency for * the microcontroller. */ /* modify */ - rcc &= ~TIVA_RCC_SYSDIV_MASK; - rcc |= (TIVA_SYSDIV & TIVA_RCC_SYSDIV_MASK) | TIVA_USESYSDIV; - rcc2 &= ~(TIVA_RCC2_SYSDIV2_MASK | TIVA_RCC2_SYSDIV2LSB); - rcc2 |= ((TIVA_SYSDIV2 | TIVA_SYSDIV2LSB) & (TIVA_RCC2_SYSDIV2_MASK | TIVA_RCC2_SYSDIV2LSB)); + rcc &= ~SYSCTL_RCC_SYSDIV_M; + rcc |= (TIVA_SYSDIV & SYSCTL_RCC_SYSDIV_M) | SYSCTL_RCC_USESYSDIV; + rcc2 &= ~(SYSCTL_RCC2_SYSDIV2_M | SYSCTL_RCC2_SYSDIV2LSB); + rcc2 |= ((TIVA_SYSDIV2 | TIVA_SYSDIV2LSB) & (SYSCTL_RCC2_SYSDIV2_M | SYSCTL_RCC2_SYSDIV2LSB)); /* write */ - SYSCTL->RCC = rcc; - SYSCTL->RCC2 = rcc2; + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC2) = rcc2; /* 4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw * Interrupt Status (RIS) register. */ - while ((SYSCTL->RIS & SYSCTL_RIS_PLLLRIS) == 0); + while ((HWREG(SYSCTL_RIS) & SYSCTL_RIS_PLLLRIS) == 0); /* 5. Enable use of the PLL by clearing the BYPASS bit in RCC and RCC2. */ - rcc &= ~TIVA_RCC_BYPASS; - rcc2 &= ~TIVA_RCC2_BYPASS2; + rcc &= ~SYSCTL_RCC_BYPASS; + rcc2 &= ~SYSCTL_RCC2_BYPASS2; rcc |= (TIVA_BYPASS_VALUE << 11); rcc2 |= (TIVA_BYPASS_VALUE << 11); - SYSCTL->RCC = rcc; - SYSCTL->RCC2 = rcc2; + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC2) = rcc2; #if HAL_USE_PWM - SYSCTL->RCC |= TIVA_PWM_FIELDS; + HWREG(SYSCTL_RCC) |= TIVA_PWM_FIELDS; #endif #if defined(TIVA_UDMA_REQUIRED) |