diff options
author | Diego Ismirlian <dismirlian@gmail.com> | 2019-08-24 17:45:41 -0300 |
---|---|---|
committer | Diego Ismirlian <dismirlian@gmail.com> | 2019-08-24 17:45:41 -0300 |
commit | 7b2c61a676e024163057ec5ccc508a29ab3b9ed4 (patch) | |
tree | 5d1f5423a4e720d657681794ac81dc2a2004cbb0 /os | |
parent | 81391097156ce2c9fc71c3350457522841e10095 (diff) | |
parent | e346e779339636f578536785014609e46866fb9c (diff) | |
download | ChibiOS-Contrib-7b2c61a676e024163057ec5ccc508a29ab3b9ed4.tar.gz ChibiOS-Contrib-7b2c61a676e024163057ec5ccc508a29ab3b9ed4.tar.bz2 ChibiOS-Contrib-7b2c61a676e024163057ec5ccc508a29ab3b9ed4.zip |
Merge branch 'master' of https://github.com/ChibiOS/ChibiOS-Contrib
Diffstat (limited to 'os')
159 files changed, 8843 insertions, 4116 deletions
diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_MK66F18.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_MK66F18.mk index 50dff2d..3277ab8 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_MK66F18.mk +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_MK66F18.mk @@ -1,8 +1,8 @@ # List of the ChibiOS generic MK66F18 startup and CMSIS files.
-STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
- $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
-STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
$(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/MK66F18 \
@@ -11,3 +11,8 @@ STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \ $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/KINETIS
STARTUPLD = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x.mk index f474d19..f01bd22 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x.mk +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x.mk @@ -1,8 +1,8 @@ # List of the ChibiOS generic K20x startup and CMSIS files.
-STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
- $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
-STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
$(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/K20x \
diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk index 7ab25de..d9a059a 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk @@ -1,3 +1,8 @@ include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x.mk
STARTUPINC += $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/K20x5
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x7.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x7.mk index 3c8ea09..5c86011 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x7.mk +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x7.mk @@ -1,3 +1,8 @@ include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x.mk
STARTUPINC += $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/K20x7
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k60x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k60x.mk index 777df43..9bc04c3 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k60x.mk +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k60x.mk @@ -1,8 +1,8 @@ # List of the ChibiOS generic K60x startup and CMSIS files.
-STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
- $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
-STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
$(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/K60x \
@@ -10,3 +10,8 @@ STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \ $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/KINETIS
STARTUPLD = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk index 0c9d329..0a5d98e 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk @@ -1,8 +1,8 @@ # List of the ChibiOS generic KL2x startup and CMSIS files.
-STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
- $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
-STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
$(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/KL2x \
@@ -11,3 +11,8 @@ STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \ $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/KINETIS
STARTUPLD = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf51.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf51.mk index 8ec318f..36da146 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf51.mk +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf51.mk @@ -1,11 +1,16 @@ # List of the ChibiOS generic NRF51 startup and CMSIS files.
-STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
- $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
-STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
STARTUPINC = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/NRF51822 \
$(CHIBIOS)/os/common/ext/CMSIS/include \
$(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include
STARTUPLD = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf52.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf52.mk index 450ec41..e95f33d 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf52.mk +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf52.mk @@ -1,11 +1,16 @@ # List of the ChibiOS generic NRF51 startup and CMSIS files.
-STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
- $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
-STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
STARTUPINC = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/NRF52832 \
$(CHIBIOS)/os/common/ext/CMSIS/include \
$(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include
STARTUPLD = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.mk b/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.mk index f74d306..15c74fc 100644 --- a/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.mk +++ b/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.mk @@ -3,3 +3,7 @@ BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.c # Required include directories
BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/FREESCALE_FREEDOM_K20D50M
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
diff --git a/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.mk b/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.mk index 3097a90..96a2498 100644 --- a/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.mk +++ b/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.mk @@ -3,3 +3,7 @@ BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.c # Required include directories
BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/FREESCALE_FREEDOM_KL25Z
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
diff --git a/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.mk b/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.mk index c352346..4ee8195 100644 --- a/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.mk +++ b/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.mk @@ -3,3 +3,7 @@ BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.c # Required include directories
BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/FREESCALE_FREEDOM_KL26Z
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
diff --git a/os/hal/boards/MCHCK_K20/board.mk b/os/hal/boards/MCHCK_K20/board.mk index 22406ac..3082383 100644 --- a/os/hal/boards/MCHCK_K20/board.mk +++ b/os/hal/boards/MCHCK_K20/board.mk @@ -3,3 +3,7 @@ BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/MCHCK_K20/board.c # Required include directories
BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/MCHCK_K20
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
diff --git a/os/hal/boards/MICROBIT/board.mk b/os/hal/boards/MICROBIT/board.mk index 3595b1a..8e26ae6 100644 --- a/os/hal/boards/MICROBIT/board.mk +++ b/os/hal/boards/MICROBIT/board.mk @@ -3,3 +3,7 @@ BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/MICROBIT/board.c # Required include directories BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/MICROBIT + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) diff --git a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.mk b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.mk index 8c28257..0303442 100644 --- a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.mk +++ b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.mk @@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board. # Required include directories BOARDINC = $(CHIBIOS_CONTRIB)/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2 + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) diff --git a/os/hal/boards/NRF51-DK/board.mk b/os/hal/boards/NRF51-DK/board.mk index 631927b..3e3e465 100644 --- a/os/hal/boards/NRF51-DK/board.mk +++ b/os/hal/boards/NRF51-DK/board.mk @@ -9,3 +9,7 @@ JLINK_DEVICE = nrf51422 JLINK_PRE_FLASH = w4 4001e504 1 JLINK_ERASE_ALL = w4 4001e504 2\nw4 4001e50c 1\nsleep 100 JLINK_PIN_RESET = w4 40000544 1 + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) diff --git a/os/hal/boards/NRF52-DK/board.mk b/os/hal/boards/NRF52-DK/board.mk index 4310291..b296d27 100644 --- a/os/hal/boards/NRF52-DK/board.mk +++ b/os/hal/boards/NRF52-DK/board.mk @@ -10,3 +10,6 @@ JLINK_PRE_FLASH = w4 4001e504 1 #JLINK_ERASE_ALL = w4 4001e504 2\nw4 4001e50c 1\nsleep 100 JLINK_PIN_RESET = w4 40000544 1 +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) diff --git a/os/hal/boards/NRF52-E73-2G4M04S/board.c b/os/hal/boards/NRF52-E73-2G4M04S/board.c new file mode 100644 index 0000000..adf002d --- /dev/null +++ b/os/hal/boards/NRF52-E73-2G4M04S/board.c @@ -0,0 +1,81 @@ +/* + Copyright (C) 2016 Stéphane D'Alu + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = +{ + .pads = { + PAL_MODE_UNCONNECTED, /* P0.0 : XTAL (32MHz) */ + PAL_MODE_UNCONNECTED, /* P0.1 : XTAL (32MHz) */ + PAL_MODE_UNCONNECTED, /* P0.2 */ + PAL_MODE_UNCONNECTED, /* P0.3 */ + PAL_MODE_UNCONNECTED, /* P0.4 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.5 : UART_RTS */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.6 : UART_TX */ + PAL_MODE_INPUT_PULLUP, /* P0.7 : UART_CTS */ + PAL_MODE_INPUT_PULLUP, /* P0.8 : UART_RX */ + PAL_MODE_UNCONNECTED, /* P0.9 */ + PAL_MODE_UNCONNECTED, /* P0.10 */ + PAL_MODE_UNCONNECTED, /* P0.11 */ + PAL_MODE_UNCONNECTED, /* P0.12 */ + PAL_MODE_INPUT, /* P0.13: BTN1 */ + PAL_MODE_INPUT, /* P0.14: BTN2 */ + PAL_MODE_INPUT_PULLUP, /* P0.15: BTN3 */ + PAL_MODE_INPUT_PULLUP, /* P0.16: BTN4 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.17: LED1 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.18: LED2 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.19: LED3 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.20: LED4 */ + PAL_MODE_UNCONNECTED, /* P0.21 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.22: SPI_SS */ + PAL_MODE_INPUT_PULLUP, /* P0.23: SPI_MISO */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.24: SPI_MOSI */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.25: SPI_SCK */ + PAL_MODE_OUTPUT_OPENDRAIN, /* P0.26: SDA */ + PAL_MODE_OUTPUT_OPENDRAIN, /* P0.27: SCL */ + PAL_MODE_UNCONNECTED, /* P0.28 */ + PAL_MODE_UNCONNECTED, /* P0.29 */ + PAL_MODE_UNCONNECTED, /* P0.30 */ + PAL_MODE_UNCONNECTED, /* P0.31 */ + }, +}; +#endif + +/** + * @brief Early initialization code. + * @details This initialization is performed just after reset before BSS and + * DATA segments initialization. + */ +void __early_init(void) +{ +} + +/** + * @brief Late initialization code. + * @note This initialization is performed after BSS and DATA segments + * initialization and before invoking the main() function. + */ +void boardInit(void) +{ +} diff --git a/os/hal/boards/NRF52-E73-2G4M04S/board.h b/os/hal/boards/NRF52-E73-2G4M04S/board.h new file mode 100644 index 0000000..c78909f --- /dev/null +++ b/os/hal/boards/NRF52-E73-2G4M04S/board.h @@ -0,0 +1,164 @@ +/* + Copyright (C) 2016 Stephane D'Alu + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* Board identifier. */ +#define BOARD_NRF52_EBYTE_E73 +#define BOARD_NAME "nRF52 EBYTE E73-2G4M04S" + +/* Board oscillators-related settings. */ +#define NRF5_XTAL_VALUE 32000000 +#define NRF5_HFCLK_SOURCE NRF5_HFCLK_HFXO +#define NRF5_LFCLK_SOURCE NRF5_LFCLK_XTAL + +#define NRF5_HFCLK_HFINT 0 +#define NRF5_HFCLK_HFXO 1 + +#define NRF5_LFCLK_RC 0 +#define NRF5_LFCLK_XTAL 1 +#define NRF5_LFCLK_SYNTH 2 + +/* + * GPIO pins. + */ +/* Defined by board */ +#define BTN1 13U +#define BTN2 14U +#define BTN3 15U +#define BTN4 16U +#define LED1 17U +#define LED2 18U +#define LED3 19U +#define LED4 20U +#define UART_RTS 5U +#define UART_TX 6U +#define UART_CTS 7U +#define UART_RX 8U +#define NFC1 9U +#define NFC2 10U +#define I2C_SCL 27U +#define I2C_SDA 26U + +/* Our definitions */ +#define SPI_SCK 25U +#define SPI_MOSI 24U +#define SPI_MISO 23U +#define SPI_SS 22U + +/* Analog input */ +#define AIN0 2U +#define AIN1 3U +#define AIN2 4U +#define AIN3 5U +#define AIN4 28U +#define AIN5 29U +#define AIN6 30U +#define AIN7 31U +#define AREF0 AIN0 +#define AREF1 AIN1 + +/* + * IO pins assignments. + */ +/* Defined by board */ +#define IOPORT1_BTN1 13U +#define IOPORT1_BTN2 14U +#define IOPORT1_BTN3 15U +#define IOPORT1_BTN4 16U +#define IOPORT1_LED1 17U +#define IOPORT1_LED2 18U +#define IOPORT1_LED3 19U +#define IOPORT1_LED4 20U +#define IOPORT1_UART_RTS 5U +#define IOPORT1_UART_TX 6U +#define IOPORT1_UART_CTS 7U +#define IOPORT1_UART_RX 8U +#define IOPORT1_NFC1 9U +#define IOPORT1_NFC2 10U +#define IOPORT1_I2C_SCL 27U +#define IOPORT1_I2C_SDA 26U +#define IOPORT1_RESET 21U + +/* Our definitions */ +#define IOPORT1_SPI_SCK 25U +#define IOPORT1_SPI_MOSI 24U +#define IOPORT1_SPI_MISO 23U +#define IOPORT1_SPI_SS 22U + +/* Analog inpupt */ +#define IOPORT1_AIN0 2U +#define IOPORT1_AIN1 3U +#define IOPORT1_AIN2 4U +#define IOPORT1_AIN3 5U +#define IOPORT1_AIN4 28U +#define IOPORT1_AIN5 29U +#define IOPORT1_AIN6 30U +#define IOPORT1_AIN7 31U +#define IOPORT1_AREF0 IOPORT1_AIN0 +#define IOPORT1_AREF1 IOPORT1_AIN1 + +/* + * IO lines assignments. + */ +/* Board defined */ +#define LINE_BTN1 PAL_LINE(IOPORT1, IOPORT1_BTN1) +#define LINE_BTN2 PAL_LINE(IOPORT1, IOPORT1_BTN2) +#define LINE_BTN3 PAL_LINE(IOPORT1, IOPORT1_BTN3) +#define LINE_BTN4 PAL_LINE(IOPORT1, IOPORT1_BTN4) +#define LINE_LED1 PAL_LINE(IOPORT1, IOPORT1_LED1) +#define LINE_LED2 PAL_LINE(IOPORT1, IOPORT1_LED2) +#define LINE_LED3 PAL_LINE(IOPORT1, IOPORT1_LED3) +#define LINE_LED4 PAL_LINE(IOPORT1, IOPORT1_LED4) +#define LINE_UART_RTS PAL_LINE(IOPORT1, IOPORT1_UART_RTS) +#define LINE_UART_TX PAL_LINE(IOPORT1, IOPORT1_UART_TX) +#define LINE_UART_CTS PAL_LINE(IOPORT1, IOPORT1_UART_CTS) +#define LINE_UART_RX PAL_LINE(IOPORT1, IOPORT1_UART_RX) +#define LINE_NFC1 PAL_LINE(IOPORT1, IOPORT1_NFC1) +#define LINE_NFC2 PAL_LINE(IOPORT1, IOPORT1_NFC2) +#define LINE_I2C_SCL PAL_LINE(IOPORT1, IOPORT1_I2C_SCL) +#define LINE_I2C_SDA PAL_LINE(IOPORT1, IOPORT1_I2C_SDA) + +/* Our definitions */ +#define LINE_SPI_SCK PAL_LINE(IOPORT1, IOPORT1_SPI_SCK) +#define LINE_SPI_MOSI PAL_LINE(IOPORT1, IOPORT1_SPI_MOSI) +#define LINE_SPI_MISO PAL_LINE(IOPORT1, IOPORT1_SPI_MISO) +#define LINE_SPI_SS PAL_LINE(IOPORT1, IOPORT1_SPI_SS) + +/* Analog line */ +#define LINE_AIN0 PAL_LINE(IOPORT1, IOPORT1_AIN0) +#define LINE_AIN1 PAL_LINE(IOPORT1, IOPORT1_AIN1) +#define LINE_AIN2 PAL_LINE(IOPORT1, IOPORT1_AIN2) +#define LINE_AIN3 PAL_LINE(IOPORT1, IOPORT1_AIN3) +#define LINE_AIN4 PAL_LINE(IOPORT1, IOPORT1_AIN4) +#define LINE_AIN5 PAL_LINE(IOPORT1, IOPORT1_AIN5) +#define LINE_AIN6 PAL_LINE(IOPORT1, IOPORT1_AIN6) +#define LINE_AIN7 PAL_LINE(IOPORT1, IOPORT1_AIN7) +#define LINE_AREF0 PAL_LINE(IOPORT1, IOPORT1_AREF0) +#define LINE_AREF1 PAL_LINE(IOPORT1, IOPORT1_AREF1) + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/os/hal/boards/NRF52-E73-2G4M04S/board.mk b/os/hal/boards/NRF52-E73-2G4M04S/board.mk new file mode 100644 index 0000000..8876668 --- /dev/null +++ b/os/hal/boards/NRF52-E73-2G4M04S/board.mk @@ -0,0 +1,8 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/NRF52-E73-2G4M04S/board.c + +# Required include directories +BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/NRF52-E73-2G4M04S + +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) diff --git a/os/hal/boards/OSHCHIP_V1.0/board.mk b/os/hal/boards/OSHCHIP_V1.0/board.mk index 08afdbd..de1c59d 100644 --- a/os/hal/boards/OSHCHIP_V1.0/board.mk +++ b/os/hal/boards/OSHCHIP_V1.0/board.mk @@ -3,3 +3,7 @@ BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/OSHCHIP_V1.0/board.c # Required include directories BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/OSHCHIP_V1.0 + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) diff --git a/os/hal/boards/PJRC_TEENSY_3/board.mk b/os/hal/boards/PJRC_TEENSY_3/board.mk index b9dcdc8..cc268a9 100644 --- a/os/hal/boards/PJRC_TEENSY_3/board.mk +++ b/os/hal/boards/PJRC_TEENSY_3/board.mk @@ -3,3 +3,7 @@ BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3/board.c # Required include directories
BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
diff --git a/os/hal/boards/PJRC_TEENSY_3_1/board.mk b/os/hal/boards/PJRC_TEENSY_3_1/board.mk index 572a524..c6027b8 100644 --- a/os/hal/boards/PJRC_TEENSY_3_1/board.mk +++ b/os/hal/boards/PJRC_TEENSY_3_1/board.mk @@ -3,3 +3,7 @@ BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3_1/board.c # Required include directories
BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3_1
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
diff --git a/os/hal/boards/PJRC_TEENSY_3_5/board.mk b/os/hal/boards/PJRC_TEENSY_3_5/board.mk index 4e18eb0..6c88262 100644 --- a/os/hal/boards/PJRC_TEENSY_3_5/board.mk +++ b/os/hal/boards/PJRC_TEENSY_3_5/board.mk @@ -3,3 +3,7 @@ BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3_5/board.c # Required include directories
BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3_5
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
diff --git a/os/hal/boards/PJRC_TEENSY_3_6/board.mk b/os/hal/boards/PJRC_TEENSY_3_6/board.mk index 6e2695c..0424c4d 100644 --- a/os/hal/boards/PJRC_TEENSY_3_6/board.mk +++ b/os/hal/boards/PJRC_TEENSY_3_6/board.mk @@ -3,3 +3,7 @@ BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3_6/board.c # Required include directories
BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3_6
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
diff --git a/os/hal/boards/PJRC_TEENSY_LC/board.mk b/os/hal/boards/PJRC_TEENSY_LC/board.mk index 85c643a..87accf3 100644 --- a/os/hal/boards/PJRC_TEENSY_LC/board.mk +++ b/os/hal/boards/PJRC_TEENSY_LC/board.mk @@ -3,3 +3,7 @@ BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_LC/board.c # Required include directories
BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_LC
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
diff --git a/os/hal/boards/ST_STM32F0308_DISCOVERY/board.mk b/os/hal/boards/ST_STM32F0308_DISCOVERY/board.mk index 35b3939..614835d 100644 --- a/os/hal/boards/ST_STM32F0308_DISCOVERY/board.mk +++ b/os/hal/boards/ST_STM32F0308_DISCOVERY/board.mk @@ -3,3 +3,7 @@ BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c # Required include directories
BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/ST_STM32F0308_DISCOVERY
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
diff --git a/os/hal/boards/WVSHARE_BLE400/board.mk b/os/hal/boards/WVSHARE_BLE400/board.mk index ade4201..684efeb 100644 --- a/os/hal/boards/WVSHARE_BLE400/board.mk +++ b/os/hal/boards/WVSHARE_BLE400/board.mk @@ -3,3 +3,7 @@ BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/WVSHARE_BLE400/board.c # Required include directories BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/WVSHARE_BLE400 + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) diff --git a/os/hal/hal.mk b/os/hal/hal.mk index 119db8a..cd8420b 100644 --- a/os/hal/hal.mk +++ b/os/hal/hal.mk @@ -1,27 +1,109 @@ include ${CHIBIOS}/os/hal/hal.mk
-HALSRC += ${CHIBIOS_CONTRIB}/os/hal/src/hal_community.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_nand.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_onewire.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_eicu.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_crc.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_rng.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_usbh.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_debug.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_desciter.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_hub.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_msd.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_ftdi.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_aoa.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_hid.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_uvc.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_ee24xx.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_ee25xx.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_eeprom.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_timcap.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_qei.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_usb_hid.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_usb_msd.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_comp.c
+ifeq ($(USE_SMART_BUILD),yes)
-HALINC += ${CHIBIOS_CONTRIB}/os/hal/include
+# Configuration files directory
+ifeq ($(CONFDIR),)
+ CONFDIR = .
+endif
+
+HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define"))
+
+HALSRC_CONTRIB := ${CHIBIOS_CONTRIB}/os/hal/src/hal_community.c
+ifneq ($(findstring HAL_USE_NAND TRUE,$(HALCONF)),)
+HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_nand.c
+endif
+ifneq ($(findstring HAL_USE_ONEWIRE TRUE,$(HALCONF)),)
+HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_onewire.c
+endif
+ifneq ($(findstring HAL_USE_EICU TRUE,$(HALCONF)),)
+HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_eicu.c
+endif
+ifneq ($(findstring HAL_USE_CRC TRUE,$(HALCONF)),)
+HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_crc.c
+endif
+ifneq ($(findstring HAL_USE_RNG TRUE,$(HALCONF)),)
+HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_rng.c
+endif
+ifneq ($(findstring HAL_USE_USBH TRUE,$(HALCONF)),)
+HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_usbh.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_debug.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_desciter.c
+endif
+ifneq ($(findstring HAL_USBH_USE_HUB TRUE,$(HALCONF)),)
+HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_hub.c
+endif
+ifneq ($(findstring HAL_USBH_USE_MSD TRUE,$(HALCONF)),)
+HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_msd.c
+endif
+ifneq ($(findstring HAL_USBH_USE_FTDI TRUE,$(HALCONF)),)
+HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_usbh_ftdi.c
+endif
+ifneq ($(findstring HAL_USBH_USE_AOA TRUE,$(HALCONF)),)
+HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_usbh_aoa.c
+endif
+ifneq ($(findstring HAL_USBH_USE_HID TRUE,$(HALCONF)),)
+HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_usbh_hid.c
+endif
+ifneq ($(findstring HAL_USBH_USE_UVC TRUE,$(HALCONF)),)
+HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_uvc.c
+endif
+ifneq ($(findstring HAL_USE_EEPROM TRUE,$(HALCONF)),)
+HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_eeprom.c
+ifneq ($(findstring EEPROM_USE_EE25XX TRUE,$(HALCONF)),)
+HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_ee25xx.c
+endif
+ifneq ($(findstring EEPROM_USE_EE24XX TRUE,$(HALCONF)),)
+HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_ee24xx.c
+endif
+endif
+ifneq ($(findstring HAL_USE_TIMCAP TRUE,$(HALCONF)),)
+HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_timcap.c
+endif
+ifneq ($(findstring HAL_USE_QEI TRUE,$(HALCONF)),)
+HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_qei.c
+endif
+ifneq ($(findstring HAL_USE_USB_HID TRUE,$(HALCONF)),)
+HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_usb_hid.c
+endif
+ifneq ($(findstring HAL_USE_USB_MSD TRUE,$(HALCONF)),)
+HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_usb_msd.c
+endif
+ifneq ($(findstring HAL_USE_COMP TRUE,$(HALCONF)),)
+HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_comp.c
+endif
+ifneq ($(findstring HAL_USE_OPAMP TRUE,$(HALCONF)),)
+HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_opamp.c
+endif
+else
+HALSRC_CONTRIB := ${CHIBIOS_CONTRIB}/os/hal/src/hal_community.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/hal_nand.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/hal_onewire.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/hal_eicu.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/hal_crc.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/hal_rng.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/hal_usbh.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_debug.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_desciter.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_hub.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_msd.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_ftdi.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_aoa.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_hid.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_uvc.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/hal_ee24xx.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/hal_ee25xx.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/hal_eeprom.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/hal_timcap.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/hal_qei.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/hal_usb_hid.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/hal_usb_msd.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/hal_comp.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/hal_opamp.c
+endif
+
+HALINC_CONTRIB := ${CHIBIOS_CONTRIB}/os/hal/include
+
+# Shared variables
+ALLCSRC += $(HALSRC_CONTRIB)
+ALLINC += $(HALINC_CONTRIB)
diff --git a/os/hal/include/hal_community.h b/os/hal/include/hal_community.h index 83b1f02..f84e90a 100644 --- a/os/hal/include/hal_community.h +++ b/os/hal/include/hal_community.h @@ -75,6 +75,10 @@ #define HAL_USE_COMP FALSE
#endif
+#if !defined(HAL_USE_OPAMP)
+#define HAL_USE_OPAMP FALSE
+#endif
+
/* Abstract interfaces.*/
/* Shared headers.*/
@@ -87,6 +91,7 @@ #include "hal_timcap.h"
#include "hal_qei.h"
#include "hal_comp.h"
+#include "hal_opamp.h"
/* Complex drivers.*/
#include "hal_onewire.h"
diff --git a/os/hal/ports/NRF5/NRF51822/hal_ext_lld_isr.h b/os/hal/include/hal_opamp.h index d606866..b20c938 100644 --- a/os/hal/ports/NRF5/NRF51822/hal_ext_lld_isr.h +++ b/os/hal/include/hal_opamp.h @@ -1,79 +1,97 @@ -/*
- Copyright (C) 2015 Stephen Caudle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file NRF51x22/ext_lld_isr.h
- * @brief NRF51x22 EXT subsystem low level driver ISR header.
- *
- * @addtogroup EXT
- * @{
- */
-
-#ifndef HAL_EXT_LLD_ISR_H
-#define HAL_EXT_LLD_ISR_H
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief GPIOTE interrupt priority level setting.
- */
-#if !defined(NRF5_EXT_GPIOTE_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define NRF5_EXT_GPIOTE_IRQ_PRIORITY 3
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void ext_lld_exti_irq_enable(void);
- void ext_lld_exti_irq_disable(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_EXT */
-
-#endif /* HAL_EXT_LLD_ISR_H */
-
-/** @} */
+/* + ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio + Copyright (C) 2019 Fabien Poussin (fabien.poussin (at) google's mail) + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HAL_OPAMP_H_ +#define HAL_OPAMP_H_ + +#include "hal.h" + +#if (HAL_USE_OPAMP == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define OPAMP_P_BELOW_M (0U) +#define OPAMP_M_BELOW_P (1U) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + OPAMP_UNINIT = 0, /**< Not initialized. */ + OPAMP_STOP = 1, /**< Stopped. */ + OPAMP_ACTIVE = 2, /**< Active. */ + OPAMP_CALIBRATING = 3, /**< Calibration in progress. */ +} opampstate_t; + +/** + * @brief Type of a structure representing an OPAMP driver. + */ +typedef struct OPAMPDriver OPAMPDriver; + +#include "hal_opamp_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Calibrate opamps + * * + * @iclass + */ +#define opampCalibrate() opamp_lld_calibrate() +/** @} */ + +/** + * @name Low Level driver helper macros + * @{ + */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void opampInit(void); + void opampObjectInit(OPAMPDriver *opamp); + void opampStart(OPAMPDriver *opamp, const OPAMPConfig *config); + void opampStop(OPAMPDriver *opamp); + void opampEnable(OPAMPDriver *opamp); + void opampDisable(OPAMPDriver *opamp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_OPAMP */ + +#endif /* HAL_OPAMP_H_ */ diff --git a/os/hal/include/hal_qei.h b/os/hal/include/hal_qei.h index 15f24ce..de41b97 100644 --- a/os/hal/include/hal_qei.h +++ b/os/hal/include/hal_qei.h @@ -145,6 +145,7 @@ extern "C" { void qeiEnable(QEIDriver *qeip);
void qeiDisable(QEIDriver *qeip);
qeicnt_t qeiGetCount(QEIDriver *qeip);
+ void qeiSetCount(QEIDriver *qeip, qeicnt_t value);
qeidelta_t qeiUpdate(QEIDriver *qeip);
qeidelta_t qeiUpdateI(QEIDriver *qeip);
qeidelta_t qeiAdjustI(QEIDriver *qeip, qeidelta_t delta);
diff --git a/os/hal/ports/KINETIS/K20x/hal_spi_lld.c b/os/hal/ports/KINETIS/K20x/hal_spi_lld.c deleted file mode 100644 index 29ab4e8..0000000 --- a/os/hal/ports/KINETIS/K20x/hal_spi_lld.c +++ /dev/null @@ -1,539 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KINETIS/spi_lld.c
- * @brief KINETIS SPI subsystem low level driver source.
- *
- * @addtogroup SPI
- * @{
- */
-
-#include "hal.h"
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-#if !defined(KINETIS_SPI0_RX_DMA_IRQ_PRIORITY)
-#define KINETIS_SPI0_RX_DMA_IRQ_PRIORITY 8
-#endif
-
-#if !defined(KINETIS_SPI0_RX_DMAMUX_CHANNEL)
-#define KINETIS_SPI0_RX_DMAMUX_CHANNEL 0
-#endif
-
-#if !defined(KINETIS_SPI0_RX_DMA_CHANNEL)
-#define KINETIS_SPI0_RX_DMA_CHANNEL 0
-#endif
-
-#if !defined(KINETIS_SPI0_TX_DMAMUX_CHANNEL)
-#define KINETIS_SPI0_TX_DMAMUX_CHANNEL 1
-#endif
-
-#if !defined(KINETIS_SPI0_TX_DMA_CHANNEL)
-#define KINETIS_SPI0_TX_DMA_CHANNEL 1
-#endif
-
-#if !defined(KINETIS_SPI1_RX_DMA_IRQ_PRIORITY)
-#define KINETIS_SPI1_RX_DMA_IRQ_PRIORITY 8
-#endif
-
-#if !defined(KINETIS_SPI1_RX_DMAMUX_CHANNEL)
-#define KINETIS_SPI1_RX_DMAMUX_CHANNEL 0
-#endif
-
-#if !defined(KINETIS_SPI1_RX_DMA_CHANNEL)
-#define KINETIS_SPI1_RX_DMA_CHANNEL 0
-#endif
-
-#if !defined(KINETIS_SPI1_TX_DMAMUX_CHANNEL)
-#define KINETIS_SPI1_TX_DMAMUX_CHANNEL 1
-#endif
-
-#if !defined(KINETIS_SPI1_TX_DMA_CHANNEL)
-#define KINETIS_SPI1_TX_DMA_CHANNEL 1
-#endif
-
-#if KINETIS_SPI_USE_SPI0
-#define DMAMUX_SPI_RX_SOURCE 16
-#define DMAMUX_SPI_TX_SOURCE 17
-#endif
-
-#if KINETIS_SPI_USE_SPI1
-#define DMAMUX_SPI_RX_SOURCE 18
-#define DMAMUX_SPI_TX_SOURCE 19
-#endif
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/** @brief SPI0 driver identifier.*/
-#if KINETIS_SPI_USE_SPI0 || defined(__DOXYGEN__)
-SPIDriver SPID1;
-#endif
-
-/** @brief SPI1 driver identifier.*/
-#if KINETIS_SPI_USE_SPI1 || defined(__DOXYGEN__)
-SPIDriver SPID2;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/* Use a dummy byte as the source/destination when a buffer is not provided */
-/* Note: The MMC driver relies on 0xFF being sent for dummy bytes. */
-static volatile uint16_t dmaRxDummy;
-static uint16_t dmaTxDummy = 0xFFFF;
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-static void spi_start_xfer(SPIDriver *spip, bool polling)
-{
- /*
- * Enable the DSPI peripheral in master mode.
- * Clear the TX and RX FIFOs.
- * */
- spip->spi->MCR = SPIx_MCR_MSTR | SPIx_MCR_CLR_TXF | SPIx_MCR_CLR_RXF;
-
- /* If we are not polling then enable DMA */
- if (!polling) {
-
- /* Enable receive dma and transmit dma */
- spip->spi->RSER = SPIx_RSER_RFDF_DIRS | SPIx_RSER_RFDF_RE |
- SPIx_RSER_TFFF_RE | SPIx_RSER_TFFF_DIRS;
-
- /* Configure RX DMA */
- if (spip->rxbuf) {
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DADDR = (uint32_t)spip->rxbuf;
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DOFF = spip->word_size;
- } else {
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DADDR = (uint32_t)&dmaRxDummy;
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DOFF = 0;
- }
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].BITER_ELINKNO = spip->count;
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].CITER_ELINKNO = spip->count;
-
- /* Enable Request Register (ERQ) for RX by writing 0 to SERQ */
- DMA->SERQ = KINETIS_SPI0_RX_DMA_CHANNEL;
-
- /* Configure TX DMA */
- if (spip->txbuf) {
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SADDR = (uint32_t)spip->txbuf;
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SOFF = spip->word_size;
- } else {
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SADDR = (uint32_t)&dmaTxDummy;
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SOFF = 0;
- }
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].BITER_ELINKNO = spip->count;
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].CITER_ELINKNO = spip->count;
-
- /* Enable Request Register (ERQ) for TX by writing 1 to SERQ */
- DMA->SERQ = KINETIS_SPI0_TX_DMA_CHANNEL;
- }
-}
-
-static void spi_stop_xfer(SPIDriver *spip)
-{
- /* Halt the DSPI peripheral */
- spip->spi->MCR = SPIx_MCR_MSTR | SPIx_MCR_HALT;
-
- /* Clear all the flags which are currently set. */
- spip->spi->SR |= spip->spi->SR;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if KINETIS_SPI_USE_SPI0 || defined(__DOXYGEN__)
-
-OSAL_IRQ_HANDLER(KINETIS_DMA0_IRQ_VECTOR) {
- OSAL_IRQ_PROLOGUE();
-
- /* Clear bit 0 in Interrupt Request Register (INT) by writing 0 to CINT */
- DMA->CINT = KINETIS_SPI0_RX_DMA_CHANNEL;
-
- spi_stop_xfer(&SPID1);
-
- _spi_isr_code(&SPID1);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-#endif
-
-#if KINETIS_SPI_USE_SPI1 || defined(__DOXYGEN__)
-
-OSAL_IRQ_HANDLER(KINETIS_DMA0_IRQ_VECTOR) {
- OSAL_IRQ_PROLOGUE();
-
- /* Clear bit 0 in Interrupt Request Register (INT) by writing 0 to CINT */
- DMA->CINT = KINETIS_SPI1_RX_DMA_CHANNEL;
-
- spi_stop_xfer(&SPID2);
-
- _spi_isr_code(&SPID2);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level SPI driver initialization.
- *
- * @notapi
- */
-void spi_lld_init(void) {
-#if KINETIS_SPI_USE_SPI0
- spiObjectInit(&SPID1);
-#endif
-#if KINETIS_SPI_USE_SPI1
- spiObjectInit(&SPID2);
-#endif
-}
-
-/**
- * @brief Configures and activates the SPI peripheral.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_start(SPIDriver *spip) {
-
- /* If in stopped state then enables the SPI and DMA clocks.*/
- if (spip->state == SPI_STOP) {
-
-#if KINETIS_SPI_USE_SPI0
- if (&SPID1 == spip) {
-
- /* Enable the clock for SPI0 */
- SIM->SCGC6 |= SIM_SCGC6_SPI0;
-
- SPID1.spi = SPI0;
-
- if (spip->config->tar0) {
- spip->spi->CTAR[0] = spip->config->tar0;
- } else {
- spip->spi->CTAR[0] = KINETIS_SPI_TAR0_DEFAULT;
- }
- }
-#endif
-
-#if KINETIS_SPI_USE_SPI1
- if (&SPID2 == spip) {
-
- /* Enable the clock for SPI0 */
- SIM->SCGC6 |= SIM_SCGC6_SPI1;
-
- SPID2.spi = SPI1;
-
- if (spip->config->tar0) {
- spip->spi->CTAR[0] = spip->config->tar0;
- } else {
- spip->spi->CTAR[0] = KINETIS_SPI_TAR0_DEFAULT;
- }
- }
-#endif
-
- nvicEnableVector(DMA0_IRQn, KINETIS_SPI0_RX_DMA_IRQ_PRIORITY);
-
- SIM->SCGC6 |= SIM_SCGC6_DMAMUX;
- SIM->SCGC7 |= SIM_SCGC7_DMA;
-
- /* Clear DMA error flags */
- DMA->ERR = 0x0F;
-
-#if KINETIS_SPI_USE_SPI0
- /* Rx, select SPI Rx FIFO */
- DMAMUX->CHCFG[KINETIS_SPI0_RX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
- DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_RX_SOURCE);
-
- /* Tx, select SPI Tx FIFO */
- DMAMUX->CHCFG[KINETIS_SPI0_TX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
- DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_TX_SOURCE);
-
- /* Extract the frame size from the TAR */
- uint16_t frame_size = ((spip->spi->CTAR[0] >> SPIx_CTARn_FMSZ_SHIFT) &
- SPIx_CTARn_FMSZ_MASK) + 1;
-
- /* DMA transfer size is 16 bits for a frame size > 8 bits */
- uint16_t dma_size = frame_size > 8 ? 1 : 0;
-
- /* DMA word size is 2 for a 16 bit frame size */
- spip->word_size = frame_size > 8 ? 2 : 1;
-
- /* configure DMA RX fixed values */
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].SADDR = (uint32_t)&SPI0->POPR;
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].SOFF = 0;
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].SLAST = 0;
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DLASTSGA = 0;
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
- DMA_ATTR_DSIZE(dma_size);
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK |
- DMA_CSR_INTMAJOR_MASK;
-
- /* configure DMA TX fixed values */
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SLAST = 0;
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].DADDR = (uint32_t)&SPI0->PUSHR;
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].DOFF = 0;
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].DLASTSGA = 0;
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
- DMA_ATTR_DSIZE(dma_size);
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK;
-#endif
-
-#if KINETIS_SPI_USE_SPI1
- /* Rx, select SPI Rx FIFO */
- DMAMUX->CHCFG[KINETIS_SPI1_RX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
- DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_RX_SOURCE);
-
- /* Tx, select SPI Tx FIFO */
- DMAMUX->CHCFG[KINETIS_SPI1_TX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
- DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_TX_SOURCE);
-
- /* Extract the frame size from the TAR */
- uint16_t frame_size = ((spip->spi->CTAR[0] >> SPIx_CTARn_FMSZ_SHIFT) &
- SPIx_CTARn_FMSZ_MASK) + 1;
-
- /* DMA transfer size is 16 bits for a frame size > 8 bits */
- uint16_t dma_size = frame_size > 8 ? 1 : 0;
-
- /* DMA word size is 2 for a 16 bit frame size */
- spip->word_size = frame_size > 8 ? 2 : 1;
-
- /* configure DMA RX fixed values */
- DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].SADDR = (uint32_t)&SPI1->POPR;
- DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].SOFF = 0;
- DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].SLAST = 0;
- DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].DLASTSGA = 0;
- DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
- DMA_ATTR_DSIZE(dma_size);
- DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
- DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK |
- DMA_CSR_INTMAJOR_MASK;
-
- /* configure DMA TX fixed values */
- DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].SLAST = 0;
- DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].DADDR = (uint32_t)&SPI1->PUSHR;
- DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].DOFF = 0;
- DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].DLASTSGA = 0;
- DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
- DMA_ATTR_DSIZE(dma_size);
- DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
- DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK;
-#endif
- }
-}
-
-/**
- * @brief Deactivates the SPI peripheral.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_stop(SPIDriver *spip) {
-
- /* If in ready state then disables the SPI clock.*/
- if (spip->state == SPI_READY) {
-
- nvicDisableVector(DMA0_IRQn);
-
- SIM->SCGC7 &= ~SIM_SCGC7_DMA;
- SIM->SCGC6 &= ~SIM_SCGC6_DMAMUX;
-
-#if KINETIS_SPI_USE_SPI0
- if (&SPID1 == spip) {
- /* SPI halt.*/
- spip->spi->MCR |= SPIx_MCR_HALT;
- }
-
- /* Disable the clock for SPI0 */
- SIM->SCGC6 &= ~SIM_SCGC6_SPI0;
-#endif
-
-#if KINETIS_SPI_USE_SPI1
- if (&SPID2 == spip) {
- /* SPI halt.*/
- spip->spi->MCR |= SPIx_MCR_HALT;
- }
-
- /* Disable the clock for SPI1 */
- SIM->SCGC6 &= ~SIM_SCGC6_SPI1;
-#endif
- }
-}
-
-/**
- * @brief Asserts the slave select signal and prepares for transfers.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_select(SPIDriver *spip) {
-
- palClearPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief Deasserts the slave select signal.
- * @details The previously selected peripheral is unselected.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_unselect(SPIDriver *spip) {
-
- palSetPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief Ignores data on the SPI bus.
- * @details This asynchronous function starts the transmission of a series of
- * idle words on the SPI bus and ignores the received data.
- * @post At the end of the operation the configured callback is invoked.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be ignored
- *
- * @notapi
- */
-void spi_lld_ignore(SPIDriver *spip, size_t n) {
-
- spip->count = n;
- spip->rxbuf = NULL;
- spip->txbuf = NULL;
-
- spi_start_xfer(spip, false);
-}
-
-/**
- * @brief Exchanges data on the SPI bus.
- * @details This asynchronous function starts a simultaneous transmit/receive
- * operation.
- * @post At the end of the operation the configured callback is invoked.
- * @note The buffers are organized as uint8_t arrays for data sizes below or
- * equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be exchanged
- * @param[in] txbuf the pointer to the transmit buffer
- * @param[out] rxbuf the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_exchange(SPIDriver *spip, size_t n,
- const void *txbuf, void *rxbuf) {
-
- spip->count = n;
- spip->rxbuf = rxbuf;
- spip->txbuf = txbuf;
-
- spi_start_xfer(spip, false);
-}
-
-/**
- * @brief Sends data over the SPI bus.
- * @details This asynchronous function starts a transmit operation.
- * @post At the end of the operation the configured callback is invoked.
- * @note The buffers are organized as uint8_t arrays for data sizes below or
- * equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to send
- * @param[in] txbuf the pointer to the transmit buffer
- *
- * @notapi
- */
-void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
-
- spip->count = n;
- spip->rxbuf = NULL;
- spip->txbuf = (void *)txbuf;
-
- spi_start_xfer(spip, false);
-}
-
-/**
- * @brief Receives data from the SPI bus.
- * @details This asynchronous function starts a receive operation.
- * @post At the end of the operation the configured callback is invoked.
- * @note The buffers are organized as uint8_t arrays for data sizes below or
- * equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to receive
- * @param[out] rxbuf the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
-
- spip->count = n;
- spip->rxbuf = rxbuf;
- spip->txbuf = NULL;
-
- spi_start_xfer(spip, false);
-}
-
-/**
- * @brief Exchanges one frame using a polled wait.
- * @details This synchronous function exchanges one frame using a polled
- * synchronization method. This function is useful when exchanging
- * small amount of data on high speed channels, usually in this
- * situation is much more efficient just wait for completion using
- * polling than suspending the thread waiting for an interrupt.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] frame the data frame to send over the SPI bus
- * @return The received data frame from the SPI bus.
- */
-uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
-
- spi_start_xfer(spip, true);
-
- spip->spi->PUSHR = SPIx_PUSHR_TXDATA(frame);
-
- while ((spip->spi->SR & SPIx_SR_RFDF) == 0)
- ;
-
- frame = spip->spi->POPR;
-
- spi_stop_xfer(spip);
-
- return frame;
-}
-
-#endif /* HAL_USE_SPI */
-
-/** @} */
diff --git a/os/hal/ports/KINETIS/K20x/hal_spi_lld.h b/os/hal/ports/KINETIS/K20x/hal_spi_lld.h deleted file mode 100644 index 0cf108e..0000000 --- a/os/hal/ports/KINETIS/K20x/hal_spi_lld.h +++ /dev/null @@ -1,261 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KINETIS/spi_lld.h
- * @brief KINETIS SPI subsystem low level driver header.
- *
- * @addtogroup SPI
- * @{
- */
-
-#ifndef HAL_SPI_LLD_H_
-#define HAL_SPI_LLD_H_
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief SPI0 driver enable switch.
- * @details If set to @p TRUE the support for SPI0 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(KINETIS_SPI_USE_SPI0) || defined(__DOXYGEN__)
-#define KINETIS_SPI_USE_SPI0 FALSE
-#endif
-
-/**
- * @brief SPI0 interrupt priority level setting.
- */
-#if !defined(KINETIS_SPI_SPI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_SPI_SPI0_IRQ_PRIORITY 10
-#endif
-
-/**
- * @brief SPI1 driver enable switch.
- * @details If set to @p TRUE the support for SPI0 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(KINETIS_SPI_USE_SPI1) || defined(__DOXYGEN__)
-#define KINETIS_SPI_USE_SPI1 FALSE
-#endif
-
-/**
- * @brief SPI1 interrupt priority level setting.
- */
-#if !defined(KINETIS_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_SPI_SPI1_IRQ_PRIORITY 10
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if KINETIS_SPI_USE_SPI0 && !KINETIS_HAS_SPI0
-#error "SPI0 not present in the selected device"
-#endif
-
-#if KINETIS_SPI_USE_SPI1 && !KINETIS_HAS_SPI1
-#error "SPI1 not present in the selected device"
-#endif
-
-#if KINETIS_SPI_USE_SPI0 && KINETIS_SPI_USE_SPI1
-#error "Only one SPI peripheral can be enabled"
-#endif
-
-#if !(KINETIS_SPI_USE_SPI0 || KINETIS_SPI_USE_SPI1)
-#error "SPI driver activated but no SPI peripheral assigned"
-#endif
-
-#if KINETIS_SPI_USE_SPI0 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_SPI_SPI0_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to SPI0"
-#endif
-
-#if KINETIS_SPI_USE_SPI1 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_SPI_SPI1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to SPI1"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Type of a structure representing an SPI driver.
- */
-typedef struct SPIDriver SPIDriver;
-
-/**
- * @brief SPI notification callback type.
- *
- * @param[in] spip pointer to the @p SPIDriver object triggering the
- * callback
- */
-typedef void (*spicallback_t)(SPIDriver *spip);
-
-/**
- * @brief Driver configuration structure.
- */
-typedef struct {
- /**
- * @brief Operation complete callback or @p NULL.
- */
- spicallback_t end_cb;
- /* End of the mandatory fields.*/
- /**
- * @brief The chip select line port - when not using pcs.
- */
- ioportid_t ssport;
- /**
- * @brief The chip select line pad number - when not using pcs.
- */
- uint16_t sspad;
- /**
- * @brief SPI initialization data.
- */
- uint32_t tar0;
-} SPIConfig;
-
-/**
- * @brief Structure representing a SPI driver.
- */
-struct SPIDriver {
- /**
- * @brief Driver state.
- */
- spistate_t state;
- /**
- * @brief Current configuration data.
- */
- const SPIConfig *config;
-#if SPI_USE_WAIT || defined(__DOXYGEN__)
- /**
- * @brief Waiting thread.
- */
- thread_reference_t thread;
-#endif /* SPI_USE_WAIT */
-#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
- /**
- * @brief Mutex protecting the bus.
- */
- mutex_t mutex;
-#endif /* SPI_USE_MUTUAL_EXCLUSION */
-#if defined(SPI_DRIVER_EXT_FIELDS)
- SPI_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the SPIx registers block.
- */
- SPI_TypeDef *spi;
- /**
- * @brief Number of bytes/words of data to transfer.
- */
- size_t count;
- /**
- * @brief Word size in bytes.
- */
- size_t word_size;
- /**
- * @brief Pointer to the buffer with data to send.
- */
- const uint8_t *txbuf;
- /**
- * @brief Pointer to the buffer to put received data.
- */
- uint8_t *rxbuf;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/* TAR settings for n bits at SYSCLK / 2 */
-#define KINETIS_SPI_TAR_SYSCLK_DIV_2(n)\
- SPIx_CTARn_FMSZ((n) - 1) | \
- SPIx_CTARn_CPOL | \
- SPIx_CTARn_CPHA | \
- SPIx_CTARn_DBR | \
- SPIx_CTARn_PBR(0) | \
- SPIx_CTARn_BR(0) | \
- SPIx_CTARn_CSSCK(0) | \
- SPIx_CTARn_ASC(0) | \
- SPIx_CTARn_DT(0)
-
-/* TAR settings for n bits at SYSCLK / 4096 for debugging */
-#define KINETIS_SPI_TAR_SYSCLK_DIV_4096(n) \
- SPIx_CTARn_FMSZ(((n) - 1)) | \
- SPIx_CTARn_CPOL | \
- SPIx_CTARn_CPHA | \
- SPIx_CTARn_PBR(0) | \
- SPIx_CTARn_BR(0xB) | \
- SPIx_CTARn_CSSCK(0xB) | \
- SPIx_CTARn_ASC(0x7) | \
- SPIx_CTARn_DT(0xB)
-
-#define KINETIS_SPI_TAR_8BIT_FAST KINETIS_SPI_TAR_SYSCLK_DIV_2(8)
-#define KINETIS_SPI_TAR_8BIT_SLOW KINETIS_SPI_TAR_SYSCLK_DIV_4096(8)
-
-#define KINETIS_SPI_TAR0_DEFAULT KINETIS_SPI_TAR_SYSCLK_DIV_2(8)
-#define KINETIS_SPI_TAR1_DEFAULT KINETIS_SPI_TAR_SYSCLK_DIV_2(8)
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if KINETIS_SPI_USE_SPI0 && !defined(__DOXYGEN__)
-extern SPIDriver SPID1;
-#endif
-
-#if KINETIS_SPI_USE_SPI1 && !defined(__DOXYGEN__)
-extern SPIDriver SPID2;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void spi_lld_init(void);
- void spi_lld_start(SPIDriver *spip);
- void spi_lld_stop(SPIDriver *spip);
- void spi_lld_select(SPIDriver *spip);
- void spi_lld_unselect(SPIDriver *spip);
- void spi_lld_ignore(SPIDriver *spip, size_t n);
- void spi_lld_exchange(SPIDriver *spip, size_t n,
- const void *txbuf, void *rxbuf);
- void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
- void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
- uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SPI */
-
-#endif /* HAL_SPI_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/ports/KINETIS/K20x/platform.mk b/os/hal/ports/KINETIS/K20x/platform.mk index beee336..537a6b6 100644 --- a/os/hal/ports/KINETIS/K20x/platform.mk +++ b/os/hal/ports/KINETIS/K20x/platform.mk @@ -1,18 +1,32 @@ -# List of all platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K20x/hal_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_pal_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_serial_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K20x/hal_spi_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_ext_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_adc_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_gpt_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K20x/hal_pwm_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_st_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
+PLATFORMSRC_CONTRIB := ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K20x/hal_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/PITv1/hal_st_lld.c
+
+PLATFORMINC_CONTRIB := ${CHIBIOS}/os/hal/ports/common/ARMCMx \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K20x
+
+ifeq ($(USE_SMART_BUILD),yes)
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K20x \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD
+# Configuration files directory
+ifeq ($(CONFDIR),)
+ CONFDIR = .
+endif
+
+HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define"))
+
+endif
+
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/GPIOv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/UARTv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/SPIv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/I2Cv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/PORTv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/ADCv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/PITv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/FTMv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/USBHSv1/driver.mk
+
+# Shared variables
+ALLCSRC += $(PLATFORMSRC_CONTRIB)
+ALLINC += $(PLATFORMINC_CONTRIB)
diff --git a/os/hal/ports/KINETIS/K60x/platform.mk b/os/hal/ports/KINETIS/K60x/platform.mk index 33ac2cc..1eb6cc5 100644 --- a/os/hal/ports/KINETIS/K60x/platform.mk +++ b/os/hal/ports/KINETIS/K60x/platform.mk @@ -1,19 +1,30 @@ -# List of all platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K60x/hal_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_pal_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_serial_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_ext_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_gpt_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_st_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_adc_lld.c \
-# ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K60x/hal_spi_lld.c \
-# ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K60x/hal_pwm_lld.c \
-# ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
+PLATFORMSRC_CONTRIB := ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K60x/hal_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/PITv1/hal_st_lld.c
+
+PLATFORMINC_CONTRIB := ${CHIBIOS}/os/hal/ports/common/ARMCMx \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K60x
+
+ifeq ($(USE_SMART_BUILD),yes)
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K60x \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD
+# Configuration files directory
+ifeq ($(CONFDIR),)
+ CONFDIR = .
+endif
+
+HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define"))
+
+endif
+
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/GPIOv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/UARTv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/PORTv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/PITv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/SDHCv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/I2Cv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/ADCv1/driver.mk
+
+# Shared variables
+ALLCSRC += $(PLATFORMSRC_CONTRIB)
+ALLINC += $(PLATFORMINC_CONTRIB)
diff --git a/os/hal/ports/KINETIS/KL2x/platform.mk b/os/hal/ports/KINETIS/KL2x/platform.mk index dda7a6d..9185022 100644 --- a/os/hal/ports/KINETIS/KL2x/platform.mk +++ b/os/hal/ports/KINETIS/KL2x/platform.mk @@ -1,17 +1,31 @@ -# List of all platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/KL2x/hal_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_pal_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_serial_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_ext_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_adc_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_gpt_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/KL2x/hal_pwm_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_st_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
+PLATFORMSRC_CONTRIB := ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/KL2x/hal_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/PITv1/hal_st_lld.c
+
+PLATFORMINC_CONTRIB := ${CHIBIOS}/os/hal/ports/common/ARMCMx \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/KL2x
+
+ifeq ($(USE_SMART_BUILD),yes)
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/KL2x \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD
+# Configuration files directory
+ifeq ($(CONFDIR),)
+ CONFDIR = .
+endif
+
+HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define"))
+
+endif
+
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/GPIOv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/UARTv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/I2Cv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/PORTv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/ADCv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/PITv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/TPMv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/USBHSv1/driver.mk
+
+# Shared variables
+ALLCSRC += $(PLATFORMSRC_CONTRIB)
+ALLINC += $(PLATFORMINC_CONTRIB)
diff --git a/os/hal/ports/KINETIS/LLD/ADCv1/driver.mk b/os/hal/ports/KINETIS/LLD/ADCv1/driver.mk new file mode 100644 index 0000000..5b5bcbb --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/ADCv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/ADCv1/hal_adc_lld.c +endif +else +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/ADCv1/hal_adc_lld.c +endif + +PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/ADCv1 diff --git a/os/hal/ports/KINETIS/LLD/hal_adc_lld.c b/os/hal/ports/KINETIS/LLD/ADCv1/hal_adc_lld.c index 56ae4c3..847f424 100644 --- a/os/hal/ports/KINETIS/LLD/hal_adc_lld.c +++ b/os/hal/ports/KINETIS/LLD/ADCv1/hal_adc_lld.c @@ -15,7 +15,7 @@ */
/**
- * @file KINETIS/LLD/adc_lld.c
+ * @file ADCv1/hal_adc_lld.c
* @brief KINETIS ADC subsystem low level driver source.
*
* @addtogroup ADC
@@ -104,9 +104,9 @@ OSAL_IRQ_HANDLER(KINETIS_ADC0_IRQ_VECTOR) { /* At the end of the buffer then we may be finished */
if (adcp->current_index == adcp->number_of_samples) {
- /* We are never finished in circular mode */ - more = ADCD1.grpp->circular; - + /* We are never finished in circular mode */
+ more = ADCD1.grpp->circular;
+
_adc_isr_full_code(&ADCD1);
adcp->current_index = 0;
diff --git a/os/hal/ports/KINETIS/LLD/hal_adc_lld.h b/os/hal/ports/KINETIS/LLD/ADCv1/hal_adc_lld.h index c4edbd6..2d11a7d 100644 --- a/os/hal/ports/KINETIS/LLD/hal_adc_lld.h +++ b/os/hal/ports/KINETIS/LLD/ADCv1/hal_adc_lld.h @@ -15,7 +15,7 @@ */
/**
- * @file KINETIS/LLD/adc_lld.h
+ * @file ADCv1/hal_adc_lld.h
* @brief KINETIS ADC subsystem low level driver header.
*
* @addtogroup ADC
diff --git a/os/hal/ports/KINETIS/LLD/FTMv1/driver.mk b/os/hal/ports/KINETIS/LLD/FTMv1/driver.mk new file mode 100644 index 0000000..d581c2e --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/FTMv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/FTMv1/hal_pwm_lld.c +endif +else +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/FTMv1/hal_pwm_lld.c +endif + +PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/FTMv1 diff --git a/os/hal/ports/KINETIS/K20x/hal_pwm_lld.c b/os/hal/ports/KINETIS/LLD/FTMv1/hal_pwm_lld.c index f5a8d96..8c1be78 100644 --- a/os/hal/ports/KINETIS/K20x/hal_pwm_lld.c +++ b/os/hal/ports/KINETIS/LLD/FTMv1/hal_pwm_lld.c @@ -1,390 +1,390 @@ -/*
- ChibiOS/HAL - Copyright (C) 2014 Adam J. Porter
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file K20x/pwm_lld.c
- * @brief KINETIS PWM subsystem low level driver source.
- *
- * @addtogroup PWM
- * @{
- */
-
-#include "hal.h"
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief PWMD1 driver identifier.
- * @note The driver PWMD1 allocates the timer FTM0 when enabled.
- */
-#if KINETIS_PWM_USE_FTM0 || defined(__DOXYGEN__)
-PWMDriver PWMD1;
-#endif
-
-/**
- * @brief PWMD2 driver identifier.
- * @note The driver PWMD2 allocates the timer FTM1 when enabled.
- */
-#if KINETIS_PWM_USE_FTM1 || defined(__DOXYGEN__)
-PWMDriver PWMD2;
-#endif
-
-/**
- * @brief PWMD3 driver identifier.
- * @note The driver PWMD3 allocates the timer FTM2 when enabled.
- */
-#if KINETIS_PWM_USE_FTM2 || defined(__DOXYGEN__)
-PWMDriver PWMD3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
- uint32_t sr;
-
- sr = pwmp->ftm->SC;
- pwmp->ftm->SC = sr&(~FTM_SC_TOF);
-
- if (((sr & FTM_SC_TOF) != 0) && /* Timer Overflow */
- ((sr & FTM_SC_TOIE) != 0) &&
- (pwmp->config->callback != NULL)) {
- pwmp->config->callback(pwmp);
- }
-
- uint8_t n=0;
- for(n=0;n<pwmp->channels;n++) {
- sr = pwmp->ftm->CHANNEL[n].CnSC;
- pwmp->ftm->CHANNEL[n].CnSC = sr&(~FTM_CnSC_CHF);
- if (((sr & FTM_CnSC_CHF) != 0) &&
- ((sr & FTM_CnSC_CHIE) != 0) &&
- (pwmp->config->channels[n].callback != NULL)) {
- pwmp->config->channels[n].callback(pwmp);
- }
- }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if KINETIS_PWM_USE_FTM0
-/**
- * @brief FTM0 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(KINETIS_FTM0_IRQ_VECTOR) {
- OSAL_IRQ_PROLOGUE();
- pwm_lld_serve_interrupt(&PWMD1);
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* KINETIS_PWM_USE_FTM0 */
-
-#if KINETIS_PWM_USE_FTM1
-/**
- * @brief FTM1 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(KINETIS_FTM1_IRQ_VECTOR) {
-
- OSAL_IRQ_PROLOGUE();
- pwm_lld_serve_interrupt(&PWMD2);
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* KINETIS_PWM_USE_FTM1 */
-
-#if KINETIS_PWM_USE_FTM2
-/**
- * @brief FTM2 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(KINETIS_FTM2_IRQ_VECTOR) {
-
- OSAL_IRQ_PROLOGUE();
- pwm_lld_serve_interrupt(&PWMD3);
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* KINETIS_PWM_USE_FTM2 */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level PWM driver initialization.
- *
- * @notapi
- */
-void pwm_lld_init(void) {
-
-#if KINETIS_PWM_USE_FTM0
- pwmObjectInit(&PWMD1);
- PWMD1.channels = KINETIS_FTM0_CHANNELS;
- PWMD1.ftm = FTM0;
-#endif
-
-#if KINETIS_PWM_USE_FTM1
- pwmObjectInit(&PWMD2);
- PWMD2.channels = KINETIS_FTM1_CHANNELS;
- PWMD2.ftm = FTM1;
-#endif
-
-#if KINETIS_PWM_USE_FTM2
- pwmObjectInit(&PWMD3);
- PWMD3.channels = KINETIS_FTM2_CHANNELS;
- PWMD3.ftm = FTM2;
-#endif
-}
-
-/**
- * @brief Configures and activates the PWM peripheral.
- * @note Starting a driver that is already in the @p PWM_READY state
- * disables all the active channels.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_start(PWMDriver *pwmp) {
- uint16_t psc;
- uint8_t i=0;
-
- if (pwmp->state == PWM_STOP) {
- /* Clock activation and timer reset.*/
-#if KINETIS_PWM_USE_FTM0
- if (&PWMD1 == pwmp) {
- SIM->SCGC6 |= SIM_SCGC6_FTM0;
- nvicEnableVector(FTM0_IRQn, KINETIS_PWM_FTM0_PRIORITY);
- }
-#endif
-
-#if KINETIS_PWM_USE_FTM1
- if (&PWMD2 == pwmp) {
- SIM->SCGC6 |= SIM_SCGC6_FTM1;
- nvicEnableVector(FTM1_IRQn, KINETIS_PWM_FTM1_PRIORITY);
- }
-#endif
-
-#if KINETIS_PWM_USE_FTM2
- if (&PWMD3 == pwmp) {
- SIM->SCGC3 |= SIM_SCGC3_FTM2;
- nvicEnableVector(FTM2_IRQn, KINETIS_PWM_FTM2_PRIORITY);
- }
-#endif
- }
- pwmp->ftm->MODE = FTM_MODE_FTMEN_MASK|FTM_MODE_PWMSYNC_MASK;
- pwmp->ftm->SYNC = FTM_SYNC_CNTMIN_MASK|FTM_SYNC_CNTMAX_MASK
- |FTM_SYNC_SWSYNC_MASK;
- pwmp->ftm->COMBINE = FTM_COMBINE_SYNCEN3_MASK | FTM_COMBINE_SYNCEN2_MASK
- | FTM_COMBINE_SYNCEN1_MASK | FTM_COMBINE_SYNCEN0_MASK;
- pwmp->ftm->SYNCONF = FTM_SYNCONF_SYNCMODE_MASK;
-
- pwmp->ftm->CNTIN = 0x0000;
- //~ pwmp->ftm->SC = 0; /* Disable FTM counter.*/
- pwmp->ftm->CNT = 0x0000; /* Clear count register.*/
-
- /* Prescaler value calculation.*/
- psc = (KINETIS_SYSCLK_FREQUENCY / pwmp->config->frequency);
- //~ /* Prescaler must be power of two between 1 and 128.*/
- osalDbgAssert(psc <= 128 && !(psc & (psc - 1)), "invalid frequency");
- //~ /* Prescaler register value determination.
- //~ Prescaler register value conveniently corresponds to bit position,
- //~ i.e., register value for prescaler CLK/64 is 6 ((1 << 6) == 64).*/
- for (i = 0; i < 8; i++) {
- if (psc == (unsigned)(1 << i)) {
- break;
- }
- }
-
- /* Set prescaler and clock mode.
- This also sets the following:
- CPWMS up-counting mode
- Timer overflow interrupt disabled
- DMA disabled.*/
- pwmp->ftm->SC = FTM_SC_CLKS(1) | FTM_SC_PS(i);
- /* Configure period */
- pwmp->ftm->MOD = pwmp->period-1;
- pwmp->ftm->PWMLOAD = FTM_PWMLOAD_LDOK_MASK;
-}
-
-/**
- * @brief Deactivates the PWM peripheral.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_stop(PWMDriver *pwmp) {
-
- /* If in ready state then disables the PWM clock.*/
- if (pwmp->state == PWM_READY) {
-#if KINETIS_PWM_USE_FTM0
- if (&PWMD1 == pwmp) {
- SIM->SCGC6 &= ~SIM_SCGC6_FTM0;
- nvicDisableVector(FTM0_IRQn);
- }
-#endif
-
-#if KINETIS_PWM_USE_FTM1
- if (&PWMD2 == pwmp) {
- SIM->SCGC6 &= ~SIM_SCGC6_FTM1;
- nvicDisableVector(FTM1_IRQn);
- }
-#endif
-
-#if KINETIS_PWM_USE_FTM2
- if (&PWMD3 == pwmp) {
- SIM->SCGC3 &= ~SIM_SCGC3_FTM2;
- nvicDisableVector(FTM2_IRQn);
- }
-#endif
- /* Disable FTM counter.*/
- pwmp->ftm->SC = 0;
- pwmp->ftm->MOD = 0;
- }
-}
-
-/**
- * @brief Enables a PWM channel.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The channel is active using the specified configuration.
- * @note The function has effect at the next cycle start.
- * @note Channel notification is not enabled.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...channels-1)
- * @param[in] width PWM pulse width as clock pulses number
- *
- * @notapi
- */
-void pwm_lld_enable_channel(PWMDriver *pwmp,
- pwmchannel_t channel,
- pwmcnt_t width) {
- uint32_t mode = FTM_CnSC_MSB; /* Edge-aligned PWM mode.*/
-
- switch (pwmp->config->channels[channel].mode & PWM_OUTPUT_MASK) {
- case PWM_OUTPUT_ACTIVE_HIGH:
- mode |= FTM_CnSC_ELSB;
- break;
- case PWM_OUTPUT_ACTIVE_LOW:
- mode |= FTM_CnSC_ELSA;
- break;
- }
-
- if (pwmp->ftm->CHANNEL[channel].CnSC & FTM_CnSC_CHIE)
- mode |= FTM_CnSC_CHIE;
-
- pwmp->ftm->CHANNEL[channel].CnSC = mode;
- pwmp->ftm->CHANNEL[channel].CnV = width;
- pwmp->ftm->PWMLOAD = FTM_PWMLOAD_LDOK_MASK;
-}
-
-/**
- * @brief Disables a PWM channel and its notification.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The channel is disabled and its output line returned to the
- * idle state.
- * @note The function has effect at the next cycle start.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...channels-1)
- *
- * @notapi
- */
-void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
-
- pwmp->ftm->CHANNEL[channel].CnSC = 0;
- pwmp->ftm->CHANNEL[channel].CnV = 0;
-}
-
-/**
- * @brief Enables the periodic activation edge notification.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @note If the notification is already enabled then the call has no effect.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) {
- pwmp->ftm->SC |= FTM_SC_TOIE;
-}
-
-/**
- * @brief Disables the periodic activation edge notification.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @note If the notification is already disabled then the call has no effect.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) {
- pwmp->ftm->SC &= ~FTM_SC_TOIE;
-}
-
-/**
- * @brief Enables a channel de-activation edge notification.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @pre The channel must have been activated using @p pwmEnableChannel().
- * @note If the notification is already enabled then the call has no effect.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...channels-1)
- *
- * @notapi
- */
-void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
- pwmchannel_t channel) {
- pwmp->ftm->CHANNEL[channel].CnSC |= FTM_CnSC_CHIE;
-}
-
-/**
- * @brief Disables a channel de-activation edge notification.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @pre The channel must have been activated using @p pwmEnableChannel().
- * @note If the notification is already disabled then the call has no effect.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...channels-1)
- *
- * @notapi
- */
-void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
- pwmchannel_t channel) {
- pwmp->ftm->CHANNEL[channel].CnSC &= ~FTM_CnSC_CHIE;
-}
-
-#endif /* HAL_USE_PWM */
-
-/** @} */
+/* + ChibiOS/HAL - Copyright (C) 2014 Adam J. Porter + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file K20x/pwm_lld.c + * @brief KINETIS PWM subsystem low level driver source. + * + * @addtogroup PWM + * @{ + */ + +#include "hal.h" + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief PWMD1 driver identifier. + * @note The driver PWMD1 allocates the timer FTM0 when enabled. + */ +#if KINETIS_PWM_USE_FTM0 || defined(__DOXYGEN__) +PWMDriver PWMD1; +#endif + +/** + * @brief PWMD2 driver identifier. + * @note The driver PWMD2 allocates the timer FTM1 when enabled. + */ +#if KINETIS_PWM_USE_FTM1 || defined(__DOXYGEN__) +PWMDriver PWMD2; +#endif + +/** + * @brief PWMD3 driver identifier. + * @note The driver PWMD3 allocates the timer FTM2 when enabled. + */ +#if KINETIS_PWM_USE_FTM2 || defined(__DOXYGEN__) +PWMDriver PWMD3; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void pwm_lld_serve_interrupt(PWMDriver *pwmp) { + uint32_t sr; + + sr = pwmp->ftm->SC; + pwmp->ftm->SC = sr&(~FTM_SC_TOF); + + if (((sr & FTM_SC_TOF) != 0) && /* Timer Overflow */ + ((sr & FTM_SC_TOIE) != 0) && + (pwmp->config->callback != NULL)) { + pwmp->config->callback(pwmp); + } + + uint8_t n=0; + for(n=0;n<pwmp->channels;n++) { + sr = pwmp->ftm->CHANNEL[n].CnSC; + pwmp->ftm->CHANNEL[n].CnSC = sr&(~FTM_CnSC_CHF); + if (((sr & FTM_CnSC_CHF) != 0) && + ((sr & FTM_CnSC_CHIE) != 0) && + (pwmp->config->channels[n].callback != NULL)) { + pwmp->config->channels[n].callback(pwmp); + } + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if KINETIS_PWM_USE_FTM0 +/** + * @brief FTM0 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(KINETIS_FTM0_IRQ_VECTOR) { + OSAL_IRQ_PROLOGUE(); + pwm_lld_serve_interrupt(&PWMD1); + OSAL_IRQ_EPILOGUE(); +} +#endif /* KINETIS_PWM_USE_FTM0 */ + +#if KINETIS_PWM_USE_FTM1 +/** + * @brief FTM1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(KINETIS_FTM1_IRQ_VECTOR) { + + OSAL_IRQ_PROLOGUE(); + pwm_lld_serve_interrupt(&PWMD2); + OSAL_IRQ_EPILOGUE(); +} +#endif /* KINETIS_PWM_USE_FTM1 */ + +#if KINETIS_PWM_USE_FTM2 +/** + * @brief FTM2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(KINETIS_FTM2_IRQ_VECTOR) { + + OSAL_IRQ_PROLOGUE(); + pwm_lld_serve_interrupt(&PWMD3); + OSAL_IRQ_EPILOGUE(); +} +#endif /* KINETIS_PWM_USE_FTM2 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level PWM driver initialization. + * + * @notapi + */ +void pwm_lld_init(void) { + +#if KINETIS_PWM_USE_FTM0 + pwmObjectInit(&PWMD1); + PWMD1.channels = KINETIS_FTM0_CHANNELS; + PWMD1.ftm = FTM0; +#endif + +#if KINETIS_PWM_USE_FTM1 + pwmObjectInit(&PWMD2); + PWMD2.channels = KINETIS_FTM1_CHANNELS; + PWMD2.ftm = FTM1; +#endif + +#if KINETIS_PWM_USE_FTM2 + pwmObjectInit(&PWMD3); + PWMD3.channels = KINETIS_FTM2_CHANNELS; + PWMD3.ftm = FTM2; +#endif +} + +/** + * @brief Configures and activates the PWM peripheral. + * @note Starting a driver that is already in the @p PWM_READY state + * disables all the active channels. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_start(PWMDriver *pwmp) { + uint16_t psc; + uint8_t i=0; + + if (pwmp->state == PWM_STOP) { + /* Clock activation and timer reset.*/ +#if KINETIS_PWM_USE_FTM0 + if (&PWMD1 == pwmp) { + SIM->SCGC6 |= SIM_SCGC6_FTM0; + nvicEnableVector(FTM0_IRQn, KINETIS_PWM_FTM0_PRIORITY); + } +#endif + +#if KINETIS_PWM_USE_FTM1 + if (&PWMD2 == pwmp) { + SIM->SCGC6 |= SIM_SCGC6_FTM1; + nvicEnableVector(FTM1_IRQn, KINETIS_PWM_FTM1_PRIORITY); + } +#endif + +#if KINETIS_PWM_USE_FTM2 + if (&PWMD3 == pwmp) { + SIM->SCGC3 |= SIM_SCGC3_FTM2; + nvicEnableVector(FTM2_IRQn, KINETIS_PWM_FTM2_PRIORITY); + } +#endif + } + pwmp->ftm->MODE = FTM_MODE_FTMEN_MASK|FTM_MODE_PWMSYNC_MASK; + pwmp->ftm->SYNC = FTM_SYNC_CNTMIN_MASK|FTM_SYNC_CNTMAX_MASK + |FTM_SYNC_SWSYNC_MASK; + pwmp->ftm->COMBINE = FTM_COMBINE_SYNCEN3_MASK | FTM_COMBINE_SYNCEN2_MASK + | FTM_COMBINE_SYNCEN1_MASK | FTM_COMBINE_SYNCEN0_MASK; + pwmp->ftm->SYNCONF = FTM_SYNCONF_SYNCMODE_MASK; + + pwmp->ftm->CNTIN = 0x0000; + //~ pwmp->ftm->SC = 0; /* Disable FTM counter.*/ + pwmp->ftm->CNT = 0x0000; /* Clear count register.*/ + + /* Prescaler value calculation.*/ + psc = (KINETIS_SYSCLK_FREQUENCY / pwmp->config->frequency); + //~ /* Prescaler must be power of two between 1 and 128.*/ + osalDbgAssert(psc <= 128 && !(psc & (psc - 1)), "invalid frequency"); + //~ /* Prescaler register value determination. + //~ Prescaler register value conveniently corresponds to bit position, + //~ i.e., register value for prescaler CLK/64 is 6 ((1 << 6) == 64).*/ + for (i = 0; i < 8; i++) { + if (psc == (unsigned)(1 << i)) { + break; + } + } + + /* Set prescaler and clock mode. + This also sets the following: + CPWMS up-counting mode + Timer overflow interrupt disabled + DMA disabled.*/ + pwmp->ftm->SC = FTM_SC_CLKS(1) | FTM_SC_PS(i); + /* Configure period */ + pwmp->ftm->MOD = pwmp->period-1; + pwmp->ftm->PWMLOAD = FTM_PWMLOAD_LDOK_MASK; +} + +/** + * @brief Deactivates the PWM peripheral. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_stop(PWMDriver *pwmp) { + + /* If in ready state then disables the PWM clock.*/ + if (pwmp->state == PWM_READY) { +#if KINETIS_PWM_USE_FTM0 + if (&PWMD1 == pwmp) { + SIM->SCGC6 &= ~SIM_SCGC6_FTM0; + nvicDisableVector(FTM0_IRQn); + } +#endif + +#if KINETIS_PWM_USE_FTM1 + if (&PWMD2 == pwmp) { + SIM->SCGC6 &= ~SIM_SCGC6_FTM1; + nvicDisableVector(FTM1_IRQn); + } +#endif + +#if KINETIS_PWM_USE_FTM2 + if (&PWMD3 == pwmp) { + SIM->SCGC3 &= ~SIM_SCGC3_FTM2; + nvicDisableVector(FTM2_IRQn); + } +#endif + /* Disable FTM counter.*/ + pwmp->ftm->SC = 0; + pwmp->ftm->MOD = 0; + } +} + +/** + * @brief Enables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is active using the specified configuration. + * @note The function has effect at the next cycle start. + * @note Channel notification is not enabled. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...channels-1) + * @param[in] width PWM pulse width as clock pulses number + * + * @notapi + */ +void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width) { + uint32_t mode = FTM_CnSC_MSB; /* Edge-aligned PWM mode.*/ + + switch (pwmp->config->channels[channel].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_HIGH: + mode |= FTM_CnSC_ELSB; + break; + case PWM_OUTPUT_ACTIVE_LOW: + mode |= FTM_CnSC_ELSA; + break; + } + + if (pwmp->ftm->CHANNEL[channel].CnSC & FTM_CnSC_CHIE) + mode |= FTM_CnSC_CHIE; + + pwmp->ftm->CHANNEL[channel].CnSC = mode; + pwmp->ftm->CHANNEL[channel].CnV = width; + pwmp->ftm->PWMLOAD = FTM_PWMLOAD_LDOK_MASK; +} + +/** + * @brief Disables a PWM channel and its notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is disabled and its output line returned to the + * idle state. + * @note The function has effect at the next cycle start. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...channels-1) + * + * @notapi + */ +void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { + + pwmp->ftm->CHANNEL[channel].CnSC = 0; + pwmp->ftm->CHANNEL[channel].CnV = 0; +} + +/** + * @brief Enables the periodic activation edge notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @note If the notification is already enabled then the call has no effect. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) { + pwmp->ftm->SC |= FTM_SC_TOIE; +} + +/** + * @brief Disables the periodic activation edge notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @note If the notification is already disabled then the call has no effect. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) { + pwmp->ftm->SC &= ~FTM_SC_TOIE; +} + +/** + * @brief Enables a channel de-activation edge notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @pre The channel must have been activated using @p pwmEnableChannel(). + * @note If the notification is already enabled then the call has no effect. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...channels-1) + * + * @notapi + */ +void pwm_lld_enable_channel_notification(PWMDriver *pwmp, + pwmchannel_t channel) { + pwmp->ftm->CHANNEL[channel].CnSC |= FTM_CnSC_CHIE; +} + +/** + * @brief Disables a channel de-activation edge notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @pre The channel must have been activated using @p pwmEnableChannel(). + * @note If the notification is already disabled then the call has no effect. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...channels-1) + * + * @notapi + */ +void pwm_lld_disable_channel_notification(PWMDriver *pwmp, + pwmchannel_t channel) { + pwmp->ftm->CHANNEL[channel].CnSC &= ~FTM_CnSC_CHIE; +} + +#endif /* HAL_USE_PWM */ + +/** @} */ diff --git a/os/hal/ports/KINETIS/K20x/hal_pwm_lld.h b/os/hal/ports/KINETIS/LLD/FTMv1/hal_pwm_lld.h index ccc100f..dd3b721 100644 --- a/os/hal/ports/KINETIS/K20x/hal_pwm_lld.h +++ b/os/hal/ports/KINETIS/LLD/FTMv1/hal_pwm_lld.h @@ -1,270 +1,270 @@ -/*
- ChibiOS/HAL - Copyright (C) 2014 Adam J. Porter
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file K20x7/pwm_lld.h
- * @brief KINETIS PWM subsystem low level driver header.
- *
- * @addtogroup PWM
- * @{
- */
-
-#ifndef HAL_PWM_LLD_H_
-#define HAL_PWM_LLD_H_
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @brief Number of PWM channels per PWM driver.
- */
-#define PWM_CHANNELS 8
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-#if !defined(KINETIS_PWM_USE_FTM0)
- #define KINETIS_PWM_USE_FTM0 FALSE
-#endif
-
-#if !defined(KINETIS_PWM_USE_FTM1)
- #define KINETIS_PWM_USE_FTM1 FALSE
-#endif
-
-#if !defined(KINETIS_PWM_USE_FTM2)
- #define KINETIS_PWM_USE_FTM2 FALSE
-#endif
-
-/**
- * @brief FTM0 interrupt priority level setting.
- */
-#if !defined(KINETIS_PWM_FTM0_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_PWM_FTM0_PRIORITY 12
-#endif
-
-/**
- * @brief FTM1 interrupt priority level setting.
- */
-#if !defined(KINETIS_PWM_FTM1_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_PWM_FTM1_PRIORITY 12
-#endif
-
-/**
- * @brief FTM2 interrupt priority level setting.
- */
-#if !defined(KINETIS_PWM_FTM2_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_PWM_FTM2_PRIORITY 12
-#endif
-
-/** @} */
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief If advanced timer features switch.
- * @details If set to @p TRUE the advanced features for TIM1 and TIM8 are
- * enabled.
- * @note The default is @p TRUE.
- */
-#if !defined(KINETIS_PWM_USE_ADVANCED) || defined(__DOXYGEN__)
-#define KINETIS_PWM_USE_ADVANCED FALSE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Configuration checks. */
-/*===========================================================================*/
-
-#if !KINETIS_PWM_USE_FTM0 && !KINETIS_PWM_USE_FTM1 && !KINETIS_PWM_USE_FTM2
-#error "PWM driver activated but no FTM peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Type of a PWM mode.
- */
-typedef uint32_t pwmmode_t;
-
-/**
- * @brief Type of a PWM channel.
- */
-typedef uint8_t pwmchannel_t;
-
-/**
- * @brief Type of a channels mask.
- */
-typedef uint32_t pwmchnmsk_t;
-
-/**
- * @brief Type of a PWM counter.
- */
-typedef uint16_t pwmcnt_t;
-
-/**
- * @brief Type of a PWM driver channel configuration structure.
- */
-typedef struct {
- /**
- * @brief Channel active logic level.
- */
- pwmmode_t mode;
-
- /**
- * @brief Channel callback pointer.
- * @note This callback is invoked on the channel compare event. If set to
- * @p NULL then the callback is disabled.
- */
- pwmcallback_t callback;
- /* End of the mandatory fields.*/
-} PWMChannelConfig;
-
-/**
- * @brief Type of a PWM driver configuration structure.
- */
-typedef struct {
- /**
- * @brief Timer clock in Hz.
- * @note The low level can use assertions in order to catch invalid
- * frequency specifications.
- */
- uint32_t frequency;
- /**
- * @brief PWM period in ticks.
- * @note The low level can use assertions in order to catch invalid
- * period specifications.
- */
- pwmcnt_t period;
- /**
- * @brief Periodic callback pointer.
- * @note This callback is invoked on PWM counter reset. If set to
- * @p NULL then the callback is disabled.
- */
- pwmcallback_t callback;
- /**
- * @brief Channels configurations.
- */
- PWMChannelConfig channels[PWM_CHANNELS];
- /* End of the mandatory fields.*/
-} PWMConfig;
-
-/**
- * @brief Structure representing a PWM driver.
- */
-struct PWMDriver {
- /**
- * @brief Driver state.
- */
- pwmstate_t state;
- /**
- * @brief Current driver configuration data.
- */
- const PWMConfig *config;
- /**
- * @brief Current PWM period in ticks.
- */
- pwmcnt_t period;
- /**
- * @brief Mask of the enabled channels.
- */
- pwmchnmsk_t enabled;
- /**
- * @brief Number of channels in this instance.
- */
- pwmchannel_t channels;
-#if defined(PWM_DRIVER_EXT_FIELDS)
- PWM_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the FTM registers block.
- */
- FTM_TypeDef *ftm;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @brief Changes the period the PWM peripheral.
- * @details This function changes the period of a PWM unit that has already
- * been activated using @p pwmStart().
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The PWM unit period is changed to the new value.
- * @note The function has effect at the next cycle start.
- * @note If a period is specified that is shorter than the pulse width
- * programmed in one of the channels then the behavior is not
- * guaranteed.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] period new cycle time in ticks
- *
- * @notapi
- */
-#define pwm_lld_change_period(pwmp, period) \
- do { \
- (pwmp)->ftm->MOD = ((period) - 1); \
- pwmp->ftm->PWMLOAD = FTM_PWMLOAD_LDOK_MASK;\
- } while(0)
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if KINETIS_PWM_USE_FTM0 || defined(__DOXYGEN__)
-extern PWMDriver PWMD1;
-#endif
-#if KINETIS_PWM_USE_FTM1 || defined(__DOXYGEN__)
-extern PWMDriver PWMD2;
-#endif
-#if KINETIS_PWM_USE_FTM2 || defined(__DOXYGEN__)
-extern PWMDriver PWMD3;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void pwm_lld_init(void);
- void pwm_lld_start(PWMDriver *pwmp);
- void pwm_lld_stop(PWMDriver *pwmp);
- void pwm_lld_enable_channel(PWMDriver *pwmp,
- pwmchannel_t channel,
- pwmcnt_t width);
- void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
- void pwm_lld_enable_periodic_notification(PWMDriver *pwmp);
- void pwm_lld_disable_periodic_notification(PWMDriver *pwmp);
- void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
- pwmchannel_t channel);
- void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
- pwmchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PWM */
-
-#endif /* HAL_PWM_LLD_H_ */
-
-/** @} */
+/* + ChibiOS/HAL - Copyright (C) 2014 Adam J. Porter + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file K20x7/pwm_lld.h + * @brief KINETIS PWM subsystem low level driver header. + * + * @addtogroup PWM + * @{ + */ + +#ifndef HAL_PWM_LLD_H_ +#define HAL_PWM_LLD_H_ + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Number of PWM channels per PWM driver. + */ +#define PWM_CHANNELS 8 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +#if !defined(KINETIS_PWM_USE_FTM0) + #define KINETIS_PWM_USE_FTM0 FALSE +#endif + +#if !defined(KINETIS_PWM_USE_FTM1) + #define KINETIS_PWM_USE_FTM1 FALSE +#endif + +#if !defined(KINETIS_PWM_USE_FTM2) + #define KINETIS_PWM_USE_FTM2 FALSE +#endif + +/** + * @brief FTM0 interrupt priority level setting. + */ +#if !defined(KINETIS_PWM_FTM0_PRIORITY) || defined(__DOXYGEN__) +#define KINETIS_PWM_FTM0_PRIORITY 12 +#endif + +/** + * @brief FTM1 interrupt priority level setting. + */ +#if !defined(KINETIS_PWM_FTM1_PRIORITY) || defined(__DOXYGEN__) +#define KINETIS_PWM_FTM1_PRIORITY 12 +#endif + +/** + * @brief FTM2 interrupt priority level setting. + */ +#if !defined(KINETIS_PWM_FTM2_PRIORITY) || defined(__DOXYGEN__) +#define KINETIS_PWM_FTM2_PRIORITY 12 +#endif + +/** @} */ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief If advanced timer features switch. + * @details If set to @p TRUE the advanced features for TIM1 and TIM8 are + * enabled. + * @note The default is @p TRUE. + */ +#if !defined(KINETIS_PWM_USE_ADVANCED) || defined(__DOXYGEN__) +#define KINETIS_PWM_USE_ADVANCED FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Configuration checks. */ +/*===========================================================================*/ + +#if !KINETIS_PWM_USE_FTM0 && !KINETIS_PWM_USE_FTM1 && !KINETIS_PWM_USE_FTM2 +#error "PWM driver activated but no FTM peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a PWM mode. + */ +typedef uint32_t pwmmode_t; + +/** + * @brief Type of a PWM channel. + */ +typedef uint8_t pwmchannel_t; + +/** + * @brief Type of a channels mask. + */ +typedef uint32_t pwmchnmsk_t; + +/** + * @brief Type of a PWM counter. + */ +typedef uint16_t pwmcnt_t; + +/** + * @brief Type of a PWM driver channel configuration structure. + */ +typedef struct { + /** + * @brief Channel active logic level. + */ + pwmmode_t mode; + + /** + * @brief Channel callback pointer. + * @note This callback is invoked on the channel compare event. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /* End of the mandatory fields.*/ +} PWMChannelConfig; + +/** + * @brief Type of a PWM driver configuration structure. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + uint32_t frequency; + /** + * @brief PWM period in ticks. + * @note The low level can use assertions in order to catch invalid + * period specifications. + */ + pwmcnt_t period; + /** + * @brief Periodic callback pointer. + * @note This callback is invoked on PWM counter reset. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /** + * @brief Channels configurations. + */ + PWMChannelConfig channels[PWM_CHANNELS]; + /* End of the mandatory fields.*/ +} PWMConfig; + +/** + * @brief Structure representing a PWM driver. + */ +struct PWMDriver { + /** + * @brief Driver state. + */ + pwmstate_t state; + /** + * @brief Current driver configuration data. + */ + const PWMConfig *config; + /** + * @brief Current PWM period in ticks. + */ + pwmcnt_t period; + /** + * @brief Mask of the enabled channels. + */ + pwmchnmsk_t enabled; + /** + * @brief Number of channels in this instance. + */ + pwmchannel_t channels; +#if defined(PWM_DRIVER_EXT_FIELDS) + PWM_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the FTM registers block. + */ + FTM_TypeDef *ftm; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Changes the period the PWM peripheral. + * @details This function changes the period of a PWM unit that has already + * been activated using @p pwmStart(). + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The PWM unit period is changed to the new value. + * @note The function has effect at the next cycle start. + * @note If a period is specified that is shorter than the pulse width + * programmed in one of the channels then the behavior is not + * guaranteed. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] period new cycle time in ticks + * + * @notapi + */ +#define pwm_lld_change_period(pwmp, period) \ + do { \ + (pwmp)->ftm->MOD = ((period) - 1); \ + pwmp->ftm->PWMLOAD = FTM_PWMLOAD_LDOK_MASK;\ + } while(0) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if KINETIS_PWM_USE_FTM0 || defined(__DOXYGEN__) +extern PWMDriver PWMD1; +#endif +#if KINETIS_PWM_USE_FTM1 || defined(__DOXYGEN__) +extern PWMDriver PWMD2; +#endif +#if KINETIS_PWM_USE_FTM2 || defined(__DOXYGEN__) +extern PWMDriver PWMD3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void pwm_lld_init(void); + void pwm_lld_start(PWMDriver *pwmp); + void pwm_lld_stop(PWMDriver *pwmp); + void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width); + void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel); + void pwm_lld_enable_periodic_notification(PWMDriver *pwmp); + void pwm_lld_disable_periodic_notification(PWMDriver *pwmp); + void pwm_lld_enable_channel_notification(PWMDriver *pwmp, + pwmchannel_t channel); + void pwm_lld_disable_channel_notification(PWMDriver *pwmp, + pwmchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PWM */ + +#endif /* HAL_PWM_LLD_H_ */ + +/** @} */ diff --git a/os/hal/ports/KINETIS/LLD/GPIOv1/driver.mk b/os/hal/ports/KINETIS/LLD/GPIOv1/driver.mk new file mode 100644 index 0000000..1e9aca0 --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/GPIOv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/GPIOv1/hal_pal_lld.c +endif +else +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/GPIOv1/hal_pal_lld.c +endif + +PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/GPIOv1 diff --git a/os/hal/ports/KINETIS/LLD/hal_pal_lld.c b/os/hal/ports/KINETIS/LLD/GPIOv1/hal_pal_lld.c index 51f8a2e..3cba308 100644 --- a/os/hal/ports/KINETIS/LLD/hal_pal_lld.c +++ b/os/hal/ports/KINETIS/LLD/GPIOv1/hal_pal_lld.c @@ -15,7 +15,7 @@ */
/**
- * @file KINETIS/LLD/pal_lld.c
+ * @file GPIOv1/hal_pal_lld.c
* @brief PAL subsystem low level driver.
*
* @addtogroup PAL
diff --git a/os/hal/ports/KINETIS/LLD/hal_pal_lld.h b/os/hal/ports/KINETIS/LLD/GPIOv1/hal_pal_lld.h index 833d95e..376c0a6 100644 --- a/os/hal/ports/KINETIS/LLD/hal_pal_lld.h +++ b/os/hal/ports/KINETIS/LLD/GPIOv1/hal_pal_lld.h @@ -15,7 +15,7 @@ */
/**
- * @file KINETIS/LLD/pal_lld.h
+ * @file GPIOv1/hal_pal_lld.h
* @brief PAL subsystem low level driver header.
*
* @addtogroup PAL
@@ -83,6 +83,11 @@ typedef uint32_t ioline_t; typedef GPIO_TypeDef *ioportid_t;
/**
+ * @brief Type of an pad identifier.
+ */
+typedef uint32_t iopadid_t;
+
+/**
* @brief Port Configuration.
* @details This structure stores the configuration parameters of all pads
* belonging to a port.
diff --git a/os/hal/ports/KINETIS/LLD/I2Cv1/driver.mk b/os/hal/ports/KINETIS/LLD/I2Cv1/driver.mk new file mode 100644 index 0000000..19658e5 --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/I2Cv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/I2Cv1/hal_i2c_lld.c +endif +else +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/I2Cv1/hal_i2c_lld.c +endif + +PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/I2Cv1 diff --git a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c b/os/hal/ports/KINETIS/LLD/I2Cv1/hal_i2c_lld.c index f615dd5..6bb9f44 100644 --- a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c +++ b/os/hal/ports/KINETIS/LLD/I2Cv1/hal_i2c_lld.c @@ -15,7 +15,7 @@ */
/**
- * @file KINETIS/LLD/i2c_lld.c
+ * @file I2Cv1/hal_i2c_lld.c
* @brief KINETIS I2C subsystem low level driver source.
*
* @addtogroup I2C
@@ -442,7 +442,9 @@ static inline msg_t _i2c_txrx_timeout(I2CDriver *i2cp, i2caddr_t addr, /* wait until the bus is released */
/* Calculating the time window for the timeout on the busy bus condition.*/
start = osalOsGetSystemTimeX();
-#if defined(OSAL_TIME_MS2I)
+#if defined(OSAL_MS2I)
+ end = start + OSAL_MS2I(KINETIS_I2C_BUSY_TIMEOUT);
+#elif defined(OSAL_TIME_MS2I)
end = start + OSAL_TIME_MS2I(KINETIS_I2C_BUSY_TIMEOUT);
#elif defined(OSAL_TIME_MS2ST)
end = start + OSAL_TIME_MS2ST(KINETIS_I2C_BUSY_TIMEOUT);
@@ -458,7 +460,7 @@ static inline msg_t _i2c_txrx_timeout(I2CDriver *i2cp, i2caddr_t addr, break;
/* If the system time went outside the allowed window then a timeout
condition is returned.*/
- if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end)) {
+ if (!osalTimeIsInRangeX(osalOsGetSystemTimeX(), start, end)) {
return MSG_TIMEOUT;
}
osalSysUnlock();
diff --git a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.h b/os/hal/ports/KINETIS/LLD/I2Cv1/hal_i2c_lld.h index bfc5008..e5c9974 100644 --- a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.h +++ b/os/hal/ports/KINETIS/LLD/I2Cv1/hal_i2c_lld.h @@ -15,7 +15,7 @@ */
/**
- * @file KINETIS/LLD/i2c_lld.h
+ * @file I2Cv1/hal_i2c_lld.h
* @brief KINETIS I2C subsystem low level driver header.
*
* @addtogroup I2C
diff --git a/os/hal/ports/KINETIS/LLD/PITv1/driver.mk b/os/hal/ports/KINETIS/LLD/PITv1/driver.mk new file mode 100644 index 0000000..065556b --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/PITv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/PITv1/hal_gpt_lld.c +endif +else +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/PITv1/hal_gpt_lld.c +endif + +PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/PITv1 diff --git a/os/hal/ports/KINETIS/LLD/hal_gpt_lld.c b/os/hal/ports/KINETIS/LLD/PITv1/hal_gpt_lld.c index 6e88f88..3669937 100644 --- a/os/hal/ports/KINETIS/LLD/hal_gpt_lld.c +++ b/os/hal/ports/KINETIS/LLD/PITv1/hal_gpt_lld.c @@ -15,7 +15,7 @@ */
/**
- * @file KINETIS/gpt_lld.c
+ * @file PITv1/hal_gpt_lld.c
* @brief KINETIS GPT subsystem low level driver source.
*
* @addtogroup GPT
diff --git a/os/hal/ports/KINETIS/LLD/hal_gpt_lld.h b/os/hal/ports/KINETIS/LLD/PITv1/hal_gpt_lld.h index 1b9e5ef..96c4c70 100644 --- a/os/hal/ports/KINETIS/LLD/hal_gpt_lld.h +++ b/os/hal/ports/KINETIS/LLD/PITv1/hal_gpt_lld.h @@ -15,7 +15,7 @@ */
/**
- * @file KINETIS/gpt_lld.h
+ * @file PITv1/hal_gpt_lld.h
* @brief KINETIS GPT subsystem low level driver header.
*
* @addtogroup GPT
diff --git a/os/hal/ports/KINETIS/LLD/hal_st_lld.c b/os/hal/ports/KINETIS/LLD/PITv1/hal_st_lld.c index e6ed9e5..5930b76 100644 --- a/os/hal/ports/KINETIS/LLD/hal_st_lld.c +++ b/os/hal/ports/KINETIS/LLD/PITv1/hal_st_lld.c @@ -15,7 +15,7 @@ */
/**
- * @file KINETIS/LLD/st_lld.c
+ * @file PITv1/hal_st_lld.c
* @brief ST Driver subsystem low level driver code.
*
* @addtogroup ST
diff --git a/os/hal/ports/KINETIS/LLD/hal_st_lld.h b/os/hal/ports/KINETIS/LLD/PITv1/hal_st_lld.h index 29c7035..0d75a54 100644 --- a/os/hal/ports/KINETIS/LLD/hal_st_lld.h +++ b/os/hal/ports/KINETIS/LLD/PITv1/hal_st_lld.h @@ -15,7 +15,7 @@ */
/**
- * @file KINETIS/LLD/st_lld.h
+ * @file PITv1/hal_st_lld.h
* @brief ST Driver subsystem low level driver header.
* @details This header is designed to be include-able without having to
* include other files from the HAL.
diff --git a/os/hal/ports/KINETIS/LLD/PORTv1/driver.mk b/os/hal/ports/KINETIS/LLD/PORTv1/driver.mk new file mode 100644 index 0000000..ca3b9df --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/PORTv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/PORTv1/hal_ext_lld.c +endif +else +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/PORTv1/hal_ext_lld.c +endif + +PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/PORTv1 diff --git a/os/hal/ports/KINETIS/LLD/hal_ext_lld.c b/os/hal/ports/KINETIS/LLD/PORTv1/hal_ext_lld.c index 21bb6e0..c678d6a 100644 --- a/os/hal/ports/KINETIS/LLD/hal_ext_lld.c +++ b/os/hal/ports/KINETIS/LLD/PORTv1/hal_ext_lld.c @@ -15,7 +15,7 @@ */
/**
- * @file KINETIS/LLD/ext_lld.c
+ * @file PORTv1/hal_ext_lld.c
* @brief KINETIS EXT subsystem low level driver source.
*
* @addtogroup EXT
diff --git a/os/hal/ports/KINETIS/LLD/hal_ext_lld.h b/os/hal/ports/KINETIS/LLD/PORTv1/hal_ext_lld.h index bcd9cb0..0b500a4 100644 --- a/os/hal/ports/KINETIS/LLD/hal_ext_lld.h +++ b/os/hal/ports/KINETIS/LLD/PORTv1/hal_ext_lld.h @@ -15,7 +15,7 @@ */
/**
- * @file KINETIS/LLD/ext_lld.h
+ * @file PORTv1/hal_ext_lld.h
* @brief KINETIS EXT subsystem low level driver header.
*
* @addtogroup EXT
diff --git a/os/hal/ports/KINETIS/LLD/SDHCv1/driver.mk b/os/hal/ports/KINETIS/LLD/SDHCv1/driver.mk new file mode 100644 index 0000000..69f27db --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/SDHCv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_SDC TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/SDHCv1/hal_sdc_lld.c +endif +else +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/SDHCv1/hal_sdc_lld.c +endif + +PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/SDHCv1 diff --git a/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c b/os/hal/ports/KINETIS/LLD/SDHCv1/hal_sdc_lld.c index 6ba932e..6d236eb 100644 --- a/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c +++ b/os/hal/ports/KINETIS/LLD/SDHCv1/hal_sdc_lld.c @@ -16,7 +16,7 @@ */
/**
- * @file hal_sdc_lld.c
+ * @file SDHCv1/hal_sdc_lld.h
* @brief Kinetis SDC subsystem low level driver.
*
* This driver provides a single SDC driver based on the Kinetis
diff --git a/os/hal/ports/KINETIS/LLD/hal_sdc_lld.h b/os/hal/ports/KINETIS/LLD/SDHCv1/hal_sdc_lld.h index 9f77bf6..cfa23cb 100644 --- a/os/hal/ports/KINETIS/LLD/hal_sdc_lld.h +++ b/os/hal/ports/KINETIS/LLD/SDHCv1/hal_sdc_lld.h @@ -16,7 +16,7 @@ */
/**
- * @file hal_sdc_lld.h
+ * @file SDHCv1/hal_sdc_lld.h
* @brief PLATFORM SDC subsystem low level driver header.
*
* @addtogroup SDC
diff --git a/os/hal/ports/KINETIS/LLD/SPIv1/driver.mk b/os/hal/ports/KINETIS/LLD/SPIv1/driver.mk new file mode 100644 index 0000000..394b40a --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/SPIv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/SPIv1/hal_spi_lld.c +endif +else +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/SPIv1/hal_spi_lld.c +endif + +PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/SPIv1 diff --git a/os/hal/ports/KINETIS/MK66F18/hal_spi_lld.c b/os/hal/ports/KINETIS/LLD/SPIv1/hal_spi_lld.c index 29ab4e8..7e643f2 100644 --- a/os/hal/ports/KINETIS/MK66F18/hal_spi_lld.c +++ b/os/hal/ports/KINETIS/LLD/SPIv1/hal_spi_lld.c @@ -1,539 +1,539 @@ -/*
- ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KINETIS/spi_lld.c
- * @brief KINETIS SPI subsystem low level driver source.
- *
- * @addtogroup SPI
- * @{
- */
-
-#include "hal.h"
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-#if !defined(KINETIS_SPI0_RX_DMA_IRQ_PRIORITY)
-#define KINETIS_SPI0_RX_DMA_IRQ_PRIORITY 8
-#endif
-
-#if !defined(KINETIS_SPI0_RX_DMAMUX_CHANNEL)
-#define KINETIS_SPI0_RX_DMAMUX_CHANNEL 0
-#endif
-
-#if !defined(KINETIS_SPI0_RX_DMA_CHANNEL)
-#define KINETIS_SPI0_RX_DMA_CHANNEL 0
-#endif
-
-#if !defined(KINETIS_SPI0_TX_DMAMUX_CHANNEL)
-#define KINETIS_SPI0_TX_DMAMUX_CHANNEL 1
-#endif
-
-#if !defined(KINETIS_SPI0_TX_DMA_CHANNEL)
-#define KINETIS_SPI0_TX_DMA_CHANNEL 1
-#endif
-
-#if !defined(KINETIS_SPI1_RX_DMA_IRQ_PRIORITY)
-#define KINETIS_SPI1_RX_DMA_IRQ_PRIORITY 8
-#endif
-
-#if !defined(KINETIS_SPI1_RX_DMAMUX_CHANNEL)
-#define KINETIS_SPI1_RX_DMAMUX_CHANNEL 0
-#endif
-
-#if !defined(KINETIS_SPI1_RX_DMA_CHANNEL)
-#define KINETIS_SPI1_RX_DMA_CHANNEL 0
-#endif
-
-#if !defined(KINETIS_SPI1_TX_DMAMUX_CHANNEL)
-#define KINETIS_SPI1_TX_DMAMUX_CHANNEL 1
-#endif
-
-#if !defined(KINETIS_SPI1_TX_DMA_CHANNEL)
-#define KINETIS_SPI1_TX_DMA_CHANNEL 1
-#endif
-
-#if KINETIS_SPI_USE_SPI0
-#define DMAMUX_SPI_RX_SOURCE 16
-#define DMAMUX_SPI_TX_SOURCE 17
-#endif
-
-#if KINETIS_SPI_USE_SPI1
-#define DMAMUX_SPI_RX_SOURCE 18
-#define DMAMUX_SPI_TX_SOURCE 19
-#endif
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/** @brief SPI0 driver identifier.*/
-#if KINETIS_SPI_USE_SPI0 || defined(__DOXYGEN__)
-SPIDriver SPID1;
-#endif
-
-/** @brief SPI1 driver identifier.*/
-#if KINETIS_SPI_USE_SPI1 || defined(__DOXYGEN__)
-SPIDriver SPID2;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/* Use a dummy byte as the source/destination when a buffer is not provided */
-/* Note: The MMC driver relies on 0xFF being sent for dummy bytes. */
-static volatile uint16_t dmaRxDummy;
-static uint16_t dmaTxDummy = 0xFFFF;
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-static void spi_start_xfer(SPIDriver *spip, bool polling)
-{
- /*
- * Enable the DSPI peripheral in master mode.
- * Clear the TX and RX FIFOs.
- * */
- spip->spi->MCR = SPIx_MCR_MSTR | SPIx_MCR_CLR_TXF | SPIx_MCR_CLR_RXF;
-
- /* If we are not polling then enable DMA */
- if (!polling) {
-
- /* Enable receive dma and transmit dma */
- spip->spi->RSER = SPIx_RSER_RFDF_DIRS | SPIx_RSER_RFDF_RE |
- SPIx_RSER_TFFF_RE | SPIx_RSER_TFFF_DIRS;
-
- /* Configure RX DMA */
- if (spip->rxbuf) {
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DADDR = (uint32_t)spip->rxbuf;
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DOFF = spip->word_size;
- } else {
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DADDR = (uint32_t)&dmaRxDummy;
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DOFF = 0;
- }
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].BITER_ELINKNO = spip->count;
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].CITER_ELINKNO = spip->count;
-
- /* Enable Request Register (ERQ) for RX by writing 0 to SERQ */
- DMA->SERQ = KINETIS_SPI0_RX_DMA_CHANNEL;
-
- /* Configure TX DMA */
- if (spip->txbuf) {
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SADDR = (uint32_t)spip->txbuf;
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SOFF = spip->word_size;
- } else {
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SADDR = (uint32_t)&dmaTxDummy;
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SOFF = 0;
- }
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].BITER_ELINKNO = spip->count;
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].CITER_ELINKNO = spip->count;
-
- /* Enable Request Register (ERQ) for TX by writing 1 to SERQ */
- DMA->SERQ = KINETIS_SPI0_TX_DMA_CHANNEL;
- }
-}
-
-static void spi_stop_xfer(SPIDriver *spip)
-{
- /* Halt the DSPI peripheral */
- spip->spi->MCR = SPIx_MCR_MSTR | SPIx_MCR_HALT;
-
- /* Clear all the flags which are currently set. */
- spip->spi->SR |= spip->spi->SR;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if KINETIS_SPI_USE_SPI0 || defined(__DOXYGEN__)
-
-OSAL_IRQ_HANDLER(KINETIS_DMA0_IRQ_VECTOR) {
- OSAL_IRQ_PROLOGUE();
-
- /* Clear bit 0 in Interrupt Request Register (INT) by writing 0 to CINT */
- DMA->CINT = KINETIS_SPI0_RX_DMA_CHANNEL;
-
- spi_stop_xfer(&SPID1);
-
- _spi_isr_code(&SPID1);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-#endif
-
-#if KINETIS_SPI_USE_SPI1 || defined(__DOXYGEN__)
-
-OSAL_IRQ_HANDLER(KINETIS_DMA0_IRQ_VECTOR) {
- OSAL_IRQ_PROLOGUE();
-
- /* Clear bit 0 in Interrupt Request Register (INT) by writing 0 to CINT */
- DMA->CINT = KINETIS_SPI1_RX_DMA_CHANNEL;
-
- spi_stop_xfer(&SPID2);
-
- _spi_isr_code(&SPID2);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level SPI driver initialization.
- *
- * @notapi
- */
-void spi_lld_init(void) {
-#if KINETIS_SPI_USE_SPI0
- spiObjectInit(&SPID1);
-#endif
-#if KINETIS_SPI_USE_SPI1
- spiObjectInit(&SPID2);
-#endif
-}
-
-/**
- * @brief Configures and activates the SPI peripheral.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_start(SPIDriver *spip) {
-
- /* If in stopped state then enables the SPI and DMA clocks.*/
- if (spip->state == SPI_STOP) {
-
-#if KINETIS_SPI_USE_SPI0
- if (&SPID1 == spip) {
-
- /* Enable the clock for SPI0 */
- SIM->SCGC6 |= SIM_SCGC6_SPI0;
-
- SPID1.spi = SPI0;
-
- if (spip->config->tar0) {
- spip->spi->CTAR[0] = spip->config->tar0;
- } else {
- spip->spi->CTAR[0] = KINETIS_SPI_TAR0_DEFAULT;
- }
- }
-#endif
-
-#if KINETIS_SPI_USE_SPI1
- if (&SPID2 == spip) {
-
- /* Enable the clock for SPI0 */
- SIM->SCGC6 |= SIM_SCGC6_SPI1;
-
- SPID2.spi = SPI1;
-
- if (spip->config->tar0) {
- spip->spi->CTAR[0] = spip->config->tar0;
- } else {
- spip->spi->CTAR[0] = KINETIS_SPI_TAR0_DEFAULT;
- }
- }
-#endif
-
- nvicEnableVector(DMA0_IRQn, KINETIS_SPI0_RX_DMA_IRQ_PRIORITY);
-
- SIM->SCGC6 |= SIM_SCGC6_DMAMUX;
- SIM->SCGC7 |= SIM_SCGC7_DMA;
-
- /* Clear DMA error flags */
- DMA->ERR = 0x0F;
-
-#if KINETIS_SPI_USE_SPI0
- /* Rx, select SPI Rx FIFO */
- DMAMUX->CHCFG[KINETIS_SPI0_RX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
- DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_RX_SOURCE);
-
- /* Tx, select SPI Tx FIFO */
- DMAMUX->CHCFG[KINETIS_SPI0_TX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
- DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_TX_SOURCE);
-
- /* Extract the frame size from the TAR */
- uint16_t frame_size = ((spip->spi->CTAR[0] >> SPIx_CTARn_FMSZ_SHIFT) &
- SPIx_CTARn_FMSZ_MASK) + 1;
-
- /* DMA transfer size is 16 bits for a frame size > 8 bits */
- uint16_t dma_size = frame_size > 8 ? 1 : 0;
-
- /* DMA word size is 2 for a 16 bit frame size */
- spip->word_size = frame_size > 8 ? 2 : 1;
-
- /* configure DMA RX fixed values */
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].SADDR = (uint32_t)&SPI0->POPR;
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].SOFF = 0;
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].SLAST = 0;
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DLASTSGA = 0;
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
- DMA_ATTR_DSIZE(dma_size);
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK |
- DMA_CSR_INTMAJOR_MASK;
-
- /* configure DMA TX fixed values */
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SLAST = 0;
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].DADDR = (uint32_t)&SPI0->PUSHR;
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].DOFF = 0;
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].DLASTSGA = 0;
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
- DMA_ATTR_DSIZE(dma_size);
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK;
-#endif
-
-#if KINETIS_SPI_USE_SPI1
- /* Rx, select SPI Rx FIFO */
- DMAMUX->CHCFG[KINETIS_SPI1_RX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
- DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_RX_SOURCE);
-
- /* Tx, select SPI Tx FIFO */
- DMAMUX->CHCFG[KINETIS_SPI1_TX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
- DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_TX_SOURCE);
-
- /* Extract the frame size from the TAR */
- uint16_t frame_size = ((spip->spi->CTAR[0] >> SPIx_CTARn_FMSZ_SHIFT) &
- SPIx_CTARn_FMSZ_MASK) + 1;
-
- /* DMA transfer size is 16 bits for a frame size > 8 bits */
- uint16_t dma_size = frame_size > 8 ? 1 : 0;
-
- /* DMA word size is 2 for a 16 bit frame size */
- spip->word_size = frame_size > 8 ? 2 : 1;
-
- /* configure DMA RX fixed values */
- DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].SADDR = (uint32_t)&SPI1->POPR;
- DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].SOFF = 0;
- DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].SLAST = 0;
- DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].DLASTSGA = 0;
- DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
- DMA_ATTR_DSIZE(dma_size);
- DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
- DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK |
- DMA_CSR_INTMAJOR_MASK;
-
- /* configure DMA TX fixed values */
- DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].SLAST = 0;
- DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].DADDR = (uint32_t)&SPI1->PUSHR;
- DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].DOFF = 0;
- DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].DLASTSGA = 0;
- DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
- DMA_ATTR_DSIZE(dma_size);
- DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
- DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK;
-#endif
- }
-}
-
-/**
- * @brief Deactivates the SPI peripheral.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_stop(SPIDriver *spip) {
-
- /* If in ready state then disables the SPI clock.*/
- if (spip->state == SPI_READY) {
-
- nvicDisableVector(DMA0_IRQn);
-
- SIM->SCGC7 &= ~SIM_SCGC7_DMA;
- SIM->SCGC6 &= ~SIM_SCGC6_DMAMUX;
-
-#if KINETIS_SPI_USE_SPI0
- if (&SPID1 == spip) {
- /* SPI halt.*/
- spip->spi->MCR |= SPIx_MCR_HALT;
- }
-
- /* Disable the clock for SPI0 */
- SIM->SCGC6 &= ~SIM_SCGC6_SPI0;
-#endif
-
-#if KINETIS_SPI_USE_SPI1
- if (&SPID2 == spip) {
- /* SPI halt.*/
- spip->spi->MCR |= SPIx_MCR_HALT;
- }
-
- /* Disable the clock for SPI1 */
- SIM->SCGC6 &= ~SIM_SCGC6_SPI1;
-#endif
- }
-}
-
-/**
- * @brief Asserts the slave select signal and prepares for transfers.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_select(SPIDriver *spip) {
-
- palClearPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief Deasserts the slave select signal.
- * @details The previously selected peripheral is unselected.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_unselect(SPIDriver *spip) {
-
- palSetPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief Ignores data on the SPI bus.
- * @details This asynchronous function starts the transmission of a series of
- * idle words on the SPI bus and ignores the received data.
- * @post At the end of the operation the configured callback is invoked.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be ignored
- *
- * @notapi
- */
-void spi_lld_ignore(SPIDriver *spip, size_t n) {
-
- spip->count = n;
- spip->rxbuf = NULL;
- spip->txbuf = NULL;
-
- spi_start_xfer(spip, false);
-}
-
-/**
- * @brief Exchanges data on the SPI bus.
- * @details This asynchronous function starts a simultaneous transmit/receive
- * operation.
- * @post At the end of the operation the configured callback is invoked.
- * @note The buffers are organized as uint8_t arrays for data sizes below or
- * equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be exchanged
- * @param[in] txbuf the pointer to the transmit buffer
- * @param[out] rxbuf the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_exchange(SPIDriver *spip, size_t n,
- const void *txbuf, void *rxbuf) {
-
- spip->count = n;
- spip->rxbuf = rxbuf;
- spip->txbuf = txbuf;
-
- spi_start_xfer(spip, false);
-}
-
-/**
- * @brief Sends data over the SPI bus.
- * @details This asynchronous function starts a transmit operation.
- * @post At the end of the operation the configured callback is invoked.
- * @note The buffers are organized as uint8_t arrays for data sizes below or
- * equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to send
- * @param[in] txbuf the pointer to the transmit buffer
- *
- * @notapi
- */
-void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
-
- spip->count = n;
- spip->rxbuf = NULL;
- spip->txbuf = (void *)txbuf;
-
- spi_start_xfer(spip, false);
-}
-
-/**
- * @brief Receives data from the SPI bus.
- * @details This asynchronous function starts a receive operation.
- * @post At the end of the operation the configured callback is invoked.
- * @note The buffers are organized as uint8_t arrays for data sizes below or
- * equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to receive
- * @param[out] rxbuf the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
-
- spip->count = n;
- spip->rxbuf = rxbuf;
- spip->txbuf = NULL;
-
- spi_start_xfer(spip, false);
-}
-
-/**
- * @brief Exchanges one frame using a polled wait.
- * @details This synchronous function exchanges one frame using a polled
- * synchronization method. This function is useful when exchanging
- * small amount of data on high speed channels, usually in this
- * situation is much more efficient just wait for completion using
- * polling than suspending the thread waiting for an interrupt.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] frame the data frame to send over the SPI bus
- * @return The received data frame from the SPI bus.
- */
-uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
-
- spi_start_xfer(spip, true);
-
- spip->spi->PUSHR = SPIx_PUSHR_TXDATA(frame);
-
- while ((spip->spi->SR & SPIx_SR_RFDF) == 0)
- ;
-
- frame = spip->spi->POPR;
-
- spi_stop_xfer(spip);
-
- return frame;
-}
-
-#endif /* HAL_USE_SPI */
-
-/** @} */
+/* + ChibiOS - Copyright (C) 2014-2015 Fabio Utzig + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPIv1/hal_spi_lld.c + * @brief KINETIS SPI subsystem low level driver source. + * + * @addtogroup SPI + * @{ + */ + +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#if !defined(KINETIS_SPI0_RX_DMA_IRQ_PRIORITY) +#define KINETIS_SPI0_RX_DMA_IRQ_PRIORITY 8 +#endif + +#if !defined(KINETIS_SPI0_RX_DMAMUX_CHANNEL) +#define KINETIS_SPI0_RX_DMAMUX_CHANNEL 0 +#endif + +#if !defined(KINETIS_SPI0_RX_DMA_CHANNEL) +#define KINETIS_SPI0_RX_DMA_CHANNEL 0 +#endif + +#if !defined(KINETIS_SPI0_TX_DMAMUX_CHANNEL) +#define KINETIS_SPI0_TX_DMAMUX_CHANNEL 1 +#endif + +#if !defined(KINETIS_SPI0_TX_DMA_CHANNEL) +#define KINETIS_SPI0_TX_DMA_CHANNEL 1 +#endif + +#if !defined(KINETIS_SPI1_RX_DMA_IRQ_PRIORITY) +#define KINETIS_SPI1_RX_DMA_IRQ_PRIORITY 8 +#endif + +#if !defined(KINETIS_SPI1_RX_DMAMUX_CHANNEL) +#define KINETIS_SPI1_RX_DMAMUX_CHANNEL 0 +#endif + +#if !defined(KINETIS_SPI1_RX_DMA_CHANNEL) +#define KINETIS_SPI1_RX_DMA_CHANNEL 0 +#endif + +#if !defined(KINETIS_SPI1_TX_DMAMUX_CHANNEL) +#define KINETIS_SPI1_TX_DMAMUX_CHANNEL 1 +#endif + +#if !defined(KINETIS_SPI1_TX_DMA_CHANNEL) +#define KINETIS_SPI1_TX_DMA_CHANNEL 1 +#endif + +#if KINETIS_SPI_USE_SPI0 +#define DMAMUX_SPI_RX_SOURCE 16 +#define DMAMUX_SPI_TX_SOURCE 17 +#endif + +#if KINETIS_SPI_USE_SPI1 +#define DMAMUX_SPI_RX_SOURCE 18 +#define DMAMUX_SPI_TX_SOURCE 19 +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief SPI0 driver identifier.*/ +#if KINETIS_SPI_USE_SPI0 || defined(__DOXYGEN__) +SPIDriver SPID1; +#endif + +/** @brief SPI1 driver identifier.*/ +#if KINETIS_SPI_USE_SPI1 || defined(__DOXYGEN__) +SPIDriver SPID2; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/* Use a dummy byte as the source/destination when a buffer is not provided */ +/* Note: The MMC driver relies on 0xFF being sent for dummy bytes. */ +static volatile uint16_t dmaRxDummy; +static uint16_t dmaTxDummy = 0xFFFF; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void spi_start_xfer(SPIDriver *spip, bool polling) +{ + /* + * Enable the DSPI peripheral in master mode. + * Clear the TX and RX FIFOs. + * */ + spip->spi->MCR = SPIx_MCR_MSTR | SPIx_MCR_CLR_TXF | SPIx_MCR_CLR_RXF; + + /* If we are not polling then enable DMA */ + if (!polling) { + + /* Enable receive dma and transmit dma */ + spip->spi->RSER = SPIx_RSER_RFDF_DIRS | SPIx_RSER_RFDF_RE | + SPIx_RSER_TFFF_RE | SPIx_RSER_TFFF_DIRS; + + /* Configure RX DMA */ + if (spip->rxbuf) { + DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DADDR = (uint32_t)spip->rxbuf; + DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DOFF = spip->word_size; + } else { + DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DADDR = (uint32_t)&dmaRxDummy; + DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DOFF = 0; + } + DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].BITER_ELINKNO = spip->count; + DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].CITER_ELINKNO = spip->count; + + /* Enable Request Register (ERQ) for RX by writing 0 to SERQ */ + DMA->SERQ = KINETIS_SPI0_RX_DMA_CHANNEL; + + /* Configure TX DMA */ + if (spip->txbuf) { + DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SADDR = (uint32_t)spip->txbuf; + DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SOFF = spip->word_size; + } else { + DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SADDR = (uint32_t)&dmaTxDummy; + DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SOFF = 0; + } + DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].BITER_ELINKNO = spip->count; + DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].CITER_ELINKNO = spip->count; + + /* Enable Request Register (ERQ) for TX by writing 1 to SERQ */ + DMA->SERQ = KINETIS_SPI0_TX_DMA_CHANNEL; + } +} + +static void spi_stop_xfer(SPIDriver *spip) +{ + /* Halt the DSPI peripheral */ + spip->spi->MCR = SPIx_MCR_MSTR | SPIx_MCR_HALT; + + /* Clear all the flags which are currently set. */ + spip->spi->SR |= spip->spi->SR; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if KINETIS_SPI_USE_SPI0 || defined(__DOXYGEN__) + +OSAL_IRQ_HANDLER(KINETIS_DMA0_IRQ_VECTOR) { + OSAL_IRQ_PROLOGUE(); + + /* Clear bit 0 in Interrupt Request Register (INT) by writing 0 to CINT */ + DMA->CINT = KINETIS_SPI0_RX_DMA_CHANNEL; + + spi_stop_xfer(&SPID1); + + _spi_isr_code(&SPID1); + + OSAL_IRQ_EPILOGUE(); +} + +#endif + +#if KINETIS_SPI_USE_SPI1 || defined(__DOXYGEN__) + +OSAL_IRQ_HANDLER(KINETIS_DMA0_IRQ_VECTOR) { + OSAL_IRQ_PROLOGUE(); + + /* Clear bit 0 in Interrupt Request Register (INT) by writing 0 to CINT */ + DMA->CINT = KINETIS_SPI1_RX_DMA_CHANNEL; + + spi_stop_xfer(&SPID2); + + _spi_isr_code(&SPID2); + + OSAL_IRQ_EPILOGUE(); +} + +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { +#if KINETIS_SPI_USE_SPI0 + spiObjectInit(&SPID1); +#endif +#if KINETIS_SPI_USE_SPI1 + spiObjectInit(&SPID2); +#endif +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) { + + /* If in stopped state then enables the SPI and DMA clocks.*/ + if (spip->state == SPI_STOP) { + +#if KINETIS_SPI_USE_SPI0 + if (&SPID1 == spip) { + + /* Enable the clock for SPI0 */ + SIM->SCGC6 |= SIM_SCGC6_SPI0; + + SPID1.spi = SPI0; + + if (spip->config->tar0) { + spip->spi->CTAR[0] = spip->config->tar0; + } else { + spip->spi->CTAR[0] = KINETIS_SPI_TAR0_DEFAULT; + } + } +#endif + +#if KINETIS_SPI_USE_SPI1 + if (&SPID2 == spip) { + + /* Enable the clock for SPI0 */ + SIM->SCGC6 |= SIM_SCGC6_SPI1; + + SPID2.spi = SPI1; + + if (spip->config->tar0) { + spip->spi->CTAR[0] = spip->config->tar0; + } else { + spip->spi->CTAR[0] = KINETIS_SPI_TAR0_DEFAULT; + } + } +#endif + + nvicEnableVector(DMA0_IRQn, KINETIS_SPI0_RX_DMA_IRQ_PRIORITY); + + SIM->SCGC6 |= SIM_SCGC6_DMAMUX; + SIM->SCGC7 |= SIM_SCGC7_DMA; + + /* Clear DMA error flags */ + DMA->ERR = 0x0F; + +#if KINETIS_SPI_USE_SPI0 + /* Rx, select SPI Rx FIFO */ + DMAMUX->CHCFG[KINETIS_SPI0_RX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL | + DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_RX_SOURCE); + + /* Tx, select SPI Tx FIFO */ + DMAMUX->CHCFG[KINETIS_SPI0_TX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL | + DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_TX_SOURCE); + + /* Extract the frame size from the TAR */ + uint16_t frame_size = ((spip->spi->CTAR[0] >> SPIx_CTARn_FMSZ_SHIFT) & + SPIx_CTARn_FMSZ_MASK) + 1; + + /* DMA transfer size is 16 bits for a frame size > 8 bits */ + uint16_t dma_size = frame_size > 8 ? 1 : 0; + + /* DMA word size is 2 for a 16 bit frame size */ + spip->word_size = frame_size > 8 ? 2 : 1; + + /* configure DMA RX fixed values */ + DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].SADDR = (uint32_t)&SPI0->POPR; + DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].SOFF = 0; + DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].SLAST = 0; + DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DLASTSGA = 0; + DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) | + DMA_ATTR_DSIZE(dma_size); + DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size; + DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK | + DMA_CSR_INTMAJOR_MASK; + + /* configure DMA TX fixed values */ + DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SLAST = 0; + DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].DADDR = (uint32_t)&SPI0->PUSHR; + DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].DOFF = 0; + DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].DLASTSGA = 0; + DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) | + DMA_ATTR_DSIZE(dma_size); + DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size; + DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK; +#endif + +#if KINETIS_SPI_USE_SPI1 + /* Rx, select SPI Rx FIFO */ + DMAMUX->CHCFG[KINETIS_SPI1_RX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL | + DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_RX_SOURCE); + + /* Tx, select SPI Tx FIFO */ + DMAMUX->CHCFG[KINETIS_SPI1_TX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL | + DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_TX_SOURCE); + + /* Extract the frame size from the TAR */ + uint16_t frame_size = ((spip->spi->CTAR[0] >> SPIx_CTARn_FMSZ_SHIFT) & + SPIx_CTARn_FMSZ_MASK) + 1; + + /* DMA transfer size is 16 bits for a frame size > 8 bits */ + uint16_t dma_size = frame_size > 8 ? 1 : 0; + + /* DMA word size is 2 for a 16 bit frame size */ + spip->word_size = frame_size > 8 ? 2 : 1; + + /* configure DMA RX fixed values */ + DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].SADDR = (uint32_t)&SPI1->POPR; + DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].SOFF = 0; + DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].SLAST = 0; + DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].DLASTSGA = 0; + DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) | + DMA_ATTR_DSIZE(dma_size); + DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size; + DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK | + DMA_CSR_INTMAJOR_MASK; + + /* configure DMA TX fixed values */ + DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].SLAST = 0; + DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].DADDR = (uint32_t)&SPI1->PUSHR; + DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].DOFF = 0; + DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].DLASTSGA = 0; + DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) | + DMA_ATTR_DSIZE(dma_size); + DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size; + DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK; +#endif + } +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) { + + /* If in ready state then disables the SPI clock.*/ + if (spip->state == SPI_READY) { + + nvicDisableVector(DMA0_IRQn); + + SIM->SCGC7 &= ~SIM_SCGC7_DMA; + SIM->SCGC6 &= ~SIM_SCGC6_DMAMUX; + +#if KINETIS_SPI_USE_SPI0 + if (&SPID1 == spip) { + /* SPI halt.*/ + spip->spi->MCR |= SPIx_MCR_HALT; + } + + /* Disable the clock for SPI0 */ + SIM->SCGC6 &= ~SIM_SCGC6_SPI0; +#endif + +#if KINETIS_SPI_USE_SPI1 + if (&SPID2 == spip) { + /* SPI halt.*/ + spip->spi->MCR |= SPIx_MCR_HALT; + } + + /* Disable the clock for SPI1 */ + SIM->SCGC6 &= ~SIM_SCGC6_SPI1; +#endif + } +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) { + + palClearPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) { + + palSetPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Ignores data on the SPI bus. + * @details This asynchronous function starts the transmission of a series of + * idle words on the SPI bus and ignores the received data. + * @post At the end of the operation the configured callback is invoked. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) { + + spip->count = n; + spip->rxbuf = NULL; + spip->txbuf = NULL; + + spi_start_xfer(spip, false); +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + spip->count = n; + spip->rxbuf = rxbuf; + spip->txbuf = txbuf; + + spi_start_xfer(spip, false); +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { + + spip->count = n; + spip->rxbuf = NULL; + spip->txbuf = (void *)txbuf; + + spi_start_xfer(spip, false); +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { + + spip->count = n; + spip->rxbuf = rxbuf; + spip->txbuf = NULL; + + spi_start_xfer(spip, false); +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { + + spi_start_xfer(spip, true); + + spip->spi->PUSHR = SPIx_PUSHR_TXDATA(frame); + + while ((spip->spi->SR & SPIx_SR_RFDF) == 0) + ; + + frame = spip->spi->POPR; + + spi_stop_xfer(spip); + + return frame; +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/os/hal/ports/KINETIS/MK66F18/hal_spi_lld.h b/os/hal/ports/KINETIS/LLD/SPIv1/hal_spi_lld.h index 0cf108e..d25dd75 100644 --- a/os/hal/ports/KINETIS/MK66F18/hal_spi_lld.h +++ b/os/hal/ports/KINETIS/LLD/SPIv1/hal_spi_lld.h @@ -1,261 +1,261 @@ -/*
- ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KINETIS/spi_lld.h
- * @brief KINETIS SPI subsystem low level driver header.
- *
- * @addtogroup SPI
- * @{
- */
-
-#ifndef HAL_SPI_LLD_H_
-#define HAL_SPI_LLD_H_
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief SPI0 driver enable switch.
- * @details If set to @p TRUE the support for SPI0 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(KINETIS_SPI_USE_SPI0) || defined(__DOXYGEN__)
-#define KINETIS_SPI_USE_SPI0 FALSE
-#endif
-
-/**
- * @brief SPI0 interrupt priority level setting.
- */
-#if !defined(KINETIS_SPI_SPI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_SPI_SPI0_IRQ_PRIORITY 10
-#endif
-
-/**
- * @brief SPI1 driver enable switch.
- * @details If set to @p TRUE the support for SPI0 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(KINETIS_SPI_USE_SPI1) || defined(__DOXYGEN__)
-#define KINETIS_SPI_USE_SPI1 FALSE
-#endif
-
-/**
- * @brief SPI1 interrupt priority level setting.
- */
-#if !defined(KINETIS_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_SPI_SPI1_IRQ_PRIORITY 10
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if KINETIS_SPI_USE_SPI0 && !KINETIS_HAS_SPI0
-#error "SPI0 not present in the selected device"
-#endif
-
-#if KINETIS_SPI_USE_SPI1 && !KINETIS_HAS_SPI1
-#error "SPI1 not present in the selected device"
-#endif
-
-#if KINETIS_SPI_USE_SPI0 && KINETIS_SPI_USE_SPI1
-#error "Only one SPI peripheral can be enabled"
-#endif
-
-#if !(KINETIS_SPI_USE_SPI0 || KINETIS_SPI_USE_SPI1)
-#error "SPI driver activated but no SPI peripheral assigned"
-#endif
-
-#if KINETIS_SPI_USE_SPI0 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_SPI_SPI0_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to SPI0"
-#endif
-
-#if KINETIS_SPI_USE_SPI1 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_SPI_SPI1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to SPI1"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Type of a structure representing an SPI driver.
- */
-typedef struct SPIDriver SPIDriver;
-
-/**
- * @brief SPI notification callback type.
- *
- * @param[in] spip pointer to the @p SPIDriver object triggering the
- * callback
- */
-typedef void (*spicallback_t)(SPIDriver *spip);
-
-/**
- * @brief Driver configuration structure.
- */
-typedef struct {
- /**
- * @brief Operation complete callback or @p NULL.
- */
- spicallback_t end_cb;
- /* End of the mandatory fields.*/
- /**
- * @brief The chip select line port - when not using pcs.
- */
- ioportid_t ssport;
- /**
- * @brief The chip select line pad number - when not using pcs.
- */
- uint16_t sspad;
- /**
- * @brief SPI initialization data.
- */
- uint32_t tar0;
-} SPIConfig;
-
-/**
- * @brief Structure representing a SPI driver.
- */
-struct SPIDriver {
- /**
- * @brief Driver state.
- */
- spistate_t state;
- /**
- * @brief Current configuration data.
- */
- const SPIConfig *config;
-#if SPI_USE_WAIT || defined(__DOXYGEN__)
- /**
- * @brief Waiting thread.
- */
- thread_reference_t thread;
-#endif /* SPI_USE_WAIT */
-#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
- /**
- * @brief Mutex protecting the bus.
- */
- mutex_t mutex;
-#endif /* SPI_USE_MUTUAL_EXCLUSION */
-#if defined(SPI_DRIVER_EXT_FIELDS)
- SPI_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the SPIx registers block.
- */
- SPI_TypeDef *spi;
- /**
- * @brief Number of bytes/words of data to transfer.
- */
- size_t count;
- /**
- * @brief Word size in bytes.
- */
- size_t word_size;
- /**
- * @brief Pointer to the buffer with data to send.
- */
- const uint8_t *txbuf;
- /**
- * @brief Pointer to the buffer to put received data.
- */
- uint8_t *rxbuf;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/* TAR settings for n bits at SYSCLK / 2 */
-#define KINETIS_SPI_TAR_SYSCLK_DIV_2(n)\
- SPIx_CTARn_FMSZ((n) - 1) | \
- SPIx_CTARn_CPOL | \
- SPIx_CTARn_CPHA | \
- SPIx_CTARn_DBR | \
- SPIx_CTARn_PBR(0) | \
- SPIx_CTARn_BR(0) | \
- SPIx_CTARn_CSSCK(0) | \
- SPIx_CTARn_ASC(0) | \
- SPIx_CTARn_DT(0)
-
-/* TAR settings for n bits at SYSCLK / 4096 for debugging */
-#define KINETIS_SPI_TAR_SYSCLK_DIV_4096(n) \
- SPIx_CTARn_FMSZ(((n) - 1)) | \
- SPIx_CTARn_CPOL | \
- SPIx_CTARn_CPHA | \
- SPIx_CTARn_PBR(0) | \
- SPIx_CTARn_BR(0xB) | \
- SPIx_CTARn_CSSCK(0xB) | \
- SPIx_CTARn_ASC(0x7) | \
- SPIx_CTARn_DT(0xB)
-
-#define KINETIS_SPI_TAR_8BIT_FAST KINETIS_SPI_TAR_SYSCLK_DIV_2(8)
-#define KINETIS_SPI_TAR_8BIT_SLOW KINETIS_SPI_TAR_SYSCLK_DIV_4096(8)
-
-#define KINETIS_SPI_TAR0_DEFAULT KINETIS_SPI_TAR_SYSCLK_DIV_2(8)
-#define KINETIS_SPI_TAR1_DEFAULT KINETIS_SPI_TAR_SYSCLK_DIV_2(8)
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if KINETIS_SPI_USE_SPI0 && !defined(__DOXYGEN__)
-extern SPIDriver SPID1;
-#endif
-
-#if KINETIS_SPI_USE_SPI1 && !defined(__DOXYGEN__)
-extern SPIDriver SPID2;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void spi_lld_init(void);
- void spi_lld_start(SPIDriver *spip);
- void spi_lld_stop(SPIDriver *spip);
- void spi_lld_select(SPIDriver *spip);
- void spi_lld_unselect(SPIDriver *spip);
- void spi_lld_ignore(SPIDriver *spip, size_t n);
- void spi_lld_exchange(SPIDriver *spip, size_t n,
- const void *txbuf, void *rxbuf);
- void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
- void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
- uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SPI */
-
-#endif /* HAL_SPI_LLD_H_ */
-
-/** @} */
+/* + ChibiOS - Copyright (C) 2014-2015 Fabio Utzig + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPIv1/hal_spi_lld.h + * @brief KINETIS SPI subsystem low level driver header. + * + * @addtogroup SPI + * @{ + */ + +#ifndef HAL_SPI_LLD_H_ +#define HAL_SPI_LLD_H_ + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief SPI0 driver enable switch. + * @details If set to @p TRUE the support for SPI0 is included. + * @note The default is @p FALSE. + */ +#if !defined(KINETIS_SPI_USE_SPI0) || defined(__DOXYGEN__) +#define KINETIS_SPI_USE_SPI0 FALSE +#endif + +/** + * @brief SPI0 interrupt priority level setting. + */ +#if !defined(KINETIS_SPI_SPI0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define KINETIS_SPI_SPI0_IRQ_PRIORITY 10 +#endif + +/** + * @brief SPI1 driver enable switch. + * @details If set to @p TRUE the support for SPI0 is included. + * @note The default is @p FALSE. + */ +#if !defined(KINETIS_SPI_USE_SPI1) || defined(__DOXYGEN__) +#define KINETIS_SPI_USE_SPI1 FALSE +#endif + +/** + * @brief SPI1 interrupt priority level setting. + */ +#if !defined(KINETIS_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define KINETIS_SPI_SPI1_IRQ_PRIORITY 10 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if KINETIS_SPI_USE_SPI0 && !KINETIS_HAS_SPI0 +#error "SPI0 not present in the selected device" +#endif + +#if KINETIS_SPI_USE_SPI1 && !KINETIS_HAS_SPI1 +#error "SPI1 not present in the selected device" +#endif + +#if KINETIS_SPI_USE_SPI0 && KINETIS_SPI_USE_SPI1 +#error "Only one SPI peripheral can be enabled" +#endif + +#if !(KINETIS_SPI_USE_SPI0 || KINETIS_SPI_USE_SPI1) +#error "SPI driver activated but no SPI peripheral assigned" +#endif + +#if KINETIS_SPI_USE_SPI0 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_SPI_SPI0_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SPI0" +#endif + +#if KINETIS_SPI_USE_SPI1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_SPI_SPI1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SPI1" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SPI driver. + */ +typedef struct SPIDriver SPIDriver; + +/** + * @brief SPI notification callback type. + * + * @param[in] spip pointer to the @p SPIDriver object triggering the + * callback + */ +typedef void (*spicallback_t)(SPIDriver *spip); + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief Operation complete callback or @p NULL. + */ + spicallback_t end_cb; + /* End of the mandatory fields.*/ + /** + * @brief The chip select line port - when not using pcs. + */ + ioportid_t ssport; + /** + * @brief The chip select line pad number - when not using pcs. + */ + uint16_t sspad; + /** + * @brief SPI initialization data. + */ + uint32_t tar0; +} SPIConfig; + +/** + * @brief Structure representing a SPI driver. + */ +struct SPIDriver { + /** + * @brief Driver state. + */ + spistate_t state; + /** + * @brief Current configuration data. + */ + const SPIConfig *config; +#if SPI_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + thread_reference_t thread; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + mutex_t mutex; +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_FIELDS) + SPI_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the SPIx registers block. + */ + SPI_TypeDef *spi; + /** + * @brief Number of bytes/words of data to transfer. + */ + size_t count; + /** + * @brief Word size in bytes. + */ + size_t word_size; + /** + * @brief Pointer to the buffer with data to send. + */ + const uint8_t *txbuf; + /** + * @brief Pointer to the buffer to put received data. + */ + uint8_t *rxbuf; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/* TAR settings for n bits at SYSCLK / 2 */ +#define KINETIS_SPI_TAR_SYSCLK_DIV_2(n)\ + SPIx_CTARn_FMSZ((n) - 1) | \ + SPIx_CTARn_CPOL | \ + SPIx_CTARn_CPHA | \ + SPIx_CTARn_DBR | \ + SPIx_CTARn_PBR(0) | \ + SPIx_CTARn_BR(0) | \ + SPIx_CTARn_CSSCK(0) | \ + SPIx_CTARn_ASC(0) | \ + SPIx_CTARn_DT(0) + +/* TAR settings for n bits at SYSCLK / 4096 for debugging */ +#define KINETIS_SPI_TAR_SYSCLK_DIV_4096(n) \ + SPIx_CTARn_FMSZ(((n) - 1)) | \ + SPIx_CTARn_CPOL | \ + SPIx_CTARn_CPHA | \ + SPIx_CTARn_PBR(0) | \ + SPIx_CTARn_BR(0xB) | \ + SPIx_CTARn_CSSCK(0xB) | \ + SPIx_CTARn_ASC(0x7) | \ + SPIx_CTARn_DT(0xB) + +#define KINETIS_SPI_TAR_8BIT_FAST KINETIS_SPI_TAR_SYSCLK_DIV_2(8) +#define KINETIS_SPI_TAR_8BIT_SLOW KINETIS_SPI_TAR_SYSCLK_DIV_4096(8) + +#define KINETIS_SPI_TAR0_DEFAULT KINETIS_SPI_TAR_SYSCLK_DIV_2(8) +#define KINETIS_SPI_TAR1_DEFAULT KINETIS_SPI_TAR_SYSCLK_DIV_2(8) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if KINETIS_SPI_USE_SPI0 && !defined(__DOXYGEN__) +extern SPIDriver SPID1; +#endif + +#if KINETIS_SPI_USE_SPI1 && !defined(__DOXYGEN__) +extern SPIDriver SPID2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); + uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* HAL_SPI_LLD_H_ */ + +/** @} */ diff --git a/os/hal/ports/KINETIS/LLD/TPMv1/driver.mk b/os/hal/ports/KINETIS/LLD/TPMv1/driver.mk new file mode 100644 index 0000000..d4a0eef --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/TPMv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/TPMv1/hal_pwm_lld.c +endif +else +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/TPMv1/hal_pwm_lld.c +endif + +PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/TPMv1 diff --git a/os/hal/ports/KINETIS/KL2x/hal_pwm_lld.c b/os/hal/ports/KINETIS/LLD/TPMv1/hal_pwm_lld.c index 2f56216..a5eb46a 100644 --- a/os/hal/ports/KINETIS/KL2x/hal_pwm_lld.c +++ b/os/hal/ports/KINETIS/LLD/TPMv1/hal_pwm_lld.c @@ -1,388 +1,388 @@ -/*
- ChibiOS - Copyright (C) 2014 Adam J. Porter
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KL2x/pwm_lld.c
- * @brief KINETIS PWM subsystem low level driver source.
- *
- * @addtogroup PWM
- * @{
- */
-
-#include "hal.h"
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief PWMD1 driver identifier.
- * @note The driver PWMD1 allocates the timer TPM0 when enabled.
- */
-#if KINETIS_PWM_USE_TPM0 || defined(__DOXYGEN__)
-PWMDriver PWMD1;
-#endif
-
-/**
- * @brief PWMD2 driver identifier.
- * @note The driver PWMD2 allocates the timer TPM1 when enabled.
- */
-#if KINETIS_PWM_USE_TPM1 || defined(__DOXYGEN__)
-PWMDriver PWMD2;
-#endif
-
-/**
- * @brief PWMD3 driver identifier.
- * @note The driver PWMD3 allocates the timer TPM2 when enabled.
- */
-#if KINETIS_PWM_USE_TPM2 || defined(__DOXYGEN__)
-PWMDriver PWMD3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
- uint32_t sr;
-
- sr = pwmp->tpm->STATUS;
- pwmp->tpm->STATUS = 0xFFFFFFFF;
-
- if (((sr & TPMx_STATUS_TOF) != 0) &&
- (pwmp->config->callback != NULL))
- pwmp->config->callback(pwmp);
- if (((sr & TPMx_STATUS_CH0F) != 0) &&
- (pwmp->config->channels[0].callback != NULL))
- pwmp->config->channels[0].callback(pwmp);
- if (((sr & TPMx_STATUS_CH1F) != 0) &&
- (pwmp->config->channels[1].callback != NULL))
- pwmp->config->channels[1].callback(pwmp);
- if (((sr & TPMx_STATUS_CH2F) != 0) &&
- (pwmp->config->channels[2].callback != NULL))
- pwmp->config->channels[2].callback(pwmp);
- if (((sr & TPMx_STATUS_CH3F) != 0) &&
- (pwmp->config->channels[3].callback != NULL))
- pwmp->config->channels[3].callback(pwmp);
- if (((sr & TPMx_STATUS_CH4F) != 0) &&
- (pwmp->config->channels[4].callback != NULL))
- pwmp->config->channels[4].callback(pwmp);
- if (((sr & TPMx_STATUS_CH5F) != 0) &&
- (pwmp->config->channels[5].callback != NULL))
- pwmp->config->channels[5].callback(pwmp);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if KINETIS_PWM_USE_TPM0
-/**
- * @brief TPM0 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(KINETIS_TPM0_IRQ_VECTOR) {
-
- OSAL_IRQ_PROLOGUE();
- pwm_lld_serve_interrupt(&PWMD1);
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* KINETIS_PWM_USE_TPM0 */
-
-#if KINETIS_PWM_USE_TPM1
-/**
- * @brief TPM1 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(KINETIS_TPM1_IRQ_VECTOR) {
-
- OSAL_IRQ_PROLOGUE();
- pwm_lld_serve_interrupt(&PWMD2);
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* KINETIS_PWM_USE_TPM1 */
-
-#if KINETIS_PWM_USE_TPM2
-/**
- * @brief TPM2 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(KINETIS_TPM2_IRQ_VECTOR) {
-
- OSAL_IRQ_PROLOGUE();
- pwm_lld_serve_interrupt(&PWMD3);
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* KINETIS_PWM_USE_TPM2 */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level PWM driver initialization.
- *
- * @notapi
- */
-void pwm_lld_init(void) {
-
-#if KINETIS_PWM_USE_TPM0
- pwmObjectInit(&PWMD1);
- PWMD1.channels = KINETIS_TPM0_CHANNELS;
- PWMD1.tpm = TPM0;
-#endif
-
-#if KINETIS_PWM_USE_TPM1
- pwmObjectInit(&PWMD2);
- PWMD2.channels = KINETIS_TPM1_CHANNELS;
- PWMD2.tpm = TPM1;
-#endif
-
-#if KINETIS_PWM_USE_TPM2
- pwmObjectInit(&PWMD3);
- PWMD3.channels = KINETIS_TPM2_CHANNELS;
- PWMD3.tpm = TPM2;
-#endif
-}
-
-/**
- * @brief Configures and activates the PWM peripheral.
- * @note Starting a driver that is already in the @p PWM_READY state
- * disables all the active channels.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_start(PWMDriver *pwmp) {
- uint32_t psc;
- int i;
-
- if (pwmp->state == PWM_STOP) {
- /* Clock activation and timer reset.*/
-#if KINETIS_PWM_USE_TPM0
- if (&PWMD1 == pwmp) {
- SIM->SCGC6 |= SIM_SCGC6_TPM0;
- nvicEnableVector(TPM0_IRQn, KINETIS_PWM_TPM0_IRQ_PRIORITY);
- }
-#endif
-
-#if KINETIS_PWM_USE_TPM1
- if (&PWMD2 == pwmp) {
- SIM->SCGC6 |= SIM_SCGC6_TPM1;
- nvicEnableVector(TPM1_IRQn, KINETIS_PWM_TPM1_IRQ_PRIORITY);
- }
-#endif
-
-#if KINETIS_PWM_USE_TPM2
- if (&PWMD3 == pwmp) {
- SIM->SCGC6 |= SIM_SCGC6_TPM2;
- nvicEnableVector(TPM2_IRQn, KINETIS_PWM_TPM2_IRQ_PRIORITY);
- }
-#endif
- }
-
- /* Disable LPTPM counter.*/
- pwmp->tpm->SC = 0;
- /* Clear count register.*/
- pwmp->tpm->CNT = 0;
-
- /* Prescaler value calculation.*/
- psc = (KINETIS_SYSCLK_FREQUENCY / pwmp->config->frequency);
- /* Prescaler must be power of two between 1 and 128.*/
- osalDbgAssert(psc <= 128 && !(psc & (psc - 1)), "invalid frequency");
- /* Prescaler register value determination.
- Prescaler register value conveniently corresponds to bit position,
- i.e., register value for prescaler CLK/64 is 6 ((1 << 6) == 64).*/
- for (i = 0; i < 8; i++) {
- if (psc == (1UL << i)) {
- break;
- }
- }
- /* Set prescaler and clock mode.
- This also sets the following:
- CPWM up-counting mode
- Timer overflow interrupt disabled
- DMA disabled.*/
- pwmp->tpm->SC = TPMx_SC_CMOD_LPTPM_CLK | i;
- /* Configure period.*/
- pwmp->tpm->MOD = pwmp->period - 1;
-}
-
-/**
- * @brief Deactivates the PWM peripheral.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_stop(PWMDriver *pwmp) {
-
- /* If in ready state then disables the PWM clock.*/
- if (pwmp->state == PWM_READY) {
-#if KINETIS_PWM_USE_TPM0
- if (&PWMD1 == pwmp) {
- SIM->SCGC6 &= ~SIM_SCGC6_TPM0;
- nvicDisableVector(TPM0_IRQn);
- }
-#endif
-
-#if KINETIS_PWM_USE_TPM1
- if (&PWMD2 == pwmp) {
- SIM->SCGC6 &= ~SIM_SCGC6_TPM1;
- nvicDisableVector(TPM1_IRQn);
- }
-#endif
-
-#if KINETIS_PWM_USE_TPM2
- if (&PWMD3 == pwmp) {
- SIM->SCGC6 &= ~SIM_SCGC6_TPM2;
- nvicDisableVector(TPM2_IRQn);
- }
-#endif
- /* Disable LPTPM counter.*/
- pwmp->tpm->SC = 0;
- pwmp->tpm->MOD = 0;
- }
-}
-
-
-/**
- * @brief Enables a PWM channel.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The channel is active using the specified configuration.
- * @note The function has effect at the next cycle start.
- * @note Channel notification is not enabled.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...channels-1)
- * @param[in] width PWM pulse width as clock pulses number
- *
- * @notapi
- */
-void pwm_lld_enable_channel(PWMDriver *pwmp,
- pwmchannel_t channel,
- pwmcnt_t width) {
- uint32_t mode = TPMx_CnSC_MSB; /* Edge-aligned PWM mode.*/
-
- switch (pwmp->config->channels[channel].mode & PWM_OUTPUT_MASK) {
- case PWM_OUTPUT_ACTIVE_HIGH:
- mode |= TPMx_CnSC_ELSB;
- break;
- case PWM_OUTPUT_ACTIVE_LOW:
- mode |= TPMx_CnSC_ELSA;
- break;
- }
-
- if (pwmp->tpm->C[channel].SC & TPMx_CnSC_CHIE)
- mode |= TPMx_CnSC_CHIE;
-
- pwmp->tpm->C[channel].SC = mode;
- pwmp->tpm->C[channel].V = width;
-}
-
-/**
- * @brief Disables a PWM channel and its notification.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The channel is disabled and its output line returned to the
- * idle state.
- * @note The function has effect at the next cycle start.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...channels-1)
- *
- * @notapi
- */
-void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
-
- pwmp->tpm->C[channel].SC = 0;
- pwmp->tpm->C[channel].V = 0;
-}
-
-/**
- * @brief Enables the periodic activation edge notification.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @note If the notification is already enabled then the call has no effect.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) {
-
- pwmp->tpm->SC |= TPMx_SC_TOIE;
-}
-
-/**
- * @brief Disables the periodic activation edge notification.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @note If the notification is already disabled then the call has no effect.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) {
-
- pwmp->tpm->SC &= ~TPMx_SC_TOIE;
-}
-
-/**
- * @brief Enables a channel de-activation edge notification.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @pre The channel must have been activated using @p pwmEnableChannel().
- * @note If the notification is already enabled then the call has no effect.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...channels-1)
- *
- * @notapi
- */
-void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
- pwmchannel_t channel) {
-
- pwmp->tpm->C[channel].SC |= TPMx_CnSC_CHIE;
-}
-
-/**
- * @brief Disables a channel de-activation edge notification.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @pre The channel must have been activated using @p pwmEnableChannel().
- * @note If the notification is already disabled then the call has no effect.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...channels-1)
- *
- * @notapi
- */
-void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
- pwmchannel_t channel) {
-
- pwmp->tpm->C[channel].SC &= ~TPMx_CnSC_CHIE;
-}
-
-#endif /* HAL_USE_PWM */
-
-/** @} */
+/* + ChibiOS - Copyright (C) 2014 Adam J. Porter + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file KL2x/pwm_lld.c + * @brief KINETIS PWM subsystem low level driver source. + * + * @addtogroup PWM + * @{ + */ + +#include "hal.h" + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief PWMD1 driver identifier. + * @note The driver PWMD1 allocates the timer TPM0 when enabled. + */ +#if KINETIS_PWM_USE_TPM0 || defined(__DOXYGEN__) +PWMDriver PWMD1; +#endif + +/** + * @brief PWMD2 driver identifier. + * @note The driver PWMD2 allocates the timer TPM1 when enabled. + */ +#if KINETIS_PWM_USE_TPM1 || defined(__DOXYGEN__) +PWMDriver PWMD2; +#endif + +/** + * @brief PWMD3 driver identifier. + * @note The driver PWMD3 allocates the timer TPM2 when enabled. + */ +#if KINETIS_PWM_USE_TPM2 || defined(__DOXYGEN__) +PWMDriver PWMD3; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void pwm_lld_serve_interrupt(PWMDriver *pwmp) { + uint32_t sr; + + sr = pwmp->tpm->STATUS; + pwmp->tpm->STATUS = 0xFFFFFFFF; + + if (((sr & TPMx_STATUS_TOF) != 0) && + (pwmp->config->callback != NULL)) + pwmp->config->callback(pwmp); + if (((sr & TPMx_STATUS_CH0F) != 0) && + (pwmp->config->channels[0].callback != NULL)) + pwmp->config->channels[0].callback(pwmp); + if (((sr & TPMx_STATUS_CH1F) != 0) && + (pwmp->config->channels[1].callback != NULL)) + pwmp->config->channels[1].callback(pwmp); + if (((sr & TPMx_STATUS_CH2F) != 0) && + (pwmp->config->channels[2].callback != NULL)) + pwmp->config->channels[2].callback(pwmp); + if (((sr & TPMx_STATUS_CH3F) != 0) && + (pwmp->config->channels[3].callback != NULL)) + pwmp->config->channels[3].callback(pwmp); + if (((sr & TPMx_STATUS_CH4F) != 0) && + (pwmp->config->channels[4].callback != NULL)) + pwmp->config->channels[4].callback(pwmp); + if (((sr & TPMx_STATUS_CH5F) != 0) && + (pwmp->config->channels[5].callback != NULL)) + pwmp->config->channels[5].callback(pwmp); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if KINETIS_PWM_USE_TPM0 +/** + * @brief TPM0 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(KINETIS_TPM0_IRQ_VECTOR) { + + OSAL_IRQ_PROLOGUE(); + pwm_lld_serve_interrupt(&PWMD1); + OSAL_IRQ_EPILOGUE(); +} +#endif /* KINETIS_PWM_USE_TPM0 */ + +#if KINETIS_PWM_USE_TPM1 +/** + * @brief TPM1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(KINETIS_TPM1_IRQ_VECTOR) { + + OSAL_IRQ_PROLOGUE(); + pwm_lld_serve_interrupt(&PWMD2); + OSAL_IRQ_EPILOGUE(); +} +#endif /* KINETIS_PWM_USE_TPM1 */ + +#if KINETIS_PWM_USE_TPM2 +/** + * @brief TPM2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(KINETIS_TPM2_IRQ_VECTOR) { + + OSAL_IRQ_PROLOGUE(); + pwm_lld_serve_interrupt(&PWMD3); + OSAL_IRQ_EPILOGUE(); +} +#endif /* KINETIS_PWM_USE_TPM2 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level PWM driver initialization. + * + * @notapi + */ +void pwm_lld_init(void) { + +#if KINETIS_PWM_USE_TPM0 + pwmObjectInit(&PWMD1); + PWMD1.channels = KINETIS_TPM0_CHANNELS; + PWMD1.tpm = TPM0; +#endif + +#if KINETIS_PWM_USE_TPM1 + pwmObjectInit(&PWMD2); + PWMD2.channels = KINETIS_TPM1_CHANNELS; + PWMD2.tpm = TPM1; +#endif + +#if KINETIS_PWM_USE_TPM2 + pwmObjectInit(&PWMD3); + PWMD3.channels = KINETIS_TPM2_CHANNELS; + PWMD3.tpm = TPM2; +#endif +} + +/** + * @brief Configures and activates the PWM peripheral. + * @note Starting a driver that is already in the @p PWM_READY state + * disables all the active channels. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_start(PWMDriver *pwmp) { + uint32_t psc; + int i; + + if (pwmp->state == PWM_STOP) { + /* Clock activation and timer reset.*/ +#if KINETIS_PWM_USE_TPM0 + if (&PWMD1 == pwmp) { + SIM->SCGC6 |= SIM_SCGC6_TPM0; + nvicEnableVector(TPM0_IRQn, KINETIS_PWM_TPM0_IRQ_PRIORITY); + } +#endif + +#if KINETIS_PWM_USE_TPM1 + if (&PWMD2 == pwmp) { + SIM->SCGC6 |= SIM_SCGC6_TPM1; + nvicEnableVector(TPM1_IRQn, KINETIS_PWM_TPM1_IRQ_PRIORITY); + } +#endif + +#if KINETIS_PWM_USE_TPM2 + if (&PWMD3 == pwmp) { + SIM->SCGC6 |= SIM_SCGC6_TPM2; + nvicEnableVector(TPM2_IRQn, KINETIS_PWM_TPM2_IRQ_PRIORITY); + } +#endif + } + + /* Disable LPTPM counter.*/ + pwmp->tpm->SC = 0; + /* Clear count register.*/ + pwmp->tpm->CNT = 0; + + /* Prescaler value calculation.*/ + psc = (KINETIS_SYSCLK_FREQUENCY / pwmp->config->frequency); + /* Prescaler must be power of two between 1 and 128.*/ + osalDbgAssert(psc <= 128 && !(psc & (psc - 1)), "invalid frequency"); + /* Prescaler register value determination. + Prescaler register value conveniently corresponds to bit position, + i.e., register value for prescaler CLK/64 is 6 ((1 << 6) == 64).*/ + for (i = 0; i < 8; i++) { + if (psc == (1UL << i)) { + break; + } + } + /* Set prescaler and clock mode. + This also sets the following: + CPWM up-counting mode + Timer overflow interrupt disabled + DMA disabled.*/ + pwmp->tpm->SC = TPMx_SC_CMOD_LPTPM_CLK | i; + /* Configure period.*/ + pwmp->tpm->MOD = pwmp->period - 1; +} + +/** + * @brief Deactivates the PWM peripheral. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_stop(PWMDriver *pwmp) { + + /* If in ready state then disables the PWM clock.*/ + if (pwmp->state == PWM_READY) { +#if KINETIS_PWM_USE_TPM0 + if (&PWMD1 == pwmp) { + SIM->SCGC6 &= ~SIM_SCGC6_TPM0; + nvicDisableVector(TPM0_IRQn); + } +#endif + +#if KINETIS_PWM_USE_TPM1 + if (&PWMD2 == pwmp) { + SIM->SCGC6 &= ~SIM_SCGC6_TPM1; + nvicDisableVector(TPM1_IRQn); + } +#endif + +#if KINETIS_PWM_USE_TPM2 + if (&PWMD3 == pwmp) { + SIM->SCGC6 &= ~SIM_SCGC6_TPM2; + nvicDisableVector(TPM2_IRQn); + } +#endif + /* Disable LPTPM counter.*/ + pwmp->tpm->SC = 0; + pwmp->tpm->MOD = 0; + } +} + + +/** + * @brief Enables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is active using the specified configuration. + * @note The function has effect at the next cycle start. + * @note Channel notification is not enabled. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...channels-1) + * @param[in] width PWM pulse width as clock pulses number + * + * @notapi + */ +void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width) { + uint32_t mode = TPMx_CnSC_MSB; /* Edge-aligned PWM mode.*/ + + switch (pwmp->config->channels[channel].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_HIGH: + mode |= TPMx_CnSC_ELSB; + break; + case PWM_OUTPUT_ACTIVE_LOW: + mode |= TPMx_CnSC_ELSA; + break; + } + + if (pwmp->tpm->C[channel].SC & TPMx_CnSC_CHIE) + mode |= TPMx_CnSC_CHIE; + + pwmp->tpm->C[channel].SC = mode; + pwmp->tpm->C[channel].V = width; +} + +/** + * @brief Disables a PWM channel and its notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is disabled and its output line returned to the + * idle state. + * @note The function has effect at the next cycle start. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...channels-1) + * + * @notapi + */ +void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { + + pwmp->tpm->C[channel].SC = 0; + pwmp->tpm->C[channel].V = 0; +} + +/** + * @brief Enables the periodic activation edge notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @note If the notification is already enabled then the call has no effect. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) { + + pwmp->tpm->SC |= TPMx_SC_TOIE; +} + +/** + * @brief Disables the periodic activation edge notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @note If the notification is already disabled then the call has no effect. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) { + + pwmp->tpm->SC &= ~TPMx_SC_TOIE; +} + +/** + * @brief Enables a channel de-activation edge notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @pre The channel must have been activated using @p pwmEnableChannel(). + * @note If the notification is already enabled then the call has no effect. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...channels-1) + * + * @notapi + */ +void pwm_lld_enable_channel_notification(PWMDriver *pwmp, + pwmchannel_t channel) { + + pwmp->tpm->C[channel].SC |= TPMx_CnSC_CHIE; +} + +/** + * @brief Disables a channel de-activation edge notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @pre The channel must have been activated using @p pwmEnableChannel(). + * @note If the notification is already disabled then the call has no effect. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...channels-1) + * + * @notapi + */ +void pwm_lld_disable_channel_notification(PWMDriver *pwmp, + pwmchannel_t channel) { + + pwmp->tpm->C[channel].SC &= ~TPMx_CnSC_CHIE; +} + +#endif /* HAL_USE_PWM */ + +/** @} */ diff --git a/os/hal/ports/KINETIS/KL2x/hal_pwm_lld.h b/os/hal/ports/KINETIS/LLD/TPMv1/hal_pwm_lld.h index 64ff9ee..9821369 100644 --- a/os/hal/ports/KINETIS/KL2x/hal_pwm_lld.h +++ b/os/hal/ports/KINETIS/LLD/TPMv1/hal_pwm_lld.h @@ -1,305 +1,305 @@ -/*
- ChibiOS - Copyright (C) 2006..2015 Adam J. Porter
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KL2x/pwm_lld.h
- * @brief KINETIS PWM subsystem low level driver header.
- *
- * @addtogroup PWM
- * @{
- */
-
-#ifndef HAL_PWM_LLD_H_
-#define HAL_PWM_LLD_H_
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-#if !defined(KINETIS_PWM_USE_TPM0)
-#define KINETIS_PWM_USE_TPM0 FALSE
-#endif
-#if !defined(KINETIS_PWM_USE_TPM1)
-#define KINETIS_PWM_USE_TPM1 FALSE
-#endif
-#if !defined(KINETIS_PWM_USE_TPM2)
-#define KINETIS_PWM_USE_TPM2 FALSE
-#endif
-
-/**
- * @brief Number of PWM channels per PWM driver.
- */
-#define PWM_CHANNELS 6
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief If advanced timer features switch.
- * @details If set to @p TRUE the advanced features for TIM1 and TIM8 are
- * enabled.
- * @note The default is @p TRUE.
- */
-#if !defined(KINETIS_PWM_USE_ADVANCED) || defined(__DOXYGEN__)
-#define KINETIS_PWM_USE_ADVANCED FALSE
-#endif
-
-/**
- * @brief TPM0 interrupt priority level setting.
- * @note The default is 2.
- */
-#if !defined(KINETIS_PWM_TPM0_IRQ_PRIORITY)|| defined(__DOXYGEN__)
-#define KINETIS_PWM_TPM0_IRQ_PRIORITY 2
-#endif
-
-/**
- * @brief TPM1 interrupt priority level setting.
- * @note The default is 2.
- */
-#if !defined(KINETIS_PWM_TPM1_IRQ_PRIORITY)|| defined(__DOXYGEN__)
-#define KINETIS_PWM_TPM1_IRQ_PRIORITY 2
-#endif
-
-/**
- * @brief TPM2 interrupt priority level setting.
- * @note The default is 2.
- */
-#if !defined(KINETIS_PWM_TPM2_IRQ_PRIORITY)|| defined(__DOXYGEN__)
-#define KINETIS_PWM_TPM2_IRQ_PRIORITY 2
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Configuration checks. */
-/*===========================================================================*/
-
-#if KINETIS_PWM_USE_TPM0 && !KINETIS_HAS_TPM0
-#error "TPM0 not present in the selected device"
-#endif
-
-#if KINETIS_PWM_USE_TPM1 && !KINETIS_HAS_TPM1
-#error "TPM1 not present in the selected device"
-#endif
-
-#if KINETIS_PWM_USE_TPM2 && !KINETIS_HAS_TPM2
-#error "TPM2 not present in the selected device"
-#endif
-
-#if !KINETIS_PWM_USE_TPM0 && !KINETIS_PWM_USE_TPM1 && !KINETIS_PWM_USE_TPM2
-#error "PWM driver activated but no TPM peripheral assigned"
-#endif
-
-#if KINETIS_PWM_USE_TPM0 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_PWM_TPM0_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to KINETIS_PWM_TPM0_IRQ_PRIORITY"
-#endif
-
-#if KINETIS_PWM_USE_TPM1 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_PWM_TPM1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to KINETIS_PWM_TPM1_IRQ_PRIORITY"
-#endif
-
-#if KINETIS_PWM_USE_TPM2 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_PWM_TPM2_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to KINETIS_PWM_TPM2_IRQ_PRIORITY"
-#endif
-
-#if !defined(KINETIS_TPM0_IRQ_VECTOR)
-#error "KINETIS_TPM0_IRQ_VECTOR not defined"
-#endif
-
-#if !defined(KINETIS_TPM1_IRQ_VECTOR)
-#error "KINETIS_TPM1_IRQ_VECTOR not defined"
-#endif
-
-#if !defined(KINETIS_TPM2_IRQ_VECTOR)
-#error "KINETIS_TPM2_IRQ_VECTOR not defined"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Type of a PWM mode.
- */
-typedef uint32_t pwmmode_t;
-
-/**
- * @brief Type of a PWM channel.
- */
-typedef uint8_t pwmchannel_t;
-
-/**
- * @brief Type of a channels mask.
- */
-typedef uint32_t pwmchnmsk_t;
-
-/**
- * @brief Type of a PWM counter.
- */
-typedef uint16_t pwmcnt_t;
-
-/**
- * @brief Type of a PWM driver channel configuration structure.
- */
-typedef struct {
- /**
- * @brief Channel active logic level.
- */
- pwmmode_t mode;
- /**
- * @brief Channel callback pointer.
- * @note This callback is invoked on the channel compare event. If set to
- * @p NULL then the callback is disabled.
- */
- pwmcallback_t callback;
- /* End of the mandatory fields.*/
-} PWMChannelConfig;
-
-/**
- * @brief Type of a PWM driver configuration structure.
- */
-typedef struct {
- /**
- * @brief Timer clock in Hz.
- * @note The low level can use assertions in order to catch invalid
- * frequency specifications.
- */
- uint32_t frequency;
- /**
- * @brief PWM period in ticks.
- * @note The low level can use assertions in order to catch invalid
- * period specifications.
- */
- pwmcnt_t period;
- /**
- * @brief Periodic callback pointer.
- * @note This callback is invoked on PWM counter reset. If set to
- * @p NULL then the callback is disabled.
- */
- pwmcallback_t callback;
- /**
- * @brief Channels configurations.
- */
- PWMChannelConfig channels[PWM_CHANNELS];
- /* End of the mandatory fields.*/
-} PWMConfig;
-
-/**
- * @brief Structure representing a PWM driver.
- */
-struct PWMDriver {
- /**
- * @brief Driver state.
- */
- pwmstate_t state;
- /**
- * @brief Current driver configuration data.
- */
- const PWMConfig *config;
- /**
- * @brief Current PWM period in ticks.
- */
- pwmcnt_t period;
- /**
- * @brief Mask of the enabled channels.
- */
- pwmchnmsk_t enabled;
- /**
- * @brief Number of channels in this instance.
- */
- pwmchannel_t channels;
-#if defined(PWM_DRIVER_EXT_FIELDS)
- PWM_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the TPM registers block.
- */
- TPM_TypeDef *tpm;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @brief Changes the period the PWM peripheral.
- * @details This function changes the period of a PWM unit that has already
- * been activated using @p pwmStart().
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The PWM unit period is changed to the new value.
- * @note The function has effect at the next cycle start.
- * @note If a period is specified that is shorter than the pulse width
- * programmed in one of the channels then the behavior is not
- * guaranteed.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] period new cycle time in ticks
- *
- * @notapi
- */
-#define pwm_lld_change_period(pwmp, period) \
- ((pwmp)->tpm->MOD = ((period) - 1))
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if KINETIS_PWM_USE_TPM0 || defined(__DOXYGEN__)
-extern PWMDriver PWMD1;
-#endif
-#if KINETIS_PWM_USE_TPM1 || defined(__DOXYGEN__)
-extern PWMDriver PWMD2;
-#endif
-#if KINETIS_PWM_USE_TPM2 || defined(__DOXYGEN__)
-extern PWMDriver PWMD3;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void pwm_lld_init(void);
- void pwm_lld_start(PWMDriver *pwmp);
- void pwm_lld_stop(PWMDriver *pwmp);
- void pwm_lld_enable_channel(PWMDriver *pwmp,
- pwmchannel_t channel,
- pwmcnt_t width);
- void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
- void pwm_lld_enable_periodic_notification(PWMDriver *pwmp);
- void pwm_lld_disable_periodic_notification(PWMDriver *pwmp);
- void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
- pwmchannel_t channel);
- void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
- pwmchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PWM */
-
-#endif /* HAL_PWM_LLD_H_ */
-
-/** @} */
+/* + ChibiOS - Copyright (C) 2006..2015 Adam J. Porter + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file KL2x/pwm_lld.h + * @brief KINETIS PWM subsystem low level driver header. + * + * @addtogroup PWM + * @{ + */ + +#ifndef HAL_PWM_LLD_H_ +#define HAL_PWM_LLD_H_ + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#if !defined(KINETIS_PWM_USE_TPM0) +#define KINETIS_PWM_USE_TPM0 FALSE +#endif +#if !defined(KINETIS_PWM_USE_TPM1) +#define KINETIS_PWM_USE_TPM1 FALSE +#endif +#if !defined(KINETIS_PWM_USE_TPM2) +#define KINETIS_PWM_USE_TPM2 FALSE +#endif + +/** + * @brief Number of PWM channels per PWM driver. + */ +#define PWM_CHANNELS 6 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief If advanced timer features switch. + * @details If set to @p TRUE the advanced features for TIM1 and TIM8 are + * enabled. + * @note The default is @p TRUE. + */ +#if !defined(KINETIS_PWM_USE_ADVANCED) || defined(__DOXYGEN__) +#define KINETIS_PWM_USE_ADVANCED FALSE +#endif + +/** + * @brief TPM0 interrupt priority level setting. + * @note The default is 2. + */ +#if !defined(KINETIS_PWM_TPM0_IRQ_PRIORITY)|| defined(__DOXYGEN__) +#define KINETIS_PWM_TPM0_IRQ_PRIORITY 2 +#endif + +/** + * @brief TPM1 interrupt priority level setting. + * @note The default is 2. + */ +#if !defined(KINETIS_PWM_TPM1_IRQ_PRIORITY)|| defined(__DOXYGEN__) +#define KINETIS_PWM_TPM1_IRQ_PRIORITY 2 +#endif + +/** + * @brief TPM2 interrupt priority level setting. + * @note The default is 2. + */ +#if !defined(KINETIS_PWM_TPM2_IRQ_PRIORITY)|| defined(__DOXYGEN__) +#define KINETIS_PWM_TPM2_IRQ_PRIORITY 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/* Configuration checks. */ +/*===========================================================================*/ + +#if KINETIS_PWM_USE_TPM0 && !KINETIS_HAS_TPM0 +#error "TPM0 not present in the selected device" +#endif + +#if KINETIS_PWM_USE_TPM1 && !KINETIS_HAS_TPM1 +#error "TPM1 not present in the selected device" +#endif + +#if KINETIS_PWM_USE_TPM2 && !KINETIS_HAS_TPM2 +#error "TPM2 not present in the selected device" +#endif + +#if !KINETIS_PWM_USE_TPM0 && !KINETIS_PWM_USE_TPM1 && !KINETIS_PWM_USE_TPM2 +#error "PWM driver activated but no TPM peripheral assigned" +#endif + +#if KINETIS_PWM_USE_TPM0 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_PWM_TPM0_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to KINETIS_PWM_TPM0_IRQ_PRIORITY" +#endif + +#if KINETIS_PWM_USE_TPM1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_PWM_TPM1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to KINETIS_PWM_TPM1_IRQ_PRIORITY" +#endif + +#if KINETIS_PWM_USE_TPM2 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_PWM_TPM2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to KINETIS_PWM_TPM2_IRQ_PRIORITY" +#endif + +#if !defined(KINETIS_TPM0_IRQ_VECTOR) +#error "KINETIS_TPM0_IRQ_VECTOR not defined" +#endif + +#if !defined(KINETIS_TPM1_IRQ_VECTOR) +#error "KINETIS_TPM1_IRQ_VECTOR not defined" +#endif + +#if !defined(KINETIS_TPM2_IRQ_VECTOR) +#error "KINETIS_TPM2_IRQ_VECTOR not defined" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a PWM mode. + */ +typedef uint32_t pwmmode_t; + +/** + * @brief Type of a PWM channel. + */ +typedef uint8_t pwmchannel_t; + +/** + * @brief Type of a channels mask. + */ +typedef uint32_t pwmchnmsk_t; + +/** + * @brief Type of a PWM counter. + */ +typedef uint16_t pwmcnt_t; + +/** + * @brief Type of a PWM driver channel configuration structure. + */ +typedef struct { + /** + * @brief Channel active logic level. + */ + pwmmode_t mode; + /** + * @brief Channel callback pointer. + * @note This callback is invoked on the channel compare event. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /* End of the mandatory fields.*/ +} PWMChannelConfig; + +/** + * @brief Type of a PWM driver configuration structure. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + uint32_t frequency; + /** + * @brief PWM period in ticks. + * @note The low level can use assertions in order to catch invalid + * period specifications. + */ + pwmcnt_t period; + /** + * @brief Periodic callback pointer. + * @note This callback is invoked on PWM counter reset. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /** + * @brief Channels configurations. + */ + PWMChannelConfig channels[PWM_CHANNELS]; + /* End of the mandatory fields.*/ +} PWMConfig; + +/** + * @brief Structure representing a PWM driver. + */ +struct PWMDriver { + /** + * @brief Driver state. + */ + pwmstate_t state; + /** + * @brief Current driver configuration data. + */ + const PWMConfig *config; + /** + * @brief Current PWM period in ticks. + */ + pwmcnt_t period; + /** + * @brief Mask of the enabled channels. + */ + pwmchnmsk_t enabled; + /** + * @brief Number of channels in this instance. + */ + pwmchannel_t channels; +#if defined(PWM_DRIVER_EXT_FIELDS) + PWM_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the TPM registers block. + */ + TPM_TypeDef *tpm; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Changes the period the PWM peripheral. + * @details This function changes the period of a PWM unit that has already + * been activated using @p pwmStart(). + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The PWM unit period is changed to the new value. + * @note The function has effect at the next cycle start. + * @note If a period is specified that is shorter than the pulse width + * programmed in one of the channels then the behavior is not + * guaranteed. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] period new cycle time in ticks + * + * @notapi + */ +#define pwm_lld_change_period(pwmp, period) \ + ((pwmp)->tpm->MOD = ((period) - 1)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if KINETIS_PWM_USE_TPM0 || defined(__DOXYGEN__) +extern PWMDriver PWMD1; +#endif +#if KINETIS_PWM_USE_TPM1 || defined(__DOXYGEN__) +extern PWMDriver PWMD2; +#endif +#if KINETIS_PWM_USE_TPM2 || defined(__DOXYGEN__) +extern PWMDriver PWMD3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void pwm_lld_init(void); + void pwm_lld_start(PWMDriver *pwmp); + void pwm_lld_stop(PWMDriver *pwmp); + void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width); + void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel); + void pwm_lld_enable_periodic_notification(PWMDriver *pwmp); + void pwm_lld_disable_periodic_notification(PWMDriver *pwmp); + void pwm_lld_enable_channel_notification(PWMDriver *pwmp, + pwmchannel_t channel); + void pwm_lld_disable_channel_notification(PWMDriver *pwmp, + pwmchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PWM */ + +#endif /* HAL_PWM_LLD_H_ */ + +/** @} */ diff --git a/os/hal/ports/KINETIS/LLD/UARTv1/driver.mk b/os/hal/ports/KINETIS/LLD/UARTv1/driver.mk new file mode 100644 index 0000000..e0ba660 --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/UARTv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/UARTv1/hal_serial_lld.c +endif +else +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/UARTv1/hal_serial_lld.c +endif + +PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/UARTv1 diff --git a/os/hal/ports/KINETIS/LLD/hal_serial_lld.c b/os/hal/ports/KINETIS/LLD/UARTv1/hal_serial_lld.c index a1b6632..443ec5f 100644 --- a/os/hal/ports/KINETIS/LLD/hal_serial_lld.c +++ b/os/hal/ports/KINETIS/LLD/UARTv1/hal_serial_lld.c @@ -16,7 +16,7 @@ */
/**
- * @file KL2x/serial_lld.c
+ * @file UARTv1/hal_serial_lld.c
* @brief Kinetis KL2x Serial Driver subsystem low level driver source.
*
* @addtogroup SERIAL
diff --git a/os/hal/ports/KINETIS/LLD/hal_serial_lld.h b/os/hal/ports/KINETIS/LLD/UARTv1/hal_serial_lld.h index 3cb6d2b..df7045b 100644 --- a/os/hal/ports/KINETIS/LLD/hal_serial_lld.h +++ b/os/hal/ports/KINETIS/LLD/UARTv1/hal_serial_lld.h @@ -15,7 +15,7 @@ */
/**
- * @file KL2x/serial_lld.h
+ * @file UARTv1/hal_serial_lld.h
* @brief Kinetis KL2x Serial Driver subsystem low level driver header.
*
* @addtogroup SERIAL
diff --git a/os/hal/ports/KINETIS/LLD/USBHSv1/driver.mk b/os/hal/ports/KINETIS/LLD/USBHSv1/driver.mk new file mode 100644 index 0000000..1c0192a --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/USBHSv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_USB TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/USBHSv1/hal_usb_lld.c +endif +else +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/USBHSv1/hal_usb_lld.c +endif + +PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/USBHSv1 diff --git a/os/hal/ports/KINETIS/LLD/hal_usb_lld.c b/os/hal/ports/KINETIS/LLD/USBHSv1/hal_usb_lld.c index a01b92e..dc1fca9 100644 --- a/os/hal/ports/KINETIS/LLD/hal_usb_lld.c +++ b/os/hal/ports/KINETIS/LLD/USBHSv1/hal_usb_lld.c @@ -16,7 +16,7 @@ */
/**
- * @file KINETIS/LLD/usb_lld.c
+ * @file USBHSv1/hal_usb_lld.c
* @brief KINETIS USB subsystem low level driver source.
*
* @addtogroup USB
diff --git a/os/hal/ports/KINETIS/LLD/hal_usb_lld.h b/os/hal/ports/KINETIS/LLD/USBHSv1/hal_usb_lld.h index bd4eb39..05dd9c8 100644 --- a/os/hal/ports/KINETIS/LLD/hal_usb_lld.h +++ b/os/hal/ports/KINETIS/LLD/USBHSv1/hal_usb_lld.h @@ -16,7 +16,7 @@ */
/**
- * @file KINETIS/LLD/usb_lld.h
+ * @file USBHSv1/hal_usb_lld.h
* @brief KINETIS USB subsystem low level driver header.
*
* @addtogroup USB
diff --git a/os/hal/ports/KINETIS/MK66F18/platform.mk b/os/hal/ports/KINETIS/MK66F18/platform.mk index 0e6be12..ce16bd5 100644 --- a/os/hal/ports/KINETIS/MK66F18/platform.mk +++ b/os/hal/ports/KINETIS/MK66F18/platform.mk @@ -1,19 +1,33 @@ -# List of all platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/MK66F18/hal_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_pal_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_serial_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/MK66F18/hal_spi_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_ext_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_adc_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_gpt_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/MK66F18/hal_pwm_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_st_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
+PLATFORMSRC_CONTRIB := ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/MK66F18/hal_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/PITv1/hal_st_lld.c
+
+PLATFORMINC_CONTRIB := ${CHIBIOS}/os/hal/ports/common/ARMCMx \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/MK66F18
+
+ifeq ($(USE_SMART_BUILD),yes)
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/MK66F18 \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD
+# Configuration files directory
+ifeq ($(CONFDIR),)
+ CONFDIR = .
+endif
+
+HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define"))
+
+endif
+
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/GPIOv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/UARTv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/SPIv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/I2Cv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/PORTv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/ADCv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/PITv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/SDHCv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/FTMv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/USBHSv1/driver.mk
+
+# Shared variables
+ALLCSRC += $(PLATFORMSRC_CONTRIB)
+ALLINC += $(PLATFORMINC_CONTRIB)
diff --git a/os/hal/ports/NRF5/LLD/ADCv1/driver.mk b/os/hal/ports/NRF5/LLD/ADCv1/driver.mk new file mode 100644 index 0000000..88deb3e --- /dev/null +++ b/os/hal/ports/NRF5/LLD/ADCv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/ADCv1/hal_adc_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/ADCv1/hal_adc_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/ADCv1
diff --git a/os/hal/ports/NRF5/NRF51822/hal_adc_lld.c b/os/hal/ports/NRF5/LLD/ADCv1/hal_adc_lld.c index 6c0f2c6..e1d8bc6 100644 --- a/os/hal/ports/NRF5/NRF51822/hal_adc_lld.c +++ b/os/hal/ports/NRF5/LLD/ADCv1/hal_adc_lld.c @@ -15,8 +15,8 @@ */
/**
- * @file NRF51Fx22/adc_lld.c
- * @brief NRF51Fx22 ADC subsystem low level driver source.
+ * @file ADCv1/adc_lld.c
+ * @brief NRF51 ADC subsystem low level driver source.
*
* @addtogroup ADC
* @{
diff --git a/os/hal/ports/NRF5/NRF51822/hal_adc_lld.h b/os/hal/ports/NRF5/LLD/ADCv1/hal_adc_lld.h index 2ee30ac..4e185d5 100644 --- a/os/hal/ports/NRF5/NRF51822/hal_adc_lld.h +++ b/os/hal/ports/NRF5/LLD/ADCv1/hal_adc_lld.h @@ -15,8 +15,8 @@ */
/**
- * @file NRF51x22/adc_lld.h
- * @brief NRF51x22 ADC subsystem low level driver header.
+ * @file ADCv1/adc_lld.h
+ * @brief NRF51 ADC subsystem low level driver header.
*
* @addtogroup ADC
* @{
diff --git a/os/hal/ports/NRF5/LLD/GPIOv1/driver.mk b/os/hal/ports/NRF5/LLD/GPIOv1/driver.mk new file mode 100644 index 0000000..a627fab --- /dev/null +++ b/os/hal/ports/NRF5/LLD/GPIOv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/GPIOv1/hal_pal_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/GPIOv1/hal_pal_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/GPIOv1
diff --git a/os/hal/ports/NRF5/LLD/hal_pal_lld.c b/os/hal/ports/NRF5/LLD/GPIOv1/hal_pal_lld.c index 21e4b0b..3029367 100644 --- a/os/hal/ports/NRF5/LLD/hal_pal_lld.c +++ b/os/hal/ports/NRF5/LLD/GPIOv1/hal_pal_lld.c @@ -1,4 +1,5 @@ /*
+ Copyright (C) 2018 Konstantin Oblaukhov
Copyright (C) 2015 Fabio Utzig
Licensed under the Apache License, Version 2.0 (the "License");
@@ -15,7 +16,7 @@ */
/**
- * @file NRF5/LLD/hal_pal_lld.c
+ * @file GPIOv1/hal_pal_lld.c
* @brief NRF5 PAL subsystem low level driver source.
*
* @addtogroup PAL
@@ -35,6 +36,11 @@ /* Driver exported variables. */
/*===========================================================================*/
+/**
+ * @brief Event records for the GPIOTE channels.
+ */
+palevent_t _pal_events[NRF5_GPIOTE_NUM_CHANNELS];
+
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
@@ -127,6 +133,12 @@ void _pal_lld_init(const PALConfig *config) for (i = 0; i < TOTAL_GPIO_PADS; i++) {
pal_lld_setpadmode(IOPORT1, i, config->pads[i]);
}
+
+#if PAL_USE_CALLBACKS || PAL_USE_WAIT || defined(__DOXYGEN__)
+ for (i = 0; i < NRF5_GPIOTE_NUM_CHANNELS; i++) {
+ _pal_init_event(i);
+ }
+#endif
}
/**
@@ -153,6 +165,76 @@ void _pal_lld_setgroupmode(ioportid_t port, }
}
+#if PAL_USE_CALLBACKS || PAL_USE_WAIT || defined(__DOXYGEN__)
+/**
+ * @brief Pad event enable.
+ * @note Programming an unknown or unsupported mode is silently ignored.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @param[in] mode pad event mode
+ *
+ * @notapi
+ */
+void _pal_lld_enablepadevent(ioportid_t port,
+ iopadid_t pad,
+ ioeventmode_t mode) {
+ (void)port;
+
+ int ch = NRF5_PAL_PAD_TO_EVENT(pad);
+ uint32_t config = NRF_GPIOTE->CONFIG[ch];
+
+ osalDbgAssert((((config & GPIOTE_CONFIG_PSEL_Msk) >> GPIOTE_CONFIG_PSEL_Pos) == pad) ||
+ (((config & GPIOTE_CONFIG_MODE_Msk) >> GPIOTE_CONFIG_MODE_Pos) != GPIOTE_CONFIG_MODE_Event),
+ "channel already in use");
+
+ if ((mode & PAL_EVENT_MODE_RISING_EDGE) && (mode & PAL_EVENT_MODE_FALLING_EDGE))
+ config |= (GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos);
+ else if (mode & PAL_EVENT_MODE_RISING_EDGE)
+ config |= (GPIOTE_CONFIG_POLARITY_LoToHi << GPIOTE_CONFIG_POLARITY_Pos);
+ else
+ config |= (GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos);
+
+ config |= (pad << GPIOTE_CONFIG_PSEL_Pos);
+
+ config |= (GPIOTE_CONFIG_MODE_Event << GPIOTE_CONFIG_MODE_Pos);
+
+ NRF_GPIOTE->CONFIG[ch] = config;
+ NRF_GPIOTE->EVENTS_PORT = 0;
+ NRF_GPIOTE->EVENTS_IN[ch] = 0;
+ NRF_GPIOTE->INTENSET = (1 << ch);
+}
+
+/**
+ * @brief Pad event disable.
+ * @details This function disables previously programmed event callbacks.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ *
+ * @notapi
+ */
+void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) {
+ (void)port;
+ int ch = NRF5_PAL_PAD_TO_EVENT(pad);
+ uint32_t config = NRF_GPIOTE->CONFIG[ch];
+
+ if (((config & GPIOTE_CONFIG_MODE_Msk) >> GPIOTE_CONFIG_MODE_Pos) == GPIOTE_CONFIG_MODE_Event)
+ {
+ osalDbgAssert(((config & GPIOTE_CONFIG_PSEL_Msk) >> GPIOTE_CONFIG_PSEL_Pos) == pad,
+ "channel mapped on different pad");
+
+ NRF_GPIOTE->INTENSET &= ~(1 << ch);
+ NRF_GPIOTE->CONFIG[ch] = 0;
+
+#if PAL_USE_CALLBACKS || PAL_USE_WAIT
+ /* Callback cleared and/or thread reset.*/
+ _pal_clear_event(pad);
+#endif
+ }
+}
+#endif /* PAL_USE_CALLBACKS || PAL_USE_WAIT */
+
#endif /* HAL_USE_PAL == TRUE */
/** @} */
diff --git a/os/hal/ports/NRF5/LLD/hal_pal_lld.h b/os/hal/ports/NRF5/LLD/GPIOv1/hal_pal_lld.h index 745afd3..e9021eb 100644 --- a/os/hal/ports/NRF5/LLD/hal_pal_lld.h +++ b/os/hal/ports/NRF5/LLD/GPIOv1/hal_pal_lld.h @@ -1,4 +1,5 @@ /*
+ Copyright (C) 2018 Konstantin Oblaukhov
Copyright (C) 2015 Fabio Utzig
Licensed under the Apache License, Version 2.0 (the "License");
@@ -15,7 +16,7 @@ */
/**
- * @file NRF5/LLD/hal_pal_lld.h
+ * @file GPIOv1/hal_pal_lld.h
* @brief NRF5 PAL subsystem low level driver header.
*
* @addtogroup PAL
@@ -112,6 +113,11 @@ typedef uint8_t iomode_t; typedef uint32_t ioline_t;
/**
+ * @brief Type of an event mode.
+ */
+typedef uint32_t ioeventmode_t;
+
+/**
* @brief Port Identifier.
* @details This type can be a scalar or some kind of pointer, do not make
* any assumption about it, use the provided macros when populating
@@ -119,6 +125,11 @@ typedef uint32_t ioline_t; */
typedef NRF_GPIO_Type *ioportid_t;
+/**
+ * @brief Type of an pad identifier.
+ */
+typedef uint32_t iopadid_t;
+
/*===========================================================================*/
/* I/O Ports Identifiers. */
/*===========================================================================*/
@@ -134,6 +145,24 @@ typedef NRF_GPIO_Type *ioportid_t; #define IOPORT1 NRF_P0
#endif
+/**
+ * @brief Number of PAL events.
+ * @details Maximum number of GPIO events supported by GPIOTE peripheral
+ */
+#if NRF_SERIES == 51
+#define NRF5_GPIOTE_NUM_CHANNELS (4)
+#else
+#define NRF5_GPIOTE_NUM_CHANNELS (8)
+#endif
+
+/**
+ * @brief Pad to event number
+ * @details Converts pad to GPIOTE peripheral pad event number
+ */
+#if !defined(NRF5_PAL_PAD_TO_EVENT) || defined(__DOXYGEN__)
+#define NRF5_PAL_PAD_TO_EVENT(pad) ((pad) % NRF5_GPIOTE_NUM_CHANNELS)
+#endif
+
/*===========================================================================*/
/* Implementation, some of the following macros could be implemented as */
/* functions, if so please put them in pal_lld.c. */
@@ -326,8 +355,55 @@ typedef NRF_GPIO_Type *ioportid_t; */
#define pal_lld_setpadmode(port, pad, mode) _pal_lld_setpadmode(port, pad, mode)
+/**
+ * @brief Pad event enable.
+ * @note Programming an unknown or unsupported mode is silently ignored.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @param[in] mode pad event mode
+ *
+ * @notapi
+ */
+#define pal_lld_enablepadevent(port, pad, mode) \
+ _pal_lld_enablepadevent(port, pad, mode)
+
+/**
+ * @brief Pad event disable.
+ * @details This function disables previously programmed event callbacks.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_disablepadevent(port, pad) \
+ _pal_lld_disablepadevent(port, pad)
+
+/**
+ * @brief Returns a PAL event structure associated to a pad.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_get_pad_event(port, pad) \
+ &_pal_events[NRF5_PAL_PAD_TO_EVENT(pad)]; (void)(port)
+
+/**
+ * @brief Returns a PAL event structure associated to a line.
+ *
+ * @param[in] line line identifier
+ *
+ * @notapi
+ */
+#define pal_lld_get_line_event(line) \
+ &_pal_events[NRF5_PAL_PAD_TO_EVENT(PAL_PAD(line))]
+
#if !defined(__DOXYGEN__)
extern const PALConfig pal_default_config;
+extern palevent_t _pal_events[NRF5_GPIOTE_NUM_CHANNELS];
#endif
#ifdef __cplusplus
@@ -340,6 +416,12 @@ extern "C" { void _pal_lld_setpadmode(ioportid_t port,
uint8_t pad,
iomode_t mode);
+#if PAL_USE_CALLBACKS || PAL_USE_WAIT
+ void _pal_lld_enablepadevent(ioportid_t port,
+ iopadid_t pad,
+ ioeventmode_t mode);
+ void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad);
+#endif
#ifdef __cplusplus
}
#endif
diff --git a/os/hal/ports/NRF5/LLD/PWMv1/driver.mk b/os/hal/ports/NRF5/LLD/PWMv1/driver.mk new file mode 100644 index 0000000..d64b5dc --- /dev/null +++ b/os/hal/ports/NRF5/LLD/PWMv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/PWMv1/hal_pwm_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/PWMv1/hal_pwm_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/PWMv1
diff --git a/os/hal/ports/NRF5/NRF51822/hal_pwm_lld.c b/os/hal/ports/NRF5/LLD/PWMv1/hal_pwm_lld.c index e2b4b6b..d5201b8 100644 --- a/os/hal/ports/NRF5/NRF51822/hal_pwm_lld.c +++ b/os/hal/ports/NRF5/LLD/PWMv1/hal_pwm_lld.c @@ -15,7 +15,7 @@ */
/**
- * @file hal_pwm_lld.c
+ * @file PWMv1/hal_pwm_lld.c
* @brief NRF51 PWM subsystem low level driver source.
*
* @note Using the method described in nrf51-pwm-library to correctly
diff --git a/os/hal/ports/NRF5/NRF51822/hal_pwm_lld.h b/os/hal/ports/NRF5/LLD/PWMv1/hal_pwm_lld.h index 2cad6e7..616e61a 100644 --- a/os/hal/ports/NRF5/NRF51822/hal_pwm_lld.h +++ b/os/hal/ports/NRF5/LLD/PWMv1/hal_pwm_lld.h @@ -15,7 +15,7 @@ */
/**
- * @file hal_pwm_lld.h
+ * @file PWMv1/hal_pwm_lld.h
* @brief NRF51 PWM subsystem low level driver header.
*
* @addtogroup PWM
diff --git a/os/hal/ports/NRF5/LLD/PWMv2/driver.mk b/os/hal/ports/NRF5/LLD/PWMv2/driver.mk new file mode 100644 index 0000000..ce247df --- /dev/null +++ b/os/hal/ports/NRF5/LLD/PWMv2/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/PWMv2/hal_pwm_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/PWMv2/hal_pwm_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/PWMv2
diff --git a/os/hal/ports/KINETIS/MK66F18/hal_pwm_lld.c b/os/hal/ports/NRF5/LLD/PWMv2/hal_pwm_lld.c index f39823d..7162b1b 100644 --- a/os/hal/ports/KINETIS/MK66F18/hal_pwm_lld.c +++ b/os/hal/ports/NRF5/LLD/PWMv2/hal_pwm_lld.c @@ -1,5 +1,5 @@ /*
- ChibiOS/HAL - Copyright (C) 2014 Adam J. Porter
+ ChibiOS/HAL - Copyright (C) 2018 Andru
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,8 +15,8 @@ */
/**
- * @file MK66F18/pwm_lld.c
- * @brief KINETIS PWM subsystem low level driver source.
+ * @file hal_pwm_lld.c
+ * @brief NRF52 PWM subsystem low level driver source.
*
* @addtogroup PWM
* @{
@@ -29,7 +29,7 @@ /*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
-
+uint16_t pwm_seq[PWM_CHANNELS];
/*===========================================================================*/
/* Driver exported variables. */
@@ -37,25 +37,25 @@ /**
* @brief PWMD1 driver identifier.
- * @note The driver PWMD1 allocates the timer FTM0 when enabled.
+ * @note The driver PWMD1 enabled.
*/
-#if KINETIS_PWM_USE_FTM0 || defined(__DOXYGEN__)
+#if NRF5_PWM_USE_PWM0 || defined(__DOXYGEN__)
PWMDriver PWMD1;
#endif
/**
* @brief PWMD2 driver identifier.
- * @note The driver PWMD2 allocates the timer FTM1 when enabled.
+ * @note The driver PWMD2 enabled.
*/
-#if KINETIS_PWM_USE_FTM1 || defined(__DOXYGEN__)
+#if NRF5_PWM_USE_PWM1 || defined(__DOXYGEN__)
PWMDriver PWMD2;
#endif
/**
* @brief PWMD3 driver identifier.
- * @note The driver PWMD3 allocates the timer FTM2 when enabled.
+ * @note The driver PWMD3 enabled.
*/
-#if KINETIS_PWM_USE_FTM2 || defined(__DOXYGEN__)
+#if NRF5_PWM_USE_PWM2 || defined(__DOXYGEN__)
PWMDriver PWMD3;
#endif
@@ -68,26 +68,16 @@ PWMDriver PWMD3; /*===========================================================================*/
static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
- uint32_t sr;
-
- sr = pwmp->ftm->SC;
- pwmp->ftm->SC = sr&(~FTM_SC_TOF);
-
- if (((sr & FTM_SC_TOF) != 0) && /* Timer Overflow */
- ((sr & FTM_SC_TOIE) != 0) &&
- (pwmp->config->callback != NULL)) {
- pwmp->config->callback(pwmp);
+ /* Deal with PWM period
+ */
+ if (pwmp->config->callback == NULL) {
+ return;
}
- uint8_t n=0;
- for(n=0;n<pwmp->channels;n++) {
- sr = pwmp->ftm->CHANNEL[n].CnSC;
- pwmp->ftm->CHANNEL[n].CnSC = sr&(~FTM_CnSC_CHF);
- if (((sr & FTM_CnSC_CHF) != 0) &&
- ((sr & FTM_CnSC_CHIE) != 0) &&
- (pwmp->config->channels[n].callback != NULL)) {
- pwmp->config->channels[n].callback(pwmp);
- }
+ if ((pwmp->pwm->INTEN & PWM_INTEN_PWMPERIODEND_Msk) && (pwmp->pwm->EVENTS_PWMPERIODEND)) {
+ pwmp->config->callback(pwmp);
+ pwmp->pwm->EVENTS_PWMPERIODEND = 0;
+ (void)pwmp->pwm->EVENTS_PWMPERIODEND;
}
}
@@ -95,46 +85,44 @@ static void pwm_lld_serve_interrupt(PWMDriver *pwmp) { /* Driver interrupt handlers. */
/*===========================================================================*/
-#if KINETIS_PWM_USE_FTM0
+#if NRF5_PWM_USE_PWM0
/**
- * @brief FTM0 interrupt handler.
+ * @brief PWM0 interrupt handler.
*
* @isr
*/
-OSAL_IRQ_HANDLER(KINETIS_FTM0_IRQ_VECTOR) {
+OSAL_IRQ_HANDLER(VectorB0) {
OSAL_IRQ_PROLOGUE();
pwm_lld_serve_interrupt(&PWMD1);
OSAL_IRQ_EPILOGUE();
}
-#endif /* KINETIS_PWM_USE_FTM0 */
+#endif /* NRF5_PWM_USE_PWM0 */
-#if KINETIS_PWM_USE_FTM1
+#if NRF5_PWM_USE_PWM1
/**
- * @brief FTM1 interrupt handler.
+ * @brief PWM1 interrupt handler.
*
* @isr
*/
-OSAL_IRQ_HANDLER(KINETIS_FTM1_IRQ_VECTOR) {
-
+OSAL_IRQ_HANDLER(VectorC4) {
OSAL_IRQ_PROLOGUE();
pwm_lld_serve_interrupt(&PWMD2);
OSAL_IRQ_EPILOGUE();
}
-#endif /* KINETIS_PWM_USE_FTM1 */
+#endif /* NRF5_PWM_USE_PWM1 */
-#if KINETIS_PWM_USE_FTM2
+#if NRF5_PWM_USE_PWM2
/**
- * @brief FTM2 interrupt handler.
+ * @brief PWM2 interrupt handler.
*
* @isr
*/
-OSAL_IRQ_HANDLER(KINETIS_FTM2_IRQ_VECTOR) {
-
+OSAL_IRQ_HANDLER(VectorC8) {
OSAL_IRQ_PROLOGUE();
pwm_lld_serve_interrupt(&PWMD3);
OSAL_IRQ_EPILOGUE();
}
-#endif /* KINETIS_PWM_USE_FTM2 */
+#endif /* NRF5_PWM_USE_PWM2 */
/*===========================================================================*/
/* Driver exported functions. */
@@ -147,22 +135,22 @@ OSAL_IRQ_HANDLER(KINETIS_FTM2_IRQ_VECTOR) { */
void pwm_lld_init(void) {
-#if KINETIS_PWM_USE_FTM0
+#if NRF5_PWM_USE_PWM0
pwmObjectInit(&PWMD1);
- PWMD1.channels = KINETIS_FTM0_CHANNELS;
- PWMD1.ftm = FTM0;
+ PWMD1.channels = PWM_CHANNELS;
+ PWMD1.pwm = NRF_PWM0;
#endif
-#if KINETIS_PWM_USE_FTM1
+#if NRF5_PWM_USE_PWM1
pwmObjectInit(&PWMD2);
- PWMD2.channels = KINETIS_FTM1_CHANNELS;
- PWMD2.ftm = FTM1;
+ PWMD2.channels = PWM_CHANNELS;
+ PWMD2.pwm = NRF_PWM1;
#endif
-#if KINETIS_PWM_USE_FTM2
+#if NRF5_PWM_USE_PWM2
pwmObjectInit(&PWMD3);
- PWMD3.channels = KINETIS_FTM2_CHANNELS;
- PWMD3.ftm = FTM2;
+ PWMD3.channels = PWM_CHANNELS;
+ PWMD3.pwm = NRF_PWM2;
#endif
}
@@ -176,65 +164,58 @@ void pwm_lld_init(void) { * @notapi
*/
void pwm_lld_start(PWMDriver *pwmp) {
- uint16_t psc;
- uint8_t i=0;
-
- if (pwmp->state == PWM_STOP) {
- /* Clock activation and timer reset.*/
-#if KINETIS_PWM_USE_FTM0
- if (&PWMD1 == pwmp) {
- SIM->SCGC6 |= SIM_SCGC6_FTM0;
- nvicEnableVector(FTM0_IRQn, KINETIS_PWM_FTM0_PRIORITY);
- }
-#endif
+ /* Prescaler value calculation: ftimer = 16MHz / 2^PRESCALER */
+ /* Prescaler value as a power of 2, must be 0..7 */
+ uint8_t i, psc_value;
+ for (psc_value = 0; psc_value < 8; psc_value++)
+ if (pwmp->config->frequency == (uint32_t)(16000000 >> psc_value))
+ break;
-#if KINETIS_PWM_USE_FTM1
- if (&PWMD2 == pwmp) {
- SIM->SCGC6 |= SIM_SCGC6_FTM1;
- nvicEnableVector(FTM1_IRQn, KINETIS_PWM_FTM1_PRIORITY);
- }
-#endif
+ /* Prescaler value must be between 0..7, and a power of two. */
+ osalDbgAssert(psc_value <= 7, "invalid frequency");
-#if KINETIS_PWM_USE_FTM2
- if (&PWMD3 == pwmp) {
- SIM->SCGC3 |= SIM_SCGC3_FTM2;
- nvicEnableVector(FTM2_IRQn, KINETIS_PWM_FTM2_PRIORITY);
- }
-#endif
- }
- pwmp->ftm->MODE = FTM_MODE_FTMEN_MASK|FTM_MODE_PWMSYNC_MASK;
- pwmp->ftm->SYNC = FTM_SYNC_CNTMIN_MASK|FTM_SYNC_CNTMAX_MASK
- |FTM_SYNC_SWSYNC_MASK;
- pwmp->ftm->COMBINE = FTM_COMBINE_SYNCEN3_MASK | FTM_COMBINE_SYNCEN2_MASK
- | FTM_COMBINE_SYNCEN1_MASK | FTM_COMBINE_SYNCEN0_MASK;
- pwmp->ftm->SYNCONF = FTM_SYNCONF_SYNCMODE_MASK;
-
- pwmp->ftm->CNTIN = 0x0000;
- //~ pwmp->ftm->SC = 0; /* Disable FTM counter.*/
- pwmp->ftm->CNT = 0x0000; /* Clear count register.*/
-
- /* Prescaler value calculation.*/
- psc = (KINETIS_SYSCLK_FREQUENCY / pwmp->config->frequency);
- //~ /* Prescaler must be power of two between 1 and 128.*/
- osalDbgAssert(psc <= 128 && !(psc & (psc - 1)), "invalid frequency");
- //~ /* Prescaler register value determination.
- //~ Prescaler register value conveniently corresponds to bit position,
- //~ i.e., register value for prescaler CLK/64 is 6 ((1 << 6) == 64).*/
- for (i = 0; i < 8; i++) {
- if (psc == (unsigned)(1 << i)) {
- break;
- }
+ /* Set PWM output lines */
+ for (i=0; i<PWM_CHANNELS; i++) {
+ const PWMChannelConfig *cfg_channel = &pwmp->config->channels[i];
+ uint32_t gpio_pin = PAL_PAD(cfg_channel->ioline);
+ if (cfg_channel->mode == PWM_OUTPUT_DISABLED) {
+ gpio_pin = PAL_NOLINE;
+ }
+
+ pwmp->pwm->PSEL.OUT[i] = gpio_pin << PWM_PSEL_OUT_PIN_Pos;
}
- /* Set prescaler and clock mode.
- This also sets the following:
- CPWMS up-counting mode
- Timer overflow interrupt disabled
- DMA disabled.*/
- pwmp->ftm->SC = FTM_SC_CLKS(1) | FTM_SC_PS(i);
- /* Configure period */
- pwmp->ftm->MOD = pwmp->period-1;
- pwmp->ftm->PWMLOAD = FTM_PWMLOAD_LDOK_MASK;
+ /* Enable PWM */
+ pwmp->pwm->ENABLE = PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos;
+
+ /* Set mode */
+ pwmp->pwm->MODE = PWM_MODE_UPDOWN_Up & PWM_MODE_UPDOWN_Msk;
+
+ /* Set prescaler */
+ pwmp->pwm->PRESCALER = psc_value & PWM_PRESCALER_PRESCALER_Msk;
+
+ /* Set period */
+ pwmp->pwm->COUNTERTOP = pwmp->period & PWM_COUNTERTOP_COUNTERTOP_Msk;
+
+ pwmp->pwm->LOOP = PWM_LOOP_CNT_Disabled & PWM_LOOP_CNT_Msk;
+ pwmp->pwm->DECODER = (PWM_DECODER_LOAD_Individual << PWM_DECODER_LOAD_Pos) |
+ (PWM_DECODER_MODE_RefreshCount << PWM_DECODER_MODE_Pos);
+
+ pwmp->pwm->SEQ[0].PTR = ((uint32_t)(pwm_seq) << PWM_SEQ_PTR_PTR_Pos);
+ pwmp->pwm->SEQ[0].CNT = ((sizeof(pwm_seq) / sizeof(uint16_t)) << PWM_SEQ_CNT_CNT_Pos);
+ pwmp->pwm->SEQ[0].REFRESH = 0;
+ pwmp->pwm->SEQ[0].ENDDELAY = 0;
+
+ pwmp->pwm->SEQ[1].PTR = ((uint32_t)(pwm_seq) << PWM_SEQ_PTR_PTR_Pos);
+ pwmp->pwm->SEQ[1].CNT = ((sizeof(pwm_seq) / sizeof(uint16_t)) << PWM_SEQ_CNT_CNT_Pos);
+ pwmp->pwm->SEQ[1].REFRESH = 0;
+ pwmp->pwm->SEQ[1].ENDDELAY = 0;
+
+ /* With clear shortcuts for period */
+ pwmp->pwm->SHORTS = 0;
+
+ /* Disable and reset interrupts */
+ pwmp->pwm->INTEN = 0;
}
/**
@@ -245,33 +226,29 @@ void pwm_lld_start(PWMDriver *pwmp) { * @notapi
*/
void pwm_lld_stop(PWMDriver *pwmp) {
-
- /* If in ready state then disables the PWM clock.*/
- if (pwmp->state == PWM_READY) {
-#if KINETIS_PWM_USE_FTM0
- if (&PWMD1 == pwmp) {
- SIM->SCGC6 &= ~SIM_SCGC6_FTM0;
- nvicDisableVector(FTM0_IRQn);
- }
+#if NRF5_PWM_USE_PWM0
+ if (&PWMD1 == pwmp) {
+ nvicDisableVector(PWM0_IRQn);
+ }
#endif
-#if KINETIS_PWM_USE_FTM1
- if (&PWMD2 == pwmp) {
- SIM->SCGC6 &= ~SIM_SCGC6_FTM1;
- nvicDisableVector(FTM1_IRQn);
- }
+#if NRF5_PWM_USE_PWM1
+ if (&PWMD2 == pwmp) {
+ nvicDisableVector(PWM1_IRQn);
+ }
#endif
-#if KINETIS_PWM_USE_FTM2
- if (&PWMD3 == pwmp) {
- SIM->SCGC3 &= ~SIM_SCGC3_FTM2;
- nvicDisableVector(FTM2_IRQn);
- }
-#endif
- /* Disable FTM counter.*/
- pwmp->ftm->SC = 0;
- pwmp->ftm->MOD = 0;
+#if NRF5_PWM_USE_PWM2
+ if (&PWMD3 == pwmp) {
+ nvicDisableVector(PWM2_IRQn);
}
+#endif
+
+ /* Stop PWM generation */
+ pwmp->pwm->TASKS_STOP = 1;
+
+ /* Disable PWM */
+ pwmp->pwm->ENABLE = (PWM_ENABLE_ENABLE_Disabled << PWM_ENABLE_ENABLE_Pos);
}
/**
@@ -290,23 +267,22 @@ void pwm_lld_stop(PWMDriver *pwmp) { void pwm_lld_enable_channel(PWMDriver *pwmp,
pwmchannel_t channel,
pwmcnt_t width) {
- uint32_t mode = FTM_CnSC_MSB; /* Edge-aligned PWM mode.*/
-
- switch (pwmp->config->channels[channel].mode & PWM_OUTPUT_MASK) {
- case PWM_OUTPUT_ACTIVE_HIGH:
- mode |= FTM_CnSC_ELSB;
- break;
- case PWM_OUTPUT_ACTIVE_LOW:
- mode |= FTM_CnSC_ELSA;
- break;
+ const PWMChannelConfig *cfg_channel = &pwmp->config->channels[channel];
+
+ /* Deal with corner case: 0% and 100% */
+ if ((width <= 0) || (width >= pwmp->period)) {
+ pwm_seq[channel] = pwmp->period & PWM_COUNTERTOP_COUNTERTOP_Msk;
+ if (cfg_channel->mode == PWM_OUTPUT_ACTIVE_LOW) pwm_seq[channel] |= 0x8000;
+ /* Really doing PWM */
+ } else {
+ pwm_seq[channel] = width & PWM_COUNTERTOP_COUNTERTOP_Msk;
+ if (cfg_channel->mode == PWM_OUTPUT_ACTIVE_HIGH) pwm_seq[channel] |= 0x8000;
}
- if (pwmp->ftm->CHANNEL[channel].CnSC & FTM_CnSC_CHIE)
- mode |= FTM_CnSC_CHIE;
+ pwmp->pwm->EVENTS_STOPPED = 0;
+ (void)pwmp->pwm->EVENTS_STOPPED;
- pwmp->ftm->CHANNEL[channel].CnSC = mode;
- pwmp->ftm->CHANNEL[channel].CnV = width;
- pwmp->ftm->PWMLOAD = FTM_PWMLOAD_LDOK_MASK;
+ pwmp->pwm->TASKS_SEQSTART[0] = 1;
}
/**
@@ -322,9 +298,15 @@ void pwm_lld_enable_channel(PWMDriver *pwmp, * @notapi
*/
void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
+ const PWMChannelConfig *cfg_channel = &pwmp->config->channels[channel];
+
+ pwm_seq[channel] = pwmp->period & PWM_COUNTERTOP_COUNTERTOP_Msk;
+ if (cfg_channel->mode == PWM_OUTPUT_ACTIVE_LOW) pwm_seq[channel] |= 0x8000;
- pwmp->ftm->CHANNEL[channel].CnSC = 0;
- pwmp->ftm->CHANNEL[channel].CnV = 0;
+ pwmp->pwm->EVENTS_STOPPED = 0;
+ (void)pwmp->pwm->EVENTS_STOPPED;
+
+ pwmp->pwm->TASKS_SEQSTART[0] = 1;
}
/**
@@ -337,7 +319,39 @@ void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { * @notapi
*/
void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) {
- pwmp->ftm->SC |= FTM_SC_TOIE;
+
+ /* Events clear */
+ pwmp->pwm->EVENTS_LOOPSDONE = 0;
+ pwmp->pwm->EVENTS_SEQEND[0] = 0;
+ pwmp->pwm->EVENTS_SEQEND[1] = 0;
+ pwmp->pwm->EVENTS_STOPPED = 0;
+#if CORTEX_MODEL >= 4
+ (void)pwmp->pwm->EVENTS_LOOPSDONE;
+ (void)pwmp->pwm->EVENTS_SEQEND[0];
+ (void)pwmp->pwm->EVENTS_SEQEND[1];
+ (void)pwmp->pwm->EVENTS_STOPPED;
+#endif
+
+ pwmp->pwm->INTENSET = PWM_INTENSET_PWMPERIODEND_Msk;
+
+ /* Enable interrupt */
+#if NRF5_PWM_USE_PWM0
+ if (&PWMD1 == pwmp) {
+ nvicEnableVector(PWM0_IRQn, NRF5_PWM_PWM0_PRIORITY);
+ }
+#endif
+
+#if NRF5_PWM_USE_PWM1
+ if (&PWMD2 == pwmp) {
+ nvicEnableVector(PWM1_IRQn, NRF5_PWM_PWM1_PRIORITY);
+ }
+#endif
+
+#if NRF5_PWM_USE_PWM2
+ if (&PWMD3 == pwmp) {
+ nvicEnableVector(PWM2_IRQn, NRF5_PWM_PWM2_PRIORITY);
+ }
+#endif
}
/**
@@ -350,7 +364,7 @@ void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) { * @notapi
*/
void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) {
- pwmp->ftm->SC &= ~FTM_SC_TOIE;
+ pwmp->pwm->INTENCLR = PWM_INTENCLR_PWMPERIODEND_Msk;
}
/**
@@ -366,7 +380,6 @@ void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) { */
void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
pwmchannel_t channel) {
- pwmp->ftm->CHANNEL[channel].CnSC |= FTM_CnSC_CHIE;
}
/**
@@ -375,14 +388,13 @@ void pwm_lld_enable_channel_notification(PWMDriver *pwmp, * @pre The channel must have been activated using @p pwmEnableChannel().
* @note If the notification is already disabled then the call has no effect.
*
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...channels-1)
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
*
* @notapi
*/
void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
- pwmchannel_t channel) {
- pwmp->ftm->CHANNEL[channel].CnSC &= ~FTM_CnSC_CHIE;
+ pwmchannel_t channel) {
}
#endif /* HAL_USE_PWM */
diff --git a/os/hal/ports/KINETIS/MK66F18/hal_pwm_lld.h b/os/hal/ports/NRF5/LLD/PWMv2/hal_pwm_lld.h index 9332e34..647b95e 100644 --- a/os/hal/ports/KINETIS/MK66F18/hal_pwm_lld.h +++ b/os/hal/ports/NRF5/LLD/PWMv2/hal_pwm_lld.h @@ -1,5 +1,5 @@ /*
- ChibiOS/HAL - Copyright (C) 2014 Adam J. Porter
+ ChibiOS/HAL - Copyright (C) 2018 Andru
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,8 +15,8 @@ */
/**
- * @file MK66F18/pwm_lld.h
- * @brief KINETIS PWM subsystem low level driver header.
+ * @file hal_pwm_lld.h
+ * @brief NRF52 PWM subsystem low level driver header.
*
* @addtogroup PWM
* @{
@@ -34,69 +34,34 @@ /**
* @brief Number of PWM channels per PWM driver.
*/
-#define PWM_CHANNELS 8
+#define PWM_CHANNELS 4
+
+typedef enum {
+ PWM_FREQUENCY_16MHZ = 16000000, /** @brief 16MHz */
+ PWM_FREQUENCY_8MHZ = 8000000, /** @brief 8MHz */
+ PWM_FREQUENCY_4MHZ = 4000000, /** @brief 4MHz */
+ PWM_FREQUENCY_2MHZ = 2000000, /** @brief 2MHz */
+ PWM_FREQUENCY_1MHZ = 1000000, /** @brief 1MHz */
+ PWM_FREQUENCY_500KHZ = 500000, /** @brief 500kHz */
+ PWM_FREQUENCY_250KHZ = 250000, /** @brief 250kHz */
+ PWM_FREQUENCY_125KHZ = 125000, /** @brief 125kHz */
+} pwm_frequency_t;
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
-#if !defined(KINETIS_PWM_USE_FTM0)
- #define KINETIS_PWM_USE_FTM0 FALSE
-#endif
-
-#if !defined(KINETIS_PWM_USE_FTM1)
- #define KINETIS_PWM_USE_FTM1 FALSE
-#endif
-
-#if !defined(KINETIS_PWM_USE_FTM2)
- #define KINETIS_PWM_USE_FTM2 FALSE
-#endif
-
-/**
- * @brief FTM0 interrupt priority level setting.
- */
-#if !defined(KINETIS_PWM_FTM0_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_PWM_FTM0_PRIORITY 12
-#endif
-
-/**
- * @brief FTM1 interrupt priority level setting.
- */
-#if !defined(KINETIS_PWM_FTM1_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_PWM_FTM1_PRIORITY 12
-#endif
-
-/**
- * @brief FTM2 interrupt priority level setting.
- */
-#if !defined(KINETIS_PWM_FTM2_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_PWM_FTM2_PRIORITY 12
-#endif
-
-/** @} */
-
/**
* @name Configuration options
* @{
*/
-/**
- * @brief If advanced timer features switch.
- * @details If set to @p TRUE the advanced features for TIM1 and TIM8 are
- * enabled.
- * @note The default is @p TRUE.
- */
-#if !defined(KINETIS_PWM_USE_ADVANCED) || defined(__DOXYGEN__)
-#define KINETIS_PWM_USE_ADVANCED FALSE
-#endif
+
/** @} */
/*===========================================================================*/
/* Configuration checks. */
/*===========================================================================*/
-#if !KINETIS_PWM_USE_FTM0 && !KINETIS_PWM_USE_FTM1 && !KINETIS_PWM_USE_FTM2
-#error "PWM driver activated but no FTM peripheral assigned"
-#endif
/*===========================================================================*/
/* Driver data structures and types. */
@@ -138,6 +103,15 @@ typedef struct { */
pwmcallback_t callback;
/* End of the mandatory fields.*/
+
+ /**
+ * @brief PAL line to toggle.
+ * @note Only used if mode is PWM_OUTPUT_HIGH or PWM_OUTPUT_LOW.
+ * @note When channel enabled it wont be possible to access this PAL line using the PAL
+ * driver.
+ */
+ ioline_t ioline;
+
} PWMChannelConfig;
/**
@@ -149,7 +123,7 @@ typedef struct { * @note The low level can use assertions in order to catch invalid
* frequency specifications.
*/
- uint32_t frequency;
+ pwm_frequency_t frequency;
/**
* @brief PWM period in ticks.
* @note The low level can use assertions in order to catch invalid
@@ -198,9 +172,9 @@ struct PWMDriver { #endif
/* End of the mandatory fields.*/
/**
- * @brief Pointer to the FTM registers block.
+ * @brief Pointer to the PWM registers block.
*/
- FTM_TypeDef *ftm;
+ NRF_PWM_Type *pwm;
};
/*===========================================================================*/
@@ -223,23 +197,22 @@ struct PWMDriver { *
* @notapi
*/
-#define pwm_lld_change_period(pwmp, period) \
+#define pwm_lld_change_period(pwmp, period) \
do { \
- (pwmp)->ftm->MOD = ((period) - 1); \
- pwmp->ftm->PWMLOAD = FTM_PWMLOAD_LDOK_MASK;\
+ (pwmp)->pwm->COUNTERTOP = period & PWM_COUNTERTOP_COUNTERTOP_Msk; \
} while(0)
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
-#if KINETIS_PWM_USE_FTM0 || defined(__DOXYGEN__)
+#if NRF5_PWM_USE_PWM0 || defined(__DOXYGEN__)
extern PWMDriver PWMD1;
#endif
-#if KINETIS_PWM_USE_FTM1 || defined(__DOXYGEN__)
+#if NRF5_PWM_USE_PWM1 || defined(__DOXYGEN__)
extern PWMDriver PWMD2;
#endif
-#if KINETIS_PWM_USE_FTM2 || defined(__DOXYGEN__)
+#if NRF5_PWM_USE_PWM2 || defined(__DOXYGEN__)
extern PWMDriver PWMD3;
#endif
diff --git a/os/hal/ports/NRF5/LLD/QDECv1/driver.mk b/os/hal/ports/NRF5/LLD/QDECv1/driver.mk new file mode 100644 index 0000000..de18c39 --- /dev/null +++ b/os/hal/ports/NRF5/LLD/QDECv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_QEI TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/QDECv1/hal_qei_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/QDECv1/hal_qei_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/QDECv1
diff --git a/os/hal/ports/NRF5/LLD/hal_qei_lld.c b/os/hal/ports/NRF5/LLD/QDECv1/hal_qei_lld.c index d3b99cd..f0c24c9 100644 --- a/os/hal/ports/NRF5/LLD/hal_qei_lld.c +++ b/os/hal/ports/NRF5/LLD/QDECv1/hal_qei_lld.c @@ -15,8 +15,8 @@ */
/**
- * @file NRF51/hal_qei_lld.c
- * @brief NRF51 QEI subsystem low level driver.
+ * @file QDECv1/hal_qei_lld.c
+ * @brief NRF5 QEI subsystem low level driver.
*
* @addtogroup QEI
* @{
diff --git a/os/hal/ports/NRF5/LLD/hal_qei_lld.h b/os/hal/ports/NRF5/LLD/QDECv1/hal_qei_lld.h index 85c96a5..f4db11e 100644 --- a/os/hal/ports/NRF5/LLD/hal_qei_lld.h +++ b/os/hal/ports/NRF5/LLD/QDECv1/hal_qei_lld.h @@ -15,8 +15,8 @@ */
/**
- * @file NRF51/hal_qei_lld.h
- * @brief NRF51 QEI subsystem low level driver header.
+ * @file QDECv1/hal_qei_lld.h
+ * @brief NRF5 QEI subsystem low level driver header.
*
* @note Not tested with LED pin
*
diff --git a/os/hal/ports/NRF5/LLD/RNGv1/driver.mk b/os/hal/ports/NRF5/LLD/RNGv1/driver.mk new file mode 100644 index 0000000..c128aae --- /dev/null +++ b/os/hal/ports/NRF5/LLD/RNGv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_RNG TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/RNGv1/hal_rng_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/RNGv1/hal_rng_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/RNGv1
diff --git a/os/hal/ports/NRF5/LLD/hal_rng_lld.c b/os/hal/ports/NRF5/LLD/RNGv1/hal_rng_lld.c index 9712150..bf9382c 100644 --- a/os/hal/ports/NRF5/LLD/hal_rng_lld.c +++ b/os/hal/ports/NRF5/LLD/RNGv1/hal_rng_lld.c @@ -15,7 +15,7 @@ */ /** - * @file NRF5/LLD/hal_rng_lld.c + * @file RNGv1/hal_rng_lld.c * @brief NRF5 RNG subsystem low level driver source. * * @addtogroup RNG diff --git a/os/hal/ports/NRF5/LLD/hal_rng_lld.h b/os/hal/ports/NRF5/LLD/RNGv1/hal_rng_lld.h index 5c56be2..a74f6ef 100644 --- a/os/hal/ports/NRF5/LLD/hal_rng_lld.h +++ b/os/hal/ports/NRF5/LLD/RNGv1/hal_rng_lld.h @@ -15,7 +15,7 @@ */ /** - * @file NRF5/LLD/hal_rng_lld.h + * @file RNGv1/hal_rng_lld.h * @brief NRF5 RNG subsystem low level driver header. * * @addtogroup RNG diff --git a/os/hal/ports/NRF5/LLD/SPIv1/driver.mk b/os/hal/ports/NRF5/LLD/SPIv1/driver.mk new file mode 100644 index 0000000..d583a68 --- /dev/null +++ b/os/hal/ports/NRF5/LLD/SPIv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/SPIv1/hal_spi_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/SPIv1/hal_spi_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/SPIv1
diff --git a/os/hal/ports/NRF5/LLD/hal_spi_lld.c b/os/hal/ports/NRF5/LLD/SPIv1/hal_spi_lld.c index 2c6ec91..3e0bc83 100644 --- a/os/hal/ports/NRF5/LLD/hal_spi_lld.c +++ b/os/hal/ports/NRF5/LLD/SPIv1/hal_spi_lld.c @@ -15,7 +15,7 @@ */
/**
- * @file NRF5/LLD/hal_spi_lld.c
+ * @file SPIv1/hal_spi_lld.c
* @brief NRF5 low level SPI driver code.
*
* @addtogroup SPI
@@ -26,6 +26,11 @@ #if HAL_USE_SPI || defined(__DOXYGEN__)
+#if NRF_SERIES == 52
+#define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn
+#define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn
+#endif
+
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
diff --git a/os/hal/ports/NRF5/LLD/hal_spi_lld.h b/os/hal/ports/NRF5/LLD/SPIv1/hal_spi_lld.h index afad5ab..1c6d858 100644 --- a/os/hal/ports/NRF5/LLD/hal_spi_lld.h +++ b/os/hal/ports/NRF5/LLD/SPIv1/hal_spi_lld.h @@ -15,7 +15,7 @@ */
/**
- * @file NRF/LLD/hal_spi_lld.h
+ * @file SPIv1/hal_spi_lld.h
* @brief NRF5 low level SPI driver header.
*
* @addtogroup SPI
diff --git a/os/hal/ports/NRF5/LLD/TIMERv1/driver.mk b/os/hal/ports/NRF5/LLD/TIMERv1/driver.mk new file mode 100644 index 0000000..333fe3c --- /dev/null +++ b/os/hal/ports/NRF5/LLD/TIMERv1/driver.mk @@ -0,0 +1,13 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/TIMERv1/hal_gpt_lld.c
+endif
+ifneq ($(findstring HAL_USE_ICU TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/TIMERv1/hal_icu_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/TIMERv1/hal_gpt_lld.c
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/TIMERv1/hal_icu_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/TIMERv1
diff --git a/os/hal/ports/NRF5/LLD/hal_gpt_lld.c b/os/hal/ports/NRF5/LLD/TIMERv1/hal_gpt_lld.c index 20dbcef..aaff432 100644 --- a/os/hal/ports/NRF5/LLD/hal_gpt_lld.c +++ b/os/hal/ports/NRF5/LLD/TIMERv1/hal_gpt_lld.c @@ -15,7 +15,7 @@ */
/**
- * @file NRF5/LLD/hal_gpt_lld.c
+ * @file TIMERv1/hal_gpt_lld.c
* @brief NRF5 GPT subsystem low level driver source.
*
* @addtogroup GPT
diff --git a/os/hal/ports/NRF5/LLD/hal_gpt_lld.h b/os/hal/ports/NRF5/LLD/TIMERv1/hal_gpt_lld.h index 4173a3a..d362106 100644 --- a/os/hal/ports/NRF5/LLD/hal_gpt_lld.h +++ b/os/hal/ports/NRF5/LLD/TIMERv1/hal_gpt_lld.h @@ -15,7 +15,7 @@ */
/**
- * @file NRF5/LLD/gpt_lld.h
+ * @file TIMERv1/gpt_lld.h
* @brief NRF5 GPT subsystem low level driver header.
*
* @addtogroup GPT
diff --git a/os/hal/ports/NRF5/LLD/TIMERv1/hal_icu_lld.c b/os/hal/ports/NRF5/LLD/TIMERv1/hal_icu_lld.c new file mode 100644 index 0000000..bca8855 --- /dev/null +++ b/os/hal/ports/NRF5/LLD/TIMERv1/hal_icu_lld.c @@ -0,0 +1,749 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * Hardware Abstraction Layer for Extended Input Capture Unit + */ +#include "hal.h" + +#if (HAL_USE_ICU == TRUE) || defined(__DOXYGEN__) + +/** + * @brief Returns the compare value of the latest cycle. + * + * @param[in] chp Pointer to channel structure that fired the interrupt. + * @return The number of ticks. + * + * @notapi + */ +//#define icu_lld_get_compare(chp) (*((chp)->ccp) + 1) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief ICUD1 driver identifier. + * @note The driver ICUD1 allocates the complex timer TIMER0 when enabled. + */ +#if NRF5_ICU_USE_TIMER0 && !defined(__DOXYGEN__) +ICUDriver ICUD1; +#endif + +/** + * @brief ICUD2 driver identifier. + * @note The driver ICUD2 allocates the timer TIMER1 when enabled. + */ +#if NRF5_ICU_USE_TIMER1 && !defined(__DOXYGEN__) +ICUDriver ICUD2; +#endif + +/** + * @brief ICUD3 driver identifier. + * @note The driver ICUD3 allocates the timer TIMER2 when enabled. + */ +#if NRF5_ICU_USE_TIMER2 && !defined(__DOXYGEN__) +ICUDriver ICUD3; +#endif + +/** + * @brief ICUD4 driver identifier. + * @note The driver ICUD4 allocates the timer TIMER3 when enabled. + */ +#if NRF5_ICU_USE_TIMER3 && !defined(__DOXYGEN__) +ICUDriver ICUD4; +#endif + +/** + * @brief ICUD5 driver identifier. + * @note The driver ICUD5 allocates the timer TIMER4 when enabled. + */ +#if NRF5_ICU_USE_TIMER4 && !defined(__DOXYGEN__) +ICUDriver ICUD5; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ +/** + * @brief Returns pulse width. + * @details The time is defined as number of ticks. + * + * @param[in] icup Pointer to the ICUDriver object. + * @param[in] channel The timer channel that fired the interrupt. + * @param[in] compare Content of the CC register. + * @return The number of ticks. + * + * @notapi + */ +static icucnt_t get_time_width(const ICUDriver *icup, + uint8_t channel, + icucnt_t compare) { + + const ICUChannel *chp = &icup->channel[channel]; + + /* Note! there is no overflow check because it handles under the hood of + unsigned subtraction math.*/ + return compare - chp->last_idle; +} + +/** + * @brief Returns pulse period. + * @details The time is defined as number of ticks. + * + * @param[in] icup Pointer to the ICUDriver object. + * @param[in] channel The timer channel that fired the interrupt. + * @param[in] compare Content of the CC register. + * @return The number of ticks. + * + * @notapi + */ +static icucnt_t get_time_period(const ICUDriver *icup, + uint8_t channel, + icucnt_t compare) { + + const ICUChannel *chp = &icup->channel[channel]; + + /* Note! there is no overflow check because it handles under the hood of + unsigned subtraction math.*/ + return compare - chp->last_idle; +} + +/** + * @brief ICU width event. + * + * @param[in] icup Pointer to the @p ICUDriver object + * @param[in] channel The timer channel that fired the interrupt. + * + * @notapi + */ +static void _isr_invoke_width_cb(ICUDriver *icup, uint8_t channel) { + ICUChannel *chp = &icup->channel[channel]; + icucnt_t compare = icup->timer->CC[channel+2]; + chp->last_active = compare; + if (ICU_CH_ACTIVE == chp->state) { + icup->result.width = get_time_width(icup, channel, compare); + if ((icup->state == ICU_ACTIVE) && (icup->config->width_cb != NULL)) + icup->config->width_cb(icup); + chp->state = ICU_CH_IDLE; + } +} + +/** + * @brief ICU period detect event. + * + * @param[in] icup Pointer to the @p ICUDriver object + * @param[in] channel The timer channel that fired the interrupt. + * + * @notapi + */ +static void _isr_invoke_period_cb(ICUDriver *icup, uint8_t channel) { + ICUChannel *chp = &icup->channel[channel]; + icucnt_t compare = (uint32_t)icup->timer->CC[channel]; + icup->result.period = get_time_period(icup, channel, compare); + chp->last_idle = compare; + chp->state = ICU_CH_ACTIVE; + if ((icup->state == ICU_ACTIVE) && (icup->config->period_cb != NULL)) + icup->config->period_cb(icup); + icup->state = ICU_ACTIVE; + /* Set overflow timeout */ + icup->timer->CC[channel] = compare + ICU_WAIT_TIMEOUT; +} + +/** + * @brief Shared IRQ handler. + * + * @param[in] icup Pointer to the @p ICUDriver object + */ +void icu_lld_serve_gpiote_interrupt(ICUDriver *icup) { + uint8_t ch; + for (ch=0; ch<ICU_CHANNELS; ch++) { + const ICUChannelConfig *cfg_channel = &icup->config->iccfgp[ch]; + const uint8_t *gpiote_channel = cfg_channel->gpiote_channel; + + /* Period event */ + if (NRF_GPIOTE->INTENSET & (1 << gpiote_channel[0]) && NRF_GPIOTE->EVENTS_IN[gpiote_channel[0]]) { + _isr_invoke_period_cb(icup, ch); + NRF_GPIOTE->EVENTS_IN[gpiote_channel[0]] = 0; + (void) NRF_GPIOTE->EVENTS_IN[gpiote_channel[0]]; + } + /* Width event */ + if (NRF_GPIOTE->INTENSET & (1 << gpiote_channel[1]) && NRF_GPIOTE->EVENTS_IN[gpiote_channel[1]]) { + _isr_invoke_width_cb(icup, ch); + NRF_GPIOTE->EVENTS_IN[gpiote_channel[1]] = 0; + (void) NRF_GPIOTE->EVENTS_IN[gpiote_channel[1]]; + } + } +} + +/** + * @brief Overflow IRQ handler. + * + * @param[in] icup Pointer to the @p ICUDriver object + */ +void icu_lld_serve_interrupt(ICUDriver *icup) { + uint8_t ch; + for (ch=0; ch<ICU_CHANNELS; ch++) { + /* Clear overflow events */ + if (icup->timer->INTENSET & (1 << (TIMER_INTENSET_COMPARE0_Pos + ch)) && + icup->timer->EVENTS_COMPARE[ch]) { + icup->timer->EVENTS_COMPARE[ch] = 0; + (void) icup->timer->EVENTS_COMPARE[ch]; + /* Set next overlow compare */ + icup->timer->CC[ch] = icup->timer->CC[ch] + ICU_WAIT_TIMEOUT; + } + } + if (icup->config->overflow_cb != NULL) + icup->config->overflow_cb(icup); + icup->state = ICU_WAITING; +} + +/** + * @brief Starts every channel. + * + * @param[in] icup Pointer to the @p ICUDriver object + * + * @note GPIO Line[0] -> GPIOTE channel[0] will detect start edge. + * @note GPIO Line[1] -> GPIOTE channel[1] will detect end edge. + */ +static void start_channels(ICUDriver *icup) { + + /* Set each input channel that is used as: a normal input capture channel. */ +#if NRF5_ICU_USE_GPIOTE_PPI + uint8_t channel; + for (channel = 0; channel<ICU_CHANNELS; channel++) { + const ICUChannelConfig *cfg_channel = &icup->config->iccfgp[channel]; + if (cfg_channel->mode == ICU_INPUT_DISABLED) continue; + + const uint32_t gpio_pin0 = PAL_PAD(cfg_channel->ioline[0]); + const uint32_t gpio_pin1 = PAL_PAD(cfg_channel->ioline[1]); + osalDbgAssert((gpio_pin0 < 32) && + (gpio_pin1 < 32) && + (gpio_pin0 != gpio_pin1), + "invalid Line configuration"); + + /* NRF52832 GPIOTE channels 0..7 */ + const uint8_t *gpiote_channel = cfg_channel->gpiote_channel; + osalDbgAssert((gpiote_channel[0] < 8) && + (gpiote_channel[1] < 8) && + (gpiote_channel[0] != gpiote_channel[1]), + "invalid GPIOTE configuration"); + + /* NRF52832 PPI channels 0..19 */ + const uint8_t *ppi_channel = cfg_channel->ppi_channel; + osalDbgAssert((gpiote_channel[0] < 20) && + (gpiote_channel[1] < 20) && + (gpiote_channel[0] != gpiote_channel[1]), + "invalid PPI configuration"); + + /* Program PPI events for period */ + NRF_PPI->CH[ppi_channel[0]].EEP = (uint32_t) &NRF_GPIOTE->EVENTS_IN[gpiote_channel[0]]; + NRF_PPI->CH[ppi_channel[0]].TEP = (uint32_t) &icup->timer->TASKS_CAPTURE[channel]; + + /* Program PPI events for width */ + NRF_PPI->CH[ppi_channel[1]].EEP = (uint32_t) &NRF_GPIOTE->EVENTS_IN[gpiote_channel[1]]; + NRF_PPI->CH[ppi_channel[1]].TEP = (uint32_t) &icup->timer->TASKS_CAPTURE[channel+2]; + + /* Disable GPIOTE interrupts */ + NRF_GPIOTE->INTENCLR = (GPIOTE_INTENCLR_PORT_Clear << GPIOTE_INTENCLR_PORT_Pos) | + (1 << gpiote_channel[0]) | (1 << gpiote_channel[1]); + NRF_GPIOTE->EVENTS_PORT = 1; + + /* Clear GPIOTE channels */ + NRF_GPIOTE->CONFIG[gpiote_channel[0]] &= ~(GPIOTE_CONFIG_PSEL_Msk | GPIOTE_CONFIG_POLARITY_Msk); + NRF_GPIOTE->CONFIG[gpiote_channel[1]] &= ~(GPIOTE_CONFIG_PSEL_Msk | GPIOTE_CONFIG_POLARITY_Msk); + + /* Set GPIOTE channels */ + if (cfg_channel->mode == ICU_INPUT_ACTIVE_HIGH) { + NRF_GPIOTE->CONFIG[gpiote_channel[0]] = + (GPIOTE_CONFIG_MODE_Event << GPIOTE_CONFIG_MODE_Pos) | + ((gpio_pin0 << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PSEL_Msk) | + ((GPIOTE_CONFIG_POLARITY_LoToHi << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk); + NRF_GPIOTE->CONFIG[gpiote_channel[1]] = + (GPIOTE_CONFIG_MODE_Event << GPIOTE_CONFIG_MODE_Pos) | + ((gpio_pin1 << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PSEL_Msk) | + ((GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk); + } else { + NRF_GPIOTE->CONFIG[gpiote_channel[0]] = + (GPIOTE_CONFIG_MODE_Event << GPIOTE_CONFIG_MODE_Pos) | + ((gpio_pin0 << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PSEL_Msk) | + ((GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos) + & GPIOTE_CONFIG_POLARITY_Msk); + NRF_GPIOTE->CONFIG[gpiote_channel[1]] = + (GPIOTE_CONFIG_MODE_Event << GPIOTE_CONFIG_MODE_Pos) | + ((gpio_pin1 << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PSEL_Msk) | + ((GPIOTE_CONFIG_POLARITY_LoToHi << GPIOTE_CONFIG_POLARITY_Pos) + & GPIOTE_CONFIG_POLARITY_Msk); + } + } +#endif + +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if NRF5_ICU_USE_TIMER0 +/** + * @brief TIMER0 compare interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector60) { + + OSAL_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD1); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* NRF5_ICU_USE_TIMER0 */ + +#if NRF5_ICU_USE_TIMER1 +/** + * @brief TIMER1 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector64) { + + OSAL_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD2); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* NRF5_ICU_USE_TIMER1 */ + +#if NRF5_ICU_USE_TIMER2 +/** + * @brief TIMER2 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector68) { + + OSAL_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD3); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* NRF5_ICU_USE_TIMER2 */ + +#if NRF5_ICU_USE_TIMER3 +/** + * @brief TIMER3 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(VectorA8) { + + OSAL_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD4); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* NRF5_ICU_USE_TIMER3 */ + +#if NRF5_ICU_USE_TIMER4 +/** + * @brief TIMER4 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(VectorAC) { + + OSAL_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD5); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* NRF5_ICU_USE_TIMER4 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ICU driver initialization. + * + * @notapi + */ +void icu_lld_init(void) { +#if NRF5_ICU_USE_TIMER0 + /* Driver initialization.*/ + icuObjectInit(&ICUD1); + ICUD1.timer = NRF_TIMER0; +#endif + +#if NRF5_ICU_USE_TIMER1 + /* Driver initialization.*/ + icuObjectInit(&ICUD2); + ICUD2.timer = NRF_TIMER1; +#endif + +#if NRF5_ICU_USE_TIMER2 + /* Driver initialization.*/ + icuObjectInit(&ICUD3); + ICUD3.timer = NRF_TIMER2; +#endif + +#if NRF5_ICU_USE_TIMER3 + /* Driver initialization.*/ + icuObjectInit(&ICUD4); + ICUD4.timer = NRF_TIMER3; +#endif + +#if NRF5_ICU_USE_TIMER4 + /* Driver initialization.*/ + icuObjectInit(&ICUD5); + ICUD5.timer = NRF_TIMER4; +#endif +} + +/** + * @brief Configures and activates the ICU peripheral. + * + * @param[in] icup Pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_start(ICUDriver *icup) { + size_t ch; + osalDbgAssert((&icup->config->iccfgp[0] != NULL) || + (&icup->config->iccfgp[1] != NULL), + "invalid input configuration"); + /* Prescaler value calculation: ftimer = 16MHz / 2^PRESCALER */ + uint16_t psc_ratio = 16000000 / icup->config->frequency; + /* Prescaler ratio must be between 1 and 512, and a power of two. */ + osalDbgAssert(psc_ratio <= 512 && !(psc_ratio & (psc_ratio - 1)), + "invalid frequency"); + /* Prescaler value as a power of 2, must be 0..9 */ + uint32_t psc_value; + for (psc_value = 0; psc_value < 10; psc_value++) + if (psc_ratio == (unsigned)(1 << psc_value)) + break; + + /* Configure as 32bits timer */ + icup->timer->BITMODE = TIMER_BITMODE_BITMODE_32Bit; + + /* Set timer mode */ + icup->timer->MODE = TIMER_MODE_MODE_Timer; + + /* Set prescaler */ + icup->timer->PRESCALER = psc_value; + + /* With clear shortcuts. */ + icup->timer->SHORTS = 0; + + /* Clear Timer */ + icup->timer->TASKS_CLEAR = 1; + + /* Disable and reset interrupts for compare events */ + icup->timer->INTENCLR = (TIMER_INTENCLR_COMPARE0_Msk | + TIMER_INTENCLR_COMPARE1_Msk | + TIMER_INTENCLR_COMPARE2_Msk | + TIMER_INTENCLR_COMPARE3_Msk ); + + icup->timer->EVENTS_COMPARE[0] = 0; + icup->timer->EVENTS_COMPARE[1] = 0; + icup->timer->EVENTS_COMPARE[2] = 0; + icup->timer->EVENTS_COMPARE[3] = 0; + (void) icup->timer->EVENTS_COMPARE[0]; + (void) icup->timer->EVENTS_COMPARE[1]; + (void) icup->timer->EVENTS_COMPARE[2]; + (void) icup->timer->EVENTS_COMPARE[3]; + + /* Enable GPIOTE and TIMER interrupt vectors.*/ +#if NRF5_ICU_USE_GPIOTE_PPI + nvicEnableVector(GPIOTE_IRQn, NRF5_ICU_GPIOTE_IRQ_PRIORITY); +#endif +#if NRF5_ICU_USE_TIMER0 + if (&ICUD1 == icup) { + nvicEnableVector(TIMER0_IRQn, NRF5_ICU_TIMER0_IRQ_PRIORITY); + } +#endif +#if NRF5_ICU_USE_TIMER1 + if (&ICUD2 == icup) { + nvicEnableVector(TIMER1_IRQn, NRF5_ICU_TIMER1_IRQ_PRIORITY); + } +#endif +#if NRF5_ICU_USE_TIMER2 + if (&ICUD3 == icup) { + nvicEnableVector(TIMER2_IRQn, NRF5_ICU_TIMER2_IRQ_PRIORITY); + } +#endif +#if NRF5_ICU_USE_TIMER3 + if (&ICUD4 == icup) { + nvicEnableVector(TIMER3_IRQn, NRF5_ICU_TIMER3_IRQ_PRIORITY); + } +#endif +#if NRF5_ICU_USE_TIMER4 + if (&ICUD5 == icup) { + nvicEnableVector(TIMER4_IRQn, NRF5_ICU_TIMER4_IRQ_PRIORITY); + } +#endif + + /* clean channel structures and set pointers to channel configs */ + for (ch=0; ch<ICU_CHANNELS; ch++) { + icup->channel[ch].last_active = 0; + icup->channel[ch].last_idle = 0; + icup->channel[ch].state = ICU_CH_IDLE; + } + /* Set GPIOTE & PPI channels */ + start_channels(icup); +} + +/** + * @brief Deactivates the ICU peripheral. + * + * @param[in] icup Pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_stop(ICUDriver *icup) { + + if (icup->state == ICU_READY) { + /* Timer stop.*/ + icup->timer->TASKS_STOP = 1; + +#if NRF5_ICU_USE_GPIOTE_PPI + uint8_t channel; + for (channel = 0; channel<ICU_CHANNELS; channel++) { + const ICUChannelConfig *cfg_channel = &icup->config->iccfgp[channel]; + if (cfg_channel == NULL) continue; + + const uint8_t *gpiote_channel = cfg_channel->gpiote_channel; + const uint8_t *ppi_channel = cfg_channel->ppi_channel; + + /* Disable Timer interrupt */ + icup->timer->INTENCLR = 1 << (TIMER_INTENCLR_COMPARE0_Pos + channel); + + /* Disable GPIOTE interrupts */ + NRF_GPIOTE->INTENCLR = (1 << gpiote_channel[0]) | (1 << gpiote_channel[1]); + + /* Disable PPI channels */ + NRF_PPI->CHENCLR = ((1 << ppi_channel[0]) | (1 << ppi_channel[1])); + + /* Clear GPIOTE channels */ + NRF_GPIOTE->CONFIG[gpiote_channel[0]] &= ~(GPIOTE_CONFIG_PSEL_Msk | GPIOTE_CONFIG_POLARITY_Msk); + NRF_GPIOTE->CONFIG[gpiote_channel[1]] &= ~(GPIOTE_CONFIG_PSEL_Msk | GPIOTE_CONFIG_POLARITY_Msk); + } +#endif + +#if NRF5_ICU_USE_GPIOTE_PPI + nvicDisableVector(GPIOTE_IRQn); +#endif +#if NRF5_ICU_USE_TIMER0 + if (&ICUD1 == icup) { + nvicDisableVector(TIMER0_IRQn); + } +#endif +#if NRF5_ICU_USE_TIMER1 + if (&ICUD2 == icup) { + nvicDisableVector(TIMER1_IRQn); + } +#endif +#if NRF5_ICU_USE_TIMER2 + if (&ICUD3 == icup) { + nvicDisableVector(TIMER2_IRQn); + } +#endif +#if NRF5_ICU_USE_TIMER3 + if (&ICUD4 == icup) { + nvicDisableVector(TIMER3_IRQn); + } +#endif +#if NRF5_ICU_USE_TIMER4 + if (&ICUD5 == icup) { + nvicDisableVector(TIMER4_IRQn); + } +#endif + } +} + +/** + * @brief Starts the input capture. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_start_capture(ICUDriver *icup) { + /* Clear and start Timer */ + icup->timer->TASKS_CLEAR = 1; + icup->timer->TASKS_START = 1; + +#if NRF5_ICU_USE_GPIOTE_PPI + uint8_t channel; + for (channel = 0; channel<ICU_CHANNELS; channel++) { + const ICUChannelConfig *cfg_channel = &icup->config->iccfgp[channel]; + if (cfg_channel == NULL) continue; + + const uint8_t *gpiote_channel = cfg_channel->gpiote_channel; + const uint8_t *ppi_channel = cfg_channel->ppi_channel; + + /* Enable interrupt for overflow events */ + icup->timer->CC[channel] = ICU_WAIT_TIMEOUT; + icup->timer->INTENSET = 1 << (TIMER_INTENSET_COMPARE0_Pos + channel); + + /* Enable PPI channels */ + NRF_PPI->CHENSET = ((1 << ppi_channel[0]) | (1 << ppi_channel[1])); + + /* Enable GPIOTE interrupt */ + NRF_GPIOTE->INTENSET = (1 << gpiote_channel[0]) | (1 << gpiote_channel[1]); + } +#endif +} + +/** + * @brief Waits for a completed capture. + * @note The operation is performed in polled mode. + * @note In order to use this function notifications must be disabled. + * + * @param[in] icup pointer to the @p ICUDriver object + * @return The capture status. + * @retval false if the capture is successful. + * @retval true if a timer overflow occurred. + * + * @notapi + */ +bool icu_lld_wait_capture(ICUDriver *icup) { + + /* If the driver is still in the ICU_WAITING state then we need to wait + for the first activation edge.*/ + if (icup->state == ICU_WAITING) + if (icu_lld_wait_edge(icup)) + return true; + + /* This edge marks the availability of a capture result.*/ + return icu_lld_wait_edge(icup); +} + +/** + * @brief Stops the input capture. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_stop_capture(ICUDriver *icup) { + /* Timer stopped.*/ + icup->timer->TASKS_STOP = 1; + +#if NRF5_ICU_USE_GPIOTE_PPI + uint8_t channel; + for (channel = 0; channel<ICU_CHANNELS; channel++) { + const ICUChannelConfig *cfg_channel = &icup->config->iccfgp[channel]; + if (cfg_channel == NULL) continue; + + const uint8_t *gpiote_channel = cfg_channel->gpiote_channel; + const uint8_t *ppi_channel = cfg_channel->ppi_channel; + + /* Disable Timer interrupt for overflow events */ + icup->timer->INTENCLR = 1 << (TIMER_INTENCLR_COMPARE0_Pos + channel); + + /* Disable GPIOTE interrupt */ + NRF_GPIOTE->INTENCLR = (1 << gpiote_channel[0]) | (1 << gpiote_channel[1]); + + /* Disable PPI channels */ + NRF_PPI->CHENCLR = ((1 << ppi_channel[0]) | (1 << ppi_channel[1])); + } +#endif +} + +/** + * @brief Enables notifications. + * @pre The ICU unit must have been activated using @p icuStart() and the + * capture started using @p icuStartCapture(). + * @note If the notification is already enabled then the call has no effect. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_enable_notifications(ICUDriver *icup) { +#if NRF5_ICU_USE_GPIOTE_PPI + uint8_t channel; + for (channel = 0; channel<ICU_CHANNELS; channel++) { + const ICUChannelConfig *cfg_channel = &icup->config->iccfgp[channel]; + if (cfg_channel == NULL) continue; + + const uint8_t *gpiote_channel = cfg_channel->gpiote_channel; + + /* Enable Timer interrupt */ + icup->timer->INTENSET = 1 << (TIMER_INTENSET_COMPARE0_Pos + channel); + + /* Enable GPIOTE interrupt */ + NRF_GPIOTE->INTENSET = (1 << gpiote_channel[0]) | (1 << gpiote_channel[1]); + } +#endif +} + +/** + * @brief Disables notifications. + * @pre The ICU unit must have been activated using @p icuStart() and the + * capture started using @p icuStartCapture(). + * @note If the notification is already disabled then the call has no effect. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_disable_notifications(ICUDriver *icup) { + /* All interrupts disabled.*/ +#if NRF5_ICU_USE_GPIOTE_PPI + uint8_t channel; + for (channel = 0; channel<ICU_CHANNELS; channel++) { + const ICUChannelConfig *cfg_channel = &icup->config->iccfgp[channel]; + if (cfg_channel == NULL) continue; + + const uint8_t *gpiote_channel = cfg_channel->gpiote_channel; + + /* Disable Timer interrupt for overflow events */ + icup->timer->INTENCLR = 1 << (TIMER_INTENCLR_COMPARE0_Pos + channel); + + /* Disable GPIOTE interrupt */ + NRF_GPIOTE->INTENCLR = (1 << gpiote_channel[0]) | (1 << gpiote_channel[1]); + } +#endif + +} + +#endif /* HAL_USE_ICU */ diff --git a/os/hal/ports/NRF5/LLD/TIMERv1/hal_icu_lld.h b/os/hal/ports/NRF5/LLD/TIMERv1/hal_icu_lld.h new file mode 100644 index 0000000..7fcace7 --- /dev/null +++ b/os/hal/ports/NRF5/LLD/TIMERv1/hal_icu_lld.h @@ -0,0 +1,424 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* +*/ + +#ifndef HAL_ICU_LLD_H +#define HAL_ICU_LLD_H + +#if (HAL_USE_ICU == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ +/** + * @brief Number of ICU channels per ICU driver. + */ +#define ICU_CHANNELS 2 /* max channels */ +#define ICU_WAIT_TIMEOUT ( 0xFFFF ) /* first edge wait timeout */ + +#define ICU_FREQUENCY_16MHZ 16000000 /** @brief 16MHz */ +#define ICU_FREQUENCY_8MHZ 8000000 /** @brief 8MHz */ +#define ICU_FREQUENCY_4MHZ 4000000 /** @brief 4MHz */ +#define ICU_FREQUENCY_2MHZ 2000000 /** @brief 2MHz */ +#define ICU_FREQUENCY_1MHZ 1000000 /** @brief 1MHz */ +#define ICU_FREQUENCY_500KHZ 500000 /** @brief 500kHz */ +#define ICU_FREQUENCY_250KHZ 250000 /** @brief 250kHz */ +#define ICU_FREQUENCY_125KHZ 125000 /** @brief 125kHz */ +#define ICU_FREQUENCY_62500HZ 62500 /** @brief 62500Hz */ +#define ICU_FREQUENCY_31250HZ 31250 /** @brief 31250Hz */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief ICUD1 driver enable switch. + * @details If set to @p TRUE the support for ICUD1 is included. + * @note The default is @p TRUE. + */ +#if !defined(NRF5_ICU_USE_TIMER0) || defined(__DOXYGEN__) +#define NRF5_ICU_USE_TIMER0 FALSE +#endif + +/** + * @brief ICUD2 driver enable switch. + * @details If set to @p TRUE the support for ICUD2 is included. + * @note The default is @p TRUE. + */ +#if !defined(NRF5_ICU_USE_TIMER1) || defined(__DOXYGEN__) +#define NRF5_ICU_USE_TIMER1 FALSE +#endif + +/** + * @brief ICUD3 driver enable switch. + * @details If set to @p TRUE the support for ICUD3 is included. + * @note The default is @p TRUE. + */ +#if !defined(NRF5_ICU_USE_TIMER2) || defined(__DOXYGEN__) +#define NRF5_ICU_USE_TIMER2 FALSE +#endif + +/** + * @brief ICUD4 driver enable switch. + * @details If set to @p TRUE the support for ICUD4 is included. + * @note The default is @p TRUE. + */ +#if !defined(NRF5_ICU_USE_TIMER3) || defined(__DOXYGEN__) +#define NRF5_ICU_USE_TIMER3 FALSE +#endif + +/** + * @brief ICUD5 driver enable switch. + * @details If set to @p TRUE the support for ICUD5 is included. + * @note The default is @p TRUE. + */ +#if !defined(NRF5_ICU_USE_TIMER4) || defined(__DOXYGEN__) +#define NRF5_ICU_USE_TIMER4 FALSE +#endif + +/** + * @brief ICUD1 interrupt priority level setting. + */ +#if !defined(NRF5_ICU_TIMER0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define NRF5_ICU_TIMER0_IRQ_PRIORITY 3 +#endif + +/** + * @brief ICUD2 interrupt priority level setting. + */ +#if !defined(NRF5_ICU_TIMER1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define NRF5_ICU_TIMER1_IRQ_PRIORITY 3 +#endif + +/** + * @brief ICUD3 interrupt priority level setting. + */ +#if !defined(NRF5_ICU_TIMER2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define NRF5_ICU_TIMER2_IRQ_PRIORITY 3 +#endif + +/** + * @brief ICUD4 interrupt priority level setting. + */ +#if !defined(NRF5_ICU_TIMER3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define NRF5_ICU_TIMER3_IRQ_PRIORITY 3 +#endif + +/** + * @brief ICUD5 interrupt priority level setting. + */ +#if !defined(NRF5_ICU_TIMER4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define NRF5_ICU_TIMER4_IRQ_PRIORITY 3 +#endif + +/** + * @brief Allow driver to use GPIOTE/PPI to capture PAL line + */ +#if !defined(NRF5_ICU_USE_GPIOTE_PPI) +#define NRF5_ICU_USE_GPIOTE_PPI TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !NRF5_ICU_USE_TIMER0 && !NRF5_ICU_USE_TIMER1 && \ + !NRF5_ICU_USE_TIMER2 && !NRF5_ICU_USE_TIMER3 && \ + !NRF5_ICU_USE_TIMER4 +#error "ICU driver activated but no TIMER peripheral assigned" +#endif + +#if NRF5_ICU_USE_TIMER0 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_ICU_TIMER0_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIMER0" +#endif + +#if NRF5_ICU_USE_TIMER1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_ICU_TIMER1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIMER1" +#endif + +#if NRF5_ICU_USE_TIMER2 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_ICU_TIMER2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIMER2" +#endif + +#if NRF5_ICU_USE_TIMER3 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_ICU_TIMER3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIMER3" +#endif + +#if NRF5_ICU_USE_TIMER4 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_ICU_TIMER4_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIMER4" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ +/** + * @brief Active level selector. + */ +typedef enum { + ICU_INPUT_DISABLED, /**< Channel disabled . */ + ICU_INPUT_ACTIVE_HIGH, /**< Trigger on rising edge. */ + ICU_INPUT_ACTIVE_LOW, /**< Trigger on falling edge. */ +} icumode_t; + +/** + * @brief ICU channel state. + */ +typedef enum { + ICU_CH_IDLE = 0, /**< Not initialized. */ + ICU_CH_ACTIVE = 1 /**< First front detected. */ +} icuchannelstate_t; + +/** + * @brief ICU frequency type. + */ +typedef uint32_t icufreq_t; + +/** + * @brief ICU channel type. + */ +typedef enum { + ICU_CHANNEL_1 = 0, /**< Use TIMERx channel 0,2 */ + ICU_CHANNEL_2 = 1, /**< Use TIMERx channel 1,3 */ +} icuchannel_t; + +/** + * @brief ICU counter type. + */ +typedef uint32_t icucnt_t; + +/** + * @brief ICU captured width and (or) period. + */ +typedef struct { + /** + * @brief Pulse width. + */ + icucnt_t width; + /** + * @brief Pulse period. + */ + icucnt_t period; +} icuresult_t; + +/** + * @brief ICU Capture Channel Config structure definition. + */ +typedef struct { + /** + * @brief Specifies the channel capture mode. + */ + icumode_t mode; + +#if NRF5_ICU_USE_GPIOTE_PPI || defined(__DOXYGEN__) + /** + * @brief PAL line to capture. + * @note When NRF5_ICU_USE_GPIOTE_PPI is used and channel enabled, + * it wont be possible to access this PAL line using the PAL + * driver. + */ + ioline_t ioline[2]; + + /** + * @brief Unique GPIOTE channel to use. (2 channel) + * @note Only 8 GPIOTE channels are available on nRF52. + */ + uint8_t gpiote_channel[2]; + + /** + * @brief Unique PPI channels to use. (2 channels) + * @note Only 20 PPI channels are available on nRF52 + * (When Softdevice is enabled, only channels 0-7 are available) + */ + uint8_t ppi_channel[2]; +#endif +} ICUChannelConfig; + +/** + * @brief ICU Capture Channel structure definition. + */ +typedef struct { + /** + * @brief Channel state for the internal state machine. + */ + icuchannelstate_t state; + /** + * @brief Cached value for pulse width calculation. + */ + icucnt_t last_active; + /** + * @brief Cached value for period calculation. + */ + icucnt_t last_idle; + /** + * @brief Pointer to Input Capture channel configuration. + */ +// const ICUChannelConfig *config; +} ICUChannel; + +/** + * @brief ICU Config structure definition. + */ +typedef struct { + /** + * @brief Specifies the Timer clock in Hz. + */ + icufreq_t frequency; + /** + * @brief Callback for pulse width measurement. + */ + icucallback_t width_cb; + /** + * @brief Callback for cycle period measurement. + */ + icucallback_t period_cb; + /** + * @brief Callback for timer overflow. + */ + icucallback_t overflow_cb; + /** + * @brief Pointer to each Input Capture channel configuration. + * @note A NULL parameter indicates the channel as unused. + * @note In ICU mode, only Channel 1 OR Channel 2 may be used. + */ + const ICUChannelConfig iccfgp[ICU_CHANNELS]; +} ICUConfig; + +/** + * @brief ICU Driver structure definition + */ +struct ICUDriver { + /** + * @brief NRF52 timer peripheral for Input Capture. + */ + NRF_TIMER_Type *timer; + /** + * @brief Driver state for the internal state machine. + */ + icustate_t state; + /** + * @brief Channels' data structures. + */ + ICUChannel channel[ICU_CHANNELS]; + /** + * @brief Timer base clock. + */ + uint32_t clock; + /** + * @brief Pointer to configuration for the driver. + */ + const ICUConfig *config; + /** + * @brief Period, width last value. + */ + icuresult_t result; +#if defined(ICU_DRIVER_EXT_FIELDS) + ICU_DRIVER_EXT_FIELDS +#endif +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ +/** + * @brief Returns the width of the latest pulse. + * @details The pulse width is defined as number of ticks between the start + * edge and the stop edge. + * + * @param[in] icup pointer to the @p ICUDriver object + * @return The number of ticks. + * + * @notapi + */ +#define icu_lld_get_width(icup) ((uint32_t)((icup)->result.width)) + +/** + * @brief Returns the width of the latest cycle. + * @details The cycle width is defined as number of ticks between a start + * edge and the next start edge. + * + * @param[in] icup pointer to the @p ICUDriver object + * @return The number of ticks. + * + * @notapi + */ +#define icu_lld_get_period(icup) ((uint32_t)((icup)->result.period)) + +/** + * @brief Check on notifications status. + * + * @param[in] icup pointer to the @p ICUDriver object + * @return The notifications status. + * @retval false if notifications are not enabled. + * @retval true if notifications are enabled. + * + * @notapi + */ +#define icu_lld_are_notifications_enabled(icup) ( 1 ) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ +#if NRF5_ICU_USE_TIMER0 && !defined(__DOXYGEN__) +extern ICUDriver ICUD1; +#endif + +#if NRF5_ICU_USE_TIMER1 && !defined(__DOXYGEN__) +extern ICUDriver ICUD2; +#endif + +#if NRF5_ICU_USE_TIMER2 && !defined(__DOXYGEN__) +extern ICUDriver ICUD3; +#endif + +#if NRF5_ICU_USE_TIMER3 && !defined(__DOXYGEN__) +extern ICUDriver ICUD4; +#endif + +#if NRF5_ICU_USE_TIMER4 && !defined(__DOXYGEN__) +extern ICUDriver ICUD5; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void icu_lld_init(void); + void icu_lld_start(ICUDriver *icup); + void icu_lld_stop(ICUDriver *icup); + void icu_lld_start_capture(ICUDriver *icup); + bool icu_lld_wait_capture(ICUDriver *icup); + void icu_lld_stop_capture(ICUDriver *icup); + void icu_lld_enable_notifications(ICUDriver *icup); + void icu_lld_disable_notifications(ICUDriver *icup); + void icu_lld_serve_interrupt(ICUDriver *icup); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ICU */ + +#endif /* HAL_ICU_LLD_H */ diff --git a/os/hal/ports/NRF5/LLD/hal_st_lld.c b/os/hal/ports/NRF5/LLD/TIMERv1/hal_st_lld.c index 8e42029..20aa6e0 100644 --- a/os/hal/ports/NRF5/LLD/hal_st_lld.c +++ b/os/hal/ports/NRF5/LLD/TIMERv1/hal_st_lld.c @@ -16,7 +16,7 @@ */
/**
- * @file NRF5/LLD/hal_st_lld.c
+ * @file TIMERv1/hal_st_lld.c
* @brief NRF5 ST subsystem low level driver source.
*
* @addtogroup ST
diff --git a/os/hal/ports/NRF5/LLD/hal_st_lld.h b/os/hal/ports/NRF5/LLD/TIMERv1/hal_st_lld.h index 93c2abb..c026d2b 100644 --- a/os/hal/ports/NRF5/LLD/hal_st_lld.h +++ b/os/hal/ports/NRF5/LLD/TIMERv1/hal_st_lld.h @@ -15,7 +15,7 @@ */
/**
- * @file NRF5/LLD/st_lld.h
+ * @file TIMERv1/st_lld.h
* @brief NRF5 ST subsystem low level driver header.
* @details This header is designed to be include-able without having to
* include other files from the HAL.
diff --git a/os/hal/ports/NRF5/LLD/TWIMv1/driver.mk b/os/hal/ports/NRF5/LLD/TWIMv1/driver.mk new file mode 100644 index 0000000..43ad8e3 --- /dev/null +++ b/os/hal/ports/NRF5/LLD/TWIMv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/TWIMv1/hal_i2c_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/TWIMv1/hal_i2c_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/TWIMv1
diff --git a/os/hal/ports/NRF5/LLD/TWIMv1/hal_i2c_lld.c b/os/hal/ports/NRF5/LLD/TWIMv1/hal_i2c_lld.c new file mode 100644 index 0000000..7d5a26d --- /dev/null +++ b/os/hal/ports/NRF5/LLD/TWIMv1/hal_i2c_lld.c @@ -0,0 +1,420 @@ +/*
+ Copyright (C) 2018 andru
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file NRF5/NRF52832/hal_i2c_lld.c
+ * @brief NRF52 I2C subsystem low level driver source.
+ *
+ * @addtogroup I2C
+ * @{
+ */
+
+#include "osal.h"
+#include "hal.h"
+#include "nrf_delay.h"
+
+#if HAL_USE_I2C || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/* These macros are needed to see if the slave is stuck and we as master send dummy clock cycles to end its wait */
+#define I2C_HIGH(p) do { IOPORT1->OUTSET = (1UL << (p)); } while(0) /*!< Pulls I2C line high */
+#define I2C_LOW(p) do { IOPORT1->OUTCLR = (1UL << (p)); } while(0) /*!< Pulls I2C line low */
+#define I2C_INPUT(p) do { IOPORT1->DIRCLR = (1UL << (p)); } while(0) /*!< Configures I2C pin as input */
+#define I2C_OUTPUT(p) do { IOPORT1->DIRSET = (1UL << (p)); } while(0) /*!< Configures I2C pin as output */
+
+#define I2C_PIN_CNF(internal_pullup) \
+ ((GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \
+ | (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) \
+ | (((internal_pullup) ? GPIO_PIN_CNF_PULL_Pullup : GPIO_PIN_CNF_PULL_Disabled) << GPIO_PIN_CNF_PULL_Pos) \
+ | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \
+ | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos))
+
+#define I2C_PIN_CNF_CLR(internal_pullup) \
+ ((GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \
+ | (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) \
+ | (((internal_pullup) ? GPIO_PIN_CNF_PULL_Pullup : GPIO_PIN_CNF_PULL_Disabled) << GPIO_PIN_CNF_PULL_Pos) \
+ | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \
+ | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos))
+
+#if NRF5_I2C_USE_I2C0
+#define I2C0_IRQ_NUM SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn
+#define I2C0_IRQ_PRI NRF5_I2C_I2C0_IRQ_PRIORITY
+#endif
+#if NRF5_I2C_USE_I2C1
+#define I2C1_IRQ_NUM SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn
+#define I2C1_IRQ_PRI NRF5_I2C_I2C1_IRQ_PRIORITY
+#endif
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief I2C0 driver identifier.
+ */
+#if NRF5_I2C_USE_I2C0 || defined(__DOXYGEN__)
+I2CDriver I2CD1;
+#endif
+
+/**
+ * @brief I2C1 driver identifier.
+ */
+#if NRF5_I2C_USE_I2C1 || defined(__DOXYGEN__)
+I2CDriver I2CD2;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+/**
+ * @brief Function for detecting stuck slaves (SDA = 0 and SCL = 1) and tries to clear the bus.
+ *
+ * @return
+ * @retval false Bus is stuck.
+ * @retval true Bus is clear.
+ */
+static void i2c_clear_bus(I2CDriver *i2cp) {
+ const I2CConfig *cfg = i2cp->config;
+ uint8_t i;
+
+ IOPORT1->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF(cfg->scl_pullup);
+ IOPORT1->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF(cfg->sda_pullup);
+
+ I2C_HIGH(cfg->sda_pad);
+ I2C_HIGH(cfg->scl_pad);
+
+ IOPORT1->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF_CLR(cfg->scl_pullup);
+ IOPORT1->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF_CLR(cfg->sda_pullup);
+
+ nrf_delay_us(4);
+
+ for(i = 0; i < 9; i++) {
+ if (palReadPad(IOPORT1, cfg->sda_pad)) {
+ if(i > 0)
+ break;
+ else
+ return;
+ }
+
+ I2C_LOW(cfg->scl_pad);
+ nrf_delay_us(4);
+ I2C_HIGH(cfg->scl_pad);
+ nrf_delay_us(4);
+ }
+
+ I2C_LOW(cfg->sda_pad);
+ nrf_delay_us(4);
+ I2C_HIGH(cfg->sda_pad);
+}
+
+#if defined(__GNUC__)
+__attribute__((noinline))
+#endif
+/**
+ * @brief Common IRQ handler.
+ * @note Tries hard to clear all the pending interrupt sources, we don't
+ * want to go through the whole ISR and have another interrupt soon
+ * after.
+ *
+ * @param[in] i2cp pointer to an I2CDriver
+ */
+static void i2c_serve_interrupt(I2CDriver *i2cp) {
+ NRF_TWIM_Type *i2c = i2cp->i2c;
+
+ if (i2c->EVENTS_ERROR) {
+ uint32_t err = i2c->ERRORSRC;
+ i2c->EVENTS_ERROR = 0;
+ (void)i2c->EVENTS_ERROR;
+
+ if (err & 0x01) // nRF52832 Product Specification v1.3 p.314 TWIM_ERRORSRC OVERRUN bit = 0x01
+ i2cp->errors |= I2C_OVERRUN;
+ if (err & (TWIM_ERRORSRC_ANACK_Msk | TWIM_ERRORSRC_DNACK_Msk))
+ i2cp->errors |= I2C_ACK_FAILURE;
+
+ i2c->TASKS_STOP = 1;
+
+ _i2c_wakeup_error_isr(i2cp);
+ } else if(i2c->EVENTS_STOPPED) {
+
+ i2c->EVENTS_STOPPED = 0;
+ (void)i2c->EVENTS_STOPPED;
+
+ _i2c_wakeup_isr(i2cp);
+ }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if NRF5_I2C_USE_I2C0 || defined(__DOXYGEN__)
+
+OSAL_IRQ_HANDLER(Vector4C) {
+
+ OSAL_IRQ_PROLOGUE();
+ i2c_serve_interrupt(&I2CD1);
+ OSAL_IRQ_EPILOGUE();
+}
+
+#endif
+
+#if NRF5_I2C_USE_I2C1 || defined(__DOXYGEN__)
+
+OSAL_IRQ_HANDLER(Vector50) {
+
+ OSAL_IRQ_PROLOGUE();
+ i2c_serve_interrupt(&I2CD2);
+ OSAL_IRQ_EPILOGUE();
+}
+
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level I2C driver initialization.
+ *
+ * @notapi
+ */
+void i2c_lld_init(void) {
+
+#if NRF5_I2C_USE_I2C0
+ i2cObjectInit(&I2CD1);
+ I2CD1.thread = NULL;
+ I2CD1.i2c = NRF_TWIM0;
+#endif
+
+#if NRF5_I2C_USE_I2C1
+ i2cObjectInit(&I2CD2);
+ I2CD2.thread = NULL;
+ I2CD2.i2c = NRF_TWIM1;
+#endif
+
+}
+
+/**
+ * @brief Configures and activates the I2C peripheral.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+void i2c_lld_start(I2CDriver *i2cp) {
+ NRF_TWIM_Type *i2c = i2cp->i2c;
+
+ const I2CConfig *cfg = i2cp->config;
+
+ if (i2cp->state != I2C_STOP)
+ return;
+
+ osalDbgAssert(i2c->ENABLE == 0, "already in use");
+
+ i2c_clear_bus(i2cp);
+
+ IOPORT1->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF(cfg->scl_pullup);
+ IOPORT1->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF(cfg->sda_pullup);
+
+ i2c->SHORTS = 0;
+
+ i2c->EVENTS_STOPPED = 0;
+ i2c->EVENTS_ERROR = 0;
+ (void)i2c->EVENTS_STOPPED;
+ (void)i2c->EVENTS_ERROR;
+
+ i2c->PSEL.SCL = cfg->scl_pad;
+ i2c->PSEL.SDA = cfg->sda_pad;
+
+ switch (cfg->clock) {
+ case 100000:
+ i2c->FREQUENCY = TWIM_FREQUENCY_FREQUENCY_K100 << TWIM_FREQUENCY_FREQUENCY_Pos;
+ break;
+ case 250000:
+ i2c->FREQUENCY = TWIM_FREQUENCY_FREQUENCY_K250 << TWIM_FREQUENCY_FREQUENCY_Pos;
+ break;
+ case 400000:
+ i2c->FREQUENCY = TWIM_FREQUENCY_FREQUENCY_K400 << TWIM_FREQUENCY_FREQUENCY_Pos;
+ break;
+ default:
+ osalDbgAssert(0, "invalid I2C frequency");
+ break;
+ };
+
+#if NRF5_I2C_USE_I2C0
+ nvicEnableVector(I2C0_IRQ_NUM, I2C0_IRQ_PRI);
+#endif
+
+#if NRF5_I2C_USE_I2C1
+ nvicEnableVector(I2C1_IRQ_NUM, I2C1_IRQ_PRI);
+#endif
+
+ i2c->INTENSET = TWIM_INTENSET_STOPPED_Msk | TWIM_INTENSET_ERROR_Msk;
+
+ i2c->ENABLE = TWIM_ENABLE_ENABLE_Enabled << TWIM_ENABLE_ENABLE_Pos;
+}
+
+/**
+ * @brief Deactivates the I2C peripheral.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+void i2c_lld_stop(I2CDriver *i2cp) {
+ NRF_TWIM_Type *i2c = i2cp->i2c;
+ const I2CConfig *cfg = i2cp->config;
+
+ if (i2cp->state != I2C_STOP) {
+ i2c->SHORTS = 0;
+
+ i2c->INTENCLR = TWIM_INTENCLR_STOPPED_Msk | TWIM_INTENCLR_ERROR_Msk;
+
+#if NRF5_I2C_USE_I2C0
+ nvicDisableVector(I2C0_IRQ_NUM);
+#endif
+
+#if NRF5_I2C_USE_I2C1
+ nvicDisableVector(I2C1_IRQ_NUM);
+#endif
+
+ i2c->ENABLE = TWIM_ENABLE_ENABLE_Disabled << TWIM_ENABLE_ENABLE_Pos;
+
+ IOPORT1->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF_CLR(cfg->scl_pullup);
+ IOPORT1->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF_CLR(cfg->sda_pullup);
+ }
+}
+
+static inline msg_t _i2c_txrx_timeout(I2CDriver *i2cp, i2caddr_t addr,
+ const uint8_t *txbuf, size_t txbytes,
+ uint8_t *rxbuf, size_t rxbytes,
+ systime_t timeout) {
+
+ NRF_TWIM_Type *i2c = i2cp->i2c;
+ msg_t msg;
+
+ i2cp->errors = I2C_NO_ERROR;
+ i2cp->addr = addr;
+
+ uint8_t tx_bytes = txbytes;
+ uint8_t rx_bytes = rxbytes;
+
+ i2cp->i2c->SHORTS = 0;
+ i2c->ADDRESS = addr;
+
+ if (tx_bytes && rx_bytes) {
+ i2c->TXD.PTR = (uint32_t)txbuf;
+ i2c->TXD.MAXCNT = tx_bytes;
+ i2c->TXD.LIST = TWIM_TXD_LIST_LIST_ArrayList << TWIM_TXD_LIST_LIST_Pos;
+ i2c->RXD.PTR = (uint32_t)rxbuf;
+ i2c->RXD.MAXCNT = rx_bytes;
+ i2c->RXD.LIST = TWIM_RXD_LIST_LIST_ArrayList << TWIM_RXD_LIST_LIST_Pos;
+ i2cp->i2c->SHORTS = TWIM_SHORTS_LASTTX_STARTRX_Enabled << TWIM_SHORTS_LASTTX_STARTRX_Pos |
+ TWIM_SHORTS_LASTRX_STOP_Enabled << TWIM_SHORTS_LASTRX_STOP_Pos;
+ i2c->TASKS_STARTTX = 1;
+ } else if (tx_bytes && !rx_bytes) {
+ i2c->TXD.PTR = (uint32_t)txbuf;
+ i2c->TXD.MAXCNT = tx_bytes;
+ i2c->TXD.LIST = TWIM_TXD_LIST_LIST_ArrayList << TWIM_TXD_LIST_LIST_Pos;
+ i2cp->i2c->SHORTS = TWIM_SHORTS_LASTTX_STOP_Enabled << TWIM_SHORTS_LASTTX_STOP_Pos;
+ i2c->TASKS_STARTTX = 1;
+ } else if (!tx_bytes && rx_bytes) {
+ i2c->RXD.PTR = (uint32_t)rxbuf;
+ i2c->RXD.MAXCNT = rx_bytes;
+ i2c->RXD.LIST = TWIM_RXD_LIST_LIST_ArrayList << TWIM_RXD_LIST_LIST_Pos;
+ i2cp->i2c->SHORTS = TWIM_SHORTS_LASTRX_STOP_Enabled << TWIM_SHORTS_LASTRX_STOP_Pos;
+ i2c->TASKS_STARTRX = 1;
+ } else {
+ osalDbgAssert(0, "no bytes to transfer");
+ }
+
+ msg = osalThreadSuspendTimeoutS(&i2cp->thread, timeout);
+
+ if (msg == MSG_TIMEOUT)
+ i2c->TASKS_STOP = 1;
+
+ return msg;
+}
+
+/**
+ * @brief Receives data via the I2C bus as master.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ * @param[in] addr slave device address
+ * @param[out] rxbuf pointer to the receive buffer
+ * @param[in] rxbytes number of bytes to be received
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more I2C errors occurred, the errors can
+ * be retrieved using @p i2cGetErrors().
+ * @retval MSG_TIMEOUT if a timeout occurred before operation end. <b>After a
+ * timeout the driver must be stopped and restarted
+ * because the bus is in an uncertain state</b>.
+ *
+ * @notapi
+ */
+msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
+ uint8_t *rxbuf, size_t rxbytes,
+ systime_t timeout) {
+
+ return _i2c_txrx_timeout(i2cp, addr, NULL, 0, rxbuf, rxbytes, timeout);
+}
+
+/**
+ * @brief Transmits data via the I2C bus as master.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ * @param[in] addr slave device address
+ * @param[in] txbuf pointer to the transmit buffer
+ * @param[in] txbytes number of bytes to be transmitted
+ * @param[out] rxbuf pointer to the receive buffer
+ * @param[in] rxbytes number of bytes to be received
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more I2C errors occurred, the errors can
+ * be retrieved using @p i2cGetErrors().
+ * @retval MSG_TIMEOUT if a timeout occurred before operation end. <b>After a
+ * timeout the driver must be stopped and restarted
+ * because the bus is in an uncertain state</b>.
+ *
+ * @notapi
+ */
+msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
+ const uint8_t *txbuf, size_t txbytes,
+ uint8_t *rxbuf, size_t rxbytes,
+ systime_t timeout) {
+
+ return _i2c_txrx_timeout(i2cp, addr, txbuf, txbytes, rxbuf, rxbytes, timeout);
+}
+
+#endif /* HAL_USE_I2C */
+
+/** @} */
diff --git a/os/hal/ports/NRF5/LLD/TWIMv1/hal_i2c_lld.h b/os/hal/ports/NRF5/LLD/TWIMv1/hal_i2c_lld.h new file mode 100644 index 0000000..a73efc7 --- /dev/null +++ b/os/hal/ports/NRF5/LLD/TWIMv1/hal_i2c_lld.h @@ -0,0 +1,214 @@ +/*
+ Copyright (C) 2018 andru
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file NRF5/NRF52832/hal_i2c_lld.h
+ * @brief NRF52 I2C subsystem low level driver header.
+ *
+ * @addtogroup I2C
+ * @{
+ */
+
+#ifndef HAL_I2C_LLD_H
+#define HAL_I2C_LLD_H
+
+#if HAL_USE_I2C || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief I2C0 driver enable switch.
+ * @details If set to @p TRUE the support for I2C0 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(NRF5_I2C_USE_I2C0) || defined(__DOXYGEN__)
+#define NRF5_I2C_USE_I2C0 FALSE
+#endif
+
+/**
+ * @brief I2C1 driver enable switch.
+ * @details If set to @p TRUE the support for I2C1 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(NRF5_I2C_USE_I2C1) || defined(__DOXYGEN__)
+#define NRF5_I2C_USE_I2C1 FALSE
+#endif
+
+/**
+ * @brief I2C0 interrupt priority level setting.
+ */
+#if !defined(NRF5_I2C_I2C0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define NRF5_I2C_I2C0_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief I2C1 interrupt priority level setting.
+ */
+#if !defined(NRF5_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define NRF5_I2C_I2C1_IRQ_PRIORITY 3
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if NRF5_I2C_USE_I2C0 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_I2C_I2C0_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to I2C0"
+#endif
+
+#if NRF5_I2C_USE_I2C1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_I2C_I2C1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to I2C1"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/* @brief Type representing I2C address. */
+typedef uint8_t i2caddr_t;
+
+/* @brief Type of I2C Driver condition flags. */
+typedef uint32_t i2cflags_t;
+
+/**
+ * @brief Driver configuration structure.
+ * @note Implementations may extend this structure to contain more,
+ * architecture dependent, fields.
+ */
+
+/**
+ * @brief Driver configuration structure.
+ */
+typedef struct {
+
+ /* @brief Clock to be used for the I2C bus. */
+ uint32_t clock;
+ /* @brief Pad number for SCL */
+ uint8_t scl_pad;
+ /* @brief Pad number for SDA */
+ uint8_t sda_pad;
+ /* @brief Whether to use the internal pull-up for SCL */
+ bool scl_pullup;
+ /* @brief Whether to use the internal pull-up for SDA */
+ bool sda_pullup;
+
+} I2CConfig;
+
+/**
+ * @brief Type of a structure representing an I2C driver.
+ */
+typedef struct I2CDriver I2CDriver;
+
+/**
+ * @brief Structure representing an I2C driver.
+ */
+struct I2CDriver {
+ /**
+ * @brief Driver state.
+ */
+ i2cstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const I2CConfig *config;
+ /**
+ * @brief Error flags.
+ */
+ i2cflags_t errors;
+#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+ /**
+ * @brief Mutex protecting the bus.
+ */
+ mutex_t mutex;
+#endif /* I2C_USE_MUTUAL_EXCLUSION */
+#if defined(I2C_DRIVER_EXT_FIELDS)
+ I2C_DRIVER_EXT_FIELDS
+#endif
+ /* @brief Thread waiting for I/O completion. */
+ thread_reference_t thread;
+ /* @brief Current slave address without R/W bit. */
+ i2caddr_t addr;
+
+ /* End of the mandatory fields.*/
+
+ /* @brief Low-level register access. */
+ NRF_TWIM_Type *i2c;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Get errors from I2C driver.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+#define i2c_lld_get_errors(i2cp) ((i2cp)->errors)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+
+#if NRF5_I2C_USE_I2C0
+extern I2CDriver I2CD1;
+#endif
+
+#if NRF5_I2C_USE_I2C1
+extern I2CDriver I2CD2;
+#endif
+
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void i2c_lld_init(void);
+ void i2c_lld_start(I2CDriver *i2cp);
+ void i2c_lld_stop(I2CDriver *i2cp);
+ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
+ const uint8_t *txbuf, size_t txbytes,
+ uint8_t *rxbuf, size_t rxbytes,
+ systime_t timeout);
+ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
+ uint8_t *rxbuf, size_t rxbytes,
+ systime_t timeout);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_I2C */
+
+#endif /* HAL_I2C_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/NRF5/LLD/TWIv1/driver.mk b/os/hal/ports/NRF5/LLD/TWIv1/driver.mk new file mode 100644 index 0000000..3bc55d8 --- /dev/null +++ b/os/hal/ports/NRF5/LLD/TWIv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/TWIv1/hal_i2c_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/TWIv1/hal_i2c_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/TWIv1
diff --git a/os/hal/ports/NRF5/LLD/hal_i2c_lld.c b/os/hal/ports/NRF5/LLD/TWIv1/hal_i2c_lld.c index fefca0c..a9391dd 100644 --- a/os/hal/ports/NRF5/LLD/hal_i2c_lld.c +++ b/os/hal/ports/NRF5/LLD/TWIv1/hal_i2c_lld.c @@ -15,7 +15,7 @@ */
/**
- * @file NRF5/LLD/hal_i2c_lld.c
+ * @file TWIv1/hal_i2c_lld.c
* @brief NRF5 I2C subsystem low level driver source.
*
* @addtogroup I2C
@@ -38,17 +38,17 @@ #define I2C_INPUT(p) do { IOPORT1->DIRCLR = (1UL << (p)); } while(0) /*!< Configures I2C pin as input */
#define I2C_OUTPUT(p) do { IOPORT1->DIRSET = (1UL << (p)); } while(0) /*!< Configures I2C pin as output */
-#define I2C_PIN_CNF \
+#define I2C_PIN_CNF(internal_pullup) \
((GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \
| (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) \
- | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) \
+ | (((internal_pullup) ? GPIO_PIN_CNF_PULL_Pullup : GPIO_PIN_CNF_PULL_Disabled) << GPIO_PIN_CNF_PULL_Pos) \
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos))
-#define I2C_PIN_CNF_CLR \
+#define I2C_PIN_CNF_CLR(internal_pullup) \
((GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \
| (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) \
- | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) \
+ | (((internal_pullup) ? GPIO_PIN_CNF_PULL_Pullup : GPIO_PIN_CNF_PULL_Disabled) << GPIO_PIN_CNF_PULL_Pos) \
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos))
@@ -102,14 +102,14 @@ static void i2c_clear_bus(I2CDriver *i2cp) const I2CConfig *cfg = i2cp->config;
int i;
- IOPORT1->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF;
- IOPORT1->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF;
+ IOPORT1->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF(cfg->scl_pullup);
+ IOPORT1->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF(cfg->sda_pullup);
I2C_HIGH(cfg->sda_pad);
I2C_HIGH(cfg->scl_pad);
- IOPORT1->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF_CLR;
- IOPORT1->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF_CLR;
+ IOPORT1->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF_CLR(cfg->scl_pullup);
+ IOPORT1->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF_CLR(cfg->sda_pullup);
nrf_delay_us(4);
@@ -290,8 +290,8 @@ void i2c_lld_start(I2CDriver *i2cp) { i2c_clear_bus(i2cp);
- IOPORT1->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF;
- IOPORT1->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF;
+ IOPORT1->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF(cfg->scl_pullup);
+ IOPORT1->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF(cfg->sda_pullup);
i2c->EVENTS_RXDREADY = 0;
i2c->EVENTS_TXDSENT = 0;
@@ -351,8 +351,8 @@ void i2c_lld_stop(I2CDriver *i2cp) { nvicDisableVector(I2C_IRQ_NUM);
- IOPORT1->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF_CLR;
- IOPORT1->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF_CLR;
+ IOPORT1->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF_CLR(cfg->scl_pullup);
+ IOPORT1->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF_CLR(cfg->sda_pullup);
}
}
diff --git a/os/hal/ports/NRF5/LLD/hal_i2c_lld.h b/os/hal/ports/NRF5/LLD/TWIv1/hal_i2c_lld.h index 578d69b..f126983 100644 --- a/os/hal/ports/NRF5/LLD/hal_i2c_lld.h +++ b/os/hal/ports/NRF5/LLD/TWIv1/hal_i2c_lld.h @@ -15,7 +15,7 @@ */
/**
- * @file NRF5/LLD/hal_i2c_lld.h
+ * @file TWIv1/hal_i2c_lld.h
* @brief NRF5 I2C subsystem low level driver header.
*
* @addtogroup I2C
@@ -121,6 +121,10 @@ typedef struct { uint8_t scl_pad;
/* @brief Pad number for SDA */
uint8_t sda_pad;
+ /* @brief Whether to use the internal pull-up for SCL */
+ bool scl_pullup;
+ /* @brief Whether to use the internal pull-up for SDA */
+ bool sda_pullup;
} I2CConfig;
diff --git a/os/hal/ports/NRF5/LLD/UARTv1/driver.mk b/os/hal/ports/NRF5/LLD/UARTv1/driver.mk new file mode 100644 index 0000000..5b4f634 --- /dev/null +++ b/os/hal/ports/NRF5/LLD/UARTv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/UARTv1/hal_serial_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/UARTv1/hal_serial_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/UARTv1
diff --git a/os/hal/ports/NRF5/LLD/hal_serial_lld.c b/os/hal/ports/NRF5/LLD/UARTv1/hal_serial_lld.c index 42091e8..76ba0e0 100644 --- a/os/hal/ports/NRF5/LLD/hal_serial_lld.c +++ b/os/hal/ports/NRF5/LLD/UARTv1/hal_serial_lld.c @@ -15,7 +15,7 @@ */
/**
- * @file NRF5/LLD/hal_serial_lld.c
+ * @file UARTv1/hal_serial_lld.c
* @brief NRF5 serial subsystem low level driver source.
*
* @addtogroup SERIAL
diff --git a/os/hal/ports/NRF5/LLD/hal_serial_lld.h b/os/hal/ports/NRF5/LLD/UARTv1/hal_serial_lld.h index 741a40a..9c76777 100644 --- a/os/hal/ports/NRF5/LLD/hal_serial_lld.h +++ b/os/hal/ports/NRF5/LLD/UARTv1/hal_serial_lld.h @@ -15,7 +15,7 @@ */
/**
- * @file NRF5/LLD/hal_serial_lld.h
+ * @file UARTv1/hal_serial_lld.h
* @brief NRF5 serial subsystem low level driver header.
*
* @addtogroup SERIAL
diff --git a/os/hal/ports/NRF5/LLD/WDTv1/driver.mk b/os/hal/ports/NRF5/LLD/WDTv1/driver.mk new file mode 100644 index 0000000..07e0fb9 --- /dev/null +++ b/os/hal/ports/NRF5/LLD/WDTv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/WDTv1/hal_wdg_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/WDTv1/hal_wdg_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/WDTv1
diff --git a/os/hal/ports/NRF5/LLD/hal_wdg_lld.c b/os/hal/ports/NRF5/LLD/WDTv1/hal_wdg_lld.c index 35c079f..7bd2966 100644 --- a/os/hal/ports/NRF5/LLD/hal_wdg_lld.c +++ b/os/hal/ports/NRF5/LLD/WDTv1/hal_wdg_lld.c @@ -15,7 +15,7 @@ */
/**
- * @file NRF5/LLD/hal_wdg_lld.c
+ * @file WDTv1/hal_wdg_lld.c
* @brief NRF5 Watchdog Driver subsystem low level driver source template.
*
* @addtogroup WDG
diff --git a/os/hal/ports/NRF5/LLD/hal_wdg_lld.h b/os/hal/ports/NRF5/LLD/WDTv1/hal_wdg_lld.h index 109b67e..c478919 100644 --- a/os/hal/ports/NRF5/LLD/hal_wdg_lld.h +++ b/os/hal/ports/NRF5/LLD/WDTv1/hal_wdg_lld.h @@ -15,7 +15,7 @@ */
/**
- * @file NRF5/LLD/hal_wdg_lld.h
+ * @file WDTv1/hal_wdg_lld.h
* @brief NRF5 Watchdog Driver subsystem low level driver header template.
*
* @addtogroup WDG
diff --git a/os/hal/ports/NRF5/NRF51822/hal_ext_lld.c b/os/hal/ports/NRF5/NRF51822/hal_ext_lld.c deleted file mode 100644 index 47736c7..0000000 --- a/os/hal/ports/NRF5/NRF51822/hal_ext_lld.c +++ /dev/null @@ -1,168 +0,0 @@ -/*
- Copyright (C) 2015 Stephen Caudle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file NRF51822/ext_lld.c
- * @brief NRF51822 EXT subsystem low level driver source.
- *
- * @addtogroup EXT
- * @{
- */
-
-#include "hal.h"
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-#include "hal_ext_lld_isr.h"
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief EXTD1 driver identifier.
- */
-EXTDriver EXTD1;
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level EXT driver initialization.
- *
- * @notapi
- */
-void ext_lld_init(void) {
-
- /* Driver initialization.*/
- extObjectInit(&EXTD1);
-}
-
-/**
- * @brief Configures and activates the EXT peripheral.
- *
- * @param[in] extp pointer to the @p EXTDriver object
- *
- * @notapi
- */
-void ext_lld_start(EXTDriver *extp) {
-
- unsigned i;
-
- ext_lld_exti_irq_enable();
-
- /* Configuration of automatic channels.*/
- for (i = 0; i < EXT_MAX_CHANNELS; i++) {
- uint32_t config = 0;
- uint32_t pad = (extp->config->channels[i].mode & EXT_MODE_GPIO_MASK)
- >> EXT_MODE_GPIO_OFFSET;
-
- if (extp->config->channels[i].mode & EXT_CH_MODE_BOTH_EDGES)
- config |= (GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos);
- else if (extp->config->channels[i].mode & EXT_CH_MODE_RISING_EDGE)
- config |= (GPIOTE_CONFIG_POLARITY_LoToHi << GPIOTE_CONFIG_POLARITY_Pos);
- else
- config |= (GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos);
-
- config |= (pad << GPIOTE_CONFIG_PSEL_Pos);
-
- NRF_GPIOTE->CONFIG[i] = config;
- NRF_GPIOTE->EVENTS_PORT = 0;
- NRF_GPIOTE->EVENTS_IN[i] = 0;
-
- if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART)
- ext_lld_channel_enable(extp, i);
- else
- ext_lld_channel_disable(extp, i);
- }
-}
-
-/**
- * @brief Deactivates the EXT peripheral.
- *
- * @param[in] extp pointer to the @p EXTDriver object
- *
- * @notapi
- */
-void ext_lld_stop(EXTDriver *extp) {
-
- unsigned i;
-
- (void)extp;
- ext_lld_exti_irq_disable();
-
- for (i = 0; i < EXT_MAX_CHANNELS; i++)
- NRF_GPIOTE->CONFIG[i] = 0;
-
- NRF_GPIOTE->INTENCLR =
- (GPIOTE_INTENCLR_IN3_Msk | GPIOTE_INTENCLR_IN2_Msk |
- GPIOTE_INTENCLR_IN1_Msk | GPIOTE_INTENCLR_IN0_Msk);
-}
-
-/**
- * @brief Enables an EXT channel.
- *
- * @param[in] extp pointer to the @p EXTDriver object
- * @param[in] channel channel to be enabled
- *
- * @notapi
- */
-void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) {
-
- uint32_t config = NRF_GPIOTE->CONFIG[channel] & ~GPIOTE_CONFIG_MODE_Msk;
-
- (void)extp;
- config |= (GPIOTE_CONFIG_MODE_Event << GPIOTE_CONFIG_MODE_Pos);
-
- NRF_GPIOTE->CONFIG[channel] = config;
- NRF_GPIOTE->INTENSET = (1 << channel);
-}
-
-/**
- * @brief Disables an EXT channel.
- *
- * @param[in] extp pointer to the @p EXTDriver object
- * @param[in] channel channel to be disabled
- *
- * @notapi
- */
-void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) {
-
- (void)extp;
- NRF_GPIOTE->CONFIG[channel] &= ~GPIOTE_CONFIG_MODE_Msk;
- NRF_GPIOTE->INTENCLR = (1 << channel);
-}
-
-#endif /* HAL_USE_EXT */
-
-/** @} */
diff --git a/os/hal/ports/NRF5/NRF51822/hal_ext_lld.h b/os/hal/ports/NRF5/NRF51822/hal_ext_lld.h deleted file mode 100644 index 37ae721..0000000 --- a/os/hal/ports/NRF5/NRF51822/hal_ext_lld.h +++ /dev/null @@ -1,139 +0,0 @@ -/*
- Copyright (C) 2015 Stephen Caudle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file NRF51822/ext_lld.h
- * @brief NRF51822 GPIOTE subsystem low level driver header.
- *
- * @addtogroup EXT
- * @{
- */
-
-#ifndef HAL_EXT_LLD_H
-#define HAL_EXT_LLD_H
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @brief Available number of EXT channels.
- */
-#define EXT_MAX_CHANNELS 4
-#define EXT_MODE_GPIO_MASK 0xF8 /**< @brief Pad field mask. */
-#define EXT_MODE_GPIO_OFFSET 3 /**< @brief Pad field offset. */
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief EXT channel identifier.
- */
-typedef uint32_t expchannel_t;
-
-/**
- * @brief Type of an EXT generic notification callback.
- *
- * @param[in] extp pointer to the @p EXPDriver object triggering the
- * callback
- */
-typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel);
-
-/**
- * @brief Channel configuration structure.
- */
-typedef struct {
- /**
- * @brief Channel mode.
- */
- uint32_t mode;
- /**
- * @brief Channel callback.
- * @details In the STM32 implementation a @p NULL callback pointer is
- * valid and configures the channel as an event sources instead
- * of an interrupt source.
- */
- extcallback_t cb;
-} EXTChannelConfig;
-
-/**
- * @brief Driver configuration structure.
- * @note It could be empty on some architectures.
- */
-typedef struct {
- /**
- * @brief Channel configurations.
- */
- EXTChannelConfig channels[EXT_MAX_CHANNELS];
- /* End of the mandatory fields.*/
-} EXTConfig;
-
-/**
- * @brief Structure representing an EXT driver.
- */
-struct EXTDriver {
- /**
- * @brief Driver state.
- */
- extstate_t state;
- /**
- * @brief Current configuration data.
- */
- const EXTConfig *config;
- /* End of the mandatory fields.*/
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern EXTDriver EXTD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void ext_lld_init(void);
- void ext_lld_start(EXTDriver *extp);
- void ext_lld_stop(EXTDriver *extp);
- void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel);
- void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_EXT */
-
-#endif /* HAL_EXT_LLD_H */
-
-/** @} */
diff --git a/os/hal/ports/NRF5/NRF51822/hal_lld.c b/os/hal/ports/NRF5/NRF51822/hal_lld.c index f33fdda..412cfea 100644 --- a/os/hal/ports/NRF5/NRF51822/hal_lld.c +++ b/os/hal/ports/NRF5/NRF51822/hal_lld.c @@ -80,6 +80,8 @@ void hal_lld_init(void) (NRF5_SYSTEM_TICKS == NRF5_SYSTEM_TICKS_AS_RTC) NRF_CLOCK->TASKS_LFCLKSTART = 1; #endif + + irqInit(); } /** diff --git a/os/hal/ports/NRF5/NRF51822/hal_lld.h b/os/hal/ports/NRF5/NRF51822/hal_lld.h index a1d2460..178bb42 100644 --- a/os/hal/ports/NRF5/NRF51822/hal_lld.h +++ b/os/hal/ports/NRF5/NRF51822/hal_lld.h @@ -94,7 +94,7 @@ /*===========================================================================*/ #include "nvic.h" - +#include "nrf51_isr.h" #ifdef __cplusplus extern "C" { diff --git a/os/hal/ports/NRF5/NRF51822/nrf51_isr.c b/os/hal/ports/NRF5/NRF51822/nrf51_isr.c new file mode 100644 index 0000000..9a2bd94 --- /dev/null +++ b/os/hal/ports/NRF5/NRF51822/nrf51_isr.c @@ -0,0 +1,96 @@ +/*
+ Copyright (C) 2018 Konstantin Oblaukhov
+ Copyright (C) 2015 Stephen Caudle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file NRF51822/nrf51_isr.c
+ * @brief NRF51822 ISR handler code.
+ *
+ * @addtogroup NRF51822_ISR
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/**
+ * @brief GPIOTE interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector58) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ for (int ch = 0; ch < NRF5_GPIOTE_NUM_CHANNELS; ch++)
+ {
+ if (NRF_GPIOTE->EVENTS_IN[ch])
+ {
+ NRF_GPIOTE->EVENTS_IN[ch] = 0;
+ _pal_isr_code(ch);
+ }
+ }
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+/**
+ * @brief Enables IRQ sources.
+ *
+ * @notapi
+ */
+void irqInit(void) {
+
+#if HAL_USE_PAL
+ nvicEnableVector(GPIOTE_IRQn, NRF5_IRQ_GPIOTE_PRIORITY);
+#endif
+}
+
+/**
+ * @brief Disables IRQ sources.
+ *
+ * @notapi
+ */
+void irqDeinit(void) {
+
+#if HAL_USE_PAL
+ nvicDisableVector(GPIOTE_IRQn);
+#endif
+}
+
+/** @} */
diff --git a/os/hal/ports/NRF5/NRF51822/nrf51_isr.h b/os/hal/ports/NRF5/NRF51822/nrf51_isr.h new file mode 100644 index 0000000..832d2c3 --- /dev/null +++ b/os/hal/ports/NRF5/NRF51822/nrf51_isr.h @@ -0,0 +1,44 @@ +/*
+ Copyright (C) 2018 Konstantin Oblaukhov
+ Copyright (C) 2015 Stephen Caudle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file NRF51822/nrf51_isr.h
+ * @brief NRF51822 ISR handler header.
+ *
+ * @addtogroup NRF51822_ISR
+ * @{
+ */
+
+#ifndef NRF51_ISR_H
+#define NRF51_ISR_H
+
+#if !defined(NRF5_IRQ_GPIOTE_PRIORITY) || defined(__DOXYGEN__)
+#define NRF5_IRQ_GPIOTE_PRIORITY 3
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void irqInit(void);
+ void irqDeinit(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NRF51_ISR_H */
+
+/** @} */
diff --git a/os/hal/ports/NRF5/NRF51822/platform.mk b/os/hal/ports/NRF5/NRF51822/platform.mk index 7305acf..711a625 100644 --- a/os/hal/ports/NRF5/NRF51822/platform.mk +++ b/os/hal/ports/NRF5/NRF51822/platform.mk @@ -1,66 +1,34 @@ +PLATFORMSRC_CONTRIB := ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/nrf51_isr.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/TIMERv1/hal_st_lld.c + +PLATFORMINC_CONTRIB := ${CHIBIOS}/os/hal/ports/common/ARMCMx \ + ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD \ + ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822 + ifeq ($(USE_SMART_BUILD),yes) -HALCONF := $(strip $(shell cat halconf.h halconf_community.h 2>/dev/null | egrep -e "define")) -# List of all the NRF51x platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_st_lld.c - -ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_pal_lld.c -endif -ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_serial_lld.c -endif -ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_spi_lld.c -endif -ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_ext_lld_isr.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_ext_lld.c -endif -ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_i2c_lld.c -endif -ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_adc_lld.c -endif -ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_gpt_lld.c -endif -ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_wdg_lld.c -endif -ifneq ($(findstring HAL_USE_RNG TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_rng_lld.c -endif -ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_pwm_lld.c -endif -ifneq ($(findstring HAL_USE_QEI TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_qei_lld.c -endif -else -PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_pal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_serial_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_st_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_spi_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_ext_lld_isr.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_ext_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_i2c_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_adc_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_gpt_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_wdg_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_rng_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_pwm_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_qei_lld.c +# Configuration files directory +ifeq ($(CONFDIR),) + CONFDIR = . endif -# Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822 +HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define")) + +endif +include ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/GPIOv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/UARTv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/SPIv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/TWIv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/ADCv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/TIMERv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/WDTv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/RNGv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/PWMv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/QDECv1/driver.mk +# Shared variables +ALLCSRC += $(PLATFORMSRC_CONTRIB) +ALLINC += $(PLATFORMINC_CONTRIB) diff --git a/os/hal/ports/NRF5/NRF52832/hal_lld.c b/os/hal/ports/NRF5/NRF52832/hal_lld.c index 500de13..11307f8 100644 --- a/os/hal/ports/NRF5/NRF52832/hal_lld.c +++ b/os/hal/ports/NRF5/NRF52832/hal_lld.c @@ -55,24 +55,40 @@ */ void hal_lld_init(void) { - /* High frequency clock initialisation + /* High frequency clock initialization */ NRF_CLOCK->TASKS_HFCLKSTOP = 1; + #if !defined(NRF5_XTAL_VALUE) && (NRF5_XTAL_VALUE != 32000000) #error "A 32Mhz crystal is mandatory on nRF52 boards." #endif +#if (NRF5_HFCLK_SOURCE == NRF5_HFCLK_HFXO) + NRF_CLOCK->EVENTS_HFCLKSTARTED = 0; + NRF_CLOCK->TASKS_HFCLKSTART = 1; + while (NRF_CLOCK->EVENTS_HFCLKSTARTED == 0); +#endif - /* Low frequency clock initialisation - * Clock is only started if st driver requires it + /* Low frequency clock initialization */ +#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) +#if (NRF5_ST_USE_RTC0 || NRF5_ST_USE_RTC1) && \ + (NRF5_LFCLK_SOURCE == NRF5_LFCLK_RC) +#error "A NRF5_SYSTEM_TICKS_AS_RTC requires LFCLK clock to be started." +#endif +#endif + NRF_CLOCK->TASKS_LFCLKSTOP = 1; + +#if (NRF5_LFCLK_SOURCE != NRF5_LFCLK_RC) NRF_CLOCK->LFCLKSRC = NRF5_LFCLK_SOURCE; - -#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) && \ - (NRF5_SYSTEM_TICKS == NRF5_SYSTEM_TICKS_AS_RTC) + + NRF_CLOCK->EVENTS_LFCLKSTARTED = 0; NRF_CLOCK->TASKS_LFCLKSTART = 1; + while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0); #endif + + irqInit(); } /** diff --git a/os/hal/ports/NRF5/NRF52832/hal_lld.h b/os/hal/ports/NRF5/NRF52832/hal_lld.h index 24784d3..0620b5f 100644 --- a/os/hal/ports/NRF5/NRF52832/hal_lld.h +++ b/os/hal/ports/NRF5/NRF52832/hal_lld.h @@ -60,22 +60,36 @@ /*===========================================================================*/ /** + * @brief Select source of High Frequency Clock (HFCLK) + * @details Possible values for source are: + * 0 : 64 MHz internal oscillator (HFINT) + * 1 : 32 MHz external crystal oscillator (HFXO) + */ +#if !defined(NRF5_HFCLK_SOURCE) || defined(__DOXYGEN__) +#define NRF5_HFCLK_SOURCE NRF5_HFCLK_HFINT +#endif + +/** * @brief Select source of Low Frequency Clock (LFCLK) * @details Possible values for source are: * 0 : RC oscillator - * 1 : External cristal - * 2 : Synthetized clock from High Frequency Clock (HFCLK) - * When cristal is not available it's preferable to use the - * internal RC oscillator that synthezing the clock. + * 1 : External crystal + * 2 : Synthesized clock from High Frequency Clock (HFCLK) + * When crystal is not available it's preferable to use the + * internal RC oscillator that synthesizing the clock. */ #if !defined(NRF5_LFCLK_SOURCE) || defined(__DOXYGEN__) -#define NRF5_LFCLK_SOURCE 0 +#define NRF5_LFCLK_SOURCE NRF5_LFCLK_RC #endif /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ +#if (NRF5_HFCLK_SOURCE < 0) || (NRF5_HFCLK_SOURCE > 1) +#error "Possible value for NRF5_HFCLK_SOURCE are HFINT=0, HFXO=1" +#endif + #if (NRF5_LFCLK_SOURCE < 0) || (NRF5_LFCLK_SOURCE > 2) #error "Possible value for NRF5_LFCLK_SOURCE are 0=RC, 1=XTAL, 2=Synth" #endif @@ -91,8 +105,17 @@ /*===========================================================================*/ /* External declarations. */ /*===========================================================================*/ +#if 0 // moved to board.h +#define NRF5_HFCLK_HFINT 0 +#define NRF5_HFCLK_HFXO 1 + +#define NRF5_LFCLK_RC 0 +#define NRF5_LFCLK_XTAL 1 +#define NRF5_LFCLK_SYNTH 2 +#endif #include "nvic.h" +#include "nrf52_isr.h" #ifdef __cplusplus diff --git a/os/hal/ports/NRF5/NRF51822/hal_ext_lld_isr.c b/os/hal/ports/NRF5/NRF52832/nrf52_isr.c index ca8e24d..431bb3b 100644 --- a/os/hal/ports/NRF5/NRF51822/hal_ext_lld_isr.c +++ b/os/hal/ports/NRF5/NRF52832/nrf52_isr.c @@ -1,4 +1,5 @@ /*
+ Copyright (C) 2018 Konstantin Oblaukhov
Copyright (C) 2015 Stephen Caudle
Licensed under the Apache License, Version 2.0 (the "License");
@@ -15,19 +16,15 @@ */
/**
- * @file NRF51x22/ext_lld_isr.h
- * @brief NRF51x22 EXT subsystem low level driver ISR code.
+ * @file NRF52832/nrf52_isr.c
+ * @brief NRF52832 ISR handler code.
*
- * @addtogroup EXT
+ * @addtogroup NRF52832_ISR
* @{
*/
#include "hal.h"
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-#include "hal_ext_lld_isr.h"
-
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
@@ -44,12 +41,16 @@ /* Driver local functions. */
/*===========================================================================*/
+#if (HAL_USE_ICU && NRF5_ICU_USE_GPIOTE_PPI)
+extern void icu_lld_serve_gpiote_interrupt(ICUDriver *icup);
+#endif
+
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/**
- * @brief EXTI[0]...EXTI[1] interrupt handler.
+ * @brief GPIOTE interrupt handler.
*
* @isr
*/
@@ -57,26 +58,20 @@ OSAL_IRQ_HANDLER(Vector58) { OSAL_IRQ_PROLOGUE();
- if (NRF_GPIOTE->EVENTS_IN[0])
- {
- NRF_GPIOTE->EVENTS_IN[0] = 0;
- EXTD1.config->channels[0].cb(&EXTD1, 0);
- }
- if (NRF_GPIOTE->EVENTS_IN[1])
- {
- NRF_GPIOTE->EVENTS_IN[1] = 0;
- EXTD1.config->channels[1].cb(&EXTD1, 1);
- }
- if (NRF_GPIOTE->EVENTS_IN[2])
- {
- NRF_GPIOTE->EVENTS_IN[2] = 0;
- EXTD1.config->channels[2].cb(&EXTD1, 2);
- }
- if (NRF_GPIOTE->EVENTS_IN[3])
+#if (HAL_USE_ICU && NRF5_ICU_USE_GPIOTE_PPI)
+ icu_lld_serve_gpiote_interrupt(&ICUD1);
+#endif
+
+#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS))
+ for (int ch = 0; ch < NRF5_GPIOTE_NUM_CHANNELS; ch++)
{
- NRF_GPIOTE->EVENTS_IN[3] = 0;
- EXTD1.config->channels[3].cb(&EXTD1, 3);
+ if (NRF_GPIOTE->EVENTS_IN[ch])
+ {
+ NRF_GPIOTE->EVENTS_IN[ch] = 0;
+ _pal_isr_code(ch);
+ }
}
+#endif
OSAL_IRQ_EPILOGUE();
}
@@ -84,27 +79,28 @@ OSAL_IRQ_HANDLER(Vector58) { /*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
-
/**
- * @brief Enables EXTI IRQ sources.
+ * @brief Enables IRQ sources.
*
* @notapi
*/
-void ext_lld_exti_irq_enable(void) {
+void irqInit(void) {
- nvicEnableVector(GPIOTE_IRQn, NRF5_EXT_GPIOTE_IRQ_PRIORITY);
+#if HAL_USE_PAL
+ nvicEnableVector(GPIOTE_IRQn, NRF5_IRQ_GPIOTE_PRIORITY);
+#endif
}
/**
- * @brief Disables EXTI IRQ sources.
+ * @brief Disables IRQ sources.
*
* @notapi
*/
-void ext_lld_exti_irq_disable(void) {
+void irqDeinit(void) {
+#if HAL_USE_PAL
nvicDisableVector(GPIOTE_IRQn);
+#endif
}
-#endif /* HAL_USE_EXT */
-
/** @} */
diff --git a/os/hal/ports/NRF5/NRF52832/nrf52_isr.h b/os/hal/ports/NRF5/NRF52832/nrf52_isr.h new file mode 100644 index 0000000..b9f81d0 --- /dev/null +++ b/os/hal/ports/NRF5/NRF52832/nrf52_isr.h @@ -0,0 +1,44 @@ +/*
+ Copyright (C) 2018 Konstantin Oblaukhov
+ Copyright (C) 2015 Stephen Caudle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file NRF52832/nrf52_isr.h
+ * @brief NRF52832 ISR handler header.
+ *
+ * @addtogroup NRF52832_ISR
+ * @{
+ */
+
+#ifndef NRF52_ISR_H
+#define NRF52_ISR_H
+
+#if !defined(NRF5_IRQ_GPIOTE_PRIORITY) || defined(__DOXYGEN__)
+#define NRF5_IRQ_GPIOTE_PRIORITY 3
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void irqInit(void);
+ void irqDeinit(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NRF52_ISR_H */
+
+/** @} */
diff --git a/os/hal/ports/NRF5/NRF52832/nrf_delay.h b/os/hal/ports/NRF5/NRF52832/nrf_delay.h index 9b5df64..b73d8ae 100644 --- a/os/hal/ports/NRF5/NRF52832/nrf_delay.h +++ b/os/hal/ports/NRF5/NRF52832/nrf_delay.h @@ -1,97 +1,238 @@ -/* - Copyright (C) 2015 Stephen Caudle - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file NRF5/NRF52832/nrf_delay.h - * @brief NRF5 Delay routines - * - * @{ - */ - -#ifndef _NRF_DELAY_H -#define _NRF_DELAY_H - -inline static void nrf_delay_us(uint32_t volatile number_of_us) __attribute__((always_inline)); -inline static void nrf_delay_us(uint32_t volatile number_of_us) -{ -register uint32_t delay __asm ("r0") = number_of_us; -__asm volatile ( -".syntax unified\n" - "1:\n" - " SUBS %0, %0, #1\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " BNE 1b\n" - ".syntax divided\n" - : "+r" (delay)); -} -#endif //__NRF_DELAY_H +#ifndef _NRF_DELAY_H
+#define _NRF_DELAY_H
+
+/**
+ * @brief Function for delaying execution for number of microseconds.
+ *
+ * @note NRF52 has instruction cache and because of that delay is not precise.
+ *
+ * @param number_of_ms
+ */
+/*lint --e{438, 522} "Variable not used" "Function lacks side-effects" */
+#if defined ( __CC_ARM )
+
+static __ASM void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
+{
+loop
+ SUBS R0, R0, #1
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+#ifdef NRF52
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+#endif
+ BNE loop
+ BX LR
+}
+
+#elif defined ( __ICCARM__ )
+
+static void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
+{
+__ASM (
+"loop:\n\t"
+ " SUBS R0, R0, #1\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+#ifdef NRF52
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+#endif
+ " BNE.n loop\n\t");
+}
+
+#elif defined ( _WIN32 ) || defined ( __unix ) || defined( __APPLE__ )
+
+__STATIC_INLINE void nrf_delay_us(uint32_t volatile number_of_us);
+
+#ifndef CUSTOM_NRF_DELAY_US
+__STATIC_INLINE void nrf_delay_us(uint32_t volatile number_of_us)
+{}
+#endif
+
+#elif defined ( __GNUC__ )
+
+inline static void nrf_delay_us(uint32_t volatile number_of_us) __attribute__((always_inline));
+inline static void nrf_delay_us(uint32_t volatile number_of_us)
+{
+register uint32_t delay __ASM ("r0") = number_of_us;
+__ASM volatile (
+#ifdef NRF51
+ ".syntax unified\n"
+#endif
+ "1:\n"
+ " SUBS %0, %0, #1\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+#ifdef NRF52
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+ " NOP\n"
+#endif
+ " BNE 1b\n"
+#ifdef NRF51
+ ".syntax divided\n"
+#endif
+ : "+r" (delay));
+}
+#endif
+
+#endif
diff --git a/os/hal/ports/NRF5/NRF52832/platform.mk b/os/hal/ports/NRF5/NRF52832/platform.mk index 248027b..1e0a1af 100644 --- a/os/hal/ports/NRF5/NRF52832/platform.mk +++ b/os/hal/ports/NRF5/NRF52832/platform.mk @@ -1,52 +1,33 @@ +PLATFORMSRC_CONTRIB := ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF52832/hal_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF52832/nrf52_isr.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/TIMERv1/hal_st_lld.c + +PLATFORMINC_CONTRIB := ${CHIBIOS}/os/hal/ports/common/ARMCMx \ + ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD \ + ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF52832 + ifeq ($(USE_SMART_BUILD),yes) -HALCONF := $(strip $(shell cat halconf.h halconf_community.h 2>/dev/null | egrep -e "define")) -# List of all the NRF51x platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF52832/hal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_st_lld.c - -ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_pal_lld.c -endif -ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_serial_lld.c -endif -ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_spi_lld.c -endif -ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_i2c_lld.c -endif -ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_gpt_lld.c -endif -ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_wdg_lld.c -endif -ifneq ($(findstring HAL_USE_RNG TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_rng_lld.c -endif -ifneq ($(findstring HAL_USE_QEI TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_qei_lld.c -endif -else -PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF52832/hal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_pal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_serial_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_spi_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_i2c_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_st_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_gpt_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_wdg_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_rng_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_qei_lld.c +# Configuration files directory +ifeq ($(CONFDIR),) + CONFDIR = . endif -# Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF52832 +HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define")) + +endif +include ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/GPIOv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/UARTv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/SPIv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/TWIMv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/PWMv2/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/TIMERv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/WDTv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/RNGv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/QDECv1/driver.mk +# Shared variables +ALLCSRC += $(PLATFORMSRC_CONTRIB) +ALLINC += $(PLATFORMINC_CONTRIB) diff --git a/os/hal/ports/STM32/LLD/COMPv1/driver.mk b/os/hal/ports/STM32/LLD/COMPv1/driver.mk new file mode 100644 index 0000000..e819a32 --- /dev/null +++ b/os/hal/ports/STM32/LLD/COMPv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_COMP TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/COMPv1/hal_comp_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/COMPv1/hal_comp_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/COMPv1
diff --git a/os/hal/ports/STM32/LLD/CRCv1/driver.mk b/os/hal/ports/STM32/LLD/CRCv1/driver.mk new file mode 100644 index 0000000..b8c16d4 --- /dev/null +++ b/os/hal/ports/STM32/LLD/CRCv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_CRC TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1
diff --git a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c index 180a383..882022b 100755 --- a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c +++ b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c @@ -160,7 +160,7 @@ void crc_lld_start(CRCDriver *crcp) { if (crcp->config == NULL) crcp->config = &default_config; - rccEnableCRC(); + rccEnableCRC( FALSE ); #if STM32_CRC_PROGRAMMABLE == TRUE crcp->crc->INIT = crcp->config->initial_val; diff --git a/os/hal/ports/STM32/LLD/DMA2Dv1/driver.mk b/os/hal/ports/STM32/LLD/DMA2Dv1/driver.mk new file mode 100644 index 0000000..22be164 --- /dev/null +++ b/os/hal/ports/STM32/LLD/DMA2Dv1/driver.mk @@ -0,0 +1,2 @@ +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/DMA2Dv1
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/driver.mk b/os/hal/ports/STM32/LLD/FSMCv1/driver.mk new file mode 100644 index 0000000..d92230d --- /dev/null +++ b/os/hal/ports/STM32/LLD/FSMCv1/driver.mk @@ -0,0 +1,17 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_FSMC TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c
+endif
+ifneq ($(findstring HAL_USE_NAND TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1
diff --git a/os/hal/ports/STM32/LLD/LTDCv1/driver.mk b/os/hal/ports/STM32/LLD/LTDCv1/driver.mk new file mode 100644 index 0000000..d6cabcd --- /dev/null +++ b/os/hal/ports/STM32/LLD/LTDCv1/driver.mk @@ -0,0 +1,2 @@ +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/LTDCv1
diff --git a/os/hal/ports/STM32/LLD/OPAMPv1/driver.mk b/os/hal/ports/STM32/LLD/OPAMPv1/driver.mk new file mode 100644 index 0000000..08dc0f4 --- /dev/null +++ b/os/hal/ports/STM32/LLD/OPAMPv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_OPAMP TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/OPAMPv1/hal_opamp_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/OPAMPv1/hal_opamp_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/OPAMPv1
diff --git a/os/hal/ports/STM32/LLD/OPAMPv1/hal_opamp_lld.c b/os/hal/ports/STM32/LLD/OPAMPv1/hal_opamp_lld.c new file mode 100644 index 0000000..db988aa --- /dev/null +++ b/os/hal/ports/STM32/LLD/OPAMPv1/hal_opamp_lld.c @@ -0,0 +1,615 @@ +/* + ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio + Copyright (C) 2019 Fabien Poussin (fabien.poussin (at) google's mail) + Copyright (C) 2019 Alexandre Bustico + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + + +/** + * @file STM32/hal_opamp_lld.c + * @brief STM32 Operational Amplifier subsystem low level driver header. + * + * @addtogroup OPAMP + * @{ + */ + +#include "hal.h" + +#if HAL_USE_OPAMP || defined(__DOXYGEN__) + +#include "hal_opamp.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief OPAMPD1 driver identifier. + * @note The driver OPAMPD1 allocates the comparator OPAMP1 when enabled. + */ +#if STM32_OPAMP_USE_OPAMP1 || defined(__DOXYGEN__) +OPAMPDriver OPAMPD1; +#endif + +/** + * @brief OPAMPD2 driver identifier. + * @note The driver OPAMPD2 allocates the comparator OPAMP2 when enabled. + */ +#if STM32_OPAMP_USE_OPAMP2 || defined(__DOXYGEN__) +OPAMPDriver OPAMPD2; +#endif + +/** + * @brief OPAMPD3 driver identifier. + * @note The driver OPAMPD3 allocates the comparator OPAMP3 when enabled. + */ +#if STM32_OPAMP_USE_OPAMP3 || defined(__DOXYGEN__) +OPAMPDriver OPAMPD3; +#endif + +/** + * @brief OPAMPD4 driver identifier. + * @note The driver OPAMPD4 allocates the comparator OPAMP4 when enabled. + */ +#if STM32_OPAMP_USE_OPAMP4 || defined(__DOXYGEN__) +OPAMPDriver OPAMPD4; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level OPAMP driver initialization. + * + * @notapi + */ +void opamp_lld_init(void) { + +#if STM32_OPAMP_USE_OPAMP1 + /* Driver initialization.*/ + opampObjectInit(&OPAMPD1); + OPAMPD1.opamp = OPAMP; + OPAMPD1.opamp->CSR = 0; +#endif + +#if STM32_OPAMP_USE_OPAMP2 + /* Driver initialization.*/ + opampObjectInit(&OPAMPD2); + OPAMPD2.opamp = OPAMP2; + OPAMPD2.opamp->CSR = 0; +#endif + +#if STM32_OPAMP_USE_OPAMP3 + /* Driver initialization.*/ + opampObjectInit(&OPAMPD3); + OPAMPD3.opamp = OPAMP3; + OPAMPD3.opamp->CSR = 0; +#endif + +#if STM32_OPAMP_USE_OPAMP4 + /* Driver initialization.*/ + opampObjectInit(&OPAMPD4); + OPAMPD4.opamp = OPAMP4; + OPAMPD4.opamp->CSR = 0; +#endif + +} + +/** + * @brief Configures and activates the OPAMP peripheral. + * + * @param[in] opampp pointer to the @p OPAMPDriver object + * + * @notapi + */ +void opamp_lld_start(OPAMPDriver *opampp) { + + // Apply CSR Execpt the enable bit. + opampp->opamp->CSR = opampp->config->csr & ~OPAMP_CSR_OPAMPxEN; + +} + +/** + * @brief Deactivates the comp peripheral. + * + * @param[in] opampp pointer to the @p OPAMPDriver object + * + * @notapi + */ +void opamp_lld_stop(OPAMPDriver *opampp) { + + if (opampp->state == OPAMP_ACTIVE) { + + opampp->opamp->CSR = 0; + } + +} + +/** + * @brief Enables the output. + * + * @param[in] opampp pointer to the @p OPAMPDriver object + * + * @notapi + */ +void opamp_lld_enable(OPAMPDriver *opampp) { + + opampp->opamp->CSR |= OPAMP_CSR_OPAMPxEN; /* Enable */ +} + +/** + * @brief Disables the output. + * + * @param[in] opampp pointer to the @p OPAMPDriver object + * + * @notapi + */ +void opamp_lld_disable(OPAMPDriver *opampp) { + + opampp->opamp->CSR &= ~OPAMP_CSR_OPAMPxEN; /* Disable */ +} + +#if STM32_OPAMP_USER_TRIM_ENABLED + +void opamp_lld_calibrate_once(void) +{ +#if STM32_OPAMP_USE_OPAMP1 + uint32_t trimmingvaluen1 = 16U; + uint32_t trimmingvaluep1 = 16U; + OPAMPD1.state = OPAMP_CALIBRATING; +#define CSRm OPAMPD1.opamp->CSR + /* Set Calibration mode */ + /* Non-inverting input connected to calibration reference voltage. */ + CSRm |= OPAMP_CSR_FORCEVP; + /* user trimming values are used for offset calibration */ + CSRm |= OPAMP_CSR_USERTRIM; + /* Enable calibration */ + CSRm |= OPAMP_CSR_CALON; + /* 1st calibration - N Select 90U% VREF */ + MODIFY_REG(CSRm, OPAMP_CSR_CALSEL, OPAMPx_CSR_CALSEL_90P); + /* Enable the opamps */ + CSRm |= OPAMP_CSR_OPAMPxEN; +#undef CSRm +#endif + +#if STM32_OPAMP_USE_OPAMP2 + uint32_t trimmingvaluen2 = 16U; + uint32_t trimmingvaluep2 = 16U; + OPAMPD2.state = OPAMP_CALIBRATING; +#define CSRm OPAMPD2.opamp->CSR + CSRm |= OPAMP_CSR_FORCEVP; + CSRm |= OPAMP_CSR_USERTRIM; + CSRm |= OPAMP_CSR_CALON; + MODIFY_REG(CSRm, OPAMP_CSR_CALSEL, OPAMPx_CSR_CALSEL_90P); + CSRm |= OPAMP_CSR_OPAMPxEN; +#undef CSRm +#endif + +#if STM32_OPAMP_USE_OPAMP3 + uint32_t trimmingvaluen3 = 16U; + uint32_t trimmingvaluep3 = 16U; + OPAMPD3.state = OPAMP_CALIBRATING; +#define CSRm OPAMPD3.opamp->CSR + CSRm |= OPAMP_CSR_FORCEVP; + CSRm |= OPAMP_CSR_USERTRIM; + CSRm |= OPAMP_CSR_CALON; + MODIFY_REG(CSRm, OPAMP_CSR_CALSEL, OPAMPx_CSR_CALSEL_90P); + CSRm |= OPAMP_CSR_OPAMPxEN; +#undef CSRm +#endif + +#if STM32_OPAMP_USE_OPAMP4 + uint32_t trimmingvaluen4 = 16U; + uint32_t trimmingvaluep4 = 16U; + OPAMPD4.state = OPAMP_CALIBRATING; +#define CSRm OPAMPD4.opamp->CSR + CSRm |= OPAMP_CSR_FORCEVP; + CSRm |= OPAMP_CSR_USERTRIM; + CSRm |= OPAMP_CSR_CALON; + MODIFY_REG(CSRm, OPAMP_CSR_CALSEL, OPAMPx_CSR_CALSEL_90P); + CSRm |= OPAMP_CSR_OPAMPxEN; +#undef CSRm +#endif + + chSysPolledDelayX(MS2RTC(STM32_SYSCLK, 20)); + uint32_t delta = 8U; + + while (delta != 0U) { +#if STM32_OPAMP_USE_OPAMP1 + MODIFY_REG(OPAMPD1.opamp->CSR, OPAMP_CSR_TRIMOFFSETN, + trimmingvaluen1<<OPAMP_CSR_TRIMOFFSETN_Pos); +#endif +#if STM32_OPAMP_USE_OPAMP2 + MODIFY_REG(OPAMPD2.opamp->CSR, OPAMP_CSR_TRIMOFFSETN, + trimmingvaluen2<<OPAMP_CSR_TRIMOFFSETN_Pos); +#endif +#if STM32_OPAMP_USE_OPAMP3 + MODIFY_REG(OPAMPD3.opamp->CSR, OPAMP_CSR_TRIMOFFSETN, + trimmingvaluen3<<OPAMP_CSR_TRIMOFFSETN_Pos); +#endif +#if STM32_OPAMP_USE_OPAMP4 + MODIFY_REG(OPAMPD4.opamp->CSR, OPAMP_CSR_TRIMOFFSETN, + trimmingvaluen4<<OPAMP_CSR_TRIMOFFSETN_Pos); +#endif + + /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */ + /* Offset trim time: during calibration, minimum time needed between */ + /* two steps to have 1 mV accuracy */ + chSysPolledDelayX(MS2RTC(STM32_SYSCLK, 2)); + +#if STM32_OPAMP_USE_OPAMP1 + if (OPAMPD1.opamp->CSR & OPAMP_CSR_OUTCAL) { + /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */ + trimmingvaluen1 += delta; + } else { + /* OPAMP_CSR_OUTCAL is LOW try lower trimming */ + trimmingvaluen1 -= delta; + } +#endif + +#if STM32_OPAMP_USE_OPAMP2 + if (OPAMPD2.opamp->CSR & OPAMP_CSR_OUTCAL) { + trimmingvaluen2 += delta; + } else { + trimmingvaluen2 -= delta; + } +#endif + +#if STM32_OPAMP_USE_OPAMP3 + if (OPAMPD3.opamp->CSR & OPAMP_CSR_OUTCAL) { + trimmingvaluen3 += delta; + } else { + trimmingvaluen3 -= delta; + } +#endif + +#if STM32_OPAMP_USE_OPAMP4 + if (OPAMPD4.opamp->CSR & OPAMP_CSR_OUTCAL) { + trimmingvaluen4 += delta; + } else { + trimmingvaluen4 -= delta; + } +#endif + + delta >>= 1U; + + } + + /* Still need to check if righ calibration is current value or un step below */ + /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0U */ +#if STM32_OPAMP_USE_OPAMP1 + MODIFY_REG(OPAMPD1.opamp->CSR, OPAMP_CSR_TRIMOFFSETN, + trimmingvaluen1<<OPAMP_CSR_TRIMOFFSETN_Pos); +#endif +#if STM32_OPAMP_USE_OPAMP2 + MODIFY_REG(OPAMPD2.opamp->CSR, OPAMP_CSR_TRIMOFFSETN, + trimmingvaluen2<<OPAMP_CSR_TRIMOFFSETN_Pos); +#endif +#if STM32_OPAMP_USE_OPAMP3 + MODIFY_REG(OPAMPD3.opamp->CSR, OPAMP_CSR_TRIMOFFSETN, + trimmingvaluen3<<OPAMP_CSR_TRIMOFFSETN_Pos); +#endif +#if STM32_OPAMP_USE_OPAMP4 + MODIFY_REG(OPAMPD4.opamp->CSR, OPAMP_CSR_TRIMOFFSETN, + trimmingvaluen4<<OPAMP_CSR_TRIMOFFSETN_Pos); +#endif + + /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */ + /* Offset trim time: during calibration, minimum time needed between */ + /* two steps to have 1 mV accuracy */ + chSysPolledDelayX(MS2RTC(STM32_SYSCLK, 2)); + +#if STM32_OPAMP_USE_OPAMP1 + if (OPAMPD1.opamp->CSR & OPAMP_CSR_OUTCAL) { + /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */ + trimmingvaluen1 += (trimmingvaluen1 != 31); + MODIFY_REG(OPAMPD1.opamp->CSR, OPAMP_CSR_TRIMOFFSETN, + trimmingvaluen1<<OPAMP_CSR_TRIMOFFSETN_Pos); + } +#endif + +#if STM32_OPAMP_USE_OPAMP2 + if (OPAMPD2.opamp->CSR & OPAMP_CSR_OUTCAL) { + trimmingvaluen2 += (trimmingvaluen2 != 31); + MODIFY_REG(OPAMPD2.opamp->CSR, OPAMP_CSR_TRIMOFFSETN, + trimmingvaluen2<<OPAMP_CSR_TRIMOFFSETN_Pos); + } +#endif + +#if STM32_OPAMP_USE_OPAMP3 + if (OPAMPD3.opamp->CSR & OPAMP_CSR_OUTCAL) { + trimmingvaluen3 += (trimmingvaluen3 != 31); + MODIFY_REG(OPAMPD3.opamp->CSR, OPAMP_CSR_TRIMOFFSETN, + trimmingvaluen3<<OPAMP_CSR_TRIMOFFSETN_Pos); + } +#endif + +#if STM32_OPAMP_USE_OPAMP4 + if (OPAMPD4.opamp->CSR & OPAMP_CSR_OUTCAL) { + trimmingvaluen4 += (trimmingvaluen4 != 31); + MODIFY_REG(OPAMPD4.opamp->CSR, OPAMP_CSR_TRIMOFFSETN, + trimmingvaluen4<<OPAMP_CSR_TRIMOFFSETN_Pos); + } +#endif + + /* 2nd calibration - P */ + /* Select 10U% VREF */ +#if STM32_OPAMP_USE_OPAMP1 + MODIFY_REG(OPAMPD1.opamp->CSR, OPAMP_CSR_CALSEL, OPAMPx_CSR_CALSEL_10P); +#endif +#if STM32_OPAMP_USE_OPAMP2 + MODIFY_REG(OPAMPD2.opamp->CSR, OPAMP_CSR_CALSEL, OPAMPx_CSR_CALSEL_10P); +#endif +#if STM32_OPAMP_USE_OPAMP3 + MODIFY_REG(OPAMPD3.opamp->CSR, OPAMP_CSR_CALSEL, OPAMPx_CSR_CALSEL_10P); +#endif +#if STM32_OPAMP_USE_OPAMP4 + MODIFY_REG(OPAMPD4.opamp->CSR, OPAMP_CSR_CALSEL, OPAMPx_CSR_CALSEL_10P); +#endif + + delta = 8U; + + while (delta != 0U) { +#if STM32_OPAMP_USE_OPAMP1 + MODIFY_REG(OPAMPD1.opamp->CSR, OPAMP_CSR_TRIMOFFSETP, + trimmingvaluep1<<OPAMP_CSR_TRIMOFFSETP_Pos); +#endif +#if STM32_OPAMP_USE_OPAMP2 + MODIFY_REG(OPAMPD2.opamp->CSR, OPAMP_CSR_TRIMOFFSETP, + trimmingvaluep2<<OPAMP_CSR_TRIMOFFSETP_Pos); +#endif +#if STM32_OPAMP_USE_OPAMP3 + MODIFY_REG(OPAMPD3.opamp->CSR, OPAMP_CSR_TRIMOFFSETP, + trimmingvaluep3<<OPAMP_CSR_TRIMOFFSETP_Pos); +#endif +#if STM32_OPAMP_USE_OPAMP4 + MODIFY_REG(OPAMPD4.opamp->CSR, OPAMP_CSR_TRIMOFFSETP, + trimmingvaluep4<<OPAMP_CSR_TRIMOFFSETP_Pos); +#endif + + + /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */ + /* Offset trim time: during calibration, minimum time needed between */ + /* two steps to have 1 mV accuracy */ + chSysPolledDelayX(MS2RTC(STM32_SYSCLK, 2)); +#if STM32_OPAMP_USE_OPAMP1 + if (OPAMPD1.opamp->CSR & OPAMP_CSR_OUTCAL) { + /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */ + trimmingvaluep1 += delta; + } else { + /* OPAMP_CSR_OUTCAL is LOW try lower trimming */ + trimmingvaluep1 -= delta; + } +#endif + +#if STM32_OPAMP_USE_OPAMP2 + if (OPAMPD2.opamp->CSR & OPAMP_CSR_OUTCAL) { + trimmingvaluep2 += delta; + } else { + trimmingvaluep2 -= delta; + } +#endif + +#if STM32_OPAMP_USE_OPAMP3 + if (OPAMPD3.opamp->CSR & OPAMP_CSR_OUTCAL) { + trimmingvaluep3 += delta; + } else { + trimmingvaluep3 -= delta; + } +#endif + +#if STM32_OPAMP_USE_OPAMP4 + if (OPAMPD4.opamp->CSR & OPAMP_CSR_OUTCAL) { + trimmingvaluep4 += delta; + } else { + trimmingvaluep4 -= delta; + } +#endif + + delta >>= 1U; + } + + /* Still need to check if righ calibration is current value or un step below */ + /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0U */ +#if STM32_OPAMP_USE_OPAMP1 + MODIFY_REG(OPAMPD1.opamp->CSR, OPAMP_CSR_TRIMOFFSETP, + trimmingvaluep1<<OPAMP_CSR_TRIMOFFSETP_Pos); +#endif +#if STM32_OPAMP_USE_OPAMP2 + MODIFY_REG(OPAMPD2.opamp->CSR, OPAMP_CSR_TRIMOFFSETP, + trimmingvaluep2<<OPAMP_CSR_TRIMOFFSETP_Pos); +#endif +#if STM32_OPAMP_USE_OPAMP3 + MODIFY_REG(OPAMPD3.opamp->CSR, OPAMP_CSR_TRIMOFFSETP, + trimmingvaluep3<<OPAMP_CSR_TRIMOFFSETP_Pos); +#endif +#if STM32_OPAMP_USE_OPAMP4 + MODIFY_REG(OPAMPD4.opamp->CSR, OPAMP_CSR_TRIMOFFSETP, + trimmingvaluep4<<OPAMP_CSR_TRIMOFFSETP_Pos); +#endif + + /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */ + /* Offset trim time: during calibration, minimum time needed between */ + /* two steps to have 1 mV accuracy */ + chSysPolledDelayX(MS2RTC(STM32_SYSCLK, 2)); + +#if STM32_OPAMP_USE_OPAMP1 + if (OPAMPD1.opamp->CSR & OPAMP_CSR_OUTCAL) { + /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */ + trimmingvaluep1 += (trimmingvaluep1 != 31); + MODIFY_REG(OPAMPD1.opamp->CSR, OPAMP_CSR_TRIMOFFSETP, + trimmingvaluep1<<OPAMP_CSR_TRIMOFFSETP_Pos); + } +#endif + +#if STM32_OPAMP_USE_OPAMP2 + if (OPAMPD2.opamp->CSR & OPAMP_CSR_OUTCAL) { + trimmingvaluep2 += (trimmingvaluep2 != 31); + MODIFY_REG(OPAMPD2.opamp->CSR, OPAMP_CSR_TRIMOFFSETP, + trimmingvaluep2<<OPAMP_CSR_TRIMOFFSETP_Pos); + } +#endif + +#if STM32_OPAMP_USE_OPAMP3 + if (OPAMPD3.opamp->CSR & OPAMP_CSR_OUTCAL) { + trimmingvaluep3 += (trimmingvaluep3 != 31); + MODIFY_REG(OPAMPD3.opamp->CSR, OPAMP_CSR_TRIMOFFSETP, + trimmingvaluep3<<OPAMP_CSR_TRIMOFFSETP_Pos); + } +#endif + +#if STM32_OPAMP_USE_OPAMP4 + if (OPAMPD4.opamp->CSR & OPAMP_CSR_OUTCAL) { + trimmingvaluep4 += (trimmingvaluep4 != 31); + MODIFY_REG(OPAMPD4.opamp->CSR, OPAMP_CSR_TRIMOFFSETP, + trimmingvaluep4<<OPAMP_CSR_TRIMOFFSETP_Pos); + } +#endif + +#if STM32_OPAMP_USE_OPAMP1 +#define CSRm OPAMPD1.opamp->CSR + /* Disable calibration */ + CSRm &= ~OPAMP_CSR_CALON; + /* Disable the OPAMPs */ + CSRm &= ~OPAMP_CSR_OPAMPxEN; + /* Set normal operating mode back */ + CSRm &= ~OPAMP_CSR_FORCEVP; + /* Write calibration result N */ + OPAMPD1.trim_n = trimmingvaluen1; + /* Write calibration result P */ + OPAMPD1.trim_p = trimmingvaluep1; + MODIFY_REG(CSRm, OPAMP_CSR_TRIMOFFSETN, + trimmingvaluen1<<OPAMP_CSR_TRIMOFFSETN_Pos); + MODIFY_REG(CSRm, OPAMP_CSR_TRIMOFFSETP, + trimmingvaluep1<<OPAMP_CSR_TRIMOFFSETP_Pos); + OPAMPD1.state = OPAMP_STOP; +#undef CSRm +#endif + +#if STM32_OPAMP_USE_OPAMP2 +#define CSRm OPAMPD2.opamp->CSR + /* Disable calibration */ + CSRm &= ~OPAMP_CSR_CALON; + /* Disable the OPAMPs */ + CSRm &= ~OPAMP_CSR_OPAMPxEN; + /* Set normal operating mode back */ + CSRm &= ~OPAMP_CSR_FORCEVP; + /* Write calibration result N */ + OPAMPD2.trim_n = trimmingvaluen2; + /* Write calibration result P */ + OPAMPD2.trim_p = trimmingvaluep2; + MODIFY_REG(CSRm, OPAMP_CSR_TRIMOFFSETN, + trimmingvaluen2<<OPAMP_CSR_TRIMOFFSETN_Pos); + MODIFY_REG(CSRm, OPAMP_CSR_TRIMOFFSETP, + trimmingvaluep2<<OPAMP_CSR_TRIMOFFSETP_Pos); + OPAMPD2.state = OPAMP_STOP; +#undef CSRm +#endif + +#if STM32_OPAMP_USE_OPAMP3 +#define CSRm OPAMPD3.opamp->CSR + /* Disable calibration */ + CSRm &= ~OPAMP_CSR_CALON; + /* Disable the OPAMPs */ + CSRm &= ~OPAMP_CSR_OPAMPxEN; + /* Set normal operating mode back */ + CSRm &= ~OPAMP_CSR_FORCEVP; + /* Write calibration result N */ + OPAMPD3.trim_n = trimmingvaluen3; + /* Write calibration result P */ + OPAMPD3.trim_p = trimmingvaluep3; + MODIFY_REG(CSRm, OPAMP_CSR_TRIMOFFSETN, + trimmingvaluen3<<OPAMP_CSR_TRIMOFFSETN_Pos); + MODIFY_REG(CSRm, OPAMP_CSR_TRIMOFFSETP, + trimmingvaluep3<<OPAMP_CSR_TRIMOFFSETP_Pos); + OPAMPD3.state = OPAMP_STOP; +#undef CSRm +#endif + +#if STM32_OPAMP_USE_OPAMP4 +#define CSRm OPAMPD4.opamp->CSR + /* Disable calibration */ + CSRm &= ~OPAMP_CSR_CALON; + /* Disable the OPAMPs */ + CSRm &= ~OPAMP_CSR_OPAMPxEN; + /* Set normal operating mode back */ + CSRm &= ~OPAMP_CSR_FORCEVP; + /* Write calibration result N */ + OPAMPD4.trim_n = trimmingvaluen4; + /* Write calibration result P */ + OPAMPD4.trim_p = trimmingvaluep4; + MODIFY_REG(CSRm, OPAMP_CSR_TRIMOFFSETN, + trimmingvaluen4<<OPAMP_CSR_TRIMOFFSETN_Pos); + MODIFY_REG(CSRm, OPAMP_CSR_TRIMOFFSETP, + trimmingvaluep4<<OPAMP_CSR_TRIMOFFSETP_Pos); + OPAMPD4.state = OPAMP_STOP; +#undef CSRm +#endif +} + +void opamp_lld_calibrate(void) +{ + uint8_t trim_n[4] = {255}; + uint8_t trim_p[4] = {255}; + bool done; + do { + done = true; + opamp_lld_calibrate_once(); +#if STM32_OPAMP_USE_OPAMP1 + done = done && (OPAMPD1.trim_n == trim_n[0]) && (OPAMPD1.trim_p == trim_p[0]); + trim_n[0] = OPAMPD1.trim_n; + trim_p[0] = OPAMPD1.trim_p; +#endif +#if STM32_OPAMP_USE_OPAMP2 + done = done && (OPAMPD2.trim_n == trim_n[1]) && (OPAMPD2.trim_p == trim_p[1]); + trim_n[1] = OPAMPD2.trim_n; + trim_p[1] = OPAMPD2.trim_p; +#endif +#if STM32_OPAMP_USE_OPAMP3 + done = done && (OPAMPD3.trim_n == trim_n[2]) && (OPAMPD3.trim_p == trim_p[2]); + trim_n[2] = OPAMPD3.trim_n; + trim_p[2] = OPAMPD3.trim_p; +#endif +#if STM32_OPAMP_USE_OPAMP4 + done = done && (OPAMPD4.trim_n == trim_n[3]) && (OPAMPD4.trim_p == trim_p[3]); + trim_n[3] = OPAMPD4.trim_n; + trim_p[3] = OPAMPD4.trim_p; +#endif + } while (!done); + +} +#endif // STM32_OPAMP_USER_TRIM_ENABLED +#endif /* HAL_USE_OPAMP */ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/OPAMPv1/hal_opamp_lld.h b/os/hal/ports/STM32/LLD/OPAMPv1/hal_opamp_lld.h new file mode 100644 index 0000000..6a701b9 --- /dev/null +++ b/os/hal/ports/STM32/LLD/OPAMPv1/hal_opamp_lld.h @@ -0,0 +1,336 @@ +/* + ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio + Copyright (C) 2019 Fabien Poussin (fabien.poussin (at) google's mail) + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32/opamp_lld.h + * @brief STM32 Operational Amplifier subsystem low level driver header. + * + * @addtogroup OPAMP + * @{ + */ + +#ifndef HAL_OPAMP_LLD_H_ +#define HAL_OPAMP_LLD_H_ + +#include "hal.h" + +#if HAL_USE_OPAMP || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define OPAMPx_CSR_PGAGAIN_x2 ((uint32_t)0x00000000) +#define OPAMPx_CSR_PGAGAIN_x4 OPAMP_CSR_PGGAIN_0 +#define OPAMPx_CSR_PGAGAIN_x8 OPAMP_CSR_PGGAIN_1 +#define OPAMPx_CSR_PGAGAIN_x16 ((uint32_t)0x0000C000) +#define OPAMPx_CSR_PGAGAIN_LESS_IFB_VM0 (0b10 << 16) +#define OPAMPx_CSR_PGAGAIN_LESS_IFB_VM1 (0b11 << 16) + +#define OPAMPx_CSR_PGACONNECT_GROUND ((uint32_t)0x00000000) +#define OPAMPx_CSR_PGACONNECT_IO1 OPAMP_CSR_PGGAIN_3 +#define OPAMPx_CSR_PGACONNECT_IO2 ((uint32_t)0x00030000) + +#define OPAMPx_CSR_CALSEL_3P3 ((uint32_t)0x00000000) +#define OPAMPx_CSR_CALSEL_10P OPAMP_CSR_CALSEL_0 +#define OPAMPx_CSR_CALSEL_50P OPAMP_CSR_CALSEL_1 +#define OPAMPx_CSR_CALSEL_90P OPAMP_CSR_CALSEL + +#define OPAMPx_CSR_TRIM_FACTORY ((uint32_t)0x00000000) +#define OPAMPx_CSR_TRIM_USER OPAMP_CSR_USERTRIM /*!< User trimming */ + +#define OPAMPx_CSR_OUTPUT_NORMAL ((uint32_t)0x00000000) +#define OPAMPx_CSR_OUTPUT_INVERTED OPAMP_CSR_OUTCAL + +#define OPAMPx_CSR_LOCK OPAMP_CSR_LOCK + + +#if defined(STM32F302xB) || defined(STM32F302xC) || defined(STM32F302xD) \ +|| defined(STM32F302xE) || defined(STM32F302xc) || defined(STM32F302xe) \ +|| defined(STM32L1XX) || defined(STM32L4XX) || defined(STM32H7XX) +#define STM32_HAS_OPAMP1 TRUE +#define STM32_HAS_OPAMP2 TRUE +#define STM32_HAS_OPAMP3 FALSE +#define STM32_HAS_OPAMP4 FALSE + +#elif defined(STM32F303xB) || defined(STM32F303xC) || defined(STM32F303xE) \ +|| defined(STM32F358xx) || defined(STM32F398xx) +#define STM32_HAS_OPAMP1 TRUE +#define STM32_HAS_OPAMP2 TRUE +#define STM32_HAS_OPAMP3 TRUE +#define STM32_HAS_OPAMP4 TRUE + +#else +#define STM32_HAS_OPAMP1 FALSE +#define STM32_HAS_OPAMP2 FALSE +#define STM32_HAS_OPAMP3 FALSE +#define STM32_HAS_OPAMP4 FALSE +#endif + + +#if STM32_HAS_OPAMP1 +#define OPAMP1_CSR_VPSEL_PA07 ((uint32_t)0x00000000) +#define OPAMP1_CSR_VPSEL_PA05 OPAMP_CSR_VPSEL_0 +#define OPAMP1_CSR_VPSEL_PA03 OPAMP_CSR_VPSEL_1 +#define OPAMP1_CSR_VPSEL_PA01 OPAMP_CSR_VPSEL + +#define OPAMP1_CSR_VMSEL_PC05 ((uint32_t)0x00000000) +#define OPAMP1_CSR_VMSEL_PA03 OPAMP_CSR_VMSEL_0 +#define OPAMP1_CSR_VMSEL_PGA OPAMP_CSR_VMSEL_1 +#define OPAMP1_CSR_VMSEL_FOLWR OPAMP_CSR_VMSEL + +#define OPAMP1_CSR_VMSSEL_PC05 ((uint32_t)0x00000000) +#define OPAMP1_CSR_VMSSEL_PA03 OPAMP_CSR_VMSSEL + +#define OPAMP1_CSR_VPSSEL_PA07 ((uint32_t)0x00000000) +#define OPAMP1_CSR_VPSSEL_PA05 OPAMP_CSR_VPSSEL_0 +#define OPAMP1_CSR_VPSSEL_PA03 OPAMP_CSR_VPSSEL_1 +#define OPAMP1_CSR_VPSSEL_PA01 OPAMP_CSR_VPSSEL +#endif + +#if STM32_HAS_OPAMP2 +#define OPAMP2_CSR_VPSEL_PD14 ((uint32_t)0x00000000) +#define OPAMP2_CSR_VPSEL_PB14 OPAMP_CSR_VPSEL_0 +#define OPAMP2_CSR_VPSEL_PB00 OPAMP_CSR_VPSEL_1 +#define OPAMP2_CSR_VPSEL_PA07 OPAMP_CSR_VPSEL + +#define OPAMP2_CSR_VMSEL_PC05 ((uint32_t)0x00000000) +#define OPAMP2_CSR_VMSEL_PA05 OPAMP_CSR_VMSEL_0 +#define OPAMP2_CSR_VMSEL_PGA OPAMP_CSR_VMSEL_1 +#define OPAMP2_CSR_VMSEL_FOLWR OPAMP_CSR_VMSEL + +#define OPAMP2_CSR_VMSSEL_PC05 ((uint32_t)0x00000000) +#define OPAMP2_CSR_VMSSEL_PA05 OPAMP_CSR_VMSSEL + +#define OPAMP2_CSR_VPSSEL_PD14 ((uint32_t)0x00000000) +#define OPAMP2_CSR_VPSSEL_PB14 OPAMP_CSR_VPSSEL_0 +#define OPAMP2_CSR_VPSSEL_PB00 OPAMP_CSR_VPSSEL_1 +#define OPAMP2_CSR_VPSSEL_PA07 OPAMP_CSR_VPSSEL +#endif + +#if STM32_HAS_OPAMP3 +#define OPAMP3_CSR_VPSEL_PB13 ((uint32_t)0x00000000) +#define OPAMP3_CSR_VPSEL_PA05 OPAMP_CSR_VPSEL_0 +#define OPAMP3_CSR_VPSEL_PA01 OPAMP_CSR_VPSEL_1 +#define OPAMP3_CSR_VPSEL_PB00 OPAMP_CSR_VPSEL + +#define OPAMP3_CSR_VMSEL_PB10 ((uint32_t)0x00000000) +#define OPAMP3_CSR_VMSEL_PB02 OPAMP_CSR_VMSEL_0 +#define OPAMP3_CSR_VMSEL_PGA OPAMP_CSR_VMSEL_1 +#define OPAMP3_CSR_VMSEL_FOLWR OPAMP_CSR_VMSEL + +#define OPAMP3_CSR_VMSSEL_PB10 ((uint32_t)0x00000000) +#define OPAMP3_CSR_VMSSEL_PB02 OPAMP_CSR_VMSSEL + +#define OPAMP3_CSR_VPSSEL_PB13 ((uint32_t)0x00000000) +#define OPAMP3_CSR_VPSSEL_PA05 OPAMP_CSR_VPSSEL_0 +#define OPAMP3_CSR_VPSSEL_PA01 OPAMP_CSR_VPSSEL_1 +#define OPAMP3_CSR_VPSSEL_PB00 OPAMP_CSR_VPSSEL +#endif + +#if STM32_HAS_OPAMP4 +#define OPAMP4_CSR_VPSEL_PD11 ((uint32_t)0x00000000) +#define OPAMP4_CSR_VPSEL_PB11 OPAMP_CSR_VPSEL_0 +#define OPAMP4_CSR_VPSEL_PA04 OPAMP_CSR_VPSEL_1 +#define OPAMP4_CSR_VPSEL_PB13 OPAMP_CSR_VPSEL + +#define OPAMP4_CSR_VMSEL_PB10 ((uint32_t)0x00000000) +#define OPAMP4_CSR_VMSEL_PD08 OPAMP_CSR_VMSEL_0 +#define OPAMP4_CSR_VMSEL_PGA OPAMP_CSR_VMSEL_1 +#define OPAMP4_CSR_VMSEL_FOLWR OPAMP_CSR_VMSEL + +#define OPAMP4_CSRVMSSEL_PB10 ((uint32_t)0x00000000) +#define OPAMP4_CSR_VMSSEL_PD08 OPAMP_CSR_VMSSEL + +#define OPAMP4_CSR_VPSSEL_PD11 ((uint32_t)0x00000000) +#define OPAMP4_CSR_VPSSEL_PB11 OPAMP_CSR_VPSSEL_0 +#define OPAMP4_CSR_VPSSEL_PA04 OPAMP_CSR_VPSSEL_1 +#define OPAMP4_CSR_VPSSEL_PB13 OPAMP_CSR_VPSSEL +#endif + + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ + +/** + * @brief OPAMPD1 driver enable switch. + * @details If set to @p TRUE the support for OPAMPD1 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_OPAMP_USE_OPAMP1) || defined(__DOXYGEN__) +#define STM32_OPAMP_USE_OPAMP1 FALSE +#endif + +/** + * @brief OPAMPD2 driver enable switch. + * @details If set to @p TRUE the support for OPAMPD2 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_OPAMP_USE_OPAMP2) || defined(__DOXYGEN__) +#define STM32_OPAMP_USE_OPAMP2 FALSE +#endif + +/** + * @brief OPAMPD3 driver enable switch. + * @details If set to @p TRUE the support for OPAMPD3 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_OPAMP_USE_OPAMP3) || defined(__DOXYGEN__) +#define STM32_OPAMP_USE_OPAMP3 FALSE +#endif + +/** + * @brief OPAMPD4 driver enable switch. + * @details If set to @p TRUE the support for OPAMPD4 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_OPAMP_USE_OPAMP4) || defined(__DOXYGEN__) +#define STM32_OPAMP_USE_OPAMP4 FALSE +#endif + +/** + * @brief OPAMPD TRIM and CALIBRATION enable switch. + * @details If set to @p TRUE the support for USER_TRIM is included and calibration is done @init + * @note The default is @p TRUE. + */ +#if !defined(STM32_OPAMP_USER_TRIM_ENABLED) || defined(__DOXYGEN__) +#define STM32_OPAMP_USER_TRIM_ENABLED TRUE +#endif + + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + + +#if STM32_OPAMP_USE_OPAMP1 && !STM32_HAS_OPAMP1 +#error "OPAMP1 not present in the selected device" +#endif + +#if STM32_OPAMP_USE_OPAMP2 && !STM32_HAS_OPAMP2 +#error "OPAMP2 not present in the selected device" +#endif + +#if STM32_OPAMP_USE_OPAMP3 && !STM32_HAS_OPAMP3 +#error "OPAMP3 not present in the selected device" +#endif + +#if STM32_OPAMP_USE_OPAMP4 && !STM32_HAS_OPAMP4 +#error "OPAMP4 not present in the selected device" +#endif + +#if !STM32_OPAMP_USE_OPAMP1 && !STM32_OPAMP_USE_OPAMP2 && \ + !STM32_OPAMP_USE_OPAMP3 && !STM32_OPAMP_USE_OPAMP4 +#error "OPAMP driver activated but no OPAMP peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief OPAMP CSR register initialization data. + * @note The value of this field should normally be equal to zero. + */ + uint32_t csr; +} OPAMPConfig; + +/** + * @brief Structure representing an OPAMP driver. + */ +struct OPAMPDriver { + /** + * @brief Driver state. + */ + opampstate_t state; + /** + * @brief Current configuration data. + */ + const OPAMPConfig *config; +#if defined(OPAMP_DRIVER_EXT_FIELDS) + OPAMP_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the OPAMPx registers block. + */ + OPAMP_TypeDef *opamp; + +#if STM32_OPAMP_USER_TRIM_ENABLED + uint16_t trim_p; + uint16_t trim_n; +#endif +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_OPAMP_USE_OPAMP1 && !defined(__DOXYGEN__) +extern OPAMPDriver OPAMPD1; +#endif + +#if STM32_OPAMP_USE_OPAMP2 && !defined(__DOXYGEN__) +extern OPAMPDriver OPAMPD2; +#endif + +#if STM32_OPAMP_USE_OPAMP3 && !defined(__DOXYGEN__) +extern OPAMPDriver OPAMPD3; +#endif + +#if STM32_OPAMP_USE_OPAMP4 && !defined(__DOXYGEN__) +extern OPAMPDriver OPAMPD4; +#endif + + +#ifdef __cplusplus +extern "C" { +#endif + void opamp_lld_init(void); + void opamp_lld_start(OPAMPDriver *compp); + void opamp_lld_stop(OPAMPDriver *compp); + void opamp_lld_enable(OPAMPDriver *compp); + void opamp_lld_disable(OPAMPDriver *compp); +#if STM32_OPAMP_USER_TRIM_ENABLED + void opamp_lld_calibrate(void); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_OPAMP */ + +#endif /* _opamp_lld_H_ */ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/TIMv1/driver.mk b/os/hal/ports/STM32/LLD/TIMv1/driver.mk new file mode 100644 index 0000000..86eb7c7 --- /dev/null +++ b/os/hal/ports/STM32/LLD/TIMv1/driver.mk @@ -0,0 +1,17 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_EICU TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c
+endif
+ifneq ($(findstring HAL_USE_QEI TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
+endif
+ifneq ($(findstring HAL_USE_TIMCAP TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1
diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h index 73468f5..a9bdaf4 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h @@ -415,7 +415,7 @@ struct QEIDriver { *
* @notapi
*/
-#define qei_lld_set_count(qeip, value)
+#define qei_lld_set_count(qeip, value) ((qeip)->tim->CNT = (value))
/*===========================================================================*/
/* External declarations. */
diff --git a/os/hal/ports/STM32/LLD/USBHv1/driver.mk b/os/hal/ports/STM32/LLD/USBHv1/driver.mk new file mode 100644 index 0000000..b8f8988 --- /dev/null +++ b/os/hal/ports/STM32/LLD/USBHv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_USBH TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1
diff --git a/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c b/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c index 226f1bb..192b008 100644 --- a/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c +++ b/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c @@ -594,9 +594,10 @@ void usbh_lld_ep_open(usbh_ep_t *ep) { } void usbh_lld_ep_close(usbh_ep_t *ep) { - usbh_urb_t *urb, *tmp; + usbh_urb_t *urb; uinfof("\t%s: Closing EP...", ep->name); - list_for_each_entry_safe(urb, usbh_urb_t, tmp, &ep->urb_list, node) { + while (!list_empty(&ep->urb_list)) { + urb = list_first_entry(&ep->urb_list, usbh_urb_t, node); uinfof("\t%s: Abort URB, USBH_URBSTATUS_DISCONNECTED", ep->name); _usbh_urb_abort_and_waitS(urb, USBH_URBSTATUS_DISCONNECTED); } @@ -987,7 +988,7 @@ static inline void _hcint_int(USBHDriver *host) { haint = host->otg->HAINT; haint &= host->otg->HAINTMSK; -#if USBH_LLD_DEBUG_ENABLE_ERRORS +#if USBH_DEBUG_ENABLE && USBH_LLD_DEBUG_ENABLE_ERRORS if (!haint) { uint32_t a, b; a = host->otg->HAINT; @@ -1327,7 +1328,7 @@ static void usb_lld_serve_interrupt(USBHDriver *host) { gintsts &= otg->GINTMSK; if (!gintsts) { -#if USBH_DEBUG_ENABLE_WARNINGS +#if USBH_DEBUG_ENABLE && USBH_DEBUG_ENABLE_WARNINGS uint32_t a, b; a = otg->GINTSTS; b = otg->GINTMSK; @@ -1504,8 +1505,8 @@ static void _usbh_start(USBHDriver *usbh) { #endif { /* OTG HS clock enable and reset.*/ - rccEnableOTG_HS(TRUE); // Enable HS clock when cpu is in sleep mode - rccDisableOTG_HSULPI(TRUE); // Disable HS ULPI clock when cpu is in sleep mode + rccEnableOTG_HS(FALSE); // Disable HS clock when cpu is in sleep mode + rccDisableOTG_HSULPI(); rccResetOTG_HS(); otgp->GINTMSK = 0; diff --git a/os/hal/ports/STM32/STM32F0xx/platform.mk b/os/hal/ports/STM32/STM32F0xx/platform.mk index 0102162..5bffece 100644 --- a/os/hal/ports/STM32/STM32F0xx/platform.mk +++ b/os/hal/ports/STM32/STM32F0xx/platform.mk @@ -1,9 +1,20 @@ include ${CHIBIOS}/os/hal/ports/STM32/STM32F0xx/platform.mk -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c +ifeq ($(USE_SMART_BUILD),yes) -PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD +# Configuration files directory +ifeq ($(CONFDIR),) + CONFDIR = . +endif + +HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define")) + +else +endif + +include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC_CONTRIB) +ALLINC += $(PLATFORMINC_CONTRIB) diff --git a/os/hal/ports/STM32/STM32F1xx/platform.mk b/os/hal/ports/STM32/STM32F1xx/platform.mk index a8f21bc..9562942 100644 --- a/os/hal/ports/STM32/STM32F1xx/platform.mk +++ b/os/hal/ports/STM32/STM32F1xx/platform.mk @@ -1,15 +1,21 @@ include ${CHIBIOS}/os/hal/ports/STM32/STM32F1xx/platform.mk -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc_sdram.c - -PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD +ifeq ($(USE_SMART_BUILD),yes) + +# Configuration files directory +ifeq ($(CONFDIR),) + CONFDIR = . +endif + +HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define")) + +else +endif + +include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/COMPv1/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC_CONTRIB) +ALLINC += $(PLATFORMINC_CONTRIB) diff --git a/os/hal/ports/STM32/STM32F3xx/platform.mk b/os/hal/ports/STM32/STM32F3xx/platform.mk index 910fb1f..befe229 100644 --- a/os/hal/ports/STM32/STM32F3xx/platform.mk +++ b/os/hal/ports/STM32/STM32F3xx/platform.mk @@ -1,12 +1,22 @@ include ${CHIBIOS}/os/hal/ports/STM32/STM32F3xx/platform.mk -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/COMPv1/hal_comp_lld.c \ - -PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/COMPv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD +ifeq ($(USE_SMART_BUILD),yes) + +# Configuration files directory +ifeq ($(CONFDIR),) + CONFDIR = . +endif + +HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define")) + +else +endif + +include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/COMPv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/OPAMPv1/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC_CONTRIB) +ALLINC += $(PLATFORMINC_CONTRIB) diff --git a/os/hal/ports/STM32/STM32F4xx/platform.mk b/os/hal/ports/STM32/STM32F4xx/platform.mk index c312e72..73af8ff 100644 --- a/os/hal/ports/STM32/STM32F4xx/platform.mk +++ b/os/hal/ports/STM32/STM32F4xx/platform.mk @@ -1,21 +1,24 @@ include ${CHIBIOS}/os/hal/ports/STM32/STM32F4xx/platform.mk
-PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc_sdram.c
+ifeq ($(USE_SMART_BUILD),yes)
-PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/DMA2Dv1 \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1 \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/LTDCv1 \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1 \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD
+# Configuration files directory
+ifeq ($(CONFDIR),)
+ CONFDIR = .
+endif
+
+HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define"))
+
+else
+endif
+
+include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/DMA2Dv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/LTDCv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1/driver.mk
+
+# Shared variables
+ALLCSRC += $(PLATFORMSRC_CONTRIB)
+ALLINC += $(PLATFORMINC_CONTRIB)
diff --git a/os/hal/ports/STM32/STM32F7xx/platform.mk b/os/hal/ports/STM32/STM32F7xx/platform.mk index 2f9392f..9294c6a 100644 --- a/os/hal/ports/STM32/STM32F7xx/platform.mk +++ b/os/hal/ports/STM32/STM32F7xx/platform.mk @@ -1,9 +1,24 @@ include ${CHIBIOS}/os/hal/ports/STM32/STM32F7xx/platform.mk -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc_sdram.c +ifeq ($(USE_SMART_BUILD),yes) -PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD +# Configuration files directory +ifeq ($(CONFDIR),) + CONFDIR = . +endif + +HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define")) + +else +endif + +include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/DMA2Dv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/LTDCv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC_CONTRIB) +ALLINC += $(PLATFORMINC_CONTRIB) diff --git a/os/hal/ports/STM32/STM32L4xx/platform.mk b/os/hal/ports/STM32/STM32L4xx/platform.mk index b9bbfea..096fd59 100644 --- a/os/hal/ports/STM32/STM32L4xx/platform.mk +++ b/os/hal/ports/STM32/STM32L4xx/platform.mk @@ -1,21 +1,24 @@ include ${CHIBIOS}/os/hal/ports/STM32/STM32L4xx/platform.mk
-PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc_sdram.c
+ifeq ($(USE_SMART_BUILD),yes)
-PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/DMA2Dv1 \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1 \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/LTDCv1 \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1 \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD
+# Configuration files directory
+ifeq ($(CONFDIR),)
+ CONFDIR = .
+endif
+
+HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define"))
+
+else
+endif
+
+include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/DMA2Dv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/LTDCv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/driver.mk
+include ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1/driver.mk
+
+# Shared variables
+ALLCSRC += $(PLATFORMSRC_CONTRIB)
+ALLINC += $(PLATFORMINC_CONTRIB)
diff --git a/os/hal/src/hal_ee24xx.c b/os/hal/src/hal_ee24xx.c index 725258c..1df1b9f 100644 --- a/os/hal/src/hal_ee24xx.c +++ b/os/hal/src/hal_ee24xx.c @@ -334,6 +334,7 @@ static size_t read(void *ip, uint8_t *bp, size_t n) { } static const struct EepromFileStreamVMT vmt = { + (size_t)0, write, read, eepfs_put, diff --git a/os/hal/src/hal_ee25xx.c b/os/hal/src/hal_ee25xx.c index 8c35976..2849e66 100644 --- a/os/hal/src/hal_ee25xx.c +++ b/os/hal/src/hal_ee25xx.c @@ -383,6 +383,7 @@ static size_t read(void *ip, uint8_t *bp, size_t n) { } static const struct EepromFileStreamVMT vmt = { + (size_t)0, write, read, eepfs_put, diff --git a/os/hal/src/hal_opamp.c b/os/hal/src/hal_opamp.c new file mode 100644 index 0000000..79a5ec8 --- /dev/null +++ b/os/hal/src/hal_opamp.c @@ -0,0 +1,155 @@ +/* + ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio + Copyright (C) 2019 Fabien Poussin (fabien.poussin (at) google's mail) + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_opamp.c + * @brief OPAMP Driver code. + * + * @addtogroup OPAMP + * @{ + */ + +#include "hal_opamp.h" + +#if HAL_USE_OPAMP || defined(__DOXYGEN__) + + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief OPAMP Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void opampInit(void) { + + opamp_lld_init(); +} + +/** + * @brief Initializes the standard part of a @p OPAMPDriver structure. + * + * @param[out] opampp pointer to the @p OPAMPDriver object + * + * @init + */ +void opampObjectInit(OPAMPDriver *opampp) { + + opampp->state = OPAMP_STOP; + opampp->config = NULL; +} + +/** + * @brief Configures and activates the OPAMP peripheral. + * + * @param[in] opampp pointer to the @p OPAMPDriver object + * @param[in] config pointer to the @p OPAMPConfig object + * + * @api + */ +void opampStart(OPAMPDriver *opampp, const OPAMPConfig *config) { + + osalDbgCheck((opampp != NULL) && (config != NULL)); + + osalSysLock(); + osalDbgAssert((opampp->state == OPAMP_STOP) || (opampp->state == OPAMP_ACTIVE), + "invalid state"); + opampp->config = config; + opamp_lld_start(opampp); + opampp->state = OPAMP_ACTIVE; + osalSysUnlock(); +} + +/** + * @brief Deactivates the OPAMP peripheral. + * + * @param[in] opampp pointer to the @p OPAMPDriver object + * + * @api + */ +void opampStop(OPAMPDriver *opampp) { + + osalDbgCheck(opampp != NULL); + + osalSysLock(); + osalDbgAssert((opampp->state == OPAMP_STOP) || (opampp->state == OPAMP_ACTIVE), + "invalid state"); + opamp_lld_stop(opampp); + opampp->state = OPAMP_STOP; + osalSysUnlock(); +} + +/** + * @brief Activates the opamp. + * + * @param[in] opampp pointer to the @p OPAMPDriver object + * + * @api + */ +void opampEnable(OPAMPDriver *opampp) { + + osalDbgCheck(opampp != NULL); + + osalSysLock(); + osalDbgAssert(opampp->state == OPAMP_ACTIVE, "invalid state"); + opamp_lld_enable(opampp); + opampp->state = OPAMP_ACTIVE; + osalSysUnlock(); +} + +/** + * @brief Deactivates the opamp. + * + * @param[in] opampp pointer to the @p OPAMPDriver object + * + * @api + */ +void opampDisable(OPAMPDriver *opampp) { + + osalDbgCheck(opampp != NULL); + + osalSysLock(); + osalDbgAssert((opampp->state == OPAMP_ACTIVE), + "invalid state"); + opamp_lld_disable(opampp); + opampp->state = OPAMP_ACTIVE; + osalSysUnlock(); +} + +#endif /* HAL_USE_OPAMP */ + +/** @} */ diff --git a/os/hal/src/hal_usb_hid.c b/os/hal/src/hal_usb_hid.c index d9d671b..305fe8d 100644 --- a/os/hal/src/hal_usb_hid.c +++ b/os/hal/src/hal_usb_hid.c @@ -128,15 +128,23 @@ static size_t readt(void *ip, uint8_t *bp, size_t n, systime_t timeout) { return ibqReadTimeout(&((USBHIDDriver *)ip)->ibqueue, bp, n, timeout);
}
+static msg_t ctl(void *ip, unsigned int operation, void *arg) {
+ (void)ip;
+ (void)operation;
+ (void)arg;
+ return MSG_OK;
+}
+
static void flush(void *ip) {
obqFlush(&((USBHIDDriver *)ip)->obqueue);
}
static const struct USBHIDDriverVMT vmt = {
+ (size_t)0,
write, read, put, get,
putt, gett, writet, readt,
- flush
+ ctl, flush
};
/**
diff --git a/os/hal/src/usbh/hal_usbh_aoa.c b/os/hal/src/usbh/hal_usbh_aoa.c index bda93a2..4e1d65d 100644 --- a/os/hal/src/usbh/hal_usbh_aoa.c +++ b/os/hal/src/usbh/hal_usbh_aoa.c @@ -509,8 +509,15 @@ static size_t _read(USBHAOAChannel *aoacp, uint8_t *bp, size_t n) { return _read_timeout(aoacp, bp, n, TIME_INFINITE); } +static msg_t _ctl(USBHAOAChannel *ftdipp, unsigned int operation, void *arg) { + (void)ftdipp; + (void)operation; + (void)arg; + return MSG_OK; +} + static const struct AOADriverVMT async_channel_vmt = { - (size_t) 0, + (size_t)0, (size_t (*)(void *, const uint8_t *, size_t))_write, (size_t (*)(void *, uint8_t *, size_t))_read, (msg_t (*)(void *, uint8_t))_put, @@ -519,7 +526,7 @@ static const struct AOADriverVMT async_channel_vmt = { (msg_t (*)(void *, systime_t))_get_timeout, (size_t (*)(void *, const uint8_t *, size_t, systime_t))_write_timeout, (size_t (*)(void *, uint8_t *, size_t, systime_t))_read_timeout, - (void*) 0 // FIXME: Implement CTL + (msg_t (*)(void *, unsigned int, void *))_ctl }; static void _stop_channelS(USBHAOAChannel *aoacp) { diff --git a/os/hal/src/usbh/hal_usbh_ftdi.c b/os/hal/src/usbh/hal_usbh_ftdi.c index 070dbcf..b262256 100644 --- a/os/hal/src/usbh/hal_usbh_ftdi.c +++ b/os/hal/src/usbh/hal_usbh_ftdi.c @@ -601,6 +601,13 @@ static size_t _read(USBHFTDIPortDriver *ftdipp, uint8_t *bp, size_t n) { return _read_timeout(ftdipp, bp, n, TIME_INFINITE); } +static msg_t _ctl(USBHFTDIPortDriver *ftdipp, unsigned int operation, void *arg) { + (void)ftdipp; + (void)operation; + (void)arg; + return MSG_OK; +} + static void _vt(void *p) { USBHFTDIPortDriver *const ftdipp = (USBHFTDIPortDriver *)p; osalSysLockFromISR(); @@ -616,7 +623,7 @@ static void _vt(void *p) { } static const struct FTDIPortDriverVMT async_channel_vmt = { - (size_t) 0, + (size_t)0, (size_t (*)(void *, const uint8_t *, size_t))_write, (size_t (*)(void *, uint8_t *, size_t))_read, (msg_t (*)(void *, uint8_t))_put, @@ -624,8 +631,8 @@ static const struct FTDIPortDriverVMT async_channel_vmt = { (msg_t (*)(void *, uint8_t, systime_t))_put_timeout, (msg_t (*)(void *, systime_t))_get_timeout, (size_t (*)(void *, const uint8_t *, size_t, systime_t))_write_timeout, - (size_t (*)(void *, uint8_t *, size_t, systime_t))_read_timeout, - (void*) 0 // FIXME: Implement CTL + (size_t (*)(void *, uint8_t *, size_t, systime_t))_read_timeout, + (msg_t (*)(void *, unsigned int, void *))_ctl }; diff --git a/os/hal/src/usbh/hal_usbh_msd.c b/os/hal/src/usbh/hal_usbh_msd.c index fe97ff0..3d57934 100644 --- a/os/hal/src/usbh/hal_usbh_msd.c +++ b/os/hal/src/usbh/hal_usbh_msd.c @@ -516,6 +516,8 @@ static msd_result_t _scsi_perform_transaction(USBHMassStorageLUNDriver *lunp, if (scsi_requestsense(lunp, &sense) == MSD_RESULT_OK) { uwarnf("\tMSD: REQUEST SENSE: Sense key=%x, ASC=%02x, ASCQ=%02x", sense.byte[2] & 0xf, sense.byte[12], sense.byte[13]); + + return MSD_RESULT_OK; } } return MSD_RESULT_FAILED; diff --git a/os/various/devices_lib/rf/nrf52_radio.c b/os/various/devices_lib/rf/nrf52_radio.c new file mode 100644 index 0000000..e55870f --- /dev/null +++ b/os/various/devices_lib/rf/nrf52_radio.c @@ -0,0 +1,1111 @@ +/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + * Enhanced ShockBurst proprietary protocol to ChibiOS port + * + * ported on: 25/10/2018, by andru + * + */ + +#include <stdint.h> +#include <string.h> + +#include "ch.h" +#include "hal.h" + +#include "nrf52_radio.h" + + +#define BIT_MASK_UINT_8(x) (0xFF >> (8 - (x))) +#define NRF52_PIPE_COUNT 9 + +#define RADIO_SHORTS_COMMON ( RADIO_SHORTS_READY_START_Msk | RADIO_SHORTS_END_DISABLE_Msk | \ + RADIO_SHORTS_ADDRESS_RSSISTART_Msk | RADIO_SHORTS_DISABLED_RSSISTOP_Msk ) + +// Constant parameters +#define RX_WAIT_FOR_ACK_TIMEOUT_US_2MBPS (48) /**< 2MBit RX wait for ack timeout value. Smallest reliable value - 43 */ +#define RX_WAIT_FOR_ACK_TIMEOUT_US_1MBPS (64) /**< 1MBit RX wait for ack timeout value. Smallest reliable value - 59 */ + +#define NRF52_ADDR_UPDATE_MASK_BASE0 (1 << 0) /*< Mask value to signal updating BASE0 radio address. */ +#define NRF52_ADDR_UPDATE_MASK_BASE1 (1 << 1) /*< Mask value to signal updating BASE1 radio address. */ +#define NRF52_ADDR_UPDATE_MASK_PREFIX (1 << 2) /*< Mask value to signal updating radio prefixes */ + +#define NRF52_PID_RESET_VALUE 0xFF /**< Invalid PID value which is guaranteed to not collide with any valid PID value. */ +#define NRF52_PID_MAX 3 /**< Maximum value for PID. */ +#define NRF52_CRC_RESET_VALUE 0xFFFF /**< CRC reset value*/ + +#ifndef NRF52_RADIO_USE_TIMER0 +#define NRF52_RADIO_USE_TIMER0 FALSE +#endif + +#ifndef NRF52_RADIO_USE_TIMER1 +#define NRF52_RADIO_USE_TIMER1 FALSE +#endif + +#ifndef NRF52_RADIO_USE_TIMER2 +#define NRF52_RADIO_USE_TIMER2 FALSE +#endif + +#ifndef NRF52_RADIO_USE_TIMER3 +#define NRF52_RADIO_USE_TIMER3 FALSE +#endif + +#ifndef NRF52_RADIO_USE_TIMER4 +#define NRF52_RADIO_USE_TIMER4 FALSE +#endif + +#ifndef NRF52_RADIO_IRQ_PRIORITY +#define NRF52_RADIO_IRQ_PRIORITY 3 /**< RADIO interrupt priority. */ +#endif + +#ifndef NRF52_RADIO_PPI_TIMER_START +#error "PPI channel NRF52_RADIO_PPI_TIMER_START need to be defined" +#endif + +#ifndef NRF52_RADIO_PPI_TIMER_STOP +#error "PPI channel NRF52_RADIO_PPI_TIMER_STOP need to be defined" +#endif + +#ifndef NRF52_RADIO_PPI_RX_TIMEOUT +#error "PPI channel NRF52_RADIO_PPI_RX_TIMEOUT need to be defined" +#endif + +#ifndef NRF52_RADIO_PPI_TX_START +#error "PPI channel NRF52_RADIO_PPI_TX_START need to be defined" +#endif + +#if (NRF52_RADIO_USE_TIMER0 == FALSE) && (NRF52_RADIO_USE_TIMER1 == FALSE) && \ + (NRF52_RADIO_USE_TIMER2 == FALSE) && (NRF52_RADIO_USE_TIMER3 == FALSE) && \ + (NRF52_RADIO_USE_TIMER4 == FALSE) +#error "At least one hardware TIMER must be defined" +#endif + +#ifndef NRF52_RADIO_INTTHD_PRIORITY +#error "Interrupt handle thread priority need to be defined" +#endif + +#ifndef NRF52_RADIO_EVTTHD_PRIORITY +#error "Event thread priority need to be defined" +#endif + +#define VERIFY_PAYLOAD_LENGTH(p) \ +do \ +{ \ + if(p->length == 0 || \ + p->length > NRF52_MAX_PAYLOAD_LENGTH || \ + (RFD1.config.protocol == NRF52_PROTOCOL_ESB && \ + p->length > RFD1.config.payload_length)) \ + { \ + return NRF52_ERROR_INVALID_LENGTH; \ + } \ +}while(0) + +//Structure holding pipe info PID and CRC and ack payload. +typedef struct +{ + uint16_t m_crc; + uint8_t m_pid; + uint8_t m_ack_payload; +} pipe_info_t; + +// First in first out queue of payloads to be transmitted. +typedef struct +{ + nrf52_payload_t * p_payload[NRF52_TX_FIFO_SIZE]; /**< Pointer to the actual queue. */ + uint32_t entry_point; /**< Current start of queue. */ + uint32_t exit_point; /**< Current end of queue. */ + uint32_t count; /**< Current number of elements in the queue. */ +} nrf52_payload_tx_fifo_t; + +// First in first out queue of received payloads. +typedef struct +{ + nrf52_payload_t * p_payload[NRF52_RX_FIFO_SIZE]; /**< Pointer to the actual queue. */ + uint32_t entry_point; /**< Current start of queue. */ + uint32_t exit_point; /**< Current end of queue. */ + uint32_t count; /**< Current number of elements in the queue. */ +} nrf52_payload_rx_fifo_t; + +// These function pointers are changed dynamically, depending on protocol configuration and state. +//static void (*on_radio_end)(RFDriver *rfp) = NULL; +static void (*set_rf_payload_format)(RFDriver *rfp, uint32_t payload_length) = NULL; + +// The following functions are assigned to the function pointers above. +static void on_radio_disabled_tx_noack(RFDriver *rfp); +static void on_radio_disabled_tx(RFDriver *rfp); +static void on_radio_disabled_tx_wait_for_ack(RFDriver *rfp); +static void on_radio_disabled_rx(RFDriver *rfp); +static void on_radio_disabled_rx_ack(RFDriver *rfp); + +static volatile uint16_t wait_for_ack_timeout_us; +static nrf52_payload_t * p_current_payload; + +// TX FIFO +static nrf52_payload_t tx_fifo_payload[NRF52_TX_FIFO_SIZE]; +static nrf52_payload_tx_fifo_t tx_fifo; + +// RX FIFO +static nrf52_payload_t rx_fifo_payload[NRF52_RX_FIFO_SIZE]; +static nrf52_payload_rx_fifo_t rx_fifo; + +// Payload buffers +static uint8_t tx_payload_buffer[NRF52_MAX_PAYLOAD_LENGTH + 2]; +static uint8_t rx_payload_buffer[NRF52_MAX_PAYLOAD_LENGTH + 2]; + +static uint8_t pids[NRF52_PIPE_COUNT]; +static pipe_info_t rx_pipe_info[NRF52_PIPE_COUNT]; + + // disable and events semaphores. +static binary_semaphore_t disable_sem; +static binary_semaphore_t events_sem; + +RFDriver RFD1; + +// Function to do bytewise bit-swap on a unsigned 32 bit value +static uint32_t bytewise_bit_swap(uint8_t const * p_inp) { + uint32_t inp = (*(uint32_t*)p_inp); + + return __REV((uint32_t)__RBIT(inp)); //lint -esym(628, __rev) -esym(526, __rev) -esym(628, __rbit) -esym(526, __rbit) */ +} + +// Internal function to convert base addresses from nRF24L type addressing to nRF52 type addressing +static uint32_t addr_conv(uint8_t const* p_addr) { + return __REV(bytewise_bit_swap(p_addr)); //lint -esym(628, __rev) -esym(526, __rev) */ +} + +static thread_t *rfEvtThread_p; +static THD_WORKING_AREA(waRFEvtThread, 64); +static THD_FUNCTION(rfEvtThread, arg) { + (void)arg; + + chRegSetThreadName("rfevent"); + + while (!chThdShouldTerminateX()) { + chBSemWait(&events_sem); + + nrf52_int_flags_t interrupts = RFD1.flags; + RFD1.flags = 0; + + if (interrupts & NRF52_INT_TX_SUCCESS_MSK) { + chEvtBroadcastFlags(&RFD1.eventsrc, (eventflags_t) NRF52_EVENT_TX_SUCCESS); + } + if (interrupts & NRF52_INT_TX_FAILED_MSK) { + chEvtBroadcastFlags(&RFD1.eventsrc, (eventflags_t) NRF52_EVENT_TX_FAILED); + } + if (interrupts & NRF52_INT_RX_DR_MSK) { + chEvtBroadcastFlags(&RFD1.eventsrc, (eventflags_t) NRF52_EVENT_RX_RECEIVED); + } + } + chThdExit((msg_t) 0); +} + +static thread_t *rfIntThread_p; +static THD_WORKING_AREA(waRFIntThread, 64); +static THD_FUNCTION(rfIntThread, arg) { + (void)arg; + + chRegSetThreadName("rfint"); + + while (!chThdShouldTerminateX()) { + chBSemWait(&disable_sem); + switch (RFD1.state) { + case NRF52_STATE_PTX_TX: + on_radio_disabled_tx_noack(&RFD1); + break; + case NRF52_STATE_PTX_TX_ACK: + on_radio_disabled_tx(&RFD1); + break; + case NRF52_STATE_PTX_RX_ACK: + on_radio_disabled_tx_wait_for_ack(&RFD1); + break; + case NRF52_STATE_PRX: + on_radio_disabled_rx(&RFD1); + break; + case NRF52_STATE_PRX_SEND_ACK: + on_radio_disabled_rx_ack(&RFD1); + break; + default: + break; + } + } + chThdExit((msg_t) 0); +} + +static void serve_radio_interrupt(RFDriver *rfp) { + (void) rfp; + if ((NRF_RADIO->INTENSET & RADIO_INTENSET_READY_Msk) && NRF_RADIO->EVENTS_READY) { + NRF_RADIO->EVENTS_READY = 0; + (void) NRF_RADIO->EVENTS_READY; + } + if ((NRF_RADIO->INTENSET & RADIO_INTENSET_DISABLED_Msk) && NRF_RADIO->EVENTS_DISABLED) { + NRF_RADIO->EVENTS_DISABLED = 0; + (void) NRF_RADIO->EVENTS_DISABLED; + chSysLockFromISR(); + chBSemSignalI(&disable_sem); + chSysUnlockFromISR(); + } +} + +/** + * @brief RADIO events interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector44) { + + OSAL_IRQ_PROLOGUE(); + + serve_radio_interrupt(&RFD1); + + OSAL_IRQ_EPILOGUE(); +} + +static void set_rf_payload_format_esb_dpl(RFDriver *rfp, uint32_t payload_length) { + (void)payload_length; +#if (NRF52_MAX_PAYLOAD_LENGTH <= 32) + // Using 6 bits for length + NRF_RADIO->PCNF0 = (0 << RADIO_PCNF0_S0LEN_Pos) | + (6 << RADIO_PCNF0_LFLEN_Pos) | + (3 << RADIO_PCNF0_S1LEN_Pos) ; +#else + // Using 8 bits for length + NRF_RADIO->PCNF0 = (0 << RADIO_PCNF0_S0LEN_Pos) | + (8 << RADIO_PCNF0_LFLEN_Pos) | + (3 << RADIO_PCNF0_S1LEN_Pos) ; +#endif + NRF_RADIO->PCNF1 = (RADIO_PCNF1_WHITEEN_Disabled << RADIO_PCNF1_WHITEEN_Pos) | + (RADIO_PCNF1_ENDIAN_Big << RADIO_PCNF1_ENDIAN_Pos) | + ((rfp->config.address.addr_length - 1) << RADIO_PCNF1_BALEN_Pos) | + (0 << RADIO_PCNF1_STATLEN_Pos) | + (NRF52_MAX_PAYLOAD_LENGTH << RADIO_PCNF1_MAXLEN_Pos); +} + +static void set_rf_payload_format_esb(RFDriver *rfp, uint32_t payload_length) { + NRF_RADIO->PCNF0 = (1 << RADIO_PCNF0_S0LEN_Pos) | + (0 << RADIO_PCNF0_LFLEN_Pos) | + (1 << RADIO_PCNF0_S1LEN_Pos); + + NRF_RADIO->PCNF1 = (RADIO_PCNF1_WHITEEN_Disabled << RADIO_PCNF1_WHITEEN_Pos) | + (RADIO_PCNF1_ENDIAN_Big << RADIO_PCNF1_ENDIAN_Pos) | + ((rfp->config.address.addr_length - 1) << RADIO_PCNF1_BALEN_Pos) | + (payload_length << RADIO_PCNF1_STATLEN_Pos) | + (payload_length << RADIO_PCNF1_MAXLEN_Pos); +} + +/* Set BASE0 and BASE1 addresses & prefixes registers + * NRF52 { prefixes[0], base0_addr[0], base0_addr[1], base0_addr[2], base0_addr[3] } == + * NRF24 { addr[0], addr[1], addr[2], addr[3], addr[4] } + */ +static void set_addresses(RFDriver *rfp, uint8_t update_mask) { + if (update_mask & NRF52_ADDR_UPDATE_MASK_BASE0) { + NRF_RADIO->BASE0 = addr_conv(rfp->config.address.base_addr_p0); + NRF_RADIO->DAB[0] = addr_conv(rfp->config.address.base_addr_p0); + } + + if (update_mask & NRF52_ADDR_UPDATE_MASK_BASE1) { + NRF_RADIO->BASE1 = addr_conv(rfp->config.address.base_addr_p1); + NRF_RADIO->DAB[1] = addr_conv(rfp->config.address.base_addr_p1); + } + + if (update_mask & NRF52_ADDR_UPDATE_MASK_PREFIX) { + NRF_RADIO->PREFIX0 = bytewise_bit_swap(&rfp->config.address.pipe_prefixes[0]); + NRF_RADIO->DAP[0] = bytewise_bit_swap(&rfp->config.address.pipe_prefixes[0]); + NRF_RADIO->PREFIX1 = bytewise_bit_swap(&rfp->config.address.pipe_prefixes[4]); + NRF_RADIO->DAP[1] = bytewise_bit_swap(&rfp->config.address.pipe_prefixes[4]); + } +} + +static void set_tx_power(RFDriver *rfp) { + NRF_RADIO->TXPOWER = rfp->config.tx_power << RADIO_TXPOWER_TXPOWER_Pos; +} + +static void set_bitrate(RFDriver *rfp) { + NRF_RADIO->MODE = rfp->config.bitrate << RADIO_MODE_MODE_Pos; + + switch (rfp->config.bitrate) { + case NRF52_BITRATE_2MBPS: + wait_for_ack_timeout_us = RX_WAIT_FOR_ACK_TIMEOUT_US_2MBPS; + break; + case NRF52_BITRATE_1MBPS: + wait_for_ack_timeout_us = RX_WAIT_FOR_ACK_TIMEOUT_US_1MBPS; + break; + } +} + +static void set_protocol(RFDriver *rfp) { + switch (rfp->config.protocol) { + case NRF52_PROTOCOL_ESB_DPL: + set_rf_payload_format = set_rf_payload_format_esb_dpl; + break; + case NRF52_PROTOCOL_ESB: + set_rf_payload_format = set_rf_payload_format_esb; + break; + } +} + +static void set_crc(RFDriver *rfp) { + NRF_RADIO->CRCCNF = rfp->config.crc << RADIO_CRCCNF_LEN_Pos; + + if (rfp->config.crc == RADIO_CRCCNF_LEN_Two) + { + NRF_RADIO->CRCINIT = 0xFFFFUL; // Initial value + NRF_RADIO->CRCPOLY = 0x11021UL; // CRC poly: x^16+x^12^x^5+1 + } + else if (rfp->config.crc == RADIO_CRCCNF_LEN_One) + { + NRF_RADIO->CRCINIT = 0xFFUL; // Initial value + NRF_RADIO->CRCPOLY = 0x107UL; // CRC poly: x^8+x^2^x^1+1 + } +} + +static void ppi_init(RFDriver *rfp) { + NRF_PPI->CH[NRF52_RADIO_PPI_TIMER_START].EEP = (uint32_t)&NRF_RADIO->EVENTS_READY; + NRF_PPI->CH[NRF52_RADIO_PPI_TIMER_START].TEP = (uint32_t)&rfp->timer->TASKS_START; + + NRF_PPI->CH[NRF52_RADIO_PPI_TIMER_STOP].EEP = (uint32_t)&NRF_RADIO->EVENTS_ADDRESS; + NRF_PPI->CH[NRF52_RADIO_PPI_TIMER_STOP].TEP = (uint32_t)&rfp->timer->TASKS_STOP; + + NRF_PPI->CH[NRF52_RADIO_PPI_RX_TIMEOUT].EEP = (uint32_t)&rfp->timer->EVENTS_COMPARE[0]; + NRF_PPI->CH[NRF52_RADIO_PPI_RX_TIMEOUT].TEP = (uint32_t)&NRF_RADIO->TASKS_DISABLE; + + NRF_PPI->CH[NRF52_RADIO_PPI_TX_START].EEP = (uint32_t)&rfp->timer->EVENTS_COMPARE[1]; + NRF_PPI->CH[NRF52_RADIO_PPI_TX_START].TEP = (uint32_t)&NRF_RADIO->TASKS_TXEN; +} + +static void set_parameters(RFDriver *rfp) { + set_tx_power(rfp); + set_bitrate(rfp); + set_protocol(rfp); + set_crc(rfp); + set_rf_payload_format(rfp, rfp->config.payload_length); +} + +static void reset_fifo(void) { + tx_fifo.entry_point = 0; + tx_fifo.exit_point = 0; + tx_fifo.count = 0; + + rx_fifo.entry_point = 0; + rx_fifo.exit_point = 0; + rx_fifo.count = 0; +} + +static void init_fifo(void) { + uint8_t i; + reset_fifo(); + + for (i = 0; i < NRF52_TX_FIFO_SIZE; i++) { + tx_fifo.p_payload[i] = &tx_fifo_payload[i]; + } + + for (i = 0; i < NRF52_RX_FIFO_SIZE; i++) { + rx_fifo.p_payload[i] = &rx_fifo_payload[i]; + } +} + +static void tx_fifo_remove_last(void) { + if (tx_fifo.count > 0) { + nvicDisableVector(RADIO_IRQn); + + tx_fifo.count--; + if (++tx_fifo.exit_point >= NRF52_TX_FIFO_SIZE) { + tx_fifo.exit_point = 0; + } + + nvicEnableVector(RADIO_IRQn, NRF52_RADIO_IRQ_PRIORITY); + } +} + +/** @brief Function to push the content of the rx_buffer to the RX FIFO. + * + * The module will point the register NRF_RADIO->PACKETPTR to a buffer for receiving packets. + * After receiving a packet the module will call this function to copy the received data to + * the RX FIFO. + * + * @param pipe Pipe number to set for the packet. + * @param pid Packet ID. + * + * @retval true Operation successful. + * @retval false Operation failed. + */ +static bool rx_fifo_push_rfbuf(RFDriver *rfp, uint8_t pipe, uint8_t pid) { + if (rx_fifo.count < NRF52_RX_FIFO_SIZE) { + if (rfp->config.protocol == NRF52_PROTOCOL_ESB_DPL) { + if (rx_payload_buffer[0] > NRF52_MAX_PAYLOAD_LENGTH) { + return false; + } + + rx_fifo.p_payload[rx_fifo.entry_point]->length = rx_payload_buffer[0]; + } + else if (rfp->state == NRF52_STATE_PTX_RX_ACK) { + // Received packet is an acknowledgment + rx_fifo.p_payload[rx_fifo.entry_point]->length = 0; + } + else { + rx_fifo.p_payload[rx_fifo.entry_point]->length = rfp->config.payload_length; + } + + memcpy(rx_fifo.p_payload[rx_fifo.entry_point]->data, &rx_payload_buffer[2], + rx_fifo.p_payload[rx_fifo.entry_point]->length); + + rx_fifo.p_payload[rx_fifo.entry_point]->pipe = pipe; + rx_fifo.p_payload[rx_fifo.entry_point]->rssi = NRF_RADIO->RSSISAMPLE; + rx_fifo.p_payload[rx_fifo.entry_point]->pid = pid; + if (++rx_fifo.entry_point >= NRF52_RX_FIFO_SIZE) { + rx_fifo.entry_point = 0; + } + rx_fifo.count++; + + return true; + } + + return false; +} + +static void timer_init(RFDriver *rfp) { + // Configure the system timer with a 1 MHz base frequency + rfp->timer->PRESCALER = 4; + rfp->timer->BITMODE = TIMER_BITMODE_BITMODE_16Bit; + rfp->timer->SHORTS = TIMER_SHORTS_COMPARE1_CLEAR_Msk | TIMER_SHORTS_COMPARE1_STOP_Msk; +} + +static void start_tx_transaction(RFDriver *rfp) { + bool ack; + + rfp->tx_attempt = 1; + rfp->tx_remaining = rfp->config.retransmit.count; + + // Prepare the payload + p_current_payload = tx_fifo.p_payload[tx_fifo.exit_point]; + + // Handling ack if noack is set to false or if selctive auto ack is turned turned off + ack = !p_current_payload->noack || !rfp->config.selective_auto_ack; + + switch (rfp->config.protocol) { + case NRF52_PROTOCOL_ESB: + set_rf_payload_format(rfp, p_current_payload->length); + tx_payload_buffer[0] = p_current_payload->pid; + tx_payload_buffer[1] = 0; + memcpy(&tx_payload_buffer[2], p_current_payload->data, p_current_payload->length); + + NRF_RADIO->SHORTS = RADIO_SHORTS_COMMON | RADIO_SHORTS_DISABLED_RXEN_Msk; + NRF_RADIO->INTENSET = RADIO_INTENSET_DISABLED_Msk | RADIO_INTENSET_READY_Msk; + + // Configure the retransmit counter + rfp->tx_remaining = rfp->config.retransmit.count; + rfp->state = NRF52_STATE_PTX_TX_ACK; + break; + + case NRF52_PROTOCOL_ESB_DPL: + tx_payload_buffer[0] = p_current_payload->length; + tx_payload_buffer[1] = p_current_payload->pid << 1; + tx_payload_buffer[1] |= ack ? 0x00 : 0x01; + memcpy(&tx_payload_buffer[2], p_current_payload->data, p_current_payload->length); + + if (ack) { + NRF_RADIO->SHORTS = RADIO_SHORTS_COMMON | RADIO_SHORTS_DISABLED_RXEN_Msk; + NRF_RADIO->INTENSET = RADIO_INTENSET_DISABLED_Msk | RADIO_INTENSET_READY_Msk; + + // Configure the retransmit counter + rfp->tx_remaining = rfp->config.retransmit.count; + rfp->state = NRF52_STATE_PTX_TX_ACK; + } + else { + NRF_RADIO->SHORTS = RADIO_SHORTS_COMMON; + NRF_RADIO->INTENSET = RADIO_INTENSET_DISABLED_Msk; + rfp->state = NRF52_STATE_PTX_TX; + } + break; + } + + NRF_RADIO->TXADDRESS = p_current_payload->pipe; + NRF_RADIO->RXADDRESSES = 1 << p_current_payload->pipe; + + NRF_RADIO->FREQUENCY = rfp->config.address.rf_channel; + NRF_RADIO->PACKETPTR = (uint32_t)tx_payload_buffer; + + NRF_RADIO->EVENTS_READY = 0; + NRF_RADIO->EVENTS_DISABLED = 0; + (void)NRF_RADIO->EVENTS_READY; + (void)NRF_RADIO->EVENTS_DISABLED; + + nvicClearPending(RADIO_IRQn); + nvicEnableVector(RADIO_IRQn, NRF52_RADIO_IRQ_PRIORITY); + + NRF_RADIO->TASKS_TXEN = 1; +} + +static void on_radio_disabled_tx_noack(RFDriver *rfp) { + rfp->flags |= NRF52_INT_TX_SUCCESS_MSK; + tx_fifo_remove_last(); + + chBSemSignal(&events_sem); + + if (tx_fifo.count == 0) { + rfp->state = NRF52_STATE_IDLE; + } + else { + start_tx_transaction(rfp); + } +} + +static void on_radio_disabled_tx(RFDriver *rfp) { + // Remove the DISABLED -> RXEN shortcut, to make sure the radio stays + // disabled after the RX window + NRF_RADIO->SHORTS = RADIO_SHORTS_COMMON; + + // Make sure the timer is started the next time the radio is ready, + // and that it will disable the radio automatically if no packet is + // received by the time defined in m_wait_for_ack_timeout_us + rfp->timer->CC[0] = wait_for_ack_timeout_us + 130; + rfp->timer->CC[1] = rfp->config.retransmit.delay - 130; + rfp->timer->TASKS_CLEAR = 1; + rfp->timer->EVENTS_COMPARE[0] = 0; + rfp->timer->EVENTS_COMPARE[1] = 0; + (void)rfp->timer->EVENTS_COMPARE[0]; + (void)rfp->timer->EVENTS_COMPARE[1]; + + NRF_PPI->CHENSET = (1 << NRF52_RADIO_PPI_TIMER_START) | + (1 << NRF52_RADIO_PPI_RX_TIMEOUT) | + (1 << NRF52_RADIO_PPI_TIMER_STOP); + NRF_PPI->CHENCLR = (1 << NRF52_RADIO_PPI_TX_START); + + NRF_RADIO->EVENTS_END = 0; + (void)NRF_RADIO->EVENTS_END; + + if (rfp->config.protocol == NRF52_PROTOCOL_ESB) { + set_rf_payload_format(rfp, 0); + } + + NRF_RADIO->PACKETPTR = (uint32_t)rx_payload_buffer; + rfp->state = NRF52_STATE_PTX_RX_ACK; +} + +static void on_radio_disabled_tx_wait_for_ack(RFDriver *rfp) { + // This marks the completion of a TX_RX sequence (TX with ACK) + + // Make sure the timer will not deactivate the radio if a packet is received + NRF_PPI->CHENCLR = (1 << NRF52_RADIO_PPI_TIMER_START) | + (1 << NRF52_RADIO_PPI_RX_TIMEOUT) | + (1 << NRF52_RADIO_PPI_TIMER_STOP); + + // If the radio has received a packet and the CRC status is OK + if (NRF_RADIO->EVENTS_END && NRF_RADIO->CRCSTATUS != 0) { + rfp->timer->TASKS_STOP = 1; + NRF_PPI->CHENCLR = (1 << NRF52_RADIO_PPI_TX_START); + rfp->flags |= NRF52_INT_TX_SUCCESS_MSK; + rfp->tx_attempt++;// = rfp->config.retransmit.count - rfp->tx_remaining + 1; + + tx_fifo_remove_last(); + + if (rfp->config.protocol != NRF52_PROTOCOL_ESB && rx_payload_buffer[0] > 0) { + if (rx_fifo_push_rfbuf(rfp, (uint8_t)NRF_RADIO->TXADDRESS, 0)) { + rfp->flags |= NRF52_INT_RX_DR_MSK; + } + } + + chBSemSignal(&events_sem); + + if ((tx_fifo.count == 0) || (rfp->config.tx_mode == NRF52_TXMODE_MANUAL)) { + rfp->state = NRF52_STATE_IDLE; + } + else { + start_tx_transaction(rfp); + } + } + else { + if (rfp->tx_remaining-- == 0) { + rfp->timer->TASKS_STOP = 1; + NRF_PPI->CHENCLR = (1 << NRF52_RADIO_PPI_TX_START); + // All retransmits are expended, and the TX operation is suspended + rfp->tx_attempt = rfp->config.retransmit.count + 1; + rfp->flags |= NRF52_INT_TX_FAILED_MSK; + + chBSemSignal(&events_sem); + + rfp->state = NRF52_STATE_IDLE; + } + else { + // There are still have more retransmits left, TX mode should be + // entered again as soon as the system timer reaches CC[1]. + NRF_RADIO->SHORTS = RADIO_SHORTS_COMMON | RADIO_SHORTS_DISABLED_RXEN_Msk; + set_rf_payload_format(rfp, p_current_payload->length); + NRF_RADIO->PACKETPTR = (uint32_t)tx_payload_buffer; + rfp->state = NRF52_STATE_PTX_TX_ACK; + rfp->timer->TASKS_START = 1; + NRF_PPI->CHENSET = (1 << NRF52_RADIO_PPI_TX_START); + if (rfp->timer->EVENTS_COMPARE[1]) + NRF_RADIO->TASKS_TXEN = 1; + } + } +} + +static void clear_events_restart_rx(RFDriver *rfp) { + NRF_RADIO->SHORTS = RADIO_SHORTS_COMMON; + set_rf_payload_format(rfp, rfp->config.payload_length); + NRF_RADIO->PACKETPTR = (uint32_t)rx_payload_buffer; + + NRF_RADIO->INTENCLR = RADIO_INTENCLR_DISABLED_Msk; + NRF_RADIO->EVENTS_DISABLED = 0; + (void) NRF_RADIO->EVENTS_DISABLED; + + NRF_RADIO->TASKS_DISABLE = 1; + while (NRF_RADIO->EVENTS_DISABLED == 0); + + NRF_RADIO->EVENTS_DISABLED = 0; + (void) NRF_RADIO->EVENTS_DISABLED; + NRF_RADIO->INTENSET = RADIO_INTENSET_DISABLED_Msk; + + NRF_RADIO->SHORTS = RADIO_SHORTS_COMMON | RADIO_SHORTS_DISABLED_TXEN_Msk; + NRF_RADIO->TASKS_RXEN = 1; +} + +static void on_radio_disabled_rx(RFDriver *rfp) { + bool ack = false; + bool retransmit_payload = false; + bool send_rx_event = true; + pipe_info_t * p_pipe_info; + + if (NRF_RADIO->CRCSTATUS == 0) { + clear_events_restart_rx(rfp); + return; + } + + if(rx_fifo.count >= NRF52_RX_FIFO_SIZE) { + clear_events_restart_rx(rfp); + return; + } + + p_pipe_info = &rx_pipe_info[NRF_RADIO->RXMATCH]; + if (NRF_RADIO->RXCRC == p_pipe_info->m_crc && + (rx_payload_buffer[1] >> 1) == p_pipe_info->m_pid ) { + retransmit_payload = true; + send_rx_event = false; + } + + p_pipe_info->m_pid = rx_payload_buffer[1] >> 1; + p_pipe_info->m_crc = NRF_RADIO->RXCRC; + + if(rfp->config.selective_auto_ack == false || ((rx_payload_buffer[1] & 0x01) == 0)) + ack = true; + + if(ack) { + NRF_RADIO->SHORTS = RADIO_SHORTS_COMMON | RADIO_SHORTS_DISABLED_RXEN_Msk; + + switch(rfp->config.protocol) { + case NRF52_PROTOCOL_ESB_DPL: + { + if (tx_fifo.count > 0 && + (tx_fifo.p_payload[tx_fifo.exit_point]->pipe == NRF_RADIO->RXMATCH)) + { + // Pipe stays in ACK with payload until TX fifo is empty + // Do not report TX success on first ack payload or retransmit + if (p_pipe_info->m_ack_payload != 0 && !retransmit_payload) { + if(++tx_fifo.exit_point >= NRF52_TX_FIFO_SIZE) { + tx_fifo.exit_point = 0; + } + + tx_fifo.count--; + + // ACK payloads also require TX_DS + // (page 40 of the 'nRF24LE1_Product_Specification_rev1_6.pdf'). + rfp->flags |= NRF52_INT_TX_SUCCESS_MSK; + } + + p_pipe_info->m_ack_payload = 1; + + p_current_payload = tx_fifo.p_payload[tx_fifo.exit_point]; + + set_rf_payload_format(rfp, p_current_payload->length); + tx_payload_buffer[0] = p_current_payload->length; + memcpy(&tx_payload_buffer[2], + p_current_payload->data, + p_current_payload->length); + } + else { + p_pipe_info->m_ack_payload = 0; + set_rf_payload_format(rfp, 0); + tx_payload_buffer[0] = 0; + } + + tx_payload_buffer[1] = rx_payload_buffer[1]; + } + break; + + case NRF52_PROTOCOL_ESB: + { + set_rf_payload_format(rfp, 0); + tx_payload_buffer[0] = rx_payload_buffer[0]; + tx_payload_buffer[1] = 0; + } + break; + } + + rfp->state = NRF52_STATE_PRX_SEND_ACK; + NRF_RADIO->TXADDRESS = NRF_RADIO->RXMATCH; + NRF_RADIO->PACKETPTR = (uint32_t)tx_payload_buffer; + } + else { + clear_events_restart_rx(rfp); + } + + if (send_rx_event) { + // Push the new packet to the RX buffer and trigger a received event if the operation was + // successful. + if (rx_fifo_push_rfbuf(rfp, NRF_RADIO->RXMATCH, p_pipe_info->m_pid)) { + rfp->flags |= NRF52_INT_RX_DR_MSK; + chBSemSignal(&events_sem); + } + } +} + +static void on_radio_disabled_rx_ack(RFDriver *rfp) { + NRF_RADIO->SHORTS = RADIO_SHORTS_COMMON | RADIO_SHORTS_DISABLED_TXEN_Msk; + set_rf_payload_format(rfp, rfp->config.payload_length); + + NRF_RADIO->PACKETPTR = (uint32_t)rx_payload_buffer; + + rfp->state = NRF52_STATE_PRX; +} + +nrf52_error_t radio_disable(void) { + RFD1.state = NRF52_STATE_IDLE; + + // Clear PPI + NRF_PPI->CHENCLR = (1 << NRF52_RADIO_PPI_TIMER_START) | + (1 << NRF52_RADIO_PPI_TIMER_STOP) | + (1 << NRF52_RADIO_PPI_RX_TIMEOUT); + + reset_fifo(); + + memset(rx_pipe_info, 0, sizeof(rx_pipe_info)); + memset(pids, 0, sizeof(pids)); + + // Disable the radio + NRF_RADIO->SHORTS = RADIO_SHORTS_READY_START_Enabled << RADIO_SHORTS_READY_START_Pos | + RADIO_SHORTS_END_DISABLE_Enabled << RADIO_SHORTS_END_DISABLE_Pos; + + nvicDisableVector(RADIO_IRQn); + + // Terminate interrupts handle thread + chThdTerminate(rfIntThread_p); + chBSemSignal(&disable_sem); + chThdWait(rfIntThread_p); + + // Terminate events handle thread + chThdTerminate(rfEvtThread_p); + RFD1.flags = 0; + chBSemSignal(&events_sem); + chThdWait(rfEvtThread_p); + + RFD1.state = NRF52_STATE_UNINIT; + + return NRF52_SUCCESS; +} + +// +nrf52_error_t radio_init(nrf52_config_t const *config) { + osalDbgAssert(config != NULL, + "config must be defined"); + osalDbgAssert(&config->address != NULL, + "address must be defined"); + osalDbgAssert(NRF52_RADIO_IRQ_PRIORITY <= 7, + "wrong radio irq priority"); + + if (RFD1.state != NRF52_STATE_UNINIT) { + nrf52_error_t err = radio_disable(); + if (err != NRF52_SUCCESS) + return err; + } + + RFD1.radio = NRF_RADIO; + RFD1.config = *config; + RFD1.flags = 0; + + init_fifo(); + +#if NRF52_RADIO_USE_TIMER0 + RFD1.timer = NRF_TIMER0; +#endif +#if NRF52_RADIO_USE_TIMER1 + RFD1.timer = NRF_TIMER1; +#endif +#if NRF52_RADIO_USE_TIMER2 + RFD1.timer = NRF_TIMER2; +#endif +#if NRF52_RADIO_USE_TIMER3 + RFD1.timer = NRF_TIMER3; +#endif +#if NRF52_RADIO_USE_TIMER4 + RFD1.timer = NRF_TIMER4; +#endif + + set_parameters(&RFD1); + + set_addresses(&RFD1, NRF52_ADDR_UPDATE_MASK_BASE0); + set_addresses(&RFD1, NRF52_ADDR_UPDATE_MASK_BASE1); + set_addresses(&RFD1, NRF52_ADDR_UPDATE_MASK_PREFIX); + + ppi_init(&RFD1); + timer_init(&RFD1); + + chBSemObjectInit(&disable_sem, TRUE); + chBSemObjectInit(&events_sem, TRUE); + + chEvtObjectInit(&RFD1.eventsrc); + + // interrupt handle thread + rfIntThread_p = chThdCreateStatic(waRFIntThread, sizeof(waRFIntThread), + NRF52_RADIO_INTTHD_PRIORITY, rfIntThread, NULL); + + // events handle thread + rfEvtThread_p = chThdCreateStatic(waRFEvtThread, sizeof(waRFEvtThread), + NRF52_RADIO_EVTTHD_PRIORITY, rfEvtThread, NULL); + + nvicEnableVector(RADIO_IRQn, NRF52_RADIO_IRQ_PRIORITY); + + RFD1.state = NRF52_STATE_IDLE; + + return NRF52_SUCCESS; +} + +nrf52_error_t radio_write_payload(nrf52_payload_t const * p_payload) { + if (RFD1.state == NRF52_STATE_UNINIT) + return NRF52_INVALID_STATE; + if(p_payload == NULL) + return NRF52_ERROR_NULL; + VERIFY_PAYLOAD_LENGTH(p_payload); + if (tx_fifo.count >= NRF52_TX_FIFO_SIZE) + return NRF52_ERROR_INVALID_LENGTH; + + if (RFD1.config.mode == NRF52_MODE_PTX && + p_payload->noack && !RFD1.config.selective_auto_ack ) + { + return NRF52_ERROR_NOT_SUPPORTED; + } + + nvicDisableVector(RADIO_IRQn); + + memcpy(tx_fifo.p_payload[tx_fifo.entry_point], p_payload, sizeof(nrf52_payload_t)); + + pids[p_payload->pipe] = (pids[p_payload->pipe] + 1) % (NRF52_PID_MAX + 1); + tx_fifo.p_payload[tx_fifo.entry_point]->pid = pids[p_payload->pipe]; + + if (++tx_fifo.entry_point >= NRF52_TX_FIFO_SIZE) { + tx_fifo.entry_point = 0; + } + + tx_fifo.count++; + + nvicEnableVector(RADIO_IRQn, NRF52_RADIO_IRQ_PRIORITY); + + if (RFD1.config.mode == NRF52_MODE_PTX && + RFD1.config.tx_mode == NRF52_TXMODE_AUTO && + RFD1.state == NRF52_STATE_IDLE) + { + start_tx_transaction(&RFD1); + } + + return NRF52_SUCCESS; +} + +nrf52_error_t radio_read_rx_payload(nrf52_payload_t * p_payload) { + if (RFD1.state == NRF52_STATE_UNINIT) + return NRF52_INVALID_STATE; + if (p_payload == NULL) + return NRF52_ERROR_NULL; + + if (rx_fifo.count == 0) { + return NRF52_ERROR_INVALID_LENGTH; + } + + nvicDisableVector(RADIO_IRQn); + + p_payload->length = rx_fifo.p_payload[rx_fifo.exit_point]->length; + p_payload->pipe = rx_fifo.p_payload[rx_fifo.exit_point]->pipe; + p_payload->rssi = rx_fifo.p_payload[rx_fifo.exit_point]->rssi; + p_payload->pid = rx_fifo.p_payload[rx_fifo.exit_point]->pid; + memcpy(p_payload->data, rx_fifo.p_payload[rx_fifo.exit_point]->data, p_payload->length); + + if (++rx_fifo.exit_point >= NRF52_RX_FIFO_SIZE) { + rx_fifo.exit_point = 0; + } + + rx_fifo.count--; + + nvicEnableVector(RADIO_IRQn, NRF52_RADIO_IRQ_PRIORITY); + + return NRF52_SUCCESS; +} + +nrf52_error_t radio_start_tx(void) { + if (RFD1.state != NRF52_STATE_IDLE) + return NRF52_ERROR_BUSY; + + if (tx_fifo.count == 0) { + return NRF52_ERROR_INVALID_LENGTH; + } + + start_tx_transaction(&RFD1); + + return NRF52_SUCCESS; +} + +nrf52_error_t radio_start_rx(void) { + if (RFD1.state != NRF52_STATE_IDLE) + return NRF52_ERROR_BUSY; + + NRF_RADIO->INTENCLR = 0xFFFFFFFF; + NRF_RADIO->EVENTS_DISABLED = 0; + (void) NRF_RADIO->EVENTS_DISABLED; + + NRF_RADIO->SHORTS = RADIO_SHORTS_COMMON | RADIO_SHORTS_DISABLED_TXEN_Msk; + NRF_RADIO->INTENSET = RADIO_INTENSET_DISABLED_Msk; + RFD1.state = NRF52_STATE_PRX; + + NRF_RADIO->RXADDRESSES = RFD1.config.address.rx_pipes; + NRF_RADIO->FREQUENCY = RFD1.config.address.rf_channel; + NRF_RADIO->PACKETPTR = (uint32_t)rx_payload_buffer; + + nvicClearPending(RADIO_IRQn); + nvicEnableVector(RADIO_IRQn, NRF52_RADIO_IRQ_PRIORITY); + + NRF_RADIO->EVENTS_ADDRESS = 0; + NRF_RADIO->EVENTS_PAYLOAD = 0; + NRF_RADIO->EVENTS_DISABLED = 0; + (void) NRF_RADIO->EVENTS_ADDRESS; + (void) NRF_RADIO->EVENTS_PAYLOAD; + (void) NRF_RADIO->EVENTS_DISABLED; + + NRF_RADIO->TASKS_RXEN = 1; + + return NRF52_SUCCESS; +} + +nrf52_error_t radio_stop_rx(void) { + if (RFD1.state != NRF52_STATE_PRX) { + return NRF52_INVALID_STATE; + } + + NRF_RADIO->SHORTS = 0; + NRF_RADIO->INTENCLR = 0xFFFFFFFF; + NRF_RADIO->EVENTS_DISABLED = 0; + (void) NRF_RADIO->EVENTS_DISABLED; + NRF_RADIO->TASKS_DISABLE = 1; + while (NRF_RADIO->EVENTS_DISABLED == 0); + RFD1.state = NRF52_STATE_IDLE; + + return NRF52_SUCCESS; +} + +nrf52_error_t radio_flush_tx(void) { + if (RFD1.state == NRF52_STATE_UNINIT) + return NRF52_INVALID_STATE; + + nvicDisableVector(RADIO_IRQn); + + tx_fifo.count = 0; + tx_fifo.entry_point = 0; + tx_fifo.exit_point = 0; + + nvicEnableVector(RADIO_IRQn, NRF52_RADIO_IRQ_PRIORITY); + + return NRF52_SUCCESS; +} + +nrf52_error_t radio_pop_tx(void) { + if (RFD1.state == NRF52_STATE_UNINIT) + return NRF52_INVALID_STATE; + if (tx_fifo.count == 0) + return NRF52_ERROR_INVALID_LENGTH; + + nvicDisableVector(RADIO_IRQn); + + if (++tx_fifo.entry_point >= NRF52_TX_FIFO_SIZE) { + tx_fifo.entry_point = 0; + } + tx_fifo.count--; + + nvicEnableVector(RADIO_IRQn, NRF52_RADIO_IRQ_PRIORITY); + + return NRF52_SUCCESS; +} + +nrf52_error_t radio_flush_rx(void) { + if (RFD1.state == NRF52_STATE_UNINIT) + return NRF52_INVALID_STATE; + + nvicDisableVector(RADIO_IRQn); + + rx_fifo.count = 0; + rx_fifo.entry_point = 0; + rx_fifo.exit_point = 0; + + memset(rx_pipe_info, 0, sizeof(rx_pipe_info)); + + nvicEnableVector(RADIO_IRQn, NRF52_RADIO_IRQ_PRIORITY); + + return NRF52_SUCCESS; +} + +nrf52_error_t radio_set_base_address_0(uint8_t const * p_addr) { + if (RFD1.state != NRF52_STATE_IDLE) + return NRF52_ERROR_BUSY; + if (p_addr == NULL) + return NRF52_ERROR_NULL; + + memcpy(RFD1.config.address.base_addr_p0, p_addr, 4); + set_addresses(&RFD1, NRF52_ADDR_UPDATE_MASK_BASE0); + + return NRF52_SUCCESS; +} + +nrf52_error_t radio_set_base_address_1(uint8_t const * p_addr) { + if (RFD1.state != NRF52_STATE_IDLE) + return NRF52_ERROR_BUSY; + if (p_addr == NULL) + return NRF52_ERROR_NULL; + + memcpy(RFD1.config.address.base_addr_p1, p_addr, 4); + set_addresses(&RFD1, NRF52_ADDR_UPDATE_MASK_BASE1); + + return NRF52_SUCCESS; +} + +nrf52_error_t radio_set_prefixes(uint8_t const * p_prefixes, uint8_t num_pipes) { + if (RFD1.state != NRF52_STATE_IDLE) + return NRF52_ERROR_BUSY; + if (p_prefixes == NULL) + return NRF52_ERROR_NULL; + if (num_pipes > 8) + return NRF52_ERROR_INVALID_PARAM; + + memcpy(RFD1.config.address.pipe_prefixes, p_prefixes, num_pipes); + RFD1.config.address.num_pipes = num_pipes; + RFD1.config.address.rx_pipes = BIT_MASK_UINT_8(num_pipes); + + set_addresses(&RFD1, NRF52_ADDR_UPDATE_MASK_PREFIX); + + return NRF52_SUCCESS; +} + +nrf52_error_t radio_set_prefix(uint8_t pipe, uint8_t prefix) { + if (RFD1.state != NRF52_STATE_IDLE) + return NRF52_ERROR_BUSY; + if (pipe > 8) + return NRF52_ERROR_INVALID_PARAM; + + RFD1.config.address.pipe_prefixes[pipe] = prefix; + + NRF_RADIO->PREFIX0 = bytewise_bit_swap(&RFD1.config.address.pipe_prefixes[0]); + NRF_RADIO->PREFIX1 = bytewise_bit_swap(&RFD1.config.address.pipe_prefixes[4]); + + return NRF52_SUCCESS; +} diff --git a/os/various/devices_lib/rf/nrf52_radio.h b/os/various/devices_lib/rf/nrf52_radio.h new file mode 100644 index 0000000..2f94465 --- /dev/null +++ b/os/various/devices_lib/rf/nrf52_radio.h @@ -0,0 +1,256 @@ +/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + * @brief Enhanced ShockBurst (ESB) is a basic protocol supporting two-way data + * packet communication including packet buffering, packet acknowledgment + * and automatic retransmission of lost packets. + * + * ported on: 25/10/2018, by andru + * + */ + +#ifndef NRF52_RADIO_H_ +#define NRF52_RADIO_H_ + +// Hard coded parameters - change if necessary +#ifndef NRF52_MAX_PAYLOAD_LENGTH +#define NRF52_MAX_PAYLOAD_LENGTH 32 /**< The max size of the payload. Valid values are 1 to 252 */ +#endif + +#define NRF52_CRC_RESET_VALUE 0xFFFF /**< CRC reset value*/ + +#define NRF52_TX_FIFO_SIZE 8 /**< The size of the transmission first in first out buffer. */ +#define NRF52_RX_FIFO_SIZE 8 /**< The size of the reception first in first out buffer. */ + +#define NRF52_RADIO_USE_TIMER0 FALSE /**< TIMER0 will be used by the module. */ +#define NRF52_RADIO_USE_TIMER1 TRUE /**< TIMER1 will be used by the module. */ +#define NRF52_RADIO_USE_TIMER2 FALSE /**< TIMER2 will be used by the module. */ +#define NRF52_RADIO_USE_TIMER3 FALSE /**< TIMER3 will be used by the module. */ +#define NRF52_RADIO_USE_TIMER4 FALSE /**< TIMER4 will be used by the module. */ + +#define NRF52_RADIO_IRQ_PRIORITY 3 /**< RADIO interrupt priority. */ +#define NRF52_RADIO_INTTHD_PRIORITY (NORMALPRIO+2) /**< Interrupts handle thread priority. */ +#define NRF52_RADIO_EVTTHD_PRIORITY (NORMALPRIO+1) /**< Events handle thread priority */ + +#define NRF52_RADIO_PPI_TIMER_START 10 /**< The PPI channel used for timer start. */ +#define NRF52_RADIO_PPI_TIMER_STOP 11 /**< The PPI channel used for timer stop. */ +#define NRF52_RADIO_PPI_RX_TIMEOUT 12 /**< The PPI channel used for RX timeout. */ +#define NRF52_RADIO_PPI_TX_START 13 /**< The PPI channel used for starting TX. */ + + +typedef enum { + NRF52_SUCCESS, /* Call was successful. */ + NRF52_INVALID_STATE, /* Module is not initialized. */ + NRF52_ERROR_BUSY, /* Module was not in idle state. */ + NRF52_ERROR_NULL, /* Required parameter was NULL. */ + NRF52_ERROR_INVALID_PARAM, /* Required parameter is invalid */ + NRF52_ERROR_NOT_SUPPORTED, /* p_payload->noack was false while selective ack was not enabled. */ + NRF52_ERROR_INVALID_LENGTH, /* Payload length was invalid (zero or larger than max allowed). */ +} nrf52_error_t; + +// Internal radio module state. +typedef enum { + NRF52_STATE_UNINIT, /**< Module not initialized. */ + NRF52_STATE_IDLE, /**< Module idle. */ + NRF52_STATE_PTX_TX, /**< Module transmitting without ack. */ + NRF52_STATE_PTX_TX_ACK, /**< Module transmitting with ack. */ + NRF52_STATE_PTX_RX_ACK, /**< Module transmitting with ack and reception of payload with the ack response. */ + NRF52_STATE_PRX, /**< Module receiving packets without ack. */ + NRF52_STATE_PRX_SEND_ACK, /**< Module transmitting ack in RX mode. */ +} nrf52_state_t; + +/**@brief Events to indicate the last transmission/receiving status. */ +typedef enum { + NRF52_EVENT_TX_SUCCESS = 0x01, /**< Event triggered on TX success. */ + NRF52_EVENT_TX_FAILED = 0x02, /**< Event triggered on TX failed. */ + NRF52_EVENT_RX_RECEIVED = 0x04, /**< Event triggered on RX Received. */ +} nrf52_event_t; + +// Interrupt flags +typedef enum { + NRF52_INT_TX_SUCCESS_MSK = 0x01, /**< The flag used to indicate a success since last event. */ + NRF52_INT_TX_FAILED_MSK = 0x02, /**< The flag used to indicate a failiure since last event. */ + NRF52_INT_RX_DR_MSK = 0x04, /**< The flag used to indicate a received packet since last event. */ +} nrf52_int_flags_t; + +/**Macro to create initializer for a TX data packet. + * + * @details This macro generates an initializer. It is more efficient + * than setting the individual parameters dynamically. + * + * @param[in] _pipe The pipe to use for the data packet. + * @param[in] ... Comma separated list of character data to put in the TX buffer. + * Supported values are from 1 to 63 characters. + * + * @return Initializer that sets up pipe, length and the byte array for content of the TX data. + */ +#define NRF52_CREATE_PAYLOAD(_pipe, ...) \ + {.pipe = _pipe, .length = NUM_VA_ARGS(__VA_ARGS__), .data = {__VA_ARGS__}}; \ + STATIC_ASSERT(NUM_VA_ARGS(__VA_ARGS__) > 0 && NUM_VA_ARGS(__VA_ARGS__) <= 63) + +/**@brief Enhanced ShockBurst protocol. */ +typedef enum { + NRF52_PROTOCOL_ESB, /*< Enhanced ShockBurst with fixed payload length. */ + NRF52_PROTOCOL_ESB_DPL /*< Enhanced ShockBurst with dynamic payload length. */ +} nrf52_protocol_t; + +/**@brief Enhanced ShockBurst mode. */ +typedef enum { + NRF52_MODE_PTX, /*< Primary transmitter mode. */ + NRF52_MODE_PRX /*< Primary receiver mode. */ +} nrf52_mode_t; + +/**@brief Enhanced ShockBurst bitrate mode. */ +typedef enum { + NRF52_BITRATE_2MBPS = RADIO_MODE_MODE_Nrf_2Mbit, /**< 2Mbit radio mode. */ + NRF52_BITRATE_1MBPS = RADIO_MODE_MODE_Nrf_1Mbit, /**< 1Mbit radio mode. */ +} nrf52_bitrate_t; + +/**@brief Enhanced ShockBurst CRC modes. */ +typedef enum { + NRF52_CRC_16BIT = RADIO_CRCCNF_LEN_Two, /**< Use two byte CRC. */ + NRF52_CRC_8BIT = RADIO_CRCCNF_LEN_One, /**< Use one byte CRC. */ + NRF52_CRC_OFF = RADIO_CRCCNF_LEN_Disabled /**< Disable CRC. */ +} nrf52_crc_t; + +/**@brief Enhanced ShockBurst radio transmission power modes. */ +typedef enum { + NRF52_TX_POWER_4DBM = RADIO_TXPOWER_TXPOWER_Pos4dBm, /**< 4 dBm radio transmit power. */ + NRF52_TX_POWER_0DBM = RADIO_TXPOWER_TXPOWER_0dBm, /**< 0 dBm radio transmit power. */ + NRF52_TX_POWER_NEG4DBM = RADIO_TXPOWER_TXPOWER_Neg4dBm, /**< -4 dBm radio transmit power. */ + NRF52_TX_POWER_NEG8DBM = RADIO_TXPOWER_TXPOWER_Neg8dBm, /**< -8 dBm radio transmit power. */ + NRF52_TX_POWER_NEG12DBM = RADIO_TXPOWER_TXPOWER_Neg12dBm, /**< -12 dBm radio transmit power. */ + NRF52_TX_POWER_NEG16DBM = RADIO_TXPOWER_TXPOWER_Neg16dBm, /**< -16 dBm radio transmit power. */ + NRF52_TX_POWER_NEG20DBM = RADIO_TXPOWER_TXPOWER_Neg20dBm, /**< -20 dBm radio transmit power. */ + NRF52_TX_POWER_NEG30DBM = RADIO_TXPOWER_TXPOWER_Neg30dBm /**< -30 dBm radio transmit power. */ +} nrf52_tx_power_t; + +/**@brief Enhanced ShockBurst transmission modes. */ +typedef enum { + NRF52_TXMODE_AUTO, /*< Automatic TX mode - When the TX fifo is non-empty and the radio is idle packets will be sent automatically. */ + NRF52_TXMODE_MANUAL, /*< Manual TX mode - Packets will not be sent until radio_start_tx() is called. Can be used to ensure consistent packet timing. */ + NRF52_TXMODE_MANUAL_START /*< Manual start TX mode - Packets will not be sent until radio_start_tx() is called, but transmission will continue automatically until the TX fifo is empty. */ +} nrf52_tx_mode_t; + +/**@brief Enhanced ShockBurst addresses. + * + * @details The module is able to transmit packets with the TX address stored in tx_address. + The module can also receive packets from peers with up to eight different tx_addresses + stored in esb_addr_p0 - esb_addr_p7. esb_addr_p0 can have 5 arbitrary bytes + independent of the other addresses. esb_addr_p1 - esb_addr_p7 will share the + same four byte base address found in the last four bytes of esb_addr_p1. + They have an independent prefix byte found in esb_addr_p1[0] and esb_addr_p2 - + esb_addr_p7. +*/ +typedef struct { + uint8_t base_addr_p0[4]; /**< Base address for pipe 0 encoded in big endian. */ + uint8_t base_addr_p1[4]; /**< Base address for pipe 1-7 encoded in big endian. */ + uint8_t pipe_prefixes[8]; /**< Address prefix for pipe P0 to P7. */ + uint8_t num_pipes; /**< Number of pipes available. */ + uint8_t addr_length; /**< Length of address including prefix */ + uint8_t rx_pipes; /**< Bitfield for enabled RX pipes. */ + uint8_t rf_channel; /**< Which channel is to be used. Must be in range 0 and 125 to be valid. */ +} nrf52_address_t; + +/**@brief Enhanced ShockBurst payload. + * + * @note The payload is used both for transmission and receive with ack and payload. +*/ +typedef struct +{ + uint8_t length; /**< Length of the packet. Should be equal or less than NRF_ESB_MAX_PAYLOAD_LENGTH. */ + uint8_t pipe; /**< Pipe used for this payload. */ + int8_t rssi; /**< RSSI for received packet. */ + uint8_t noack; /**< Flag indicating that this packet will not be acknowledged. */ + uint8_t pid; /**< PID assigned during communication. */ + uint8_t data[NRF52_MAX_PAYLOAD_LENGTH]; /**< The payload data. */ +} nrf52_payload_t; + +/**@brief Retransmit attempts delay and counter. */ +typedef struct { + uint16_t delay; /**< The delay between each retransmission of unacked packets. */ + uint16_t count; /**< The number of retransmissions attempts before transmission fail. */ +} nrf52_retransmit_t; + +/**@brief Main nrf_esb configuration struct. */ +typedef struct { + nrf52_protocol_t protocol; /**< Enhanced ShockBurst protocol. */ + nrf52_mode_t mode; /**< Enhanced ShockBurst default RX or TX mode. */ + + // General RF parameters + nrf52_bitrate_t bitrate; /**< Enhanced ShockBurst bitrate mode. */ + nrf52_crc_t crc; /**< Enhanced ShockBurst CRC mode. */ + nrf52_tx_power_t tx_power; /**< Enhanced ShockBurst radio transmission power mode.*/ + + // Control settings + nrf52_tx_mode_t tx_mode; /**< Enhanced ShockBurst transmit mode. */ + + bool selective_auto_ack; /**< Enable or disable selective auto acknowledgement. */ + + nrf52_retransmit_t retransmit; /**< Packet retransmit parameters */ + + uint8_t payload_length; /**< Enhanced ShockBurst static payload length */ + + nrf52_address_t address; /**< Address parameters structure */ +} nrf52_config_t; + +typedef struct { + /** + * @brief NRF52 radio peripheral. + */ + NRF_RADIO_Type *radio; + /** + * @brief NRF52 timer peripheral. + */ + NRF_TIMER_Type *timer; + /** + * @brief Driver state. + */ + nrf52_state_t state; + /** + * @brief RF parameters. + */ + nrf52_config_t config; + /** + * @brief Interrupts flag. + */ + nrf52_int_flags_t flags; + /** + * @brief TX attempt number. + */ + uint16_t tx_attempt; + /** + * @brief TX retransmits remaining. + */ + uint16_t tx_remaining; + /** + * @brief Radio events source. + */ + event_source_t eventsrc; +} RFDriver; + +extern RFDriver RFD1; + +nrf52_error_t radio_init(nrf52_config_t const *config); +nrf52_error_t radio_disable(void); +nrf52_error_t radio_write_payload(nrf52_payload_t const * p_payload); +nrf52_error_t radio_read_rx_payload(nrf52_payload_t * p_payload); +nrf52_error_t radio_start_tx(void); +nrf52_error_t radio_start_rx(void); +nrf52_error_t radio_stop_rx(void); +nrf52_error_t radio_flush_tx(void); +nrf52_error_t radio_flush_rx(void); +nrf52_error_t radio_pop_tx(void); +nrf52_error_t radio_set_base_address_0(uint8_t const * p_addr); +nrf52_error_t radio_set_base_address_1(uint8_t const * p_addr); +nrf52_error_t radio_set_prefixes(uint8_t const * p_prefixes, uint8_t num_pipes); +nrf52_error_t radio_set_prefix(uint8_t pipe, uint8_t prefix); + +#endif /* NRF52_RADIO_H_ */ diff --git a/os/various/fatfs_bindings/fatfs.mk b/os/various/fatfs_bindings/fatfs.mk index 02ebed5..7548acf 100644 --- a/os/various/fatfs_bindings/fatfs.mk +++ b/os/various/fatfs_bindings/fatfs.mk @@ -5,3 +5,7 @@ FATFSSRC = ${CHIBIOS_CONTRIB}/os/various/fatfs_bindings/fatfs_diskio.c \ $(CHIBIOS)/ext/fatfs/src/ffunicode.c FATFSINC = ${CHIBIOS}/ext/fatfs/src ${CHIBIOS_CONTRIB}/os/various/fatfs_bindings + +# Shared variables +ALLCSRC += $(FATFSSRC) +ALLINC += $(FATFSINC) diff --git a/os/various/fatfs_bindings/fatfs_devices.h b/os/various/fatfs_bindings/fatfs_devices.h index 5ec05ca..fe28383 100644 --- a/os/various/fatfs_bindings/fatfs_devices.h +++ b/os/various/fatfs_bindings/fatfs_devices.h @@ -20,39 +20,21 @@ #include "hal.h" -#if HAL_USE_MMC_SPI && HAL_USE_SDC -#error "cannot specify both MMC_SPI and SDC drivers" -#endif - -#if HAL_USE_MMC_SPI -extern MMCDriver MMCD1; -#elif HAL_USE_SDC -extern SDCDriver SDCD1; -#elif HAL_USBH_USE_MSD - -#else -#error "MMC_SPI, SDC or USBH_MSD driver must be specified" -#endif - /*-----------------------------------------------------------------------*/ /* Correspondence between physical drive number and physical drive. */ -#if HAL_USE_MMC_SPI +#if HAL_USE_MMC_SPI || HAL_USE_SDC #define FATFSDEV_MMC 0 #define FATFSDEV_MMC_DRIVE "0:" #endif -#if HAL_USE_SDC -#define FATFSDEV_SDC 0 -#define FATFSDEV_SDC_DRIVE "0:" -#endif #if HAL_USBH_USE_MSD -#if defined(FATFSDEV_MMC) || defined(FATFSDEV_SDC) -#define FATFSDEV_MSDLUN0 1 -#define FATFSDEV_MSDLUN0_DRIVE "1:" +#if defined(FATFSDEV_MMC) +#define FATFSDEV_MSD 1 +#define FATFSDEV_MSD_DRIVE "1:" #else -#define FATFSDEV_MSDLUN0 0 -#define FATFSDEV_MSDLUN0_DRIVE "0:" +#define FATFSDEV_MSD 0 +#define FATFSDEV_MSD_DRIVE "0:" #endif #endif diff --git a/os/various/fatfs_bindings/fatfs_diskio.c b/os/various/fatfs_bindings/fatfs_diskio.c index 0104a11..e3cfd53 100644 --- a/os/various/fatfs_bindings/fatfs_diskio.c +++ b/os/various/fatfs_bindings/fatfs_diskio.c @@ -7,15 +7,48 @@ #include "hal.h" #include "ffconf.h" +#include "ff.h" #include "diskio.h" #include "usbh/dev/msd.h" #include "fatfs_devices.h" +#if HAL_USE_MMC_SPI && HAL_USE_SDC +#error "cannot specify both MMC_SPI and FATFSDEV_MMC drivers" +#endif + +// sanity check for no FAT option selected +// why is the FAT sources being pulled into the build? +#if !HAL_USE_MMC_SPI && !HAL_USE_SDC & !HAL_USBH_USE_MSD +#error "MMC_SPI, FATFSDEV_MMC or USBH_MSD driver must be specified. None was." +#endif + +#if !defined(FATFS_HAL_DEVICE) +#if HAL_USE_MMC_SPI +#define FATFS_HAL_DEVICE MMCD1 +#else +#define FATFS_HAL_DEVICE SDCD1 +#endif +#endif + +#if HAL_USE_MMC_SPI +extern MMCDriver FATFS_HAL_DEVICE; +#endif +#if HAL_USE_SDC +extern SDCDriver FATFS_HAL_DEVICE; +#endif +#if HAL_USBH_USE_MSD +#endif + +#if HAL_USE_RTC +extern RTCDriver RTCD1; +#endif + + /*-----------------------------------------------------------------------*/ /* Inidialize a Drive */ DSTATUS disk_initialize ( - BYTE pdrv /* Physical drive nmuber (0..) */ + BYTE pdrv /* Physical drive number (0..) */ ) { DSTATUS stat; @@ -25,23 +58,23 @@ DSTATUS disk_initialize ( case FATFSDEV_MMC: stat = 0; /* It is initialized externally, just reads the status.*/ - if (blkGetDriverState(&MMCD1) != BLK_READY) + if (blkGetDriverState(&FATFS_HAL_DEVICE) != BLK_READY) stat |= STA_NOINIT; - if (mmcIsWriteProtected(&MMCD1)) + if (mmcIsWriteProtected(&FATFS_HAL_DEVICE)) stat |= STA_PROTECT; return stat; #elif HAL_USE_SDC - case FATFSDEV_SDC: + case FATFSDEV_MMC: stat = 0; /* It is initialized externally, just reads the status.*/ - if (blkGetDriverState(&SDCD1) != BLK_READY) + if (blkGetDriverState(&FATFS_HAL_DEVICE) != BLK_READY) stat |= STA_NOINIT; - if (sdcIsWriteProtected(&SDCD1)) + if (sdcIsWriteProtected(&FATFS_HAL_DEVICE)) stat |= STA_PROTECT; return stat; #endif #if HAL_USBH_USE_MSD - case FATFSDEV_MSDLUN0: + case FATFSDEV_MSD: stat = 0; /* It is initialized externally, just reads the status.*/ if (blkGetDriverState(&MSBLKD[0]) != BLK_READY) @@ -68,23 +101,23 @@ DSTATUS disk_status ( case FATFSDEV_MMC: stat = 0; /* It is initialized externally, just reads the status.*/ - if (blkGetDriverState(&MMCD1) != BLK_READY) + if (blkGetDriverState(&FATFS_HAL_DEVICE) != BLK_READY) stat |= STA_NOINIT; - if (mmcIsWriteProtected(&MMCD1)) + if (mmcIsWriteProtected(&FATFS_HAL_DEVICE)) stat |= STA_PROTECT; return stat; #elif HAL_USE_SDC - case FATFSDEV_SDC: + case FATFSDEV_MMC: stat = 0; /* It is initialized externally, just reads the status.*/ - if (blkGetDriverState(&SDCD1) != BLK_READY) + if (blkGetDriverState(&FATFS_HAL_DEVICE) != BLK_READY) stat |= STA_NOINIT; - if (sdcIsWriteProtected(&SDCD1)) + if (sdcIsWriteProtected(&FATFS_HAL_DEVICE)) stat |= STA_PROTECT; return stat; #endif #if HAL_USBH_USE_MSD - case FATFSDEV_MSDLUN0: + case FATFSDEV_MSD: stat = 0; /* It is initialized externally, just reads the status.*/ if (blkGetDriverState(&MSBLKD[0]) != BLK_READY) @@ -110,29 +143,29 @@ DRESULT disk_read ( switch (pdrv) { #if HAL_USE_MMC_SPI case FATFSDEV_MMC: - if (blkGetDriverState(&MMCD1) != BLK_READY) + if (blkGetDriverState(&FATFS_HAL_DEVICE) != BLK_READY) return RES_NOTRDY; - if (mmcStartSequentialRead(&MMCD1, sector)) + if (mmcStartSequentialRead(&FATFS_HAL_DEVICE, sector)) return RES_ERROR; while (count > 0) { - if (mmcSequentialRead(&MMCD1, buff)) + if (mmcSequentialRead(&FATFS_HAL_DEVICE, buff)) return RES_ERROR; buff += MMCSD_BLOCK_SIZE; count--; } - if (mmcStopSequentialRead(&MMCD1)) + if (mmcStopSequentialRead(&FATFS_HAL_DEVICE)) return RES_ERROR; return RES_OK; #elif HAL_USE_SDC - case FATFSDEV_SDC: - if (blkGetDriverState(&SDCD1) != BLK_READY) + case FATFSDEV_MMC: + if (blkGetDriverState(&FATFS_HAL_DEVICE) != BLK_READY) return RES_NOTRDY; - if (sdcRead(&SDCD1, sector, buff, count)) + if (sdcRead(&FATFS_HAL_DEVICE, sector, buff, count)) return RES_ERROR; return RES_OK; #endif #if HAL_USBH_USE_MSD - case FATFSDEV_MSDLUN0: + case FATFSDEV_MSD: /* It is initialized externally, just reads the status.*/ if (blkGetDriverState(&MSBLKD[0]) != BLK_READY) return RES_NOTRDY; @@ -149,6 +182,7 @@ DRESULT disk_read ( /*-----------------------------------------------------------------------*/ /* Write Sector(s) */ +#if !FF_FS_READONLY DRESULT disk_write ( BYTE pdrv, /* Physical drive number (0..) */ const BYTE *buff, /* Data to be written */ @@ -156,37 +190,51 @@ DRESULT disk_write ( UINT count /* Number of sectors to write (1..255) */ ) { + switch (pdrv) { #if HAL_USE_MMC_SPI case FATFSDEV_MMC: - if (blkGetDriverState(&MMCD1) != BLK_READY) + if (blkGetDriverState(&FATFS_HAL_DEVICE) != BLK_READY) return RES_NOTRDY; - if (mmcIsWriteProtected(&MMCD1)) + if (mmcIsWriteProtected(&FATFS_HAL_DEVICE)) return RES_WRPRT; - if (mmcStartSequentialWrite(&MMCD1, sector)) + if (mmcStartSequentialWrite(&FATFS_HAL_DEVICE, sector)) return RES_ERROR; + while (count > 0) { - if (mmcSequentialWrite(&MMCD1, buff)) + // invalidate cache on buffer + cacheBufferFlush(buff, MMCSD_BLOCK_SIZE); + + if (mmcSequentialWrite(&FATFS_HAL_DEVICE, buff)) return RES_ERROR; buff += MMCSD_BLOCK_SIZE; count--; } - if (mmcStopSequentialWrite(&MMCD1)) + if (mmcStopSequentialWrite(&FATFS_HAL_DEVICE)) return RES_ERROR; return RES_OK; #elif HAL_USE_SDC - case FATFSDEV_SDC: - if (blkGetDriverState(&SDCD1) != BLK_READY) + case FATFSDEV_MMC: + if (blkGetDriverState(&FATFS_HAL_DEVICE) != BLK_READY) return RES_NOTRDY; - if (sdcWrite(&SDCD1, sector, buff, count)) - return RES_ERROR; + + // invalidate cache on buffer + cacheBufferFlush(buff, count * MMCSD_BLOCK_SIZE); + + if (sdcWrite(&FATFS_HAL_DEVICE, sector, buff, count)) + return RES_ERROR; + return RES_OK; #endif #if HAL_USBH_USE_MSD - case FATFSDEV_MSDLUN0: + case FATFSDEV_MSD: /* It is initialized externally, just reads the status.*/ if (blkGetDriverState(&MSBLKD[0]) != BLK_READY) return RES_NOTRDY; + + // invalidate cache on buffer + cacheBufferFlush(buff, count * MSBLKD[0].info.blk_size); + if (usbhmsdLUNWrite(&MSBLKD[0], sector, buff, count)) return RES_ERROR; return RES_OK; @@ -194,6 +242,7 @@ DRESULT disk_write ( } return RES_PARERR; } +#endif /* _FS_READONLY */ @@ -207,6 +256,7 @@ DRESULT disk_ioctl ( ) { (void)buff; + switch (pdrv) { #if HAL_USE_MMC_SPI case FATFSDEV_MMC: @@ -220,19 +270,19 @@ DRESULT disk_ioctl ( #endif #if FF_USE_TRIM case CTRL_TRIM: - mmcErase(&MMCD1, *((DWORD *)buff), *((DWORD *)buff + 1)); + mmcErase(&FATFS_HAL_DEVICE, *((DWORD *)buff), *((DWORD *)buff + 1)); return RES_OK; #endif default: return RES_PARERR; } #elif HAL_USE_SDC - case FATFSDEV_SDC: + case FATFSDEV_MMC: switch (cmd) { case CTRL_SYNC: return RES_OK; case GET_SECTOR_COUNT: - *((DWORD *)buff) = mmcsdGetCardCapacity(&SDCD1); + *((DWORD *)buff) = mmcsdGetCardCapacity(&FATFS_HAL_DEVICE); return RES_OK; #if FF_MAX_SS > FF_MIN_SS case GET_SECTOR_SIZE: @@ -244,7 +294,7 @@ DRESULT disk_ioctl ( return RES_OK; #if FF_USE_TRIM case CTRL_TRIM: - sdcErase(&SDCD1, *((DWORD *)buff), *((DWORD *)buff + 1)); + sdcErase(&FATFS_HAL_DEVICE, *((DWORD *)buff), *((DWORD *)buff + 1)); return RES_OK; #endif default: @@ -252,7 +302,7 @@ DRESULT disk_ioctl ( } #endif #if HAL_USBH_USE_MSD - case FATFSDEV_MSDLUN0: + case FATFSDEV_MSD: switch (cmd) { case CTRL_SYNC: return RES_OK; diff --git a/os/various/median.c b/os/various/median.c new file mode 100644 index 0000000..6e2f99f --- /dev/null +++ b/os/various/median.c @@ -0,0 +1,129 @@ +/* + ChibiOS-Contrib - Copyright (C) 2014...2019 Fabien Poussin + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "median.h" + +void median_init(median_t* conf, uint16_t stopper, pair_t* buffer, uint16_t size) +{ + conf->stopper = stopper; + conf->buffer = buffer; + conf->size = size; + pair_t small_tmp = {NULL, conf->stopper}; + pair_t big_tmp = {&conf->small, 0}; + conf->datpoint = conf->buffer; /* Pointer into circular buffer of data */ + conf->small = small_tmp; /* Chain stopper */ + conf->big = big_tmp; /* Pointer to head (largest) of linked list.*/ +} + +uint16_t median_filter(median_t* conf, uint16_t datum) +{ + pair_t *successor; /* Pointer to successor of replaced data item */ + pair_t *scan; /* Pointer used to scan down the sorted list */ + pair_t *scanold; /* Previous value of scan */ + pair_t *median; /* Pointer to median */ + uint16_t i; + + if (datum == conf->stopper) + { + datum = conf->stopper + 1; /* No stoppers allowed. */ + } + + if ( (++conf->datpoint - conf->buffer) >= conf->size) + { + conf->datpoint = conf->buffer; /* Increment and wrap data in pointer.*/ + } + + conf->datpoint->value = datum; /* Copy in new datum */ + successor = conf->datpoint->point; /* Save pointer to old value's successor */ + median = &conf->big; /* Median initially to first in chain */ + scanold = NULL; /* Scanold initially null. */ + scan = &conf->big; /* Points to pointer to first (largest) datum in chain */ + + /* Handle chain-out of first item in chain as special case */ + if (scan->point == conf->datpoint) + { + scan->point = successor; + } + scanold = scan; /* Save this pointer and */ + scan = scan->point ; /* step down chain */ + + /* Loop through the chain, normal loop exit via break. */ + for (i = 0 ; i < conf->size; ++i) + { + /* Handle odd-numbered item in chain */ + if (scan->point == conf->datpoint) + { + scan->point = successor; /* Chain out the old datum.*/ + } + + if (scan->value < datum) /* If datum is larger than scanned value,*/ + { + conf->datpoint->point = scanold->point; /* Chain it in here. */ + scanold->point = conf->datpoint; /* Mark it chained in. */ + datum = conf->stopper; + }; + + /* Step median pointer down chain after doing odd-numbered element */ + median = median->point; /* Step median pointer. */ + if (scan == &conf->small) + { + break; /* Break at end of chain */ + } + scanold = scan; /* Save this pointer and */ + scan = scan->point; /* step down chain */ + + /* Handle even-numbered item in chain. */ + if (scan->point == conf->datpoint) + { + scan->point = successor; + } + + if (scan->value < datum) + { + conf->datpoint->point = scanold->point; + scanold->point = conf->datpoint; + datum = conf->stopper; + } + + if (scan == &conf->small) + { + break; + } + + scanold = scan; + scan = scan->point; + } + return median->value; +} + +uint16_t middle_of_3(uint16_t a, uint16_t b, uint16_t c) +{ + uint16_t middle; + + if ((a <= b) && (a <= c)) + { + middle = (b <= c) ? b : c; + } + else if ((b <= a) && (b <= c)) + { + middle = (a <= c) ? a : c; + } + else + { + middle = (a <= b) ? a : b; + } + return middle; +} diff --git a/os/various/median.h b/os/various/median.h new file mode 100644 index 0000000..c74cb66 --- /dev/null +++ b/os/various/median.h @@ -0,0 +1,42 @@ +/* + ChibiOS-Contrib - Copyright (C) 2014...2019 Fabien Poussin + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MEDIAN_H_ +#define MEDIAN_H_ + +#include "ch.h" + +typedef struct pair_ +{ + struct pair_* point; /* Pointers forming list linked in sorted order */ + uint16_t value; /* Values to sort */ +} pair_t; + +typedef struct +{ + uint16_t stopper; /* Smaller than any datum */ + uint16_t size; /* 3 or more */ + pair_t* buffer; /* Buffer of nwidth pairs */ + pair_t* datpoint; /* Pointer into circular buffer of data */ + pair_t small; /* Chain stopper */ + pair_t big; /* Pointer to head (largest) of linked list.*/ +} median_t; + +void median_init(median_t* conf, uint16_t stopper, pair_t* buffer, uint16_t size); +uint16_t median_filter(median_t* conf, uint16_t datum); +uint16_t middle_of_3(uint16_t a, uint16_t b, uint16_t c); + +#endif /* MEDIAN_H_ */ diff --git a/os/various/ramdisk.c b/os/various/ramdisk.c index 23bf658..d0d366a 100644 --- a/os/various/ramdisk.c +++ b/os/various/ramdisk.c @@ -139,6 +139,7 @@ static bool get_info(void *instance, BlockDeviceInfo *bdip) { * */ static const struct BaseBlockDeviceVMT vmt = { + (size_t)0, is_inserted, is_protected, connect, |