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Author
Age
Files
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test: add attribute-before-stmt test from @nakengelhardt
Eddie Hung
2020-05-25
1
-0
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+15
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verilog: do not warn for attributes on null statements
Eddie Hung
2020-05-25
1
-4
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+4
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tests: add an generate-else test too
Eddie Hung
2020-05-25
1
-0
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+34
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tests: add #2037 testcase
Eddie Hung
2020-05-25
1
-0
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+9
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xaiger: add testcase
Eddie Hung
2020-05-24
1
-0
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+13
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Merge pull request #2057 from YosysHQ/eddie/fix_task_attr
Eddie Hung
2020-05-21
1
-0
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+28
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tests: attributes before task enable
Eddie Hung
2020-05-14
1
-0
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+28
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Add force_downto and force_upto wire attributes.
Marcelina Kościelnicka
2020-05-19
1
-2
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+4
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Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff
Eddie Hung
2020-05-18
6
-117
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+108
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abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it
Eddie Hung
2020-05-14
1
-3
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+8
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abc9_ops: add -prep_bypass for auto bypass boxes; refactor
Eddie Hung
2020-05-14
1
-5
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+29
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abc9: not enough to techmap_fail on (* init=1 *), hide them using $__
Eddie Hung
2020-05-14
1
-2
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+21
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abc9: test to use box file instead of auto
Eddie Hung
2020-05-14
3
-2
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+5
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abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too
Eddie Hung
2020-05-14
1
-5
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+7
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abc9: suppress warnings when no compatible + used flop boxes formed
Eddie Hung
2020-05-14
1
-1
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+3
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xilinx: update abc9_dff tests
Eddie Hung
2020-05-14
1
-18
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+45
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xilinx: remove no-longer-relevant test
Eddie Hung
2020-05-14
1
-91
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+0
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Merge pull request #1994 from YosysHQ/eddie/fix_bug1758
Eddie Hung
2020-05-14
8
-5
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+451
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test: update opt_expr_alu test
Eddie Hung
2020-05-08
1
-2
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+1
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tests: opt_expr tests that depend on consumex
Eddie Hung
2020-05-08
1
-0
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+35
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tests: fsm to use a randomly-generated seed
Eddie Hung
2020-04-24
1
-3
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+5
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opt_expr: const_xnor replacement to pad Y with 1'b1
Eddie Hung
2020-04-24
1
-0
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+46
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tests: opt_expr update xnor/xor tests
Eddie Hung
2020-04-24
2
-7
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+6
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opt_expr: do not group by X, more fixes
Eddie Hung
2020-04-23
2
-2
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+2
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tests: add opt_expr tests
Eddie Hung
2020-04-23
5
-0
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+365
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Merge pull request #2045 from YosysHQ/eddie/fix2042
Eddie Hung
2020-05-14
4
-0
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+93
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test: add another testcase as per @nakengelhardt
Eddie Hung
2020-05-14
1
-0
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+25
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tests: update/extend task argument tests
Eddie Hung
2020-05-13
2
-2
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+35
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tests: add #2042 testcase
Eddie Hung
2020-05-11
1
-0
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+12
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Setup tests/verilog properly
Eddie Hung
2020-05-11
2
-0
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+23
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Merge pull request #2050 from YosysHQ/eddie/opt_clean_fixes
Claire Wolf
2020-05-14
1
-0
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+13
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opt_clean: improve warning message
Eddie Hung
2020-05-14
1
-1
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+1
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opt_clean: add init test
Eddie Hung
2020-05-14
1
-0
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+13
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Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto
Claire Wolf
2020-05-14
1
-0
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+4
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techlibs/common: more robustness when *_WIDTH = 0
Eddie Hung
2020-05-05
1
-1
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+0
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test: add failing test
Eddie Hung
2020-05-04
1
-0
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+5
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intel_alm: direct LUTRAM cell instantiation
Dan Ravensloft
2020-05-07
1
-0
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+20
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Merge pull request #2005 from YosysHQ/claire/fix1990
Claire Wolf
2020-05-07
1
-0
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+46
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Bugfix in partsel.v signed indices test cases
Claire Wolf
2020-05-02
1
-2
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+2
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Add tests based on the test case from #1990
Claire Wolf
2020-05-02
1
-0
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+46
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Merge pull request #2028 from zachjs/master
Eddie Hung
2020-05-06
2
-0
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+17
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verilog: allow null gen-if then block
Zachary Snow
2020-05-06
2
-0
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+17
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Merge pull request #2024 from YosysHQ/eddie/primitive_src
Eddie Hung
2020-05-05
1
-0
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+16
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tests: add tests for primitives' src
Eddie Hung
2020-05-04
1
-0
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+16
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verilog: fix specify src attribute
Eddie Hung
2020-05-04
1
-0
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+6
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Merge pull request #2014 from YosysHQ/claire/fixoptalu
Claire Wolf
2020-05-03
1
-0
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+12
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test: add test for #2014
Eddie Hung
2020-05-02
1
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+12
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tests: aiger test for wire->start_offset != 0
Eddie Hung
2020-05-02
2
-0
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+41
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Add testcase for #2010
Eddie Hung
2020-05-01
1
-0
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+10
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intel_alm: work around a Quartus ICE
Dan Ravensloft
2020-04-23
1
-0
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+12
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