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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-15 15:41:55 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:56 -0700 |
| commit | 8d7b3c06b2ced88d40bc5c024805c778edd6fe2f (patch) | |
| tree | 52d6ed21d788ebd0b4ea53551b6cad2cf7eddbb3 /tests | |
| parent | cdd250ef166ec98b053db44d0d811e98bdef53b4 (diff) | |
| download | yosys-8d7b3c06b2ced88d40bc5c024805c778edd6fe2f.tar.gz yosys-8d7b3c06b2ced88d40bc5c024805c778edd6fe2f.tar.bz2 yosys-8d7b3c06b2ced88d40bc5c024805c778edd6fe2f.zip | |
abc9: suppress warnings when no compatible + used flop boxes formed
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/arch/xilinx/abc9_dff.ys | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/tests/arch/xilinx/abc9_dff.ys b/tests/arch/xilinx/abc9_dff.ys index abe597e2c..15343970f 100644 --- a/tests/arch/xilinx/abc9_dff.ys +++ b/tests/arch/xilinx/abc9_dff.ys @@ -14,6 +14,7 @@ endmodule EOT equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf design -load postopt +select -assert-count 6 t:FD* select -assert-count 6 c:fd2 c:fd3 c:fd4 c:fd6 c:fd7 c:fd8 @@ -32,6 +33,7 @@ endmodule EOT equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf design -load postopt +select -assert-count 4 t:FD* select -assert-count 4 c:fd3 c:fd4 c:fd7 c:fd8 @@ -54,6 +56,6 @@ logger -expect warning "Module 'FDSE' contains a \$_DFF_P_ cell .*" 1 logger -expect warning "Module '\$paramod\\FDSE_1\\INIT=1' contains a \$_DFF_N_ cell .*" 1 equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf design -load postopt -#select -assert-count 4 c:fd3 c:fd4 c:fd7 c:fd8 +select -assert-count 8 t:FD* logger -expect-no-warnings |