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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-04 10:53:06 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-04 10:53:06 -0700 |
| commit | eb5eb60fd4af431ea38a50ad1deebcc40ad4c222 (patch) | |
| tree | 7115f9042aa94798283a091633b760ad56e6769f /tests | |
| parent | 584780d776c92bc91731dbc2710dd8d9a624dc70 (diff) | |
| download | yosys-eb5eb60fd4af431ea38a50ad1deebcc40ad4c222.tar.gz yosys-eb5eb60fd4af431ea38a50ad1deebcc40ad4c222.tar.bz2 yosys-eb5eb60fd4af431ea38a50ad1deebcc40ad4c222.zip | |
verilog: fix specify src attribute
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/specify.ys | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/tests/various/specify.ys b/tests/various/specify.ys index 9d55b8eb5..d7260d524 100644 --- a/tests/various/specify.ys +++ b/tests/various/specify.ys @@ -4,10 +4,16 @@ cd test select t:$specify2 -assert-count 0 select t:$specify3 -assert-count 1 select t:$specrule -assert-count 2 +select t:$specify3 a:src=specify.v:10.3-10.49 %i -assert-count 1 +select t:$specrule a:src=specify.v:11.3-11.36 %i -assert-count 1 +select t:$specrule a:src=specify.v:12.3-12.35 %i -assert-count 1 cd test2 select t:$specify2 -assert-count 2 select t:$specify3 -assert-count 0 select t:$specrule -assert-count 0 +select t:$specify2 a:src=specify.v:26.3-26.20 %i -assert-count 1 + # ^^ Note use of macro +select t:$specify2 a:src=specify.v:28.3-28.18 %i -assert-count 1 cd write_verilog specify.out design -stash gold |