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authorEddie Hung <eddie@fpgeh.com>2020-05-21 11:00:36 -0700
committerGitHub <noreply@github.com>2020-05-21 11:00:36 -0700
commit574812d9a54881784b104c71ba56a2e6ed14d39f (patch)
treea0c659648a7a541602d9b68db5910c9586d5c7fb /tests
parent637650597b27a2e2f5407fc128ffd21d7a0b3016 (diff)
parent38e858af8d5f61677d9686c022c864857f729d58 (diff)
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Merge pull request #2057 from YosysHQ/eddie/fix_task_attr
verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
Diffstat (limited to 'tests')
-rw-r--r--tests/verilog/task_attr.ys28
1 files changed, 28 insertions, 0 deletions
diff --git a/tests/verilog/task_attr.ys b/tests/verilog/task_attr.ys
new file mode 100644
index 000000000..d6e75f85f
--- /dev/null
+++ b/tests/verilog/task_attr.ys
@@ -0,0 +1,28 @@
+read_verilog <<EOT
+module top;
+ task foo;
+ endtask
+
+ always @*
+ (* foo *) foo;
+
+ initial
+ if (0) $info("bar");
+endmodule
+EOT
+# Since task enables are not an RTLIL object,
+# any attributes on their AST get dropped
+select -assert-none a:* a:src %d
+
+
+logger -expect error "syntax error, unexpected ATTR_BEGIN" 1
+design -reset
+read_verilog <<EOT
+module top;
+ task foo;
+ endtask
+
+ always @*
+ foo (* foo *);
+endmodule
+EOT