| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Call shregmap twice -- once for variable, another for fixed | Eddie Hung | 2019-04-05 | 2 | -8/+14 |
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| * | Move dffinit til after abc | Eddie Hung | 2019-04-05 | 3 | -2/+2 |
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| * | Merge branch 'eddie/fix_retime' into xc7srl | Eddie Hung | 2019-04-05 | 4 | -11/+12 |
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| | * | Move techamp t:$_DFF_?N? to before abc call | Eddie Hung | 2019-04-05 | 1 | -2/+2 |
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| | * | Retry | Eddie Hung | 2019-04-05 | 1 | -1/+1 |
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| | * | Resolve @daveshah1 comment, update synth_xilinx help | Eddie Hung | 2019-04-05 | 2 | -7/+9 |
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| | * | synth_xilinx to techmap FFs after abc call, otherwise -retime fails | Eddie Hung | 2019-04-05 | 1 | -3/+3 |
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| * | | techmap inside map_cells stage | Eddie Hung | 2019-04-05 | 2 | -2/+1 |
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| * | | Merge branch 'map_cells_before_map_luts' into xc7srl | Eddie Hung | 2019-04-04 | 1 | -0/+1 |
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| | * | | Missing techmap entry in help | Eddie Hung | 2019-04-04 | 1 | -0/+1 |
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| * | | | Use soft-logic, not LUT3 instantiation | Eddie Hung | 2019-04-04 | 1 | -4/+2 |
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| * | | | Merge branch 'map_cells_before_map_luts' into xc7srl | Eddie Hung | 2019-04-04 | 1 | -12/+12 |
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| | * | | synth_xilinx to map_cells before map_luts | Eddie Hung | 2019-04-04 | 1 | -12/+12 |
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| * | | Cleanup comments | Eddie Hung | 2019-04-04 | 1 | -5/+4 |
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| * | | t:$dff* -> t:$dff t:$dffe | Eddie Hung | 2019-04-04 | 1 | -2/+2 |
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| * | | -nosrl meant when -nobram | Eddie Hung | 2019-04-03 | 1 | -1/+1 |
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| * | | Remove duplicate STARTUPE2 | Eddie Hung | 2019-04-03 | 1 | -1/+0 |
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| * | | Disable shregmap in synth_xilinx if -retime | Eddie Hung | 2019-04-03 | 1 | -3/+3 |
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| * | | synth_xilinx to use shregmap with -minlen 3 | Eddie Hung | 2019-03-25 | 1 | -2/+2 |
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| * | | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-03-22 | 2 | -24/+31 |
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| | * | xilinx: Add keep attribute where appropriate | David Shah | 2019-03-22 | 2 | -25/+31 |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | Add '-nosrl' option to synth_xilinx | Eddie Hung | 2019-03-21 | 1 | -6/+16 |
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| * | | Fine tune cells_map.v | Eddie Hung | 2019-03-20 | 1 | -19/+15 |
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| * | | Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length | Eddie Hung | 2019-03-19 | 1 | -53/+20 |
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| * | | Add support for variable length Xilinx SRL > 128 | Eddie Hung | 2019-03-19 | 1 | -11/+67 |
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| * | | Restore original synth_xilinx commands | Eddie Hung | 2019-03-19 | 1 | -1/+2 |
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| * | | Fix spacing | Eddie Hung | 2019-03-19 | 1 | -1/+1 |
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| * | | Fix INIT for variable length SRs that have been bumped up one | Eddie Hung | 2019-03-19 | 1 | -1/+1 |
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| * | | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-03-19 | 1 | -2/+4 |
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| | * | Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873 | Clifford Wolf | 2019-03-19 | 1 | -2/+4 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Only accept <128 for variable length, only if $shiftx exclusive | Eddie Hung | 2019-03-16 | 1 | -5/+1 |
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| * | | Cleanup synth_xilinx | Eddie Hung | 2019-03-15 | 2 | -3/+2 |
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| * | | Working | Eddie Hung | 2019-03-15 | 2 | -47/+78 |
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| * | | Reverse bits in INIT parameter for Xilinx, since MSB is shifted first | Eddie Hung | 2019-03-14 | 1 | -16/+32 |
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| * | | Misspell | Eddie Hung | 2019-03-14 | 1 | -1/+1 |
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| * | | Revert "Add shregmap -init_msb_first and use in synth_xilinx" | Eddie Hung | 2019-03-14 | 1 | -3/+2 |
| | | | | | | | | | This reverts commit 26ecbc1aee1dca1c186ab2b51835d74f67bc3e75. | ||||
| * | | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-03-14 | 10 | -177/+571 |
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| | * | Merge pull request #842 from litghost/merge_upstream | Clifford Wolf | 2019-03-05 | 10 | -176/+570 |
| | |\ | | | | | | | Changes required for VPR place and route in synth_xilinx | ||||
| | | * | Revert BRAM WRITE_MODE changes. | Keith Rothman | 2019-03-04 | 1 | -12/+12 |
| | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| | | * | Revert FF models to include IS_x_INVERTED parameters. | Keith Rothman | 2019-03-01 | 1 | -6/+34 |
| | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| | | * | Use singular for disabling of DRAM or BRAM inference. | Keith Rothman | 2019-03-01 | 1 | -13/+13 |
| | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| | | * | Modify arguments to match existing style. | Keith Rothman | 2019-03-01 | 1 | -6/+6 |
| | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| | | * | Changes required for VPR place and route synth_xilinx. | Keith Rothman | 2019-03-01 | 11 | -221/+587 |
| | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| | * | | Use "write_edif -pvector bra" for Xilinx EDIF files | Clifford Wolf | 2019-03-05 | 1 | -1/+1 |
| | |/ | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Add shregmap -init_msb_first and use in synth_xilinx | Eddie Hung | 2019-03-14 | 1 | -2/+2 |
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| * | | Fix cells_map for SRL | Eddie Hung | 2019-03-14 | 1 | -19/+17 |
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| * | | Move shregmap until after first techmap | Eddie Hung | 2019-03-13 | 1 | -2/+2 |
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| * | | Refactor $__SHREG__ in cells_map.v | Eddie Hung | 2019-03-13 | 1 | -32/+24 |
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| * | | Remove SRL16/32 from cells_xtra | Eddie Hung | 2019-02-28 | 2 | -18/+2 |
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| * | | Add SRL16 and SRL32 sim models | Eddie Hung | 2019-02-28 | 1 | -0/+39 |
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index : iCE40/yosys | |
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