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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 13:11:30 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 13:11:30 -0700 |
| commit | 24553326dde876b51179e092e608ce8174a44681 (patch) | |
| tree | 29af5ce1fabcef3a105f45898b411ec4188bf97f /techlibs/xilinx | |
| parent | 0ea7eba5f13b20de28181a66181ee821820027db (diff) | |
| parent | 8c0740bcf7a1149ac11332f7e7fd9c8f78f0a0b5 (diff) | |
| download | yosys-24553326dde876b51179e092e608ce8174a44681.tar.gz yosys-24553326dde876b51179e092e608ce8174a44681.tar.bz2 yosys-24553326dde876b51179e092e608ce8174a44681.zip | |
Merge remote-tracking branch 'origin/master' into xc7srl
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 763732fe5..61895e032 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -122,7 +122,8 @@ struct SynthXilinxPass : public Pass log("\n"); log(" map_cells:\n"); log(" techmap -map +/xilinx/cells_map.v\n"); - log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT\n"); + log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT \\\n"); + log(" -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n"); log(" clean\n"); log("\n"); log(" check:\n"); @@ -278,7 +279,8 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_cells")) { Pass::call(design, "techmap -map +/xilinx/cells_map.v"); - Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT"); + Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " + "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); Pass::call(design, "clean"); } |