diff options
| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-28 13:56:22 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-28 13:56:22 -0800 |
| commit | 73ddab6960a02aef0c5f9ccee8cee2e666778c06 (patch) | |
| tree | 3bdc3d5b0c18f279645138475a89b2dff2f94b38 /techlibs/xilinx | |
| parent | 8aab7fe7e64b1c213d924126e30994ab7b6d4625 (diff) | |
| download | yosys-73ddab6960a02aef0c5f9ccee8cee2e666778c06.tar.gz yosys-73ddab6960a02aef0c5f9ccee8cee2e666778c06.tar.bz2 yosys-73ddab6960a02aef0c5f9ccee8cee2e666778c06.zip | |
Add SRL16 and SRL32 sim models
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index eba17ac9c..68f678385 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -186,3 +186,42 @@ module RAM128X1D ( wire clk = WCLK ^ IS_WCLK_INVERTED; always @(posedge clk) if (WE) mem[A] <= D; endmodule + +module SRL16E ( + output Q, + input A0, A1, A2, A3, CE, CLK, D +); + parameter [15:0] INIT = 16'h0000; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + + reg [15:0] r = INIT; + assign Q = r[{A3,A2,A1,A0}]; + generate + if (IS_CLK_INVERTED) begin + always @(negedge CLK) if (CE) r <= { r[14:0], D }; + end + else + always @(posedge CLK) if (CE) r <= { r[14:0], D }; + endgenerate +endmodule + +module SRLC32E ( + output Q, + output Q31, + input [4:0] A, + input CE, CLK, D +); + parameter [31:0] INIT = 32'h00000000; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + + reg [31:0] r = INIT; + assign Q31 = r[31]; + assign Q = r[A]; + generate + if (IS_CLK_INVERTED) begin + always @(negedge CLK) if (CE) r <= { r[30:0], D }; + end + else + always @(posedge CLK) if (CE) r <= { r[30:0], D }; + endgenerate +endmodule |