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* Update Xilinx cell definitions, fixes #3699Miodrag Milanovic2023-03-233-6/+16
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* Check DREG attributeOliver Keszöcze2023-02-171-1/+1
| | | The DSP48E1 implementation checked the wrong attribute (i.e. CREG) to initialize the D input register. This PR fixes 3680
* Fitting help messages to 80 character widthKrystalDelusion2022-08-241-3/+4
| | | | | | | | | Uses the regex below to search (using vscode): ^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\); Finds any log messages double indented (which help messages are) and checks if *either* there are is no newline character at the end, *or* the number of characters before the newline is more than 80.
* xilinx: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-1837-2269/+4525
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* xilinx: Add RAMB4* blackboxesMarcelina Kościelnicka2022-03-212-1/+695
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* iopadmap: Add native support for negative-polarity output enable.Marcelina Kościelnicka2021-11-092-10/+3
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* Fixes xc7 BRAM36sMaciej Dudek2021-07-301-4/+6
| | | | | | UG473 from Xilinx states that 15 bit should always be set if RAMB isn't in cascade mode. Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-089-9/+9
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* Fix use of blif name in synth_xilinx commandMichael Christensen2021-04-271-1/+1
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* Blackbox all whiteboxes after synthesisgatecat2021-03-171-0/+1
| | | | | | | This prevents issues like processes in whiteboxes triggering an error in the JSON backend. Signed-off-by: gatecat <gatecat@ds0.me>
* verilog: significant block scoping improvementsZachary Snow2021-01-311-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
* xilinx_dffopt: Don't crash on missing IS_*_INVERTED.Marcelina Kościelnicka2021-01-271-3/+3
| | | | | | | | The presence of IS_*_INVERTED on FD* cells follows Vivado, which apparently has been decided by a dice roll. Just assume false if the parameter doesn't exist. Fixes #2559.
* xilinx: Add FDRSE_1, FDCPE_1.Marcelina Kościelnicka2021-01-271-0/+80
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* xilinx: Add some missing blackbox cells.Marcelina Kościelnicka2020-12-213-798/+6276
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* xilinx: Regenerate cells_xtra.v using Vivado 2020.2Marcelina Kościelnicka2020-12-212-42/+49
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* xilinx: Add FDDRCPE and FDDRRSE blackbox cells.Marcelina Kościelnicka2020-12-172-0/+33
| | | | | These are necessary primitives for proper DDR support on Virtex 2 and Spartan 3.
* Move signal declarations to before first useJeff Goeders2020-10-191-2/+2
| | | | Signed-off-by: Jeff Goeders <jeff.goeders@gmail.com>
* xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)Eddie Hung2020-09-232-17/+65
| | | | | | | | | | | * xilinx: eliminate SCCs from DSP48E1 model * xilinx: add SCC test for DSP48E1 * Update techlibs/xilinx/cells_sim.v * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled
* Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-071-3/+1
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* opt_expr: Remove -clkinv option, make it the default.Marcelina Kościelnicka2020-07-311-1/+1
| | | | | Adds -noclkinv option just in case the old behavior was actually useful to someone.
* synth_xilinx: Use opt_dff.Marcelina Kościelnicka2020-07-301-17/+12
| | | | | | | | | The main part is converting xilinx_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway.
* Remove EXPLICIT_CARRY logic.Keith Rothman2020-07-233-150/+2
| | | | | | | The symbiflow-arch-defs tool chain no longer needs the EXPLICIT_CARRY within yosys itself. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* xilinx: Fix srl regression.Marcelina Kościelnicka2020-07-121-2/+2
| | | | | | | Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and $_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the point where xilinx_srl is called for non-abc9. Fix this by running ff_map.v first, resulting in FDRE cells, which are handled correctly.
* xilinx: Use dfflegalize.Marcelina Kościelnicka2020-07-096-484/+131
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* Update dff2dffe, dff2dffs, zinit to new FF types.Marcelina Kościelnicka2020-06-234-50/+50
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* Use C++11 final/override keywords.whitequark2020-06-182-7/+7
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* xilinx: tidy up cells_sim.v a littleEddie Hung2020-05-251-5/+7
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* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-194-0/+33
| | | | Fixes #2058.
* xilinx: gate specify/attributes from iverilogEddie Hung2020-05-141-1/+3
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* xilinx/ice40/ecp5: zinit requires selected wires, so select them allEddie Hung2020-05-141-2/+2
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* xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cellsEddie Hung2020-05-141-1/+19
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* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-146-761/+127
| | | | | Eliminate need for abc9_{,un}map.v in xilinx -prep_dff_{hier,unmap} -> -prep_hier
* synth_*: no need to explicitly read +/abc9_model.vEddie Hung2020-05-141-1/+1
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* abc9_ops: -prep_dff_map to error if async flop foundEddie Hung2020-05-141-4/+0
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* Uncomment negative setup times; clamp to zero for connectivityEddie Hung2020-05-141-13/+29
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* synth_xilinx: rename dff_mode -> dffEddie Hung2020-05-141-8/+10
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* abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxesEddie Hung2020-05-144-366/+5
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* synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpadEddie Hung2020-05-041-3/+5
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* xilinx: improve xilinx_dffopt messageEddie Hung2020-04-221-3/+6
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* Use default parameter value in getParamMarcelina Kościelnicka2020-04-211-3/+3
| | | | Fixes #1822.
* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-2/+1
| | | | | | This pass is a proper subset of opt_rmdff, which is called by opt, which is called by every synth flow in the coarse part. Thus, it never actually does anything and can be safely removed.
* Merge pull request #1648 from YosysHQ/eddie/cmp2lcuEddie Hung2020-04-031-2/+1
|\ | | | | "techmap -map +/cmp2lcu.v" for decomposing arithmetic compares to $lcu
| * synth_xilinx: techmap +/cmp2lut.v and +/cmp2lcu.v in 'coarse'Eddie Hung2020-04-031-2/+1
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* | kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-13/+13
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* xilinx: Mark IOBUFDS.IOB as external padMarcin Kościelnicki2020-03-202-1/+2
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* xilinx: consider DSP48E1.ADREGEddie Hung2020-03-044-5/+8
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* xilinx: cleanup DSP48E1 handling for abc9Eddie Hung2020-03-043-86/+125
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* xilinx: improve specify for DSP48E1Eddie Hung2020-03-041-32/+116
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* xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.vEddie Hung2020-03-042-5/+14
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* Remove RAMB{18,36}E1 from cells_xtra.pyEddie Hung2020-02-271-2/+2
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