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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-25 13:18:55 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-25 13:18:55 -0700 |
| commit | f9fb05cf6684d855ce2fc776a20cd5552a4ef4a8 (patch) | |
| tree | 1b815d45ffab4398972dcf890405c876d27edb62 /techlibs/xilinx | |
| parent | 6b90d3cf6cd433420ed46e0cc31fc71773f3117b (diff) | |
| download | yosys-f9fb05cf6684d855ce2fc776a20cd5552a4ef4a8.tar.gz yosys-f9fb05cf6684d855ce2fc776a20cd5552a4ef4a8.tar.bz2 yosys-f9fb05cf6684d855ce2fc776a20cd5552a4ef4a8.zip | |
synth_xilinx to use shregmap with -minlen 3
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 5237cc4c6..b6225a1a3 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -114,7 +114,7 @@ struct SynthXilinxPass : public Pass log(" dff2dffe\n"); log(" opt -full\n"); log(" simplemap t:$dff* (only without -nosrl)\n"); - log(" shregmap -tech xilinx (only without -nosrl)\n"); + log(" shregmap -tech xilinx -minlen 3 (only without -nosrl)\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n"); log(" opt -fast\n"); log("\n"); @@ -267,7 +267,7 @@ struct SynthXilinxPass : public Pass if (!nosrl) { Pass::call(design, "simplemap t:$dff*"); - Pass::call(design, "shregmap -tech xilinx"); + Pass::call(design, "shregmap -tech xilinx -minlen 3"); } if (vpr) { |