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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-03 08:28:07 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-03 08:28:07 -0700 |
| commit | 0e2d929cead2a32ae176a408da257ec5b8b79f47 (patch) | |
| tree | 606458d04967bdf77e84ce8294d49e09119cd5c8 /techlibs/xilinx | |
| parent | ff385a5ad0570cb56ae63d450e1dcba76ffaff7e (diff) | |
| download | yosys-0e2d929cead2a32ae176a408da257ec5b8b79f47.tar.gz yosys-0e2d929cead2a32ae176a408da257ec5b8b79f47.tar.bz2 yosys-0e2d929cead2a32ae176a408da257ec5b8b79f47.zip | |
-nosrl meant when -nobram
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index df30a22de..601a6811d 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -69,7 +69,7 @@ struct SynthXilinxPass : public Pass log(" -nodram\n"); log(" disable inference of distributed rams\n"); log("\n"); - log(" -nobram\n"); + log(" -nosrl\n"); log(" disable inference of shift registers\n"); log("\n"); log(" -run <from_label>:<to_label>\n"); |