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* Merge branch 'eddie/fix_retime' into xc7srlEddie Hung2019-04-054-11/+12
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| * Move techamp t:$_DFF_?N? to before abc callEddie Hung2019-04-051-2/+2
| * RetryEddie Hung2019-04-051-1/+1
| * Resolve @daveshah1 comment, update synth_xilinx helpEddie Hung2019-04-052-7/+9
| * synth_xilinx to techmap FFs after abc call, otherwise -retime failsEddie Hung2019-04-051-3/+3
* | techmap inside map_cells stageEddie Hung2019-04-052-2/+1
* | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-041-0/+1
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| * | Missing techmap entry in helpEddie Hung2019-04-041-0/+1
* | | Use soft-logic, not LUT3 instantiationEddie Hung2019-04-041-4/+2
* | | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-041-12/+12
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| * | synth_xilinx to map_cells before map_lutsEddie Hung2019-04-041-12/+12
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* | Cleanup commentsEddie Hung2019-04-041-5/+4
* | t:$dff* -> t:$dff t:$dffeEddie Hung2019-04-041-2/+2
* | -nosrl meant when -nobramEddie Hung2019-04-031-1/+1
* | Remove duplicate STARTUPE2Eddie Hung2019-04-031-1/+0
* | Disable shregmap in synth_xilinx if -retimeEddie Hung2019-04-031-3/+3
* | synth_xilinx to use shregmap with -minlen 3Eddie Hung2019-03-251-2/+2
* | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-222-24/+31
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| * xilinx: Add keep attribute where appropriateDavid Shah2019-03-222-25/+31
* | Add '-nosrl' option to synth_xilinxEddie Hung2019-03-211-6/+16
* | Fine tune cells_map.vEddie Hung2019-03-201-19/+15
* | Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable lengthEddie Hung2019-03-191-53/+20
* | Add support for variable length Xilinx SRL > 128Eddie Hung2019-03-191-11/+67
* | Restore original synth_xilinx commandsEddie Hung2019-03-191-1/+2
* | Fix spacingEddie Hung2019-03-191-1/+1
* | Fix INIT for variable length SRs that have been bumped up oneEddie Hung2019-03-191-1/+1
* | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-191-2/+4
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| * Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873Clifford Wolf2019-03-191-2/+4
* | Only accept <128 for variable length, only if $shiftx exclusiveEddie Hung2019-03-161-5/+1
* | Cleanup synth_xilinxEddie Hung2019-03-152-3/+2
* | WorkingEddie Hung2019-03-152-47/+78
* | Reverse bits in INIT parameter for Xilinx, since MSB is shifted firstEddie Hung2019-03-141-16/+32
* | MisspellEddie Hung2019-03-141-1/+1
* | Revert "Add shregmap -init_msb_first and use in synth_xilinx"Eddie Hung2019-03-141-3/+2
* | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-1410-177/+571
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| * Merge pull request #842 from litghost/merge_upstreamClifford Wolf2019-03-0510-176/+570
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| | * Revert BRAM WRITE_MODE changes.Keith Rothman2019-03-041-12/+12
| | * Revert FF models to include IS_x_INVERTED parameters.Keith Rothman2019-03-011-6/+34
| | * Use singular for disabling of DRAM or BRAM inference.Keith Rothman2019-03-011-13/+13
| | * Modify arguments to match existing style.Keith Rothman2019-03-011-6/+6
| | * Changes required for VPR place and route synth_xilinx.Keith Rothman2019-03-0111-221/+587
| * | Use "write_edif -pvector bra" for Xilinx EDIF filesClifford Wolf2019-03-051-1/+1
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* | Add shregmap -init_msb_first and use in synth_xilinxEddie Hung2019-03-141-2/+2
* | Fix cells_map for SRLEddie Hung2019-03-141-19/+17
* | Move shregmap until after first techmapEddie Hung2019-03-131-2/+2
* | Refactor $__SHREG__ in cells_map.vEddie Hung2019-03-131-32/+24
* | Remove SRL16/32 from cells_xtraEddie Hung2019-02-282-18/+2
* | Add SRL16 and SRL32 sim modelsEddie Hung2019-02-281-0/+39
* | Fix SRL16/32 techmap off-by-oneEddie Hung2019-02-281-18/+24
* | synth_xilinx to call shregmap with enable supportEddie Hung2019-02-282-24/+29
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