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* synth_*: call 'opt -fast' after 'techmap'Eddie Hung2020-02-051-0/+1
* Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwardsEddie Hung2020-01-271-1/+1
* Import tests from #1628Eddie Hung2020-01-271-2/+2
* xilinx/ice40/ecp5: undo permuting LUT masks in lut_mapEddie Hung2020-01-271-7/+6
* Merge pull request #1656 from YosysHQ/eddie/ice40_abc9_warningsEddie Hung2020-01-274-6/+10
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| * ice40: reduce ABC9 internal fanout warnings with a param for CI->I3Eddie Hung2020-01-244-6/+10
* | ice40: add SB_SPRAM256KA arrival timeEddie Hung2020-01-241-0/+1
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* Merge pull request #1602 from niklasnisbeth/ice40-init-vals-warningDavid Shah2020-01-181-2/+8
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| * ice40: Demote conflicting FF init values to a warningNiklas Nisbeth2019-12-311-2/+8
* | synth_ice40: call wreduce before mul2dspEddie Hung2020-01-171-1/+2
* | synth_ice40: -abc2 to always use `abc` even if `-abc9`Eddie Hung2020-01-121-10/+10
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-061-0/+2
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| * | Valid to have attribute starting with SB_CARRY.Miodrag Milanovic2020-01-041-0/+2
* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-021-2/+2
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| * | Update doc that "-retime" calls abc with "-dff -D 1"Eddie Hung2019-12-301-1/+1
| * | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-301-1/+1
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| * Revert "Optimise write_xaiger"Eddie Hung2019-12-201-5/+0
| * Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanupEddie Hung2019-12-191-0/+5
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| | * techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaigerEddie Hung2019-12-061-0/+5
* | | Cleanup ice40 boxesEddie Hung2019-12-313-30/+43
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* | ice40_opt to restore attributes/name when unwrappingEddie Hung2019-12-091-0/+15
* | Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4Eddie Hung2019-12-091-1/+1
* | ice40_wrapcarry to really preserve attributes via -unwrap optionEddie Hung2019-12-092-19/+1
* | $__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserveEddie Hung2019-12-031-1/+1
* | ice40_opt to ignore (* keep *) -ed cellsEddie Hung2019-12-031-0/+5
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* Merge pull request #1490 from YosysHQ/clifford/autonameClifford Wolf2019-11-141-0/+1
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| * Add "autoname" pass and use it in "synth_ice40"Clifford Wolf2019-11-131-0/+1
* | Merge pull request #1465 from YosysHQ/dave/ice40_timing_simClifford Wolf2019-11-141-14/+436
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| * ice40: Add post-pnr ICESTORM_RAM model and fix FFsDavid Shah2019-10-231-2/+340
| * ice40: Support for post-pnr timing simulationDavid Shah2019-10-231-12/+96
* | Merge pull request #1452 from nakengelhardt/fix_dsp_mem_regClifford Wolf2019-10-221-0/+1
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| * Call memory_dff before DSP mapping to reserve registers (fixes #1447)N. Engelhardt2019-10-171-0/+1
* | Makefile: don't assume python is called `python3`Sean Cross2019-10-191-1/+1
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* Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-0410-91/+90
* Panic over. Model was elsewhere. Re-arrange for consistencyEddie Hung2019-10-044-31/+3
* OopsEddie Hung2019-10-041-1/+1
* Ohmilord this wasn't added all this time!?!Eddie Hung2019-10-041-0/+29
* Re-orderEddie Hung2019-09-271-1/+1
* select onceEddie Hung2019-09-261-5/+7
* Stop trying to be too smart by prematurely optimisingEddie Hung2019-09-261-3/+5
* Only wreduce on t:$addEddie Hung2019-09-251-1/+1
* Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40Eddie Hung2019-09-201-2/+1
* Revert "Move mul2dsp before wreduce"Eddie Hung2019-09-201-4/+5
* Move mul2dsp before wreduceEddie Hung2019-09-201-5/+4
* Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2Eddie Hung2019-09-191-1/+3
* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-052-22/+175
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| * Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-303-3/+3
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| * | Comment out SB_MAC16 arrival time for now, need to handle all its modesEddie Hung2019-08-281-1/+1
| * | Add arrival for SB_MAC16.OEddie Hung2019-08-281-0/+1
| * | Add arrival times for UEddie Hung2019-08-281-0/+26