Add arrival times for U

1 files changed, 26 insertions, 0 deletions

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index f5fe800f7..116188acb 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -175,12 +175,14 @@ endmodule
 
 // Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
 //                 https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+//                 https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
 
 // Positive Edge SiliconBlue FF Cells
 
 module SB_DFF (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, D
 );
@@ -191,6 +193,7 @@ endmodule
 module SB_DFFE (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, D
 );
@@ -202,6 +205,7 @@ endmodule
 module SB_DFFSR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -215,6 +219,7 @@ endmodule
 module SB_DFFR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -228,6 +233,7 @@ endmodule
 module SB_DFFSS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -241,6 +247,7 @@ endmodule
 module SB_DFFS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -254,6 +261,7 @@ endmodule
 module SB_DFFESR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -269,6 +277,7 @@ endmodule
 module SB_DFFER (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -282,6 +291,7 @@ endmodule
 module SB_DFFESS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -297,6 +307,7 @@ endmodule
 module SB_DFFES (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -312,6 +323,7 @@ endmodule
 module SB_DFFN (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, D
 );
@@ -322,6 +334,7 @@ endmodule
 module SB_DFFNE (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, D
 );
@@ -333,6 +346,7 @@ endmodule
 module SB_DFFNSR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -346,6 +360,7 @@ endmodule
 module SB_DFFNR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -359,6 +374,7 @@ endmodule
 module SB_DFFNSS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -372,6 +388,7 @@ endmodule
 module SB_DFFNS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -385,6 +402,7 @@ endmodule
 module SB_DFFNESR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -400,6 +418,7 @@ endmodule
 module SB_DFFNER (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -413,6 +432,7 @@ endmodule
 module SB_DFFNESS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -428,6 +448,7 @@ endmodule
 module SB_DFFNES (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -443,6 +464,7 @@ endmodule
 module SB_RAM40_4K (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+	`ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -613,6 +635,7 @@ endmodule
 module SB_RAM40_4KNR (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+	`ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -680,6 +703,7 @@ endmodule
 module SB_RAM40_4KNW (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+	`ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -747,6 +771,7 @@ endmodule
 module SB_RAM40_4KNRNW (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+	`ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -818,6 +843,7 @@ module ICESTORM_LC (
 	output LO,
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output O,
 	output COUT
 );