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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-19 12:24:03 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-19 12:24:03 -0500 |
| commit | df626ee7abca3446225dac9179d7e7f380774b2c (patch) | |
| tree | 548ad4c0f8492421a1f06f7f659e1759a2d3c955 /techlibs/ice40 | |
| parent | d406f2ffd776e4f69c86a96db8e69a9aa8a1dc1c (diff) | |
| parent | 91467938c477c5c668f5ea1a38fef59e2b19db5c (diff) | |
| download | yosys-df626ee7abca3446225dac9179d7e7f380774b2c.tar.gz yosys-df626ee7abca3446225dac9179d7e7f380774b2c.tar.bz2 yosys-df626ee7abca3446225dac9179d7e7f380774b2c.zip | |
Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup
Optimise write_xaiger
Diffstat (limited to 'techlibs/ice40')
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index ed7a16c08..5073ba917 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -350,6 +350,11 @@ struct SynthIce40Pass : public ScriptPass } if (!noabc) { if (abc == "abc9") { + run("select -set abc9_boxes A:abc9_box_id A:whitebox=1"); + run("wbflip @abc9_boxes"); + run("techmap -autoproc @abc9_boxes"); + run("aigmap @abc9_boxes"); + run("wbflip @abc9_boxes"); run("read_verilog -icells -lib +/ice40/abc9_model.v"); int wire_delay; if (device_opt == "lp") |