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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-06 17:05:02 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-06 17:05:02 -0800 |
| commit | 98c9ea605b5cb2eb540ae5b804a18f8921f0bc46 (patch) | |
| tree | 60e4232c602402b618390ac232323ab45d607cbe /techlibs/ice40 | |
| parent | 7dece7955e9682dddec67eb99d4f99742e637a07 (diff) | |
| download | yosys-98c9ea605b5cb2eb540ae5b804a18f8921f0bc46.tar.gz yosys-98c9ea605b5cb2eb540ae5b804a18f8921f0bc46.tar.bz2 yosys-98c9ea605b5cb2eb540ae5b804a18f8921f0bc46.zip | |
techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger
Diffstat (limited to 'techlibs/ice40')
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 901194b06..2f0bdb130 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -350,6 +350,11 @@ struct SynthIce40Pass : public ScriptPass } if (!noabc) { if (abc == "abc9") { + run("select -set abc9_boxes A:abc9_box_id A:whitebox=1"); + run("wbflip @abc9_boxes"); + run("techmap -autoproc @abc9_boxes"); + run("aigmap @abc9_boxes"); + run("wbflip @abc9_boxes"); run("read_verilog -icells -lib +/ice40/abc9_model.v"); int wire_delay; if (device_opt == "lp") |