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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 14:02:13 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 14:02:13 -0800 |
| commit | e18aeda7ed3b3dbf4700e25c2bc745c93541b3b8 (patch) | |
| tree | f41b454d90ffdff2f08a625cf36932805f3ee8d8 /techlibs/ice40 | |
| parent | cfb0366a18b0f3cab254636fdf534a3de76af8d5 (diff) | |
| download | yosys-e18aeda7ed3b3dbf4700e25c2bc745c93541b3b8.tar.gz yosys-e18aeda7ed3b3dbf4700e25c2bc745c93541b3b8.tar.bz2 yosys-e18aeda7ed3b3dbf4700e25c2bc745c93541b3b8.zip | |
Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards
Just like Verilog...
Diffstat (limited to 'techlibs/ice40')
| -rw-r--r-- | techlibs/ice40/ice40_opt.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 940a11063..925ab31bb 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -140,7 +140,7 @@ static void run_ice40_opts(Module *module) log_id(module), log_id(cell), log_signal(replacement_output)); cell->type = "$lut"; auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3))); - cell->setPort("\\A", { get_bit_or_zero(cell->getPort("\\I0")), inbit[0], inbit[1], I3 }); + cell->setPort("\\A", { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort("\\I0")) }); cell->setPort("\\Y", cell->getPort("\\O")); cell->unsetPort("\\B"); cell->unsetPort("\\CI"); |